ATI AGP RV350 Schematics

5

<Core D

esign>

Title

4

3

2

1

Date:Schematic No.

AGP RV350 128M BGA VGA DVI VO

105-A034XX-20

REVISION HISTORY

D D

Sch
Rev

0 10/23/02 PRELIMINARY BASED ON "RV-350 REFERENCE (105-REF113-00A)"

1 01/10/03 Removed C168, C169, to make the MVREFS, MVREFD traces shorter (for better noise)

2 01/15/03 Added fix for MVDDQ leakage and R119, C163

C C

3 01/15/03 Added external strap for PKGTYPE

Date

REVISION DESCRIPTION

Added R91 pull-up to fix "cold boot" problem: some boards would perform like ID DISABLED without the R91, because of floating /CS pin on the ROM (serial output overrides the ID DISABLED strap).
Added J5/6 connection for auto detection of component video
Added R100, R101 for easier power measurement
Changed AGP connector to 4X/8X type

Added provision for 3.3V_BUS on the MVDDC power supply
PCB changed to rev C to fix component interference with daughtercards
Removed R9, R11
Added R102 pull down
Fixed connection QSA4, QSA5 on the ASIC side
Changed C106, C107 to though-hole, added C166, C167 surface mount, alternate
Added C74

Added pullups for ZV_LCDCNTL(3:0) and STEREOSYNC
Changed R123 to pull-up to MVDDC
Added R255 for VDDC enable
Added D122 alternative for cost reduction
Added R1007 for EMI
Removed R605, R606, R607, R608 to improve EMI

Monday, February 23, 2004

Rev

7

4 03/26/03 Allegro conversion based on the latest -00 revision

B B

5 05/27/03

6 07/30/03

7 09/23/03

A A

5

PCB changes only. No schematic changes from previous revision.
This is a pads version based on the -00 revision.

Changed thermal sence and fan control circuit
Changed temperature interrupt to AUXWIN aand added inverter
Added C165

Changed p/n for J5, ASSY3, REF2
Deleted ASSY6

4

3

2

1

5

4

3

2

1

MEMORY CHANNEL A

D D

BGA Memory 4Mx32

MEMORY TERMINATIONS A

MA[14..0]

CASA#

RASA#

WEA#

QSA[7..0]

CS0A#MDA[63..0]

DQMA[0..7]

CLKA01CKEA

CLKA01#

MB[14..0]

CASB#

QSB[7..0]

MDB[63..0] CS0B#

WEA/B#

RASB#

MEMORY CHANNEL B

BGA Memory 4Mx32

MEMORY TERMINATIONS B

DQMB[0..7]

CKEB/D CLKB01

CLKB01#

PRIMARY CRT

LOGIC

VGA
DB15
CONN

MEM A MEM B

DAC1

C C

R G B HSY VSY DDC1DATA DDC1CLK

DVI-I CONN

THERMAL

SENSOR

DPLUS DMINUS I2C_CLK I2C_DAT

TMDS

TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA

INTEGRATED TMDS
LOGIC

STRAPS

BIOS

HEATSINK/FAN

B B

POWER

REGULATION

VDDC VDDC_CT MVDDC MVDDQ VTT
PVDD TPVDD MPVDD
A2VDD Vref

ROMCS#

ROM

RV350

TVO

DDR DVO

VIP

DAC2

DVO, VID ports

Y/R C/G COMP/B H2SYNC

D
E

CRT2DDCDATA CRT2DDCCLK V2SYNC

TVOUT Filters

HDH

TVOUT
CONN

and/or VGA Slim
DB15 CONN

M

AGP/PCI

LCDDATA19

SEL

U
X

Secondary
CRT LOGIC

CBE3..0

GNT#

CLK

SBA[7..0]

AD_STB1#

CPUCLK

TRDY#

INTR

ST2..0

WBF#

AD_STB0

DEVSEL#

DBI_HI

SB_STB

AD_STB0#

RESET#

DBI_LO

SB_STB#

RBF#

<Core Design>

REFERENCE
DESIGN

THESE SCHEMATICS ARE
SUBJECT TO MODIFICATION
AND DESIGN IMPROVEMENTS.
PLEASE CONTACT ATI FIELD
APPLICATION ENGINEERING
BEFORE USING THE INFOR­MATION CONTAINED HEREIN.

3

RESTRICTION
NOTICE

THESE SCHEMATICS CONTAIN
INFORMATION W HICH IS PROPRIETARY
TO AND IS THE PROPERTY OF ATI, AND
MAY NOT BE USED, REPRODUCED OR
DISCLOSED IN ANY MANNER WITHOUT
EXPRESSED WRITTEN PERMISSION
FROM ATI.

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

B

2

Date: Sheet

105-A034XX-20

120Monday, February 23, 2004

1

of

7

AD31..0

IRDY#

FRAME#

+5V_BUS+3.3V_BUS

+12V_BUS

+VDDQ_BUS

A A

5

AGPREF

AD_STB1

AGP B US
4X/8X

4

PAR

REQ#

STOP#

8

7

6

5

4

3

2

1

4X/8X AGP BUS

GND_TPVSSGND_MPVSS

GND_A2VSSN

+12V_BUS +5V_BUS +3.3V_BUS

C10
100uF_16V

D D

C C

B B

C5
100uF_16V

AGP_INTR#[3]

AGP_GNT#[3]

AGP_MB_8X_DET#[3]

AGP_DBI_HI[3]

AGP_WBF#[3]

AGP_SBSTB#[3]

AGP_ADSTB1#[3]

AGP_FRAME#[3]

AGP_TRDY#[3]

AGP_STOP#[3]

AGP_PAR[3]

AGP_ADSTB0#[3]

C8
100uF_16V

+VDDQ_BUS

TYDET
AGP_GC_8X_DET#

AGP_RST#

R15 _0R
R16 _0R
R18 _0R

R1 0R

R5 _0R

R7 0R

R12 _0R

AGP_VREFGC

USE 47uF TANTALUM
CAPACITOR OR HIGHER

C2
47uF_16V_Tant

>=6.3V

+12V_BUS

+3.3V_BUS

+VDDQ_BUS

AGP_ST1

AGP_SBA1
AGP_SBA3

AGP_SBA5
AGP_SBA7

AGP_AD30
AGP_AD28

AGP_AD26
AGP_AD24

AGP_C/BE#3
AGP_AD22

AGP_AD20 AGP_AD19
AGP_AD18

AGP_AD16

AGP_PAR_R
AGP_AD15
AGP_AD13

AGP_AD11
AGP_AD9

AGP_C/BE#0

AGP_AD6
AGP_AD4

AGP_AD2
AGP_AD0

MAGP1

A1

12V

A2

TYPEDET#

A3

GC_DET#/RESERVED

A4

USB-

A5

GND

A6

INTA#

A7

RST#

A8

GNT#

A9

VCC3.3

A10

ST1

A11

MB_DET#/RESERVED

A12

DBI_HI/PIPE#

A13

GND#A13

A14

WBF#

A15

SBA1

A16

VCC3.3#A16

A17

SBA3

A18

SB_STB#

A19

GND#A19

A20

SBA5

A21

SBA7

A22

RESERVED

A23

GND#A23

A24

RESERVED#A24

A25

VCC3.3#A25

A26

AD30

A27

AD28

A28

VCC3.3#A28

A29

AD26

A30

AD24

A31

GND#A31

A32

AD_STB1#

A33

C/BE3#

A34

VDDQ1.5

A35

AD22

A36

AD20

A37

GND#A37

A38

AD18

A39

AD16

A40

VDDQ1.5#A40

A41

FRAME#

A42

KEY

A43

KEY#A43

A44

KEY#A44

A45

KEY#A45

A46

TRDY#

A47

STOP#

A48

PME#

A49

GND#A49

A50

PAR

A51

AD15

A52

VDDQ1.5#A52

A53

AD13

A54

AD11

A55

GND#A55

A56

AD9

A57

C/BE0#

A58

VDDQ1.5#A58

A59

AD_STB0#

A60

AD6

A61

GND#A61

A62

AD4

A63

AD2

A64

VDDQ1.5#A64

A65

AD0

A66

VREFGC

1.5V_AGP_BUS

OVRCNT#

5.0V#B3
GND#B5

VCC3.3#B9

GND#B13

DBI_LO/RESERVED

VCC3.3#B16

SB_STB

GND#B19

RESERVED#B22

GND#B23

3.3VAUX

VCC3.3#B25

VCC3.3#B28

GND#B31
AD_STB1

VDDQ1.5#B34

GND#B37

VDDQ1.5#B40

KEY#B42
KEY#B43
KEY#B44
KEY#B45
DEVSEL#

VDDQ1.5#B47

GND#B49

VDDQ1.5#B52

GND#B55

VDDQ1.5#B58

AD_STB0
GND#B61

VDDQ1.5#B64

VREFCG

USB+

INTB#

REQ#

RBF#

SBA0
SBA2

SBA4
SBA6

AD31
AD29

AD27
AD25

AD23
AD21

AD19
AD17

C/BE2#

IRDY#

PERR#
SERR#

C/BE1#

AD14
AD12

AD10

+3.3V_BUS

+5V_BUS

+VDDQ_BUS
B1
B2

5.0V

B3
B4
B5
B6
B7

CLK

B8
B9
B10

ST0

B11

ST2

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57

AD8

B58
B59
B60

AD7

B61
B62

AD5

B63

AD3

B64
B65

AD1

B66

AGP_ST0
AGP_ST2

AGP_SBA0
AGP_SBA2

AGP_SBA4
AGP_SBA6

AGP_AD31
AGP_AD29

AGP_AD27
AGP_AD25

AGP_AD23
AGP_AD21

AGP_AD17
AGP_C/BE#2

AGP_C/BE#1
AGP_AD14

AGP_AD12
AGP_AD10

AGP_AD8

AGP_AD7
AGP_AD5

AGP_AD3
AGP_AD1

AGP_C/BE#[3..0]
AGP_AD[31..0]
AGP_SBA[7..0]
AGP_ST[2..0]

AGP_AGPCLK_R

AGP_DBI_LO_R

AGP_SBSTB_R

AGP_ADSTB1_R

AGP_ADSTB0_R

AGP_AGPREF

AGP_C/BE#[3..0] [3]
AGP_AD[31..0] [3]
AGP_SBA[7..0] [3]
AGP_ST[2..0] [3]

R61 0R

R62 _0R

R2 0R

R6 _0R

R8 0R

R10 0R

R13 0R

C1
DNI_1.0uF

C4
DNI_10pF

AGP_AGPCLK [3]
AGP_REQ# [3]

AGP_RBF# [3]
AGP_DB I_LO [3]

AGP_SBSTB [3]

AGP_ADSTB1 [3]

AGP_IRDY# [3]

AGP_DEVSEL# [3]

AGP_ADSTB0 [3]

GND_PVSS GND_TXVSSR

NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE

GND_AVSSQ GND_RSET

GND_A2VSSQ

GND_R2SETGND_AVSSN

SYMBOL LEGEND

DNI

DO NOT
INSTALL

#

ACTIVE
LOW

DIGITAL
GROUND

ANALOG
GROUND

UNIVERSAL VREFCG CIRCUIT (4X, 8X)

<Core Design>

AGP_AGPREF

TEST

Q5

_2N7002E

+VDDQ_BUS

32

1

2

R66

R64

_324R_1%

DNI_0R

R67
_147R_1%

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title
Size Docum e n t N u mb er R ev

C

Date: Sheet

AGP_AGPREFCG

C7

R65

10nF

_100R_1%

*

AGP RV350 128M BGA VGA DVI VO

105-A034XX-20

AGP_AGPREFCG [3]

of

220Monday, February 23, 2004

1

7

TEST

+VDDQ_BUS+3.3V_BUS

32

1

Q1

2N7002E

R23
1K

R21
147R_1%

R20
324R_1%

R24

_100R_1%

3

AGP_VREFGC

C6
10nF

*

TYDET

AGP_GC_8X_DET#

A A

R19

2.2R

R60
_0R

For retail, 1K ohm
pull-down causes AMD
system detects
AGP2X only

+12V, TYPEDET#
short protection
for OEM (1KR)

+5V_BUS

C11

1.0uF

147

AGP_RST#

1

AGP_RESET#[3,14]

R4
180R

R3
100R

3

U6A
SN74ACT86D

2

AGP_MB_8X_DET#[3]

AGP_MB_8X_DET#

8X_DET#[3]

R17
47K

4
5

U6B

SN74ACT86D

6

UNIVERSAL VREFGC CIRCUIT (4X, 8X)

8

7

6

5

4

5

4

3

2

1

AGP_AD[31..0][2]

D D

*

AGP_C/BE#[3..0][2]

C C

AGP_SBA[7..0][2]

R46
_4.7K

AGP_ST[2..0][2]

AGP_AGPREFCG[2]

AGP_MB_8X_DET#[2]

A_R/C_DAC2[14,17]
A_G/Y_DAC2[14,17]

A_B/COMP_DAC2[14,17]

A_HSYNC_DAC2[16]
A_VSYNC_DAC2[16]

+VDDQ_BUS

R37

32

_47R
Q2
DNI_2N7002E

8X_DET#[2]

B B

1

R38
DNI_71.5R

+3.3V_BUS

R45
_4.7K

SCL[14,19]

SDA[14,19]

OPTION 1: Crystal Circuit

C71
DNI_22pF

+3.3V_BUS

C3
100nF

A A

C72
DNI_22pF

Y2

8

VDD

4

GND

27.000MHz

2 1

OUT

Y1
DNI_27_MHZ

5
1

E/D

+3.3V_BUS

R27
150R

R32
DNI_1M

R28
100R_1%

OPTION 2: Oscillator Circuit

5

AGP_AD[31..0]

AGP_C/BE#[3..0]

AGP_AGPCLK[2]

AGP_RESET#[2,14]

AGP_REQ#[2]
AGP_GNT#[2]

AGP_PAR[2]

AGP_STOP#[2]

AGP_DEVSEL#[2]

AGP_TRDY#[2]

AGP_IRDY#[2]

AGP_FRAME#[2]

AGP_INTR#[2]

AGP_WBF#[2]

AGP_RBF#[2]
AGP_ADSTB0[2]
AGP_ADSTB1[2]

AGP_SBSTB[2]

AGP_SBA[7..0]

AGP_ST[2..0]

AGP_SBSTB#[2]
AGP_ADSTB0#[2]
AGP_ADSTB1#[2]

AGP_DBI_LO[2]

AGP_DBI_HI[2]

R29
0R_0805

OSCILLATOR CAN BE
CONNECTED TO XTALIN
OR XTALOUT

When RV350_XTALOUT is
used by the oscillator, XTALIN
should be grounded to prevent
the input buffers from picking
up noise.

OPTIONAL SCAN PIN_PERMISSION

TP10

PLACE C83 CLOSE TO ASIC PIN

GND_R2SET

TP6

R14
0R

R33
0R

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_ST0
AGP_ST1
AGP_ST2

C83 1 00nF

R40 715R_1%

TESTEN

R41

R42

_0R

_0R

R36

4.7K

4

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

U1A

H29

AD0

Part 1 of 6

H28

AD1

J29

AD2

J28

AD3

K29

AD4

K28

AD5

L29

AD6

L28

AD7

N28

AD8

P29

AD9

P28

AD10

R29

AD11

R28

AD12

T29

AD13

T28

AD14

U29

AD15

N25

AD16

R26

AD17

P25

AD18

R27

AD19

R25

AD20

T25

AD21

T26

AD22

U25

AD23

V27

AD24

W26

AD25

W25

AD26

Y26

AD27

Y25

AD28

AA26

AD29

AA25

AD30

AA27

AD31

N29

C/BE#0

U28

C/BE#1

P26

C/BE#2

U26

C/BE#3

AG30

PCICLK

AG28

RST#

AF28

REQ#

AD26

GNT#

M25

PAR

N26

STOP#

V29

DEVSEL#

V28

TRDY#

W29

IRDY#

W28

FRAME#

AE26

INTA#

AC26

WBF#

AE29

RBF#

M28

AD_STBF_0

V25

AD_STBF_1

AB29

SB_STBF

AD28

SBA0

AD29

SBA1

AC28

SBA2

AC29

SBA3

AA28

SBA4

AA29

SBA5

Y28

SBA6

Y29

SBA7

AF29

ST0

AD27

ST1

AE28

ST2

AB28

SB_STBS

M29

ADSTBS_0

V26

ADSTBS_1

M26

AGPREF

M27

AGPTEST

AB26

DBI_LO

AB25

DBI_HI

AC25
AK21
AJ23

AJ22
AK22

AJ24
AK24

AG23
AG24

AK25
AJ25
AH28
AJ29
AH27

E8
B6

AE25
AG26

AH30
AH29
AG29

R30
0R

STEREOSYNC [17]

+3.3V_BUS

IT IS RECOMMENDED TO ALLOW SERIES RESISTOR
FOOT PRINTS ON THE INDICATED AGP CONTROL SIGNALS

TO ADDRESS ANY LAYOUT NOISE RELATED

AGP

AGP_DET#
R2SET
C_R_Pr

Y_G_Y
COMP_B_Pb

H2SYNC
V2SYNC

DDC3CLK
DDC3DATA

VSS
NC#AJ25
XTALIN
XTALOUT
TESTEN

TEST_YCLK
TEST_MCLK
PLLTEST

STEREOSYNC
NC
NC#AH29
RSTB_MSK

RV350

SIGNAL DAMPING REQUIREMENTS

PCI / AGPAGP2X

4X

8X

DAC2CLK

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16

DVOMODE

ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9

DVO / EXT TMDS / GPIOTMDSDAC1

ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23

ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3

VREFG

NC#AK16
NC#AH16
NC#AH17

NC#AJ16
NC#AH18

NC#AJ17

NC#AK19
NC#AH19

NC#AK18

NC#AJ18
NC#AG16

NC#AF16
NC#AG17

NC#AF17

NC#AF18

NC#AE18
NC#AH20
NC#AG20

NC#AF19
NC#AG19

NC#AE12
NC#AG12

TX0M
TX1M
TX2M

TXCM

TXCP

DDC2CLK

DDC2DATA

HPD1

HSYNC

VSYNC

RSET

DDC1DATA

DDC1CLK

AUXWIN

DPLUS

DMINUS

THERM

TX0P
TX1P
TX2P

AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2

AE10
AH6

AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

AG4

AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19

AE12
AG12

AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13

AE13
AE14

AF12
AK27

R

AJ27

G

AJ26

B

AG25
AH25

AH26
AF25

AF24
AF26

AF11
AE11

C74
100nF

R39 _499R_1%

AUXWIN

3

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16

DVOMODE
VID/DVO0

VID/DVO1
VID/DVO2
VID/DVO3
VID/DVO4
VID/DVO5
VID/DVO6
VID/DVO7
VID/DVO8
VID/DVO9
VID/DVO10
VID/DVO11
VID/DVO12
VID/DVO13
VID/DVO14
VID/DVO15
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23

LCDCNTL0
LCDCNTL1
LCDCNTL2
LCDCNTL3

R34
_1.00K_1%

TP11
TP12

D+ [19]
D- [19]

HPD_ExtTMDS [14]
Mem_Strap1 [15]
Mem_Strap0 [15]

DVOMODE [14,15]

+3.3V_BUS

R35
_1.00K_1%

Boundary scan test

A_HSYNC_DAC1
SCL
CRT1DDCDATA
CRT1DDCCLK
A_VSYNC_DAC1

TESTEN

GND_RSET

R63

_4.7K

GPIO[13..0]

+3.3V_BUS

GPIO[13..0] [9, 1 4 , 15]

PKGTYPE [15]
DC_Strap2 [14]
DC_Strap3 [14,17]
DC_Strap4 [14]
LCDDATA16 [15]
LCDDATA17 [15]
PAL/NTSC [14]
DEMUX_SEL [14,17]
VHAD0 [14,15]
VHAD1 [14]
VPHCTL [14]
CLK_VIPCLK [14]

LCDCNTL0 [14]
LCDCNTL1 [14]
LCDCNTL2 [14]
CLK_VID/DVO [14]

TMDS_TX0N [18]
TMDS_TX0P [18]
TMDS_TX1N [18]
TMDS_TX1P [18]
TMDS_TX2N [18]
TMDS_TX2P [18]
TMDS_TXCN [18 ]
TMDS_TXCP [18]

DVIDDCCLK [16]
DVIDDCDATA [16]

HPD [ 18]
A_R_DAC1 [16]

A_G_DAC1 [16]
A_B_DAC1 [16]

A_HSYNC_DAC1 [16]
A_VSYNC_DAC1 [16]

TP7

CRT1DDCDATA [16]
CRT1DDCCLK [16]

INT_ALERT [19]

GPIO7

GPIO10

VID/DVO[11..0]

TRST/
TDO
TDI

TMS

TCK

R31
_0R

VID/DVO[11..0] [14]

TP1
TP2
TP3
TP4
TP5

TP8

2

EXT_PWR [7]

DC_Strap1 [9,14]

<Core Design>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Docum e n t N u mb er R ev

Custom

Date: Sheet

105-A034XX-20

1

of

320Monday, February 23, 2004

7

1

2

3

4

5

6

7

8

QSA[7..0][10] QSB[7..0][11]

DQMA#[7..0][10]

MAA[13..0][10]

MDA[63..0][10]

A A

B B

C C

QSA[7..0]
DQMA#[7..0]
MAA[13..0]

MDA[63..0]

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DQMB#[7..0][11]

MAB[13..0][11]

MDB[63..0][11]

U1B

L25

DQA0

L26

DQA1

K25

DQA2

K26

DQA3

J26

DQA4

H25

DQA5

H26

DQA6

G26

DQA7

G30

DQA8

D29

DQA9

D28

DQA10

E28

DQA11

E29

DQA12

G29

DQA13

G28

DQA14

F28

DQA15

G25

DQA16

F26

DQA17

E26

DQA18

F25

DQA19

E24

DQA20

F23

DQA21

E23

DQA22

D22

DQA23

B29

DQA24

C29

DQA25

C25

DQA26

C27

DQA27

B28

DQA28

B25

DQA29

C26

DQA30

B26

DQA31

F17

DQA32

E17

DQA33

D16

DQA34

F16

DQA35

E15

DQA36

F14

DQA37

E14

DQA38

F13

DQA39

C17

DQA40

B18

DQA41

B17

DQA42

B15

DQA43

C13

DQA44

B14

DQA45

C14

DQA46

C16

DQA47

A13

DQA48

A12

DQA49

C12

DQA50

B12

DQA51

C10

DQA52

C9

DQA53

B9

DQA54

B10

DQA55

E13

DQA56

E12

DQA57

E10

DQA58

F12

DQA59

F11

DQA60

E9

DQA61

F9

DQA62

F8

DQA63

RV350

Part 2 of 6

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA0

QSA1

QSA2

QSA3

QSA4

QSA5

QSA6

QSA7
RASA#
CASA#

WEA#
CSA0#
CSA1#

CKEA

CLKA0

CLKA0#

CLKA1

CLKA1#

MEMORY INTERFACE A

MVREFD

MVREFS

DIMA_0
DIMA_1

MAA0

E22

MAA1

B22

MAA2

B23

MAA3

B24

MAA4

C23

MAA5

C22

MAA6

F22

MAA7

F21

MAA8

C21

MAA9

A24

MAA10

C24

MAA11

A25

MAA12

E21

MAA13

B20
C19

DQMA#0

J25

DQMA#1

F29

DQMA#2

E25

DQMA#3

A27

DQMA#4

F15

DQMA#5

C15

DQMA#6

C11

DQMA#7

E11

QSA0

J27

QSA1

F30

QSA2

F24

QSA3

B27

QSA4

E16

QSA5

B16

QSA6

B11

QSA7

F10

RASA#

A19

CASA#

E18

WEA#

E19

CSA#0

E20

CSA#1

F20

CKEA

B19

CLKA0

B21

CLKA#0

C20

CLKA1

C18

CLKA#1

A18

RASA# [10]
CASA# [10]
WEA# [10]
CSA#0 [10]
CSA#1 [10]
CKEA [10]

CLKA0 [10,12,13]
CLKA#0 [10,12,13]

CLKA1 [10,12,13]
CLKA#1 [10,12,13]

B7
B8

DIMA0

D30
B13

DIMA1

DIMA0 [12,13]
DIMA1 [12,13]

R57
_100R_1%

+MVDDQ

C151
_100nF

+MVDDQ

QSB[7..0]
DQMB#[7..0]
MAB[13..0]

MDB[63..0]

R56
_133R_1%

R58
_47R

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

U1C

D7

DQB0

F7

DQB1

E7

DQB2

G6

DQB3

G5

DQB4

F5

DQB5

E5

DQB6

C4

DQB7

B5

DQB8

C5

DQB9

A4

DQB10

B4

DQB11

C2

DQB12

D3

DQB13

D1

DQB14

D2

DQB15

G4

DQB16

H6

DQB17

H5

DQB18

J6

DQB19

K5

DQB20

K4

DQB21

L6

DQB22

L5

DQB23

G2

DQB24

F3

DQB25

H2

DQB26

E2

DQB27

F2

DQB28

J3

DQB29

F1

DQB30

H3

DQB31

U6

DQB32

U5

DQB33

U3

DQB34

V6

DQB35

W5

DQB36

W4

DQB37

Y6

DQB38

Y5

DQB39

U2

DQB40

V2

DQB41

V1

DQB42

V3

DQB43

W3

DQB44

Y2

DQB45

Y3

DQB46

AA2

DQB47

AA6

DQB48

AA5

DQB49

AB6

DQB50

AB5

DQB51

AD6

DQB52

AD5

DQB53

AE5

DQB54

AE4

DQB55

AB2

DQB56

AB3

DQB57

AC2

DQB58

AC3

DQB59

AD3

DQB60

AE1

DQB61

AE2

DQB62

AE3

DQB63

Part 3 of 6

RV350

MEMORY INTERFACE B

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8

MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7
RASB#
CASB#

WEB#
CSB0#
CSB1#

CKEB
CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB_0
DIMB_1

ROMCS#

MEMVMODE_0
MEMVMODE_1

MEMTEST

MAB0

N5

MAB1

M1

MAB2

M3

MAB3

L3

MAB4

L2

MAB5

M2

MAB6

M5

MAB7

P6

MAB8

N3

MAB9

K2

MAB10

K3

MAB11

J2

MAB12

P5

MAB13

P3
P2

DQMB#0

E6

DQMB#1

B2

DQMB#2

J5

DQMB#3

G3

DQMB#4

W6

DQMB#5

W2

DQMB#6

AC6

DQMB#7

AD2

QSB0

F6

QSB1

B3

QSB2

K6

QSB3

G1

QSB4

V5

QSB5

W1

QSB6

AC5

QSB7

AD1

RASB#

R2

CASB#

T5

WEB#

T6

CSB#0

R5

CSB#1

R6

CKEB

R3

CLKB0

N1

CLKB#0

N2

CLKB1

T2

CLKB#1

T3

DIMB0

E3

DIMB1

AA3

AF5
C6

C7
C8

R55
_47R

R53
DNI_4.7K

RASB# [11]
CASB# [11]
WEB# [11]
CSB#0 [11]
CSB#1 [11]
CKEB [11]
CLKB0 [11,12,13]

CLKB#0 [11,12,13]
CLKB1 [11,12,13]

CLKB#1 [11,12,13]

DIMB0 [12,13]
DIMB1 [12,13]

ROMCS# [9]

R51 4.7K
R52 4.7K

R54
DNI_4.7K

+VDDC_CT

C152

R59

100nF

MEMORY CHANNEL A

D D

1

2

3

_51R

4

MEMORY CHANNEL B

5

VDDR1 MEMVMODE_0 MEMVMODE_1

1.8V

2.5V

2.8V

<Core Design>

6

GND

+VDDC_CT GND

+VDDC_CT +VDDC_CT

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, On ta ri o
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Re v

Custom

Date: Sheet

7

+VDDC_CT

105-A034XX-20

7

of

420Wednesday, February 25, 2004

8

5

+MVDDQ

CP6A

D D

C C

B B

CP6B

_10nF

_10nF

8 1

7 2

+MVDDQ

C32

C33

1.0uF

1.0uF

CP6C
_10nF

6 3

C35

1.0uF

10uF_16V_TANT

C61

10uF_16V_TANT

GND_A2VSSN

10uF_16V_TANT

CP6D
_10nF

5 4

C57

+VDDR4

10uF_16V_TANT

+A2VDD

10uF_16V_TANT

GND_A2VSSQ

GND_PVSS

CP5A
_10nF

8 1

+MVDDQ

C39

10uf_1206

+TPVDD

B11
B200R_0805

C62

1.0uF
+A2VDDQ

C63

10uF_16V_TANT

+PVDD

C54

7 2

C38
10uf_1206

C43

1.0uF

C59

C67

GND_AVSSN

C53

1.0uF

CP5B
_10nF

C64

1.0uF
+AVDD

C58

1.0uF

GND_TPVSS

C60

1.0uF

CP5C
_10nF

6 3

C73
100pF

C81
100pF

GND_TXVSSR

+VDDR4

C68

1.0uF
B200R_0805

10uF_16V_TANT

+MPVDD

C52

10uF_16V_TANT

GND_MPVSS

CP5D
_10nF

5 4

+A2VDD

B10
B200R_0805

+MVDDQ

B12

C66

C51

1.0uF

C65

1.0uF

AE17
AE20
AE15
AF21

AK12
AF13

AF14

AG21
AH21

AF22
AH24

AE24
AE22

AK28

H10
H13
H15
H17

AA1
AA4
AA7
AA8

G10
G13
G15
G19
G22
G27
H22
H19
AD4

D19
D13

AJ20

F18

T7
R4
R1
N8
N7
M4

L27

L8

J24
J23

J8
J7
J4
J1

T8

V4

V7

V8

A3

A9

A15
A21
A28

B1

B30
D26
D23
D20
D17
D14
D11

D8
D5

E27

F4
G7

T4
N4

N6

A7

4

U1D

VDDR1#T7
VDDR1#R4
VDDR1#R1
VDDR1#N8
VDDR1#N7
VDDR1#M4
VDDR1#L27
VDDR1#L8
VDDR1#J24
VDDR1#J23
VDDR1#J8
VDDR1#J7
VDDR1#J4
VDDR1#J1
VDDR1#H10
VDDR1#H13
VDDR1#H15
VDDR1#H17
VDDR1#T8
VDDR1#V4
VDDR1#V7
VDDR1#V8
VDDR1#AA1
VDDR1#AA4
VDDR1#AA7
VDDR1#AA8
VDDR1#A3
VDDR1
VDDR1#A15
VDDR1#A21
VDDR1#A28
VDDR1#B1
VDDR1#B30
VDDR1#D26
VDDR1#D23
VDDR1#D20
VDDR1#D17
VDDR1#D14
VDDR1#D11
VDDR1#D8
VDDR1#D5
VDDR1#E27
VDDR1#F4
VDDR1#G7
VDDR1#G10
VDDR1#G13
VDDR1#G15
VDDR1#G19
VDDR1#G22
VDDR1#G27
VDDR1#H22
VDDR1#H19
VDDR1#AD4
VDDR1#T4
VDDR1#N4
VDDR1#D19
VDDR1#D13

A2VDD
VDDL1
VDDL0#AE15
VDDL0#AF21

VDDL0
TPVDD

TXVDDR
TXVDDR#AF14

VDDRH0
VDDRH1

A2VDD#AG21
A2VDD#AH21

A2VDDQ
AVDD

VDD1DI
VDD2DI

PVDD
MPVDD

RV350

Part 4 of 6

VDDC#AD13
VDDC#AD15
VDDC#AC15
VDDC#AC17

VDDC15#AC11
VDDC15#AC20

VDDC15#Y23

VDDC15#L23
VDDC15#H20
VDDC15#H11

VDDR3#AD19
VDDR3#AD21
VDDR3#AD22
VDDR3#AC22
VDDR3#AC21
VDDR3#AC19

VDDR3#AC8
VDDR4#AG7

VDDR4#AD9

VDDR4#AC10
VDDR4#AD10

VDDP#AE30
VDDP#AC27
VDDP#AC23
VDDP#AB30
VDDP#AA24
VDDP#AA23

I/O POWER

TXVSSR#AH12
TXVSSR#AG13

A2VSSN#AJ21

VDDC

VDDC15

VDDC15#Y8

VDDR3

VDDR4

VDDP#J30

VDDP#AF27

VDDP#Y27

VDDP#W30

VDDP#V23

VDDP#V24
VDDP#M23
VDDP#M24

VDDP
VDDP#P23
VDDP#P27
VDDP#T23
VDDP#T24
VDDP#T30
VDDP#U27

AVSSQ

VSS#AF20
VSS#AE19
VSS#AE16
VSS#AF15

TPVSS

TXVSSR

VSSRH0
VSSRH1

A2VSSN

A2VSSQ

AVSSN

VSS1DI
VSS2DI

PVSS

MPVSS

3

DIODE SUPPLIES POWER
TO VDDC RAIL
WHILE VDDC REGULATOR
STABALIZES DURING POWER ON

+3.3V_BUS

D30

2.4V_SOD123

2 1

C24

+3.3V_BUS

2 1

C70

10uF_16V_TANT

>= 6.3V

TP9

GND_AVSSQ

GND_TPVSS

GND_TXVSSR

GND_AVSSN

GND_PVSS

10uf_1206

D31

_2.4V_SOD123

+VDDC_CT

GND_A2VSSQ

AC13
AD13
AD15
AC15
AC17

P8
Y8
AC11
AC20
Y23
L23
H20
H11

AD7
AD19
AD21
AD22
AC22
AC21
AC19
AC8

AG7
AD9
AC9
AC10
AD10

J30
AF27
AE30
AC27
AC23
AB30
AA24
AA23
Y27
W30
V23
V24
M23
M24
N30
P23
P27
T23
T24
T30
U27

AD24
AF20

AE19
AE16
AF15

AJ19

VSS

AJ12
AH12

AG13
AG14

F19
M6

AH22
AJ21

AF23
AH23

AE23
AE21
AJ28
A6

GND_MPVSS

CP2A
_10nF

8 1

CP3A
_10nF

8 1

C46

C44

1.0uF

1.0uF

B53 B200R_0805

C69

1.0uF

C36

C37

1.0uF

1.0uF

GND_A2VSSN

+3.3V_BUS

8 1

7 2

7 2

CP9A
_10nF

CP2B
_10nF

CP3B
_10nF

6 3

+VDDR4+VDD_DVO

R68
DNI_0R

R69
_0R

CP9B
_10nF

7 2

CP2C
_10nF

CP3C
_10nF

6 3

+3.3V_BUS

6 3

+VDDC

CP9C
_10nF

CP8A

CP2D
_10nF

5 4

CP3D
_10nF

5 4

CP9D
_10nF

5 4

_10nF

8 1

CP4A
_10nF

8 1

1.0uF

+VDDC_CT

C49

1.0uF

+VDDQ_BUS

7 2

+VDDC

C26

CP8B
_10nF

7 2

CP4B
_10nF

1.0uF

C48

1.0uF

6 3

+VDDC

C27

CP8C
_10nF

5 4

CP4C
_10nF

6 3

C28

1.0uF

C47

1.0uF

CP8D
_10nF

2

+VDDC

U1F

P17

VDDC

Part 6 of 6

P18

VDDC#P18

P19

VDDC#P19

U12

VDDC#U12

U13

VDDC#U13

U14

VDDC#U14

U17

VDDC#U17

U18

VDDC#U18

U19

VDDC#U19

V19

VDDC#V19

V18

VDDC#V18

CENTER

V17

VDDC#V17

V14

VDDC#V14

ARRAY

V13

VDDC#V13

V12

VDDC#V12

N18

VDDC#N18

N17

VDDC#N17

N14

VDDC#N14

W17

VDDC#W17

W18

VDDC#W18

W12

VDDC#W12

W13

VDDC#W13

W14

VDDC#W14

N13

VDDC#N13

N19

VDDC#N19

M19

VDDC#M19

M18

VDDC#M18

M12

VDDC#M12

N12

VDDC#N12

M13

VDDC#M13

M14

VDDC#M14

P12

VDDC#P12

P13

VDDC#P13

P14

VDDC#P14

M17

VDDC#M17

W19

VDDC#W19

RV350

U1E

A2

VSS

A10

VSS#A10

A16

VSS#A16

A22

VSS#A22

A29

VSS#A29

C1

VSS#C1

C3

VSS#C3

C28

VSS#C28

C30

VSS#C30

D27

VSS#D27

D24

VSS#D24

D21

VSS#D21

D18

VSS#D18

D15

VSS#D15

D12

VSS#D12

E4

VSS#D9
VSS#D6
VSS#D4
VSS#F27
VSS#G9
VSS#G12
VSS#G16
VSS#G18
VSS#G21
VSS#G24
VSS#H27
VSS#H23
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12
VSS#H9
VSS#H8
VSS#H4
VSS#K30
VSS#K27
VSS#K24
VSS#K23
VSS#AG15
VSS#AD12
VSS#AE27
VSS#AG5
VSS#AG9
VSS#AG11
VSS#AG18
VSS#AG22
VSS#AG27
VSS#E4
VSS#AB4

RV350

CORE GND

D9
D6
D4

F27

G9
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12

H9

H8

H4
K30
K27
K24
K23

AG15
AD12
AE27

AG5

AG9
AG11
AG18
AG22
AG27

AB4

ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED

PLACED CLOSE TO THE POWER/GND PINS

WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC

5 4

1.0uF

CP4D
_10nF

C29

C45

1.0uF

VDDC1#M15
VDDC1#R19
VDDC1#T12

Part 5 of 6

VSS#D21
VSS#D18
VSS#D15
VSS#D12

VSS#D9
VSS#D6

VSS#D4
VSS#F27
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12

VSS#H9

VSS#H8

VSS#H4

VSS#K7

VSS#AE16
VSS#AF15
VSS#AF20
VSS#AE19

VSS#M7

VSS#N23

VDDC1

VSS

VSS#AE16
VSS#AF15
VSS#AF20
VSS#AE19

VSS#AA30
VSS#AB27
VSS#AB24
VSS#AB23

VSS#AC12
VSS#AC14
VSS#AD16
VSS#AC16
VSS#AC18
VSS#AD30
VSS#AD25
VSS#AD18

VSS#AK29

VSS#N23
VSS#N24
VSS#N27

VSS#R23
VSS#R24
VSS#R30
VSS#T27

VSS#U23
VSS#V30

VSS#W23
VSS#W24
VSS#W27

VSS#AB8
VSS#AB7
VSS#AB1
VSS#AC4

VSS#AK2

VSS#AJ30

VSS#AJ1
VSS#D10
VSS#D25

M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16

W16
M15
R19
T12

VSS#K8
VSS#K7

VSS#M7

VSS#P4
VSS#R7
VSS#R8

VSS#T1
VSS#U4
VSS#U8

VSS#W7
VSS#W8

VSS#Y4

K8
K7
K1
L4
M30
M8
M7
N23
N24
N27
P4
R7
R8
R23
R24
R30
T27
T1
U4
U8
U23
V30
W7
W8
W23
W24
W27
Y4
AA30
AB27
AB24
AB23
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD30
AD25
AD18
AK2
AK29
AJ30
AJ1
D10
D25

1

A A

<Core Design>

5

4

3

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Docum e n t N u mb er R ev

C

Date: Sheet

105-A034XX-20

1

of

520Monday, February 23, 2004

7

8

7

6

5

4

3

2

1

+3.3V_BUS

***

B21

C101
470uF_6.3V

Rc1

R253

_1.10K_1%

1%

Rc2

R256
_1.78K_1%

1%

60R_1806

Cout1

***

C106
1000uF_10V

***

Dual footprint Dual footprint

**

C108

22uF_16V_TANT

**

C166
DNI_470uF

+VDDC

**

DNI_22uF_16V

**

***

***

C109

C107
1000uF_10V

DNI_470uF

+VDDC

***

C97

***

C167
DNI_470uF

D D

+12V_BUS

+5V_BUS

BOOT_VDDC

C105

1.0uF

C C

+PW_V DDC
SS_VDDC
COMP_VDDC
Fb_VDDC

Alternative 2

B B

SS_VDDC

C100

220nF

COMP_VDDC

+3.3V_BUS

R255
_10K

R258 _51K
R259 _3K

R257
DNI_10K

C113
DNI_10nF

Alternative 1

U31

2

Vcc

6

8
7

4

1
2
3
4
5
6
7

HDrv

Vc

LDrv

SS
Comp

GND

DNI_IRU3037ACS
Alternate part IRU3037CS

MU31

RT
OCSET
SS
COMP
FB
EN
GND

_ISL6522CB

Fb

VCC

PVCC

LGATE

PGND

BOOT
UGATE
PHASE

5

3

1

14
13
12
11

BOOT_VDDC

10
9
8

ISL6522CB : SOIC
ISL6522CV : TSSOP

+12V_BUS

R251 _10R

+VDDC Switching Regulator

Q21

4 5
3
2
1

IRF7413A

Q22

4 5
3
2
1

IRF7413A

Fb_VDDC

+PW_V DDC

6
7
8

L63

1.5uH_9.0A

6
7
8

C110
1nf

Cc1

R254
_1.5K

Rc4

C102

1.0uF

Part

IRU3037

Regulator for VDDC (RV350 Core)
Vin = 3.3V_BUS
Vout = 1.2V

IRU3037A

ISL6522CB

Compensation options for
+VDDC regulator

Alt. Compensation 1

This compensation circuit is
simplified and will only work
with the IRU 3037(A ) Regulator

COMP_VDDC
C103
DNI_2.2nF

Cc4

R252
DNI_27K

Rc6

Alt. Compensation 2

This is re quired for the ISL6522CB
regulator, and provides maximum
regulation speed for IRU3037 Regultor

COMP_VDDC

C111

Cc3

Cc2

Cout1

33pF
C112
10nF

Fb_VDDC
R260
_15K

Rc5

470uF thru hole capacitor has 30mR ESR
where as 470uF SMT capacitor has
22mR ESR. For curre nt below 4.5A, 1
thru 470uF is enough.

INSTALL DO NOT INSTALL

Alternative1

Alternative2

Compens ation Circuit

Common, and Either Alt.
Compensation 1, or Alt.
Compensation 2

Common and Alt.
Compensation 2

Common

Note: Alternative
Compensation
Circuit 2 will only
work if Rc1 is a 1k
Ohm Resistor.
Alternative
Compensation
Circuit 1 has no
requirements for
the divider circuit.

Cc4, Rc6
Alternative 2

Alternative1

C104

4.7nf

SS_VDDC

Iout = 7A MAX (load consumption)
Iout = 3A MAX (Power rail consumption)

REG . VOLTAGE RESISTORS

Rc1

A A

ISL6522C

8

1.2V

1.25V

1.3V

1.00K (p/n 3240100100) 2K (p/n 3240200100)

1.10K (p/n 3240110100)

7

Rc2

1K78 (p/n 3240178100)1.00K (p/n 3240100100)
1K78 (p/n 3240178100)

<Core Design>

6

5

4

3

Indicates number of vias required for the connection

***

C166, C167 alternate parts for C106, C107
Place C102 capacitor very close to the Q21 pins

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 12 8M B GA VGA DVI VO

Size Document Number Rev

B

Date: Sheet

2

105-A034XX-20

of

620Monday, March 29, 2004

1

7

8

7

6

5

4

3

2

1

Layout Guide Lines for switching regulators

1) Feedback trace from the voltage divider resistors to the controller as short as possible.

2) Components with " ** " should have two vias on each pad

3) Components with " *** " should have three vias on each pad.

4) Connections indicated by bold thick line are high current path. Short, thick traces (at
least 30 mil) sh ould be used.

5) Place C94, C98, C99 close to Q3, Q4

6) C13, C14 are the alternate surface mount components for C55, C56

DNI_SHORTED

R77
_147R_1%

C86

2.2uF_0805

C88

0.22uF_0805

Cb4

R100

R78
_1.33K_1%

1%

Rb1

R87
_1K_1%

1%

Rb2

***

DNI DNI

C55

**

C13

***

DUAL
FOOTPRINT

1000uF_10V

DNI_470uF

Part

SC1175

IRU3047

***

DNI_470uF

***

DUAL
FOOTPRINT

1000uF_10V

C56

C14

INSTALL

Rb4, Rb6, Rb9, Rb10,

Cb4

Rb7, Rb8, Rb5, Cb1, Cb2

Db1, Db2

STUFFING O PTIO NS FO R E XTERNAL/INTERNA L POWER

+5VEXT +12V_BUS

B26 DO NO T S TU FF DO NO T ST UF F P/N 5050003200
B18

R101

DNI_SHORTED

R90
DNI_150R

C92
DNI_2.2uF

C95
DNI_0.22uF

C98, C99

C114, C123

B30, B31

P/N 5050003200 DO NOT ST UF F

B28

DO NOT STUFF
P/N 4240010500

C91

P/N 4264047700

C118

DO NOT STUFF

R111

P/N 3230000000

C140

P/N 4250022400
P/N 4273010600 DO NOT ST UF F

C124

P/N 4210022500 DO NOT ST UF F
P/N 5050003200 DO NOT ST UF F

JU2

P/N 6140011300 DO NOT ST UF F

Q10

P/N 2021390600

C96

P/N 4250010200
P/N 3230047200

R97

P/N 3230056200

R98

Part

MVDDC Rb2

2.8V

SC1175

Rb1

1K24 (p/n 3240124100)

2.9V

<Core Design>

3

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

B

Date: Sheet of

2

DO NOT INSTALL

Rb7, Rb8, Rb5, Cb1,
Cb2, Db2, Db1

Rb4, Rb6, Rb9, Rb10,

P/N 5050003200
P/N 4250022400
P/N 4260018700
P/N 4250010400
DO NOT STUFF
P/N 4251022400

DO NOT STUFF
DO NOT STUFF
DO NOT STUFF
DO NOT STUFF

1.00K (p/n 3240100100)

1.00K (p/n 3240100100)1K33 (p/n 3240133100)

105-A034XX-20

+MVDDC

Cb4

DO NOT STUFF

DO NOT STUFF
P/N 4240010500
P/N 4264047700

DO NOT STUFF
P/N 3230000000
P/N 4250022400

DO NOT STUFF

DO NOT STUFF

DO NOT STUFF

DO NOT STUFF

DO NOT STUFF

DO NOT STUFF

DO NOT STUFF

DO NOT STUFF

**

C84
22uF_16V_TANT

**

+3.3V_BUS

720Monday, March 29, 2004

7

1

C94

1.0uF

2

Q3B

_FDS6898A

4

R79
_10K

R85 _100R

+12V_BUS

B28

DNI_60R

C98
DNI_1.0uF

2

Q4A

DNI_FDS6898A

4

Q4B

R92 DNI_100R

+5V_BUS

***

71

53

+5VEXT

71

53

B16
60R_1806

PW

8

6

B18

PW1

C99
DNI_1.0uF

8

6

C76
470uF_6.3V

Q3A
_FDS6898A

L1 6.8uH_4.4A_DO3316

R76

_147R_1%
D26
_SK14

2 1

+3.3V_BUS

B26
DNI_60R

L2 DNI_6.8uH

R89
DNI_51.1R

D27
DNI_SK14

2 1

4

MEMORY CORE REGULATOR MVDDC

OPTION 1: Dual Phase Switching Regulator

+5V_BUS

D D

R72

2.2R_0805

R71

C739

C116
10nF

C89
10nF

DNI_470uF

R88

DNI_5.1R

5

_5.1R

DNI_60R

C91

DNI_FDS6898A

C737
DNI_6.8uF_25V

R93

R94

DNI_10K

DNI_100K

R95
DNI_75R

Rb9

R81 0R

C87

1uF_0805

C C

B B

A A

R83 0R

+5V_BUS

R98

DNI_5K6

R99

_10K

8

Rb10

Rb7

R74

DNI_33K

Cb1

C78

DNI_2.2nF

Q10

DNI_MMBT3906
23

1

C96
DNI_1nf

Rb8

R75
DNI_100K

Cb2

C79

DNI_150pF

EXTERNAL POWER DETECT

R97
DNI_4.7K

R102
DNI_1K

EXT_PWR [3]

C77 1nf

U43

1

VREF

2

+IN2

3

-IN2

4

VCC

5

CL2-

6

CL2+

7

BST2

8

DH2

9

DL2

10

PGND

_SC1175CSW

Alternate part IRU3047

+5VEXT

7

20

GND

PWRGD

-IN1

SS/ENA

CL1­CL1+
BST1

DH1

DL1

BSTC

DNI_HEADER_1X4_RA

JUb2

19
18
17
16
15
14
13
12
11

1uF_0805

1
2
3
4

JU2

C114

DNI_22uF_16V

C85
1nF_0805

R80 0R

R84 0R

C90

C140
_220nF

/25V

C117

DNI_10nF

DNI_22uF_16V

Rb5

Rb6

R73

1

2.2R_0805

3

D7
_BAT54SLT1

2

R111
_0R

+5VEXT +12VEXT

C123

DO NOT STUFF IF +5VEXT IS NOT USED

6

+12V_BUS

R96
DNI_10K

B30 DNI_60R

C124
DNI_2.2uF

B31

DNI_60R

R82

Rb4

0R

place close
to U43

C118
DNI_100nF

place close
to U43

C93
10nF

DNI_6.8uF_25V

8

7

6

5

4

3

2

1

+12V_BUS

+12V_BUS

1

Q27

+PW_VDD

SS_VDD

C129
_10nF

R122
_15K

C119
_220nF

2 3

DNI_1nf

C780
_220nF

C747

R121

_3K

C127

_22nf

DNI

COMP_VDD

C128
_33pF

C734
DNI_1uF

R119
DNI_10K

C163

DNI_10nF

C165

DNI_10uF_25V

DNI

D D

+MVDDC

R280
DNI_8K2

R281
DNI_2.4K

C C

+12V_BUS

1

Q28

DNI_CMPT3904

R282
DNI_20K

DNI_CMPT3904

2 3

Regulator f or +VDDR4

Vin = 3.3V
Vout = 1.8V
Iout =

+3.3V_BUS

+MVDDQ

R299

B B

R300
DNI_0R

_0R

C161
_1.0uF

+VDDR4

1.8V

REG22
_LT1117CST

IN3OUT

CASE

ADJ

1

R295
_681R_1%
1%

681R 1K5

2
4

MVDDQ Switching Regulator

1

D6

_BAT54SLT1

3

R112

2

_0R

U48

2

BOOT1

+12V_BUS

+VDDR4

R296R 295

R296
_1.5K
1%

SS_VDD

COMP_VDD
C126
DNI_2.2nF

R116
DNI_27K

+MVDDC

R120
_51K

R118
_10K

6

8
7

4

DNI_IRU3037ACS

Alternate part IRU3037CS

Alternative 1

U49
1
2
3
4
5
6
7

_ISL6522CB

C158
10uF_16V_TANT

Vcc
Vc

SS
Comp

GND

RT
OCSET
SS
COMP
FB
EN
GND

Alternative 2

B24
60R_1806

+12V_BUS

C121
_100nF

_STS8DNF3LL

DNI

HDrv

LDrv

Fb

VCC

PVCC

LGATE

PGND

BOOT
UGATE
PHASE

R113
_10R

5

3

C115
10nF

1

+12V_BUS

14
13
12
11

BOOT1

10
9
8

Regulator for +PVDD Regulator for +MPVDD Regulator for +A2VDD

Vin = 3.3V AGP
Vout = +1.8V
Iout = 25mA MAX

+3.3V_BUS

R284
_18R_1206

3 2

REG25
_AS432S

1

+PVDD

R954
_10K

R287
_681R_1%
1%

R290
_1.5K
1%

Q8A

2

4

+PW_VDD

71

8

53

6

_STS8DNF3LL

4

NC

1

NC

2

GND_PVSS

C745

C744

_220nF

_220nF

L5 3 .3uH_5A _DO 3316

Q8B

MRG25
DNI_SC431LC5SK -1
ALT

5 3

C120
470uF_16V

Cd1

C125
10nF

1.33K_1%
R114

Rd4

Rd1

R115

1.5K

R117
536R_1%

Rd2

Regulator f or +TPVDD

Vin = +3.3V AGP
Vout = 1.8V
Iout = 75mA MAX

+3.3V_BUS

R286
_18R_1206

REG27
_AS432S

3 2

Part

IRU3037

IRU3037A
ISL6522CB

**

**

C746
10uF_1210

**

** ***

1%

+MVDDC

R123

R125

_1K

_1.5K

1

Q6

_CMPT3904

R124
DNI_220R

+TPVDD

R289
_681R_1%
1%

1

R292
_1.5K
1%

MVDDC

+3.3V_BUS

2 3

4
1
2

2.8V

+MVDDQ

***

_NDS335N

NC
NC

GND_TPVSS

Rd1

1.33K 1%536R

C736
470uF_6.3V_LESR

+MVDDQ

32

Q7

1

R126
_1.5K

R127

_0_0805
C131
_220nF

MRG27
DNI_SC431LC5SK -1

5 3

Rd2

1%

+MVDDQ

Regulator fo r +V D DC_CT

Vin = 3.3V
Vout = 1.5V (MAX TBD)
Iout =

VDDC_CT

1.5V

C154 is Tantalum only if it has to be placed on the bottom side of the board

+VTT Linear Regulator

Vin = +MVDDQ
Vout = 1.25V

R128
DNI_0R

R129
DNI_47R

Iout = 2000mA MAX
Iout = 750mA Est. MAX

1.4V

Vin = 3.3V AGP
Vout = +1.8V
Iout = 10mA MAX

+3.3V_BUS

R285
47R_1206

REG26
_AS432S

1

3 2

+MPVDD

200R 1K

R273
1K

R288
_681R_1%
1%

R291
_1.5K
1%

DNI_100uF_6.3V

R294R293

R275
1K

4

NC

1

NC

2

5 3

GND_MPVSS

+MVDDQ

R297
DNI_0R

C155

C154

_22uF_16V_TANT

+MVDDQ

MRG26
DNI_SC431LC5SK -1

ALT

+3.3V_BUS

R298
_0R

R273

***

_1.00K_1%
C133
470uF_6.3V

***

R275

_1.00K_1%

Vin = +3.3V AGP
Vout = 2.5V
Iout = 150mA MAX

+3.3V_BUS

B71
B200R_0805

1

3

C139

1.0uF

+A2VDD and GND_A2VSSN routed
with at least 1 5 m il t race and not longer
than 1.5 inch.

C156
_1.0uF

REG24

VIN

SHDN

REG21
_LT1117CST

IN3OUT

ADJ

1

R293
_200R_1%
1%

REG20

1

IN

REFEN4GND

RT9173ACL5

C137
_1.0uF

BYPASS

GND

2.5V

2

GND_A2VSSN

CASE

3

VCNTL

VOUT

+VDDC_CT

2
4

R294

C157

_1.00K_1%

100uF_16V

1%

+3.3V_BUS

C130
47uF_6.3V

R274
1K

C138
DNI_470pF
DNI

+VTT

***

C134
1000uF_10V

***

6

5

VOUT

TAB

2

+A2VDD

5

4

A A

AVDD/A2VDDQ (1st DAC & 2nd DAC Band Gap)

COMMON

+AVDD +A2VDDQ+VDDR4

B29 B200R_0805

COMMON

7

B27 B200R_0805

8

<Core Design>

6

5

4

3

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Re v

Custom

Date: Sheet

2

105-A034XX-20

820Monday, March 29, 2004

of

1

7

8

D D

7

6

5

4

3

2

1

SERIAL EEPROM 512K/1M

+3.3V_BUS

R91
10K

RP193A33R_0402

GPIO8[3,15]

GPIO9[3,15]

C C

GPIO10[3 ,14]
ROMCS#[4]

81

RP193B33R_0402

72

RP193C33R_0402

63

RP193D33R_0402

54

ROM_SO

SI/A16
SCK/WEb
CSb

HOLD1

U11

5

D

6

C

1

S

7

+3.3V_BUS

HOLD

3

W

8

VCC

M25P05-VMN6T

C80

100nF

ALTERNATIVE PA RT :M25P05(512Kbit)

VSS

ROM_SO

2

Q

4

B B

<Core Design>

A A

8

7

6

5

4

3

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6

[phone]
Title
Size Document Number Rev

B

Date: Sheet

AGP RV350 128M BGA VGA DVI VO

105-A034XX-20

2

of

920Monday, February 23, 2004

1

7

5

TERMINATION FOR
MEMORY
CHANNEL A

PARALLEL TERMINATION

C751
_1.0uF

RESISTORS AND
DECOUPLING

D D

C C

B B

A A

SSTL_2 CLASS I

PLACE AT NETS MID
POINT

PARALLEL TERMINATION COULD BE
OMITTED UNDER SOME CIRCUMSTANCE.
PLEASE CONSULT WITH ATI FOR
DETAIL.

M_RASA#[12,13]
M_CKEA[ 1 2,13]

M_CASA#[12,13]

M_WEA#[12,13]
M_CSA#0[12]
M_CSA#1[12,13]

M_CLKA0[4,12,13]
M_CLKA#0[ 4 ,12,13]
M_CLKA1[4,12,13]
M_CLKA#1[ 4 ,12,13]

5

M_RASA#
M_CKEA
M_CASA#
M_WEA#
M_CSA#0
M_CSA#1

M_CLKA0
M_CLKA#0
M_CLKA1
M_CLKA#1

C752
_1.0uF

C753

1.0uF

C754
_1.0uF

C755
_1.0uF

C756
_1.0uF

C757
_1.0uF

C758
_1.0uF

C759
_1.0uF

C760
_1.0uF

C761
_1.0uF

C762
_1.0uF

C763
_1.0uF

CLKA0 [4,12,13]
CLKA#0 [4,12,13]
CLKA1 [4,12,13]
CLKA#1 [4,12,13]

4

+VTT+MVDDQ

RP101D 56R

5 4

RP101C 56R

6 3

RP101B 56R

7 2

RP101A 56R

C764
_1.0uF

C765
_1.0uF

C766
_1.0uF

C767

1.0uF

C768
_1.0uF

C769
_1.0uF

C770

1.0uF

C771
_1.0uF

C772
_1.0uF

C773

1.0uF

C774
_1.0uF

C775
_1.0uF

C776

1.0uF

8 1

RP102D 56R

5 4

RP102C 56R

6 3

RP102B 56R

7 2

RP102A 56R

8 1
RP103D _56R
RP103C _56R
RP103B _56R
RP103A _56R
RP104D _56R
RP104C _56R
RP104B _56R
RP104A _56R
RP105D 56R

5 4
RP105C 56R

6 3
RP105B 56R

7 2
RP105A 56R

8 1
RP106D 56R

5 4
RP106C 56R

6 3
RP106B 56R

7 2
RP106A 56R

8 1
RP107D _56R
RP107C _56R
RP107B _56R
RP107A _56R
RP108D _56R
RP108C _56R
RP108B _56R
RP108A _56R
RP110C _56R
RP110D _56R
RP110A _56R
RP110B _56R
RP109C _56R
RP109D _56R
RP109A _56R
RP109B _56R
RP112C 56R

6 3
RP112D 56R

5 4
RP112A 56R

8 1
RP112B 56R

7 2
RP111C 56R

6 3
RP111D 56R

5 4
RP111A 56R

8 1
RP111B 56R

7 2
RP113A 56R
RP113B 56R
RP113C 56R
RP113D 56R
RP114A 56R
RP114B 56R
RP114C 56R
RP114D 56R
RP115D _56R
RP115C _56R
RP115B _56R
RP115A _56R
RP116A _56R

8 1
RP116B _56R

7 2
RP116C _56R

6 3
RP116D _56R

5 4

R751 121R_1%
R752 121R_1% R760 22R
R753 121R_1%
R754 _121R_1%
R756 _121R_1%
R755 121R_1%
R757 121R_1%
R758 _121R_1%

R767 56R
R768 56R
R769 56R
R770 _56R
R772 _56R
R771 56R
R773 56R
R774 _56R

RP133A 56R
RP133B 56R
RP133C 56R
RP133D 56R
RP134A 56R
RP134B 56R
RP134C 56R
RP134D 56R
RP135A 56R
RP135B 56R
RP136D _56R
RP136C _56R
RP136B _56R
RP136A _56R
RP135C 56R

RP141B _56R

7 2
RP141C _56R

6 3
RP141D _56R

5 4
RP141A _56R

8 1
RP135D 56R

C777
10uF_16V_TANT
>= 6.3V

4

MDA[63..0]

MDA[63..0][4]

MDA0
MDA1

MDA3
MDA4
MDA5
MDA6
MDA7
MDA8

54

MDA9

63

MDA10

72

MDA11

81

MDA12

54

MDA13

63

MDA14

72

MDA15

81

MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24

54

MDA25

63

MDA26

72

MDA27 MDA27

81

MDA28

54

MDA29 MDA29

63

MDA30

72

MDA31

81

MDA32

63

MDA33

54

MDA34

81

MDA35

72

MDA36

63

MDA37

54

MDA38

81

MDA39

72

MDA40
MDA42

MDA43
MDA44
MDA45
MDA46
MDA47
MDA48

81

MDA49

72

MDA50

63

MDA51

54

MDA52

81

MDA53 M_MDA53

72

MDA54

63

MDA55

54

MDA56

54

MDA57

63

MDA58

72

MDA59

81

MDA60
MDA61
MDA62
MDA63

QSA[7..0]

QSA[7..0][4]

QSA0
QSA1
QSA2 QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

M_DQMA#[7..0][12,13]

M_MAA[13..0][12,13]

M_DQMA#[7..0]

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_MAA[13..0]

M_MAA0

81

M_MAA1

72

M_MAA2

63

M_MAA3

54

M_MAA4

81

M_MAA5

72

M_MAA6

63

M_MAA7

54

M_MAA8

81

M_MAA9

72

M_MAA10

54

M_MAA11

63

M_MAA12

72

M_MAA13

81
63

M_RASA#
M_CASA#
M_WEA#
M_CSA#0
M_CSA#1

54

MDA0
MDA1
MDA2MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26

MDA28
MDA30

MDA31
MDA32
MDA33
MDA34 M_MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

QSA0
QSA1

QSA3
QSA4
QSA5
QSA6
QSA7

M_DQMA#0
M_DQMA#1
M_DQMA#2

M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13

M_CKEA

RP117D 22R
RP117C 22R
RP117B 22R
RP117A 22R
RP118D 22R
RP118C 22R
RP118B 22R
RP118A 22R
RP119D _22R
RP119C _22R
RP119B _22R
RP119A _22R
RP120A _22R
RP120B _22R
RP120C _22R
RP120D _22R
RP121D 22R
RP121C 22R
RP121B 22R
RP121A 22R
RP122D 22R
RP122C 22R
RP122B 22R
RP122A 22R
RP123A _22R
RP123B _22R
RP123C _22R
RP123D _22R
RP124D _22R
RP124C _22R
RP124B _22R
RP124A _22R
RP127C _22R
RP127D _22R
RP127A _22R
RP127B _22R
RP128B _22R
RP128A _22R
RP128D _22R
RP128C _22R
RP125C 22R
RP125D 22R
RP125A 22R
RP125B 22R
RP126C 22R
RP126D 22R
RP126A 22R
RP126B 22R
RP129D 22R
RP129C 22R
RP129B 22R
RP129A 22R
RP130D 22R
RP130C 22R
RP130B 22R
RP130A 22R
RP131A _22R
RP131B _22R
RP131C _22R
RP131D _22R
RP132D _22R
RP132C _22R
RP132B _22R
RP132A _22R

R759 22R
R761 22R

R762 22R
R764 22R
R763 22R
R765 22R
R766 22R

R775 0R
R776 0R
R777 0R
R778 _0R
R780 _0R
R779 0R
R781 0R
R782 _0R

RP137A 0R
RP137B 0R
RP137C 0R
RP137D 0R
RP138A 0R
RP138B 0R
RP138C 0R
RP138D 0R
RP139A 0R
RP139B 0R
RP140A _0R
RP140B _0R
RP140C _0R
RP140D _0R

RP142B _0R
RP142C _0R
RP142D _0R
RP142A _0R
RP139D 0R

RP139C 0R

R893
10K

5 4
6 3
7 2
8 1

5 4
6 3
7 2
8 1
6 3
5 4
8 1
7 2

5 4
6 3
7 2
8 1

8 1
7 2
6 3
5 4

7 2
6 3
5 4
8 1

3

M_MDA[63..0]

M_MDA0

54

M_MDA1

63

M_MDA2

72

M_MDA3

81

M_MDA4

54

M_MDA5

63

M_MDA6

72

M_MDA7

81

M_MDA8
M_MDA9
M_MDA10
M_MDA11
M_MDA12

81

M_MDA13

72

M_MDA14

63

M_MDA15

54

M_MDA16

54

M_MDA17

63

M_MDA18

72

M_MDA19

81

M_MDA20

54

M_MDA21

63

M_MDA22

72

M_MDA23

81

M_MDA24

81

M_MDA25

72

M_MDA26

63

M_MDA27

54

M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32
M_MDA33

M_MDA35
M_MDA36

72

M_MDA37

81

M_MDA38

54

M_MDA39

63

M_MDA40

63

M_MDA41

54

M_MDA42

81

M_MDA43

72

M_MDA44

63

M_MDA45

54

M_MDA46

81

M_MDA47

72

M_MDA48

54

M_MDA49

63

M_MDA50

72

M_MDA51

81

M_MDA52

54
63

M_MDA54

72

M_MDA55

81

M_MDA56

81

M_MDA57

72

M_MDA58

63

M_MDA59

54

M_MDA60
M_MDA61
M_MDA62
M_MDA63

81
72
63
54
81
72
63
54
81
72

54
63

3

SERIES Resistors

For Bi-Directional signals,
Series resistors should be
placed close to the memory

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7

DQMA#0
DQMA#1
DQMA#2
DQMA#3M_DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MAA0M_MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

RASA# [4]
CASA# [4]
WEA# [4]
CSA#0 [4]
CSA#1 [4]

CKEA [4]

For Uni-Directional
signals, Series
resistors should be
placed close to the
ASIC

M_QSA[7..0]

DQMA#[7..0]

MAA[13..0]

M_MDA[63..0] [12,13]

M_QSA[7..0] [12,13]

DQMA#[7..0] [4]

MAA[13..0] [4]

2

1

CLOCK
terminations

Change from 1:1 spacing to at least a

2.5:1 spacing between the pair

These resis to r s and caps m ust be placed to minimize any stubs. These
must also be placed after the memory

M_CLKA0

R797
56R

C778
10nF_0805

R798

M_CLKA#0

M_CLKA1

M_CLKA#1

<Core Design>

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

Custom

Date: Sheet

56R

R799
56R

C779

10nF_0805
R800
56R

105-A034XX-20

1

7

of

10 20Monday, February 23, 2004

5

TERMINATION FOR
MEMORY
CHANNEL B

PARALLEL TERMINATION

+MVDDQ +VTT

C851

1.0uF

RESISTORS AND
DECOUPLING

D D

C C

B B

A A

SSTL_2 CLASS I

PLACE AT NETS MID
POINT

PARALLEL TER MINA TION COUL D BE
OMITTED UNDER SOME CIRCUMSTANCE.
PLEASE CONSULT WITH ATI FOR DETAIL.

M_RASB#[12,13]
M_CKEB[12,13]
M_CASB#[12,13]
M_WEB#[12,13]
M_CSB#0[12]
M_CSB#1[12,13]

M_CLKB0[4,12,13]

M_CLKB#0[ 4 ,12,13]

M_CLKB1[4,12,13]
M_CLKB#1[ 4 ,1 2,13]

5

M_RASB#
M_CKEB
M_CASB#
M_WEB#
M_CSB#0
M_CSB#1

M_CLKB0
M_CLKB#0
M_CLKB1
M_CLKB#1

C852
_1.0uF

C853
_1.0uF

C854

1.0uF

C855
_1.0uF

C856
_1.0uF

C857
_1.0uF

C858

1.0uF

C859

1.0uF

C860

1.0uF

C861
_1.0uF

C862

1.0uF

C863

1.0uF

CLKB0 [4,12,13]
CLKB#0 [4,12,13]
CLKB1 [4,12,13]
CLKB#1 [4,12,13]

RP151A _56R
RP151B _56R
RP151C _56R

C864

RP151D _56R

_1.0uF

RP152A _56R
RP152B _56R
RP152C _56R
RP152D _56R
RP153A 56R
RP153B 56R
RP153C 56R

C865

RP153D 56R

1.0uF

RP154A 56R
RP154B 56R
RP154C 56R
RP154D 56R
RP155A _56R
RP155B _56R
RP155C _56R

C866

RP155D _56R

_1.0uF

RP156A _56R
RP156B _56R
RP156C _56R
RP156D _56R
RP157A 56R
RP157B 56R
RP157C
RP157D

C867

RP158A 56R

_1.0uF

RP158B 56R
RP158C 56R
RP158D 56R
RP159D 56R
RP159C 56R
RP159B 56R
RP159A 56R

C868

RP160D 56R

_1.0uF

RP160C 56R
RP160B 56R
RP160A 56R
RP161D _56R
RP161C _56R
RP161B _56R
RP161A _56R

C869
_1.0uF

RP162D _56R
RP162C _56R
RP162B _56R
RP162A _56R
RP163D 56R
RP163C 56R
RP163B 56R
RP163A 56R

C870

1.0uF

RP164D 56R
RP164C 56R
RP164B 56R
RP164A 56R
RP165D _56R
RP165C _56R
RP165B _56R

C871

RP165A _56R

_1.0uF

RP166D _56R
RP166C _56R
RP166B _56R
RP166A _56R

R867 _56R
R868 56R

C872

R869 _56R

1.0uF

R870 56R
R871 56R
R872 _56R
R873 56R
R874 _56R

C873

1.0uF
RP183A 56R

RP183B 56R
RP183C 56R
RP183D 56R
RP184A 56R
RP184B 56R
RP184C 56R
RP184D 56R
RP185A 56R

C874

RP185B 56R

1.0uF

RP186A _56R
RP186B _56R
RP186C _56R
RP186D _56R
RP185C 56R

RP191B _56R

C875

RP191C _56R
RP191D _56R

1.0uF
RP191A _56R
RP185D 56R

C876
_1.0uF

C877
10uF_16V_TANT
>= 6.3V

4

MDB[63..0][4]

8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4

81
72
63
54
81
72
63

54
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4

81

72

56R

63

56R

54

81

72

63

54
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1

54

63

72

81

54

63

72

81
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1

54

63

72

81

54

63

72

81

QSB[7..0][4]

R851 _121R_1%
R852 121R_1%
R853 _121R_1%
R854 121R_1%
R855 121R_1%
R856 _121R_1%
R857 121R_1%
R858 _121R_1%

M_DQMB#[7..0][12,13]

M_MAB[13..0][12,13]

81

72

63

54

81

72

63

54

81

72
8 1
7 2
6 3
5 4

63

7 2
6 3
5 4
8 1

54

4

MDB[63..0]

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

QSB0
QSB1

QSB3
QSB4
QSB5
QSB6
QSB7

M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13

M_RASB#
M_CASB#
M_WEB#
M_CSB#0
M_CSB#1

QSB[7..0]

M_DQMB#[7..0]

M_MAB[13..0]

3

8 1
7 2
6 3
5 4

8 1
7 2
6 3
5 4

5 4
6 3
7 2
8 1

5 4
6 3
7 2
8 1

7 2
6 3
5 4
8 1

M_MDB0

81

M_MDB1

72

M_MDB2

63

M_MDB3

54

M_MDB4

81

M_MDB5

72

M_MDB6

63

M_MDB7

54

M_MDB8

54

M_MDB9

63

M_MDB10

72

M_MDB11

81

M_MDB12
M_MDB13
M_MDB14

M_MDB16

81

M_MDB17

72

M_MDB18

63

M_MDB19

54

M_MDB20

81

M_MDB21

72

M_MDB22

63

M_MDB23

54

M_MDB24
M_MDB25
M_MDB26
M_MDB27
M_MDB28

54

M_MDB29

63

M_MDB30

72

M_MDB31

81

M_MDB32

54

M_MDB33

63

M_MDB34

72

M_MDB35

81

M_MDB36

54

M_MDB37

63

M_MDB38

72

M_MDB39

81

M_MDB40

81

M_MDB41

72

M_MDB42

63

M_MDB43

54

M_MDB44
M_MDB45
M_MDB46
M_MDB47
M_MDB48

54

M_MDB49

63

M_MDB50

72

M_MDB51

81

M_MDB52

54

M_MDB53

63

M_MDB54

72

M_MDB55

81

M_MDB56
M_MDB57
M_MDB58
M_MDB59
M_MDB60

81

M_MDB61

72

M_MDB62

63

M_MDB63

54

81
72
63
54
81
72
63
54
81
72
54
63
72
81

54
63

3

MDB0

RP167A _22R

MDB1

RP167B _22R

MDB2

RP167C _22R

MDB3

RP167D _22R

MDB4

RP168A _22R

MDB5

RP168B _22R

MDB6

RP168C _22R

MDB7

RP168D _22R

MDB8

RP169D 22R

MDB9

RP169C 22R

MDB10

RP169B 22R

MDB11

RP169A 22R

MDB12

RP170A 22R

MDB13

RP170B 22R

MDB14

RP170C 22R

MDB15 M_MDB15

RP170D 22R

MDB16

RP171A _22R

MDB17

RP171B _22R

MDB18

RP171C _22R

MDB19

RP171D _22R

MDB20

RP172A _22R

MDB21

RP172B _22R

MDB22

RP172C _22R

MDB23

RP172D _22R

MDB24

RP173A 22R

MDB25

RP173B 22R

MDB26

RP173C 22R

MDB27

RP173D 22R

MDB28

RP174D 22R

MDB29

RP174C 22R

MDB30

RP174B 22R

MDB31

RP174A 22R

MDB32

RP175D 22R

MDB33

RP175C 22R

MDB34

RP175B 22R

MDB35

RP175A 22R

MDB36

RP176D 22R

MDB37

RP176C 22R

MDB38

RP176B 22R

MDB39

RP176A 22R

MDB40

RP177A _22R

MDB41

RP177B _22R

MDB42

RP177C _22R

MDB43

RP177D _22R

MDB44

RP178D _22R

MDB45

RP178C _22R

MDB46

RP178B _22R

MDB47

RP178A _22R

MDB48

RP179D 22R

MDB49

RP179C 22R

MDB50

RP179B 22R

MDB51

RP179A 22R

MDB52

RP180D 22R

MDB53

RP180C 22R

MDB54

RP180B 22R

MDB55

RP180A 22R

MDB56

RP181D _22R

MDB57

RP181C _22R

MDB58

RP181B _22R

MDB59

RP181A _22R

MDB60

RP182A _22R

MDB61

RP182B _22R

MDB62

RP182C _22R

MDB63

RP182D _22R

QSB0

R859 22R

QSB1

R860 22R

QSB2QSB2

R861 22R

QSB3

R862 22R

QSB4

R863 22R

QSB5

R864 22R

QSB6

R865 22R

QSB7

R866 22R

M_DQMB#0

R875 _0R

M_DQMB#1

R876 0R

M_DQMB#2

R877 _0R

M_DQMB#3

R878 0R

M_DQMB#4

R879 0R

M_DQMB#5

R880 _0R

M_DQMB#6

R881 0R

M_DQMB#7

R882 _0R

M_MAB0

RP187A 0R

M_MAB1

RP187B 0R

M_MAB2

RP187C 0R

M_MAB3

RP187D 0R

M_MAB4

RP188A 0R

M_MAB5

RP188B 0R

M_MAB6

RP188C 0R

M_MAB7

RP188D 0R

M_MAB8

RP189A 0R

M_MAB9

RP189B 0R

M_MAB10

RP190D _0R

M_MAB11

RP190C _0R

M_MAB12

RP190B _0R

M_MAB13

RP190A _0R

RP192B _0R
RP192C _0R
RP192D _0R
RP192A _0R
RP189D 0R

M_CKEB

RP189C 0R

R895
10K

M_MDB[63..0]

SERIES Resistors

For Bi-Directional signals,
Series resistors should be
placed close to the
memory

M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

RASB# [4]
CASB# [4]
WEB# [4]
CSB#0 [4]
CSB#1 [4]

CKEB [4]

M_MDB[63..0] [12,13]

M_QSB[7..0]

DQMB#[7..0]

MAB[13..0]

For Uni-Directional
signals, Series
resistors should be
placed close to the
ASIC

MAB[13..0] [4]

M_QSB[7..0] [12,13]

DQMB#[7..0] [4]

2

1

CLOCK
terminations

Change from 1:1 spacing to at least a

2.5:1 spacing between the pair

These resis to r s and caps m ust be placed to minimize any stubs. These
must also be placed after the memory

M_CLKB0

R897
56R

C878
10nF_0805

R898

M_CLKB#0

M_CLKB1

M_CLKB#1

<Core Design>

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

C

Date: Sheet

56R

R899
_56R

C879

_10nF_0805
R900
_56R

105-A034XX-20

1

7

of

11 20Monday, February 23, 2004

8

7

6

5

4

3

2

1

rank 1

M_DQMB#[7..0][11,13]

M_DQMA#[7..0][10,13]

D D

M_QSA[7..0][10,13]

M_QSB[7..0][11,13]

C C

M_MAA[13..0][10,13]

M_MAB[13..0][11,13]

B B

M_DQMB#[7..0]

M_DQMA#[7..0]

M_QSA[7..0]

M_QSB[7..0]

M_CLKA#0[ 4 ,1 0,13]
M_CLKA#1[ 4 ,1 0,13]
M_CLKB#0[ 4 ,1 1,13]

M_CLKB#1[ 4 ,1 1,13]

M_CKEA[ 1 0,13]

M_WEA#[10,13]
M_CASA#[10,13]
M_RASA#[10,13]

M_CSA#0[10]
M_CLKA0[4,10,13]
M_CLKA1[4,10,13]

M_CKEB[ 1 1,13]

M_WEB#[11,13]
M_CASB#[11,13]
M_RASB#[11,13]

M_CSB#0[11]
M_CLKB0[4,11,13]
M_CLKB1[4,11,13]

M_MAA[13..0]

M_MAB[13..0]

M_CSA#1[10,13]

M_CSB#1[11,13]

M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6

DIMA0[4,13] DIMA1[4,13] DIMB0[4,13] DIMB1[4,13]

M_QSA7
M_QSB0

M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6

+VREF_U66

M_QSB7

M_CLKA#0
M_CLKA#1
M_CLKB#0
M_CLKB#1

M_CKEA
M_WEA#
M_CASA#0
M_RASA#0
M_CSA#0 M_WEA#
M_CLKA0
M_CLKA1

M_CKEB
M_WEB#
M_CASB#0
M_RASB#0 M_DQMB#4
M_CSB#0
M_CLKB0
M_CLKB1

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13

M_MDA[63..0][10,13]
M_MDB[63..0][11,13]

M_CSA#1
M_CSB#1

M_CLKA#0
M_CSA#0
M_RASA#0
M_CASA#0

M_DQMA#2
M_DQMA#1
M_DQMA#3
M_DQMA#0

M_CKEA

U66

M_MAA12

M3

BA0

M_MAA13

L4

BA1

M_MAA11

L6

A11

M_MAA10

K5

A10

M_MAA9

L7

A9

M_MAA8

M10

A8/AP

M_MAA7

M9

A7

M_MAA6

M8

A6

M_MAA5

L8

A5

M_MAA4

M7

A4

M_MAA3

M6

A3

M_MAA2

L5

A2

M_MAA1

M5

A1

M_MAA0

M4

A0

B3

NC

B10

NC#B10

G3

NC#G3

G10

NC#G10

K11

NC#K11

K12

NC#K12

L2

M2

L12
M12

L11

M1

A11

G11

L10
M11

A12

G12

L3

L9
K8

L1
K1
K2

G2

A2

G1

A1

E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8

NC#L2
NC#L3
NC#M2

MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE

DQS3
DQS2
DQS1
DQS0

TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8

1Mx32x4

VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B11

VDDQ#D2

VDDQ#D11

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ#A10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4

VSSQ#F9
VSSQ#G4
VSSQ#G9

VSSQ#H4

VSSQ#H9

VSSQ#J4

VSSQ#J9

VSS#D6
VSS#D7
VSS#D9

VSS#K4
VSS#K9

M_CSA#1 M_CSA#1 M_CSB#1 M_CSB#1

M_QSA2
M_QSA1
M_QSA3
M_QSA0

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ

VSSQ

VSS#J5
VSS#J6
VSS#J7
VSS#J8

M_MDA16

A7

M_MDA17

B8

M_MDA18

A8

M_MDA19

A9

M_MDA20

B12

M_MDA21

C11

M_MDA22

C12

M_MDA23

D12

M_MDA8

J2

M_MDA9

J1

M_MDA10

H1

M_MDA11

H2

M_MDA12

F1

M_MDA13

F2

M_MDA14

E1

M_MDA15

E2

M_MDA24

E11

M_MDA25

E12

M_MDA26

F11

M_MDA27

F12

M_MDA28

H11

M_MDA29

H12

M_MDA30

J11

DQ9

M_MDA31

J12

DQ8

M_MDA0

D1

DQ7

M_MDA1

C1

DQ6

M_MDA2

C2

DQ5

M_MDA3

B1

DQ4

M_MDA4

A4

DQ3

M_MDA5

A5

DQ2

M_MDA6

B5

DQ1

M_MDA7

A6

DQ0

B2
B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4

VSS

D6
D7
D9
J5
J6
J7
J8
K4
K9

+MVDDC

C201
_1.0uF

_1.0uF

C202

C203

1.0uF

C204

1.0uF

+MVDDQ

C208

1.0uF

C209

1.0uF

C210
_1.0uF

C207
_1.0uF

64MBytes DDR 128Mbit 1Mx32x4 uBGA Elpida Memory Support

U67

M_MAA12

M3

BA0

M_MAA13

L4

BA1

M_MAA11

L6

A11

M_MAA10

K5

A10

M_MAA9

L7

A9

M_MAA8

M10

A8/AP

M_MAA7

M9

A7

M_MAA6

M8

A6

M_MAA5

L8

A5

M_MAA4

M7

A4

M_MAA3

M6

A3

M_MAA2

L5

A2

M_MAA1

M5

A1

M_MAA0

M4

A0

B3

NC

B10

NC#B10

G3

NC#G3

G10

NC#G10

K11

NC#K11

K12

NC#K12

L2

NC#L2

L3

NC#L3

M2

NC#M2

L12

M_WEA#

M_QSA6
M_QSA4
M_QSA7
M_QSA5

M12

L11

A11

G11

L10
M11

A12

G12

L9
K8

M1

L1
K1
K2

G2

A2

G1

A1

E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8

MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE

DQS3
DQS2
DQS1
DQS0

TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8

1Mx32x4

VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B11

VDDQ#D2

VDDQ#D11

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ#A10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9

VSSQ#J4
VSSQ#J9

VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9

+VREF_U67

+MVDDQ

+MVDDC +MVDDC

M_CLKA#1
M_CSA#0
M_RASA#0
M_CASA#0

M_DQMA#6
M_DQMA#4
M_DQMA#7
M_DQMA#5
M_CLKA1
M_CKEA

+MVDDC

C206

C205
_1.0uF

_1.0uF

C221
_1.0uF

C222
_1.0uF

C223

1.0uF

+MVDDQ

C211
_1.0uF

C212
_1.0uF

C227
_1.0uF

C228
_1.0uF

C229

1.0uF

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ

VSSQ

M_MDA48

A7

M_MDA49

B8

M_MDA50

A8

M_MDA51

A9

M_MDA52

B12

M_MDA53

C11

M_MDA54

C12

M_MDA55

D12

M_MDA33

J2

M_MDA32

J1

M_MDA35

H1

M_MDA34

H2

M_MDA37

F1

M_MDA36

F2

M_MDA39

E1

M_MDA38

E2

M_MDA56

E11

M_MDA57

E12

M_MDA58

F11

M_MDA59

F12

M_MDA60

H11

M_MDA61

H12

M_MDA62

J11

DQ9

M_MDA63

J12

DQ8

M_MDA41

D1

DQ7

M_MDA40

C1

DQ6

M_MDA43

C2

DQ5

M_MDA42

B1

DQ4

M_MDA45

A4

DQ3

M_MDA44

A5

DQ2

M_MDA47

B5

DQ1

M_MDA46

A6

DQ0

B2
B4

+MVDDQ +MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4

VSS

D6
D7
D9
J5
J6
J7
J8
K4
K9

C224

C225

_1.0uF

_1.0uF

C230

C231

1.0uF

_1.0uF

C226

1.0uF

C232
_1.0uF

+VREF_U68

M_MAB12
M_MAB13

M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0

M_CLKB#0
M_CSB#0
M_RASB#0
M_CASB#0
M_WEB#
M_DQMB#3
M_DQMB#0
M_DQMB#2
M_DQMB#1
M_CLKB0M_CLKA0

M_CKEB

M_QSB3
M_QSB0
M_QSB2
M_QSB1

M10

G10
K11
K12

M12

G11

M11

G12

+MVDDC

+MVDDQ

M3
L4

L6
K5
L7

M9
M8
L8
M7
M6
L5
M5
M4

B3

B10

G3

L2
L3
M2

L12

L9
K8

L11

M1
L1
K1
K2

A11

G2

A2

L10

A12

G1

A1

E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8

C241
_1.0uF

C247

1.0uF

U68

BA0
BA1

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

NC
NC#B10
NC#G3
NC#G10
NC#K11
NC#K12
NC#L2
NC#L3
NC#M2

MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE

DQS3
DQS2
DQS1
DQS0

TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8

1Mx32x4

C242
_1.0uF

C248

1.0uF

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B11

VDDQ#D2

VDDQ#D11

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ

VSSQ#A10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4

VSSQ#F9
VSSQ#G4
VSSQ#G9

VSSQ#H4

VSSQ#H9

VSSQ#J4
VSSQ#J9

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

C243

1.0uF

C249
_1.0uF

M_MDB24

A7

M_MDB25

B8

M_MDB26

A8

M_MDB27

A9

M_MDB28

B12

M_MDB29

C11

M_MDB30

C12

M_MDB31

D12

M_MDB0

J2

M_MDB1

J1

M_MDB2

H1

M_MDB3

H2

M_MDB4

F1

M_MDB5

F2

M_MDB6

E1

M_MDB7

E2

M_MDB16

E11

M_MDB17

E12

M_MDB18

F11

M_MDB19

F12

M_MDB20

H11

M_MDB21

H12

M_MDB22

J11

DQ9

M_MDB23

J12

DQ8

M_MDB8

D1

DQ7

M_MDB9

C1

DQ6

M_MDB10

C2

DQ5

M_MDB11

B1

DQ4

M_MDB12

A4

DQ3

M_MDB13

A5

DQ2

M_MDB14

B5

DQ1

M_MDB15

A6

DQ0

B2
B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

VSS

+MVDDC +MVDDC

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

C245

C244

_1.0uF

1.0uF

C251

C250

1.0uF

_1.0uF

+VREF_U69

C246

1.0uF

C252

1.0uF

M_MAB12
M_MAB13

M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0

M_CLKB#1
M_CSB#0
M_RASB#0
M_CASB#0
M_WEB#
M_DQMB#6
M_DQMB#5
M_DQMB#7

M_CLKB1
M_CKEB

M_QSB6
M_QSB5
M_QSB7
M_QSB4

M10

B10
G10

K11
K12

M12

A11

G11

M11

A12

G12

+MVDDC

+MVDDQ

M3

L4
L6

K5
L7

M9
M8

L8
M7
M6

L5
M5
M4

B3
G3

L2

L3
M2

L12

L9

K8

L11

M1

L1

K1

K2

G2

A2

L10

G1

A1

E5

E6

E7

E8

F5

F6

F7

F8
G5
G6
G7
G8
H5
H6
H7
H8

C261
_1.0uF

C267

1.0uF

U69

BA0
BA1

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

NC
NC#B10
NC#G3
NC#G10
NC#K11
NC#K12
NC#L2
NC#L3
NC#M2

MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE

DQS3
DQS2
DQS1
DQS0

TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8

1Mx32x4

C262
_1.0uF

C268

1.0uF

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B11

VDDQ#D2

VDDQ#D11

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ

VSSQ#A10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4

VSSQ#F9
VSSQ#G4
VSSQ#G9

VSSQ#H4

VSSQ#H9

VSSQ#J4

VSSQ#J9

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

C263
_1.0uF

C269

1.0uF

M_MDB48

A7

M_MDB49

B8

M_MDB50

A8

M_MDB51

A9

M_MDB52

B12

M_MDB53

C11

M_MDB54

C12

M_MDB55

D12

M_MDB40

J2

M_MDB41

J1

M_MDB42

H1

M_MDB43

H2

M_MDB44

F1

M_MDB45

F2

M_MDB46

E1

M_MDB47

E2

M_MDB56

E11

M_MDB57

E12

M_MDB58

F11

M_MDB59

F12

M_MDB60

H11

M_MDB61

H12

M_MDB62

J11

DQ9

M_MDB63

J12

DQ8

M_MDB32

D1

DQ7

M_MDB33

C1

DQ6

M_MDB34

C2

DQ5

M_MDB35

B1

DQ4

M_MDB36

A4

DQ3

M_MDB37

A5

DQ2

M_MDB38

B5

DQ1

M_MDB39

A6

DQ0

B2
B4

+MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4

VSS

D6
D7
D9
J5
J6
J7
J8
K4
K9

C264

C265

_1.0uF

_1.0uF

C270

C271

1.0uF

1.0uF

C266
_1.0uF

C272

1.0uF

C213

1.0uF

C214

1.0uF

C233

1.0uF

C234

1.0uF

C253

1.0uF

C254

1.0uF

C273

1.0uF

C274

1.0uF

+MVDDQ

+MVDDQ

+MVDDQ

+MVDDQ

R805

4.99K_1%

+VREF_U66

R806

4.99K_1%

R807

4.99K_1%

+VREF_U67

R808

4.99K_1%

R905

4.99K_1%

+VREF_U68

R906

4.99K_1%

R907

4.99K_1%

+VREF_U69

R908

4.99K_1%

+MVDDC

C215
22uF_16V_TANT
>= 6.3V

+MVDDC

C235
22uF_16V_TANT
>= 6.3V

+MVDDC

C255
22uF_16V_TANT
>= 6.3V

+MVDDC

C275

_22uF_16V_TANT

>= 6.3V

A A

<Core Design>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

Custom

8

7

6

5

4

3

Date: Sheet

2

105-A034XX-20

7

of

12 20Monday, February 23, 2004

1

8

7

6

5

4

3

2

1

rank 2

M_DQMB#[7..0][11,12]

M_DQMA#[7..0][10,12]

D D

M_QSA[7..0][10,12]

M_QSB[7..0][11,12]

C C

M_MAA[13..0][10,12]

M_MAB[13..0][11,12]

B B

M_DQMB#[7..0]

M_DQMA#[7..0]

M_QSA[7..0]

M_QSB[7..0]

M_CLKA#0[ 4 ,10,12]
M_CLKA#1[ 4 ,10,12]
M_CLKB#0[ 4 ,11,12]

M_CLKB#1[ 4 ,11,12]

M_CKEA[10,12]

M_WEA#[10,12]
M_CASA#[10,12]
M_RASA#[10,12]

M_CSA#1[1 0,12]
M_CLKA0[4,10,12]
M_CLKA1[4,10,12]

M_CKEB[11,12]

M_WEB#[11,12]
M_CASB#[11,12]
M_RASB#[11,12]

M_CSB#1[1 1,12]
M_CLKB0[4,11,12]
M_CLKB1[4,11,12]

M_MAA[13..0]

M_MAB[13..0]

M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7

M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7

M_CLKA#0
M_CLKA#1
M_CLKB#0
M_CLKB#1

M_CKEA
M_WEA#
M_CASA#0
M_RASA#0
M_CSA#1 M_WEA#
M_CLKA0
M_CLKA1

M_CKEB
M_WEB#
M_CASB#0
M_RASB#0 M_DQMB#6
M_CSB#1
M_CLKB0
M_CLKB1

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13

M_MDA[63..0][10,12]
M_MDB[63..0][11,12]

DIMA0[4,12] DIMA1[4,12] DIMB0[4,12] DIMB1[4,12]

+VREF_U76

M_CLKA#0
M_CSA#1
M_RASA#0
M_CASA#0

M_DQMA#0
M_DQMA#3
M_DQMA#1
M_DQMA#2

M_CKEA

M_MAA12
M_MAA13

M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

M_QSA0
M_QSA3
M_QSA1
M_QSA2

M10

B10
G10

K11
K12

L12
M12

L11

A11

G11

L10
M11

A12

G12

M3

L4
L6

K5
L7

M9
M8

L8
M7
M6

L5
M5
M4

B3
G3

L2

L3
M2

L9

K8

M1

L1

K1

K2

G2

A2

G1

A1

E5

E6

E7

E8

F5

F6

F7

F8
G5
G6
G7
G8
H5
H6
H7
H8

U76

BA0
BA1

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

NC
NC#B10
NC#G3
NC#G10
NC#K11
NC#K12
NC#L2
NC#L3
NC#M2

MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE

DQS3
DQS2
DQS1
DQS0

TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8

_1Mx32x4

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B11

VDDQ#D2

VDDQ#D11

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ

VSSQ#A10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4

VSSQ#F9
VSSQ#G4
VSSQ#G9

VSSQ#H4

VSSQ#H9

VSSQ#J4
VSSQ#J9

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

M_MDA7

A7

M_MDA6

B8

M_MDA5

A8

M_MDA4

A9

M_MDA3

B12

M_MDA2

C11

M_MDA1

C12

M_MDA0

D12

M_MDA30

J2

M_MDA31

J1

M_MDA29

H1

M_MDA28

H2

M_MDA27

F1

M_MDA26

F2

M_MDA25

E1

M_MDA24

E2

M_MDA15

E11

M_MDA14

E12

M_MDA13

F11

M_MDA12

F12

M_MDA11

H11

M_MDA10

H12

M_MDA9

J11

DQ9

M_MDA8

J12

DQ8

M_MDA23

D1

DQ7

M_MDA22

C1

DQ6

M_MDA21

C2

DQ5

M_MDA20

B1

DQ4

M_MDA19

A4

DQ3

M_MDA18

A5

DQ2

M_MDA17

B5

DQ1

M_MDA16

A6

DQ0

B2
B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4

VSS

D6
D7
D9
J5
J6
J7
J8
K4
K9

+MVDDC

C302

1.0uF

C303
_1.0uF

C304
_1.0uF

C301

1.0uF

+MVDDQ +MVDDQ

C309

C307

1.0uF

C308

1.0uF

_1.0uF

C310

1.0uF

64MBytes DDR 128Mbit 1Mx32x4 uBGA Elpida Memory Support

U77

M_MAA12

M3

BA0

M_MAA13

L4

BA1

M_MAA11

L6

A11

M_MAA10

K5

A10

M_MAA9

L7

A9

M_MAA8

M10

A8/AP

M_MAA7

M9

A7

M_MAA6

M8

A6

M_MAA5

L8

A5

M_MAA4

M7

A4

M_MAA3

M6

A3

M_MAA2

L5

A2

M_MAA1

M5

A1

M_MAA0

M4

A0

B3

NC

B10

NC#B10

G3

NC#G3

G10

NC#G10

K11

NC#K11

K12

NC#K12

L2

NC#L2

L3

NC#L3

M2

NC#M2

L12

M_WEA#

M_QSA5
M_QSA7
M_QSA4
M_QSA6

M12

L11

A11

G11

L10

M11

A12

G12

L9
K8

M1
L1
K1
K2

G2

A2

G1

A1

E5
E6
E7
E8
F5
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8

MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE

DQS3
DQS2
DQS1
DQS0

TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8

_1Mx32x4

VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B11

VDDQ#D2

VDDQ#D11

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ#A10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9

VSSQ#J4
VSSQ#J9

VSS#D6
VSS#D7
VSS#D9
VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9

+VREF_U77

+MVDDQ

+MVDDC +MVDDC

M_CLKA#1
M_CSA#1
M_RASA#0
M_CASA#0

M_DQMA#5
M_DQMA#7
M_DQMA#4
M_DQMA#6
M_CLKA1
M_CKEA

+MVDDC

C305
_1.0uF

C311

1.0uF

C306

1.0uF

C312
_1.0uF

C321
_1.0uF

C327

1.0uF

C322
_1.0uF

C328

1.0uF

C323

1.0uF

C329
_1.0uF

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ

VSSQ

M_MDA46

A7

M_MDA47

B8

M_MDA44

A8

M_MDA45

A9

M_MDA42

B12

M_MDA43

C11

M_MDA41

C12

M_MDA40

D12

M_MDA63

J2

M_MDA62

J1

M_MDA61

H1

M_MDA60

H2

M_MDA59

F1

M_MDA58

F2

M_MDA57

E1

M_MDA56

E2

M_MDA38

E11

M_MDA39

E12

M_MDA36

F11

M_MDA37

F12

M_MDA34

H11

M_MDA35

H12

M_MDA33

J11

DQ9

M_MDA32

J12

DQ8

M_MDA55

D1

DQ7

M_MDA54

C1

DQ6

M_MDA53

C2

DQ5

M_MDA52

B1

DQ4

M_MDA51

A4

DQ3

M_MDA50

A5

DQ2

M_MDA49

B5

DQ1

M_MDA48

A6

DQ0

B2
B4

+MVDDQ +MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4

VSS

D6
D7
D9
J5
J6
J7
J8
K4
K9

C324

C325

1.0uF

1.0uF

C331

C330

1.0uF

1.0uF

C326
_1.0uF

C332
_1.0uF

M_MAB12
M_MAB13

M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0

+VREF_U78

M_CLKB#0
M_CSB#1
M_RASB#0
M_CASB#0
M_WEB#
M_DQMB#1
M_DQMB#2
M_DQMB#0
M_DQMB#3
M_CLKB0M_CLKA0

M_CKEB

M_QSB1
M_QSB2
M_QSB0
M_QSB3

+MVDDC

+MVDDQ

M10

B10

G10

K11
K12

L12

M12

L11

A11

G11

L10

M11

A12

G12

C341
_1.0uF

C347
_1.0uF

M3

L4
L6

K5
L7

M9
M8

L8
M7
M6

L5
M5
M4

B3
G3

L2

L3
M2

L9

K8

M1

L1

K1

K2

G2

A2

G1

A1

E5

E6

E7

E8

F5

F6

F7

F8
G5
G6
G7
G8
H5
H6
H7
H8

U78

BA0
BA1

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

NC
NC#B10
NC#G3
NC#G10
NC#K11
NC#K12
NC#L2
NC#L3
NC#M2

MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE

DQS3
DQS2
DQS1
DQS0

TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8

_1Mx32x4

C342
_1.0uF

C348
_1.0uF

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B11

VDDQ#D2

VDDQ#D11

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ

VSSQ#A10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4
VSSQ#F9
VSSQ#G4
VSSQ#G9
VSSQ#H4
VSSQ#H9
VSSQ#J4
VSSQ#J9

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7

VSS#J8
VSS#K4
VSS#K9

C343

1.0uF

C349
_1.0uF

M_MDB15

A7

M_MDB14

B8

M_MDB13

A8

M_MDB12

A9

M_MDB11

B12

M_MDB10

C11

M_MDB9

C12

M_MDB8

D12

M_MDB23

J2

M_MDB22

J1

M_MDB21

H1

M_MDB20

H2

M_MDB19

F1

M_MDB18

F2

M_MDB17

E1

M_MDB16

E2

M_MDB7

E11

M_MDB6

E12

M_MDB5

F11

M_MDB4

F12

M_MDB3

H11

M_MDB2

H12

M_MDB1

J11

DQ9

M_MDB0

J12

DQ8

M_MDB30

D1

DQ7

M_MDB31

C1

DQ6

M_MDB29

C2

DQ5

M_MDB28

B1

DQ4

M_MDB27

A4

DQ3

M_MDB26

A5

DQ2

M_MDB25

B5

DQ1

M_MDB24

A6

DQ0

B2
B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

VSS

+MVDDC +MVDDC

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

C346

C345

C344

1.0uF

C350

1.0uF

_1.0uF

C351

1.0uF

_1.0uF

C352
_1.0uF

+VREF_U79

M_CLKB#1
M_CSB#1
M_RASB#0
M_CASB#0
M_WEB#
M_DQMB#4
M_DQMB#7
M_DQMB#5

M_CLKB1
M_CKEB

M_MAB12
M_MAB13

M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0

M_QSB4
M_QSB7
M_QSB5
M_QSB6

+MVDDC

+MVDDQ

M10

B10
G10

K11
K12

L12

M12

L11

A11

G11

L10

M11

A12

G12

C361
_1.0uF

C367
_1.0uF

M3

L4
L6

K5
L7

M9
M8

L8
M7
M6

L5
M5
M4

B3
G3

L2

L3
M2

L9

K8

M1

L1

K1

K2

G2

A2

G1

A1

E5

E6

E7

E8

F5

F6

F7

F8
G5
G6
G7
G8
H5
H6
H7
H8

U79

BA0
BA1

A11
A10
A9
A8/AP
A7
A6
A5
A4
A3
A2
A1
A0

NC
NC#B10
NC#G3
NC#G10
NC#K11
NC#K12
NC#L2
NC#L3
NC#M2

MCL
VREF
RFU#L9
RFU
CLK
CS
RAS
CAS
WE
DM3
DM2
DM1
DM0
CLK
CKE

DQS3
DQS2
DQS1
DQS0

TH GND
TH GND#E6
TH GND#E7
TH GND#E8
TH GND#F5
TH GND#F6
TH GND#F7
TH GND#F8
TH GND#G5
TH GND#G6
TH GND#G7
TH GND#G8
TH GND#H5
TH GND#H6
TH GND#H7
TH GND#H8

_1Mx32x4

C362
_1.0uF

C368
_1.0uF

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ#B4
VDDQ#B6
VDDQ#B7
VDDQ#B9

VDDQ#B11

VDDQ#D2

VDDQ#D11

VDDQ#E3

VDDQ#E10

VDDQ#F3

VDDQ#F10

VDDQ#H3

VDDQ#H10

VDDQ#J3

VDDQ#J10

VDD#C7
VDD#D3

VDD#D10

VDD#K3
VDD#K6
VDD#K7

VDD#K10

VSSQ

VSSQ#A10

VSSQ#C3
VSSQ#C4
VSSQ#C5
VSSQ#C8
VSSQ#C9

VSSQ#C10

VSSQ#D5
VSSQ#D8
VSSQ#E4
VSSQ#E9
VSSQ#F4

VSSQ#F9
VSSQ#G4
VSSQ#G9

VSSQ#H4

VSSQ#H9

VSSQ#J4

VSSQ#J9

VSS#D6
VSS#D7
VSS#D9

VSS#J5
VSS#J6
VSS#J7
VSS#J8
VSS#K4
VSS#K9

C363
_1.0uF

C369

1.0uF

M_MDB39

A7

M_MDB38

B8

M_MDB37

A8

M_MDB36

A9

M_MDB35

B12

M_MDB34

C11

M_MDB33

C12

M_MDB32

D12

M_MDB63

J2

M_MDB62

J1

M_MDB61

H1

M_MDB60

H2

M_MDB59

F1

M_MDB58

F2

M_MDB57

E1

M_MDB56

E2

M_MDB47

E11

M_MDB46

E12

M_MDB45

F11

M_MDB44

F12

M_MDB43

H11

M_MDB42

H12

M_MDB41

J11

DQ9

M_MDB40

J12

DQ8

M_MDB55

D1

DQ7

M_MDB54

C1

DQ6

M_MDB53

C2

DQ5

M_MDB52

B1

DQ4

M_MDB51

A4

DQ3

M_MDB50

A5

DQ2

M_MDB49

B5

DQ1

M_MDB48

A6

DQ0

B2
B4

+MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

VDD

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4

VSS

D6
D7
D9
J5
J6
J7
J8
K4
K9

C365
_1.0uF

C371

1.0uF

C366

1.0uF

C372
_1.0uF

C364

1.0uF

C370

1.0uF

C313
_1.0uF

C314
_1.0uF

C333
_1.0uF

C334
_1.0uF

C353
_1.0uF

C354
_1.0uF

C373
_1.0uF

C374
_1.0uF

+MVDDQ

+MVDDQ

+MVDDQ

+MVDDQ

R801
_4.99K_1%

+VREF_U76

R802
_4.99K_1%

R803
_4.99K_1%

+VREF_U77

R804
_4.99K_1%

R901
_4.99K_1%

+VREF_U78

R902
_4.99K_1%

R903
_4.99K_1%

+VREF_U79

R904
_4.99K_1%

A A

<Core Design>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

Custom

8

7

6

5

4

3

Date: Sheet

2

105-A034XX-20

7

of

13 20Monday, February 23, 2004

1

8

7

6

5

4

3

DVOMODE [3 , 15 ]

2

1

High-Density Header

DVO/VIP Data Bus

D D

+VDD_DVO

+3.3V_BUS

C C

A_HSYNC_DAC2_B[16,17]
A_VSYNC_DAC2_B[16]

DDCDATA_DAC2_5V[16]

B B

3.3V I2C CLK

SCL[3,19]

Daughter Card Straps

R582 10K
R578 10K
R574 _10K

DEMUX_SEL[3,17]
DC_Strap3[3,17] DC_Strap4 [ 3 ]
DC_Strap1[3,9]

R575 DNI_10K
R579 DNI_10K
R583 DNI_10K

Use to reset S i168 External TMDS

0R

R561

R563
R564
R565

Analog Display from DAC2

A_G/Y_DAC2_HDH

R589
R587

DDC DATA

R588 33R

GPIO11[3,15]

R566

0R
0R
_0R

A_HSYNC_DAC2_HDH

51R

A_VSYNC_DAC2_HDH

51R

DDCDATA_DAC2_HDH

0R

CLK_VID/DVO
VID/DVO6
VID/DVO4
VID/DVO2
VID/DVO0

VID/DVO1
VID/DVO3
VID/DVO5
VID/DVO7
VID/DVO9
VID/DVO11

VHAD1

I2C_CLK

+3.3V_BUS

+5V_BUS

JU101

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66
67 68
69 70

SOCKET_STRIP_2x35_0.05x.1

+3.3V_BUS

R572
R573

CLK_VIPVPHCTL

VHAD0

I2C_DATA

DDCCLK
PCI_RESET

0R
0R

VID/DVO7
VID/DVO5
VID/DVO3
VID/DVO1

VID/DVO0
VID/DVO2
VID/DVO4
VID/DVO6
VID/DVO8
VID/DVO10

R590

4.7K

+VDD_DVO

R591

4.7K

R592

4.7K

R593

4.7K

Daughter Card Straps

R569 0R
R570 0R
R571 _0R

DDCCLK_DAC2_HDH

A_R/C_DAC2_HDH
A_B/COMP_DAC2_HDH

CLK_VID/DVO

VID/DVO[11..0] [3]

VIP Host Bus

CLK_VIPCLK [ 3 ]
VHAD0 [3,15]
VHAD1 [3]
VPHCTL [3 ]

3.3V I2C DATA

0R

R567

R586 33R

HPD_ExtTMDS [3]

SDA [3,19]

R584 10K
R580 10K
R576 DNI_10K

DC_Strap2 [ 3 ]

R577 _10K
R581 DNI_10K
R585 DNI_10K

DDC CLK

DDCCLK_DAC2_5V [16]

Analog Display from DAC2

AGP_RESET# [2,3 ]

DVO Bus control lines for
External DDR TMDS

CLK_VID/DVO [3]

LCDCNTL0 [3]
LCDCNTL1 [3]
LCDCNTL2 [3]

+VDD_DVO

41

SW1A
DIP_SWX2

PAL/NTSC [3 ]

A_R/C_DAC2_HDH
A_G/Y_DAC2_HDH
A_B/COMP_DAC2_HDH

STRAPS

DC_STRAP1 LCDDATA12

DC_STRAP2 LCDDATA13

A A

DC_STRAP4 LCDDATA15 DAC2 Config urationDC_STRAP5 LCDDATA19

DC_STRAP6 LCDDATA18 TVO Standard Default (Resistor pull-up and switch short to GND)

8

PIN

00
01
1
11

DESCRIPTION

Internal TMDS Enabled

0 - Disabled

1 - Enabled

Video Capture Enabled

0 - Disabled

1 - Enabled

DAC2 Off
DAC2 On as CRT
DAC2 On as TVOUT

0

DAC2 On as TVOUT and CRT

0 - PAL (on board resistor pull-down and switch closed)
1 -NTSC (on board resistor pull-up)

7

6

5

Map DAC2 CRT to HDH

R915 DNI_0R
R916 DNI_0R
R917 DNI_0R

Map DAC2 VO to HDH

R918 DNI_0R
R919 DNI_0R
R920 DNI_0R

Map DAC2 to HDH

R921 DNI_0R
R922 DNI_0R
R923 DNI_0R

4

A_R_DAC2
A_G_DAC2
A_B_DAC2

A_C_DAC2
A_Y_DAC2
A_COMP_DAC2

A_R/C_DAC2
A_G/Y_DAC2
A_B/COMP_DAC2

A_R_DAC2 [1 6,17]
A_G_DAC2 [16,17]
A_B_DAC2 [16,17]

A_C_DAC2 [17]
A_Y_DAC2 [17]
A_COMP_DAC2 [17]

A_R/C_DAC2 [3,17]
A_G/Y_DAC2 [3,17]
A_B/COMP_DAC2 [3,1 7]

3

<Core Design>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

C

Date: Sheet

2

105-A034XX-20

of

14 20Monday, February 23, 2004

1

7

8

7

6

5

4

3

2

1

OPTION STRAPS

GPIO[13..0]

GPIO[13..0][3,9,14]

STRAP

D D

C C

GPIO0

GPIO1

GPIO2

GPIO3

GPIO11

GPIO12

GPIO13

GPIO9

GPIO8

GPIO4

GPIO5

GPIO6

G

STRAP
H

STRAP
J

STRAP
K

STRAP L

STRAP M

STRAP
N

STRAP O

STRAP A

STRAP D

STRAP E

STRAP F

R201 10K
R202 DNI_10K
R203 _10K
R204 DNI_10K

R205 DNI_10K
R206 _10K
R207 DNI_10K
R208 10K

R209 DNI_10K
R210 10K
R211 DNI_10K
R212 10K
R213 10K
R214 DNI_10K
R215 10K
R216 DNI_10K

R217 DNI_10K
R218 10K

R219 DNI_10K
R220 _10K
R221 DNI_10K
R222 _10K
R223 DNI_10K
R224 10K

+3.3V_BUS

STRAPS

AGPFBSKEW(1:0)

X1CLK_SKWE(1:0)

ROMIDCFG(3:0)

ID_DISABLE

BUSCFG(2:0)

PIN

GPIO(1:0)

GPIO(3:2)

GPIO(9,13:11)

GPIO(8)

GPIO(6:4)

DESCRIPTION

AGP 1x clock feedback phase adjustment wrt refclk(cpuclk)
00 - refclk s li gh tly earlier then feedback
01 - refclk 1 tap earlier then feedback
10 - refclk 1 t ap later then feedback

11 - refclk 2 ta ps earlier then feedback clock

Clock phase adjustment between x1 clk and x2clk

00 - 0 tap delay

01 - 1 tap delay
10 - 2 taps delay
11 - 3 taps delay

If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
0100 - reserved
0110 - reserved
1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P10 ROM (ST), chip IDis from ROM

1100 - Serial M25P05 ROM (ST), chip IDis from ROM

1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM

0 - Normal operation

1 - Shuts the chip down by not responding to any config cycles
In a system w i th two graphics chips, one on the motherboard,
the other on add-in card, the strap can be used to disable one of the two throught a jumper.

Controls bus type , CL K PL L select, and IDSEL

000 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD16

000 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
001 - 1.5V BUS -> AGP 4x, PLL clk, IDSEL=AD17
001 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
010 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
010 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD16
011 - 1.5V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
011 - 3.3V BUS -> AGP 1x/2x, PLL clk, IDSEL=AD17
100 - PCI 66MHz, PLL clk
101 - PCI 33MHz, 3.3v, REF clk
110 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD16
110 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD16
111 - 1.5V BUS -> AGP 1x, REF clk, IDSEL=AD17
111 - 3.3V BUS -> AGP 1x, REF clk, IDSEL=AD17
Note that for AGP configurations GPIO(4) acts as the IDSEL strap.
For PCI it acts as the PLL bypass (33 or 66MHz) strap.

DEFAULT

11

00

1100

0

000

Mem_Strap0[3]

Mem_Strap1[3]

B B

32

SW1B
DIP_SWX2

PKGTYPE[3]

LCDDATA16[3]

LCDDATA17[3]

R250 10K

VHAD0[3,14]

STRAP R

STRAP S

STRAP T

DVOMODE[3,14]

A A

R235 DNI_10K
R236 10K
R237 10K
R238 DNI_10K

R225 _10K
R226 DNI_10K
R227 DNI_10K
R228 _10K
R229 10K
R230 DNI_10K

R231 10K
R232 DNI_10K

R48 DNI_10K

R49 _10K

+VDDC_CT

+VDD_DVO

MULTIFUNC(1:0)

VIP_DEVICE

STRAP P

LOW

HIGH

MEMORY TYPE STRAPS

SAM

INF
HYN
ELPIDA

LCDDATA(17:16)

LCDDATA(20)
STRAP T

INTERRUPT

ENABLED (DEFAULT)

DISABLED

Mem_Strap0 Mem_Strap1

00

0

1
0

1

11

Multi-function device select
00 - single function device.
01 - two function device. No AGP in either function
10 - two function device. AGP only in function 0

11 - two function device. AGP in both functions

If BUSCFG pin bas ed s tra ps ar e s et t o P CI, t he n AGP will not be enabled in any function.
See AGP func t io n table below for detail on AGP ability claims.

Indicates if any slave VIP host devices drove this in low during reset.
0 - Slave VIP host port devices present

1 - No slave VIP host port devices reporting presence during reset

11

0

<Core Design>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

Custom

8

7

6

5

4

3

Date: Sheet

2

105-A034XX-20

7

of

15 20Tuesday, March 23, 2004

1

8

7

6

5

4

3

OPTIONAL ESD/HOTPLUG PROTECTION DIODES

2

+5V_BUS

1

PRIMARY CRT

A_R_DAC1_F1
A_G_DAC1_F1
A_B_DAC1_F1

D D

A_R_DAC1[3]
A_G_DAC1[3]

A_B_DAC1[3]

C401

R401 75.0R_1%
R402 75.0R_1%
R403 75.0R_1%

3.3pF

C402

3.3pF

L51 82nH_0805
L52 82nH_0805
L53 82nH_0805 L56 68nH_0805

C405

C403

3.3pF

C404

3.3pF

3.3pF

L54 68nH_0805
L55 68nH_0805

C406

3.3pF

DDCDATA_DAC1_5V
DDCCLK_DAC1_5V
A_HSYNC_DAC1_B

A_VSYNC_DAC1_B

R415 _33R
R416 33R
R413

R414

51R
51R

Place close to ASIC

+5V_BUS

C450

1.0uF

A_HSYNC_DAC1[3]

C C

A_VSYNC_DAC1[3]

5
4

147

1
2

6

U7B
SN74ACT86D

U7A
SN74ACT86D

A_HSYNC_DAC1_B

3

A_VSYNC_DAC1_B

CRT1DDCDATA[3]

CRT1DDCCLK[3]

+3.3V_BUS

R404

4.7K

+3.3V_BUS

R406

4.7K

+5V_BUS

Q51

1

2N7002E

R405

6.8k

+5V_BUS

R407

6.8k

DDCDATA_DAC1_5V

DDCCLK_DAC1_5V

32

Q52

1

2N7002E

32

SECONDARY CRT

A_R_DVI-I [18]
A_G_DVI-I [18]

A_R_DAC2_F1
A_G_DAC2_F1
A_B_DAC2_F1

C455

C454

_3.3pF

_3.3pF

L74 _68nH_0805
L75 _68nH_0805
L76 _68nH_0805

C456
_3.3pF

C452
_3.3pF

C453
_3.3pF

L71 _68nH_0805
L72 _68nH_0805
L73 _68nH_0805

A_R_DAC2[14,17]
A_G_DAC2[14,17]

A_B_DAC2[14,17]

C451

R451 _75.0R_1%
R452 _75.0R_1%

B B

R453 _75.0R_1%

_3.3pF

Place close to ASIC

A_HSYNC_DAC2[3]

A_VSYNC_DAC2[3]

A_R_DAC1_F1

A A

A_G_DAC1_F1

A_B_DAC1_F1

8

10

9

13
12

L57 DNI_68nH

L58 DNI_68nH

L59 DNI_68nH

Place close to the output
of the DAC1 filters

8

U7C
SN74ACT86D

11

U7D
SN74ACT86D

A_HSYNC_DAC2_B

A_VSYNC_DAC2_B

7

A_HSYNC_DAC2_B [14,17]

A_VSYNC_DAC2_B [14]

Keep length short,
or another set of
resistors may be
needed

DVIDDCDATA[3]

DVIDDCCLK[3]

+3.3V_BUS +5V_BUS

R454

4.7K

+3.3V_BUS +5V_BUS

R456

4.7K

A_R_DVI-I

A_G_DVI-I

A_B_DVI-I

6

A_B_DVI-I [18]

Q71

1

2N7002E

32

Q72

1

2N7002E

32

DDCCLK_DAC1_5V

DDCDATA_DAC1_5V

A_HSYNC_DAC1_B

A_VSYNC_DAC1_B

R455

6.8k
DDCDATA_DAC2_5V

R457

6.8k
DDCCLK_DAC2_5V

R465 DNI_33R

R467 DNI_33R

R411

R412

5

A_R_DVI-I
A_G_DVI-I
A_B_DVI-I

DDCDATA_DVI-I_R
DDCCLK_DVI-I_R
A_HSYNC_DVI-I_R

A_VSYNC_DVI-I_R

DNI_51R

DNI_51R

DDCDATA_DAC2_5V [1 4 ]

DDCCLK_DAC2_5V [14]

+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V_BUS+5V_BUS

DNI_BAT54S;T1

D55

DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R

A_VSYNC_DAC1_R

DNI_BAT54SLT1

D75

3

R466 33R

R468 33R

R461

R462

2

3

1

2

1

51R

51R

4

DNI_BAT54S;T1

D56

3

DNI_BAT54SLT1

D76

3

DNI_BAT54S;T1

2

1

2

1

D57

3

DNI_5pF

DNI_82nH

GND_CHASSIS

DNI_BAT54SLT1

2

D77

3

1

C457

DNI_5pF

L80

DNI_82nH

GND_CHASSIS

2

1

C407

L60

DNI_82nH

DDCCLK_ D V I-I_ R
DDCCLK_DAC2_5V

DDCDATA_DVI-I_R
DDCDATA_DAC2_5V

+5V_BUS +5V_BUS

DNI_BAT54S;T1

D51

3

C409

C408

DNI_5pF

DNI_5pF

Change these inductors

L62

L61

to 0R for EMI

DNI_82nH

DNI_82nH

DNI_BAT54SLT1

2

D71

3

1

C459

C458

DNI_5pF

DNI_5pF

Change these inductors

L82

L81

to 0R for EMI

DNI_82nH

A_HSYN C _ DV I- I_ R
A_HSYNC_DAC2_B

A_VSYNC_DVI-I_R
A_VSYNC_DAC2_B

DNI_BAT54S;T1

2

1

DNI_BAT54S;T1

2

D52

3

1

2

D53

3

1

Place close to CONNECTOR

DNI_BAT54SLT1

DNI_BAT54SLT1

2

D72

3

1

2

D73

3

1

Place close to CONNECTOR

DDCCLK_D V I-I_ R [18]

DDCDATA_DVI-I_R [18]

A_HSYNC_DVI-I_R [18]

A_VSYNC_DVI-I_R [18]

3

<Core Design>

DNI_BAT54S;T1

D54

3

+5V_BUS+5V_BUS+3.3V_BUS+3.3V_BUS+3.3V_BUS +5V_BUS+5V_BUS

DNI_BAT54SLT1

D74

3

F1
_750mA

Resettable fuse

2

1

B51 B26R_1206

C441
100nF

2

1

R1001 0R_0805

805

R1002 _0R_0805

805

R1003 _0R_0805

805

R1004 0R_0805

805

R1005 _0R_0805

805

R1006 DNI_0R_0805

805

R1007 DNI_0R_0805

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham , O ntario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

C

Date: Sheet

2

11
12

15
13

14

10
16
17

GND_CHASSIS

11
12

15
13

14

10
16
17
18
19

GND_CHASSIS

Three on top side, three at
the bottom, spreaded high,
middle and low vertically

GND_CHASSIS

105-A034XX-20

+5V_DIN

J1

1

R

2

G

3

B
MS0
MS1

4

MS2
MS3

9

NC
HS
VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8
VSS#10
CASE
CASE#17

Connector_DB15_Female_VGA_Blue

MJ2

1

R

2

G

3

B

DDC2_MONID0

MS0

DDC2_MONID1(SDA)

MS1

4

DDC2_MONID2

MS2

DDC2_MONID3(SCL)

MS3

9

NC
HS
VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8
VSS#10
CASE
CASE#17
CASE#18
CASE#19

DNI_DB15F_slim_RA

1

+5V_DIN [17,18]

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

+5V_DIN

of

16 20Monday, February 23, 2004

7

8

7

6

5

4

3

2

1

Place close to ASIC

R541

DNI_75.0R

A_R/C_DAC2
A_G/Y_DAC2
A_B/COMP_DAC2

U96

1

SEL

2

1A0

3

1A1

5

1B0

6

1B1

11

1C0
1C1101D0

15

E

_PI5V330

GND

VCC

A_R_DAC2
A_G_DAC2

+5V_BUS

C735
100nF

16
4

YA

7

YB

9

YC

12

YD

13

1D1

14
8

A_B_DAC2

A_C_DAC2
A_Y_DAC2

A_COMP_DAC2

A_R_DAC2 [14,16]
A_G_DAC2 [14,16]
A_B_DAC2 [14,16]

A_C_DAC2 [14]
A_Y_DAC2 [14]
A_COMP_DAC2 [14]

Place close to ASIC

A_Y_DAC2

A_C_DAC2

A_COMP_DAC2

R504

75.0R_1%

R505

75.0R_1%

R506

75.0R_1%

C501
82pF

C503
82pF

C505
82pF

L91

1.8uH_0805

L92

1.8uH_0805

L93

1.8uH_0805

A_Y_DAC2_F

C502
82pF

GND_CHASSIS

A_C_DAC2_F

C504
82pF

GND_CHASSIS

A_COMP_DAC2_F

C506
82pF

GND_CHASSIS

Cm3

Cm4

Cm5

A_R/C_DAC2[3,14]
A_G/Y_DAC2[3,14]

A_B/COMP_DAC2[3,14]

R539

R540

DNI_75.0R

DNI_75.0R

D D

DEMUX_SEL[3 ,14]

MUX BYPASS

A_R_DAC2A_R/C_DAC2

A_G/Y_DAC2

A_B/COMP_DAC2

C C

R967DNI_0R
R968DNI_0R
R969DNI_0R

R970DNI_0R
R971DNI_0R
R972DNI_0R

A_G_DAC2
A_B_DAC2

A_C_DAC2
A_Y_DAC2

A_COMP_DAC2

PIN2

A_COMP_DAC2_F

B B

R515 DNI_0R

PIN5

R517

DNI_0R

PIN1

R516
0

1
3

GND_CHASSIS

Jm2

PIN7

1

3

2

GND_CHASSIS

MMJ5
DNI_Jack_Phono_RCA

Jm2, Jm3, Jm4 and Jm5 use

A A

8

the same footprint

7

Jm5

2

A_C_DAC2_FA_Y_DAC2_F

4

MMMJ5
Connector_DIN_DNI_Miniature_Circular_4_Pin

TV Out (Comp)

6

DC_Strap3[3,14]

A_HSYNC_DAC2_B[14,16]

STEREOSYNC[3]

5

R523 DNI_0R

A_Y_DAC2_F
A_C_DAC2_F

R518 330R

C509
DNI_470pF

+5V_BUS

53

1
2

D21

DNI_BAT54SLT1

4

R519 _B220R_0603
R520 _B220R_0603
R521 _B220R_0603

C511
DNI_1.0uF

4

U8

DNI_NC7S86M5

+5V_BUS

2

3

1

+5V_DIN[16,18]

C931
DNI_100nF

A_Y_DAC2_DIN
A_C_DAC2_DIN

R513

0

B94 DNI_Bead

R538
DNI_390R

3

R537
DNI_100R

<Core Design>

PIN7A _COMP_DAC2_DINA_COMP_DAC2_F
PIN5

PIN1
PIN2

R514

0

GND_CHASSIS

PIN1

PIN2
PIN7

GND_CHASSIS

TV Out (SVHS)

J5

6
3

4
7
5

1
2

8
9

10

MJ5

1

1

2

2

7

7

8

CASE

9

CASE

10

CASE
DNI_MiniDIN_3_Pin

Jm4

+12V
Y-OUT

C-OUT
Comp_out
SYNC

GND
GND#2

CASE
CASE#9
CASE#10

Conn_DIN_Mini_Circular_7_Pin_with_O_Ring

Jm3

ATI Techno lo gi es Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size D o c ument N umber Re v

Custom

Date: Sheet

2

105-A034XX-20

7

of

17 20Wednesday, February 25, 2004

1

5

4

3

2

1

D D

INSTALL TERMINATION RESISTORS CLOSE TO ASIC

R601 330R

TMDS_TX2N[3]
TMDS_TX2P[3]

DDCCLK_DVI-I

TMDS_TX1N[3]

R602 330R

TMDS_TX1P[3]

C C

TMDS_TX0N[3]
TMDS_TX0P[3]

R603 330R

+5V_DIN[16,17]

DDCDATA_DVI-I

B52 B26R_1206

R604 330R

TMDS_TXCP[3]
TMDS_TXCN[3]

HPD[3]

D122

B B

DDCCLK_DVI-I_R[16]
DDCDATA_DVI-I_R[16]

DNI_MMBZ5222BLT1

1 3

2 1

D121

2.5V_SOT23

A_VSYNC_DVI-I_R[16]

A_HSYNC_DVI-I_R[16]

R609
100K

A_R_DVI-I[16]
A_G_DVI-I[16]
A_B_DVI-I[16]

R610
20K

PRIMARY DVI-I CONNECTOR

J2

M1

CASE

M3

CASE#M3

1

TMDS Data2-

2

TMDS Data2+

3

TMDS Data2/4 Shield

4

TMDS Data4-

5

TMDS Data4+

6

DDC Clock

7

DDC Data

8

Analog VSYNC

9

TMDS Data1-

10

TMDS Data1+

11

TMDS Data1/3 Shield

12

TMDS Data3-

13

TMDS Data3+

14

+5V Power

15

GND (for +5V)

16

Hot Plug Detect

17

TMDS Data0-

18

TMDS Data0+

19

TMDS Data0/5 Shield

20

TMDS Data5-

21

TMDS Data5+

22

TMDS Clock Shield

23

TMDS Clock+

24

TMDS Clock-

C1

Analog Red

C2

Analog Green

C3

Analog Blue

C4

Analog HYNC

C5

Analog GND

C6

Analog GND#C6

M4

CASE#M4

M2

CASE#M2

DVI_A/D

C510
_100nF

IF HOT PLUG DETECT IS NOT REQUIRED

REMOVE ALL T H I S L OGIC EXCEPT

FOR 100K PULL DOWN

GND_CHASSIS GND_CHASSIS

<Core Design>

A A

5

4

3

2

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 12 8M B GA VGA DVI VO

Size Document Number Rev

B

Date: Sheet of

105-A034XX-20

18 20Monday, February 23, 2004

1

7

5

4

3

2

1

D+ [3]
D- [3]

1

+12V_BUS +5V_BUS+3.3V_BUS

R551
0R

Q152

DNI_MMBT2222ALT1

2 3

TACH

C259
DNI_10nF
DNI

R552
DNI_0R
DNI

1
2

JU1
Header_2P_2mm

R558

0R_0805

R560
0_0805

USE 0 Ohm resistor for LM63

ASIC TEMP ERA T URE SENSE A ND FA N SPEED CTRL

+3.3V_BUS

1

ALERT#

C240
DNI_1.0uF
DNI

C258
_100pF

C257
_2.2nF

R555
DNI_1K

Q151
DNI_MMBT2222ALT1

2 3

D+
D­PWM

R550

R548
DNI_1K

TACH

R547
DNI_0R

DNI

D+

SDA

C256
_100nF

R549
DNI_0R
DNI

+3.3V_BUS

SCL
SDA
ALERT#

R554

_10K

8

SMBCLK

7

SMBDAT

6

ALERT

5

GND

MU20
_LM63CIMAX

VDD

PWM

1
2

D+

3

D-

4

DNI_10R

D D

SCL[3,14]
SDA[3,14]

INT_ALERT[3]

1

Q150

2 3

_CMPT3904

+3.3V_BUS

C C

+3.3V_BUS

R544

DNI_10K

DNI

R543

DNI_10K

DNI

ALERT#

R546
DNI_0R

DNI

R545
DNI_0R

DNI

PWM

D-

SCL

3

NC#3

4

NC#4

1

PWM

5

GND

9

D-

13

ADD

16

SCL

7

THERM

8

FAULT

U20
DNI_ADM1030ARQ
DNI

TACH

INT

NC#11

VCC
SDA

2
14
12

NC

11
10

D+

6
15

C260
_10uf_1206

B B

H101

HEATSINK
ASSY

9

A A

10

8

U6C

SN74ACT86D

COMMON

5

4

12
13

11

U6D

SN74ACT86D

COMMON

3

MH101

HEATSINK
ASSY

<Core Design>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

Custom

Date : Sheet

2

105-A034XX-20

of

19 20Monday, February 23, 2004

1

7

5

4

3

2

1

DVI SCREWSCRT SCREWS

ASSY1

SCREW
JACKSCREW

D D

ASSY

ASSY4

SCREW
JACKSCREW
ASSY

ASSY2

SCREW
JACKSCREW
ASSY

ASSY5

SCREW
JACKSCREW
ASSY

ASSY8

BRACKET

MISC. BOARD PARTS

ASSY3

BLANK
LABEL

1.5W_X_0.50H

ASSY7

ANTISTATIC
BAG

6_X_11
ASSY

REF1

SCHEMATIC

105-A034XX-00
ASSY

REF2

PCB

109-A03400-00

REF3

ATI LOGO
LABEL

ATI_LOGO_LABEL

NO_TABS,_VGA,_DIN,_DVI

C C

B B

A A

<Core Design>

ATI Technologies Inc.

1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
[phone]

Title

AGP RV350 128M BGA VGA DVI VO

Size Document Number Rev

B

5

4

3

2

Date: Sheet

105-A034XX-20

20 20Monday, February 23, 2004

1

7

of