ATI AGP RV350 Schematics
5
<Core D
esign>
Title
4
3
2
1
Date:Schematic No.
AGP RV350 128M BGA VGA DVI VO
105-A034XX-20
REVISION HISTORY
D D
Sch
Rev
0 10/23/02 PRELIMINARY BASED ON "RV-350 REFERENCE (105-REF113-00A)"
1 01/10/03 Removed C168, C169, to make the MVREFS, MVREFD traces shorter (for better noise)
2 01/15/03 Added fix for MVDDQ leakage and R119, C163
C C
3 01/15/03 Added external strap for PKGTYPE
Date
REVISION DESCRIPTION
Added R91 pull-up to fix "cold boot" problem: some boards would perform like ID DISABLED without the R91, because of floating /CS pin on the ROM (serial output overrides the ID DISABLED strap).
Added J5/6 connection for auto detection of component video
Added R100, R101 for easier power measurement
Changed AGP connector to 4X/8X type
Added provision for 3.3V_BUS on the MVDDC power supply
PCB changed to rev C to fix component interference with daughtercards
Removed R9, R11
Added R102 pull down
Fixed connection QSA4, QSA5 on the ASIC side
Changed C106, C107 to though-hole, added C166, C167 surface mount, alternate
Added C74
Added pullups for ZV_LCDCNTL(3:0) and STEREOSYNC
Changed R123 to pull-up to MVDDC
Added R255 for VDDC enable
Added D122 alternative for cost reduction
Added R1007 for EMI
Removed R605, R606, R607, R608 to improve EMI
Monday, February 23, 2004
Rev
7
4 03/26/03 Allegro conversion based on the latest -00 revision
B B
5 05/27/03
6 07/30/03
7 09/23/03
A A
5
PCB changes only. No schematic changes from previous revision.
This is a pads version based on the -00 revision.
Changed thermal sence and fan control circuit
Changed temperature interrupt to AUXWIN aand added inverter
Added C165
Changed p/n for J5, ASSY3, REF2
Deleted ASSY6
4
3
2
1
5
4
3
2
1
MEMORY CHANNEL A
D D
BGA Memory 4Mx32
MEMORY TERMINATIONS A
MA[14..0]
CASA#
RASA#
WEA#
QSA[7..0]
CS0A#MDA[63..0]
DQMA[0..7]
CLKA01CKEA
CLKA01#
MB[14..0]
CASB#
QSB[7..0]
MDB[63..0] CS0B#
WEA/B#
RASB#
MEMORY CHANNEL B
BGA Memory 4Mx32
MEMORY TERMINATIONS B
DQMB[0..7]
CKEB/D CLKB01
CLKB01#
PRIMARY CRT
LOGIC
VGA
DB15
CONN
MEM A MEM B
DAC1
C C
R G B HSY VSY DDC1DATA DDC1CLK
DVI-I CONN
THERMAL
SENSOR
DPLUS DMINUS I2C_CLK I2C_DAT
TMDS
TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
INTEGRATED TMDS
LOGIC
STRAPS
BIOS
HEATSINK/FAN
B B
POWER
REGULATION
VDDC VDDC_CT MVDDC MVDDQ VTT
PVDD TPVDD MPVDD
A2VDD Vref
ROMCS#
ROM
RV350
TVO
DDR DVO
VIP
DAC2
DVO, VID ports
Y/R C/G COMP/B H2SYNC
D
E
CRT2DDCDATA CRT2DDCCLK V2SYNC
TVOUT Filters
HDH
TVOUT
CONN
and/or VGA Slim
DB15 CONN
M
AGP/PCI
LCDDATA19
SEL
U
X
Secondary
CRT LOGIC
CBE3..0
GNT#
CLK
SBA[7..0]
AD_STB1#
CPUCLK
TRDY#
INTR
ST2..0
WBF#
AD_STB0
DEVSEL#
DBI_HI
SB_STB
AD_STB0#
RESET#
DBI_LO
SB_STB#
RBF#
<Core Design>
REFERENCE
DESIGN
THESE SCHEMATICS ARE
SUBJECT TO MODIFICATION
AND DESIGN IMPROVEMENTS.
PLEASE CONTACT ATI FIELD
APPLICATION ENGINEERING
BEFORE USING THE INFORMATION CONTAINED HEREIN.
3
RESTRICTION
NOTICE
THESE SCHEMATICS CONTAIN
INFORMATION W HICH IS PROPRIETARY
TO AND IS THE PROPERTY OF ATI, AND
MAY NOT BE USED, REPRODUCED OR
DISCLOSED IN ANY MANNER WITHOUT
EXPRESSED WRITTEN PERMISSION
FROM ATI.
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV350 128M BGA VGA DVI VO
Size Document Number Rev
B
2
Date: Sheet
105-A034XX-20
120Monday, February 23, 2004
1
of
7
AD31..0
IRDY#
FRAME#
+5V_BUS+3.3V_BUS
+12V_BUS
+VDDQ_BUS
A A
5
AGPREF
AD_STB1
AGP B US
4X/8X
4
PAR
REQ#
STOP#
8
7
6
5
4
3
2
1
4X/8X AGP BUS
GND_TPVSSGND_MPVSS
GND_A2VSSN
+12V_BUS +5V_BUS +3.3V_BUS
C10
100uF_16V
D D
C C
B B
C5
100uF_16V
AGP_INTR#[3]
AGP_GNT#[3]
AGP_MB_8X_DET#[3]
AGP_DBI_HI[3]
AGP_WBF#[3]
AGP_SBSTB#[3]
AGP_ADSTB1#[3]
AGP_FRAME#[3]
AGP_TRDY#[3]
AGP_STOP#[3]
AGP_PAR[3]
AGP_ADSTB0#[3]
C8
100uF_16V
+VDDQ_BUS
TYDET
AGP_GC_8X_DET#
AGP_RST#
R15 _0R
R16 _0R
R18 _0R
R1 0R
R5 _0R
R7 0R
R12 _0R
AGP_VREFGC
USE 47uF TANTALUM
CAPACITOR OR HIGHER
C2
47uF_16V_Tant
>=6.3V
+12V_BUS
+3.3V_BUS
+VDDQ_BUS
AGP_ST1
AGP_SBA1
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_C/BE#3
AGP_AD22
AGP_AD20 AGP_AD19
AGP_AD18
AGP_AD16
AGP_PAR_R
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0
MAGP1
A1
12V
A2
TYPEDET#
A3
GC_DET#/RESERVED
A4
USB-
A5
GND
A6
INTA#
A7
RST#
A8
GNT#
A9
VCC3.3
A10
ST1
A11
MB_DET#/RESERVED
A12
DBI_HI/PIPE#
A13
GND#A13
A14
WBF#
A15
SBA1
A16
VCC3.3#A16
A17
SBA3
A18
SB_STB#
A19
GND#A19
A20
SBA5
A21
SBA7
A22
RESERVED
A23
GND#A23
A24
RESERVED#A24
A25
VCC3.3#A25
A26
AD30
A27
AD28
A28
VCC3.3#A28
A29
AD26
A30
AD24
A31
GND#A31
A32
AD_STB1#
A33
C/BE3#
A34
VDDQ1.5
A35
AD22
A36
AD20
A37
GND#A37
A38
AD18
A39
AD16
A40
VDDQ1.5#A40
A41
FRAME#
A42
KEY
A43
KEY#A43
A44
KEY#A44
A45
KEY#A45
A46
TRDY#
A47
STOP#
A48
PME#
A49
GND#A49
A50
PAR
A51
AD15
A52
VDDQ1.5#A52
A53
AD13
A54
AD11
A55
GND#A55
A56
AD9
A57
C/BE0#
A58
VDDQ1.5#A58
A59
AD_STB0#
A60
AD6
A61
GND#A61
A62
AD4
A63
AD2
A64
VDDQ1.5#A64
A65
AD0
A66
VREFGC
1.5V_AGP_BUS
OVRCNT#
5.0V#B3
GND#B5
VCC3.3#B9
GND#B13
DBI_LO/RESERVED
VCC3.3#B16
SB_STB
GND#B19
RESERVED#B22
GND#B23
3.3VAUX
VCC3.3#B25
VCC3.3#B28
GND#B31
AD_STB1
VDDQ1.5#B34
GND#B37
VDDQ1.5#B40
KEY#B42
KEY#B43
KEY#B44
KEY#B45
DEVSEL#
VDDQ1.5#B47
GND#B49
VDDQ1.5#B52
GND#B55
VDDQ1.5#B58
AD_STB0
GND#B61
VDDQ1.5#B64
VREFCG
USB+
INTB#
REQ#
RBF#
SBA0
SBA2
SBA4
SBA6
AD31
AD29
AD27
AD25
AD23
AD21
AD19
AD17
C/BE2#
IRDY#
PERR#
SERR#
C/BE1#
AD14
AD12
AD10
+3.3V_BUS
+5V_BUS
+VDDQ_BUS
B1
B2
5.0V
B3
B4
B5
B6
B7
CLK
B8
B9
B10
ST0
B11
ST2
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
AD8
B58
B59
B60
AD7
B61
B62
AD5
B63
AD3
B64
B65
AD1
B66
AGP_ST0
AGP_ST2
AGP_SBA0
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_AD23
AGP_AD21
AGP_AD17
AGP_C/BE#2
AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1
AGP_C/BE#[3..0]
AGP_AD[31..0]
AGP_SBA[7..0]
AGP_ST[2..0]
AGP_AGPCLK_R
AGP_DBI_LO_R
AGP_SBSTB_R
AGP_ADSTB1_R
AGP_ADSTB0_R
AGP_AGPREF
AGP_C/BE#[3..0] [3]
AGP_AD[31..0] [3]
AGP_SBA[7..0] [3]
AGP_ST[2..0] [3]
R61 0R
R62 _0R
R2 0R
R6 _0R
R8 0R
R10 0R
R13 0R
C1
DNI_1.0uF
C4
DNI_10pF
AGP_AGPCLK [3]
AGP_REQ# [3]
AGP_RBF# [3]
AGP_DB I_LO [3]
AGP_SBSTB [3]
AGP_ADSTB1 [3]
AGP_IRDY# [3]
AGP_DEVSEL# [3]
AGP_ADSTB0 [3]
GND_PVSS GND_TXVSSR
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE
GND_AVSSQ GND_RSET
GND_A2VSSQ
GND_R2SETGND_AVSSN
SYMBOL LEGEND
DNI
DO NOT
INSTALL
#
ACTIVE
LOW
DIGITAL
GROUND
ANALOG
GROUND
UNIVERSAL VREFCG CIRCUIT (4X, 8X)
<Core Design>
AGP_AGPREF
TEST
Q5
_2N7002E
+VDDQ_BUS
32
1
2
R66
R64
_324R_1%
DNI_0R
R67
_147R_1%
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
Size Docum e n t N u mb er R ev
C
Date: Sheet
AGP_AGPREFCG
C7
R65
10nF
_100R_1%
*
AGP RV350 128M BGA VGA DVI VO
105-A034XX-20
AGP_AGPREFCG [3]
of
220Monday, February 23, 2004
1
7
TEST
+VDDQ_BUS+3.3V_BUS
32
1
Q1
2N7002E
R23
1K
R21
147R_1%
R20
324R_1%
R24
_100R_1%
3
AGP_VREFGC
C6
10nF
*
TYDET
AGP_GC_8X_DET#
A A
R19
2.2R
R60
_0R
For retail, 1K ohm
pull-down causes AMD
system detects
AGP2X only
+12V, TYPEDET#
short protection
for OEM (1KR)
+5V_BUS
C11
1.0uF
147
AGP_RST#
1
AGP_RESET#[3,14]
R4
180R
R3
100R
3
U6A
SN74ACT86D
2
AGP_MB_8X_DET#[3]
AGP_MB_8X_DET#
8X_DET#[3]
R17
47K
4
5
U6B
SN74ACT86D
6
UNIVERSAL VREFGC CIRCUIT (4X, 8X)
8
7
6
5
4
5
4
3
2
1
AGP_AD[31..0][2]
D D
*
AGP_C/BE#[3..0][2]
C C
AGP_SBA[7..0][2]
R46
_4.7K
AGP_ST[2..0][2]
AGP_AGPREFCG[2]
AGP_MB_8X_DET#[2]
A_R/C_DAC2[14,17]
A_G/Y_DAC2[14,17]
A_B/COMP_DAC2[14,17]
A_HSYNC_DAC2[16]
A_VSYNC_DAC2[16]
+VDDQ_BUS
R37
32
_47R
Q2
DNI_2N7002E
8X_DET#[2]
B B
1
R38
DNI_71.5R
+3.3V_BUS
R45
_4.7K
SCL[14,19]
SDA[14,19]
OPTION 1: Crystal Circuit
C71
DNI_22pF
+3.3V_BUS
C3
100nF
A A
C72
DNI_22pF
Y2
8
VDD
4
GND
27.000MHz
2 1
OUT
Y1
DNI_27_MHZ
5
1
E/D
+3.3V_BUS
R27
150R
R32
DNI_1M
R28
100R_1%
OPTION 2: Oscillator Circuit
5
AGP_AD[31..0]
AGP_C/BE#[3..0]
AGP_AGPCLK[2]
AGP_RESET#[2,14]
AGP_REQ#[2]
AGP_GNT#[2]
AGP_PAR[2]
AGP_STOP#[2]
AGP_DEVSEL#[2]
AGP_TRDY#[2]
AGP_IRDY#[2]
AGP_FRAME#[2]
AGP_INTR#[2]
AGP_WBF#[2]
AGP_RBF#[2]
AGP_ADSTB0[2]
AGP_ADSTB1[2]
AGP_SBSTB[2]
AGP_SBA[7..0]
AGP_ST[2..0]
AGP_SBSTB#[2]
AGP_ADSTB0#[2]
AGP_ADSTB1#[2]
AGP_DBI_LO[2]
AGP_DBI_HI[2]
R29
0R_0805
OSCILLATOR CAN BE
CONNECTED TO XTALIN
OR XTALOUT
When RV350_XTALOUT is
used by the oscillator, XTALIN
should be grounded to prevent
the input buffers from picking
up noise.
OPTIONAL SCAN PIN_PERMISSION
TP10
PLACE C83 CLOSE TO ASIC PIN
GND_R2SET
TP6
R14
0R
R33
0R
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2
C83 1 00nF
R40 715R_1%
TESTEN
R41
R42
_0R
_0R
R36
4.7K
4
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
U1A
H29
AD0
Part 1 of 6
H28
AD1
J29
AD2
J28
AD3
K29
AD4
K28
AD5
L29
AD6
L28
AD7
N28
AD8
P29
AD9
P28
AD10
R29
AD11
R28
AD12
T29
AD13
T28
AD14
U29
AD15
N25
AD16
R26
AD17
P25
AD18
R27
AD19
R25
AD20
T25
AD21
T26
AD22
U25
AD23
V27
AD24
W26
AD25
W25
AD26
Y26
AD27
Y25
AD28
AA26
AD29
AA25
AD30
AA27
AD31
N29
C/BE#0
U28
C/BE#1
P26
C/BE#2
U26
C/BE#3
AG30
PCICLK
AG28
RST#
AF28
REQ#
AD26
GNT#
M25
PAR
N26
STOP#
V29
DEVSEL#
V28
TRDY#
W29
IRDY#
W28
FRAME#
AE26
INTA#
AC26
WBF#
AE29
RBF#
M28
AD_STBF_0
V25
AD_STBF_1
AB29
SB_STBF
AD28
SBA0
AD29
SBA1
AC28
SBA2
AC29
SBA3
AA28
SBA4
AA29
SBA5
Y28
SBA6
Y29
SBA7
AF29
ST0
AD27
ST1
AE28
ST2
AB28
SB_STBS
M29
ADSTBS_0
V26
ADSTBS_1
M26
AGPREF
M27
AGPTEST
AB26
DBI_LO
AB25
DBI_HI
AC25
AK21
AJ23
AJ22
AK22
AJ24
AK24
AG23
AG24
AK25
AJ25
AH28
AJ29
AH27
E8
B6
AE25
AG26
AH30
AH29
AG29
R30
0R
STEREOSYNC [17]
+3.3V_BUS
IT IS RECOMMENDED TO ALLOW SERIES RESISTOR
FOOT PRINTS ON THE INDICATED AGP CONTROL SIGNALS
TO ADDRESS ANY LAYOUT NOISE RELATED
AGP
AGP_DET#
R2SET
C_R_Pr
Y_G_Y
COMP_B_Pb
H2SYNC
V2SYNC
DDC3CLK
DDC3DATA
VSS
NC#AJ25
XTALIN
XTALOUT
TESTEN
TEST_YCLK
TEST_MCLK
PLLTEST
STEREOSYNC
NC
NC#AH29
RSTB_MSK
RV350
SIGNAL DAMPING REQUIREMENTS
PCI / AGPAGP2X
4X
8X
DAC2CLK
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
DVOMODE
ZV_LCDDATA0
ZV_LCDDATA1
ZV_LCDDATA2
ZV_LCDDATA3
ZV_LCDDATA4
ZV_LCDDATA5
ZV_LCDDATA6
ZV_LCDDATA7
ZV_LCDDATA8
ZV_LCDDATA9
DVO / EXT TMDS / GPIOTMDSDAC1
ZV_LCDDATA10
ZV_LCDDATA11
ZV_LCDDATA12
ZV_LCDDATA13
ZV_LCDDATA14
ZV_LCDDATA15
ZV_LCDDATA16
ZV_LCDDATA17
ZV_LCDDATA18
ZV_LCDDATA19
ZV_LCDDATA20
ZV_LCDDATA21
ZV_LCDDATA22
ZV_LCDDATA23
ZV_LCDCNTL0
ZV_LCDCNTL1
ZV_LCDCNTL2
ZV_LCDCNTL3
VREFG
NC#AK16
NC#AH16
NC#AH17
NC#AJ16
NC#AH18
NC#AJ17
NC#AK19
NC#AH19
NC#AK18
NC#AJ18
NC#AG16
NC#AF16
NC#AG17
NC#AF17
NC#AF18
NC#AE18
NC#AH20
NC#AG20
NC#AF19
NC#AG19
NC#AE12
NC#AG12
TX0M
TX1M
TX2M
TXCM
TXCP
DDC2CLK
DDC2DATA
HPD1
HSYNC
VSYNC
RSET
DDC1DATA
DDC1CLK
AUXWIN
DPLUS
DMINUS
THERM
TX0P
TX1P
TX2P
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AG4
AK16
AH16
AH17
AJ16
AH18
AJ17
AK19
AH19
AK18
AJ18
AG16
AF16
AG17
AF17
AF18
AE18
AH20
AG20
AF19
AG19
AE12
AG12
AJ13
AH14
AJ14
AH15
AJ15
AK15
AH13
AK13
AE13
AE14
AF12
AK27
R
AJ27
G
AJ26
B
AG25
AH25
AH26
AF25
AF24
AF26
AF11
AE11
C74
100nF
R39 _499R_1%
AUXWIN
3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
DVOMODE
VID/DVO0
VID/DVO1
VID/DVO2
VID/DVO3
VID/DVO4
VID/DVO5
VID/DVO6
VID/DVO7
VID/DVO8
VID/DVO9
VID/DVO10
VID/DVO11
VID/DVO12
VID/DVO13
VID/DVO14
VID/DVO15
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23
LCDCNTL0
LCDCNTL1
LCDCNTL2
LCDCNTL3
R34
_1.00K_1%
TP11
TP12
D+ [19]
D- [19]
HPD_ExtTMDS [14]
Mem_Strap1 [15]
Mem_Strap0 [15]
DVOMODE [14,15]
+3.3V_BUS
R35
_1.00K_1%
Boundary scan test
A_HSYNC_DAC1
SCL
CRT1DDCDATA
CRT1DDCCLK
A_VSYNC_DAC1
TESTEN
GND_RSET
R63
_4.7K
GPIO[13..0]
+3.3V_BUS
GPIO[13..0] [9, 1 4 , 15]
PKGTYPE [15]
DC_Strap2 [14]
DC_Strap3 [14,17]
DC_Strap4 [14]
LCDDATA16 [15]
LCDDATA17 [15]
PAL/NTSC [14]
DEMUX_SEL [14,17]
VHAD0 [14,15]
VHAD1 [14]
VPHCTL [14]
CLK_VIPCLK [14]
LCDCNTL0 [14]
LCDCNTL1 [14]
LCDCNTL2 [14]
CLK_VID/DVO [14]
TMDS_TX0N [18]
TMDS_TX0P [18]
TMDS_TX1N [18]
TMDS_TX1P [18]
TMDS_TX2N [18]
TMDS_TX2P [18]
TMDS_TXCN [18 ]
TMDS_TXCP [18]
DVIDDCCLK [16]
DVIDDCDATA [16]
HPD [ 18]
A_R_DAC1 [16]
A_G_DAC1 [16]
A_B_DAC1 [16]
A_HSYNC_DAC1 [16]
A_VSYNC_DAC1 [16]
TP7
CRT1DDCDATA [16]
CRT1DDCCLK [16]
INT_ALERT [19]
GPIO7
GPIO10
VID/DVO[11..0]
TRST/
TDO
TDI
TMS
TCK
R31
_0R
VID/DVO[11..0] [14]
TP1
TP2
TP3
TP4
TP5
TP8
2
EXT_PWR [7]
DC_Strap1 [9,14]
<Core Design>
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV350 128M BGA VGA DVI VO
Size Docum e n t N u mb er R ev
Custom
Date: Sheet
105-A034XX-20
1
of
320Monday, February 23, 2004
7
1
2
3
4
5
6
7
8
QSA[7..0][10] QSB[7..0][11]
DQMA#[7..0][10]
MAA[13..0][10]
MDA[63..0][10]
A A
B B
C C
QSA[7..0]
DQMA#[7..0]
MAA[13..0]
MDA[63..0]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
DQMB#[7..0][11]
MAB[13..0][11]
MDB[63..0][11]
U1B
L25
DQA0
L26
DQA1
K25
DQA2
K26
DQA3
J26
DQA4
H25
DQA5
H26
DQA6
G26
DQA7
G30
DQA8
D29
DQA9
D28
DQA10
E28
DQA11
E29
DQA12
G29
DQA13
G28
DQA14
F28
DQA15
G25
DQA16
F26
DQA17
E26
DQA18
F25
DQA19
E24
DQA20
F23
DQA21
E23
DQA22
D22
DQA23
B29
DQA24
C29
DQA25
C25
DQA26
C27
DQA27
B28
DQA28
B25
DQA29
C26
DQA30
B26
DQA31
F17
DQA32
E17
DQA33
D16
DQA34
F16
DQA35
E15
DQA36
F14
DQA37
E14
DQA38
F13
DQA39
C17
DQA40
B18
DQA41
B17
DQA42
B15
DQA43
C13
DQA44
B14
DQA45
C14
DQA46
C16
DQA47
A13
DQA48
A12
DQA49
C12
DQA50
B12
DQA51
C10
DQA52
C9
DQA53
B9
DQA54
B10
DQA55
E13
DQA56
E12
DQA57
E10
DQA58
F12
DQA59
F11
DQA60
E9
DQA61
F9
DQA62
F8
DQA63
RV350
Part 2 of 6
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA0#
CSA1#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
MEMORY INTERFACE A
MVREFD
MVREFS
DIMA_0
DIMA_1
MAA0
E22
MAA1
B22
MAA2
B23
MAA3
B24
MAA4
C23
MAA5
C22
MAA6
F22
MAA7
F21
MAA8
C21
MAA9
A24
MAA10
C24
MAA11
A25
MAA12
E21
MAA13
B20
C19
DQMA#0
J25
DQMA#1
F29
DQMA#2
E25
DQMA#3
A27
DQMA#4
F15
DQMA#5
C15
DQMA#6
C11
DQMA#7
E11
QSA0
J27
QSA1
F30
QSA2
F24
QSA3
B27
QSA4
E16
QSA5
B16
QSA6
B11
QSA7
F10
RASA#
A19
CASA#
E18
WEA#
E19
CSA#0
E20
CSA#1
F20
CKEA
B19
CLKA0
B21
CLKA#0
C20
CLKA1
C18
CLKA#1
A18
RASA# [10]
CASA# [10]
WEA# [10]
CSA#0 [10]
CSA#1 [10]
CKEA [10]
CLKA0 [10,12,13]
CLKA#0 [10,12,13]
CLKA1 [10,12,13]
CLKA#1 [10,12,13]
B7
B8
DIMA0
D30
B13
DIMA1
DIMA0 [12,13]
DIMA1 [12,13]
R57
_100R_1%
+MVDDQ
C151
_100nF
+MVDDQ
QSB[7..0]
DQMB#[7..0]
MAB[13..0]
MDB[63..0]
R56
_133R_1%
R58
_47R
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
U1C
D7
DQB0
F7
DQB1
E7
DQB2
G6
DQB3
G5
DQB4
F5
DQB5
E5
DQB6
C4
DQB7
B5
DQB8
C5
DQB9
A4
DQB10
B4
DQB11
C2
DQB12
D3
DQB13
D1
DQB14
D2
DQB15
G4
DQB16
H6
DQB17
H5
DQB18
J6
DQB19
K5
DQB20
K4
DQB21
L6
DQB22
L5
DQB23
G2
DQB24
F3
DQB25
H2
DQB26
E2
DQB27
F2
DQB28
J3
DQB29
F1
DQB30
H3
DQB31
U6
DQB32
U5
DQB33
U3
DQB34
V6
DQB35
W5
DQB36
W4
DQB37
Y6
DQB38
Y5
DQB39
U2
DQB40
V2
DQB41
V1
DQB42
V3
DQB43
W3
DQB44
Y2
DQB45
Y3
DQB46
AA2
DQB47
AA6
DQB48
AA5
DQB49
AB6
DQB50
AB5
DQB51
AD6
DQB52
AD5
DQB53
AE5
DQB54
AE4
DQB55
AB2
DQB56
AB3
DQB57
AC2
DQB58
AC3
DQB59
AD3
DQB60
AE1
DQB61
AE2
DQB62
AE3
DQB63
Part 3 of 6
RV350
MEMORY INTERFACE B
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
CASB#
WEB#
CSB0#
CSB1#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
DIMB_0
DIMB_1
ROMCS#
MEMVMODE_0
MEMVMODE_1
MEMTEST
MAB0
N5
MAB1
M1
MAB2
M3
MAB3
L3
MAB4
L2
MAB5
M2
MAB6
M5
MAB7
P6
MAB8
N3
MAB9
K2
MAB10
K3
MAB11
J2
MAB12
P5
MAB13
P3
P2
DQMB#0
E6
DQMB#1
B2
DQMB#2
J5
DQMB#3
G3
DQMB#4
W6
DQMB#5
W2
DQMB#6
AC6
DQMB#7
AD2
QSB0
F6
QSB1
B3
QSB2
K6
QSB3
G1
QSB4
V5
QSB5
W1
QSB6
AC5
QSB7
AD1
RASB#
R2
CASB#
T5
WEB#
T6
CSB#0
R5
CSB#1
R6
CKEB
R3
CLKB0
N1
CLKB#0
N2
CLKB1
T2
CLKB#1
T3
DIMB0
E3
DIMB1
AA3
AF5
C6
C7
C8
R55
_47R
R53
DNI_4.7K
RASB# [11]
CASB# [11]
WEB# [11]
CSB#0 [11]
CSB#1 [11]
CKEB [11]
CLKB0 [11,12,13]
CLKB#0 [11,12,13]
CLKB1 [11,12,13]
CLKB#1 [11,12,13]
DIMB0 [12,13]
DIMB1 [12,13]
ROMCS# [9]
R51 4.7K
R52 4.7K
R54
DNI_4.7K
+VDDC_CT
C152
R59
100nF
MEMORY CHANNEL A
D D
1
2
3
_51R
4
MEMORY CHANNEL B
5
VDDR1 MEMVMODE_0 MEMVMODE_1
1.8V
2.5V
2.8V
<Core Design>
6
GND
+VDDC_CT GND
+VDDC_CT +VDDC_CT
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, On ta ri o
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV350 128M BGA VGA DVI VO
Size Document Number Re v
Custom
Date: Sheet
7
+VDDC_CT
105-A034XX-20
7
of
420Wednesday, February 25, 2004
8
5
+MVDDQ
CP6A
D D
C C
B B
CP6B
_10nF
_10nF
8 1
7 2
+MVDDQ
C32
C33
1.0uF
1.0uF
CP6C
_10nF
6 3
C35
1.0uF
10uF_16V_TANT
C61
10uF_16V_TANT
GND_A2VSSN
10uF_16V_TANT
CP6D
_10nF
5 4
C57
+VDDR4
10uF_16V_TANT
+A2VDD
10uF_16V_TANT
GND_A2VSSQ
GND_PVSS
CP5A
_10nF
8 1
+MVDDQ
C39
10uf_1206
+TPVDD
B11
B200R_0805
C62
1.0uF
+A2VDDQ
C63
10uF_16V_TANT
+PVDD
C54
7 2
C38
10uf_1206
C43
1.0uF
C59
C67
GND_AVSSN
C53
1.0uF
CP5B
_10nF
C64
1.0uF
+AVDD
C58
1.0uF
GND_TPVSS
C60
1.0uF
CP5C
_10nF
6 3
C73
100pF
C81
100pF
GND_TXVSSR
+VDDR4
C68
1.0uF
B200R_0805
10uF_16V_TANT
+MPVDD
C52
10uF_16V_TANT
GND_MPVSS
CP5D
_10nF
5 4
+A2VDD
B10
B200R_0805
+MVDDQ
B12
C66
C51
1.0uF
C65
1.0uF
AE17
AE20
AE15
AF21
AK12
AF13
AF14
AG21
AH21
AF22
AH24
AE24
AE22
AK28
H10
H13
H15
H17
AA1
AA4
AA7
AA8
G10
G13
G15
G19
G22
G27
H22
H19
AD4
D19
D13
AJ20
F18
T7
R4
R1
N8
N7
M4
L27
L8
J24
J23
J8
J7
J4
J1
T8
V4
V7
V8
A3
A9
A15
A21
A28
B1
B30
D26
D23
D20
D17
D14
D11
D8
D5
E27
F4
G7
T4
N4
N6
A7
4
U1D
VDDR1#T7
VDDR1#R4
VDDR1#R1
VDDR1#N8
VDDR1#N7
VDDR1#M4
VDDR1#L27
VDDR1#L8
VDDR1#J24
VDDR1#J23
VDDR1#J8
VDDR1#J7
VDDR1#J4
VDDR1#J1
VDDR1#H10
VDDR1#H13
VDDR1#H15
VDDR1#H17
VDDR1#T8
VDDR1#V4
VDDR1#V7
VDDR1#V8
VDDR1#AA1
VDDR1#AA4
VDDR1#AA7
VDDR1#AA8
VDDR1#A3
VDDR1
VDDR1#A15
VDDR1#A21
VDDR1#A28
VDDR1#B1
VDDR1#B30
VDDR1#D26
VDDR1#D23
VDDR1#D20
VDDR1#D17
VDDR1#D14
VDDR1#D11
VDDR1#D8
VDDR1#D5
VDDR1#E27
VDDR1#F4
VDDR1#G7
VDDR1#G10
VDDR1#G13
VDDR1#G15
VDDR1#G19
VDDR1#G22
VDDR1#G27
VDDR1#H22
VDDR1#H19
VDDR1#AD4
VDDR1#T4
VDDR1#N4
VDDR1#D19
VDDR1#D13
A2VDD
VDDL1
VDDL0#AE15
VDDL0#AF21
VDDL0
TPVDD
TXVDDR
TXVDDR#AF14
VDDRH0
VDDRH1
A2VDD#AG21
A2VDD#AH21
A2VDDQ
AVDD
VDD1DI
VDD2DI
PVDD
MPVDD
RV350
Part 4 of 6
VDDC#AD13
VDDC#AD15
VDDC#AC15
VDDC#AC17
VDDC15#AC11
VDDC15#AC20
VDDC15#Y23
VDDC15#L23
VDDC15#H20
VDDC15#H11
VDDR3#AD19
VDDR3#AD21
VDDR3#AD22
VDDR3#AC22
VDDR3#AC21
VDDR3#AC19
VDDR3#AC8
VDDR4#AG7
VDDR4#AD9
VDDR4#AC10
VDDR4#AD10
VDDP#AE30
VDDP#AC27
VDDP#AC23
VDDP#AB30
VDDP#AA24
VDDP#AA23
I/O POWER
TXVSSR#AH12
TXVSSR#AG13
A2VSSN#AJ21
VDDC
VDDC15
VDDC15#Y8
VDDR3
VDDR4
VDDP#J30
VDDP#AF27
VDDP#Y27
VDDP#W30
VDDP#V23
VDDP#V24
VDDP#M23
VDDP#M24
VDDP
VDDP#P23
VDDP#P27
VDDP#T23
VDDP#T24
VDDP#T30
VDDP#U27
AVSSQ
VSS#AF20
VSS#AE19
VSS#AE16
VSS#AF15
TPVSS
TXVSSR
VSSRH0
VSSRH1
A2VSSN
A2VSSQ
AVSSN
VSS1DI
VSS2DI
PVSS
MPVSS
3
DIODE SUPPLIES POWER
TO VDDC RAIL
WHILE VDDC REGULATOR
STABALIZES DURING POWER ON
+3.3V_BUS
D30
2.4V_SOD123
2 1
C24
+3.3V_BUS
2 1
C70
10uF_16V_TANT
>= 6.3V
TP9
GND_AVSSQ
GND_TPVSS
GND_TXVSSR
GND_AVSSN
GND_PVSS
10uf_1206
D31
_2.4V_SOD123
+VDDC_CT
GND_A2VSSQ
AC13
AD13
AD15
AC15
AC17
P8
Y8
AC11
AC20
Y23
L23
H20
H11
AD7
AD19
AD21
AD22
AC22
AC21
AC19
AC8
AG7
AD9
AC9
AC10
AD10
J30
AF27
AE30
AC27
AC23
AB30
AA24
AA23
Y27
W30
V23
V24
M23
M24
N30
P23
P27
T23
T24
T30
U27
AD24
AF20
AE19
AE16
AF15
AJ19
VSS
AJ12
AH12
AG13
AG14
F19
M6
AH22
AJ21
AF23
AH23
AE23
AE21
AJ28
A6
GND_MPVSS
CP2A
_10nF
8 1
CP3A
_10nF
8 1
C46
C44
1.0uF
1.0uF
B53 B200R_0805
C69
1.0uF
C36
C37
1.0uF
1.0uF
GND_A2VSSN
+3.3V_BUS
8 1
7 2
7 2
CP9A
_10nF
CP2B
_10nF
CP3B
_10nF
6 3
+VDDR4+VDD_DVO
R68
DNI_0R
R69
_0R
CP9B
_10nF
7 2
CP2C
_10nF
CP3C
_10nF
6 3
+3.3V_BUS
6 3
+VDDC
CP9C
_10nF
CP8A
CP2D
_10nF
5 4
CP3D
_10nF
5 4
CP9D
_10nF
5 4
_10nF
8 1
CP4A
_10nF
8 1
1.0uF
+VDDC_CT
C49
1.0uF
+VDDQ_BUS
7 2
+VDDC
C26
CP8B
_10nF
7 2
CP4B
_10nF
1.0uF
C48
1.0uF
6 3
+VDDC
C27
CP8C
_10nF
5 4
CP4C
_10nF
6 3
C28
1.0uF
C47
1.0uF
CP8D
_10nF
2
+VDDC
U1F
P17
VDDC
Part 6 of 6
P18
VDDC#P18
P19
VDDC#P19
U12
VDDC#U12
U13
VDDC#U13
U14
VDDC#U14
U17
VDDC#U17
U18
VDDC#U18
U19
VDDC#U19
V19
VDDC#V19
V18
VDDC#V18
CENTER
V17
VDDC#V17
V14
VDDC#V14
ARRAY
V13
VDDC#V13
V12
VDDC#V12
N18
VDDC#N18
N17
VDDC#N17
N14
VDDC#N14
W17
VDDC#W17
W18
VDDC#W18
W12
VDDC#W12
W13
VDDC#W13
W14
VDDC#W14
N13
VDDC#N13
N19
VDDC#N19
M19
VDDC#M19
M18
VDDC#M18
M12
VDDC#M12
N12
VDDC#N12
M13
VDDC#M13
M14
VDDC#M14
P12
VDDC#P12
P13
VDDC#P13
P14
VDDC#P14
M17
VDDC#M17
W19
VDDC#W19
RV350
U1E
A2
VSS
A10
VSS#A10
A16
VSS#A16
A22
VSS#A22
A29
VSS#A29
C1
VSS#C1
C3
VSS#C3
C28
VSS#C28
C30
VSS#C30
D27
VSS#D27
D24
VSS#D24
D21
VSS#D21
D18
VSS#D18
D15
VSS#D15
D12
VSS#D12
E4
VSS#D9
VSS#D6
VSS#D4
VSS#F27
VSS#G9
VSS#G12
VSS#G16
VSS#G18
VSS#G21
VSS#G24
VSS#H27
VSS#H23
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12
VSS#H9
VSS#H8
VSS#H4
VSS#K30
VSS#K27
VSS#K24
VSS#K23
VSS#AG15
VSS#AD12
VSS#AE27
VSS#AG5
VSS#AG9
VSS#AG11
VSS#AG18
VSS#AG22
VSS#AG27
VSS#E4
VSS#AB4
RV350
CORE GND
D9
D6
D4
F27
G9
G12
G16
G18
G21
G24
H27
H23
H21
H18
H16
H14
H12
H9
H8
H4
K30
K27
K24
K23
AG15
AD12
AE27
AG5
AG9
AG11
AG18
AG22
AG27
AB4
ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED
PLACED CLOSE TO THE POWER/GND PINS
WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC
5 4
1.0uF
CP4D
_10nF
C29
C45
1.0uF
VDDC1#M15
VDDC1#R19
VDDC1#T12
Part 5 of 6
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#D9
VSS#D6
VSS#D4
VSS#F27
VSS#H21
VSS#H18
VSS#H16
VSS#H14
VSS#H12
VSS#H9
VSS#H8
VSS#H4
VSS#K7
VSS#AE16
VSS#AF15
VSS#AF20
VSS#AE19
VSS#M7
VSS#N23
VDDC1
VSS
VSS#AE16
VSS#AF15
VSS#AF20
VSS#AE19
VSS#AA30
VSS#AB27
VSS#AB24
VSS#AB23
VSS#AC12
VSS#AC14
VSS#AD16
VSS#AC16
VSS#AC18
VSS#AD30
VSS#AD25
VSS#AD18
VSS#AK29
VSS#N23
VSS#N24
VSS#N27
VSS#R23
VSS#R24
VSS#R30
VSS#T27
VSS#U23
VSS#V30
VSS#W23
VSS#W24
VSS#W27
VSS#AB8
VSS#AB7
VSS#AB1
VSS#AC4
VSS#AK2
VSS#AJ30
VSS#AJ1
VSS#D10
VSS#D25
M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16
W16
M15
R19
T12
VSS#K8
VSS#K7
VSS#M7
VSS#P4
VSS#R7
VSS#R8
VSS#T1
VSS#U4
VSS#U8
VSS#W7
VSS#W8
VSS#Y4
K8
K7
K1
L4
M30
M8
M7
N23
N24
N27
P4
R7
R8
R23
R24
R30
T27
T1
U4
U8
U23
V30
W7
W8
W23
W24
W27
Y4
AA30
AB27
AB24
AB23
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD30
AD25
AD18
AK2
AK29
AJ30
AJ1
D10
D25
1
A A
<Core Design>
5
4
3
2
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV350 128M BGA VGA DVI VO
Size Docum e n t N u mb er R ev
C
Date: Sheet
105-A034XX-20
1
of
520Monday, February 23, 2004
7
8
7
6
5
4
3
2
1
+3.3V_BUS
***
B21
C101
470uF_6.3V
Rc1
R253
_1.10K_1%
1%
Rc2
R256
_1.78K_1%
1%
60R_1806
Cout1
***
C106
1000uF_10V
***
Dual footprint Dual footprint
**
C108
22uF_16V_TANT
**
C166
DNI_470uF
+VDDC
**
DNI_22uF_16V
**
***
***
C109
C107
1000uF_10V
DNI_470uF
+VDDC
***
C97
***
C167
DNI_470uF
D D
+12V_BUS
+5V_BUS
BOOT_VDDC
C105
1.0uF
C C
+PW_V DDC
SS_VDDC
COMP_VDDC
Fb_VDDC
Alternative 2
B B
SS_VDDC
C100
220nF
COMP_VDDC
+3.3V_BUS
R255
_10K
R258 _51K
R259 _3K
R257
DNI_10K
C113
DNI_10nF
Alternative 1
U31
2
Vcc
6
8
7
4
1
2
3
4
5
6
7
HDrv
Vc
LDrv
SS
Comp
GND
DNI_IRU3037ACS
Alternate part IRU3037CS
MU31
RT
OCSET
SS
COMP
FB
EN
GND
_ISL6522CB
Fb
VCC
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
5
3
1
14
13
12
11
BOOT_VDDC
10
9
8
ISL6522CB : SOIC
ISL6522CV : TSSOP
+12V_BUS
R251 _10R
+VDDC Switching Regulator
Q21
4 5
3
2
1
IRF7413A
Q22
4 5
3
2
1
IRF7413A
Fb_VDDC
+PW_V DDC
6
7
8
L63
1.5uH_9.0A
6
7
8
C110
1nf
Cc1
R254
_1.5K
Rc4
C102
1.0uF
Part
IRU3037
Regulator for VDDC (RV350 Core)
Vin = 3.3V_BUS
Vout = 1.2V
IRU3037A
ISL6522CB
Compensation options for
+VDDC regulator
Alt. Compensation 1
This compensation circuit is
simplified and will only work
with the IRU 3037(A ) Regulator
COMP_VDDC
C103
DNI_2.2nF
Cc4
R252
DNI_27K
Rc6
Alt. Compensation 2
This is re quired for the ISL6522CB
regulator, and provides maximum
regulation speed for IRU3037 Regultor
COMP_VDDC
C111
Cc3
Cc2
Cout1
33pF
C112
10nF
Fb_VDDC
R260
_15K
Rc5
470uF thru hole capacitor has 30mR ESR
where as 470uF SMT capacitor has
22mR ESR. For curre nt below 4.5A, 1
thru 470uF is enough.
INSTALL DO NOT INSTALL
Alternative1
Alternative2
Compens ation Circuit
Common, and Either Alt.
Compensation 1, or Alt.
Compensation 2
Common and Alt.
Compensation 2
Common
Note: Alternative
Compensation
Circuit 2 will only
work if Rc1 is a 1k
Ohm Resistor.
Alternative
Compensation
Circuit 1 has no
requirements for
the divider circuit.
Cc4, Rc6
Alternative 2
Alternative1
C104
4.7nf
SS_VDDC
Iout = 7A MAX (load consumption)
Iout = 3A MAX (Power rail consumption)
REG . VOLTAGE RESISTORS
Rc1
A A
ISL6522C
8
1.2V
1.25V
1.3V
1.00K (p/n 3240100100) 2K (p/n 3240200100)
1.10K (p/n 3240110100)
7
Rc2
1K78 (p/n 3240178100)1.00K (p/n 3240100100)
1K78 (p/n 3240178100)
<Core Design>
6
5
4
3
Indicates number of vias required for the connection
***
C166, C167 alternate parts for C106, C107
Place C102 capacitor very close to the Q21 pins
ATI Technologies Inc.
1 Commerce Valley Drive East
Markham, Ontario
Canada, L3T 7X6
(905) 882-2600
Title
AGP RV350 12 8M B GA VGA DVI VO
Size Document Number Rev
B
Date: Sheet
2
105-A034XX-20
of
620Monday, March 29, 2004
1
7
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