Atec L116b User Manual

LP38690 LP38692

1A Low Dropout CMOS Linear RegulatorsStable with Ceramic Output

Capacitors

General Description

The LP38690/2 low dropout CMOS linear regulators provide tight output tolerance (2.5% typical), extremely low dropout voltage (450mV @ 1A load current, V AC performance utilizing ultra low ESR ceramic output capacitors.

The low thermal resistance of the LLP, SOT-223 and T0-252 packages allow the full operating current to be used even in high ambient temperature environments.

The use of a PMOS power transistor means that no DC base drive current is required to bias it allowing ground pin current to remain below 100 µA regardless of load current, input voltage, or operating temperature.

Dropout Voltage: 450 mV (typ) @ 1A (typ. 5V out). Ground Pin Current: 55 µA (typ) at full load. Precision Output Voltage: 2.5% (25°C) accuracy.

= 5V), and excellent

OUT

Typical Application Circuits

Features

2.5% output accuracy (25°C)

●

Low dropout voltage: 450mV @ 1A (typ, 5V out)

●

Wide input voltage range (2.7V to 10V)

●

Precision (trimmed) bandgap reference

●

Guaranteed specs for -40°C to +125°C

●

1µA off-state quiescent current

●

Thermal overload protection

●

Foldback current limiting

●

T0-252, SOT-223 and 6-Lead LLP packages

●

Enable pin (LP38692)

●

Applications

Hard Disk Drives

●

Notebook Computers

●

Battery Powered Devices

●

Portable Instrumentation

●

Note:

* Minimum value required for stability.

**LLP package devices only.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

20126601

20126602

LP38690 LP38692

Connection Diagrams

TO-252, Top View

LP38690DT-X.X

6-Lead LLP, Top View

LP38690SD-X.X

Pin Descriptions

Pin Description

GND

SNS

OUT

DAP

20126604

20126606

20126603

20126605

SOT-223, Top View

LP38692MP-X.X

6-Lead LLP, Top View

LP38692SD-X.X

This is the input supply voltage to the regulator. For LLP devices, both VIN pins must be tied together for full current operation (500mA maximum per pin).

Circuit ground for the regulator. For the TO-252 and SOT-223 packages this is thermally connected to the die and functions as a heat sink when the soldered down to a large copper plane.

Output sense pin allows remote sensing at the load which will eliminate the error in output voltage due to voltage drops caused by the resistance in the traces between the regulator and the load. This pin must be tied to V

OUT

The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.

Regulated output voltage.

LLP Only - The DAP (Exposed Pad) functions as a thermal connection when soldered to a copper plane. See LLP MOUNTING section in Application Hints for more information.

Ordering Information

Order Number Package Marking Package Type Package Drawing Supplied As

LP38690SD-1.8 L113B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38690SD-2.5 L114B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38690SD-3.3 L115B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38690SD-5.0 L116B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38690DT-1.8 LP38690DT-1.8 TO-252 TD03B 75 Units per Rail

LP38690DT-2.5 LP38690DT-2.5 TO-252 TD03B 75 Units per Rail

LP38690DT-3.3 LP38690DT-3.3 TO-252 TD03B 75 Units per Rail

LP38690DT-5.0 LP38690DT-5.0 TO-252 TD03B 75 Units per Rail

LP38692SD-1.8 L123B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38692SD-2.5 L124B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38692SD-3.3 L125B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38692SD-5.0 L126B 6-Lead LLP SDE06A 1000 Units Tape and Reel

LP38692MP-1.8 LJPB SOT-223 MP05A 1000 Units Tape and Reel

LP38692MP-2.5 LJRB SOT-223 MP05A 1000 Units Tape and Reel

LP38692MP-3.3 LJSB SOT-223 MP05A 1000 Units Tape and Reel

LP38692MP-5.0 LJTB SOT-223 MP05A 1000 Units Tape and Reel

LP38690SDX-1.8 L113B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38690SDX-2.5 L114B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38690SDX-3.3 L115B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38690SDX-5.0 L116B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38690DTX-1.8 LP38690DT-1.8 TO-252 TD03B 2500 Units Tape and Reel

LP38690DTX-2.5 LP38690DT-2.5 TO-252 TD03B 2500 Units Tape and Reel

LP38690DTX-3.3 LP38690DT-3.3 TO-252 TD03B 2500 Units Tape and Reel

LP38690DTX-5.0 LP38690DT-5.0 TO-252 TD03B 2500 Units Tape and Reel

LP38692SDX-1.8 L123B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38692SDX-2.5 L124B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38692SDX-3.3 L125B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38692SDX-5.0 L126B 6-Lead LLP SDE06A 4500 Units Tape and Reel

LP38692MPX-1.8 LJPB SOT-223 MP05A 2000 Units Tape and Reel

LP38692MPX-2.5 LJRB SOT-223 MP05A 2000 Units Tape and Reel

LP38692MPX-3.3 LJSB SOT-223 MP05A 2000 Units Tape and Reel

LP38692MPX-5.0 LJTB SOT-223 MP05A 2000 Units Tape and Reel

For LP38690 Ordering and Availability Information see: http://www.national.com/pf/LP/LP38690.html#Order For LP38692 Ordering and Availability Information see: http://www.national.com/pf/LP/LP38692.html#Order

LP38690 LP38692

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

Storage Temperature Range −65°C to +150°C Lead Temp. (Soldering, 5 seconds) 260°C ESD Rating (Note 3) 2 kV Power Dissipation (Note 2) Internally Limited V(max) All pins (with respect to GND) -0.3V to 12V I

OUT

Internally Limited

Junction Temperature −40°C to +150°C

Operating Ratings

VIN Supply Voltage 2.7V to 10V

Operating Junction Temperature Range

−40°C to +125°C

Electrical Characteristics Limits in standard typeface are for T

the full operating temperature range. Unless otherwise specified: VIN = V

OUT

= 25°C, and limits in boldface type apply over

+ 1V, CIN = C

limits are guaranteed through testing, statistical correlation, or design.

Symbol Parameter Conditions Min

-2.5 2.5

Output Voltage Tolerance

100 µA < IL < 1A

VO + 1V ≤ VIN ≤ 10V

ΔVO/ΔV

ΔVO/ΔI

Output Voltage Line Regulation

(Note 6)

Output Voltage Load Regulation (Note 7)

VO + 0.5V ≤ VIN ≤ 10V IL = 25mA

1 mA < IL < 1A VIN = VO + 1V

(VO = 1.8V) IL = 1A

(VO = 2.5V) IL = 0.1A IL = 1A

VIN - V

OUT

Dropout Voltage (Note 8)

(VO = 3.3V) IL = 0.1A IL = 1A

(VO = 5V) IL = 0.1A IL = 1A

Quiescent Current

VIN ≤ 10V, IL =100 µA - 1A

VEN ≤ 0.4V, (LP38692 Only)

IL(MIN) Minimum Load Current

Foldback Current Limit VIN - VO > 5V

VIN - VO ≤ 4V

VIN - VO < 4V 1500

PSRR Ripple Rejection VIN = VO + 2V(DC), with 1V(p-p) /

120Hz Ripple

Thermal Shutdown Activation (Junction Temp)

TSD (HYST) Thermal Shutdown Hysteresis

(Junction Temp)

= 10 µF, I

OUT

Typ

(Note 4)

= 10mA. Min/Max

LOAD

Max Units

-5.0 5.0

0.03 0.1 %/V

1.8 5 %/A

950 1600

800

650

450

145

1300

110

1000

100 800

55 100

0.001 1

100

450

55 dB

160

OUT

µA

°C

LP38690 LP38692

Symbol Parameter Conditions Min

Output Noise BW = 10Hz to 10kHz

VO = 3.3V

VO (LEAK) Output Leakage Current VO = VO(NOM) + 1V @ 10V

Enable Voltage (LP38692 Only) Output = OFF 0.4

0.7

0.5 12 µA

Typ

(Note 4)

Max Units

µV/

Output = ON, VIN = 4V 1.8

Output = ON, VIN = 6V 3.0

Output = ON, VIN = 10V 4.0

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions.

Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). The junction-to-ambient thermal resistance ( θ copper area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the TO-252, the θ SOT-223 package has a θ when soldered to a copper area of one square inch. The θ thermal vias used (refer to application note AN-1187 and the LLP MOUNTING section in this datasheet). If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.

Note 3: ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.

Note 4: Typical numbers represent the most likely parametric norm for 25°C operation.

Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.

Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.

Enable Pin Leakage VEN = 0V or 10V, VIN = 10V -1 0.001 1

) for the TO-252 is approximately 90°C/W for a PC board mounting with the device soldered down to minimum

J-A

of approximately 125°C/W when soldered down to a minimum sized pattern (less than 0.1 square inch) and approximately 70°C/W

J-A

values for the LLP package are also dependent on trace area, copper thickness, and the number of

J-A

drops to approximately 50°C/W. The

J-A

µA

LP38690 LP38692

Block Diagrams

FIGURE 1. LP38690 Functional Diagram (LLP)

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20126608

FIGURE 2. LP38690 Functional Diagram (TO-252)

FIGURE 3. LP38692 Functional Diagram (LLP)

LP38690 LP38692

20126609

20126610

FIGURE 4. LP38692 Functional Diagram (SOT-223)

LP38690 LP38692

Typical Performance Characteristics Unless otherwise specified: T

pin is tied to VIN (LP38692 only), V

Noise vs Frequency

= 1.8V, VIN = V

OUT

+1V, IL = 10mA.

OUT

20126635

Noise vs Frequency

Ripple Rejection

= 25°C, CIN = C

= 10 µF, Enable

OUT

20126636

20126637

Ripple Rejection

20126620

Ripple Rejection

20126618

20126622

LP38690 LP38692

Line Transient Response

20126624

Line Transient Response

20126626

Load Transient Response

20126628

20126641

20126640

Load Transient Response

20126642

LP38690 LP38692

Load Transient Response

vs Temperature (5.0V)

OUT

20126643

Load Transient Response

vs Temperature (3.3V)

OUT

20126644

vs Temperature (2.5V)

OUT

20126630

20126632

vs Temperature (1.8V)

OUT

20126631

20126633

vs VIN (1.8V)

OUT

vs VIN (Power-Up)

OUT

LP38690 LP38692

vs VEN, ON (LP38692 Only)

OUT

Dropout Voltage vs I

OUT

20126659

20126661

vs VEN, OFF (LP38692 Only)

OUT

Dropout Voltage vs I

20126660

20126662

OUT

20126650

20126651

LP38690 LP38692

Enable Voltage vs Temperature

Line Regulation vs Temperature

20126652

Load Regulation vs Temperature

20126653

20126654

LP38690 LP38692

Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance.

INPUT CAPACITOR: An input capacitor of at least 1µF is required (ceramic recommended). The capacitor must be located not more than one centimeter from the input pin and returned to a clean analog ground.

OUTPUT CAPACITOR: An output capacitor is required for loop stability. It must be located less than 1 centimeter from the device and connected directly to the output and ground pins using traces which have no other currents flowing through them.

The minimum amount of output capacitance that can be used for stable operation is 1µF. Ceramic capacitors are recommended (the LP38690/2 was designed for use with ultra low ESR capacitors). The LP38690/2 is stable with any output capacitor ESR between zero and 100 Ohms.

ENABLE PIN (LP38692 only): The LP38692 has an Enable pin (EN) which allows an external control signal to turn the regulator output On and Off. The Enable On/Off threshold has no hysteresis. The voltage signal must rise and fall cleanly, and promptly, through the ON and OFF voltage thresholds. The Enable pin has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the Enable pin is driven from a source that actively pulls high and low, the drive voltage should not be allowed to go below ground potential or higher than VIN. If the application does not require the Enable function, the pin should be connected directly to the VIN pin.

Foldback Current Limiting: Foldback current limiting is built into the LP38690/2 which reduces the amount of output current the part can deliver as the output voltage is reduced. The amount of load current is dependent on the differential voltage between VIN and V V

differential is reduced below 4V, load current is limited to about 1500 mA.

OUT

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and variation with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range.

. Typically, when this differential voltage exceeds 5V, the load current will limit at about 450 mA. When the VIN -

OUT

Capacitor Characteristics

CERAMIC

For values of capacitance in the 10 to 100 µF range, ceramics are usually larger and more costly than tantalums but give superior AC performance for bypassing high frequency noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature.

Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range.

X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance.

TANTALUM

Solid Tantalum capacitors have good temperature stability: a high quality Tantalum will typically show a capacitance value that varies less than 10-15% across the full temperature range of -40°C to +125°C. ESR will vary only about 2X going from the high to low temperature limits.

REVERSE VOLTAGE

A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and C reversed. A less common condition is when an alternate voltage source is connected to the output.

continues to hold a sufficient charge such that the input to output voltage becomes

OUT

There are two possible paths for current to flow from the output pin back to the input during a reverse voltage condition.

1) While VIN is high enough to keep the control circuity alive, and the Enable pin (LP38692 only) is above the V the control circuitry will attempt to regulate the output voltage. If the input voltage is less than the programmed output voltage, the

EN(ON)

threshold,

control circuit will drive the gate of the pass element to the full ON condition. In this condition, reverse current will flow from the output pin to the input pin, limited only by the R an output capacitor up to 1000 μF in this manner will not damage the device as the current will rapidly decay. However, continuous

of the pass element and the output to input voltage differential. Discharging

DS(ON)

reverse current should be avoided. When the Enable pin is low this condition will be prevented.

2) The internal PFET pass element has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, when VIN is below the value where the control circuity is alive, or the Enable pin is low (LP38692 only), and the output voltage is more than 500 mV (typical) above the input voltage the parasitic diode becomes forward biased and current flows from the output pin to the input pin through the diode. The current in the parasitic diode should be limited to less than 1A continuous and 5A peak.

If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground to limit the negative voltage transition. A Schottky diode is recommended for this protective clamp.

LP38690 LP38692

PCB LAYOUT

Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the input, output, and ground pins of the regulator using traces which do not have other currents flowing in them (Kelvin connect).

The best way to do this is to lay out CIN and C ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a "single point ground".

It should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the ground points of the IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single point ground technique for the regulator and it’s capacitors fixed the problem. Since high current flows through the traces going into VIN and coming from V these pins so there is no voltage drop in series with the input and output capacitors.

LLP MOUNTING

The SDE06A (No Pullback) 6-Lead LLP package requires specific mounting techniques which are detailed in National Semiconductor Application Note # 1187. Referring to the section PCB Design Recommendations in AN-1187 (Page 5), it should be noted that the pad style which should be used with the LLP package is the NSMD (non-solder mask defined) type. Additionally, it is recommended the PCB terminal pads to be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection.

The input current is split between two VIN pins, 1 and 6. The two VIN pins must be connected together to ensure that the device can meet all specifications at the rated current.

The thermal dissipation of the LLP package is directly related to the printed circuit board construction and the amount of additional copper area connected to the DAP.

The DAP (exposed pad) on the bottom of the LLP package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device lead 2 (i.e. GND). Alternately, but not recommended, the DAP may be left floating (i.e. no electrical connection). The DAP must not be connected to any potential other than ground.

For the LP38690SD and LP38692SD in the SDE06A 6-Lead LLP package, the junction-to-case thermal rating, θJC, is 10.4°C/W, where the case is the bottom of the package at the center of the DAP. The junction-to-ambient thermal performance for the LP38690SD and LP38692SD in the SDE06A 6-Lead LLP package, using the JEDEC JESD51 standards is summarized in the following table:

Board

Type

JEDEC

2–Layer

JESD 51-3

JEDEC

4–Layer

JESD 51-7

near the device with short traces to the VIN, V

OUT

Thermal

Vias

OUT

, and ground pins. The regulator

OUT

, Kelvin connect the capacitor leads to

None 10.4°C/W 237°C/W

1 10.4°C/W 74°C/W

2 10.4°C/W 60°C/W

4 10.4°C/W 49°C/W

6 10.4°C/W 45°C/W

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit’s performance because of the small dimensions of the geometries inside the device. In applications where circuit sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must be taken to ensure that this does not affect the IC regulator.

If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC.

If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency. This means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the output capacitor(s).

In applications where the load is switching at high speed, the output of the IC may need RF isolation from the load. It is recommended that some inductance be placed between the output capacitor and the load, and good RF bypass capacitors be placed directly across the load.

PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces. Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes begin to look inductive and RFI/ EMI can cause ground bounce across the ground plane. In multi-layer PCB applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground.

LP38690 LP38692

OUTPUT NOISE

Noise is specified in two ways: Spot Noise or Output Noise Density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1Hz bandwidth). This type of noise is usually plotted on a curve as a function of frequency. Total Output Noise or Broad-Band Noise is the RMS sum of spot noise over a specified bandwidth, usually several decades of frequencies.

Attention should be paid to the units of measurement. Spot noise is measured in units µV/root-Hz or nV/root-Hz and total output noise is measured in µV(rms)

The primary source of noise in low-dropout regulators is the internal reference. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current).

LP38690 LP38692

Physical Dimensions inches (millimeters) unless otherwise noted

6-lead, LLP Package

NS Package Number SDE06A

TO-252 Package

NS Package Number TD03B

LP38690 LP38692

SOT-223 Package

NS Package Number MP05A

Notes

Atec L116b User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Typical Application Circuits

Features

Applications

Connection Diagrams

Pin Descriptions

Ordering Information

Operating Ratings

Electrical Characteristics Limits in standard typeface are for T

Block Diagrams

FIGURE 1. LP38690 Functional Diagram (LLP)

FIGURE 2. LP38690 Functional Diagram (TO-252)

FIGURE 3. LP38692 Functional Diagram (LLP)

FIGURE 4. LP38692 Functional Diagram (SOT-223)

Typical Performance Characteristics Unless otherwise specified: T

Application Hints

EXTERNAL CAPACITORS

SELECTING A CAPACITOR

Capacitor Characteristics

CERAMIC

TANTALUM

REVERSE VOLTAGE

PCB LAYOUT

LLP MOUNTING

RFI/EMI SUSCEPTIBILITY

OUTPUT NOISE

Physical Dimensions inches (millimeters) unless otherwise noted