Atec DG535 User Manual
Digital Delay/Pulse Generator
DG535 — Digital delay and pulse generator (4-channel)
· Four independent delay channels
· Two fully-defined pulse channels
· 5 ps delay resolution
· <100 ps rms jitter
· Adjustable amplitude and offset
· Delays up to 1000 seconds
· 1 MHz maximum trigger rate
· Standard GPIB interface
· Optional ±32 V outputs
· DG535 ... $4195 (U.S. list)
DG535 Digital Delay/Pulse Generator
The DG535 Digital Delay/Pulse Generator provides four
precisely-timed logic transitions or two independent pulse
outputs. The delay resolution on all channels is 5 ps, and the
channel-to-channel jitter is typically 50 ps. Front-panel BNC
outputs deliver TTL, ECL, NIM or variable level (–3 to +4 V)
pulses into 50 Ω or high impedance loads. The high accuracy,
low jitter, and wide delay range make the DG535 ideal for
laser timing systems, automated testing, and precision
pulse
applications.
Delay Outputs
There are four delay output channels: A, B, C and D. The logic
transitions of these outputs can be delayed from an internal or
external trigger by up to 1000 seconds in 5 ps increments.
The T0 pulse, which marks the beginning of a timing cycle, is
generated by the trigger signal. The insertion delay between
an external trigger and the T0 pulse is about 85 ns.
Delays for each channel may be “linked” to T0 or any of the
other delay channels. For instance, you can specify the delays
of the four channels as:
A = T0 + 0.00125000
B = A + 0.00000005
C = T0 + 0.10000000
D = C + 0.00100000
Stanford Research Systems
phone: (408)744-9040
www.thinkSRS.com
DG535 Digital Delay/Pulse Generator
In this case, when the A delay is changed, the B output will
move with it. This is useful, for instance, when A and B
specify a pulse and you want the pulse width to remain
constant as the delay of the pulse is changed. Regardless of
how the delay is specified, each delay output will stay asserted
until 800 ns after all delays have timed out. The delays will
then become unasserted, and the unit will be ready to begin a
new timing cycle.
Pulse Outputs
In addition to the four delay outputs, there are four pulse
output channels: AB, –AB, CD and –CD. The leading edge
of the AB pulse coincides with the leading edge of the earlier
of A or B, and the trailing edge of the AB pulse coincides
with the leading edge of the later of B or A. For instance, in
the previous example, a 50 ns pulse would appear at the AB
output and a 1 ms pulse at CD. Pulses as short as 4 ns (FWHM)
can be generated in this manner. The complementary outputs
(–AB and –CD) provide a pulse with identical timing and
inverted amplitude.
Output Amplitude Control
Each delay and pulse output has an independently adjustable
offset and amplitude which can be set between –3 V and +4 V
with 10 mV resolution. The maximum transition for each
output is limited to 4 V. In addition, you can also separately
select 50 Ω or high impedance termination for each output.
Preset levels, corresponding to standard logic families, can
also be selected. TTL, NIM and ECL levels can each be set
with a single key press.
Triggering
The DG535 can be triggered internally from 1 mHz to 1 MHz
with 4-digit frequency resolution. External, single-shot and
burst mode triggers are also supported. For power control
applications, the DG535 can be synchronized to the AC line.
An optional trigger inhibit input allows you to enable or
disable triggering with a TTL level input signal.
±32 Volt Outputs
For applications requiring higher voltages, a rear-panel high
voltage (±32 V) option is available. This option provides five
rear-panel BNCs which output 1 µs pulses at the transition
times of the front-panel T0, A, B, C and D outputs. The high
voltage option does not affect the function or the timing of the
front-panel outputs. The amplitude of the rear-panel outputs
is approximately 8× the corresponding front-panel output,
and the outputs are designed to drive 50 Ω loads. Since they
can only drive an average current of 0.8 mA, charging and
discharging the cable capacitance may be the most important
A timing cycle is initiated by an internal or external trigger. T0 is asserted approx. 85 ns after an external trigger.
Outputs A, B, C and D are asserted relative to T0 after
their programmed delays. All of the outputs return low
about 800 ns after the longest delay. The pulse outputs,
AB and CD, go high for the time interval between their
corresponding delay channels.
t
CYCLE
t
BUSY
t
D
TRIG
T0
A
B
C
D
AB
AB
CD
CD
t
TRIG
t
ID
t
A
t
B
t
>5 ns
trig
t
>1 µs + longest delay
cycle
tID <85 ns
t
<800 ns + longest delay
BUSY
t
0 to 999.999 999 999 995 s
A,B,C,D
t
C
Stanford Research Systems
DG535 timing diagram
phone: (408)744-9040
www.thinkSRS.com
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