Atec DG2020 User Manual
The DG2000 Series of digital
pattern generators provide
digital designers with the
high performance tools
needed to evaluate advanced
digital semiconductors and
logic circuits. Whatever you
call your design process
– characterization, debug,
validation, or verification
– as a digital designer you
must have state-of-the-art
digital pattern generation as
you push the edge of the
technology envelope and race
to market.
Choose the Best Fit
The DG2000 Series is remarkable for the balanced
approach to providing the
appropriate class of instrument for a wide variety of
digital design applications.
Performance ranges from 1.1
Gbits per second to 200 Mbits
per second and from 2 to 36
channels. The table illustrates the principal specifications for members of the
DG2000 Series.
Critical Timing
The DG2000 Series is the
ideal solution for applications where you must characterize device or circuit timing
and amplitude margins. The
DG2000 Series is perfect for
simulating setup and hold
violations or conditions of
metastability. The DG2000
graphical user interface
allows you to quickly create
complex data patterns with a
few keystrokes on the front
panel. Use the advanced
sequence editing capability
of the DG2000 Series to insert
infrequent faults or glitches
in your data patterns to verify
device or circuit recovery.
The DG2000 Series is an
invaluable tool, allowing you
to simulate missing system
functionality while meeting
critical market windows.
With the introduction of the
DG2040, new capabilities are
available to control clock and
data jitter or modulate pulse
edges on a selective basis.
Copyright © 1999 Tektronix, Inc. All rights reserved.
DG2000 Series
Data Pattern Generator
Data Rate to 1.1 Gbps Tests Highspeed Logic Devices and Circuits
Data Pattern Depth to 256 K/channel
Speeds Characterization
Multiple Output Channels Increases
Flexibility
DG2040: 2
DG2030: 4 or 8
DG2020A: 12, 24, or 36
Control of Edge Timing (DG2040)
Permits Jitter Simulation in Serial
Data Streams
Precise Control of Output
Parameters Include:
Variable Output Delay
Variable Output Level
Variable Rise and Fall Time Control (DG2030)
Tri-state output control
(DG2020A, DG2030)
Large Display for Easy-to-Use Data
Editing
Create Complex Data Patterns with
Sophisticated Sequence, Looping,
Jump on Event, & Tri-state Output
Control
Characterize & Verify ASIC, FPGA, &
DACs
Evaluate Media Storage Devices and
Components (HDD, FDD, ODD, DVD)
Test Printer Engines or LCD Display
Drivers
Construct Logic Verification
Systems Utilizing Tektronix
Oscilloscopes or Logic Scopes
Use in-conjunction with TLA Logic
Analyzer to Provide Digital Stimulus
OUTPUT DATA
Data Rate –
DG2040: 0.1 bps to 1100 Mbits/s.
DG2030: 0.1 bps to 409.6 Mbits/s.
DG2020A: 0.1 bps to 200 Mbits/s.
Clock Period Jitter –
DG2040: < 30 ps p-p at 1100 MHz. Typical.
DG2030: < 50 ps p-p at 200 MHz. Typical.
DG2020A: < 50 ps p-p at 200 MHz. Typical.
Data Depth –
DG2040: 360 to 256 Kbits (1 increment).
DG2030: 90 to 256 Kbits (1 increment).
DG2020A: 64 to 64 Kbits (1 increment).
Data Width –
DG2040: 2 bits (complementary outputs)
via front-panel SMA connectors.
DG2030:
Standard: 4 bits via front-panel BNC
connectors.
Optional: 8 bits via 4 front-panel, 4
rear-panel BNC connectors.
DG2020A:
Standard: 12 bits.
Optional: 24 or 36 bits.
SEQUENCER
Maximum Number of Blocks – 256.
Maximum Number of Sequence Steps –
DG2040: 4000.
DG2030: 4000.
DG2020A: 2048.
Block Repeats Per Line – 1 to 65536 or
infinite.
DATA AND CLOCK OUTPUT (DG2040)
Data –
Output:
Standard: Ch 0 & Ch 1 at front-panel
SMA and Clock at rear panel SMA
connectors.
VOH: –0.875 V to +3.5 V into 50 Ω.
VOL: –1.125 V to +3.25 V into 50 Ω.
Rise/Fall Time (20 to 80%): < 150 ps at
1 V
p-p
and 10 MHz.
Delay Function:
Delay channel: Ch 0 or Ch 1.
Delay time: –1 ns to +2 ns.
Delay resolution: 10 ps.
DATA AND CLOCK OUTPUT (DG2030)
Data –
Output:
Standard: Ch 0 to Ch 3 and Clock at
front-panel BNC connectors.
Optional: Ch 4 to Ch 7 at rear-panel BNC
connectors.
VOH: –1.25 V to +3.5 V into 50 Ω.
VOL: –1.50 V to +3.25 V into 50 Ω.
Rise/Fall Time (20 to 80%): Variable at
amplitude range from 2 V
p-p
to 5 V
p-p
.
Variable Range: 2.1 ns to 4.7 ns at
3.00 V
p-p
– depends on amplitude
setting.
Value in Fast: 0.25 V
p-p
to 1 V
p-p
; 500 ps.
1.7 ns at 3.00 V
p-p
.
Delay Function:
Delay channel: Ch 0 to Ch 7.
Delay time: –5 ns to 18 ns.
Delay resolution: 20 ps.
Clock –
Amplitude: ±5% of setting ±50 mV at 1 MHz
clock.
Rise/Fall Time (20 to 80%): Variable at
amplitude range is 2 V
p-p
to 5 V
p-p
.
Value in Fast: 0.25 V
p-p
to 1 V
p-p
; 500 ps.
1.7 ns at 3.00 V
p-p
.
Accuracy: ±10% of setting ±500 ps.
AUXILIARY INPUTS
Clock –
Frequency:
DG2040: 10 MHz ± 0.1 MHz
DG2030: DC to 409.6 MHz.
DG2020A: DC to 200 MHz.
Trigger – Front-panel BNC connector.
Level: –5.0 V to +5.0 V.
Resolution: 0.1 V.
Polarity: Positive or negative.
Hold Off:
DG2040: 100 ns minimum.
DG2030: 100 ns minimum.
DG2020A: 500 ns minimum.
Event (DG2040 & DG2030 only) – Rearpanel BNC connector.
Threshold Level: –5.0 V to +5.0 V.
Resolution: 0.1 V.
Polarity: Positive edge.
Minimum Pulse Width: 100 ns.
Inhibit (DG2030 only) – Rear-panel BNC
connector.
Mode:
Off: Always enabled.
Internal: Controlled by Ch 0 signal.
External: Controlled by inhibit input
signal.
Both: Controlled by Ch 0 or inhibit input
signal.
Threshold Level: –5.0 V to +5.0 V into 1 kΩ.
Resolution: 0.1 V.
AUXILIARY OUTPUTS
SYNC –
DG2040: Rear-panel BNC connector.
DG2030: Rear-panel BNC connector.
DG2020A: Front-panel BNC connector.
Level:
VOH, 2.5 V into 50 Ω; VOL, 0 V into 50 Ω.
EVENT –
DG2040: Rear-panel BNC connector.
DG2030: Rear-panel BNC connector.
DG2020A: Front-panel BNC connector.
Level:
DG2040: Vhi, 2.5 V into 50 Ω; Vlo, 0 V
into 50 Ω.
DG2030: Voh, 2.5 V into 50 Ω; Vol, 0 V
into 50 Ω.
DG2020A: Positive TTL pulse, 50 Ω.
CLOCK –
(DG2020A only)
Rear-panel SMB connector.
Level: 1 V (typical) into 50 Ω.
PROGRAMMABLE INTERFACE
GPIB: ANSI/IEEE488.2-1987.
RS-232C: 19.2 kbps, D-sub 9-Pin
connector.
page 2
DG2000 Series
Characteristics
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