Atari SM194 Technical Manual

SMI 94

Technical

Manual

Februari

199

Subi

ect

TABLE

CONTENTS

OF

Section

Scope

General

Electrical

Display

Description

Characteristics

Performance

Controls

Options

Mechanical

Description

Environmental Performance

Agency Compliance

Interface

Theory of

Operation

Appendix:

Figures

Block Diagram

Trouble Shooting Chart

Schematics

'

1

2

3

4

5

6

7

8

9

10

11

\

-

^

VCX

)

1.0 SCOPE

SERIES

MONITORS

C

This

of horizontal

document

satisfy

2 . 0 GENERAL

monitor

The

with a

available.

monitor can

The

frequency

frequencies

3.1

The

specific

typical

Other

sales or

OEM

3 .

ELECTRICAL

Power Supply:

Input

Power

Power

Inrush

describes a monitor series that

scan

requirements

DESCRIPTION

series is supplied with a

degree deflection.

114

be custom configured

from 32 KHz to 128

from 49 Hz

values

monitor

scan rate

operating at a 66 KHz horizontal scan rate.

information can

application engineering.

CHARACTERISTICS

Voltage

Frequency

Current

frequencies

wide variety

a

in

and includes

20-inch diagonal

(15",

17"

for

KHz, and for vertical

to

120 Hz.

included in

this document are

be obtained

90 to

47-63

64 Watts

40 Amps

60 Amps peak at 220 VAC

137 VAC

Hz

peak at

covers

a

options

of

applications.

24"

and

CRT's

any horizontal

for a

by

consulting

or 180 to 264 VAC

VAC

120

range

to

tube

are

scan

field

)

3

3.2.1

Horizontal Sync:

Polarity Negative, edge

Signal Level
Signal rise/fall

Pulse

Width.

(Positive

TTL

TTL

0.5uSec

total

Optional)

(min)

horizontal

time

Input Impedance typical 100

Frequency

Blanking

32 KHz

3.0uSec

to

Ohms

128 KHz

(min)

to 50% of

scan

TYPICAL:

Vertical Timing

4

3.2.2

Vertical Sync:

4 .

3.2.3

4.1

DISPLAY

Input

Polarity

Signal Level

Signal Rise/Fall

Pulse

Input Impedance

Frequency

Blanking

Video

Polarity

Signal

Input Impedance

PERFORMANCE

Conditions:

Character

Brightness

Contrast

Width

Signal

Negative

Optional)

edge

TTL

TTL

Input

40-400

typical

49 Hz to

lace

450

Requirements

uSec

100 Ohms

120

Optional)

uSec(min)

Positive is

(Negative

Bit ECL

1

Typical 75 or 100

<«§»

At raster cutoff

White level

should be set to result

Foot-Lamberts
lent setting.

Optional)

Differential

input video

in P4

(Positive

'Hz

(Inter

white

Ohms

in

or

equiva-

30

4 .

4.3

4.4

Viewing Direction

Viewing Distance
Ambient

Supply

Warm up

Display

Video

Rise/Fall times

Horizontal:

Video blanking 3.0 uSec

Horizontal Scan Delay

Vertical:

Video

Temp.

Voltage

time

size

'

blanking

Along the CRT neck axis

inches

18

degrees

25

VAC

120

minutes

20

14 x 11

nsec Max.

3.5

C

max.

inches +/-

(10%

Horizontal (Min.

0-4

uSec

Adjustable Phase

Control

uSec

450

5

Vertical

0.1"

-

90%)

(Min.)

-

=

A

-B

0.07

inches

max

4.5.5 Center

0.07

Bow:

inches

max

4.5.6

Linearity

Resolution:

4.7 Light

4.8

Display

4.8.1

4.8.2

Using

the

above pattern,

better than

horizontally.

1300 Lines min. at

P104 phosphor and

Transmission glass

Output: 3 0

Stability:

Jitter:

Jitter and Swim resulting

Generated

interference

frequency

Interference

sources

inches of

Turn on

Aft$r

the

inches

minute warm-up,

around"

a 10

-display shall not

the

vertically and better

7%

linearity shall

10 Ft-L

standard

Ft-L min. with

Sources:

0.005 inch max., down

of

of 47 Hz.

from

shall not

max settings

Radiated

other

produce

jitter on the display.

Drift:

minute warm-up,

drift

in any

raster.

the

direction.

display

the

that

48%

from

Monitor

power

to a

nonsynchronous

more

the

than

periphery of

more than 0.10

During the

shall

not "wrap

0.003

be

9%

line

10

4-8.3

High

Voltage Regulation:

5 . 0

4.8.4

CONTROLS

5.1

User:

Brightness

Power

Contrast

5 . 2

Internal

Contrast

Brightness

Horizontal

Horizontal

Horizontal

Vertical

Vertical

G2

Static

Vertical

Horizontal

Bias

With

an

all

shall not

going from 2 Ft-L

(ref. P104

Black

When

Level Stability:

changing

Average Picture

reference

%.

2

Switch

(Available on Grey

Centering

Size

Linearity

Size

Linearity

Focus

Dynamic

Focus

Dynamic Focus

white

change by

phosphor)

the data

Level

black

(Phase)

level

active

to 3

will stay

Scale

display-,

more

than

0

Ft-L light

pattern

(APL) to

Units)

dimensions

0.5%,

output

from

100% APL,

constant

when

5%

the

with

6 . 0 OPTIONS

6

. 1

Video

TTL 1
ECL 1

Analog

. 2

Phosphors

6

P104

All

to 3

to

Bits

3 Bits

Composite

Video,

standard

phosphors available

RS343A

options

as

6.3 Anti-Reflection Treatment:

Fine

Bonded
available

6.4 Orientation Format:

Landscape and

Etch or Polished is standard

quarter wavelength optical

as

options

portrait with

Short dimension

6.5 Controls:

Remote contrast

Power

LED

6.6 Power:

ECL

Supply:

indicator

-10.0VDC nominal

coated

horizontal

500 ma

§

panel

scan

in Long

or

)

10

7.0 MECHANICAL

BASE:

DESCRIPTION OF OPTIONAL

CABINET

WITH

TILT-SWIVEL

8.0

Overall Height
Overall

Overall

Rear

Width

Depth

Panel

Dimensions

Weight

ENVIRONMENTAL

Operating

Storage

Temperature

Temperature

Humidity

Operating

Altitude

Nonoperating

Vibration:

Sweep 5-500-5Hz:

from 200

then 15

Shock:

vertically,

20g

wave with pulse width

14.5"

17.8"

15.0"

13.0

'36

PERFORMANCE

(in

X

Lbs.

i

box)

Altitude

0

to 500 Hz.

max from 0 to 200

.

5g

Duration of sweep

minute dwell on peak

longitudinally

ll-15mSec.

3 68mm)

(

(452mm)
(381mm)

9.5"

5 to 55 degrees

-40

5% to 95% noncondensing

(330 x

(16.4

to 65

241mm)

Kilograms)

degrees C

10.000 Ft. max.

40.000

resonant

and

Ft.

max.

Hz,

is 15

at

0.55g.

laterally,

C

0.33g

max

minutes;

half-sine

9 .

AGENCY COMPLIANCE

The unit is

TJL478

CSA C22.2

IEC

designed to meet the following

Fourth Edition

No. 154

380,

VDE 0806 GS

cabinet

CFR, Subchapter J,

DKHS

FCC

21

Class

B,‘Part

requirements:

Listed/Recognized

Mark, and VDE 0871

X-Ray

*

15 in

cabinet

11

Certified

Class

B in

10.0 INTERFACE

Power

AC

In:

10.1 Input Signals:

Connector:

9

Typical

ECL

1. ECL Video

2. ECL Video Return (GND)

.

3

4.

5. N/C

6.

7.

8 .

9.

Sync

H

V Sync

(Not) Video

ECL

(Not) Video Return

ECL

Sync

N/C

Return

(GND)

CEE-22 Receptacle

Interlock

Subminiature

Pin

Assignments

Pin

TTL

N/C

H

V Sync
N/C

TTL

(GND)

H Sync

V Sync

N/C

D

Video

Sync

Video

or

TTL

Return

Return (GND)
Return

AC

(GND)

(GND)

Safety

NOTE : Other

10.2 Analog Input:

Analog Input: BNC

Assignments readily

Pin

-

RS343A

accommodated

Levels

. 0 THEORY OF

OPERATION

11.1

i. Sync Processing

Deflection

deflection

The

processes sync

i)

provides horizontal

ii)

provides

iii)

provides

iv)

provides

v)

provides

vi)

Board

The 74LS221 U4

Schmitt

the inputs and

in

trigger

JR1/JR2 are

The TLC555

same mode as U4

the

U1

The leading

U4 .

The end of

delay is needed

time out of Ul

and

data

the
set

R12.

video

by R37

The PLL

centering

in

,

inputs. Noise is reduced

provided to select the active edge.

is a level triggered

edge

time out

to

triggers

potentiometer V10,

the raster. The

and

R68

board

vertical yoke

a sync

the

spot burn

is a dual non-retriggerable one

does several tasks;

yoke

deflection

deflection

pulse

required

to the power

focus voltage

protection

supply

by the

the non-retriggered

action. Jumper

timing device used

of horizontal

sync triggers the

triggers the TLC555 Ul. The

delay the

then centers

signal

for a duration

Q1

this pulse on

a full line. The

determined

flyback.

should

be set to

amount and range of

V10.

shot

with

hysteresis

blocks

in

one

shot

second

end

of

by C18

The

center

delay

is

Vertical

sync is

noise immunity,
allow some delay

Horizontal

ii.

phase locked

The

switch

to the

Deflection

timing pulses

generator.

The delayed

pulse width

coupled

MC13

to

91. This

samples

sync 'from Ul

set

PLL, U2. The sync is fed

the

sync pulse determines when

the

ramp waveform generated by

available to pin 4

ly coupled to

positions

generated

on

at pin

U2.

the ramp

fed through

to offer

the option of inversion

for interlace

loop

'

(by

of

5. The

used

is

is

R12

U2. The ramp

the

If

at

error

one shot

the

requirements.

to

synchronize

from the

computer or signal

buffered through

and

C18)

and

waveform

sampling

pin

4,

voltage

occurs

’error

an

connected

is

to get

Ul

the

Q1

capacitively

is

into pin

(MC1391/PLL)

U2

the yoke

capacitive-

is

at

voltage

better

and

to

horizontal

with

its

3 of the

and

different

is

to pin

7

through a

therefore

frequency

controls

pass

low

filter. Pin 7

the error voltage

difference between the

the oscillator.

See

the

is

created

flyback

figure 1 for

timing input

by

the

and

phase

sync

waveform

of

U2

or

signals

details.

The free run

Cl. The duty cycle of

The

Q3

and

output is

The

.

shuts

The switching

through

Q7

turns

On the

off.

right

frequency

pin 1

FET

off

a current transformer. When

is normally

Q3

Q3

of

Q3

of

which

drives the

The Baker's clamp D23 is an optional

hand half of

conducting current through

This current is provided

C25

supply

(

C44

voltage. The

flow from

the left

The flyback

yoke to

the

length of the

The

"S"

linearity

which has

,

)

ground

hand

through the

half

of

capacitor

ground.

flyback

shaping capacitor(s) C25

since the

by

a

damper diode DIO allows

the

(s) C2

This

pulse.

CRT

U2

U2

determines

the deflection

the

charge approximately

screen.

4

component determines

face has a larger

determined

is

determined

is

the

on until

U2

pulls

horizontal output

Q3

the screen,

correction

"S"

deflection

(C43)

connects

(C44) is used

yoke to

by

by

drive

is

transistor

yoke to

the

curvature than does the deflecting electron

capacitor (s)

linearity.

voltage plus

of 35

C25 is

size

to 90 volts

reduced this

the outside

of

corrects

There is

parabolic voltage

a

the outside versus center

a

depending on the

parabola will increase,

characters with respect

DC voltage equal

with a peak

setup.

to

If

to

characters

VI,

R19

R16.

and

of the

the gate

transistor

turned

component.

-ground.

capacitor

equal to

current

C2

5

hot side

the size

to correct

radius

beam.

of

the

to peak

the value

reducing

the center

and

R17

FET

low

on,

Q7

is

Q7

(s)

the

to

giving

of

and

of

The

screen

supply

value

of

the

Left

coil

current.

the

saturable coil will change

direction of

start of

20%

versus right

L2.

This

Like the

yoke

will reduce

linearity is

is a saturable coil

size coil,

the

any inductance

size of the

inductance

a

current

trace

'

flow

the

through it. In

linearity

of the yoke. By the center of

coil inductance has decreased to

remains

it

inductor should be

the picture are the

for

the

rest of

adjusted so

same size.

14

controlled

in

with

the path

in series with

the linearity

the yoke

of

picture. This

with amplitude

this case at

coil has an inductance of

the trace, the linearity

about

5%

the trace.

the

right

the yoke where

of

This

left

and

variable

sides of

and

the

Horizontal

LI.

These

connected

yoke.

centering

two

from the supply

conjunction with Dll and D12

In

connected for

serves

the

slug is in

left half. If

the

average current

If there is

net flow

position

an

causing

on the screen.

done

is

'variable

inductors

the right half

with the dual

are in one

voltage

of a trace

the two

inductors

to

the center, or removed

flow is zero

imbalance

the picture

and

inductance

in

the picture

(raster

variable

unit and

the

cold

one

and

are

completely)

is not

then

there

included)

coil

side

of

inductor

the

other

equal

then

,

shifted.

will

to

shift

are

the

is

(when

the

be

a

iii.

Vertical

The TDA1670

providing

deflection.

oscillator, ramp

doubler and

The

oscillator

Deflection

incorporates all the necessary

yoke with the current

the

Incorporated

generator,

in

silicon

voltage

power amplifier.

is an integrator (pins

required

is

threshold comparator which switches pin

allow the charging of C8. D3 allows

discharge

ramps to

pulses come in on pin 5.

The

ramp

controlled by

from pin 9 to

linear ramp is

pin 7

at a much

The
pin

through

power amplifier,

10 with

generator is made up of

current .through

ground. The slope and thus

adjustable

V3

lower impedance.

the current ramp

stabilize the high

from

CIS,

Voltage

pin

and the

which represents yoke current

the input of

ce.

through the yoke,

1,

current

the amplifier to be

have

. This ramp also appears

with input on

adjustable

See

figure

pin

setting

by

slopes.

2.

a current

and the

7,

the current

pin

12,

through the yoke.

gain power

amplifier.

the DC blocking

sampling resistor

compared with the referen-

is then

functions

for vertical

a

synchronizable

regulator,

4 to

6

3)

high

the

Vertical

voltage

and

or low

charge

a two

sync

generator,

capacitor

the size

pulled

buffered on

sums

the

of the

from

pin 10

ramp on

R31 and C14

Yoke current flows

capacitor

R33 to ground.

back to

fed

for

to

and

C12

output stage of the power amplifier is

The

volt supply during the trace, and by

25

generator circuit during

turns off the

output stage

lower

is thermally protected by sensing

output stage to start flyback.

temperature and shutting

the retrace.

off the current source

stage.

15

supplied

The

by the

the flyback

internal clock

The power

junction

the

the power

of

The

DC bias

R33.

Capacitors C16 and C15 find

voltage. This

the

buffer

point is maintained

voltage

amplifier

Any difference in

-point

the power amplifier to self-adjust.

of

then

is

where

these two

the divider

by

the

back

fed

it

compared to

is

voltages causes

R34, R32

average

into the

a

the

and

output

input

of

reference.

DC

bias

In

order

to obtain

sufficiently short

voltage greater than that

applied to
flyback only,

equal to double

capacitor C9, up

then sets

retrace,

Vertical linearity

ments. The ramp

across
pin

R33

7 of

Vertical "S"

with R3 8

integrated becomes

U9 .

pin
The

This

7 of the

parabola

modulator.

develop a

C17

Vertical centering

or sink.

then

If

the picture

V5

is

picture will

be set to

the yoke. The

supplies (to the

this

thus

the

capacitor

doubling

supply

to the supply

the

adjustments

and

from

the

pin

results

the TDA1670.

is done by using the TL43T (U9) and

as

shaping

integrator.- The vertical ramp

an

the vertical parabola on the output

parabola is fed back to the vertical size

TDA1670

is also used

and

compensates

Diode D6, resistors

bias

V5 is adjusted so that it is a

If

adjusted so

move down

center

voltage.

is accomplished with a current source

(raster included) will

that it provides current, then

the screen.

the

data, not the raster

required

during

flyback

power amplifier)

voltage.

voltage

on

top

the power

of

available voltage.

interact

10 is

are

subtracted from the

back

fed

for "S"

drive the vertical

to

R38,

R39, R40 and capacitor

move

Potentiometer V5

flyback

times,

scan

generator,

a voltage

Pin

15

during

charges

trace

supply

with size

to

the size

across

distortion.

current sink,

up the screen.

on the screen.

,

must

during

during

adjust-

ramp

input,

C21

R3

input,

focus

the

should

a

be

a

and

3

of

-

Power Supply

iv.

The

power

deflection in

accomplished

supply is

order to reduce the

by

horizontal flyback

blocking

v. Focus

Each

inductor

Modulation

section

of the

voltage. The

Sync

synchronous with

sending a stepped

pulse

T2.

by

sampling

CRT screen

center

the screen

of

16

switching

down version

the

focuses

may

the

noise.

horizontal

pulse

a

at

require

This is

the

of

on the

different

several

Horizontal

LI.

These

connected from

yoke.

connected for

serves

the

slug is in

average

there

If

net

flow

centering is

two variable inductors are

conjunction with Dll and

In

left half. If

the

current

is an

imbalance

causing the

the supply

the

the

right

center,

flow is zero and the

position on the screen.

done with the

voltage

half

the

or removed

in

picture

of

two

inductance

(raster

dual

in one

to the

D12 one

trace

a

inductors

completely)

picture

then

included)

variable

unit

cold

side

inductor

and the

are equal

is

not

there

and

of

then

,

shifted.

will

to

coil

are

the

is

other

(when

the

be

shift

a

iii.

Vertical

The TDA1670

providing

deflection.

oscillator, ramp

doubler

The

and power amplifier.

oscillator is an integrator

Deflection

incorporates all the necessary

yoke with the current

the

Incorporated

generator,

threshold comparator which

allow

discharge ramps

pulses

The

controlled by

from pin

linear ramp

pin

at a

The

pin

the

charging

to have

come

in

on

ramp generator is made up of

current .through

9 to

7 through

much lower

power

10 with the current ramp through

amplifier, with input on

ground. The slope

is adjustable by setting the

V3

.

impedance.

stabilize the high gain

from

C16

pin

and the current sampling resistor

,

Voltage which

the input of

ce.

through the yoke,

1,

represents yoke

the

of C8.

adjustable slopes.

pin 5.

This ramp also

See

power

amplifier

required

in silicon is

voltage

(pins 4 to

switches

D3 allows

figure

pin

pin 6

2.

a current

and the

7,

and thus the

appears

pin

12,

the yoke.

amplifier.

the DC blocking

current is then

to

be compared

functions

for vertical

a

synchronizable

regulator,

and

3)

high or low

the

charge

Vertical

generator,

capacitor C12

size of

current

pulled

buffered on

sums the

R31 and

Yoke current

R33

to

fed back

with the

for

voltage

a two

to

and

sync

the

from

pin 10

ramp

on

C14

flows

capacitor

ground.

to

referen-

output stage of the power

The

volt supply during the trace, and by

25

generator circuit during

turns off the lower output

output stage is thermally protected

temperature and

shutting off the current source

amplifier

the retrace.

stage to start

by

stage.

15

supplied

is

The

flyback.

sensing

by the

the flyback

internal clock

The power

junction

the

the power

of

hundred volts

while the

left and right require more.

less than the

top or

bottom

of

the

screen,

To achieve the

modulated

vertical

common

base

with

parabola

both a

configured

The collector of

best focus over

vertical and horizontal

developed

Q5

then

Q5

at U9

which

has a high voltage

all,

is a high voltage

the

drives

the

vertical frequency.

The

horizontal

on

"S" capacitor

deflection

added to the

focus parabola

C25. The

current at C25

vertical parabola

developed

is

parabola

is stepped

at

developed

up

to

Q5

provide

voltage.

The

autotrans former

T3

accommodate different

focus potentiometer

vi.

High

the deflection circuitry, horizontal

If

Voltage

V6,

Shut

is

,

capacitor waveforms

"S"

sets the

Down/Spotbum

multitapped

a

focus

DC

Protection

voltage.

or

functioning at required frequencies, the-

supply will be

at the horizontal

which will

down

shut

pin

down. Likewise,

on the

shut down.

provide a positive voltage

vertical rate C3

in

high

voltage shut down.

If

rate, C3 9

power

8 will charge up

supply causing

if

Q8

will

does

Q9

does

charge

not

and

not receive-

up and turn

to the remote

the

receive

turn

focus

voltage

signals.

emitter

of

amplifier.

parabola

from

the

from

through

voltage

the

T3

the

yoke

focus

transformer

and CRTs.

vertical,

The

stops

high voltage

a

signal

Q10

shut

high voltage to

a signal at

on

Q10

resulting

the

is

The

the

of

and

to

on

11 . 2

11.2.1

The

operating

switcher with

output filter

used.

Power Supply

Low Voltage Supply

design utilizes a

current-mode

in

outputs

chokes

fast transient response of the

The

maintains picture

protects the

The input

into

a crudely

which powers

configured

is

220V

110V. There is a

of

line, and

operation.

switeher against

rectifier section converts the AC

the switching

as a fullwave

as

discontinuous

resulting in a

which

are needed and slower

integrity.

track well.

Very

fast

short circuit.

filtered

unregulated DC

and

regulator.

bridge

a voltage doubler when

header

available to

flyback

multiple

Small

diodes can

control

current

line

The input

when

operated

. operating

select either

topology

output

or no

be

loop

limiting

voltage

voltage,

section

from

from

mode

reduce noise transmission to

To

low

pass filter isolates

is reduced by

X and Y

transformer.

and

the

switcher. The

capacitors

from

and

the

power

conducted

a

common

line,

noise

mode

a

3

842

(Ul)

modulator. It consists

amplifier, current sense comparator,

lockout and

under-voltage lockout

adequate to

is an integrated

,

output MOSFET

an

circuit insures

make the 3842 fully

current

of

an oscillator,

driver stage.

operational

mode

under-voltage

that

enabling the oscillator, voltage reference

stage. Turn-on turn-off are

and.

oscillations ' during

10V respectively.

power

The

sequencing.

The oscillator consists of a

the

ground.

internal

capacitor

sink and starts

frequency is

3842 can also

achieved

the horizontal flyback

capacitor

running

less than the

5V reference to pin 4 and

When the voltage ramps

current sink

a

1.0V

to

the

pulls

level. This level releases the

next

cycle.

approximately equal

be synchronized to

capacitively coupling

by

pulse

CIO.

Noise immunity

frequency of the oscillator is set

clock frequency.

fixed

6V hysteresis

pull

a timing capacitor

up

down,

The

to 1/.55RC.

an external clock.

through C33

internally

up resistor

to 2.8V

discharging the

free

a stepped

is enhanced

pulse

error

Vcc

before

or

output

at 16V

prevents

Rll,

on

pin

running

down

to the

if the

to be about

width

The

is

Vcc

from

to

an

4,

timing

current

oscillator

This

signal

is

of

timing

free

20%

output stage of the 3842

The

output

capable of

operating

has a single

to

1A

peaks

totem-pole

and a 200

mA

average current.

3842

controllers

utilizes a current

inherently keep

transistor's current

comparator

the primary

desired level,

which shuts

winding

as

prescribed by

Ql.

of

sense

Pin

off the

the

power

comparator.

.

close

3 is connected

output

watch over the

when

the

transformer reaches

the error amplifier.

Current

a

to

voltage

current

way the controller will only allow the needed amount

power

to be

Current

controllers which compare the

against

control

power stared in

stored

mode

control differs from

the output transformer.

in

the oscillator's voltage

of

on-time,

the

which

transformer.

does

error

ramp.

necessarily

not

most

pulse

width

amplifier's output

This results

mirror

mode

pass

in

the

This

of

in

the

The current

monitoring

output is

core

saturations should be

sense

current limit.

comparator

also

If

terminated. Therefore,

detected before

serves

the

dual

purpose

pin 3 rises above

output

short-circuits

destroying

IV

Ql.

of

the

and

The error

on

pin

reference

is compared

amplified

amplifier of

non-inverting input

2,

the

and an output on pin 1. The voltage

to

and fed to

2.5V. Errors

the

pin

compensated by an RC back

internally dropped by

fed to

the error

the current comparator. At

amplifier output

1.4V and divided by

current sensed at pin 3 will

amount

therefore, the

In this

the secondary

voltage to a

output

voltage is

energy

of

power at

application, an operational

side of the

regulated reference voltage.

compensated by R24
optocoupler

3842

enough

draws very little current

power from the line bleeders

charge C8 to
switching

the

10V

to the error amplifier of the 3842.

the

begins,

shut-off

stored in the

the

switcher, compares

amplified by U4

and C24. Error

'

16V needed to start the

Vcc

falls quickly but before

level the auxiliary winding

3842 has

tied to an

where

1

to

pin 2.

sets the level

ramp up to, thereby setting

output.

in start-up mode.

the

output

in

they

the current

power

amplifier

The output is

.

current is

transformer provides the required power.

inverting

are

This

R2 and

input

internal

voltage

on

2.5

pin

are

frequency

error voltage

3 before

being

comparator,

at which

transformer

U4, located

single

a

Any

output

error

frequency

fed through

There

to

R3

slowly

switcher.

reaches

it

on the

power

V

2

is

the

the

and

on

in

the

is

When

As the 3842

This

current

sense

enough

off

from

allows

ramps up with

resistor R7 also ramps to

power has been stored via

Ql.

As the voltage

the main power transformer

different

voltage

Ql,

starts a cycle,

current

to flow

time,

outputs.

clamped

is

it turns

the

in

the voltage

point where

a

the comparator,

on

flies upward, power

Ql

Tl

Primary ringing which

by D2. Currents from

windings are rectified and filtered
output

11.2.2 High

The

The input supply

regulated

down and

operational amplifier U4

voltages.

high

Voltage

voltage

down to 15V

Supply

power

voltage

supply

by U3 .

is

a

25V

is

DC.

This regulated 15V

used as the reference voltage

.

The inverting input

19

on transistor

primary

.across

of

the

Ql.

Tl. As

current

U1 determines

and turns

is dumped

through

to

diodes into the

could

the

secondary

over

create the desired

resonant mode regulator.

The

25V

input

input

is

divided

of

is the

is

the

anode. P0T2 adjusts

feedback from

for the non-inverting

In addition

developed from

the

to

the

the

same

the

reference

input and thus the anode

anode voltage, 1200V

transformer.

voltage.

and

-120V

voltage

are

The remote

if the

voltage at the base of

shutdown will

shut

the high voltage

Q5

reaches

approximately

supply

down

6V.

11.3

1BIT

ECL'

Video

The

main

functions of

the

IBit ECL

the cathode and arc protection. The

voltages

are

coupled through .the

video

ECL

board

rest

board

protected, but are not modified by the video

The ECL

and R4

R3

are

D4

10 and

and 15

The

When

When

is a peaking

LI

signal

are the termination resistors

clamp diodes.

and the

14,

of Ul. Ul, MC10H125, is an ECL to

output of the Ul

turns on,

Ql

turns

Ql

turn on and off

ripple or

Any

will

probably show

necessary

Cll,

C12

,

other noise on the voltage

to

C7

C8 and L2

,

Arc protection is provided for Gl,

Arc

gaps are used for Gl, G2

for the

cathode. These gaps provide

voltage across them

the gap is

of

received by U1 through

is

inverted

The

non-inverted

off,

inductor

drives

Q2

Q2

Ql,

turns

off pulling

turns on

for

faster during it's

on the screen

filter

the supply

and G4 and

reaches

connected

to

a

the

Jl-2

and

signal

input goes

goes

to

TTL

which drives

the cathode

pulling

the

amplifier which

the

transitions.

driving the

as shading.

voltage, and

G2, G4

a short circuit

certain

and

a gas arc gap

threshold.

grid it is protecting,

the other side is connected to the arc return

arc

return

connected directly to the CRT

ground

separate

is

from the signal

dag.

are

driving

of

the

and

board.

, 3 .

Dl,

to pins

pins

D2,

Rl,

3,

D3

2, 6,
7,

translator.

the cathode.

cathode

high.

helps

cathode

This makes

done

is

the

cathode.

if the

One side

while

ground.

ground

and

grid

arc

R2

and

11

low.

Q2

it

with

used

The

is

When

fires

thus

the

anode arcs

.

to an element of the

creating a short circuit directly

protecting the circuitry.

21

CRT gun,

back to the

the gap

CRT dag,

11.4

Analog

Video, Low Bandwidth

The

low

about 90MHz.

bandwidth

It

analog

uses

differential amplifier-

sync stripper,

amplifier.

similar

The

to the 1BIT ECL

sync stripper

The analog board also

sync separator,

supporting circuitry.

the

sync

signals and to

further processing.

Some

the

setups

video

stripper and only

and R23

however

6 .

in

composite

sync separator

The

the composite

exclusive

the

sync.

C223 .

composite sync and

The

Composite sync is

require

signal.

a

These systems

need

Note that

case of R236

video is used

separates the vertical sync signal

signal. This is accomplished with

gate, U204A.

OR

horizontal rate is filtered out by

The

output

is a

used

video

the MC10115, (U201

board has

The general

video

consists

This

provide

board.

of

circuits' function

composite

a

separate composite

would

R23

proper

6 and

termination supplied by

R237

are optional

optional applies to

R236

should be a lk

One

input

the other

to

negative vertical sync signal.

the horizontal sync signal.

for

circuit

dc

restore

provides

Q202,

not require

is

tied directly

a

filtered composite

a

bandwidth

and

U202)

consists

and

arc

protection

Q203 and

is to

sync

signal

sync signal

components,

it's value.

ohm

resistor.

R23

of

quad

of

video

their

remove

for

from

a

sync

R237

If

from

an

to

4 and

a

The dc

voltage level

voltage level is

reference

of the horizontal sync

turns on

reach the

is fed to U202

The video

08 and Q209

Q2

U202

signal and amplify

level and therefore

together act

the gain of

current- draw

restore circuit

represents

voltage (set

Q205

and allows a sample of

operational amplifier U203B.

and U201.

amplifier circuit consists of

and

compare

the

as

the

through

sampled

their

black level

the

the gain. The

another

circuit.

cathode.

Pin 1 of

transistor

emitters

the

and pin

together

MC10115

2

(3,

gives

tells

black video level. The video

a

during

R238) by

by

is used to

the

blanking and compared to

video

U203B. The

shut

the cathode voltage

The output of

supporting circuitry.

set

by

U203B

difference. R211

outputs

differential

The

Q207,

which

the collector

is

14, 15)

the

remote

is

amplifier,

contrast

sets the

emitter.

the

differential

amplifier

trailing edge

04 off.

Q2

U201, U202,

to the

of

input video

sets the

U201

increasing

pot

swing

-

the

of

Tying

amplifier

what

This

U203B

Q207,

U201

and

input

and U202

sets the

on the

output

.

the

a

to

configuration

U201 are

versa. The

video

on)

,

lower,

tied to

levels,

which

resulting in a brighter

of

U201

and U202. The

the non-inverting inputs

larger the difference

between

the more U201 turns on (the

in turn

drives

Q2

on,

07

video.

inverting inputs

of

U202 and

black and

less U2

forcing

the

02

cathode

of

visa

input

turns

C20

or

11.5 Analog

The

135MHz.

signal

also

The

and

the

Some

This

separate

The

the

exclusive

the

The

C204

3

,

contrast

medium

It's

separation,

provides

sync stripper

their

supporting

composite

setups

allowed by JR101.

is

sync

sync

separator separates the vertical sync

composite signal. This is accomplished

OR

+5V

line

horizontal

output is a

used for the

C205

and

as does the

are

peaking

remote contrast

capacitors.

potentiometer.

R211 sets

Video, Medium Bandwidth

bandwidth

functions are sync signal

analog

DC restore

board

and

has

a bandwidth

video

stripping,

amplification.

arc protection for all circuitry.

consists of .U105A,

circuitry. The collector of

sync

signal

stripped from composite

have a separate sync

Composite

uses

JR101-B.

signal from

Q103

video

,

uses

Q104

video

JR101-A and

signal

gate, U103D. One input is tied

and the other to a filtered

rate

is filtered

out by

R13 2 and C118.

directly

composite

negative vertical sync signal. Composite

horizontal sync signal.

gain

of

about

sync

and

Q105

Q105

video.

signal.

from

with an

sync.

sync is

It

has

to

The

The trailing

causing

a

sample the

with

output

the

U102 is

a

the

RIO 6

the

used to

is

Clll and

internal

is

video driver amplifier

an LH2424

60V supply.

output,

controls

range of

select

set, so

C112

edge of the horizontal sync activates

positive gate

black

black level restore and

coupled to

The

pin

9,

the DC

the remote contrast

between

6 on

pin

are

signal

level

video

video. U101 is a

Q101

where it

U102.

driver amplifier. It operates off

input on pin 1

which is

level or

coupled

separate

U103 has

peaking

capacitors

23

to

5 of

pin

is buffered

is amplified and drives

to the cathode.

black

potentiometer.

composite

and

negative

a

.

Q106

U101 for U101 to

video

preamplifier

gain control. The

sent to

and

level.

R108

limits

JR101

sync.

going sync

JR102

output.

is

o

H

«

\h

A05I/AGD

FIGURE

moniTERm

cnRPDRaTion

Configuration

Customer

Viking VCX 91

Procedure

High.

Pot

Test

Bum-In 37.1

Visual

Inspection

Preliminary

Monitor

Display

High

Page Size 7.4

Page

Video Centering

Vertical Linearity

Horizontal Linearity 10.5

Pincushioning 18.4 Screen Facing Magnetic

Vertical

I

tote Brightness 11.2 Leave Remote

Highlinc/Lowline

Interim

Phase

Switching

Brightness

Display

Focus

Horizontal Retrace

Spot

AC

Power Cycling

120 Volt

Adhesives

Wrap-Up

Auxiliary

Setup

Setup 5.4

Orientation 34.1 LMLS-UL

Voltage 6.1 18,000

Centering

In Raster

Hold 23.3

ttence

Locked Loop Drift

Power Supply 20.6 Tap

Quality

Knll

Operation

Power

Check 47.1

DPI

Paragrauh

and Alignment

220V

38.2

4.1 Phillips

5.2 ECL

8.6

8.7

9-5 5%

12.1

17.1

13.3

14.5

16.1

15.6 Reference

27.1

19.1

36.1 5

26.10

24.0

32.1

Number

Part

Parameter Limits

Maximum Leakage Current

1/2 Amp

Use

video. Viking

Lowline

82.0V

Dead Center

Mechanical Center

Maximum

10%

265/198

0.10”

2-5

G2= 650 VDC ±30 Footiamberts

Reference

Use

Height 615V;

Cycles

90/135 VAC

you

Axe

-9

VDC

Specification

903-0279-03

Volt DC Load

9

72j±H, SPS

=

198 VAC; Nominal

VDC;

±1.0V,

Maximum

VAC

Maximum

Q1002,

Minimum

proud

on

pin

Tap

Cable with

±100 VDC

14.0"

Max.

For

60Hz

Display

Paragraph

Time

2.6 ±0.1(xsec (REF)

Hz

60

this

of

of 9D

5

10_50” ±0.10"

x

monitor?

11mA

2-5

North

Intensity

9

LED

=

220

Rev. B

VAC

±3£L

tal

alignment

Tim

in t.

Dot

Rate

Horizontal

Vertical

Step

All

OP

Set Moniterm

generator outputs

Rate 66.43 KHz

Rate 66.43

Codes

must be done on Moniterm

62.176 MHz

Hz

2

Arc

Zero Except:

video

to:

Video:

KJC.

pecial

S

9 1

Instructio ns

DPI controller

Quantum Generator

Horizontal:

Dots/Character

Total 104

Characters

Delay

Drive

Drive

Width

OP

3.1,

OP

4.1, OP

Sync:

Reverse

+,

H.

OP

7.1, OP

8.1.

sync

card.

Settings

Vertical:

9 Lincs/Character

Total

80 Rows

78

4

OP

Bit

3: Off Bit

H Sync:

Drive

Drive Width.

12.2, OP 14.1,

V

OP 15.2,

2z Off

sync:

13.3,

-

Delay

-

Bit 1:

OP

16

1000

60

60

3

16.3

On

Postbus

Telefoon

Telefax

70, 4 1 30

03473

77200

-

-

Telex

Vianen

EB

77272

76409'

-

Holland

i

training;,

De training

Moniterm

gegeven door:

werd

De moniterm monitor bestaat

SPS

-

unieke

op,

-

levert

110/220

waardoor

9*

25,

de

40

protection,

voeding automatisch op

Volt

High Voltage Power supply

-

levert 120

Deflection

en

board

1200 Volt

19

april

1989

Dennis Pederson {international sales)

Rich Rheault

uit:

Switching power supply

(technical support)

(SPS)

High Voltage Power supply

Deflection board

Video board

bij 220V op

110 blaas

een zekering

je

220V werkt.

Zorgt

-

voor sync en dus voor de

unieke bescherming tegen

schakelt

Video

board

Verwerkt

Anode-buis.

ontstaan,

geluid)

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wd^HiKii

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'roAdaMmcncu-vcftt&anfc

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signalen,

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bezwaar

•

cM

>

geeft

dit

typisch

moniTERm

cnRPciRaTion

Configuration

Customer

Viking

Procedure

High.

Pot

Test

Bum-In 37.1 Use

Visual

Inspection

Preliminary

Monitor Setup 5.4

Display

High

Page

Page Centering In Raster

Video

Vertical

Horizontal Linearity 10.5 10%

Pincushioning 18.4 Screen Facing Magnetic

Vertical

I tote Brightness

Highlinc/Lowlinc

Interim

Phase

Switching

Brightness

Display

Focus

Horizontal

Spot

AC

Power Cycling

120 Volt

Adhesives

Wrap-Up

Auxiliary

Setup

Orientation 34.1 LMLS-UL

Voltage 6.1 18.000

Size 7.4

Centering

Linearity

Hold 23.3

ttence 17.1

Locked

Loop Drift 133

Power

Quality

Retrace

Kill

Operation

Power

VCX 91 DPI

Paragraoh

Supply 20.6 Tap

Check 47.1

and Alignment

220V

3812

4.1

5.2 ECL

8.6

8.7

9.5

11.2 Leave Remote

12.1 265/198

14.5

16.1 Use Reference Display

15.6 Reference

27.1 Height 615V;

19.1

36.1

26.10

24.0

32.1 Are

Part

Parameter Limits

Maximum Leakage Current

1/2 Amp

Phillips

video. Viking Cable

Lowline

82.0V ±1.0V,

Dead Center

Mechanical

Maximum

5%

0.10”

2-5

650

G2=

Cycles Minimum

5

90/135 VAC

you

-9

VDC

Specification

Number

72uU.

=

198

VDC;

Maximum

VAC

Maximum

VDC,

Q1002.

proud of

on pin

903-0279-03

Volt DC

9

Tap

SPS

VAC;

±100 VDC

14.0"

Center

Max.

For

60Hz

±30 Footlamberts ±3fL

Paragraph

Time

Hz

60

this

of 9D

5

Nominal

x

2.6 ±0.1psec (REF)

monitor?

Load

2-5

with

1030"

North

Intensity

11mA

LED

=

±0.10"

9

220

Rev. B

VAC

-

'

tal

alignment

Timing-

Dot

Rate

Horizontal

Vertical

Step

All

OP

Codes Arc

Set

Moniterrn video

generator

Rate

Rate

outputs

must be done

on

62.176

66.43 KHz Totai

66.43

MHz

Hz

2

Zero Except:

to:

Monitenn

Special

9 1 DPI controller

Instructions

Quantum Generator Settings

Horizontal:

Dots/Character

Characters

Drive Delay

Drive Width 4

.

OP

OP

Video:

KJC.

3.1.

4.1, OP

Sync:

Reverse

+,

H. sync

OP

7.1, OP

8.1.

card.

Vertical:

9 Lincs/Character

104

80 Rows

78

OP

Bit

3: Off

Sync:

H

Total

Drive

Drive

123, OP 14.1,

13.3, OP 15.2.

Bit

2: Off

-

V

sync:

16

1000

60

Delay 60

Width

3

OP 16.3

On

Bit 1:

-

Postbus

Telefoon 03473

Telefax 77200

70,

4

1 30 EB

-77272

-

Telex

Vianen

76409'

-

Holland

Reparatie

tips

Output

v

9

V 2 K

25

40 V

100

V

120

V 14 M

1200

V 8-9 M

SPS defecten

normale

weerstand

M

4.3

20

3-4

7-3

(zonder

(met video

M

M

> check

vervang

potmeter 1 regelt alle DC output

>

potmeter 2

video board)

board)

VI, FET, transformator

ook VI+FET

bij

regelt high voltage circuit

check

SPS, D8, R220

U2,

SPS

U3,

diodes

diodes

rondom,

SPS D10

T2

Q7,

High

tion

High

tion

voltage

protection

voltage

protection,

output diodes

en

box, deflec-

box, deflec-

Q5,

transformator defect!

levels

D5

Defect

9

spoelhuis > check T2,

volt defect?

"

W48«4

(Oordr-rchx)

vangen

evt. V5 op

D32/37.

Q7,

als

,

je

het

deflection board

al deze

spoelhuis

componenten ver-

vervangt!!

Postbus

70,

Telefoon

elefax 77200

T

4 1

30 EBVianen- Holland

03473-77272

-

Telex 76409

•

1

Moniterm kent/kende

Viking 1

Viking

Viking

2

3

De VCX heeft

storing)

.

Atari krijgt VCX

VXP

VXP

VCX 1000

betere focus

een

Deflection board is veel

1000,

3

1000

.1000

"Viking"

electronica.

electronica.

electronica. plastic

modellen:

en een verbeterde

Moniterm beschikt over een support

De

Atari interface

De

software is geschreven

van

Atari Corp. Deze

T0S

1.4

(geen

mogelijkheid

Wilfred

Kilwinger

32K video

om te

kaart

software

switchen tussen SM194 en SM124.

ontwikkeld door een extreme

is

door deze

werkt momenteel uitsluitend

memory beperking) .

metalen kast

plastic kast

beter.

BBS.

ontwikkelaar

De

kast

voeding

(beeld-

ontwikkelaar.

Bradertcher

Ken

en

onder

software kent geen

T

i*

(iwnnuntom

544*4

(Qordrrctu)

UCr^cftC. Ond^rw.

Bu

i co<) U

01/S4.

rrvrt

n mfl.

uofcianf

n vyn

(td«pon««rd UfCfiirurMd*

ws»r» voonvunlM,

yu

Dumr

*rr in

R

c

1A

IB

1CLR 20

1CX

IRC

470PF

,NPO

IQ

74LS221

2A,

22

2CLR 20

^2CX

S . IK

r^T

20

,HF

DIS

U1

THR OUT

TLCS5S

TRIC

CTRL CND

!

VIP PC A.

1BK

TO

PIN

VERT

UN

IK

OF

16

IH

VERT HcICHT

5V

1

>

R28

•<

>•

180K

<

200K

<

<

nvo

4

r VERT

2SK

LIN

V4

COE

•

of

e

to pin

8

e 5

w