Atari 520STE Field Service manual

II

Atari STe 520/1040

Computer Field Service Manual

Part Number: C302481–001 Rev A

August 1991

III

TABLE OF CONTENTS

SECTION ONE: INTRODUCTION ................................................................................... 1

1.0 Overview .......................................................................................................... 1

1.1 Main Components ............................................................................................ 1

1.2 Case Design .................................................................................................... 1

1.3 Power Supply ................................................................................................... 3

1.4 Negative Supplies ............................................................................................ 3

SECTION TWO. THEORY OF OPERATION .................................................................. 4

2.0 Overview .......................................................................................................... 4

2.1 Main System .................................................................................................... 4

2.2 Audio/Video Subsystem ................................................................................... 4

2.3 InputlOutput Subsystems ................................................................................. 5

2.4 Microprocessing Unit ........................................................................................5

2.5 GSTMCU ..........................................................................................................5

2.6 Main Memory ................................................................................................... 6

2.7 Direct Memory Access ..................................................................................... 7

2.8 Multi–Function Peripheral Control ....................................................................7

2.9 Audio/Viideo Subsystem .................................................................................. 8

2.10 Digitized Sound ................................................................................................ 10

2.11 Genlock and the STE ....................................................................................... 10

2.12 Input/Output Subsystems .................................................................................11

2.13 System Startup ................................................................................................ 21

2.14 System Errors .................................................................................................. 22

SECTION THREE: TESTING .......................................................................................... 24

3.1 Overview .......................................................................................................... 24

3.2 Test Configuration ............................................................................................25

3.3 Troubleshooting a Dead Unit ........................................................................... 25

3.4 Diagnostic Cartridge ....................................................................................... 26

3.5 Power Up Sequence ....................................................................................... 26

3.6 Test Menu ....................................................................................................... 28

3.7 RAM Test ........................................................................................................ 28

3.8 ROM Test ........................................................................................................ 29

3.9 Color Test ........................................................................................................ 29

3.10 Keyboard Test ................................................................................................. 30

3.11 MIDI Tests ........................................................................................................ 31

3.12 RS232 Tests .................................................................................................... 31

3.13 Audio Test ........................................................................................................ 32

3.14 Timing Tests .................................................................................................... 33

3.15 DMA Tests ....................................................................................................... 34

3.16 FIoppy Disk Tests ............................................................................................ 34

3.17 Printer and Joystick Port Tests ........................................................................ 36

3.18 Monochrome Monitor ....................................................................................... 37

3.19 Hard Disk WriteIRead ...................................................................................... 37

3.20 Graphics Chip BLiT .......................................................................................... 38

3.21 Error Codes (quick Reference)......................................................................... 38

SECTION FOUR: DISASSEMBLY/ASSEMBLY …………………………………………… 43

4.1 STE Disassembly .............................................................................................43

4.2 STE Reassembly ............................................................................................. 44

IV

SECTION FIVE: SYMPTOM CHECKLIST ………………………………………………….. 45

5.1 Display Problems ............................................................................................. 45

5.2 Disk Drive Problems ......................................................................................... 45

5.3 Keyboard Problems .......................................................................................... 46

5.4 MIDI Problems ................................................................................................. 46

5.5 RS232 Problems .............................................................................................. 46

5.6 Printer Port Problems ....................................................................................... 46

5.7 Hard Disk Port Problems .................................................................................. 46

5.8 DMA Sound ...................................................................................................... 46

SECTION SIX: DIAGNOSTIC FLOWCHARTS ………………………………………….…..47

6.1 Replacement Procedures .................................................................................47

6.2 Handling of Integrated Circuits ......................................................................... 47

SECTION SEVEN: PARTS LIST ..................................................................................... 52

SECTION EIGHT: GLOSSARY ....................................................................................... 56

SECTION NINE: SCHEMATICS AND SILKSCREENS ...................................................58

V

Reproduction of all or any portions of this manual is not allowed without the specific
written consent of Atari Corporation.

Every effort has been made to ensure the accuracy of the product documentation in
this manual. However, because Atari Corporation is constantly improving and
updating its computer hardware and software, it is unable to guarantee the accuracy
of printed material after the date of publication and disclaims liability for changes,
errors. or omissions.

These documents are for repair service information only. Part numbers are for
reference only. Only parts on current dealer parts lists are available. No license is
given for any use by the possession of these documents and may not be reproduced
in any form without the written approval of Atari Corporation.

Atari, the Atari logo, STE, TOS, BLiTTER , SM124, SC1224, SF314, SF354,
PCF554, SLM804, CDAR504, Atari BASIC, and Atari SFP–004 are trademarks or
registered trademarks of Atari Corporation. Centronics is a registered trademark of
Centronics Data Computer Corporation. GEM and GEM Desktop are trademarks or
registered trademarks of Digital Research, Inc. MS–DOS is a registered trademark of
Microsoft Corporation. Epson is a registered trademark of Seiko–Epson Corporation.
VT and DEC are registered trademarks of Digital Equipment Corporation.

Copyright © 1991, Atari Corporation
Sunnyvale, CA 94089–1302
All rights reserved.

1

SECTION ONE: INTRODUCTION

1.0 OVERVIEW

The 520STE and 1040STE are designed as integrated units with keyboard,
processor, memory, and I/O control in one package. The 520STE has 520 kbytes
(524.280 bytes ) of RAM, and the 1040STE has 1040 kbytes (1,048,568 bytes) of
RAM. The 1040STE and 520STE both have a built–in 1 megabyte floppy disk drive
(unformatted). Both the 520STE and 1040STE come with a modulator for TV output.
The 520STE and 1040STE both have the power supply integrated into the case.

1.1 MAIN COMPONENTS

• 524K RAM (1048K for the 1040STE)

• Main Board with modulator (except French Peritel)

• Keyboard Assembly

• RF Shield (upper and lower) and Power Supply

• Plastic Case (upper and lower)

• Mouse

• Power Supply

• Disk Drive

1.2 CASE DESIGN

The 520STE and the 1040STE are nearly identical. The upper case has openings for
the keyboard and a lens for both the power indicator LED (front left corner) and the
Disk Drive Activity LED (mid right side). (see Fig. 1–1)

Figure 1–1: 520STE Upper Case

2

Figure 1–2. 1040STE Upper Case

The left side panels of both machines have slots for the expansion cartridge, two
MIDI ports and two game controllers.

Figure 1–3. STE Left Side Panel

The right side panel has a slot for the floppy disk drive.

Figure 1–4. STE Right Side Panel

The STE back panel contains (left to right) the modem (RS232) connector, printer
connector, hard disk/DMA connector, external floppy disk connector, television
output, monitor connector, power switch, stereo output (right and left), AC power
input, and reset button. (see Fig. 1–5)

3

Figure 1–5. STE Back Panel

1.3 POWER SUPPLY

The 520STE and 1040STE have an integral switching power supply providing +5V
and +12V. There is a 2A fuse. Voltage should be adjusted to 5.1V. The power supply
has overcurrent protection; if the fuse is blown, a catastrophic failure is likely, such
as shorted primary

Power Supply Rating

Current out: 3A at 5V, 0.9A at +12V

Max. power in: 33.5W

Typical (in system) Demand.

Typical current: 1.75A at 5V, 86 mA at + 12V

Max. current: 2.2A at +5V, 90 mA at +12 (during disk access)

1.4 NEGATIVE SUPPLIES

The STE motherboard contains two small switching voltage regulators (the TL497 or
equivalent) that are used to provide additional voltages.
0204 is used to generate the positive and negative voltages for the RS232C line
drivers. These voltages are normally ±12 VDC.
U205 is used to generate a –5 VDC supply for the audio subsection. This output is
heavily filtered to reduce the switching noise that might otherwise appear in the
audio output.

4

SECTION TWO: THEORY OF OPERATION

2.0 OVERVIEW

The 520STE and 1040STE share a common architecture, using the same LSI chip
set. The most significant difference is the addition (to the 1040STE) of one bank of
512K of RAM, for a total of 1024K (1,048,568 bytes). Except for the additional RAM,
the differences between the 520STE and 1040STE are transparent to software. The
hardware can be considered as consisting of a main system (central processing unit
and support chips) and several Input/Output subsystems.

2.1 MAIN SYSTEM

• MC68000 running at 8 MHz

• 256 kbyte ROM

• 512/1024 kbyte RAM

• Direct Memory Access Support

• System Timing and Bus Control

• Interrupt Control

2.2 AUDIO/VIDEO SUBSYSTEM

The STE has bit–mapped video display, normally using 32,000 bytes of RAM,
relocatable anywhere in memory. There are three display modes available:

RGB, with the ability to be GenLocked:

1. 320 x 200 pixel, 16 color palette from 4096 selections

2. 640 x 200 pixel, 4 color palette from 4096 selections

Monochrome:

3. 640 x 400 pixel, monochrome monitor interface

2.2.1 Audio Output

The STE has a programmable sound chip and 8–bit stereo DMA at 4 playback
frequencies.

2.2.2 Television Interface

NTSC, PAL I and PAL B.

5

2.3 INPUT/OUTPUT SUBSYSTEMS

• Intelligent keyboard with 2 button mouse/joystick interface

• Parallel printer interface

• RS232C serial interface

• Floppy disk drive and connector for external drive

• Game controller ports

• Hard disk drive interface (ACSI)

• Musical instrument network communication: Musical Instrument Digital

Interface (MIDI)

2.4 MICROPROCESSING UNIT

The STE uses the Motorola MC68000 16–bit external/32–bit internal data bus. 24–bit
address bus microprocessor, running at 8 MHz.

2.5 GSTMCU

GSTMCU is such an important component that it is involved in nearly every operation in the

computer. The functions may be summarized as follows:

CLOCK DIVIDERS takes the 16 MHz clock and outputs 8 MHz, 4 MHz, and
500 kHz clocks.

VIDEO TIMING Blank, DE (Display Enable), Vsync and Hsync are used to generate
signals for the video display. There is a Read/Write register in GSTMCU which may
be written to configure for 50 or 60 Hz operation or 71 Hz monochrome operation
(done by the Operating System).

INTERRUPT PRIORITY interrupts from the MFP and video timing are coded into
four levels of priority on outputs IPLO and IPL1 to the 68000. These levels corres­pond to no interrupts, MFP interrupts, VSYNC interrupt, HSYNC interrupt.

level 7 reserved
level 6 MFP
level 5 unused
level 4 VSYNC
level 3 unused
level 2 HSYNC
level 1 unused

SIGNAL AND BUS ARBITRATION GSTMCU decodes addresses to generate chip
selects to the 6850s, MFP, DMA Controller. Programmable Sound Generator,
Memory Controller, and ROMS. It receives signals from the MFP, DMA, Memory

6

Controller, to synchronize data transfer. It arbitrates the bus during DMA transfers to
prevent CPU and DMA devices from interfering with each other (see DMA below).

ILLEGAL CONDITION DETECTION GSTMCU asserts Bus Error (BERR) if certain
conditions are violated, such as writing to ROM, writing to system memory when the
processor is in user mode, or if no device responds within 64 cycles of the 8 MHz
clock (8Ns). For example, if the CPU tries to read from beyond the end of memory,
the Memory Controller will not assert DTACK, resulting in a bus error which will
terminate the memory cycle.

MEMORY CONTROLLER takes addresses from the address bus and converts to
Row Address Strobe (RAS) and Column Address Strobe (CAS). All RAM accesses
are controlled by this Atari proprietary chip, which is programmable for up to 4
Megabytes of memory. The Operating System determines how much memory is
present and configures the Memory Controller at power–up. The Memory Controller
refreshes the dynamic RAMs, loads the Video Shifter with display data, and gives or
receives data during direct memory access (DMA). The Memory Controller produces
all of the addresses for video, sound, and DMA on the multiplexed address bus.
These addresses never appear on the system address bus.

CHIP SELECTS Decodes addresses for RAM and ROM and asserts output signals
to enable these devices.

2.6 MAIN MEMORY

Main memory consists of 256 kbytes of ROM and one or two banks (512 kbyte each)
of dynamic RAM. In addition, the cartridge slot allows access to 128 kbytes of ROM.
All memory is directly addressable. The components of the memory system are:
ROM, RAM, GSTMCU and shifter. The Operating System resides mostly in ROM,
with optional segments loaded from disk into RAM.
Each bank of RAM in the STE is made up of a pair of 8–bit wide SIMMs to create the
16–bit wide system memory bus. All of the SIMMs in the system must be the same
size. It is not possible to mix 256 kbit SIMMs and 1 Mbit SIMMs in the same system.
All of the SIMMs used should have the same access time, which can be no greater
than 150 ns.
It is possible to use 9–bit wide SIMMs, with the hardware simply ignoring the ninth
bit.

RAM MEMORY MAP:

000008–000800 System Memory (privileged access)
000800–07FFFF Low Bank
080000–0FFFFF High Bank (1040 only)

Note: The first 8 bytes of ROM are mapped into addresses 0–7. These are reset
vectors which the 68000 uses on start–up.
The Operating System is located in two 128K x 8 ROM chips.

ROM MEMORY MAP.

E00000–E3FFFF

7

2. 7 DIRECT MEMORY ACCESS

A single direct memory access (DMA) channel is provided that is shared between
the internal floppy disk controller and external devices connected to the ACSI port.
Data can be transferred at up to 10 Megabits/sec (1.25 Megabytes/sec) across the
8–bit wide ACSI port.

For DMA to take place, the memory controller is programmed with the starting
address at the RAM buffer. The DMA controller is set up to select the source and the
number of 512 byte blocks to transfer, and then the FDC or external peripheral is
given the command to send or receive data. The entire block of data is then
transferred to or from memory
without intervention by the CPU. The FDC or peripheral generally asserts its interrupt
line to signal the completion of the transfer (and the availability of status information).

To access registers in the FDC or ACSI bus peripherals, the 68000 talks through the
DMA chip. The state of two address lines that are generated by the DMAC is set by
writing to the DMA control register. Then a 68000 read or write cycle causes the
corresponding cycle on the peripheral side of the DMAC.

2.8 MULTI–FUNCTION PERlPHERAL CONTROL

2.8.1 Interrupt Control

The 68901 MFP can generate up to 16 interrupts, 8 internally and 8 from external
sources. Each interrupt can be masked off or disabled by programming the MFP.
The 8 inputs are also directly readable by the CPU. When the MFP receives an
interrupt internally, if the interrupt is enabled, MFPINT will be driven low. When the
CPU is ready to respond, it signals interrupt acknowledge (FC2–FC0 high, A3–A1=6,
and R/W low) and GSTMCU will assert the MFPs IACK signal (interrupt
acknowledge). The MFP will assert DTACK and put a vector number on the data
bus, which the CPU will read and use to calculate the address of the interrupt
routine.

The interrupts controlled by the MFP are: monochrome monitor detect (MONOMON),
RS232 (including CTS, DCD, RI), disk (FDINT and HDINT), parallel port BUSY,
display enable (DE, equals the active part of a display line), 6850 IRQs for keyboard
and MIDI data, and MFP timers.

Not all I/O operations use interrupts. The CPU can also poll the MFP while waiting
for an operation to complete or to check the current status.

2.8.2 MFP Counter/Timers

The MFP clock runs at 2.4576 MHz. The MFP contains four timers:

Timer A Reserved for application software used in the original ST. In the STE, its

external event input is used to count DMA sound subsystem cycles.

8

Timer B External input can be used to count horizontal display lines.

Timer C Reserved for use by the operating system as a periodic interrupt (nominally

200 Hz when running TOS).

Timer D Baud rate generator for the MFP's RS232 port. Its output is used to drive
both the receiver and transmitter clock inputs. It will normally be
programmed to be 16 times the desired asynchronous baud rate.

2.9 AUDIO/VIDEO SUBSYSTEM

The video subsystem consists of the video display memory (an arbitrary block of
RAM starting on any word boundary), the GSTMCU, a graphics control chip (Video
Shifter), some discrete components to drive the video output, and an RF modulator.
The audio subsystem consists of a Programmable Sound Generator chip, DMA
sound circuit, and a programmable mixer (LMC 1992).

2.9.1 Video Shifter (GSTShifter)

There are 16 color palette registers in the shifter. All 16 may be used in low
resolution, 4 may be used in medium resolution, and only one is used in high
resolution (actually, only bit 0 of register 0 is used for inverse/normal video). Each
palette is programmed for 16 levels of intensity of red, blue, and green, so there are
16 x 16 x 16 = 4096 colors possible. For a given pixel, the color which is displayed is
taken from the palette pointed to by assembling the bits from each logical plane (see
description of video display memory below). The shifter will output the red, green and
blue levels specified by the palette. Note that there are four outputs for each color.
Each output is either on or off. Thus, the number of possible output levels is 2 to the
4th power = 16 levels. The four outputs are summed through a resistor network to
proportion the voltage level to give 16 equal steps. In monochrome mode, the color
palettes are bypassed and there is a separate output.

2.9.2 Video Display Memory

Display memory is part of main memory with the physical screen origin located at the
top left corner of the screen. Display memory is configured as 1, 2, or 4 (high,
medium, or low resolution) logical planes are interwoven as 16 bit words into
contiguous memory to form one 32,000–byte physical plane starting at any word
boundary. The starting address of display memory is placed in the Memory
Controller's Video Base Address register by the Operating System or application.
The Memory Controller will load display information into the Video Shifter 16 bits at a
time, and the Video Shifter will decode this information to generate a serial display
stream. In monochrome mode, each bit represents 1 pixel on or off. In color, bits are
combined from each plane to generate the correct level of red, green and blue.
For example, in low resolution (4 planes) 4 words are loaded into the Video Shifter
for each word (16 pixels displayed on the screen). The Video Shifter combines bit 0
from each word to form a four bit number (0 –15), and takes the color from the
palette referenced by that number (e.g. 0101 = 5, use color from palette register 5)

9

and outputs those levels, then takes bit 1 from each plane and outputs the color from
the palette referenced by those 4 bits, etc.

2.9.3 GSTMCU

GSTMCU provides timing control to the Memory Controller, video output, and
monitorIRF output. VSYNC input to the Memory Controller causes the starting
address of the display memory to be reloaded into the address counter during
vertical blanking. DISPLAY ENABLE (DE) tells the Memory Controller and Video
Shifter that a display line is being scanned and data should be loaded into the Video
Shifter. BLANK shuts off the video output from the Video Shifter during periods when
the scan is not in a displayable part of the screen. VSYNC and HSYNC both go to
the monitor output and RF modulator. These signals synchronize the monitor or TV
vertical and horizontal sweep to the display signal.

2.9.4 Memory Controller

In addition to the inputs from GSTMCU mentioned above, there are two output
control signals associated with video. DCYC strobes data from the display memory
into the Video Shifter. CMPCS (color map select) is active only when changing the
color attributes in the color palettes.

2.9.5 Sound Synthesizer

The YM2149 Programmable Sound Generator (PSG) produced music synthesis,
sound effects, and audio feedback (e.g. alarms and key clicks). The clock input is 2
MHz; the frequency response range is 30 Hz to 125 kHz. There are three sound
channels output from the chip, which are mixed and sent to the monitor speaker.
The PSG is also used in the system for various Il0 functions relating to printer port,
disk drive, and RS232.

2.9.6 Video Interface

The three types of video output interface provided by the STEs are analog RGB and
monochrome, composite and modulated RF. The presence of a monochrome
monitor is detected by the MONOMON input (when a monochrome monitor is
connected, it will be TTL low). The possible displays are:

MONOCHROME: single emitter follower amplifier driving the output of the Video
Shifter.

RGB: resistor network sums outputs for each color. The three colors each have an
emitter follower amplifier to drive output.

COMPOSITE: the outputs of the emitter followers are input to the modulator box,
where the vertical and horizontal sync signals are added to form the composite
signal.

10

TELEVISION: the composite signal is modulated onto an RF carrier. The signal is
locked onto the color burst frequency by the phase locked loop (PLL). Without the
PLL, the colors will shift or dance on the TV screen.

2.10 STE DIGITIZED SOUND

The Atari ST family of computers is equipped to reproduce digitized sound using
DMA (direct memory access; that is, without using the 68000). This section provides
the information required to understand and use this feature.

2.10.1 Overview

Sound is stored in memory as digitized samples. Each sample is a number, from

-128 to +127, which represents displacement of the speaker from the "neutral" or
middle position. During horizontal blanking (transparent to the processor) the DMA
sound chip fetches samples from memory and provides them to a digital–to–analog
converter (DAC) at one of several constant rates, programmable as (approximately)
50 kHz (kilohertz), 25 kHz. 12.5 kHz, and 6.25 kHz. This rate is called the sample
frequency.

The output of the DAC is then filtered to a frequency equal to 40% of the sample
frequency by a four–pole switched low–pass filter. This performs "anti–aliasing" of
the sound data in a sample–frequency–sensitive way. The signal is further filtered by
a twopole fixed frequency (16 KHz) low–pass filter and provided to a National LMX
1992 Volume/Tone Controller– Finally the output is available at an RCA–style output
jack on the back of the computer. This can be fed into an amplifier, and then to
speakers, headphones, or tape recorders.

There are two channels which behave as described above; they are intended to be
used as the left and right channels of a stereo system when using the audio inputs of
the machine. A monophonic mode is provided which will send the same sample data
to each channel.

The stereo sound output is also mixed onto the standard ST audio output sent to the
monitor's speaker. The ST's GI sound chip output can be mixed to the monitor and to
both stereo output jacks as well.

2.11 GENLOCK AND THE STE

The ST (and STE) chip set have the ability to accept external sync. This is controlled
by bit 0 at FF820A, as documented in the ST Hardware Specification. This is
provided to allow the synchronization of the ST video. In order to do this reliably the
system clock must also be phase–locked (or synchronized in some other way) to the
input sync signals. No way to achieve this was provided in the ST. As a result, the
only GENLOCKs available were internal modifications (usually for the MEGA).
The STE, on the other hand, allows this to be done without opening the case. To
inject a system clock ground pin three (GPO) on the monitor connector and then
inject the clock into pin 4 (mono detect). The internal frequency of this clock is

32.215905 MHz (NTSC) and 32.084988 MHz (PAL).

11

Note. DO NOT SWITCH CLOCK SOURCE WHILE THE SYSTEM IS ACTIVE.

As a result the GPO is no longer available.

MONITOR INPUTS:

HSYNC TTL level, negative, 3.3k ohm.

VSYNC TTL level, negative, 3.3k ohm.

Monochrome Digital 1.0 Vpp, 75 ohm.

RGB Analog 0–1.0 Vpp, 75 ohm. Audio 1 Vpp, 1 k ohm.

Monitor

1 – Audio Out
2 – Composite Video
3 – External Clock Select (Pull low

for external dock on pin 4)

4 – Monochrome Monitor Detect (when

used for GENLOCK becomes clock)

5 – Audio In
6 – Green
7 – Red
8 – +12 Volt Pullup
9 – Horizontal Sync
10 – Blue
11 – Monochrome
12 – Vertical Sync
13 – Ground

Figure 2–1: Monitor Ports

2.12 INPUT/OUTPUT SUBSYSTEMS

2.12.1 Musical Instrument Communication

The Musical Instrument Digital Interface (MIDI) allows the integration of the STE with
music synthesizers, sequencers, drum boxes and other devices possessing a MIDI
interface. High speed (31.25 kilobaud) asynchronous current loop serial
communication of keyboard and program information is provided by two ports, MIDI
OUT and MIDI IN (MIDI OUT also supports the optional MIDI THRU port). MIDI
specifies that data consist of 8 data bits preceded by one start bit and followed by
one stop bit.

Communication takes place via a 6850 ACIA. The CPU writes to the 6850 in
response to interrupts which are passed from the 6850 to the MFP interrupt

12

controller. The system is interfaced to the outside via two inverters on the transmit
side and an LED/photo–transistor chip on the input side. The input signal is also
routed around through two inverters to the output connector where it is called MIDI
THRU in order to allow chaining of multiple devices on the MIDI bus.

MIDI Out

1 – THRU Transmit Data
2 – Shield Ground,
3 – THRU Loop Return 3
4 – OUT Transmit Data
5 – OUT Loop Return

MIDI In

1 – Not Connected
2 – Not Connected 3
3 – Not Connected
4 – IN Receive Data
5 – IN Loop Return z

Figure 2–2. MIDI Ports

2.12.2 Intelligent Keyboard

The keyboard transmits make/break key scan codes, ASCII codes, mouse data, and
joystick data, in response to external events, and time–of–day (year, month, day,
hour, minute, second) in response to requests by the CPU. Communication is
controlled on the main board by a 6850 device and on the keyboard assembly by the
1 MHz 8 bit HD6301 Microcomputer Unit. The HD6301 has internal RAM and ROM.
Included in ROM are selftest diagnostics which are performed at power–up and
whenever the RESET command is sent over the serial communication line by the
CPU. The MC6850 is read from and written to by the CPU in response to interrupts
which are passed to the CPU by the MFP interrupt controller.

2.12.3 Mouse/Joysticks

The 2 Button Mouse is an opto–mechanical device with the following characteristics:
a resolution of 100 countslinch, a maximum velocity of 10 inches/second and a
maximum pulse phase error of 50 percent. The joystick/mouse port has inputs for up,

13

down, left, right, right button, left button. The right button equals the joystick trigger,
the left button is wired to the second joystick port trigger. The joystick has four
directions (up, down, etc.) and one trigger.

Note. The Atari CX24 joystick cannot be installed during initialization.

Mouse/Joystick

1 – Up/XB
2 – Down/XA
3 – Left/YA
4 – Right/YB
5 – Not Connected
6 – Fire/Left Button
7 – +5VDC
8 – Ground
9 – Joy1 Fire/Right Button

Joystick

1 – Up
2 – Down
3 – Left
4 – Right
5 – Reserved
6 – Fire Button
7 – +5 VDC
8 – Ground
9 – Not Connected

Figure 2–3: Mouse/Joystick Ports

2.12.4 Parallel lnterface

The parallel port is primarily intended as a Centronics type printer interface, but can
also be used as a general purpose I/O port. Centronics STROBE and BUSY are
supported. BUSY is read by the MFP chip. Data and strobe signals are output by the
YM2149 PSG chip. Not all Centronics printers are compatible with this port. The
current loading on the data lines should not exceed 2.3 mA. (This corresponds to a

2.2k ohm resistor pull–up on the printer side).
The port can be programmed to be input or output. The PSG chip is read directly by
the CPU, with GSTMCU doing address decode to provide chip select.

14

Printer

1 – STROBE
2 – Data 0
3 – Data 1
4 – Data 2
5 – Data 3
6 – Data 4
7 – Data 5
8 – Data 6
9 – Data 7
10 – Not Connected
11 – BUSY
12 – 17 – Not Connected
18 – 25 – Ground

Figure 2–4: Printer Port

2.12.5 RS232C Interface

The RS232C interface provides asynchronous serial communication with five
handshake control signals: Request to Send and Data Terminal Ready are output by
the PSG chip: Clear to Send, Data Carrier Detect, and Ring Indicator are input to the
MFP chip. The MFP contains a USART (Universal Synchronous/Asynchronous
ReceiverlTransmitter) which handles data transmission and reception. The 2.4576
MHz clock to the MFP is divided by the timer D (pin 16) output of the MFP to provide
the basic clock for receiver and transmitter. Data rate of 50 to 19200 bits per second
are supported. 1488 line drivers and 1489 line receivers with ±12V supply (supplied
by the TL947 DC:DC inverter) meet the EIA RS232C standard for electrical interface.

Modem

1 – Protective Ground
2 – Transmitted Data
3 – Received Data
4 – Request to Send
5 – Clear to Send
6 – Not Connected
7 – Signal Ground
8 – Data Carrier Detect
9 – 19 – Not Connected
20 – Data Terminal Ready
21 – Noi Connected
22 – Ring Indicaor
23 – 25 – Not Connected

Figure 2–5. RS232 Port

15

2.12.6 Disk Drive Interface

The STE computers have a built–in floppy disk controller and logic for selecting up to
two single or double sided drives. The 1040 STE has one built–in floppy disk drive
and provision for one external disk drive. A single 1772 Controller services both
drives. Drive and side selection is done by outputs on the YM2149 PSG chip. The
CPU reads and writes to the 1772 through the DMA Controller. The 1772 interrupts
the CPU on the INTR line, via the MFP interrupt controller. The 1772 accepts high
level commands, such as seek, format track, write sector, read sector, etc. and
passes data to the DMA Controller (see DMA controuer under Main system, above,
for details on DMA transfer). The 1772 interrupts the CPU when the operation is
complete. The CPU is freed from much of the overhead of disk I/O.

Note: Several of the 1772 output signals are externally buffered or inverted. See
Block Diagram.

Floppy Disk

1 – Read Data
2 – Side 0 Select
3 – Logic Ground
4 – Index Pulse
5 – Drive 0 Select
6 – Drive 1 Select
7 – Logic Ground
8 – Motor On
9 – Direction In
10 – Step
11 – Write Data
12 – Write Gate
13 – Track 00
14 – Write Protect

Figure 2–5: Floppy Port

2.12.7 Hard Disk Interface

The hard disk drive interface is provided through the DMA controller. The hard disk
controller is off–board and is sent commands via a SCSI–like (Small Computer
System Interface) command parameter block. Data is transferred via DMA. Writing to
the external controller causes HDCS (Hard Disk Chip Select) to go low and CA1 to
go high. DMA transfers are controlled by the external device. When data is available,
or the device is ready to accept data, HDRQ will be driven high by the external
controller. The DMA chip must respond within 250 nanoseconds with ACK (low) to
knowledge that data is on the bus or has been read from the bus. The Memory
Controller feeds data to or accepts data from the DMA Controller. Transfers can take
place at up to 1 Mbyte/sec.

16

Hard Disk

1 – Data 0
2 – Data 1
3 – Data 2
4 – Data 3
5 – Data 4
6 – Data 5
7 – Data 6
8 – Data 7
9 – Chip Select
10 – Interrupt Request
11 – Ground
12 – Reset
13 – Ground
14 – Acknowledge
15 – Ground
16 – A1
17 – Ground
18 – Read/Write
19 – Data Request

Figure 2–6. Hard Disk Port

17

Controller A

1 – Up 0
2 – Down 0
3 – Left 0
4 – Right 0
5 – Paddle 0Y
6 – Fire 0
7 – +5 VDC
8 – Not Connected
9 – Ground
10 – Fire 1
11 – Up 1
12 – Down 1
13 – Left 1
14 – Right 1
15 – Paddle 0X

Controller B

1 – Up 2
2 – Down 2
3 – Left 2
4 – Right 2
5 – Paddle 1X
6 – Fire 2
7 – +5 VDC
8 – Not Connected
9 – Ground
10 – Fire 3
11 – Up 3
12 – Down 3
13 – Left 3
14 – Right 3
15 – Paddle 1Y

Figure 2–7. Game Controller Ports

18

Figure 2-8: STE Functional Block Diagram

19

Figure 2–9. STE DMA Block Diagram

20

Figure 2–10: STE Audio Block Diagram

2.12.8 Controllers

The controllers allow the integration of the STE with joysticks, paddles, and light
gun/pen.

2.12.8.1 JOYSTICKS

Four new joystick ports are added. These ports are controlled directly by the CPU.
The current state may be sampled at any time by reading the above locations.
Joystick 0 and Joystick 2 direction bits are readlwrite. If written to they will be driven

21

until a read is performed. Similarly, they will not be driven after a read until a write is
performed.

2.12.8.2 PADDLES

One pair of paddles can be plugged into Joystick 0 (Paddle 0). A second set can be
plugged into Joystick 1 (Paddle 1). The current position of each of the four paddles is
reported at these locations. The fire buttons are the same as for the respective
joystick. The triggers for the paddles are read as bits one and two of FF9202 (JOY0
Left and Right).

2.12.8.3 LIGHT GUN/PEN

A light gun or pen can be plugged into Joystick 0. The current position that the gun
or pen is pointing to is reported by these registers. The position is accurate to within
(X direction only):

4 Pixels in 320 x 200 Mode 8 Pixels in 640 x 200 Mode 16 Pixels in 640 x 400 Mode
Accurate to 1 pixel in the Y direction in all modes. Accuracies do not account for the
quality of the light gun or pen. Note that the X position is given in pixels for 320 x 200
only. In order to get correct results in 640 x 200 mode this number needs to be
shifted left
one bit and in 640 x 400 modes this number needs to be shifted left two bits.

2.13 SYSTEM STARTUP

After a RESET (power–up or reset button) the 68000 will start executing at the
address pointed to by locations 4–7, which is ROM (GSTMCU maps the first 8 bytes
of ROM at E00000 into the addresses 0–7). Location 000004 points to the start of
the operating system code in ROM. The following sequence is then executed:

1. Perform a reset instruction (outputs a reset pulse). (RESET.)

2. Read the longword at cartridge address FA0000. If the data read is a "magic
number", execute from the cartridge (cartridge takes over here). If not,
continue.

3. Check for a warm start (see if RAM locations are valid). If not, initialize the
memory controller.

4. Initialize the PSG chip, deselect disk drives.

5. Initialize color palettes and set screen address.

6. If not a warm start, zero memory.

7. Set up operating system variables in RAM.

8. Set up exception vectors.

9. Initialize MFP.

10. Set screen resolution.

11. Attempt to boot floppy; attempt to boot hard disk; run program if successful.

12. If no boot disk, load the desktop ROM on board 256K ROM.

22

2.14 SYSTEM ERRORS

The 68000 has a feature called exception processing, which takes place when an
interrupt or bus error is indicated by external logic, or when the CPU detects an error
internally, or when certain types of instructions are executed. An exception will cause
the CPU to fetch a vector (address to a routine) from RAM and start processing at
the routine pointed to by the vector. Exception vectors are initialized by the operating
system. Those exceptions which do not have legitimate occurrences (interrupts
being legitimate) have vectors pointing to a general purpose routine which will
display some number of bombs showing on the screen. The number of bombs
equals the number of exceptions which occurred. System errors may or may not be
recoverable. Errors in loading files from disk may cause the system to crash,
necessitating a reset. Verify the diskette and disk drive before attempting to repair
the computer.

2.14.1 Number of Bombs and Meaning

2: BUS ERROR. GSTMCU asserted bus error.
3: ADDRESS ERROR_ Processor attempted to access word or long word

sized data on an odd address.

4: ILLEGAL INSTRUCTION. Processor fetched an instruction from ROM

or RAM which was not a legal instruction.

5: ZERO DIVIDE. Processor was asked to perform a division by zero.
6: CHK INSTRUCTION. This is a legal instruction, if software uses this, it

must install a handler.

7: TRAPV INSTRUCTION. See Chk instruction.
8: PRIVILEGE VIOLATION. CPU was in user mode, tried to execute a

68000 instruction that can only be performed in supervisor mode.

9: TRACE. If trace bit is set in the status register, the CPU will execute

this exception after every instruction. Used to debug software.

10: LINE 1010 EMULATOR. CPU read an instruction which has '1010' as

its most significant nibble. Used by TOS for low level graphics software
routines.

11: LINE 1111 EMULATOR. CPU read an instruction which has ' 1111' as

its most significant nibble. Used internally in earlier versions of TOS,
but reserved on STE.

12: 12–23 Unassigned, should be no occurrence.
24: SPURIOUS INTERRUPT. Bus error during interrupt processing.

25–31: AUTOVECTOR INTERRUPT. Numbers 4 and 2 are used,

others should have no occurrence.

32–63: TRAP INSTRUCTION. CPU read instruction which is used to generate

a software exception (such as the entry to GEMDOS, VDI, or AES).

64–79: MFP interrupts.
80–127: Reserved for Atari use.
128–255: Unused.

23

24

SECTION THREE: TESTING

3.1 OVERVIEW

This section pertains to the test equipment, diagnostic software, and test procedures
used to verify correct operation and repair of the STE computers. The diagnostic
cartridge should be used if possible. If the unit gives no display or RS232 output
when running the cartridge, see Section 3.3: Troubleshooting a Dead Unit.

Since the STE system is quite complex, it should not be expected that this document
can cover all possible problems or pinpoint the causes; rather, the intent here is to
give a systematic approach which a technician can use to narrow down a problem to
its most likely source. Experience in troubleshooting computer systems is assumed.
Knowledge of the 68000 processor may be helpful.
Economics will be an important consideration; due to the low cost of the STE
computer line, little time can be justified in troubleshooting down to the component
level when it may be cheaper to replace the functional sub–assembly.

3.1.1 Test Equipment

The following equipment may be needed to test the STE computer:

• Atari SC 1224 or SC 1435 RGB Monitor (or similar)

• Atari SM 124 Monochrome Monitor (or similar)

• Atari SF354 or SF314 External Floppy Disk Drive

• ST Port Test Fixture, C103589–001 (DMA Test Fixture)

• STE Port Test Fixture. C301153–001 (Genlock Test Fixture)

• RS232 Loop–Back Connector

• MIDI Loop–Back Connector, C302272–001

• STE Test Diagnostic Cartridge, Revision 1.5 or later (pln C302260–001)

• Blank Double Sided 3.5" Diskettes (2)

• RS232 Terminal (or STE with VT52 emulator)

• RS232 Null Modem Cable (25 Pin Female–Female)

In addition, the following items may be needed to troubleshoot and repair failed
computers:

• Two Channel Oscilloscope

• Small Hand Tools

• Spare Parts

25

3.2 TEST CONFIGURATION

With the power switch off, install the Diagnostic Cartridge with the label facing UP.

Important: if the cartridge does not have the plastic enclosure; BE SURE THE
CARTRIDGE IS INSTALLED WITH THE CHIPS FACING DOWN.

Connect cables from STE test fixture into the hard disk port, parallel port, and joystick/
mouse ports. The joystick cables should be plugged in so that, if the fixture ports were
directly facing the computer ports, the cables would not be crossed. Plug the RS232 and
MIDI loopback connectors into their ports. Plug the color monitor into the monitor output (a
monochrome monitor can be used instead).
Make sure the switch on the STE test fixture is in the position marked INT, otherwise the
program will not proceed past the initialization.

Power on the unit. Some tests will be run automatically, in a few seconds the menu screen
should appear. If the screen appears, skip down to section 3_4: ST Diagnostic Cartridge,
below. If not read the next Section 3.3: Troubleshooting a Dead Unit.

If the unit is being used as a terminal for a host computer, it should be disconnected from the
host before using the diagnostic; otherwise, the host may think someone is logged on. and
will send messages which will act like keystrokes input to the diagnostic.

3.3 TROUBLESHOOTING A DEAD UNIT

In the event that the system is correctly configured and powered and no display appears,
this is the procedure to use for determining the problem. This assumes elementary steps
have been taken, such as checking the LED in the forward left corner of the computer to
verify the unit is powered and making sure the monitor is working.

1. Connect a terminal to the RS232 port of the unit under test (U.U.T.). you can use an
STE running the VT52 terminal emulator program – see the owner's manual for
setting up the VT52. The cable should connect pin 2 (serial out) of the U.U.T. to pin 3
(serial in) of the terminal and vice versa. Connect pin 7 (ground) to pin 7. The
terminal should be set up for 9600 bps, 8 bits of data, 1 stop bit, no parity (this is the
default condition for the VT52 emulator).

Insert the Diagnostic Cartridge into the U.U.T., and power on the unit. If the
Diagnostic Cartridge messages appear on the display of the terminal, use the
diagnostic to troubleshoot the computer. If not, the computer will have to be
disassembled to troubleshoot. Refer to section 3.4. STE Diagnostic Cartridge for
information on using the cartridge.

If no activity is seen on the RS232 port or display, continue with (2) below.

2. Disassemble the computer so that the printed circuit board is exposed (see section

4. Disassembly). Power up the computer. Using an oscilloscope, verify the 8 MHz

clock to the 68000 CPU. Replace the oscillator if necessary. Then check the HALT
pin of the 68000 CPU. It should be TTL high. If so, go on to 3 below. If not, the CPU
is halted. The reasons may be: (a) bad reset circuit. (b) double bus error. (c) bad
CPU.
Check (a) by observing signal on input of the two inverters on the HALT line. Check
(b) by observing BERR of the CPU as the unit is powered on. It should be high
always. If there are logic low pulses, some component is malfunctioning and
GSTMCU is generating the error. Verify the clocks to GTMCU, tracing back to the
Shifter and MC (master clock) if necessary.

26

If still failing, the CPU is unable to read ROM or there is a component which is not
responding to a read or write by the CPU, probably the MFP 68901 or DMA
Controller. The MFP should respond to an MFPCS with DTACK. The DMA chip
should respond to FCS by asserting RDY. There is no way to check for a bad CPU
other than by elimination of the other two possibilities, although a hot CPU (too hot to
touch for more than a second) strongly indicates a bad CPU.

3. If the CPU is not halted, it should be reading instructions from the ROM (cartridge, if
installed) and data and address lines will be toggling (if not, replace CPU). At this
point, there is the possibility that both the video and RS232 subsystems are failing.
Verify the output of the MFP chip (pin 8) while powering on the unit with the cartridge
installed. If the data is being sent, trace it through the 1488 driver. Note that ±12V is
required for RS232. If all looks good, there may be something wrong with the
connection to the terminal.

Verify also the output of the Video Shifter. If using an RGB monitor, check the
outputs to the summing resistors for R, G, and B. Note that if BLANK is not going
high, no picture will be output. If using monochrome, check the MONO output pin.
Also check the input to the MFP, pin 29, MONOMON. Note that if the CPU does not
read a low on this signal on power–up, it will cause RGB output on the Video Shifter
instead of MONO.

If the Video Shifter is outputting a signal, but the picture is unreadable, there is
probably a problem with the screen RAM. The cartridge should be used to diagnose
this problem, with the RS232 terminal as a display device.

3.4 STE DIAGNOSTIC CARTRIDGE

The STE Diagnostic Cartridge is used to detect and isolate component failures in STE
computers. This section gives a brief guide to its use with a description of each test, error
codes or passlfail criteria, and recommendations on repair.

3.5 POWER UP SEQUENCE

The diagnostic program performs several tests on power–up. The messages “Checking
Exception Handling” and "testing MFP, GSTMCU timing, video” will appear, and the
screen will appear scrambled for a few seconds before the menu is printed. The screen will
turn red (dark background in monochrome) if an error occurs in the initial testing, with a
message indicating the failure. The lowest 2 kbytes of RAM is tested on power–up; if a
location fails, the error will be printed to the RS232 device. It is assumed that if RAM is
failing, the screen may not be readable and program execution will fail because there are no
stack or system variables. The program will continue to test RAM and print errors, but no
screen will be displayed (the screen may turn red). Repair RAM.
If the keyboard fails, it will be inactivated. The user must connect a terminal to the RS232
port. The diagnostic program looks for keystrokes from the RS232 device.
If the display is unreadable, the RS232 terminal should be used. All messages are printed to
the RS232 port as well as on the screen.

27

3.5.1 Power–Up Initialization Errors

I1 Error in RAM or Data Bus
I2 RAM Disturbance Error

location.)

I3 RAM Addressing Error.

I4 Memory Configuration Error. (Problem with Memory Controller or RAM.)
I5 RAM Sizing Error.
I6 Checking Exception Handling

initialization. If the system can fetch the vector from RAM and execute the
handling routine, the message will be erased later.)

I7 Bus Error Not Service.

this error will occur.)

T0 MFP Timer Error.

an interrupt.)

T1 Vertical Svnc.

period.)

T2 Horizontal Sync.

time period.)

T3 Display Enable.

generating an interrupt.)

T4 Video Counter Error.

address for the display. This will result in a broken–up display in some or all
display modes.)

T5 PSG Bus Error.

T6 1772 Bus Error.
K0 Stuck Kev.

executing.

K1 Keyboard Not Responding.

and no status was returned within the allowed time. Verify that the keyboard is
connected to the STE. Verify that Pin 4 of J202 is +5 VDC. Verify that Pin 3 of
U201 is 500 KHz ±50 KHz. Replace the keyboard, 0201. 8210. 8209.

K2 Keyboard Status Error.

completion of the test, the keyboard sent an error status. Replace the
keyboard.

A key closure was detected while the keyboard self test was

(Incorrect amount of good RAM found.)

(One or more of the four timers in the MFP did not generate

(GSTMCU is not generating vertical sync in the required time

(GSTMCU is not generating horizontal sync in the required

(GSTMCU is not generating DE output or the MFP is not

The PSG chip is defective. (Replace chip.)

The 1772 chip is defective. (Replace chip.)

. (Test walks 1 or 0 across data bus.)

. (Writing to one location alters data in another

(Test shows bad RAM cell or incorrect address code.)

. (This message is always printed on power–up

(If the GSTMCU does not assert the Bus Error signal,

(The Memory Controller is not generating the correct

A command was sent to the keyboard processor

The self test command was sent to the keyboard, on

28

3.6 TEST MENU

The normal screen will be dark blue with white letters. The test title and revision
number are displayed at the top, with the amount of RAM and keyboard controller
revision below, and a test menu below that. To select tests, the user types the keys
corresponding to those tests and the [Return] key. Many iterations of the test or
tests chosen can be run by typing in the number of cycles just before typing
RETURN. Typing a zero will cause the test sequence to run continuously. To stop a
cycle before completion, hit the [Esc] key (there may be some delay in some tests
before the test stops). As each cycle completes, the total number of cycles will be
displayed on the screen.

3.6.1 Main Menu (Typical)

The RAM size, keyboard revision, O.S. version, country (or language), and television
standard (PAL or NTSC) are shown.

The 'Q' selection sequences through all the tests which do not require operator inter­action. The 'Z' selection sequences through RAM, ROM, Color, Keyboard, and
Timing, Audio and short BLiT tests. Selection 'E' enables the operator to examine or
modify RAM or hardware registers. 'B' enables the operator to change the baud rate
on the RS232 port. Pressing the up arrow increases it, pressing the down arrow
decreases it.
Pressing '?' or the [Help] key brings up a brief synopsis of the cartridge functions.
After a test (or series of tests) completes. the passlfail status and error report, if any,
will be displayed. Press the space bar to return to the menu.
If multiple tests are selected, the sequence can be halted before completion by
pressing the [Esc] key. At the completion of the current test, the sequence will halt,
with the options of either continuing or returning to the menu. In some cases there
will be considerable delay before the current test completes and the keystroke is
detected.

3.7 RAM TEST (R)

RAM is tested in three stages: low 2 kbytes, middle (up to 64K), and from 64K to top.
The test patterns used are: all 1's, all 0's, a counting pattern (data = low word of the
address), reverse counting pattern (data = complement of address low word). The
counting pattern is copied from the top and bottom of a 32 kbyte buffer into the
current 32 kbytes of video RAM to a new area, verifies the pattern, and repeats the
test, until the top of RAM is reached. Finally, addressing at 64K boundaries is
checked by writing unique patterns in the last 256 bytes of each 64K block.
If an error occurs, on red screen the error code is displayed, followed by the address,
data written, data read, and the bits which did not agree. In example:

3.7.1 RAM Error Codes

Except where noted, repair by replacing the RAM chip corresponding to the indicated
bit(s).

29

R0 low memory failed while setting up to run test.
R1 failed walking 1s or 0s.
R2 failed address (counting pattern).
R3 failed 64K boundary test. Probable failure in GSTMCU.
R4 failed while displaying area tested (video RAM).

3.8 ROM TEST (O)

This test reads the configuration bytes of the operating system to determine the
version, language/country, and TV standard (PAL or NTSC). All bytes from operating
system ROMs are then read and the checksums and CRCs (cyclic redundancy
check) are calculated. The configuration byte is then read to determine the language
and version of the ROM. The correct checksum and CRC is then read from a
look-up table. The unit fails if the values found do not match the values from the
look-up table.

Incorrect checksums are indicated by a message. If an error is displayed, replace the
corresponding ROM.

New versions of TOS will not cause this test to fail since the calculated CRC is
compared with a value found in the new TOS ROMs and is independent of a fixed
look up table.

3.9 COLOR TEST (C)

There are four screens in this selection. The first two are used to verify the color
circuitry, the third verifies the vertical scrolling circuit, and the fourth verifies
horizontal scrolling.

Screen One: red, green, blue, and white color bands are shown. Each band consists
of 16 levels of intensity. All 16 color palettes are represented, each palette is a
vertical strip across the screen (strips should not be discernible, but each color
should be a straight line across the screen). Because of the tight timing involved,
keystroke interrupts will cause the display to fitter.

Screen Two: This is the same as screen one except cyan, magenta, yellow, and
white color bands are shown. These colors are formed by adding together two
primary colors (blue + green, blue + red, red + green). The operator should see that
there are no gaps or missing scan lines in the display. If lines are missing, check the
three outputs on the Video Shifter for that color, and verify the values of the resistors
on the output. Too low a brightness setting on the monitor will cause the monitor not
to distinguish between fine levels, making it appear there are only four levels being
output.

The Video Shifter has four outputs for red (R0, R1, R2, R3), green (G0, G1, G2. G3)
and blue (B0, B 1, B2, B3). Each of these quadruples is summed together by a
resistor network to give 16 levels of intensity for each color, depending on which of
the outputs are on. The values of the resistors give different weight to each output.
The values of the resistor at R0 is twice that of R 1, which is twice that of R2, etc.
This allows us to get 16 equal steps on the summed outputs. For example, R0 on

30

and R 1, R2 and R3 off = 1/16. R0 off, R1, R2 and R3 on = 15/16. This signal then
passes through a transistor amplifier, and from there to the video monitor connector.

3.9.1 Symptoms and Fixes

1. Missing primary color. Check the output of the transistor amplifier. X402 is
blue, 0401 is green, X400 is red. Look for a staircase pattern (eight levels of
intensity). If the signal is there, trace forward to the video connector, if not,
trace backward to the Video Shifter, until the faulty component is found.

2. Primary colors present, secondaries missing or incorrect. Replace the Video
Shifter. Coarse change in the intensity (not a smooth dark to light transition).
Replace Video Shifter or look for a short on the output of one of the three
color outputs for the appropriate color.

3. Specks or lines on the screen. This can be caused by bad RAM; if RAM has
been tested and is good, replace the Video Shifter.

4. Wavering display, horizontal lines not occurring in the same place every time.
The processor may be getting extra interrupts (if the processor is required to
handle additional interrupts it will not have time to change all 16 color re isters
during a horizontal scan time). Examine the MFP interrupt request (pin

32).There should be an interrupt every 126 microseconds (2 display lines)
from Display Enable (pin 20). If additional interrupts occur, locate the source:
the inputs at pins 22–29 should all be high. If no external (to the MFP) source
for the interrupts is found, replace the MFP.

Note: If the keyboard is not connected, the input to the 6850 will be low,
causing continual interrupts.

Screen Three: This tests the vertical scrolling function. The screen is divided
diagonally, white on top/right, and black on the bottomlleft. The screen is scrolled,
making more of the screen black. until the entire width of the screen is black. Then
the reverse takes place, so that the black portion becomes smaller again. Any break
in the border or gaps or sudden shifts indicates a problem in the MCU or RAM.
Screen Four: This tests horizontal scrolling. A series of triangles moves across the
screen from right to left. The border should be a straight line and there must be no
gaps or sudden shifts. EXCEPT THERE WILL BE SOME SHIFTING ON THE TOP
TWO LINES. Any other irregularity indicates a problem in the MCU or RAM.

3.10 KEYBOARD TEST (K)

Two types of tests are run. The keyboard self–test is done first, and if this passes, a
screen is displayed representing the keyboard. If multiple tests have been selected,
only the selftest is run. The operator presses keys and observes that the
corresponding character on the screen changes (reverses background color). The
key will also be displayed in the lower half of the screen. The mouse buttons and
four directions are also shown on the screen. Connect the mouse, move in any
direction, and that arrow will flicker.

31

Note: It is possible, if pressing keys very rapidly, to leave the representation
of the key on screen in a depressed state. This does not indicate a problem
with the hardware.

The self–test checks communication between the CPU and the keyboard
microcomputer. checks RAM and ROM in the keyboard microcomputer, and scans
the keyboard for stuck keys.

3.10.1 Keyboard Error Codes

K0 Stuck key.

executing

K1 Keyboard not responding.

and no status was returned within the allowed time. The keyboard needs to be
replaced or the communication channel through the 6850 is not functional (see
Sec_ 3.5.1).

K2 Keyboard status error.

completion of the self–test, the keyboard sent an error status. Replace the
keyboard.

A key closure was detected while the keyboard self–test was

A command was sent to the keyboard processor

The self–test command was sent to the keyboard, on

3.11 MIDI TESTS (M)

This test sends data out the MIDI port, (data loops back through the cable) and
reads from the input and verifies the data is current. This also tests the interrupt from
the 6850 through the MFP chip. The LED in the loopback cable will blink as data is
sent (not all cables have the LED).

3 .11.1 MIDI Error Codes

M0 Data not received

drivers, loopback cable, and receivers to the input of the 6850. Replace the
defective component as found.

M1 WriteIRead data mismatch

read. Replace 6850.

M2 Input frame error.

M3 put parity error. Bad 6850 or bad driver or receiver causing noisy signal.

M4 Bad 6850 received a byte before the previous byte was read. Input data

overrun. Replace the 6850.

. Trace the signal from the output of the 6850, through the

. The data written was not the same as the data

Bad 6850 or bad driver or receiver causing noisy signal.

3.12 RS232 TESTS (S)

Note. Install Loopback Plug after power up.

32

First the RS232 control lines are tested (which are tied together by the loopback
connector), the data loopback is tested. Data is checked transmittinglreceiving using
a polling method first, then using interrupts.

Data is transmitted at 300. 600, 1200...19200 bps. Data transmission is performed
by the MFP and the 1488 and 1489 driver and receiver chips. Interrupts are a
function of the MFP. Control lines are output by the PSG and input on the MFP. Note
that this test does not thoroughly test the drive capability of the port. If the unit
passes but fails in use, it is likely that the 1488 or 1489 chips are bad.

3.12.1 RS232 Error Codes

S0 Data Not Received. Check signal path, MFP pin 8 to J204 pin 2 via 1488 to

J204 pin 3 to MFP pin 9 via 1489.

S1 Data Mismatch.

signal. May be bad driver, receiver, or MFP.

S2 Input Frame Error.

failure.

S3 Input Parity Error.

S4 Input Data Overrun

byte. MFP failure.

S5 No IRQ.

failure.

S6 Transmit Error.
S7 Transmit Error lnterrupt.

an interrupt, and the MFP did not respond.

S8 Receive Error Interrupt.

an interrupt, and the MFP did not respond.

S9 RI/DTR Connection.
SA DCD/DTR Connection.
SB RTS/CTS Connection.

CPU did not detect an interrupt by the MFP. MFP or GSTMCU

Data read was not what was sent. Check integrity of the

Incorrect time between start and stop bits. Probable MFP

Input data had incorrect parity. Probable MFP failure.

. A byte was received before the CPU read the previous

MFP transmitter failed.

An error condition was created intentionally to cause

An error condition was created intentionally to cause

Signal sent at DTR is not detected at RI.

Signal sent at DTR is not detected at DCD.

Signal sent at RTS is not detected at CTS.

3.13 AUDIO TEST (A)

This test requires the operator to decide if the unit passes or fails.
There are two sound generating circuits: the Programmable Sound Generator (PSG)
and DMA sound. Both are controlled by the LMC1992 chip and associated circuitry,
so if the unit fails both parts of the test, look at the LMC1992 chip first.

3.13.1 PSG Sound

A sound is output on each of the three programmable sound generator channels.
The 518 sound is a sweep from low to high frequency. Verify that sound can be
heard throughout the range, with no dropping of audio level.

33

3.13.2 DMA Sound

Connect an oscilloscope at the stereo output jacks. The setting should be 1
ms/division, 5 volts/division. There are four parts to this test. After observing the
signals, proceed to the next part by pressing the space bar. In each case, the output
signal amplitude should go from 0 volts to maximum amplitude in steps.

a. Mono 1 kHz:

sine wave and be 5–6 volts in amplitude.

b. Stereo 1 kHz/500 Hz

frequencies. As one channel increases in amplitude, the other channel
decreases. Maximum amplitude is 5–6 volts.

c. Treble:

about 6 volts.

Both channels output the same signal; it should approximate a

: Verify that the right and left channels have correct

A 12.5 kHz signal is output on both channels. Maximum amplitude is

d. Bass:

A 50 Hz signal is output on both channels. Maximum amplitude is about

6 volts.

3.14 TIMING TESTS (T)

These tests are run at power–up as well as being selectable from the menu. The
MFP timers, the GSTMCU timing for VSYNC and HSYNC, and the Memory
Controller video display counters are tested. The video display test redirects display
memory throughout RAM and verifies that the correct addresses are generated. Odd
patterns may flash on screen as this test is run. There are two tests which check the
bus timing for the 1772 and PSG chips. An error message is printed on the screen
then the test is run. If the test passes, the message is erased. If not, a Bus Error will
occur and the message will remain. If a terminal is connected to the RS232 port, the
message will not be erased, but "Pass" will be printed.

3.14.1 Timing Test Error Codes

T0 MFP Timer Error.

an interrupt on counting down.

T1 Vertical sync.

period.

T2 Horizontal Sync.

time period.

T3 DispIay Enable.

generating an interrupt.

T4 Video Counter Error.

addresses for the display. This will result in a broken–up display in some or all
display modes.

T5 PSG Bus Error.
T6 1772 Bus Error.

One or more of the four timers in the MFP did not generate

GSTMCU is not generating vertical sync in the required time

GSTMCU is not generating horizontal sync in the required

GSTMCU is not generating DE output or the MFP is not

The memory controller is not generating the correct

The PSG chip is defective.

The 1772 chip is defective.

34

3.15 DMA TESTS (D)

Four sectors (2048 bytes) of data are written to the RAM on the port test fixture via
high speed DMA, then read back and verified. This test is repeated many times for
RAM addresses throughout the range of RAM.

3.15.1 DMA Test Error Codes

D0 DMA Timed Out.

or Memory Controller, or the HDINT interrupt was not processed by the MFP.
The failure can be isolated by seeing if the DMA Controller responds to HDRQ
from the test fixture with ACK. Verify the MFP by seeing that the HDINT input
causes an INTR output from the MFP.

D1 DMA Counter Error.

Memory Controller or DMA Controller is bad.

D2 Data Mismatch Error.

as the data sent. Replace the DMA Controller If the problem persists, check
the data lines to the port for opens and shorts. A third possibility is that a
defective 1772 is loading the bus.

D3 DMA Controller Not Responding

No DMA occurred due to faulty DMA Controller, GSTMCU,

The number of bytes transferred was incorrect. The

The data received from the DMA port was not the same

.

3.16 FLOPPY DISK TESTS (F)

In a single test mode, a menu is displayed showing seven options:

1. Quick Test. For each disk installed, formats, writes, and reads tracks 0, 1,
and 79 of side 0. If double sided, formats and writes track 79 of side 1 and
verifies that side 0 was not overwritten. If no disks are installed, checks to see
what drives are online and if they are double or single sided. To assure that
the drives are correctly tested, the operator should install menu option 6
before calling the test. Once the test is run, the drives become installed, and
will be displayed on the menu screen.

2. Read Track. Continuously reads a track, for checking alignment with an
analog alignment diskette. The choice of track to be read may be input by the
operator. If [Return] is pressed without entering a number,

3. Interchangeability Test. Checks to see if diskettes from two disk drives each
can be read by the other disk drive.

4. Disk Exerciser. A more thorough disk test; tests all sectors used on the disk
for an indefinite period of time.

5. Copy Protect Tracks. Tests tracks 80–82, which are used by some software
companies for copy protection. Not all manufacturers disk drives will write to
these tracks.

Note: This test is for information only and should not be used to reject a
mechanism.

6. Test Speed. The rotational speed of the drive is tested and displayed on the
screen as the period of rotation. The acceptable range is 196–203

35

milliseconds. The highest and lowest values measured are displayed. The test
stops when any key is pressed.

7. Install Disks. Specify how many and what type of disk drives to test.

One additional test which can be performed is testing the write protect detection.
Slide the write protect tab to the protected position, and run test # 1. You should see
'F5 Write Protected– displayed if the drive has been installed, or 'unable to write oisk'
displayed if the drive has not been installed.

If more than one test is selected from the Main Menu, the Floppy Menu will not
appear, but the quick Test will be selected automatically.

3.16.1 Floppy Disk Test Error Codes

No Floppies Connected – The controller cannot read index pulses. The cable may
be improperly connected, or the drive has no power, or the drive is faulty.

F0 Drive not selected. Drive was installed, but failed attempting restore (seek

track 0). Check connection of cables, power to drive. Verify that the light on
the front of the drive goes on. Listen for the sound of the head seeking (the
slide on the diskette should open). If all this occurs, TR00 (pin 23 on the 1772)
should go low. If so, check for an interrupt on pin 28 of the 1772. If none,
replace the 1772. Else trace the interrupt to the MFP, verify that the MFP
responds by asserting INTR. If the drive is not being selected (no light), check
the PSG chip. Pin 20 should go low when drive A is selected, and pin 19
should go low when drive B is selected. If not, replace the PSG.

F1 Error of previous version

"Error Writing" (or reading or formatting), and displays a more specific error
message, e.g., "F9 CRC error."

F2 Error of previous version

"Error Writing" (or reading or formatting), and displays a more specific error
message, e.g., "F9 CRC error."

F3 Error of previous version

"Error Writing" (or reading or formatting), and displays a more specific error
message, e.g., "F9 CRC error."

F4 Seek Error.

sent to the drive. Probable failure in the 1772, but the drive is also suspect.

F5 Write Protected.

the WP input (1772, pin 25) is getting low during the test; if it is then the 1772
is defective: if not, the problem is with the disk drive.

F6 Read Compare Error.

be written. Check in the following order: diskette, disk drive, 1772, and DMA
Controller.

F7 DMA Error.

the DMA Controller. If error persists, check FDRQ while running the test. It
should normally be low and go high with each data byte transferred. If stuck
high, push the reset button and verify that MR (1772, pin 13) goes low. If not,
trace RESET to its source. If MR is OK, but FDRQ is still stuck, replace the

1772.

Verify that the STEP, MO, and DIRC outputs from the 1772 are

Check the write protect tab on the diskette. If OK, verify that

DMA Controller could not respond to a request for DMA. Replace

that has been deleted. Error message now says

that has been deleted. Error message now says

that has been deleted. Error message now says

Data read from the disk was not what was supposed to

36

F8 DMA Count Error. Replace the Memory Controller, if that does not fix it,

replace the DMA Controller.

F9 CRC Error.
FA Record Not Found

diskette, drive or 1772. If the test fails drive A but not drive B, the 1772 is not
at fault (likewise fails B but not A).

FB Lost Data.

transfer data to the DMA Controller. If DMA Port passes the test, the 1772 is
probably bad. The DMA Controller could also be at fault.

FC Side Select Error – Single Sided Drive.

diskette, but writing side 1 caused side 0 to be overwritten.

FD Drive Not Ready.

disk drive. Verify by checking another drive. Could also be a faulty 1772.

The diskette or disk drive may be bad, else replace the 1772.

. The 1772 could not read a sector header. May be a bad

Data was transferred to the 1772 faster than the 1772 could

The test tried to write both sides of the

The forma/lwrite/read operation timed–out. Probably a bad

3.17 PRINTER AND JOYSTICK PORT TESTS

The ST Port Test Fixture and STE Game Port Test Fixture must be properly
connected for this test.

The port test fixture is used to test the parallel printer port. DMA, and joystick ports.
The parallel port test writes to a latch on the test fixture and reads back data. The
joystick port tests output data on the parallel port, which is directed through the test
fixture to the joystick ports. The keyboard reads the joystick data in response to
commands from the CPU. The cables connecting the joystick ports to the test fixture
must not be reversed, or the printer and joystick tests will fail.

The game controller port test simulates joystick direction input, fire button input,
paddle controller input, and light gun inputs. The STE game port test fixture used the
joystick outputs and control lines from the STE Port Test Fixture to generate the
signals input to the STE.

3.17.1 Printer/Joystick Error Codes

P0 Printer Port Error.

Verify that the data lines on the PSG chip (pins 6–13) are toggling when the
test is run. If not, run the RS232 test. If the RI–DTR and DCD–DTR errors
occur, the chip is probably not being selected. Check if the chip selects are
being activated and the 2 MHz clock is present. If the PSG is selected and not
outputting signals, replace it. If the data lines toggle, verify continuity. Also
verify that J11 (Joystick 0) pin 3 is pulled up. Verify the test fixture is good by
testing another computer. If it is OK, replace the PSG

P1 Busy Input Error.

output from the PSG is not functioning, or Joystick 0 pin 3 is not connected. If
the P0 error also occurs, see handling for that. Otherwise, look for a signal
arriving at MFP pin 22 from J5 pin 11. If no signal at J5, the test fixture may be
bad. Verify with another computer.

Data read from the printer port was not what was written.

The input to the MFP is not being read, or the STROBE

37

J0 Joystick Port 0. The keyboard input is not functioning. If the busy input error

occurs, fix that first. Otherwise, replace the keyboard. If error persists, check
continuity from J11 , pins 1. 2, 3, 4 to J 12 pins 12, 10, 9, 8 respectively.

J1 Joystick Port 1.

occurs, fix that first. Otherwise, replace the keyboard. If error persists, check
continuity from J11 , pins 1, 2, 3, 4 to J12 pins 7, 5, 4, 3 respectively.

J2 Joystick Time–Out.

printer port and routing it via the test fixture to the joystick ports. Joystick
inputs are detected by the keyboard and sent to the CPU via the 6850. This
error can be caused by printer port failure (code P0), keyboard failure,
keyboard–CPU communication line 1, or a faulty test fixture. If the power–up
keyboard test passes, this eliminates any problem with keyboard–CPU
communication.

The keyboard input is not functioning. If the busy input error

Joystick inputs were simulated by outputting data on the

J3 Left Button Input.

keyboard. On the STE, also check continuity from J10 pin 6 to J12 pin 11.

J4 Right Button Input.

keyboard. On the STE, also check continuity from J10 pin 6 to J12 pin 6.

J5 Aux Joystick Direction.

used to drive the input via the test fixture. The hexadecimal data following
corresponds to the bits read from latches U510 and 0512, where a 1 indicates
an error. For example, 0002 indicates an error at J500 pin 3.

J6 Aux Fire Sutton. Fire buttons are read from U509. Signal is driven via the test

fixture from the output of U51 1.

J7 Paddle.

fixture. This current charges the RC network on the STE, varying the output
pulse of the LM556. The pulse width is measured by the GSTMCU chip.

J8 Light Gun.

(the video address counter is used to find the position of the screen). The MCU
should return the XlY coordinates of the screen position. If the XPEN signal is
toggling and this error occurs, there is a problem with the GSTMCU.

The inputs are driven by either 5V/100 ohms or 5VI1 M on the test

The light gun (XPEN) input is toggled at three points on the screen

If P1 error occurs, fix that first. Otherwise replace the

If P1 error occurs, fix that first. Otherwise replace the

Game controller port (J500, J501) direction bits. 0511 is

3.18 MONOCHROME MONITOR ( H )

If this test is selected while a color monitor is connected, a message is displayed to
connect the monochrome monitor. The CPU waits for an interrupt from the
MONOMON input to the MFP, and when received (the operator connects the
monochrome monitor), changes the display to high resolution. The display screen
will reverse every two seconds. When the operator sees the display is correct, he
unplugs the monochrome monitor and re–connects the RGB monitor and the display
should return to normal.

3.19 HARD DISK WRITE/READ (J)

This tests the hard disk interface by writing and reading one complete track of the hard disk.
It is not intended to test the hard disk drive, but tests the computer DMA circuitry. The test

38

has been found to be more effective than the DMA test for some types of failures; these
show up as "Data Compare" errors.

The test program will save the data on the cylinder used for testing and restore the data
when the test is done (when "quit" or "park heads" is selected).

NOTE. Always back up the hard disk before running this test. Bad hardware can still
destroy the data on the disk.

The test will run until the operator presses the (Esc) key. There is no "Pass" condition. A
failure will usually show up within a few seconds if it is going to occur at all. The following
messages can appear if there is an error:

Controller Not Responding There is no communication between the computer and hard
disk. Cycling power on the hard disk may correct this condition.

Operation Timed Out The computer sent a command, which was accepted by the hard
disk, but the hard disk did not return a completion code in time.

Command Error The hard disk attempted to execute a command, but an error occurred in
the hard disk.

DMA Count Error After completing a data transfer, the byte count of the data in the
computer memory controller was incorrect.

Data Compare Error This is followed by the data written to the disk and the data read from
the disk. The error is the condition this test was meant to detect. The circuitry involves the
custom LSI chips (GSTMCU, Memory Controller, and DMA Controller). The comparison is
done by the CPU, and it has found an error in the read/write buffers in memory.

3.20 GRAPHICS CHIP BLiT (G,Y)

Two tests are available for this chip. The "Short BLiT Test" checks the ability of the
BLiTTER to move blocks of memory around and perform logical operations on the
data. No patterns appear on the screen. If an error is detected, one of the error
codes (G1–G12) is displayed.

In the "Long BLiT Test", a triangle is drawn on the screen and rotated 180 degrees
until a rectangle is formed. If a color monitor is used, two identical images will be
drawn. If an error occurs, a message will appear telling you to replace the BLiTTER.

Corrective action for any error is the same:

a. Verify the jumpers for the BLiT chip are installed correctly.

b. Replace the chip (and if that does not cure the problem, replace the 68000).

3.21 ERROR CODES QUICK REFERENCE

This is a brief summary of all error codes which may occur when running the
diagnostic.

3.21.1 Initialization

Error occuring before the title and menu appear. (see section 3.5.1)

I1 RAM data line is stuck.

I2 RAM disturbance. Location is altered by write to another location.

39

I3 RAM addressing. Wrong location is being addressed.

I4 MMU error. No DTACK after RAM access.
I5 RAM Sizing Error. Uppermost address fails.

I6 Bus Error Handling Failed. Bus Error occurred (on purpose), but caused a

crash (e.g. System was unable to read the vector from RAM).

I7 Bus Error not detected. Glue not asserting Bus Error or the signal is not

reaching the CPU.

3.21.2 Exception (may occur at any time.)

E1 Not used
E2 Not used

E3 Not used
E4 Not used
E5 Not used

E6 Autovector Error. IPL0 is grounded or 68000 is bad.
E7 Spurious Interrupt. Bus error during exception processing. Device interrupted,

but did not provide interrupt vector.

E8 Internal Exception (generated by 68000).

E9 Bad Instruction Fetch.

EA Address Error. Tried to read an instruction from an odd address or read or

write word or long word at an odd address. Usually this error is preceded by a
bus error or bad instruction fetch.

EB Bus Error. Generated internally by the 68000 or externally by GSTMCU.

Usually caused by device not responding. Displays the address of the device
being accessed.

3.21.3 RAM

R0 Error in low memory, possibly affecting program execution. R 1 Error in RAM

chip.

R2 Address Error. Bad RAM chip or Memory Controller. Address line not working.

R3 Address error at 64K boundary.
R4 Error during video RAM test. Bad RAM chip.

3.21.4 Keyboard

K0 Stuck key.

K1 Keyboard controller is not responding.
K2 Keyboard controller reports error.

40

3.21.5 MIDI

M0 Data not received.

M1 Data received is not what was sent. M2 Data input framing error.

M3 Parity error.
M4 Data overrun. Byte was not read from the 6850 before next byte arrived.

3.21.6 Printer and Joystick/Game Ports

P0 Printer port error.

P1 Busy (printer port input) failed.

J0 Joystick port 0 failed.
J1 Joystick port 1 failed.
J2 Joystick (keyboard controller) timed–out.

J3 Left button line failed.
J4 Right button line failed.
J5 Auxiliary joystick direction (game controller port).

J6 Auxiliary fire button (game controller port).

J7 Paddle (game controller port).
J8 Light gun (game controller port).

3.21.7 RS232

S0 Data not received.

S1 Data received is nat what was sent.
S2 Data input framing error.

S3 Parity error.
S4 Data overrun. Byte was not read from the MFP before the next byte arrived.
S5 IRQ. The MFP is not generating interrupts for transmit or receive.

S6 Transmitter error – MFP
S7 No interrupt from transmit error (MFP).

S8 No interrupt from receiver error (MFP).

S9 DTR–RI. These signals are connected by the loopback connector. Changing

DTR does not cause change in RI.

SA DTR–DCD. Same as S9 for these signals.
SB RTS–CTS. Same as S9 for these signals.

41

3.21.8 DMA

D0 Time–out. DMA did not take place, or interrupt not detected.

D1 DMA Count Error. Not all bytes arrived. Possible Memory Controller or

GSTMCU error.

D2 Data Mismatch Error.
D3 DMA Controller not responding.

3.21.9 Timing

T0 MFP timers failed.

T1 Vertical sync timing failed.

T2 Horizontal sync failed.
T3 Display Enable Interrupt failed.

T4 Memory Controller video address counter failed.

T5 PSG Bus test. PSG chip is causing a bus error by staying on the data bus too

long.

T6 1772 Bus test. 1772 chip is causing a bus error by staying on the data bus too

long.

3.21.10 Floppy Disk Drive

F0 Drive offline. Not responding to restore (seek track 0).

F1 Format error. The message will say 'error writing' (or reading) and display

the specific error found.

F2 Error Writing. Gives specific error found.
F3 Error Reading. Gives specific error found.
F4 Seek error.

F5 Write protected.
F6 Data compare. Data read not equal to data written.
F7 DMA error.

F8 DMA count error (GSTMCU).
F9 CRC error.

FA Record not found.
FB Lost data.

FC Side select error.
FD Drive not ready. Timed–out performing the command.

42

3.21.11 BLiTTER

G1 Halftone RAM (internal RAM in BLiT chip).

G2 Endmask.

G3 Operation.

G4 Halftone Op.
G5 Skew.

G6 Reverse Bit.
G7 Force Extra Source Read.
G8 Smudge.

G9 X Count.
GA Y Count.
GB Time–out.

GC Address Count.

BUS ERROR during BLiT Test – Replace BLiTTER chip.

43

SECTION FOUR: DISASSEMBLY/ASSEMBLY

4.1 STE DISASSEMBLY

Use the following procedure to disassemble the STE. Refer to Assembly Drawing,

Section 6.

4.1.1 Top Cover/Keyboard Removal

1. Turn unit upside down

2. Remove the 6 screws from the square holes. These fasten the top case to the

bottom. If the printed circuit board is to be exposed, or the disk drive is to be
removed, also remove the three screws from the round holes. These hold the
disk drive in place.

3. Turn the unit upright and remove the top case.

4. Remove the keyboard by unplugging the keyboard harness connector located

in the right front corner.

4.1.2 Disk Drive Removal

Remove the the screws in the round holes. Lift the disk drive slightly and unplug the

power harness connector and the ribbon cable.

4.1.3 Power Supply Removal

The power supply may be left in place and the upper shield removed in one piece for
troubleshooting, as follows:

1. Remove one screw on the right side of the power supply shield. Remove
three screws from the back panel EMR shield to the power supply shield.

2. Straighten the two twist tabs.

3. Lift off the power supply shield from the rear.

4. Unplug the wire harness connector in the right front corner of the power

supply.

5. Remove two screws at front corners of power supply.

6. Lift the power supply up out of the main assembly.

4.1.4 Removal of Main Assembly from Bottom Case

1. Remove three screws from the front of the shield/printed circuit board
assembly.

2. If power supply has not already been removed, remove the two screws
securing the power supply to the case at the front corners of the power
supply. This can be done by inserting a screwdriver through the holes in the
power supply shield or by removing the shield.

3. Lift the assembly up from the front and pull forward.

44

4.1.5 Removal of Shield from Printed Circuit Board

1. Straighten twist tabs (usually four).

2. Remove copper tape (if present).

3. Lift upper shield straight up.

Note. Now that the major components are exposed, this is a convenient

configuration for troubleshooting. The keyboard and disk drive may be re­connected and placed off to the side if those components are needed.

4. Lift printed circuit assembly away from bottom shield. It may be necessary to
pull the
twist tabs away from the board slightly.

4.2 STE RE–ASSEMBLY

1. Place insulation panel on Bottom Shield.

2. Place Main Board on top of Bottom Shield over insulator panel.

3. Plug in power supply connector and position power supply with tabs in slots.

4. Align tabs on bottom shield with slots on top shield and fit top shield over main

assembly. Twist the tabs to lock in place.

5. Place assembly in lower plastic case.

6. Fasten the power supply to the bottom case at both front corners with two

screws. This can be done with the power supply shield in place, using a
magnetized screwdriver to hold the screw, or by by removing the shield.

7. If power supply shield was removed from main shield, position it over the
power supply. Front tabs slide under slots. Twist rear tabs and replace the
screw. Replace three screws holding back panel EMR shield to the power
supply shield.

8. Plug disk drive power and ribbon cables into drive (cables go under shield),
and position drive over standoffs.

9. Replace four screws at the front edge of the main assembly.

10. Connect keyboard harness to main board through the opening in the upper

shield. and place keyboard on the supporting ribs of the bottom case.

11. Place the top cover over the assembly.

12. Turn over the assembly and replace the nine screws. The three longer screws

go in the round holes to secure the disk drive.
Warning: It is strongly recommended that the computer be retested once in

plastic to make sure that the reassembly was done correctly and there are no
shorts to the shield.

45

SECTION FIVE: SYMPTOM CHECKLIST

This section gives a brief summary of common problems and their most probable
causes. For more detail, refer to the section of troubleshooting in this document, or
the Diagnostic Cartridge Troubleshooting Guide.

5.1 DISPLAY PROBLEMS

Symptom

Black Screen No power (check LED), bad GSTMCU chip, bad Video

White Screen Video Shifter, GSTMCU, Memory Controller, DMA

Dots/Bars on Screen RAM, Memory Controller, Video Shifter. Use the

One Color Missing Video cable or connector. Video summer, buffer, Video
Shifter. Check signals with oscilloscope.

Probable Cause

Shifter. See Section 3_3. Troubleshooting a Dead
Unit.

Controller, 68000. Use diagnostic cartridge with
terminal connected via RS232 port.

diagnostic cartridge.

Monochrome Monitor Verify that the monochrome monitor detect bit is being
Fails to Synch but grounded when monochrome monitor is plugged in.
Color Monitor Okay Check MFP GPIP bit 7; replace MFP.

Scrambled Screen GSTMCU, Memory Controller. Use diagnostic

Cartridge.

TV Output Bad Modulator, phase locked loop. Trace signal with
oscilloscope.

5 . 2 DISK DRIVE PROBLEMS

Symptom

Disk Won't Boot Power supply. 1772, DMA Controller, PSG chip, disk drive

Disk Won't Format 1772, DMA Controller, disk drive.

System Crash after Data on diskette, disk drive, 1772, DMA, or GSTMCU.
Loading Files Swap diskette, retry. Use diagnostic cartridge to check

1772, DMA Controller, GSTMCU; replace disk drive.

Probable Cause

external ACSI buffer, external HD IRQ lines shorted to
ground. See if Select light goes on, if not, check PSG
outputs. Listen for motor spinning. If not, check power
supply. Swap disk drive or try external drive. If not working,
check DMA Controller 1772 with diagnostic chart.

5.3 KEYBOARD PROBLEMS

46

Symptom Probable Cause

Red Screen: Keyboard Bad keyboard, 6850, MFP.
not responding

5.4 MIDI PROBLEMS

Symptom

Red Screen: Error Bad opto–isolator chip, 6850, inverter (74LS06).
Codes M0, M1, M2, See section 3.11.1
M3. or M4

Probable Cause

5.5 RS232 PROBLEMS

Symptom

Red Screen: Error Bad MFP, 1489 receiver, 1488 driver, or PSG chips,
Codes S0 through SB ±12 VDC:DC inverting power supply. See section

Probable Cause

3.12.1

5.6 PRINTER PORT PROBLEMS

Symptom

Probable Cause

Red Screen: Error Bad PSG, MFP chips. See section 3.17.1
Codes P0. P1:

Shadow Printing Bad ASCI port cables,

terminator resistors, bad LS244, LS245 drivers.

5.7 HARD DISK PORT PROBLEMS

Symptom

Red Screen: Error Bad DMA Controller, Memory Controller, 1772 (loading the
Codes D0, D1, D2 bus). See Section 3.15_1

Probable Cause

5.8 DMA SOUND

Symptom

No Sound +8V regulator, ±supplies, 1992 Volume Control, R542, R543

Probable Cause

47

SECTION SIX: DIAGNOSTIC FLOW CHARTS

This section summarizes in diagrammatic form the steps taken in troubleshooting the STE
using the diagnostic cartridge. The details of using the cartridge are not shown; this shows
the context in which the cartridge would be used, including some problems for which the
cartridge would not be useful. Usage of the cartridge is covered in the troubleshooting guide.
In general, the user would run all tests, look up errors in the troubleshooting guide, and take
the action recommended.

Although a thorough understanding of the system may be necessary in solving some
problems, in most cases following the flowchart, reading the documentation on the
diagnostic cartridge where necessary, and swapping out the indicated component(s) will
result in repair of the problem.

6.1 REPLACEMENT PROCEDURES

Where replacement is indicated, replace the component (if more than one is indicated,
replace one at a time) with a known good part. If other components are later replaced, verify
whether the first part is good by replacing it in the system once the system has been
repaired.

6.2 HANDLING OF INTEGRATED CIRCUITS

Warning. Extreme care should be taken when handling the integrated circuit chips. They are
very sensitive to static electricity and can easily be damaged by careless handling. Keep
chips in their plastic carriers or on conductive foam when not in use. The operator handling
such components should wear a properly grounded ground strap and work on a properly
grounded conductive surface.

48

Figure 6–1: STE Diagnostic Flow Chart

49

Figure 6–2: STE Diagnostic Flow Chart

50

Figure 6–3: STE Diagnostic Flow Chart

51

Figure 6–4. STE Diagnostic Flow Chart

52

SECTION SEVEN: PARTS LIST

ASSY NO: CA400338-201

PART NUMBER DESCRIPTION LOCATION/QUANTITY

CA200133-001 1 ASSY CABLE COAXIAL (NTSC) 1
C070349-001 CORD AC WITH POLY BAG 1
CA400607-001 DISK LANGUAGE USA IDD 1
C026406-001 MANUAL OWNER'S 1
0100536-001 MANUAL BASIC MEGA/ST/STE 1
C 100971-001 MANUAL PCM 1 ENG. 1
0300986-001 MANUAL ADDENDUM STE ENG. 1
CA070025 MOUSE MEGA/ST/STE 1
CA400339-201 ASSY MAIN 1040 STE W/MOD USA 1

ASSY NO: CA400339-201

PART NUMBER DESCRIPTION LOCATION/QUANTITY

CA400343-003 ASSY TOP CASE 1040 STE 1
CA400344-001 ASSY BTM CASE NTSC 1
0301430-001 SHIELD REAR STE FCC USA/CAN/GE 1
CA400340-1 11 ASSY PCB 1040 STE USA W/MOD 1
CA070059 003 ASSY PSU 110V STE USA/CAN 1
CA070057-005 ASSY K/B CAN ST 1
C 103704-001 FDD 1 MB 3.5" SONY WILED 1

ASSY NO: SE400340-111

PART NUMBER DESCRIPTION LOCATION/QUANTITY

CA400329-101 ASSY PCB SUB STE NTSC WIMOD
CA400366-001 ASSY TOS ROM 1.62 USA STE U102 - 103
CA400495-001 ASSY SIM 256K x 1 x (8) DIP U600 - 603

ASSY NO: CA400366-001

PART NUMBER DESCRIPTION LOCATION/QUANTITY

C301 163-002 IC TOS ROM 1.62 USA HI STE U102
C301 164-002 IC TOS ROM 1.62 USA LO STE U103

ASSY NO: CA400495-001

PART NUMBER DESCRIPTION LOCATION/QUANTITY

C398152-001 PCB SIMM 256K x 8 DIP STE 4
0101743-002 IC DRAM 256K x 1 120 NS 16P 16
0101207-224 CAP CER 22UF 50V AX 2

ASSY NO: CA400329-101 DESC: PCV SUB ASSY STE WIMODULATOR

PART NUMBER DESCRIPTION LOCATION/QUANTITY

0300780-001 SCHEMATIC DIAGRAM
CA070023-009 ASSY CABLE 4P CONN 280 MM J302
CA070024 CABLE FLAT ASSY 34P J303
0070335 BANDAGE PLATE

53

0025993 CRYSTAL 2.4576 MHZ Y200
0398066-001 OSC 8.010613 MHZ U303
0398068-001 OSC 32.215905 MHZ U402
CO 19748 IC 555 TIMER 8P U 104
0398739-001 IC OMA CONTL 4140 40P U300
0025983 IC 'YM-2149 SOUND 40P U202
0025984 IC 68901 MFP 48P U203
0025985 IC 6850 ACIA 24P U200,201
0025986 IC MC1488 RS232C DRIVER 14P U206
0025988 IC PC900 PHOTO COUPLER 6P U208
0025989 IC LM556 DUAL PRECISION 14P U513,514
0026028-002 IC 1772 FDD CONTROLLER 28P ST U301
0070447 IC TL497A SW REGULATOR 14P U204,205
01001 17 IC MC1377 ENCODER 20 PIN U403
0101609-006 IC 7406 DIP 14P U210,305
C01610-257 IC 745257 DIP 16P U405
C 10161 1-004 IC 74LS04 DIP 14P U211
0101611-074 IC 74LS74 DIP 14P U304,306
0101611-086 IC 74LS86 DIP 14P U209
0101611-164 IC 74LS164 DIP 14P U900
0101611-244 IC 74LS244 DIP 20P U307,509,510,512,632
0101611-245 IC 74LS245 DIP 20P U302
0101611-373 IC 74LS373 DIP 20P U511
0101643 IC ST GLITTER CUSTOM 68 PIN U101
0101739-001 IC 1489A RS-2320 RECEIVER 14P U207
0300259-257 IC 74F257 DIP 16P U405
0300259-374 IC 74374 DIP 20P U500,501
0300588-001 IC STESHFTR 84P NATIONAL U401
0398055-001 IC LF347 14P U504,507
0398056-001 IC MF4-100 8P U505,506
0398057-001 IC DAC0802 16P U502,503
0398058-001 IC LMC 1992 28P U508
0398061-001 IC 68000 PLCC 68P U100
0070734-002 IC LM78L82 VOLTAGE REGULATOR 3P U500
34-2N3904 IC TRAN 2N3904 3P Q400 - 404
0101008-472 RES NET 4.7K 5% 9P BUS P101-103, 500-502
0070448 RES NET SIP 10K 9P P104,105,600
C 101008-122 RES NET 1.2K 9P P100
0070157-004 CAP ELEC 47uF 16V RA C566.567
0398121-001 CAP ELEC 47uF 16V 20% RA C416
0398069-001 CAP 15UF 25V +/-2 RA TANTL 0% C420,424.426
0070157-005 CAP ELEC 100uF 16V RA C423,417
0070157-008 CAP ELEC 470uF 16V RA C415
0070450-001 CAP ELEC 4.7uF 25V 20% AX NPO C202,204,205,215
0070450-002 CAP ELEC 10uF 35V 20% RA C100,542
0070450-008 CAP ELEC 470uF 35V 20% AX C216
0070499-001 CAP ELEC 22uF 16V +-20% AX C102
0070499-003 CAP ELEC 47uF 16V 20% AX 0508,520,525,529,535

537.541, 0543, 544, 546,
547
0070499-004 CAP ELEC 100uF 16V C107,110,600,558,
561, 564
0070566 CAP ELEC 10uF 50V C433
0101205-472 CAP ELEC 4700UF 16V AX C103
0070741-007 CAP MICA 680PF 50V +-5°lo RA C526,532,539,548
0101403-102 FILTER NOISE TDK L200-202,204-207,209­ 227, 511-527, L300-310,
404-409,504-507, 509,510
0070241-002 FILTER NOISE *ALT* ZJS5101-02
0100091-002 FILTER NOISE *ALT* DSS306-55B 102M

54

0101403-002 FILTER NOISE *ALT* ZJSR5101-102
0101404-002 FILTER NOISE *ALT* STB102KB
0100210 COIL VARIABLE 24uH L403
0100209 DELAY LfNE 3.58 MHz DL1
0070119 SW PUSH SP J312U S100
0100184 RF MODULATOR ST NTSC ST MOD
0014386-13 SKT UC IUO 32 POS U102,103
0070120-002 SKT 68P PLCC U100,101
0070718 PLCC STOPPER 68P
0100384-001 CONN SKT PLCC 84P STG U401
0398063-001 UC SOCKET SIMM 30P U600,603
0070033 CONN DIN 5P MIDE I RIGHT ANGLE J200,201
0070129 CONN 40P RIGHT ANGLE J103
0070130-002 CONN DB19S HARD HOOK TYPE J301
0070131 CONN DIN FLOPPY DISK 14P J304
0070132-002 CONN DB 25P RS232C HOOK TYPE J204
0070133-002 CONN D 25B FEMALE RT-ANGLE J203
0070134 CONN 13P DIN VIDEO J400
0070445 CONN SINGLE INLINE 6P J100
0070446 CONN SINGLE INLINE 8P J202
0398064-002 CONN D SUB 15P 3 ROW FEMALE J500,501
0398065-001 CONN PHONO RIGHT ANGLE J502,503
0100287-070 WIRE SOLID AWG26 200MM

ASSY NO. SB400329-101

PART NUMBER DESCRIPTION LOCATION

0060607 DIODE 1N4148 D100,200-203
31-1N914 DIODE 1N914 SIGNAL 'ALT' SILICON
0060629 RES JMPR 0 R405,451,459
0101004-1002 RES MF AX 10K 1% 1/4W R501-504,505,506,
510-515
0101004-1003 RES MF AX 100K 1% 1/4W R545,546
C 101004-1801 RES MF AX 1.8K 1% 1/4 W R507, 516
0101004-8201 RES MF AX 8.2K 1% 1.4W R500,508,509,517
14-50101A RES CF 1Ω 5% 1/4W R211
14-51001A RES CF 10Ω 1/4W 5% AX R542,543
14-51011A RES CF 100Ω 1/4W 5% AX R441
14 51021A RES CF 1k 1/4W 5% AX R102,107,209,220,
300-306,406,413,421,
429, 430, 440.442, 470, 541,
540, 8520, 533, 463
14-51031A RES CF 10k 1/4W 5% AX R100,103105,210,525,
527, 530, 538
14-51051A RES CF 1M 1/4W 5% AX R518,521,528,535
14-51221A RES CF 1.2K 1/4W 5% AX R106,208,213,431
14-51231A RES CF 12K 1/4W 5% AX R101,206.411,416,422
14-51511A RES CF AX 150 1/4W 5% R448
14-5152IA RES CF 1.5K 1/4W 5% AX R412,417,424,452
14-5202IA RES CF AX 2K 1/4W 5% R408,423,433
14-52211A RES CF AX 220Ω 1/4W 5% R200,202,204,205,
207, 307
14-5222lA RES CF AX 2.2k 1/4W R109,8119,120
14-5270IA RES CF AX 27Ω 1/4W 5% R438
14-52741A RES CF 270k 1/4W 5% R590,591
14-5302IA RES CF 3k 5% 1/4W R414,418,426
14-53621A RES CF AX 3.6k 1/4W 5% R524,537
14-53921A RES CF AX 3.9k 1I4W 5% R214
14-54701A RES CF AX 47Ω 1/4W 5% R308-311

55

14-54711A RES CF AX 470Ω 1/4W 5% R519,523,529,536
14-54721A RES CF AX 4.7K 114W 5% R110,201,215-219,472
14-55R1/A RES CF AX 5.1 1/4W 5% R203
14-5513/A RES CF AX 51K 1/4W 5% 531.539,471
14-55621A RES CF AX 5.6K 1/4W 5% R469
14-56221A RES CF 6.2K 5% 1/4W R415,419,428
14-56801A RES CF AX 68Ω 1/4W 5% R312-323,454,455,
457, 458, 460, 461, 462,
464,465,466
14-57501A RES CF 75Ω 5% 1/4W R407,409,410,420,425
427,432,434,8436,439
14-58211A RES CF 820Ω 5% 1/4W R467,468
CO14179-05 CAP CER 47pF 50V 5% C421
0014179-30 CAP CER 30pF 50V ±5% AX CH C219,220,130
0014180-17 CAP CER .001uF 25V C427,505,506,509,
510, 517, 518, 521
0014180-18 CAP CER V.01uF 25V 20% AX C503,515,101,540,527
533,549,430
0014180-25 CAP CER 8200pF 50V 20% AX C528,531,534,538
0014181-05 CAP CER .22uF 50V -20+80% AX C633-636
0014181-07 CAP CER .47uF 25V +80-20% AX C411
00770149-008 CAP CER 100pF 50V 5% SL AX C222-225
0070290-001 CAP CER 150pF 50V 10% AX C208
0070290-004 CAP CER 270pF 50V 10% AX C218
0070290-005 CAP CER 330pF 50V 10% AX C209
0070480-001 CAP CER .1uF 25V AX -20+80% Z C104-106,108,109.
111-114,200,201,226
C300-307,402-406,409,
412-414, 419, 0500-502,
C523, 524, 632, 206, 203,
559, 562, 565, 0207, 210,
214, 217, 221, 227-230,
422, 0550-557, 428, 429,
900,536
C014384IA IND FERRITE BEAD AD L100,401,402,500-503

C070471-002 IND 220uH 10% AX L208

C101401-221 IND 220uHF AX L203

ASSY NO: SD400329-001

PART NUMBER DESCRIPTION LOCATION/QUANTITY

SA400429-001 ASSY SMD STE W/MOD 1

SB400329-101 ASSY SEQ STE NTSC W/MOD 1

ASSY NO: SA400329-001

PART NUMBER DESCRIPTION LOCATION/QUANTITY

C300779-001 PCB STE BLANK 1

C300589-001 IC STE MCU GLUE 144P U400

410, 508, 510 L208

56

SECTION EIGHT: GLOSSARY

1772 Floppy Disk Controller

6850 Also ACIA (Asynchronous Communication Interface Adapter). Each one

provides an asynchronous communications channel. In the STE, there are two
6850s, one for keyboard communication, and one for MIDI communication.

68901 See MFP.
BUS ERROR GSTMCU has asserted BERR to inform the processor that there is a

problem with the current cycle. This could be due to a device not responding (for
example, CPU tries to read memory but the Memory Controller fails to assert
DTACK), or an illegal access (attempting to write to ROM). A bus error causes
exception processing.

CPU Central Processing Unit, the 68000 microprocessor.

DMA Direct Memory Access. Process in which data is transferred from external

storage device to RAM, or from RAM to external storage. Transfer is very fast, and
takes place independent of the CPU, so that the CPU can be processing while DMA
is taking place. GSTMCU arbitrates the bus between the CPU and DMA.

DMA CONTROLLER Atari proprietary chip which controls the DMA process. All disk
I/O goes through this device.

EXCEPTION A state in which the processor stops the current activity, saves what it
will need to resume the activity later in RAM, fetches a vector (address) from RAM,
and starts executing at the address vector. When the exception processing is done,
the processor will continue what it was doing before the exception occurred.
Exceptions can be caused by interrupts, instructions, or error conditions. See also
System Errors, or a 68000 reference for more detail.

GSTMCU Atari proprietary chip which ties together all system timing and control
signals.

HALT State in which the CPU is idle, all bus lines are in the high-impedence state,
and can only be ended with a RESET input. This is a bidirectional pin on the CPU. It
is driven externally by the RESET circuit on power-up or a reset button closure, and
internally when a double bus fault occurs. A double bus fault is an error during a
sequence which is run to handle a previous error. For example, if a bus error occurs,
and during the exception processing for the bus error, another bus error occurs, then
the CPU will assert HALT.

HSYNC Timing signal for the video display. Determines when horizontal scan is on
the screen, and when it is blank (retracing). The synchronization (approx. every 63
microseconds) It is also encoded onto IPL2..0 to cause a level 2 auto-vectored
interrupt to the CPU.

INTERRUPT A request by a device for the processor to stop what it is doing and
perform processing for the device. It is a type of exception. Interrupts are maskable
in software, meaning they will be ignored if they do not meet the current priority level
of the CPU. There are three priorities:

The highest are MFP interrupts, then VSYNC interrupts, and lowest are HSYNC
inte«upts. Interrupts are signaled to the CPU on the Interrupt Priority Level inputs
(IPL0-2). See Theory of Operation, Main System, MFP, and GSTMCU.

57

MEMORY CONTROLLER Atari proprietary chip which handles all RAM accesses.
See Theory of Operation, Main System and Video Subsystem for details.

MIDI Musical Instrument Digital Interface. An electrical standard by which electronic
instruments communicate. Also, the logical system for such communication. In the
STE. consists of a 6850 communication chip, driver and receiver chips (74LS04,
74LS05, and PC-900 optoisolator), and an MFP interrupt channel.

MFP Multi-Function Peripheral, aka 68901. Interrupt control, timers, and USART for
RS232 communication. See Theory of Operation, Main System.

MODULATOR Device which modulates a composite video signal, combined with
audio. onto an RF carrier for output to a television.

PHASE LOCKED LOOP Circuit which locks the horizontal sync signal onto the color
burst reference frequency for accurate color on the T.V. Without this circuit, colors on
the T. V. become unstable, flickering or shifting about on the screen.

PSG Programmable Sound Generator, also YM2149. Yamaha version of General
Instruments AY-3-8910. Has two 8 bit I/O ports and three sound channels. Used in
parallel port and audio.

RS232C Electrical standard for serial digital communication. Also the physical and
logical device which performs communication using this standard. In the STE
computers, consists of the MFP, PSG, 1488, and 1489 chips.

SUPERVISOR MODE State of the CPU in which it is allowed to access all hardware
and RAM locations, and perform some privileged instructions. Determined by the
state of a bit in the Status Register.

USER MODE State of the CPU in which certain instructions and areas in the
memory map are disallowed (resulting in a privilege violation exception if attempted).
See also SUPERVISOR MODE.

VSYNC Signal used for vertical synchronization of CRT display device. Occurs at 70
Hz (monochrome), or 50 or 60 HZ color.

YM2149 See PSG

58

SECTION NINE: SCHEMATICS AND SILKSCREENS

Schematic Diagrams, Assembly and Drawings

Schematics:

1. CPU, Blitter, ROM, clk

2. RS232, Parallel, MIDI, PSG

3. DMA, FDD, clk

4. MCU, SHIFTER, Video

5. Stereo Sound, Joy, Paddle

6. RAM

7. PSU

8. Test Fixture

Drawings:

1. Assembly Main

2. Assembly PCB

3. Keyboard (front side)

4. Keyboard (back side)

5. Keyboard Schematic

6. Keyboard Assembly

7. PCB Soldering Side

8. PCB Components Side without BLiTTER

9. PCB Components Side with BLiTTER

10. ATARI STE Test Fixture to Computer connection

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

2 and 3

2

2 and 327010/571000/531001

27512 2 and 3

ROM jumper settings

Note: Jumpers are shown set for 1Meg ROMs

3

1N914

1 and 2

N/C

2 and 3

Don't care

1 and 2

32.215905 MHz

1

RESET

Stuffed in non-PAL systems only

2 and 3

3

2 and 3

N/C

27256

W102

NTSC

W104Part type

571001/27C100/531000

3 1

R111 & R112 are installed ONLY when U101 is NOT installed

Peritel

>

2

(See default settings below)

>

W103

32.084988 MHz

1 and 2

12

Stuffed in PAL systems only

!

Drawn by jer 1

ATARI 1040STe CPU, BLITTER, ROM and Cartridge

C

1 8Thursday, June 01, 2017

Title

Size Document Number Rev

Date: Sheet

of

XLDS

A5

D8

XIPL1

A17

A1

A18

RXW

A7

A17

D6

D12

XCPUBG

D8

A7

D14

A7

D1

A7

A22

D10

A3

A23

A4

D13

D10

A8

D11

XBGACK

D2

32MHz

A3

A4

D5

D14

A6

D5

D15

A19

A19

A8

XIPL0

D13

XBGK

D7

D1

A18

A10

A13

A6

XUDS

A1

A14

A16

D0

D12

A19

D13

A21

D3

XVPA

A14

A2

A15

A16

A8

A15

XRESET

XHALT

D7

D9

A9

D9

A5

A1

A15

G12V

D7

A10

D0

D15

A2

32MHz

D8

A12

D4

A20

A6

A21

E

A4

D7

FC0

D10

D10

A4

D14

CCLK

XBR

D11

A3

A4

A13

A22

D2

A15

A8

A9

D9

D3

A11

A2

A5

A12

A18

D13

A12
A11

A23

D2

A9

A3

A11

CLK8

A6

D4

A10

A5

XROM3

A22

A16

A8

D6

D1

A13

D6

A3

A9

A6

D11

DATA [15:0]

HSYNC

D4

D3

XROM4

D12

D11

D5

XUDSA14

XLDS

XVMA

D0

D9

A20

A5

A17

A10

D2

XROM2

ADDRESS [23:1]

A17

FC1

D14

A10

A15

A17

D4

A21

FC2

A13

A12A12

XCPUBG

A20

D0

XIPL2

A23

A1

D1

A11

D12

A7

A2

XBERR

D8

D3

D5

XBLTBG

A15

A13

D15

D6

A11

XBLTINT

XAS A2

D15

A14

A9

XDTACK

A14

A1

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

12V

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

D101

1SV89

R128
2k7

C103

4700uF

P101

4k7X8

12
3
4
5
6
7
8
9

Q100
2N3004

C127

88pF

C124

22nF

R116
18k

U104

NE555

3

4

8

1

5

2

6

7

OUT

RST

VCC

GND

CV

TRG

THR

DIS

R104
10k

C100
10uF

R124
6k8

C111

u1

W102

C120

1nF

C116
u47

U102

27C010

4

16

12
11
10

9
8
7
6

5
27
26
23
25

13

19
20
21

14
15
17
18

28
29

24

3

2

31

22

32
1
30

A12

GND

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

I/O0

I/O5
I/O6
I/O7

I/O1
I/O2
I/O3
I/O4

A13
A14

OE

A15
A16

PGM

CE

VCC

VPP

NC

P100

4k7X8

1

2

3

4

5

6

7

8

9

R127

430

R119

2k2

C125

8.2pF

R107

1k

R121

100k

U100

MC68000

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

53

54

55

14
52

16
17
56 57

15

5

4

3

2

1

68

67

66

65

64

63

62

61

60

59

58

30

29

28

6

7

8

9

11

21

22

24

12

13

1019

20

23

27

26

25

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

VCC
VCC

GND
GND
GND GND

CLK

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

FC0

FC1

FC2

AS

UDS

LDS

RXW

BG

VMA

E

BERR

BGACK

BR

DTACKHALT

RESET

VPA

IPL0

IPL1

IPL2

R120

2k2
R100
10k

S100

D102

1SV89

L101

0.27uH

C119

470pF

L100

FB

P104

10kX8

1

2

3

4

5

6

7

8

9

R117
2k4

D100

C123

1nF

Y101

32.084988 MHz

R125
5k6

R123

4k7

R103
10k

C126

33pF

R114
10k

C101

10nF

C105

u1

C115

4n7

R122

100k

C118

8.2pF

U101

ST BLITTER

46

47

48

49

50

51

52

53

54

56

57

58

59

61

62

63

64

65

66

67

2

3

4

1
33

5

35

34

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

45

44

43

23

24

25

26

28
37

38

29

30

27

39

40

41

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

VCC
VCC

GND
GND

CLK

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

FC0

FC1

FC2

AS

UDS

LDS

RXW

BGI
BGO

BERR

BGACK

BR

DTACK

RESET

BGKI

INT

C104
u1

R118
1k

U210B

7406

3 4

U308B

74LS74

12

11

9

8

10

13

D

CLK

Q

Q

PRE

CLR

U103

27C010

4

16

12
11
10

9
8
7
6

5
27
26
23
25

13

19
20
21

14
15
17
18

28
29

24

3

2

31

22

32
1
30

A12

GND

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

I/O0

I/O5
I/O6
I/O7

I/O1
I/O2
I/O3
I/O4

A13
A14

OE

A15
A16

PGM

CE

VCC

VPP

NC

P105

10kX8

1

2

3

4

5

6

7

8

9

Y100

4.43 MHz

C110
100uF

P103

4k7X8

1

2

3

4

5

6

7

8

9

R101
12k

U210A

7406

1 2

R102
1k

J103

CARTRIDGE

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31
32

33
34

35
36

37
38
39
40

R113
22k

R109
2k2

C106

u1

C102
22uF

C114
u1

Q103
2N3004

C128

1nF

W104

C108
u1

U402

OSC

14

8

7

VCC

OUT

GND

R126
560

C107

1000uF

C117

2.7-10pF

C122

220pF

R130
150

R111

0

R112

0

C409

u1

R115
1k

R105
10k

L102

1.5uH

R110
4k7

C129

27pF

C112

u1

Q104
2N3004

L103
1uH

R129
3k6

W103

R106
4k7

C113
u1

Q102
2N3004

J100

POWER

1
2
3
4
5
6

C109
u1

P102

4k7X8

1

2

3

4

5

6

7

8

9

Q101
2N3004

C121

100pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

T FILTERS

T FILTERS

PIN14

7406

PIN7

PIN14

1489

PIN7

PIN14

74LS86

PIN7

PIN14

74LS04

PIN7

1N914

1N914

1N914

T FILTERS

KEYBOARD

MIDI IN

MIDI OUT

SERIAL
PORT

drawn by jer 1

Atari 1040STe Input/Output

C

2 8Thursday, June 01, 2017

Title

Size Document Number Rev

Date: Sheet

of

TXD
RXD
RTS
CTS

PD1
PD2

STROBE
PD0

PD5
PD6

PD3
PD4

PD7

BUSY

CD

DTR

RI

DE

XDISKINT

DATA [15:0]

D7
D6
D5
D4
D3
D2
D1
D0

D7
D6
D5
D4
D3
D2
D1
D0

D1

D7

D0

D2

D3

D4

D6
D5

D1

D7

D0

D2

D3

D4

D6
D5

D1SEL

D0SEL

S0SEL

AUDIOS

A2
A3
A4
A5

A2

A2

ADDRESS [23:1]

XIACK

XBLTINT

XSINT

CLK4
XMFPCS
XLDS

XDTACK

A1

KHZ500

RXW

A1

XRESET

SNDIR
XRESET

A1

E

CLK2

SNDCS

MONOMON

XMFPINT

BD0SEL

N6850

VCC

VCC

VCC

VCC

VCC VCC VCC VCC

VCC

VCC

VCC

VCC

VCC VCC

VCC

-5V

VCC

VCC

VCC

VCC

VEE

VBB

R220

1k

R205

220

L200

J201

DIN5F

1
2
3
4
5

L211

R211

1

C224

30pF

R216

4k7

U900

74LS164

1
2

8

9

3
4
5
6
10
11
12
13

A
B

CLK

CLR

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

C219

30pF

R207

220

L215

R212

3k3

C230

u1

C204

470uF

C218

270pF

R218

4k7

L220

U210F

7406

13 12

U206C

MC1488

9

10

8

U211D

74LS04

9 8

L201

U205
TL497

13

3

2

1

4

6

5

14

10

8

7

CL

F

I

CM

SS

T

GND

VCC

C

E

A

C203

u1

U207A

1489

13

2

U207B

1489

46

5

R208
3k9

D200

C225

30pF

L212

C209

330pF

U200

MC6850

11

2

24
23

3

4

13

6

12

1

14

22

21

20

19

18

17

16

15

8

10

9

7

5

RS

RXD

CTS
DCD

RXC

TXC

R/W

TXD

VCC

GND

E

D0

D1

D2

D3

D4

D5

D6

D7

CS0
CS1
CS2

IRQ

RTS

C221

u1

L216

R215

4k7

D100

L203

220uH

L225

L219

U209D

74LS86

12

13

11

L221

L218

D202

1N914

C227

u1

J203

DB25F

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

U203

MC68901

9

1136

37

38

39

40

41

42

43

44

22

23

24

25

26

27

28

29

8

13
14
15
16

47

45

17

18

35

10

21

2
3
4
5
6

1

7

48

46

33

32

31

30

34

19
20

SI

VCCGND

D0

D1

D2

D3

D4

D5

D6

D7

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

SO

TAO

TBO
TCO
TDO

DS

IACK

X1

X2

CLK

RC

RESET

RS1
RS2
RS3
RS4
RS5

RXW

TC

CS

DTACK

IEO

IRQ

RR

TR

IEI

TAI
TBI

C202

4.7uF

L227

C206

u1

C208

u1

U211E

74LS04

11 10

U210E

7406

11 10

R210

10k

U206A

MC1488

2 3

L202

R219

4k7

L224

U206D

MC1488

12

13

11

14

7

C207

u1

L210

J204

DB25M

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

R203

5R1

U210C

7406

5 6

R200

220

L205

U207C

1489

108

9

L217

C222

1nF

Y200

2.4576 MHz

U201

MC6850

11

2

24
23

3

4

13

6

12

1

14

22

21

20

19

18

17

16

15

8

10

9

7

5

RS

RXD

CTS
DCD

RXC

TXC

R/W

TXD

VCC

GND

E

D0

D1

D2

D3

D4

D5

D6

D7

CS0
CS1
CS2

IRQ

RTS

L214

L222

C215

4.7uF

U208

PC-900

2

1

4
5

8

CL

ACE

V

R209

1k

C228

u1

C200
u1

J200

DIN5F

1
2
3
4
5

L226

C205

4.7uF

L223

U202

AY-3-8910

40

1

3

22

23

28

29
27

4

37

36

35

34

33

32

31

30

14
15

10

6

7

8

9

16
17
18
19
20
21

11

24

25

13
12

38

VCC

GND

ACB

CLK

RESET

BC2

BC1
BDIR

ACA

DA0

DA1

DA2

DA3

DA4

DA5

DA6

DA7

IOA7
IOA6

IOB3

IOB7

IOB6

IOB5

IOB4

IOA5
IOA4
IOA3
IOA2
IOA1
IOA0

IOB2

A8

A9

IOB0
IOB1

ACC

R217

4k7

R214
3k9

C201
u1

R204

220

L204

L209

L206

U211F

74LS04

13 12

R202

220

R201

4k7

R213
1k2

C223

30pF

C220

30pF

U211A

74LS04

1 2

L208

220uH

L213

J202

1
2
3
4
5
6
7
8

U206B

MC1488

4

5

6

C216

470uF

D201

U210D

7406

9 8

L207

C229

u1

U207D

1489

1311

12

U204
TL497

13

3

2

1

4

6

5

14

10

8

7

CL

F

I

CM

SS

T

GND

VCC

C

E

A

C217

u1

R206
1k2

C210
u1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EXTERNAL FDD

INTERNAL FDD

INTERNAL

FDD

POWER

CONTROL

CONTROL

3

1

2

2

3

1

PIN14

7406

PIN7

PIN14

74LS74

PIN7

PIN20

74LS244

PIN10

PIN20

74LS245

PIN10

68R X 12

8.01063 MHz

drawn by jer 1

ATARI 1040STe 03 DMA FDD CLK

C

3 8Thursday, June 01, 2017

Title

Size Document Number Rev

Date: Sheet

of

HDRW

HDA0

HDACK

HD7
HD6
HD5
HD4
HD3
HD2
HD1
HD0

S0SEL

RDATA

WPRT

TR00

WGATE

WDATA

STEP

DIRC

MON

INDEX

D1SEL

CD [7:0]

CD7
CD6
CD5
CD4
CD3
CD2
CD1

CD0

CD1

CD2

CD3

CD4

CD5

CD6

CD7

CD0

DATA [15:1]

D15
D14
D13
D12
D11
D10

D8

D9

D7
D6

D4

D5

D3
D2

D0

D1

ADDRESS [23:1]

A1

CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0

SCLK

FDINT

D0SEL

XHDINIT

HDCS

BD0SEL

HDRESET

XRESET

D0SEL

HDRQ

SCLK

CLK2

RDY

XFCS

RXW

VCC

+12V

VCC

VCC

VCC

VCC VCC VCC VCC

VCC

VCC

VCC

VCC

VCC VCC

VCC

R305
1k

U301

WD1772

5

6

7

8

9

10

11

12

3

4

2

1

28
13

18

15

14

22

21

25

26

17

16

23

19

20
24

27

DAL0

DAL1

DAL2

DAL3

DAL4

DAL5

DAL6

DAL7

A0

A1

R/W

CS

INTRQ
MR

CLK

VCC

GND

WD

WG

WPRT

DDEN

DIRC

STEP

TR00

RD

MO

IP

DRQ

R321

U304A

74LS74

2

3

5
6

4

1

D

CLK

Q
Q

PRE

CLR

R310

47

L304

R318

U302

74LS245

2
3
4
5
6
7
8
9

191

18
17
16
15
14
13
12
11

A0
A1
A2
A3
A4
A5
A6
A7

G

DIR

B0
B1
B2
B3
B4
B5
B6
B7

R301
1k

R303
1k

L306

U305B

7406

3 4

U307

74LS244

2
4
6
8

1

18
16
14

12
11
13
15
17

9

7

5

3

19

A1
A2
A3
A4

1OE

Y1
Y2
Y3

Y4
A5
A6
A7
A8

Y5

Y6

Y7

Y8

2OE

R314

R306
1k

R322

L305

J303

12
34
56
78
910
1112
1314
1516
17
19
21
23
2526
2728
2930
3132
3334

18
20
22
24

J302

1
2
3
4

L303

U305C

7406

5 6

R317

R308

47

C301
u1

U2A

74LS74

2

3

5

64

1

D

CLK

Q

Q

PRE

CLR

C304

u1

R323

R307
1k

L311

R302

1k

U305E

7406

11 10

U304B

74LS74

12

11

9
8

10

13

D

CLK

Q
Q

PRE

CLR

L308

C305
u1

C302
u1

C306

u1

R312

L302

U300

DMA

24

40

20
28

38

39

1

22

2

21

3

23

36

35

34

33

32

31

30

29

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

25

37

26

27

HDCS

VCC

GND
GND

RDY

CLK

R/W

FDCS

A1

FDRQ

FCS

HDRQ

CD0

CD1

CD2

CD3

CD4

CD5

CD6

CD7

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

CR/W

ACK

CA1

CA2

R311

47

U305F

7406

1312

R304
1k

U305D

7406

9 8

R316

U303

OSC

14

8

7

VCC

OUT

GND

C307

u1

L307

L310

L300

J304

1

2

3

4

5

6

7

8

9

10

11

12

13

14

J301

DMA PORT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

W300

R315

R320

L301

R309

47

U305A

7406

1 2

R319

W301

L309

R300
1k

C303

u1

R313

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

STMOD

Remove for PAL

1N914

1N914

Stuffed in NON-Modulator Versions ONLY

Stuffed in Modulator Versions ONLY

6

4

3 1

drawn by jer 1

Atari STe MCU, SHIFTER and VIDEO

C

4 8Thursday, June 01, 2017

Title

Size Document Number Rev

Date: Sheet

of

MC

XLDS

XAS

XDTACK

XUDS

FC2
FC1
FC0

RXW

ADDRESS [23:1]

DATA[15:0]

A22
A21
A20
A19

A23

A16

A14

A17

A18

A15

A11

A9

A12

A13

A10

A6

A4

A7

A8

A5

D13

D11

D14

D15

D12

D8

D6

D9

D10

D7

D3

D1

D4

D5

D2

D0

A3
A2
A1

XVMA
FDINT

XPAD0X
XPAD0Y
XPAD1X
XPAD1Y
XPEN

XRESET

XBINT
XSINT

XBERR
XMFCPS

XHDINT

SCLK

MAD9
MAD8
MAD7
MAD6
MAD5
MAD4
MAD3
MAD2
MAD1
MAD0

XWE

XPADRST

XBUTTON
XJOYAH
XJOYAL
XJOYWE
XJOYWL

XROM2

XROM3

XROM4

XVSYNC

XHSYNC

XVPA
XDINT
XIPL2
XIPL1
XIPL0
XIACK
N6850
KHZ500

ADDRESS [23:1]

A6
A5
A4
A3
A2
A1

DATA [15:0]

D15
D14
D13
D12

D9

D10

D11

D5

D6

D7

D4

D1

D2

D3

D0

XRDY

XFCS

SNDIR

SNDCS

XBGACK

XBGO

XBGI

XBR

CLK2

CLK4

CLK8

R

G

B

32MHZ

AUDIO

AUDIOI

HSYNC

VSYNC

MADDR [9:0]

XRAS1

XCAS0H

XCAS1H

XCAS0L

XRAS0

XCAS1L

R
G
B

CCLK

SD6
SD5
SD4
SD3
SD2
SD1
SD0

SD [7:0]

SD7

HSYNC

VSYNC

MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0

MDATA [15:0]

XMWE
MWD
MWK

FCLK

D8

XLD
XHD

MC

MONOMON

VCC

VCC

VCC

VCC

12V

VCC

VCC

VCC

12V

VCC

VCC

R427

75

R437 33

R44968

L406

R421
1k

R46468

U401

GST SHIFTER

11
32

4

5

6

8

9

10

12

14
15
16
17

18

20

21

23
24
25
26
27
28

29
30
31

13

3853

66

78

83

1

84

2

44
45
46

48
49

50

51

52

54
55

56

57

58

60

61

62

63

64

65

67

68

69

70

71

73
74
75

76

77

79

80

81

33

3435

36

37

39
40
41

7

19

42

47

59

72

82

3

22

43

VCC
VCC

PD10

PD11

PD12

PD14

PD15

R/W

A6

A4
A3
A2
A1

CS

HD

SD7

SD5
SD4
SD3
SD2
SD1
SD0

MWE

MWD

MWK

A5

R3CLK

MD10

PD0

PD5

PD7
PD6

PD8

G1
G0
B3

B1
B0

MONO

COLOR

MHZ18

DE
BLANK

MD0

MD1

MD2

MD4

MD5

MD6

MD7

MD8

MD9

MD11

MD12

MD13

MD14

MD15

LOWP
GND
GND

LATCH

HDAT

PD1

PD2

PD3

SCLK

FCLKSLOAD

SREQ

LOAD

R2
R1
R0

PD13

LD

G3

B2

MD3

WDAT

PD4

PD9

SD6

G2

R432

75

R473

10k

C428

u1

R408
2k

R433
2k

R45468

R459
0*

R415 6k2

C425
2n2

R440
1l

R410

75

DL1

2 7

10

U400

GSTMCU

3

1
73
37

109
128

67

39

47

54

56
57

62

108

36
72

120
144

2

4
5

6

7
8
9

12
1315

17

19

20

21

22

43
44
45
46

48

49
50
51
52
53

58
59

60

83

68
69

70

71

75

77
78
79
80

63
64
65

66

88

90
91

92

94
95

126

129

130

131

132

134

136

138

10

25

40

55

74

118

103

133

98

76

82

81

137

32

139

141
140

142

24

26

27

28

29

30
31

33

34

35

38

41
42

97

99
100
101
102

105

110

111

112

113

114

115

116

117

119

121

122

123

124

125

127

11

18

89

61

87

86

85

84

23

96

135

146

16

107
106

CLK8

GND
GND
GND
GND
GND

AS

FC1

A17

A11

A9
A8

A4

VCC

VCC
VCC

VCC
VCC

CLK

CLK4
CLK2

KHZ500

ROM6
ROM5
ROM4

ROM1
ROM0HDINT

DINT

SNDCS

ATCCS

ATCHO

ATCWA

A21
A20
A19
A18

N6850

A16
A15
A14
A13
A12

A7
A6

BINT

IACK

LDS
UDS

R/W

DTACK

D15

D13
D12
D11
D10

A3
A2
A1

RESET

D3

D1
D0

MFPCS

PAD0X
PAD0Y

CAS0H

WDAT

HDAT

LATCH

DMA

DEV

FCS

DCYC

ROM3

VPA

FC0

A10

TEST

MAD8

BUTTON

RAM

PADRST

D14

D8

D9

PEN

EINT7

CMPCS

DE

BLANK

VSYNC

VMA

BGACK

BGO

BGI

BR

EINT3
EINT5

IPL0

IPL1

IPL2

FC2

A23
A22

PAD1Y

JOYAH

JOYAL
JOYWE
JOYWL

SINT

MAD0

MAD1

MAD2

MAD3

MAD4

MAD5

MAD6

MAD7

MAD9

WE

CAS1L

CAS1H

RAS1

CAS0L

RAS0

ROM2

SNDIR

D2

A5

D4

D5

D6

D7

BERR

PAD1X

RDY

HSYNC

FDINT

SREQ

SLOAD

R46168

C426
15uF

C420
15uF

R422 12k

L403

D401

C404

u1

U211B

74LS04

34

L409

L401

FB

J400

DIN13F

1

2

3

4

5

6

7

8

9

10

11

12

13

R469
5k6

R475
150

Q406
2N3904

Q401
2N3904

R45568

C429

u1

R45068

L402

FB

R429

1k

R416 12k

C418

2n2

R406

1k

R470
1k

R442
1k

R46268

R44568

R438
27

R425

75

R436

75

R424 1k5

U209A

74LS86

1

2

3

R411 12k

C406

u1

C432

1nF

R409

75

R435 33

R45768

3

2

1

R474

100

R471

47k

R452
1k5

C430

10nF

R417 1k5

R44668

R405
0*

L404

U211C

74LS04

5 6

C414

u1

R431

1k2

R468

1k2

R46568

U403
MC1377

2

4

6

8

11

1

16

121415 20

13179

7

5

3

19

10

CSin

Gin

-Yout

-Yin

B-Ycl

Tr

8V2

R-Ycl

VBB

GND N/P

CRout

CLK

CVout

VC

Bin

Rin

QD

CRin

R44468

C403

u1

C413

u1

C422

C423

R426 3k

R420

75

C427

u1

Q403
2N3904

R423
2k

R412 1k5

C412

u1

Q402
2N3904

C433
1uF

C415
470uF

R439
75

R472

4k7

C416

47uF

C411
u47

R45868

L407

L410

FB

U405

74LS257

15

1

4

7

9

12

2

5

11

14

3

6

10

13

G

A/B

1Y

2Y

3Y

4Y

1A

2A

3A

4A

1B

2B

3B

4B

R418 3k

R456

2k2

C431

10nF

C419

u1

R45368

R434

75

L405

R46668

C402

u1

C405

u1

R407

75

u1

100uF

R428 6k2

R44368

C424

15uF

R467

1k2

R463

1k

R414 3k

C421

120pF

R448
150

R441
100

Q404
2N3904

R413

1k

R46068

R451

0*

Q400
2N3904

C417
100uF

L408

R419 6k2

D402

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LEFT

RIGHT

1%

1%

1%

1%

Ground Plane This Area

e

drawn by jer/eightbitter 1

ATARI 1040ST STEREO SOUND, JOYS and PADS

C

5 7Tuesday, May 30, 2017

Title

Size Document Number Rev

Date: Sheet of

XMWE

MWK

MWD

GIL

GIR

AUDIO

XPAD0Y

XPAD1X

XPAD1Y

XPAD0X

XPADRST

XPEN

XJOYRH

XJOYWE

JOYWL

XJOYRL

DATA [15:0]

D7
D6
D5
D4
D3
D2
D1
D0

XBUTTON

D3

D1

D5
D6

D0

D7

D2

D4

D3

D1

D5
D6

D0

D7

D2

D4

D11

D9

D13
D14

D8

D15

D10

D12

XLD

FCLK

XRD

FCLK

GIR

GIL

AUDIOS

AUDIOI

SO [15:0]

SO7
SO6
SO5
SO4
SO3
SO2
SO1
SO0

SO6
SO5
SO4
SO3

SO1

SO2

SO0

SO7

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

-5V

8.2V

8.2V

+12V

8.2V

L513

R524

3k6

L503

FB

U502

DAC0802

123

4

567891011

12

13

14

15

16

R500
8k2

R503

10k

U509

74LS244

2
4
6
8

1

18
16
14

12
11
13
15
17

9

7

5

3

19

A1
A2
A3
A4

1OE

Y1
Y2
Y3

Y4
A5
A6
A7
A8

Y5

Y6

Y7

Y8

2OE

R515
10k

L528

C544

47uF

C543

47\uF

C519
u1

C511
u1

C558
100uF

U514B

LM556

11

9
138
12

10

CV

OUT

DSCHGT RG

THRES

RST

R502
10k

P500
4k7X8

1

2345678

9

C512
u1

J500

JOY0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

R531
51k

C523

u1

R505
10k

L527

L524

C534

8n2

C505

1nF

C546

47uF

U513B

LM556

11

9
138
12

10

CV

OUT

DSCHGT RG

THRES

RST

C549

10nF

C520

47\uF

C518

1nF

R533

1k

L516

R501
100k

L512

R512

10k

C503

10nF

L501

FB

R535
1M

C521
1nF

R591
270k

C500

u1

R506
10k

R528
1M

C561
100uF

C525

47\uF

C506

1nF

R545
100k

R525
10k

L508

L523

R529

470

C538

8n2

J502
PHONO

R518
1k8

C517

1nF

J501

JOY1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

R542

10

C513
u1

C541

47uF

C539
680pF

-+U507B

LF347

5

6

7

411

L519

C564

100uF

L511

C524

u1

C528
680pF

-+U507C

LF347

10

9

8

411

C515

10nF

-

+

U507A

LF347

3

2

1

411

R508
8k2

C533

10nF

R546
100k

R543

10

L510

L506
FB

R521
1M

L518

P501
4k7X8

1

2
3

4

5

6

7

8

9

U503

DAC0802

123

4

567891011

12

13

14

15

16

C559
u1

L522

L507

L500

FB

C537

47\uF

R530
10k

R536

470

R519

470

R509
8k2

L520

U514A

LM556

3

5
16
2

4

CV

OUT

DSCHGT RG

THRES

RST

C514

u1

C501

u1

P502
4k7X8

1

2
3

4

5

6

7

8

9

R541

3k6

U506
MF4

1

23

456

7

8

C509
1nF

C566

47uF

C540

10nF

C103

4700uF

C526

8n2

C565

u1

C567

47uF

U513A

LM556

3

5
16
2

4

CV

OUT

DSCHGT RG

THRES

RST

R513

10k

R527

10k

R590
270k

L509

L515

R516
1M

U501

74F374

3
4
7

8
13
14
17
18

1 11

2
5
6
9
12
15
16
19

D0
D1
D2
D3
D4
D5
D6
D7

OE

CLK

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

C522
1nF

-

+

U507D

LF347

12

13

14

411

U500

74F374

3

4

7

8
13
14
17
18

1 11

2
5
6
9
12
15
16
19

D0
D1
D2
D3
D4
D5
D6
D7

OE

CLK

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

U505
MF4

1

23

456

7

8

C562
u1

L514

L525

U508

LMC1992

10

9

8

543

25

21

2

26

14

20

22

27 28

1

11

12

15

16

18

19

LTI

LSI

LSO

LI2

LI1

ENABLE

RI2

RSI

CLK

RI1

LFO

RTI

RSO

BPS VCC

DATA

LTO

LAO

GND

RFO

RAO

RTO

L502

FB

R523

470

R520

1k

R504

10k

C510
1nF

L504

C529

47\uF

C504

u1

U511

74LS373

3
4
7
8

13

14

17

18

1

11

2
5
6
9

12

15

16

19

D0
D1
D2
D3

D4

D5

D6

D7

OE

LE

Q0
Q1
Q2
Q3

Q4

Q5

Q6

Q7

C548
680pF

R507
1k8

R510
100k

C516

u1

L505

R539
51k

R517
8k2

-

+

U504C
LF347

10

9

8

J503
PHONO

Q500

LM78L82

123

R540

3k6

-

+

U504B
LF347

5

6

7

R511
10k

U512

74LS244

2
4
6
8

1

18
16
14

12
11
13
15
17

9

7

5

3

19

A1
A2
A3
A4

1OE

Y1
Y2
Y3

Y4
A5
A6
A7
A8

Y5

Y6

Y7

Y8

2OE

L521

C531

8n2

C507
u1

C532
680pF

C508

47\uF

R537

3k6

C547

47uF

R538

1k

-+U504D

LF347

12

13

14

411

R514
10k

L517

-

+

U504A

LF347

3

2

1

411

U510

74LS244

2
4
6
8

1

18
16
14
12

11

13

15

17

9

7

5

3

19

A1
A2
A3
A4

1OE

Y1

Y2

Y3

Y4

A5

A6

A7

A8

Y5

Y6

Y7

Y8

2OE

C527

10nF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

drawn by jer 1

ATARI 1040STe RAM

B

6 8Thursday, June 01, 2017

Title

Size Document Num ber Rev

Date: Sheet of

MDATA [15:0]

MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15

MD13
MD14
MD15

MD10

MD9

MD11
MD12

MD8

MD5
MD6
MD7

MD2

MD1

MD3
MD4

MD0

MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9

MAD7
MAD8

MAD0

MAD9

MAD1
MAD2
MAD3

MAD5

MAD4

MAD6
MAD7
MAD8

MAD0

MAD9

MAD1
MAD2
MAD3

MAD5

MAD4

MAD6

MAD4

MD2

MAD8

MAD3

MD6

MD4

MAD1

MAD6

MD1

MAD0

MAD5

MD7

MD0

MAD7

MAD2

MD5

MD3

MAD9

MADDR [9:0]

XRAS0

XWE

XRAS1

XCAS0H

XCAS0L

XCAS1H

XCAS1L

XBUTTON

D8
D9
D10
D11
D12
D13
D14
D15

DATA [15:0]

VCCVCCVCC VCC

VCC

VCC VCC VCC VCC

C636
u1

E0

E6

E7

C633

u1

E3

U602

SIMM 1MB

2

15

14

12

11

8

7

5

4

3
6

10

9

13
16
20
23
25

27

18

17

21

1

30

22

CAS

A7

A6

A5

A4

A3

A2

A1

A0

DQ0
DQ1
DQ2

GND

DQ3
DQ4
DQ5
DQ6
DQ7

RAS

A9

A8

WE

VCC
VCC

GND

E4

U600

SIMM 1MB

2

15

14

12

11

8

7

5

4

3
6

10

9

13
16
20
23
25

27

18

17

21

1

30

22

CAS

A7

A6

A5

A4

A3

A2

A1

A0

DQ0
DQ1
DQ2

GND

DQ3
DQ4
DQ5
DQ6
DQ7

RAS

A9

A8

WE

VCC
VCC

GND

C634

u1

E2

U601

SIMM 1MB

2

15

14

12

11

8

7

5

4

3
6

10

9

13
16
20
23
25

27

18

17

21

1

30

22

CAS

A7

A6

A5

A4

A3

A2

A1

A0

DQ0
DQ1
DQ2

GND

DQ3
DQ4
DQ5
DQ6
DQ7

RAS

A9

A8

WE

VCC
VCC

GND

P600
10kX8

12

3456789

U603

SIMM 1MB

2

15

14

12

11

8

7

5

4

3
6

10

9

13
16
20
23
25

27

18

17

21

1

30

22

CAS

A7

A6

A5

A4

A3

A2

A1

A0

DQ0
DQ1
DQ2

GND

DQ3
DQ4
DQ5
DQ6
DQ7

RAS

A9

A8

WE

VCC
VCC

GND

C635

u1

U604

74LS244

2

4

6

8

1

18

16

14

12

11

13

15

17

9

7

5

3

19

1A1

1A3

2A1

2A3

1OE

1Y1

1Y3

2Y1

2Y3

2A4

2A2

1A4

1A2

2Y4

2Y2

1Y4

1Y2

2OE

E1

E5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AC 230V white

black

green

ZLK01

250V~

400V~

400V~

400V

2W 2W

2W

2W630V

1W

HIGH VOLTAGE AREA

10V 1W 10V 10V

16V16V 3W 1 8V

blue
black
black
black
red
red

50V

HRW84

drawn by jer/eightbitter 1

Atari STe Power Supply Mitsumi SR98 CA070086-002

B

7 8Thursday, June 01, 2017

Title

Size Document Num ber Rev

Date: Sheet

of

J101

INLET

1
2
3

- +

D101

RB155

C205
1000uF

R201
2k7

PC101

16

25

Q101
2SC2979

R103
100k

D202

C110

22nF

R109

75

R113

10

R101

10

D103

R106
3R3

C204
1000uF

L202

IC201
HA17431P

R107

2k

C102

2200pF

C103

2200pF

R112

10

J201

POWER

1

2

3

4

5

6

C109

68nF

R105
1k

R205
100

R203
24

L201

D201

30DF2

C101
u47

D102

SW101

R111

470

D203
DIODE

C104
47uF

VR201

10k

C108

u1

R104
1k

C201

1000uF

C206

1uF

Q102

2SC2060

C111

1000pF

T101

TDK 68-0508A

6

4

9

8

1

2

3

5

7

L101

F1

1A/250V

R110

47

R108

470

R204
100

C203
1000uF

C105
10nF

R114

22

R202

24k

C202
2200uF

D105

R102
390k

D104

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PARALLEL
CABLE

TEST CABLES WIRING

JOY0/MOUSE

JOY1

2 Drawn by jer A

ST DMA Test Fixture C103589

C

8 8Friday, June 02, 2017

Title

Size Document Number Rev

Date: Sheet

of

STROBE

DATA2

DATA4

DATA6
DATA7

DATA5

HD0
HD1
HD2
HD3

HD5

HD4

HD7

HD6

HDINT

HDCS

HDREQ

A0

DATA1

DATA3

DATA0

BUSY

4MHz

RW

HDACK

RESET

VCC

VCC

VCC

VCC

VCC

VCC

VCC

U9E

74LS04

11 10

U6A

74LS74

2

3

5
6

4

1

D

CLK

Q
Q

PRE

CLR

JOY CABLE 2

DB9F

1
2
3
4
5
6
7
8
9

J2

DB19F

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

DIN5M

1
2
3
4
5

U9B

74LS04

34

U10B

74LS74

12

11

9
8

10

13

D

CLK

Q
Q

PRE

CLR

U21E

7407

11 10

R4

3k3

U7A

74LS132

1

2

3

U3D

74LS132

12

13

11

U2D

74LS08

12

13

11

U2B
74LS08

4

5

6

DB19M

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

Q2

2N3904

R3

3k3

R16

J5

DB25F

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

U21B

7407

34

U4B 74LS74

12

11

9
8

10

13

D

CLK

Q
Q

PRE

CLR

U3A

74LS132

1

2

3

U7C

74LS132

9

10

8

JOY CABLE 1

DB9F

1
2
3
4
5
6
7
8
9

U1 74LS240

2
4
6
8

1

18
16
14

12
11
13
15
17

9

7

5

3

19

A1
A2
A3
A4

1OE

Y1
Y2
Y3

Y4
A5
A6
A7
A8

Y5

Y6

Y7

Y8

2OE

R1

3k3

U9D

74LS04

98

U5B

74LS02

5

6

4

R7
1M

U21F

7407

13 12

Q1
2N3904

J11

DB9M

1
2
3
4
5
6
7
8
9

C1

10pF

SHIELD

DB25M

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

U2A

74LS08

1

2

3

SHIELD

DB25M

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

R15

U9C

74LS04

5 6

U11

74LS191

3
2
6
7

13

12

15
1
10
9

14

11
5

4

Q0
Q1
Q2
Q3

RCLKO

TC

P0
P1
P2
P3

CLKIN

PL

U/D

CE

Y1
4MHz

U16

74LS257

15

1

4
7
9

12

2
5
11
14

3
6
10
13

G

A/B

1Y
2Y
3Y
4Y

1A
2A
3A
4A

1B
2B
3B
4B

U6B

74LS74

12

11

9
8

10

13

D

CLK

Q
Q

PRE

CLR

U21C

7407

5 6

R11

U7B

74LS132

4

5

6

R10
68

U3C

74LS132

9

10

8

U5A

74LS02

2

3

1

U10A

74LS74

2

3

5
6

4

1

D

CLK

Q
Q

PRE

CLR

R18

R8
2k2

U2C
74LS08

9

10

8

C2

18pF

U9A

74LS04

12

U4A 74LS74

2

3

5
6

4

1

D

CLK

Q
Q

PRE

CLR

DB9F

1
2
3
4
5
6
7
8
9

R6
220

U12

74LS191

3
2
6
7

13

12

15

1

10

9

14

11

5

4

Q0
Q1
Q2
Q3

RCLKO

TC

P0
P1
P2
P3

CLKIN

PL
U/D

CE

U17

74LS257

15

1

4
7
9

12

2
5
11
14

3
6
10
13

G

A/B

1Y
2Y
3Y
4Y

1A
2A
3A
4A

1B
2B
3B
4B

R14

U9F

74LS04

13 12

R12

8 X 68

U21D

7407

9 8

U1 74LS374

3
4
7
8
13
14
17
18

1 11
2
5
6

9
12
15
16
19

D0
D1
D2
D3
D4
D5
D6
D7

OE

CLK
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

R5

R_0

U15
6116

8
7
6
5
4
3
2
1
23
22
19

18
20
21

9
10
11
13
14
15
16
17

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10

CE
OE

WE

D0
D1
D2
D3
D4
D5
D6
D7

R13

U5C

74LS02

8

9

10

U7D

74LS132

12

13

11

R9
910k

U8A

74LS02

2

3

1

ACSI CABLE

DB19M

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

R2

3k3

DB9F

1
2
3
4
5
6
7
8
9

U5D

74LS02

11

12

13

U13

74LS191

3
2
6
7

13

12

15
1
10
9

14

11
5

4

Q0
Q1
Q2
Q3

RCLKO

TC

P0
P1
P2
P3

CLKIN

PL

U/D

CE

J10

DB9M

1
2
3
4
5
6
7
8
9

U3B

74LS132

4

5

6

R17

U8 74LS138

1
2
3

15
14
13
12
11
10
9
7

6
4
5

A
B
C

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

G1
G2A
G2B

MIDI CABLE

DIN5M

1
2
3
4
5

ATARI STE TEST FIXTURE TO COMPUTER CONNECTION