Atari 400 Personal Computer, 800 Personal Computer System System Hardware Manual

ATARI%oo/8oo-

ATARI'

HARDWARE

HOME

COMPUTER

MANUAL

SYSTEM

/t\

ATAR

l' ^,."",

-.mm 6rcre c.mpa^y

o

COPYRIGHT 19 82T ATARI

ALL RIGHTS

TO

ALL PERSONS RTCEIVINC IHIS DOCUMENT

Reproduction is forbidden

without the specilic written ATARI, lNC. Sunnyvale, CA 94086. nor lhe subiect matterlhereof, is or written

oermission

from the Corporal;on.

RESERVED

ri8hl

No

granted

unless by wrilten agreement with,

INC'

'

permission

of

to reproduce this document,

Every documents However,

software

of

I i r|\i I i +rr T^r ^h.n^6c arr.

effort has been made to ensure

this

product due to the ongoing irnprovement and and haralware, ATARI, INC.

printed

naterial alter the date of

of Lhe ATAR] Home

cannot

-- -Jrs,

,

or onlsslons.

that this

Computer

update of the

guarantee

publication

manual

accurately

Division.

the

and disclairns

computer

accuracy

TABLE

OF CONTENTS

II.

III.

I.

INTRODUCTIoN.

DESCRTPTTON

B. c. SERIAL D. E,

HARDWARE

A. PAL.....

B. c. D. E. F. G.

11. I. CONTROLLER

POKEY......,.

INTERRUPT CONTRoLLERS,,

INTERRUPT Tv L1NE GMPIIICS PLAYERS AlIDfO. KEYBOARD SERIAL

, . .

. .

0F HARDWARE. ...

PORT........,.............,..,...II.25

SYSTEM.....,,..............,,.1r.28

RECTSTERS.

....

CONTRO1,..

CONTRoL.....

CoNTROL. . . . .

AND MISSILES,

....

.. .

and

SPEAKXR. .......

PORT. ..

PORTS,......................III.

......

.. ...,...

.. ..

.. ,..

,. .. ...

.....,.,.

...........

. ,. .. ...

... ...

..... .....,.,.

.. .. ..

. . . . . . .

... ,.

.. .. .

. , . . . . . .

.. . ,...

.. ..

.. ,. .. ...

. ....

.

.. .I.

..r1.I

',...rr.

.........rr.23

. .......

.. .....rr1.1

,.... .. ,11I.3

......II1.9

... ....I1I.15

.rr.30

.. ,IIt.l

.III.1

. . .III.

,.. .IIL

,.Irr.17

4 12

t9

I

t

rv,

vr,

sAltpLE

HAIDIIARE A. A'DRESS

B. AI,PHABETICAL

DISPLAY

RECISTER

FlcuRES...,. A.

MEMoRY

B.

NTSC

c.

APPENDIX

APPENDIX B:

APPENDIX

and PAL

SCIIEMATICS.,.

pRoeRAM...,...................IV.

ORDER.

..

,...

MAp........,.....................vr.

A: USE

WITH

MlXlNG

C: PINOUTS

LISTS.

........,.....v.1

ORDER.

DISPLAY..

OF PLAYER/MISSII,E

BASIC

GRAPIIICS MODES

;.........,...,v,5

....,

,. ... ....

... ,. .,.

. .. ...

...v.

,..vr.

... .VI.2

,........vI.3

GRAPHICS

I

t

t 1

1t

I. INTRODUCTION

\:,-

The ATARI

colrtaln a

6502 nlcroprocessor' 4 R-Alt, and several Thls nernral ls

(R)

800rM and

MsI chlps

prloarlly

detall to a11ow experlenced

such as

vldeo

ganes.

A11

rnlcroprocessor by nrltlng

to exlst

ln Elcroprocessol

can also be interrogated

reglsters are

!,lany

wrltten. In aone

contalned gtrobes.

address

.

conventlon

ln 4 separate No data

on the bus

1s to reglsters. For STX could

(Store

be used

x) or STY

115hed by using

PEEK would be used.

a equate llst'

uslflg the

addresses

It ls rea1ly

functlons are

I/O does

help ln learnlng

ceses, blts are deeded

ls \rhat trtggers

use the STA

exanple, STA

(store

(the

data could

eny of the

When lhe

proglaxmer can refer

the

dtreclly.

not rreceasary

perfolrned by lthtch of

these

ATARI 400rM Personal

I/O chtps, operating

for sddress decodlng

lntended to

descrlbe the 4llo

plograd&exs to create four Inpul/Ortp\rt dlrectly lnto

nenory space

by the

wllte only and

nlcroprocessor

cannot be

reading fron the

read only reglster.

ln thls case

the requested

(Store

WSYNC

Y) vould

Accufillator)

perforrns the ltait

ltork

be anythlng).

load instrrcllons

hardltare

to the registers

fot the

functlofls.

chips are

thell reglsters Just

same addless

lust

register

plograffner to kno{

lhe 4 chlps'

conputer systems

systen ROI'I' expandable

and data bu8 bufferlrg.

chtps tn sufficent

assembly tanguage

controlled by the

$hlch are decoded

as RAM

by leadlng

does. These l/o chtps

slrdlar reglsters'

read after they

glves

wrlte

Sone

slnce lhe

actlon.

only reglsters are

presence of

The usual

hstructlon

for Sync

as weL1.

Readlng

(LDA'

LDX etc').

naEes are

In BASIC'

a reglster

deflned 1n

name ralher

by

$hlch

however

are value

the

for such

functlon'

a P0KE

ls accoDp-

Ifl BASIC

lt

Prograrns'

the

an

than

nanual should

Thls

(oS)

Systen Baslc Ref erellce

CHIP T{AME

-

ANTIC

Manual,

I'I4tuaI. fUNCTION DMA(Dlrect

NUl

(Non-Maskab

Vertical I-lght

Vertlcal

WSYNC

CTIA

Prlorlty

be used

a 6502

prograoning narNal,

llenory Access)

and Horlzontal

Posltlon

Pen

l1ne counter

(ltatl

for

control

Color-Lumlnance

all oblects

to

?LAYER-MISSIIE

cre^h{ r a raoi.rarc

Slze

control

l{orlzontal

Col11slon

S{ltches

detectlon

and lriggers

ln conluncllon

lnterlupt)

1e

flne

reglsters

hortzonlal

(display

control

lttcludlng

obJects

(colors

DMA

(4

posltlon control

beBteen

(rnlscellaneous 1/0 functions)

control

sync)

of overlapplag

players and 4

rlth and the

control

scrolllng

objects

all

the Operatlng

brlghtness

alrd

fron ANTIC)

objects

4343!]!qgl.g9g

oblects)

asslgned

ldsstles)

CII1P

NAI,IE

FI]NCTION

POKEY

PIA

Sectlon varlous graphics tlne, groups

display plogtafi. the order addresses,

nation

describing

(lnterruprs,

system.

and

can be

II descrtbes

Sectlons

alphabetical

the OS shadon

found.

Keyboard Ser1a1 Pot

scan Audlo generatlon Tlners

IRQ

Randon

Controller Peripheral

(naskable)

IRQ

nodes. whar

Section

scan and

com.lnicatlons

(digitlzes

(na6kable

{runber

(Joysllck)

control

rhe

Sectlon

each bit

graphlcs,

V conlalns

VI

and VII 11s!

order,

registers

inlerrupt)

generator

conlrol

port

posltion

(4

chanllels)

lacks

and

lnterrupt

hardware

III

lists

ts used

audio,

Sectlon VII

etc.).

various

the hard\rare

and

(bidtrectlonal)

of 8 tndependelt

control

read ot write

control from

in sone

the hardrrare

for.

includes hex page

the

fron

lines

deratl,

It 1s organtzea Section flgures

ftrnbers

pertpherals

perirherats

lncludlng

resisters

IV contatns and block

regtsters

and decfidal

i,,here nore

pots)

the

orle a!

by

functional

a sanple

dtagrans

ln adilress

infor_

a

of

r,2

II. DESCRI?TION

I{ARDWARE

OF

ANTIC

TV Dlsplay: dtsplay at The PAL on

NTSC vs PAL. Each frame conslsts of 262 horizor.tal TV lines and each 11ne ls nade Dlcroprocessor nachine

AND CTIA

generate

the lelevlsi.on

(US)

systein.

rt-3, The 5502

the rate

(European)

of 228

up

The ANTIC and CTIA chips

of 50

frardes

per

second on the NTSC

systen ls dlfferent and ts descrtbed in the sectlon

color clocks, as sho\rn 1n figure

runs at 1.79 MHz. Thle rate was chosen so that one

cycle ls equlvalenr ln length to tno color clocks. One clock

ls approxlnately eqral ln width to two TV 1lnes,

In any or rectangles graphlcs

Bample dlsplay llst

The

(VCoIJNT).

l1nes

The 0

pe!

potnt Verttcal blank back to the top Atarl 800 does not do lnterlaclng, so each frar@

plogran

the

(vSYNc) (VCoUNT

stAits. AJter vsYNc, there are 16 oore

ttnes of \'BLANK. The dleplay 1lst

descrlbed later) causes the

graphtcs

called

Eode has a

current TV

Ttls reglster

frarne so VCOUNT rufls fron 0 to

occurs near the

(TELANK)

node, the dlsplay is dtvided up lnto soafl sqrares

ptxel8

plxel

glven

la

(plcture

elenenle). The highest resolutlon

slze of I/2 color clock by I Tv llne.

1rl sectlon

IV.

ltne nay be deternined by readlng the vertlcal

of

the screen

glves

the llfle count

end of vertical blank

1s the tlne durlng

1n prepaxatlon for lhe flext frane.

dlvided by 2.

(0

130

to

(see

uhlch the electron beaE returns

ls ldentical unless

which ls belng executed

changes the dlsplay.

occurs durlng the fourth rhrough slxth lines =

hex 7D through 7I).

thls tel1s lhe TV set

11nes of VBLANK fot a Lotal

walt lnstructlofl

Juop

dlsplay llst

and

graphlcs

to start

'I}:'ete

155 on the PAL syste.0).

flgure VI.5),

verllca1 sync of vertlcdl blank where each frane

(to

at lhe end

VBLANK.

A

counter

are 262

The

of 22

be

of

Operatlnq Svsten Systen it

(OS)

ln ROM. The 0S affects

!d11 be Eentloned fron tltae to tlltre

(0S):

The ATARI 400/800 cones

sone of the

in lhis nanual. Refer nanual for nore deta11s. The 0S descrlpttons verslon

The Os supports

was belng dlslrlbuted when

lhat

nost of the hardnare

PLoT, and DRAWTO coEnands). Tte OS always

the erd of vertlcal blank. for

televlslon

edges of the

ulth

but

a conpuler

sets \lhlch overacant

plcture

are cut off,

1t ls essential dlsplayed on the screen. It ctocks at that

has excesslve overscan

rtght or left

lhe

This conventlon

is fairly cor0mon edge of the rnay

have

thls nanual I'as

graphlcs

dtsplays

Most TV's are

Thls ts flne for

for all lnpotlan!

plcture

!o readjusted

dlaDlav.

II.1

wtth a loK Operatlng

hardware registers, so

in thls

na[ua1 apply to the

written.

loodes

(BASICS,

24 background l1nes

1s used at Atarl to

deslgned so lhat

ordlnary broadcasts'

infornatlon to

for four to elght

overscan.

to

to oblaln a

lo the OS

GRAPHICS'

after

compensate

lhe

be

colot

A TV set

satisfactory

The

0S uses 192 TV llnes 24 ltnes to overscanr clocks, nended or other

The hard\rare

lhat the standards

lnfornatlon

of the prograno.

for its display

It uses

will allo\r

the standard dlsplay irldth

displays of any length,

be followed. The

and devotes the remalnlng

exception night be a border

whlch is nerely decota!1ve

of 160 color

but it ts recon-

and not esse[tla1

to use

.q,q_lleggjglqE:

and cannot Every

TV frarne durlng

be read the 0S has

its shadow registers, register. ii

ATRACT

TV

screen and the reads lhe resulls code

to unpack the data.

The 0S does

(on

0S reglsrer) is negatlve.

phosphors

sante hlgh-luninance

lhe

Joysticks

1n shadow reglsrers,

lhe 0S changes or the OS

shadow registers instead the OS shadoirlng veclors

I'Ilctoprocessor

provides

lolcroprocessor

(see

l{!:Ig:

OS marlual).

In addirion to a Vertical Blank

to s)'nchronlze to the vertical TV display, this

a Walt

to synchronlze

sync takes effect \rhen

WSYNC, \rhenever

address

sets a larch which

Since nany of

vertical blank and wriles

attracr color shlfting

h'trlch can occur

and other

reads during inlerrupt

can be disabled by

for Horizontal

the

it deslres horizontal synchronizat

called REAIY. Idhen READY The lalch is of the next resunoe

progran

autonatlcally reset

horizontal blank interval, releasing

execution.

hard\,rare

the

a mnber of

"shadow

the OS takes

thero ou! to the correspondlng

reglsters are

write-only registers'i in RAM. lhe values ln sone of

hardware

on all of rhe color registers

This is to

1f the brlghtness 1s

dlsplay is lef! on

for a long tlne. The OS also

conrrollets during vertlcal

so rhat user plograns

Ttere are a few interrupt-related

processing.

of accessing

the

changtng the vertical blank

Interrupt,

prevent

do not have to tnclude

Prograr0s

hard\tare

which

da&age Eo rhe

turned up too hlgh

blank and stores

reglsrers $hlch

usually access

directly. Ho\rever,

and lnterrup!

allons rhe

systed also

Sync

(WSYNC)

cornnand rhat al1ows Ehe

ilself to lhe TV horlzontal line rate. Thts

processor pul1s

goes

to zeto the Elcroprocessor stops and \raits.

r.rrites to an I/O location ca11ed

Wriling

at the beglnnlng

nicroprocessor

to zero a

(returning

lon.

pln

on the lllctoprocessor

REAIY

true)

the

to thls

to

Obiect DMA

(Direct

chip ls to fetch data fron roenoty

display on the TV screen. Meoory Access" or Dl4A. It bus

by sending a stgnal called HALT to lhe microprocessor, causlng the

processor

cycle. The

it r,rishes

to becoEe

ANTIC chlp lhen takes over rhe address blrs and reads any data

fron nenory. Another nan€ fo! Lhis rype of

Once lnitlated,

"TRI-STATE"

this DMA is conpletely and autonatically conlrolled

Antlc chip Fithout need for futher microprocessor lnlervention.

There are l\ro types of Dl4A: Playfleld and Player-Missile

1I.2).

The

playfield

Dl4A control clrcult snall durnb drlcroprocessor. fetch its ol'n instructions fron uernory

program

(alpha

screen), and the Iolation of the data

counter(d1splay llst poln!e.). Each instructlon defines the

character or nemory nap), and the resolurlon

group

or rlnes.

Menorv Access): The

(independent

It does thls reqrests

(open

lrlth

lhe use of

circuit) all durlng the next cornputer

on

halting the main nicroprocessor 1t can

By

(lhe

ln menory L'hich is to be dtsplayed

II.2

primary

of the

functlon of the Antlc

nlcroprocessor)

a lechnlqle called

inenory address

the

DMA

1s

the Antlc

dtsplay

chip resernbles a

list) addressed by 1ts

(slze

of bits

"Dlrect

and

"cyc1e

(see

on the

for dala

stealing". by

lhe

Figure

type

Ir ordel to begln

dlsplay

l1st of lnstructloos tdenory, tell 1lst

potnter)

register).

thls DI,IA the natn

ln nenory,

the ANTIC where the dlspfay

and enable the DMA

control

nlcroprocessor lnrsE

store

data to

ltst ls

be dlsplayed ln

(hltlallze

flags on the ANTIC

sEore a

display

the

(D}.IACTL

In addttlon chlp addressea graphlc8

descrlbed

slDrltaneously

PLAYER-MISSILE

dala on to the

(1f

enabled) occurs

prevlously.

idstructions, and

III addltlon generates

1n

thls systen.

ed by

where

DMA

programer

the an exact

addresses for the refresh

Thla ia also coDpletely

count of the conputer

Color-lunlnance

for each loaded end lunlnance the serlal

Player-Mlssile

by the nlcroprocessor

of lts

pss8es

data color and hrninance to

the TV dlsplay.

background

detectlon

color

(to

be

to the

playfteld

DlttA descrlbed

colttrols another DMA

gr:aphics

CTIA chip

antoDatlcally,

data stored ln neoory and passes graphlcs

lnterspersed nith the

This ?LAYER-MISSILE

Is therefore rmlch

to the two rypes

slEpler than the PLAYFIELD Dl,lA.

of dlsplay DMA, the ANTIC

of rhe dynanlc nenory

only

lf he ls concerned with

cycles 1s lrnportant.

I A colot-lumlnance register

and Playfleld

correspondlng

lhrough the

values

In areas of

(CoLBK)

1s displayed.

\'lth

contalned ilr lhese registers,

the screen where there

type. Each color-lun reglster

a code representlng

Player-Misslle or Playfleld CTIA chlp 11 1s

descrtbed later;.

above, the ANTIC

channel. Thls type of DMA

the

reglsters. Thls

DMA has no dtsplay

type of DMA

playfleld

1lst or

DMA

chlp also

RrlM used

autollattc and need be constder-

real-tlue

ls used on the

progrardolng

CTIA chlp

the deslred color

'rtmpressed"

type. As

\rlrh

before being

are no objects

The CTIA also does

collisron

is

the

seflt lhe

?rlorltv:

overlap ttlst \rhlch

them. serlal to the TV

on the TV screen

be made

appear to

Prlorlty ls data fron

screen.

prlority

The

I'rltlng lnto

thls reglster sectlon III.

Plavers

whlch

poeltlotl

car be moved qutckly

reglsters.

$ere orlglnally

and bullets.

then. The

four

four playfield

It posslble

!o dlsplay

ltren novlng

as to whlch

pa8s

1n

flont of

asslgned

each object

of objecls

the control

glven

are

1n rhe

and }llsslles:

They are

deslgned

Itowever,

there are

player-rulsslle

color reglsters

9 different

oblects, such

(with

oblect shons

each

other or wlth

1n fronr of the othex.

others are satd

aLl

ro

objecrs by

1s conbtned

can be conlrolLed

reglster PRIOR.

table 1n the ?RIoR

players

The

in the hortzontal

called

to be used

players

games

ln

nany other posstble color and

registers, ln the background colors ar the

playets

as

and Btsslles,

playfleld)

have

to

rhe CTIA chlp befoie

rrtth

the other oblects

by the mtcroprocessor

The functtons

regtsrer descrlption

and nlssiles are

dlrecrlon by and Eissiles

for objects

appllcations

conjunclton l'lth

color teglster, raake

sane ttr0e,

a dectslon

Objects

prloriry

ower

and sent

of the bits

snall objecLs

changing

because they

such

as ahplanes

for

the

by

in

thelr

the

II.3

obj ec!s

MEMORY },IA?

=

background)

MICRO

PROCESSOR

I'IEMORY

con!!o11ed

Displai

ltst

lnstructlons

(DI,IACTL

Playfleld Dl,lA Erable

by

)

Ftgure 1I.2

OBJECT

DISPI,AY

SOURC'S

There are a nisstles n0ay objects

posltloned

are

([PoS (X)).

sor,

allowlng an TV 1ine.

The

shape of a player-nlsslle

graphics reglsters. address).

processor, tlme.

rhenever

posltion

ta1

graphlc

the

processor

access graphics

enable

graphlcs

reglster

The These although

The data ln

the horizontal

reglsters

player-ntssile

The

(CRAF

(Dl4A)

ln Demory, I1'rlte

player-Eissile

from rneuory

lotal of four

grouped

be

together and used

horlzontally by

These

reglsrers nay

object to be repllcated

(GMF (X)).

lllsslles

four

have 2

reglsters oay also

they ale usually

each

tegister.

giaphics sync

couflter equaLs

The same data

are reloaded

graphlc

(X)),

(see

or

figure

arlonattcally II.3). The

the player-miss1le (DMACTL,

DI'A

to dlsplay

players

and four nlsslles.

as a 5rh

8 horizonral

be reloaded

nany

is deterElned

Players

have independent

blt regtsters

be reloaded

changed during horlzontal

reglster is

\1111 be displayed

vrith Ire

registers rnay

fron nenory with

prograr0ner

GRACTL).

ls then fully

The

fout

player,

posltlon

at any rlne by

These

regtslers

proces-

rhe

tiioes across a horizontal

by

at afly ttne by

data

lhe

8 blt

(located

tn lts

graphtcs

wlthln

the

bLank

placed

the corresponding

on the display

horlzon-

every line

data.

be reloaded

by the mlclo-

dlrect meDory

lrusr place base address The transfer

rhe objecr

(PMBASE),

of object

autornaric.

olre

unless

and

PMBASE

player-nissile

the oblect is bytes Antic,

betrseen

so they

Only

strgle-line wlth

two-line 1n nenory tion

neans

DI.{ACTL,

blt

resolutlon

Each byte

are

to be displayed

I indlcates

graphics

The

II.3. they may al1 trro and

The

be only

0's.

pixels

is deternined

speciftes

graphics.

deternined

by addtng

the base

are available

the five nost

resolutlon

resolutior.

1s restllcted

that each

4). 540

and

l28O byres

byte of data

(decinal)

tn rhe player graphics

on

that

the

player's

nay be anyrhtng,

player

graphlcs

a couple

Each byte

for

1n rhe rolssile

each missile.

by the

the nost

slgnificanr

The locatlon

an offset

address

aod the ntsslle

to rhe progranner.

stgnificant

and the

bits oI

slx nost stgnlftcant

This !0eans

!o

certaln

page

ls repealed

bytes

(5x256)

tor

the correspondtng

color-lun not

may f111

of lines

Just

the high if dlsplay

Each ptxel

SIZE registers.

byte of rhe graphics

to PMBASE

PMBASE are

thar the

boundartes.

for

(5X128)

are requlred

one-tine area

represenls

llne(s)

ts

to be dtsplayed

rectangles

enttre hetght

the rest of

also represenrs

nay be 1, 2,

(MSB)

dara are

of the address

*256

(decimal).

not used by

used lrirh

blts are useil

location of

Two-llne reso-Lu-

lqlo Ilnes.

resoiur'ion,

elght

of rhe

TV screen.

like the ones

of rhe

the

or 4

of

for

each

The

graphlcs

the

(see

for rwo-ltne

ptxels

whtch

A

in

that

ptxel.

in ftgure

screen or dlsplay dara ts etgi.rt plxels, color clocks,

Plavfleld:

piayfields,

detection. neloory menory,

Playfleld

nap

and character.

independent

each

Playfle1d

ldenrtfled

of

ts

generated

ls

Both methods provtde player-r0issile

the

always

by

its own

generaled

by DMA.

color-1um reglster

by

lwo dlfferen!

generatlon.

llsts

There axe

and colllstott

DMA

technioues:

of insE;ctlons

four

1n

player-Mlsslle Resolutlon ls

Sase Address

controlled by bit 4 of DI4ACTL,

(PMBASE)

=

),ISB of address.

A.DDRESS Tvo-l1ne resolutlon resolutlon

(hex)

+180

+200

+280

f300

+380

+400

OFFSET

One-line

(hex)

+300

+400

+600

+700

+800

PMBASE*100

2I

M

PO

PI

P2

P3

I

(hex)

Mlss lle Nunber

.21

rP3t

i-T--

rl

tl

| |

lt

tl

ll

TV SCREEN

I

P0l

ii

r42

;i

tl I

lt

MO

i

P2

I'

M3 I

Horlzonral

ior each objec! lndependently

horlzontal positlon

regasrers.

rl

Pl

I

|.'i

MI

Dosirlon

by 8

1s

set

Player-Mtssile Ver!1ca1

Figure

II.2

Each sectlon onlo

screen

PLAYER-MISSILE

II.6

Object only by of

total height of

vertical posltion

lts Iocatlon

deDory.

I or 2

television lines

of memory

one byre of

DMA

naps dlrectly

TV screen.

is

deternined

In lts

section oenory vertlcally,

equals

Unl1ke

playfleld.

for Playfteld, 1t can fll1

players

on

lhe othet hand, nay requlre

the entire wldth of the screen.

and Elssiles,

Each player

there are oo horlzontal posltlon

can only have one byte of

display

up to 48 bytes

per

line

regtsrers

llne.

because

T'here are clocks), standard The ddth 1s nldlh

DMA. The

stored bytes 1ong. The dlsplay

Dlsplav Llst

a dlsplay progran

DIISTL.

thls counler value ls

!ton, lncrenent and so DIISTII). DLISTI or when DMA 1s disabled

the resolutlon to be dlsplayed for a ca11ed a dlsplay b1ock.

A JUMP INSTRUCTION IS USED.

ls that less R.A.lil ls reql.rlred

0S

g!9If3I-!19!:

rnemory.

fir

The dlsplay 1lst

(or

dlsplay

the

on

&.ltonatlcally irlthout Elcroprocessor control

Each lnstructlon deftnes the

TITE DISPI-AY I-IST CANNOT CROSS A lK BYTE MEMORY BOIINDARY UNLESS

three dlfferent

(160

color clocks), and wide

selected by stortng graphlcs

Counter that fetches

OS shadow registers

one

Dlsplay l,1st

(s1ze

modes

The dlsplay list is a

These lnstructlons

llst can be considered a dlsplay

counler.

counter can be inirlalized by wrirtng ro

used to address the dlsplay llst, fetch the lnstruc-

(l)

to slxteen

DLISTH should

and

(see

of blts on screen) and the

group

playfield

lnto DMACTL. The advantage of

and fener nachine cycles are

use the standald screen wldth.

lhese lnstluctlors can

(10

bit counter

SDLSTE ard SDLSTL). once

(16)

CounLei, fetch the next dlsplay lnstruction,

be aLtered

DI,IACTL).

type

(I

to 16) of l1nes. Each

lrldths:

sequence

are eithe! one

lines of data on lhe TV

(alpha

narrow

(192

of display

plus

6 bit base reglster.)

only during vertlcal

character or nemory map) and

locatlon of data

(128

color

coLor clocks),

a rarrolrer stolen for

instructlons

(1)

byte or

progran,

be

thought of as

DLISTIT and

tnltlaltzed

screen,

(see

DLISTI and

group

of lines ts

rhree

and the

blank

ln nerory

(3)

Flxed

(6

btrs) counter

DISPLAY LIST COUNTER

tr.7

(10

DI,ISTI,

blts)

Dlsplav Inslructlon Fornat: Each lnstruction conslsts

opcode only, or of

an

opcode

followed by tiro

(2)

bytes of operadd.

of either an

lopcodel

l6'..d.-l \

-.t

loperand |

------Slngle

)----Trlple

-_-t

lOperand

The opcode ls al{ays

Reelster. This opcode

and wll1 cause t\ro these or ln the

opcode of dlrectly inslruc!1ons: blank,

Blank

(

t-byte)

I.,

'Iore

(2)

rwo

Dlsplay I-1st

Instructton Reglster

the

by

the

bytes rrill be

current dtsplay 1lst lnstructlon. It cannot be accessed

prograomer.

6lD5lD4

This lnslnrctlon is used to create I to 8 blank dlsplay

Byte Display Instructlon

EyLe

DIspIdy Instructlon

fetched flrst and placed

deflnes

bytes to be fetched if needed. If fetched,

Counter

ju!0p,

(blackground

the type

placed

(if

(IR)r

There

and dlsplay.

of

lnslructlon

ln

lhe

the instructlon ts

This register is loaded wlth the

axe three bastc lypes oi display lts!

color).

ln the

l4gggTI-.gSeg-9993!CI,

leqlggllgg

(1

o! 3 bytes)

a Jump).

llnes on the

(3-bytes

Dlsplay

(1

or 3 bytes)

D7 I t5 - D4 0-7 = r-8 blank lines D3-D0 0

)

D7lD6l Xl Xl 0l 0l 0

Thls lnslructlon is used to The next two bytes

D7 D6

D5-D4 D3_D0 I

Thls lnstructlon

display block. D7 I = dlsplay

n6 n=l hvts.i^cfr,r.rlon

D5 I D4

D3-D0 2-F = dlsplay

-

display llsr

=

blank

speclfy lhe address to

I = dtsplay .I.Lsc

=

junp (creates

0 X = don't care

=

junp

D2IDl IDO

specifles the

I - 3 byLe

uslng address

=

verttcal scroll enable

I - horlzontal

see

"_i' _:t.I

list inEtructlon

Inscrucclon

node

following

InsLrucclon inEerrupt

reload the Dlsplay List Counter.

be loaded

lnscructlon interrupt

one blank ltne on dlsplay)

end of nexl

type of dlsplay

(reload

ln next lwo bytes,

scroll enable

(memory

pages).

character

or

inteErupt

vertlcal blank

Memory scan Counter

for the next

(LsB

LSB ftrst).

-

map

first).

II.8

.rr

x

FH

r&ts]t4 l&ht4 I'r E ts trhErEl

ts.o6<raoatsl

F@6<lq(JAln

Fco6<fq{JA[r]

r@6<14()aFr

N.o6<FqL)crrIr

ro6<i0<JApl

Fco6<rcrJoFt

(co6<F(JAd

Nco6<Fq(j,a

Fco6<laL)FIIr

F@6<rC(JAtst

ts@6<lqc)A14

F@6<rO(,)OEl

tsco6<roooFl

;

ts@6<laOAF.l

6ts@o<FOOtsl

--!

-----1

ttl

| | II

I

,

Btt 7 of list can

The lype of NMIST, The

lhe user's dlsplay

.olng

tnterrupt

change the

detatls.

a dtsplay

1f btt

colors or lnterrlpt current

1lst tnstructlon

7 of NMIEN 1s

graphics

ls derernlned

0S will vecror

1lst

lnterrupt

can

be set to

set. The

durtng

by checklng

through VDSLST

rourine.

dlsplay 11s!

the nlddle

See the OS nanual

create a dlsplay

lnternrpt

of the

NMIST. NMIRES

(Itex

TV dlsptay.

200

and 2Ol)

for proarau-

coile

clears

to

Blts 5 to enable depends later).

Meoorv Scan

progtaEner.

(non-Junp)

Thls

directly rane

a the reglster 4K

byte Load Meinory

strlngs

A single

contimratlon

l,lSB

and 4 of

vertlcal

on

the values

1s loaded

It

1Tlstruction.

counter

displayed

to be tndtrectly

byEe lnstructlon

In rremory of data

instructlon.

and

12 of actual counter,

boulldarles.

thlrd byte of 3 byte

hwrc lnorh!.r l^n

a dlsplsy

and horlzoflta1

ln the VSCRoI

Counter! Thls

wlth the value

pohts

(Eemory

Scan

to the locarlon

nap dtsplay)

displayed

Stnce thls

unless the

Counter instrucllon.

type of dtsplay

scro111[g.

and I{SCRO],

counter is not

or ro

(chalacter

does not reload

to be dlsplayed

counter really conslsts

a conttnuous menory

counter ls reposltloned

The amount

in rhe last 2

(address)

llst inshuctlons

of scro1llng

reglsters

dlrecrly

ln mernory

locatlon

the

dlsplay).

thts counter.

frorn that displayed by

LSB Second byte of

byte

(to

be descrtbed

accesslble by

bytes of a 3 byre

of data ro be

of characrei

Thls lnp11es of 4 btts of

block cannot cross

wlth a 3

lltstrucllon

are used

the

3

tttlttttl

15l 14l 13l r2

Flxed

Menorv Memory nap a shlft reglster required

Scan Counter) is dlsplayed dtrectly $hen executlng

dlspfay lnstruction.

(4

Map

bY the lnslructlon.

tttl

110

btts)

Dlsplav

so that it can

Instructlons: Data 1n nenory

data is betng displayed

As

3'2t1

Counter ( l2 bits)

(addressed

1t ls also

be

redlsplayed for as nany TV

2

by the

a nenory

stored

1lnes

(btt)

1n

as

1r. l0

Menory Addresses each byte

Scan Counter

Mernory

one l1ne worth

loaded tnto the

Shlft reglster data 1s dlsplayed for four Tv scan 11nes ln thls exarnple.

In Instructlon Regtster

blts of nemory are

of

the screen.

by 8

(BASIC

OS. Ttese nodes have rectanguLat plxels, wide as they are hlgh,

ltnes.

TV

GRAPITICS comand). Tvo nodes,

rdenory

of

shlft reglster

used to Plxel The 0S and BASIC support nost of these

1s

(IR)

dtsplay nodes 8 through tr', one or two

spectfy lrhal

slzes range froE l/2 clock by I TV llne to 4 cLocks

1s to

C and

be dlsplayed on

E, are not supporled by

lrhlch are approxlmately tlrlce as

grephlcs

each

nodes

plxel

the

In IR Eode F, only one luElnances correspoodlng lunlnance ts deterntned by

In

lR zero lndlcales background color and dlfference

In IR modes of each l{olrever, only

aB

SHIFT RECISTER

ptxel,

in the

avatlable.

are

plxel

modes between the varlous modes

four

prevlous

cones fron COLPI'2. If

9,8, and C, two different colors can be displayed. A

8,A,D, and E, two btts are used to speclfy

This al1ows four dlfferent colors ro be dlsplayed.

plxels Ecdes. The bi!

7

6t5

color

If a blt 1s a zero. then the lunlnance of the

the contents of CoLPFI

can be

413 2tt 0 | 7 6t5 4 2 tt 0

(CoIPI2)

packed

can be dlsplayed. T\ro dlfferent

btt 1s a one, them

the

(abbrevlated

a one hdlcates ?f0 color. T1le

1s ln the slze of the

each byte,

llrto

asslgnnents are

lnstead of elght

shoqrn

belor.

to Pf'l).

plxels.

the

2 blts

one

color

plxel

the

foro

II.

I1

l4eoorv

}lap Dlsplay ltlodes

oS

I

and

l1nst. I

BASICIRes.

odeslHEx

| | I | | I

s

lAl

ltl

lcolors

per

uode

I |

4

Plxels

per I per srd.

Line I ritre

|

lBytes lstd. I

40

l80

160

I

Iscen lColor I lLlnes I

per I per

lPtxel

l0 814

clocks

lPlxel lPlxellPixel

I

ro | 4

I

Blt

I

Btts

I lper

| 100

lvalueslcotor

tn

I

OI 10

101 l?30 lr0 lPrl

0

I

00

2 I 0l

r0

I

Rec.

I lselect

BAK

|

PFO PT'I

BAK

?r0

BAK PTO

?r1

160

I

40320

ttttl

0l 10

Prl

I

IGIIM)

rt.

t2

Character Dlsplav

map

dode 1s

character set

bytes of

data depends on also depending address Only the most descrlptlon addless acceptable

to cxeate a character

at hex E000 nay

!g!g

of the character

are assuued to

for the

slgntftcant

ln sectlo[

page

Instructlonst

graphlcs

the hode.

on the oode.

set ls stored

III). The be zero, so

boundary.

The flrst step 1n

set ln neEory

be used). The

for each character.

The charecter set

The USB

s1x or seven blts

(l,losr

ln CHBASE

other one or two

lhe character set fitst

ushg the character

(or

the bu1lt-tn OS

character set contalns

The neantng of

can contaln 64 or 128

Slgntftcant

(or

of CHBAS are

!yte) of rhe

the OS Shadon CHBAS).

used

blts and the LSB of

start aE an

(see

elgh! the characters,

CIIBASE

the

Tte dext

Then the

lgggg

nene selects froE 0 through 0 through

used

placed

are reglster as shol'n

counter v111

na.oe

CIBASE are byte glvlng

of

CEBASE,forclng

The

1024

actual dtsplay

or codes. Each

127

to speclfy the

Character nanes

ln a shtf! rotates, belon.

After

for lhat In 20

Eenory

The

aet

bytes for

a full 1lne of

character

used. Th{s

boundary.

a

rotal of 512 40 character per

rrust

step ls to set

1s set up.

nane takes

a character.

(decloal).

63

(declnal).

color or orher

(codes)

reglster.

changing only

lncrenent.

ftne rnrmber.

the

have

128 charactels

the set.

The next

f'er

requlres The set Inlst

bytes for

character set

up the dtsplay 11st

Thls constsrs of a

one byte. The last

For a 64

The

are

character data

ltne modes

ltne

charactet set, For a upper one or rwo blts

aodes

128 characrer ser,

speclal tnfornatlon,

fetched by the neroory

On any

the nane

l1ne agaln

the seven

that the

the charactet

conratn

use the slx most

to start on

of

8 bytes

glven

portlon

has been

ltne

addresses all

nost slgrlflcant

64 charcters,

each.

for the destred node.

strlflg of chatacter

6 or 7 bits of

the naEe would range

rhe range \rould be

of rhe nane byle are

dependtng on the

scan counter,

of dlsplay

of the character

dlsplayed the

set !o

slgnlficant

a lK byte rnemory

gives

Thls

the shifr

address,

line

characrers

birs

statt upon

8 bytes each,

blts

boundary.

a total of

the

and

by

of

a 512

ltex

I lCode

Graphlcs

Mode

f4l

chars.

I

L tne

Nunber

of

II.I3

laytes

lNunbe.

I28

lnytes lln

Char Set

(20

Character

Characrer

Dlsplay

per

llne mode

Internal codes for

exarnple)

shlft

Resls!er

Codes Stored ln Shlft Register

(naines)

Character

Color

Reglster

Select

Data

Addr:ess portlon

Character nane

Address

of

Llne

Char:acter

1n llemory

Set

Addresses

and displays

TV

Color assigned

by color

sefected

data in

reglsEer

on

the

0

I 2 3 4 5 6 7

TV

S can

Lines

r1.14

There

and

7 are supported by

are slx charcter inap modes,

IR rnodes 2

the OS and BASIC

through 7. Modes 2,6

(GRAPHICS

0,f and 2).

.-

In IR dodes 6 one of four playfleld selected background color

playfleld

color ts dtsplayed.

glves

a total of elght lines htgh and data byte ls dlsplayed

In IR nodes 4 and 5, each

of elght

(as

ln the olher nodes).

select one of

used

to select lhe character. If the most

the[ data of 10

blts of l0 select PF2. wlth dlfferert

roodes

lc

This

In IR

makes standard \ddth 11ne. These nodes are lur0inances In IR mode

can be dlsplayed, but only one color 1s available a! a tllle. 3,

and 7, the upper two

colors,

For each

color is dlsplayed.

The four characler colors

flve dlfferent colors.

dode

the

7 characters are slxteen lines htgh

bits of each character Iraoe

3e!g

bit that contains

For each zero data btr,

loode 6 characters

the

plus

a one, tfre

the

the background

for two ltnes).

plxels

i{de lnstead

of data are used

eqEg

nane blt ls

three

(binary)

p1ayf1eld

selects P]I.

Thls

character ls only four

Two btts

per pixel

colors, or background. Seven

signlftcant

If the nane blt 7 1s one, rhen data

nakes

possible

it

to dlsplay l\no chalaclers

colors, uslng the same data but differenr nane bytes.

2 and 3, each

posslble

to have forty etght-pixe1-wtde characters in a

each character ls

plxel

half of a color clock tn width.

is slnllar

to r0enory loode

l0 Unes high. This nakes lt

F h

posslble to

(each

bits are

that two

deflne loner case characters w_ith descender€. Tlle las! fourlh of the characte! set takes the flrs! !!r0 displaylng

(naEe

blts 5 and 6 equal

dala

bytes and noves then to the botron of the characte!,

one) is lowered. The hardware

to

two blank l1nes at the rop of the character

(see

selec!

are

to

a zero

\-

In IR oodes 2 and 3. blt 7 of the characler

vldeo or blanklng. This is controlled by CHACTL blt 2 of

CHACTL

upslde dolrn, reeardless of node, If

character \.rhich has blt 7 of 1ts nane set

vtdeo

(the

luBlnances will be reversed). If CHACTIeach character whlch has blt 7 set w'l1l dlsplayed). Characters

I and loggltng CEACTI- bit 0. Inverse vldeo and

modes 2

ard 3.

w111 appear as an lnverse

Ilardware collislon

provlded

to

playfleld. addresses D000 thlough

ls a one then all of the characlers will be dlsplayed

CEACTL

bil I is set, lhen each

l{lll be displayed in inverse

be btanked

can be blinked on and off by settlng

blank

If both inverse vldeo and blank are set then

vldeo

blank character

(solid

Delectlonr 60 bils of colllslon delect and store overlap These collislons can be read by the

(hits)

belreen

Dicroprocessol fton

D00I. There are no btts for nisslle to

co11islons.

16 bits for

ulssile to Playfield 16 btts for Player to Playfield 16 blts for }Ilssile 12 bits for Player to

to PlaYer

Player

(P0

io PO allr'ays leads

narne

ls uaed for

(character

co$tro1).

blt 0 is set, then

(on1y

background

nane bil 7 to

apply

only to IR

the character

sqrare).

register are

players, misslles and

nlssile

as zelo,

inverse

If

wil be

e!c.)

The l/2 clock lleDory

node

(IR

codes 0011

be slored in btl 2 of the

nap node

(1R

and 0010) are both

playfietd colltsion registers.

T1.15

code llll) and lhe l/2 clock playfleld

2 coLltsions and

type

chalacter

w111

Data

Upper Case

IR l,lode

3-Upper and l,ower

Case

Act\ra1 Dlsplay

E

II.I6

Chalacter

Map Displav Modes

os

I I lBAsrclRes.

lModeslttEx

I I lchars.lscan lcolor lData lcolor

and

lrnst.loolors I

lper Ista. lper lper

Mode

I

per

lllneslclockslBtrs

lper latts

lLine lchar.l?txel lPlxell

lselect lvalueslcolor

Naroe

Bit

I

rnl 1Il

lDara

I lRec.

lselect

rrrrttttll

ot2 40l8l:ll

I4

-

7

lB{t

l'o I I

7

lBlt

7

lBtt

l=0

I I

7

lBit

o

|

lr lPrl

0

I

01 l0 1I

00 01

l0 ll

II

I

PF2

PFT

?FO PTI PF2

PF311

BAK PFO PFI PF2

PF3

| | | | | | |

00 OI

IO

00 0I

10 1l

I

0

I

I I

! o

I

L

BAK PFO PT'I PF2 PF3

BAK

Pr'0

?FI

PE2 Pr'3

rr.17

Vertlcal and to Eove srnoothly. of nenory. of

the screen rfils! 6oved easlly Ilorever,

llowever,

ln a

thls

results

to another, not

(VSCRoL or vertlcal character

done by

the nenory

another

and HSCROI,)

notlon,

helgh! vertlcally.

lrrcreaslng

scan counter

characrer

llorlzontal

Me.oory

thls 1s

be noved

jerky

Flne Scrolllna:

playfield

nap

extreEely

snoothly. Character playfleld

fashlon by

1n a large

a smooth Dotlon.

and counters

up to one

character wldth horlzonrally After this ouch

the value in

ts nodlfled

distance,

?layfleld

can be rnoved

tlne-consunlng

chaoglng the nenory

posltlon

For

provtded

are

junp

fro.n

thls teason hardnare

ro a1low snooth horlzonlal snooth xnotion has

these reglsters,

and sDooth .0otlon

objects are dlfflcult

by rewrttlog

secrlons

if large secrlons

oblects

can be

scan counter.

one character

posttion

reglsters and

up to

one

been

nenory 1s reErltten or

1s resuned for

Vertlcal upward by dtsplay

blocks at

varlable

zone trlist ehortened

verElcal

ScrolllnA:

uslng VSCRoL

the upper and lower slze. In

be shortened

fron

the botton

A zone of

and bir 5 of

froid the top, and

(t.e.

be dlsplayed).

The vertlcal counter vertlcal standard for

wlthtn

scro1l1ng,

va1ue,

upper and

character

If btt 5 of the display

blocks, then If blt 5 of display

blocks, the second block r'llf coun! shortens

that

dlsplays, it 1s

the

up until delta=VSCROL, lnstesd of

dinenston

the ANTIC, called

lt starts

detelnlned by

lolrer case text

7 or 15,)

lnstructlon renalns lhe second block 1s displayed

lnstructlon goes

dtsplay

block fron the botton.

To deftne a vertlcally sel blt consecutlve blocks but reFrlttren conslan! the standard

5 to I ln the first dtsplay instnrctlon

the lasr one. If rhe VSCROL regisrer is no!

on the f1y, thls results ln a rotal

IujDber of 11nes

(provtded

lndlvidual block stze). If N rop block will be N-VSCROL VSCROL +

I 11nes:

followtng page

1s an exanple of a scrolled zone, top block, for 8 VSCROI-

(N-VSCROL) + (VSCROL

valuesforN=8.

playfleld

on the screen can be

rhe dtsplay llst lnslructlon,

boundarles of rhe

particular,

the flrst dlsplay

the last dtsplay block

not

all of the top and botton

of each dtsplay block 1s

the

'De1ta

Counter' at 0 on the firsr line, and counts the current dlsplay lnsrruction.

display, the end value is

zo[e Eu6t have a

block rrithln

ftrst be

blocks dll

controlled by a 4 btt

(DCTR),

Wlrhour

up to a

(Ex:

Ior 5

9.

unchanged between consecutlve

1n the normal fashlon.

fror0 I

to 0 between two consecutlve

\'111 start tu{th Delta = 0, as usual, but

lhe standard

value.

scrolled zone, the most dlrect melhod ls

for that zone, and 1n all

scrolled

zone that has a

that the VSCROT value does not exceed

standard block size,

and the lasr block wtll be

),

=

111.

Shown on the

l1nes

(N

>

VSCROI

1s lhe

+ 1)

scrolled

The

lhat

color

Ihls

to

che

Horlzonlal scrolllns is descrlbed

II.

under

T8

HSCROL ln sectton IIt,

o

I

2

T1

2

li

5

1

-l

I

2

I

2

5

-t

I

z

-2

I

z

l

5 7

I

fz

I13

I

3

t:

5

7

z

5

7

2

3

T

5

7

J

I

l

2

z

5

3

5 T

I

2 3

z

3

5

7

I

2 3

5

F

'7

I

2 J

5

7

I

2

J 4 5

7

-,

S+np19

. _ .

whlch

slandard

R-Al1

nlth nachtne, are

hex 70's 4 teUs address te1ls next code

The

960

The atattlng

MSB

scan nodes 10

23

for address bytes oS lErst

of

Thls counter

on

the

Dlsplav

dlsplays

screen room the

the hardware

(7C40).

the hardware

bytes

Junplng

are

address

the

ls a

dtfferent

example

40 characters

ntdth.

for dlsplay !o create

Thts

specify

and walttng

to

Junp

the

set

up the

of

address

slEple

1s only

tn

Llst

.The

the

character

l1st to

ls

to

dlsplay 23

to ts

11st

of characlers dlsplay

the

of

rhe

exardple

loaded

ltnes,

Sectlon

Exanpte:

OS sets

would

24

blank

reload

rhe

nore

7C20,

dlsplay

character

at one change IV.

BASIC

across

the

aildress

one

ltnes

until

1lsr pornter

because

by 24

up the allsplay

nanes start 1i[e6.

Bernory

of

line

of rooile

the

rhe

start

to

11st

ser

point.

chiracrer

starls

ro\rs,

at the at hex

The next ih. d.t.

of IR end

be dlsplayed,

(7C20).

(EO).

orlly

top 7CiO.

scan

noale 2

2

of the

(oirsiu

It

one

It

ls

eets

out

in os

Thls of UU. byte

cou;ter

to

characters.

alisplay

also

node

posslble and

1s IR

lts!

The

1s

wlth be dlsptayed. characters.

nex!

verllcat

40 bytes per

;nd DLISTL)

sets CIBASE

ls used

colors,

graphlcs

node

near

flext

the

On

a three

a hex

the follor,lng

Eex

llst.

and

to have

etc.,

node

2

nlth a

top

of

32 K_byte

bytes

42,

The

The 2

The

4t

is rhe btank, The

flext

l1ne.

to the

the roenory

different

as shor,rn

O

II.19

Mode 0 Dtsplav Ltst

0S

(40

chars x 24 1lnes)

Ad.i raee ahav\

7C20

7C40

Data

70'\ 70

70)

42) 40

7C)

i)

;l

'.(

2l

i)

-)

4l

20

1C)

l

)

(hex)

24 blatrk

1

reload

roode 2

IR

I

t

23 nore IR

Junp back to 7C20

walt for end

1

960 bytes

(character

l1nes

meroory

mode 2 tnstructions

of dtsplay data

naoes)

acan counter r.Ith 7C40,

and

of vertlcal b1ank.

cvcle countlns: As explatned

cessor runs at a rate of 114 machine cycles

ate 262 Ilnes (The

PAL

Each nachlne cycle are 228 color clocks on a TV 1lne. The have a

40 screen 1!

(WSYNC)

uachlne cycles betore the beglnnlng of the

thus change the next 1ine,

xefresh ls that each byte fetched dlsplay Ilst BeEory nap inslruction

ls

every l1ne,

refresh

and one cycle every'other 11ne ln the tlro 1lne

DMA can be enabled rlthou!

enabled lhen olsslle DMA n111 also be done Player DMA iequlres 4 cycles every one or tlro resolution

ptxel

nachlne cycles. Thls 1s !,'hen the bean returns to the left edge of the

lnstructlon stops the 6502. The

The ANTIC chlp steaLs cycles fron the 6502 tr order to

and fetch

only

conllnuea

l,rsstle Dl4A takes one cycle

per

TV frane and 60 frames

(Europeor)

slze of Il2 color clock by I TV Une. Ilorlzontal blank takes

preparatlon

graphlcs

fetched

unless

used.

systen ls dtfferent. See

ls

equlvalert

for dtsplaytng the next TV 1lne. A walt for Sync

or colors durlng horlzontal blallk lfl

graphtcs

on

the

pre-enpted

durtng vertlcal b1ank.

data ehen needed. The

fron nernory re$lres one Dachine cyc1e. If a

flrst 1lne. MeEory refresh takes 9 cycles

dolng

prevtously,

per

1n length to 2 color clocks. There

highest resolutlon

processor

extends over several llnes then the

by a htgh-resolutlon

per

l1ne ln the one-1lne

playex

DMA. l{owever, lf

the ATARI 800

per

second

the sectlon on

(see

llnes, dependlng on the

Tv ltne

on

the NTSC

ts restarled exactly 7 11ne.

Tv

general

graphlcs mode. Menory

Dl4AcTL, GMCTL blls).

5502 ndcropro-

(1.79

MHZ). There

(tls)

NTSC

graphtcs

prograo

lhe preparatlon for

do memory

rule to

resolutlon Bode player

Bysren.

vs. ?AL.)

nodes

can

r:emenber

data

out of

DMA ts

II.20

Each

fetch of

are required

for

a dtsplay

a three

ltst byte

byte tnstructlon.

takes one

cycle, so

three cycles

Player/mlsslle

during horlzontal

the

first l1ne

In nemory

nap modes,

of the display

use ln succeedlng

fetched graphics

dala iB

the fetch the refresh screen

tn

the hlgh resolutlon

occurs

durlng

the first

data needed

fetched,

In

lhe 40 x 24

cycles durlng

character codes

cycle

wldth

lnstead of

so two Denory

The menory

every four

refresh

A11 lntelrupts Wlth horlzontal

depends scrolling 1s

standard o!

b1ank.

The time

on

at which ANIIC

the

enabled.

graphics

see I{SCRoL.

and display

b1ank, tf

they are

the

l1nes,

In

ltne of

for that

slnce ANTIC

character rdode,

the

top ltne of

and

the usual

refresh

ls done

rnodes.

cyclea

reach

narrow

unless

the 6502

screen lrldths,

node,

Horizontal

list

lnstructton fetch required for

graphlcs

dara

hst instruc!1on,

character

each ron

llne.

renembers

nodes, the character

of characters,

Or the next ltnes,

the character

&{th

a standard

each row of

data, so rhere ls

[1ne. ]-ess DltA cycles I'ould

fast enough

Once rnenory

pre-enpted

refresh

by Dl4A,

near rhe end

refresh DMA

does cycle

screen

stealing

{1dth and

scrolling

take llne.

place

the next

ls fetched

lhen saved

DMA

as needed rhroughout

by ANTIC

codes

along rrtth

only ihe

codes.

screen wtdth. nost

chalacrers

only rlne occur in

!o nake

ts requlred

up

slarts or

ale requrleal

for one oenory

wlth a narro,

thls case.

for

the lost cycLes

a 1lne, lt

of horizontal btank.

starts after

the end of

ls deterndnlstlc,

nhether or not horlzontal

reqrtres extra

graphtcs

for

are

the

graphlcs

of

to

but

data:

ANTIC delaylng clocks inlernal

does horlzontal

the

tlne at which

(which

lnvolves half

delay.

Theoretlcally, or

colors

I'lth

all ard ls

There These

which adds

rron

the DMA

beyond

are a mlnber of

occur in

in

the flyi, t.e.

going

the scope of

the ANTIC

lhe color infornatlon.

the fly is dlfferenr

scrolllng

1t DMA'S the

of a nachtne

it

possible

ls on, rhe cycle

thls roanual.

delays assoclated

and the

fron

that for changtng graphlcs

of an

data. To do

cycle), ANTIC

to write a program

during

the nlddle

counting

CTIA, The

Thus

II.2I

even rllnber of

color clocks

an odd nunber

has a one

vhlch changes

of a TV llne.

gets

with

to be

the display of

qulte

ANTIC sends data to

the rlnlng

for changing

on the f1y.

by

of color

color clock

graphlcs

Iiowever,

conpltcateal,

graphtcs.

the CITA

colors

on

Itortzontal

When DMA ts enabled, cycles are slolen at the tiEes shown belol'.

End of

Lprevrous+l ll,lne | |

I,ISYNC

Blank

Horlzontal BIank_____J

20 nachtne cycles

DUA

Tlntne

(40

-_

. ^t -

r-v rerresn cycres. char, and dara DMA

orr.hl. m-,{ c )

Interrupt Address

Player Dlsplay 1ls t Mlsslle Dl,{A

color clocks)

graphlcs

(depends

(3-byte

DMA

lnstrucrion) lnstruction

on

dlsplay

fetch DMA

llst

Cycle Countlnq Exanple: dlsplay l1st dlsplay list DI,IA takes 32 nachlne cycles. It takes 960 cycles to Dl'lA rhe characters and 8*960 to DMA

cycles for each of 262 1ines, except for the 24 tines wnere the characters

are read, where only I refresh cycle occurs.

Thus tbe total DMA 1s 262 llr\8 with 114 machlne cycles cycles node 0.

(Untted

The PAL systeu has been destgned so that mosl belng modlfled. hardtrare

system

per

NTSC vs. ?Al, Svstens: There axe tr^ro verslons

lt Is runnins on

given

DMA descrlptlon

dtsptay llst

chalac!ers character data refresh

!ota1

fraDe. Thus 362 of each

States T,V. slandard)

Ilowever, sone dlfferences nay be notlceable.

reglscer

page

on

(PAL)

per

vhich a

and adjult;ccordlngly.

fhis exar0ple

II.24. This dlsplay lisr 1s 32 byres long so

characrer da!a. The refresh DMA

the

uses the 40 char:acter

Machine cvcles

40x24 = 960 950x8

262xe-24x8

=7680 =!!!!

1083 8

frane ls

and

progran

10838 nachine cycles. one fraroe

per

ltne for a total of 29868 nachtne

frarne is required for DMA tn 0S

of the ATARI 800: the NTSC

(one

PAI-

of

the European T.V. standards). programs

can read

deternlne

to

wlll lun

by

24 l1ne

takes 9

32

graphlcs

wlthout There 1s a which type of

..__

-

The PAL T.V.

gaues 1lnes

fot thts llsts be nodlflcetlon.

lflll be slot'er

per

by adding

do not have

shorter.

frax0e

PAL ATARI

has

a slo\rer frame

irnless

(312

lnstead of

extra 11nes

to be altered.

800 colors

rate

an adlustneflt

262r.

at

the beglnnlng llor,rever, are simtlar

(50

Hz.

instead of

is oade.

T\e Arart 800 harilr,rare

thelr

to NTSC because

pAL

has roore

of vertlcal blank.

actual vertlcal

60 t{2.)

cordpensates

of a hardware

so

T.V.

Display

heisht

\1111

B.

frequency, frequency port \rhlch

ously can and blts resolutlon, channels

and reduced

MEZ.

audlo chamels Thus eech clocked at lts by blts senpled change faster the dlvlders the low freqrency

POIGY

Audlol

block dlagran.)

selects

Irequetcy

fron 54 alternately 4 can alternately

4 and 3). Thls

Poly

4 blt)

Thel!

by the

Ttere are

nolse,

dlvider,

the tlolse

Dlvlders:

KHZ or 15

2 chanrels

of 8 blt.

Nolse Cou[ters:

used !o

to 9 bils

outputs,

at

channel

olrn frequency.

5,6 and

'rdlvtde

than

are therefore

4 seni-tndependent

arld volune

controlled

Each

KHZ.

be clocked

be

a11on6

of 16

generate

(AUDCTL

however, a rate detelnlned appears ro

7 of each

by

the saopllng

noise

to

control.

channel also

(poly

A11

from

clocked \di!h

rhe followlng

btt resolutlon,

There

random

blr

contatn

A1IDCX regtster. N[ frequeocy

acting pass.

audlo channels,

Each has an 8

by an counler)

4 frequency dlvlders

(AUDCTL

7), These counlers can be sampled

Thls poly

8 blt regtster

has an 8 btt

conrent, and

btt O).

1.79 MHZ

ale

nolse. The

by

!ate. IIr

asirlow pass,'filrer

(AUDCTL

the output of

oprlons:

or I

polynoEial

3

tndependently

each channel,s

separate

dtvldet,

poly

counter noise

Because

these nodes

Ire$ency

17 btt

lhe output obvlously

each lrith its

"dlvtde

b1t

(AUDFX).

conrrol regtster

the volune.

can

be clocked

dividers

bits

6 and 5).

dividers

4 channels

channel of

counters

poly

are ;11

counters the

clocked by 1.79

frequency dlvlder.

saopllng is controlled

poly

(poly

clocks,

by Ni,

(See

andlo-serlal

(AUDCX)

slmrltane-

I and

Dlvlders 2

I and

of 8 bits

16 btt and 2

(17

b1t, 5 btt

counter can be by the

(3

types) counters are noise outputted)

allo\rlng

3

four

cannot

(AUDCTL

o\rn

3

only

The output

pure frequency can be routed

tones

set by

of the

(sqrare

through

rrave

the

ridtvide

a high pass

notse control

type),

by Nri countet

polynonlal

or

ftller

circult

rr.23

descrtbed above counter noise

(1o\r

pass

1f desired

at a rnaxlurE

clock).

(ALIDCTL

conststs

This output

blts 1 and

of

Audio Nolse tr1lters:

trreqrelrcy

Notse

Frequency

Any chanflel nolse output

voL

chennel

-byN

channel

(or3&

-bvN

,)

Chendef I output

;\

,J

(vtthout

(wLth

fctaonet

lL-

I

v

high

htgh

o' "

pass

t

f11ter)

fllter)

f!equency

Chamel 2 output

(!?-lth

Clock

blgh

pass

Freqtrency

filter)

"D'r

a

tha[ the clock ra!e,

the two

nolse whose

channels

by the

the

to

hlgh

ftlter,

Thls

pass

filter conststs of

"Aigh

excluslve-oR

foUow

pas8

filter

Pass" c1ock. The input and output

lf the

(ll

or 00)

pass

fllter,

clock

hlgh

The

1s lncluded ooly if bit I or 2 of

Gate. If the fllp flop lnput

lt

loput and

pass

Lower

is

gtvtng rate. Only

pass

clock for channel 2

very 11!t1e drtput.

passhg

clock fo! chatlnel I

Elah Pass Fllters: The htgh attd an elcluslve-OR Gate. Ihe noise control clrcult outpu! ls thls fltp flop dt a rate set of the lllp Flop ls changing mrch through the excluslve-OR Gate. l{owever, the f11p flop outpul w111 tend Gate lnputs lll1l nostly be tdenttcal Thls olnftolid

AIIDCTL ls true.

glves

I

and 2 have such a htgh cones froo the channel 4 dlvider.

fro.n the chanfle] 3 dlvlder. The hlgh

the effect of a

frequency 1s set by the htgh

pass faster than the clock rate, the stgnal !1111

through

crude

pass

fllp flop

sanpled

pas8

easlly

excluslve-oR

by

cones

J9Jtg9_994!gf:

each chennel. Thls ts a

allons selectlon of one of 16 true audlo lnFrt. A loglc zero glves codtrolled by bits 0 thru 3 of AUDCX. lnvoked by forcing thls thla nected fron

AUDCX) determlne

zero to the volude control blts of AUDCX. A11 ones slves

an open clrcult

mode

The ardlo output of any chennel can be conpletely turned off by

dlvldels,

the

lhe chaIlnel outpu!. Olrly the volune control blts

A volune control clrcult ls

crude 4 blt dlgltal to analog coDverter that

possible

audlo ltlput !o thls volune clrcul! al\rays

(zero

the channel output current.

current) outputt The volulle selecllon 16

clrcult's arrdlo nolse counters, aod fllter clrcults are all dlscoo-

oltput current 1evels

"voluxoe

input

placed

control on1y" node can be

l.lth

true

at the output of

for a loglc

blt 4

of ALTDCX. In

(0

to 8 of

rnaxfid]n volur0e.

wrltlng

c. SERIA]- PORT

The serlal

1lne, a ser1a1 data lnput

bl-directlonal serlal data

descrlbed ln the operatlng Systen Manual. Data ls transDltted and recelved as 8 btts of serlal data

by a logtc true

(blt)

oulput

ra!e, not 16

clock

port

stop

goea

coflslsts of a serlal data output

(recetver)

clock 1lne, arld

preceded

btt.

tines baud rate. Transnltted data changes

true. Recelved data ls sanpled rhen the

Irput and

1tne, a serial output clock 1lne, a

other rolscellaneous control lines

by a logic zero

outpu!

clocks are

(transolsslon)

start

bit, and succeeded

g$g! to lhe baud

lnpu!

qrhe[

clock

the

goes

Sg4e1_9.g!!g9:

\alrltes 8 blts of audto and sertal nisston 1s flnlshed

(SERoUT)

an empty data), and auto!0attcally serlally start-stop b1!s attached. If the

reloads SERoUT before the shlft reglster 1s conpletely transnltted, the serlal

to the oltput shlft reglster, lnterrupt the

(SERoUT)

transnlssion

Ttre transElsslon sequence beglns lrtlen the peralle1 port

block diagran). vhen any

the

reglster

w111

dara into rhe serial output register

(ready

be soooth and contlnuous.

to be reloaded wtlh the transnl! processor

lhe shlft reglster contenls

responds to lhe interrupt,

transfer

processor

r1.25

processor

(sERoUT) (see

data byte trens-

new data from

lndicate

to

next byte of

ltrlth and

Output data ts nornally transnitted as loglc

leveLs

Data can also be transmirred as two lone lnforDatlon. Thls

(t4v=lrue

rdode ls

by bit 3 of SKCTI-. In rhls node andlo chanoel I 1s transroitled

loglc true, and audlo channel 2 1r the lower tone

of

the tone

Pair.

place of togic zero. channel 2 mlst be

ov=Fatse).

selected

place

1n

of

processor

The

channel 2, lf

1n

lo force a break

Serial Output

serlal

output clock

can force the data

two rone node) by settlng (I0

zeros) code tlansolsslon.

Clock:

goes

The serial output data always changes

true. Tte clock then

outpu! ltre to zero

btt 7 of sKcTL. Thls 1s requlred

returns to zero 1n the cente!

of the output dara blr tlne.

The baud

(bil)

rale of the data and channel 4 audio channel 2, or by the lnput dode

selected by btts 4, 5, and 6

SSJjg!_!.!!g.!.:

The recelvlng

received a conplete 8 blt serlal data

ls autoroatically transferred !o

(SERIN),

and the

processor

ls lnterrupted to ready to read ln SERIN. The read

SERIN, before the next

lnput dala vord receplion is coaplete, olherwise

of

sequence beglns vhen the hard\rare

data

processor nust respond to thls lnterrupt'

clock i3 deternined by audlo

cLock' dependtng on the serlal

(see

SKCTL.

i^rord plus

the 8 bit

charl at end of thls

start and stop blts. This

paraLlel

indlcate an input data byle

an input data nill occur. This over-run 5 of SKSTAT

(if

bit 5 of IRQST is not RESET

(true)

and neans input data has been lost. Thls blt should SERIN

ls read. Blt 7

caused by extra

(or

of

SKSTAT

should also be rested to detec! frame

nlsstng) data bits.

(or

to audlo

when the

has

input teglster

and

wtll be tndtcated by btt

before next lnput conplete)

be lested whenever

errors

'

Direct Serlal Input: The serial data lnput

by

rnlcroprocessor 1f deslred, ignoring lhe shlft reglster,

the

b1I 4 of SKSTAT.

Bt-Direclional Clock: This clock

ltne is clock fron an external clock source for dala, or is used to supply a clock lo

e).texnal devlces indlcatlng the

transnit or receptlon rate. This clock

by the serial rnode selected by bils 4,

at the end of this section.) Transaitted thls clock.

Recelved data 1s

sadpled

on the lfalling

Asvnchronous Serlal Input: Unclocked

known

(input)

(+5%)

rate)

shift reglster is clocked by audio 4 should be used togelher In asynchronous

beglnning of

sl lghtly

different from the rate set by channels I

can

be received

(AUDCTL

nodes,

serial data byte. This allows the

each

channels 3

1n the asynchronots bit

3

and 4 are teset by each

line can be read directly

used

lo elther recelve a

clocking iransnitted llne

d1lectlon

5, and 6 of SKCTL.

dala changes

is deternined

(See

on

the

edge of thts clock.

serial

dala

(at

an approxlllately

modes. The recelve

channel 4. channeLs 3 and

=

l) for lncreased

resolutton.

start blt at the

serial dala rale to

and 4.

by readtng

or recelved

node

chart

rislng edge of

be

Serlal cortrolled page.

Mode

by bits

Control:

4,

5, and

Thete

6 of

ate 6

SKCTL.

useful

These

rnodes

are

(of

the possible

described

on

the next

8)

.

nodes

cne

output

p7

lp6 lps

Note

that

except

lransntt

that

Force

two lone

for the

the

Mode

LD4 lD3 lD2 lDr IDO

Q"t I

D4

Rat

output

Control Break

Two

Mode

output

bortoE pair.

rate

and

1s therefore

clock rate

Tone

Control

o"t

Blrs

rnl

I

(bit

Thts

S(CTL Pot

scan

B1-Dir

c1o

linput

3 of SKCTL)

is because

nor

available

is

tdentlcal

REGISTER

and

keyboard

trrans.

lexternal

lock

Eay be

&

phase

used

channel

for

!o lhe outpur

CTRL

A-asynchronous

R.".in;

clock.

reser

1n

any

2 is

one

dara

;;i;;-;;ali

Also

lnrernal

to zero.

of

these

rare.

lext

tl

lchan

cr{4

14l

lr lcn4

lcran I 12

I

4

CII4

|

cH4

|

ctran

|

Chan

2

4

2

chan

I

l4

cI{4

CH4

Chan

2

Chan

4

lnput

I

4

lnpu t

Chan 0rr I Input

Trans.

lcfock,

lTrans. lChan.

Direc Not

lTrars. lRecelve

C1ock.

lNot

lTrans. lRecleve

4 out

lTrans. lceive lClock

clonal

Useful

UsefuI

on B1-Dlrect.

async.

nor

rale

&

4. chan.

rate set

Rate

set by external

Receive

Recetve

clock ttne.

Rate

rate

Set by

se!

set by

used

asynch.

Chan.

by

External

by

chan.

by chan.

Chan.

(chan

3&4)

(Tri-srare

CIo

(ch.

4)

bvl

on

81-

4

2. Re-

Bi-Dir.

I

ft'o

lone

(bit3)

not

useable

ln these

11,27

nodes

D. INTERRUPT

SYSTEU

There are t\ro baslc types of lnterrupts deflned on the r0lcroprocessori

(non

NMl

naskable lnterrupt)

rhar a rhorough

understanding

and IRQ

of

(lnterrupt

these

inter.rpt

reading all chapters concernlng lnterrupls in

progranmi

ng and hardware manuals.

In this systern NMI interrupls are used for video dlsplay and reset.

IRQ lnterrupts are used for

serlal

porl

com'rnlcatlon,

tlners, and keyboard inputs.

request).

types

the 6502

It is

be acqulxed

recoomended

by

microprocessor

peripheral

devlces,

NMI Interrupts.: Even

though NMI lhe nicrptocessor, this systeE function. are dlsabled interrupt.

1. D7

(Blts

6

and 7 of NMIEN) t{hen lhe€e blts are zero NMI lnterrupts

(nasked)

(see

NMIEN reglster descrlptlon)

-

lnstruction

prevented

and

lnterrupt

has

lnterrupts

interrupt

enabLe

fro![ causlng a xoicroprocessor

The 3 types

(ftrrlng

dlsplay ttrtre

"unrnaskable"

are

(:nask)

on

bits

for NHI

NUI

of

NMI lnterlupts

any

dlsplay

lnstructlon wlth blt 7=1 w111 cause thls lnterlupt to occur

(if

enabled) at lhe star! of the last video line dtsplayed by

that instructlon.

2. D6 - Vertical Blank Interrupt

)

(lnterrupt

occurs

(if

enabled) at

rhe beginning of the vertical blank rime interval.)

3, D5 = Reset Butron Interrupt

(pushtng

rhe SYSTEM RESET button lfi11

cause thls interruDt to occur,)

Slnce any

of

these

lnterrupls rtrlIl cause

processor

the

lo

Jurnp

to lhe same NMI address, lhe syslen also has NMI status blts rrtich nay be exantned by the

processor 5, 6, and 7 of NMIST serve this These

status blts are set

the loterrupt 1s Easked

deterrnlne

to

by

fron

whlch source caused the NMI lnterrupt,

functlon

correspondlng lnterrupt funcllon

the

processor by

the

(see

NI1IST register NMIEN). The

descrtptlon).

status bits toay

Blts

(even

tf

be reset logether by wriling to the address NMIRES.

Tno

of the lntelnrpt enabLe blts autornatlcally aie inilially

durlng sysren

dlsabled fron being lnte.rupted They can blts 6 and be dlsabled by the

then be enabled by the

7 of NMIEN. Except for the reset button lnterrupt, they can also

processor The reset button cannot be dlsabledj allowing an posslble

"hangup"

conditlon.

These NMI lnterrupt ovetlaps) NMT

translrlons required by the ntcroprocessor Iogtc,

and converted to

* -

NOTE: Blt 5 1s

should not be

po!/er

(nasked),

before

turr oo and therefore these

preventing

proper

processor

by writing a zero lnlo bits 6 or 7 or NMIEN.

functlons are

pulses

by

never dtsabled

pressed

durlng pover

(blts

6 and 7 of NMIEN)

are cleared NMI internrpts

any pover turn on servlce routlne

lnltiallzatlorl of reglsters and

nheneve! deslred, by

unstoppable

each

the

separaled

systeo hardware, in order to supply

and therefore the

ln tlne

Reset Button

wrltlng

escape from any

(to

turn on.

r1.28

polnlers.*

lnro

prevent

IRQ Tnterrupts:

_ -

of

rhe

sratus dtsable power

bit,

Eurn

there

lnterrupr

porrer

by

processot

D7 Db

D5 D4 D3 D2

Dl D0

teglster

condltton

autonatlcally on service are

separate

functton

turn

on, and rorsr

IRQ.

=

BREAK

=

OTHER

=

SERIAL ready

=

SERIAL SERoUT

=

TR-ANSMISSION Ourput

=

TIMER

=

TIMf,R

=

TtMf,R /it

(blts

The I

(depression

KXy Key

{depression

INPUT

!o be read

OUTPUT

is ready shift

(audio

#4 /12

(audto (audio

IRQ

lnterrupts

on

the mictoprocessor.

power

by

rortines.*r.

systenr

0 thrll

In

IRQ

lnrerrupt

7 of IRQEN).

be inttlalized

rypes

of tRQ

tnterrupts

of rhe of any

RXADy

(Byte

of serial

by the processor

NEEDED

to

FINTSEED

register

dlvider divider divider

(Byte

be lrritten

(serlal is

enpry).

/14 has

12

4t

are

a1l turn

addltlon

br€ak other

of

serial to

data

counred

has

counted

has

counred

"naskabte,'

This blt

on !o prevent

to

enable

These btts

by

rhe

progran

are:

kev) kei) data

tn

SERIN

data

agatn

by the processor).

transnission

dol''n dol',n do&n

together is

thts

processor

blts

befoie-enabling

has been

leglsrer).

is being

to zero)

to zero) to zero)

by one

se! ro

tnlerrupt

IRQ mask for each are

not tnltlalized

recelved

rransnlrrect

1s flnlshed,

blt

the

of

IRQ

the

and is

and

In addition

IRQEN

and syslen Interrupr

D7 D0 D7 of D0 of

These

.

and

thelr

register.

The

when

lts inlerrupt lndicale true

only dlsable one,

Bit

disable.

\rhen

it is

ro

ldenrtfied

IRQ lnterruprs

lines.

of

?ACTL = peripheral

of PACTL

PBC-L

=

pertpheral

-

Dertpherat

?BCTL = peripheral last tvo

starus

(See

IRQEN

birs

status

an

blts are

PORTA,

reglster,

are I

bits

interrupr

by llrlring

the

interrrlrpr

3 of

It is

IRQST ls

zero "hen

not.

the above

by

stalus

lrhlch

are

interruprs

reset

PACTL,

like

(logic

rrue). thar are reqresr,

a

zero into and

simrltaneously

nor a

rhe

IRQ

inrerrupts

btls

O rhru

generated

"A"

tnte(rupt

'tA"

tnrerruDt

',S',

internrpt

',B"

lnrerrupr

g!9

auronatically

by readtng

P0RTB,

rhe

and

NMIEN

The IRQST

normally

The IRQST

rhe

corresponding

tatch and

serlat

out rs

(enabled

7 of IRQST)

over

the serlal

status enable srarus enabte

dtsabled

fron porr

PBCTL

regtsrer,

Register

enables

horever

logic rrue,

status

bits

set the intetrupt

does

ger

nor

empty

(our

by

blrs 0

ih"re

bus

bit blt bit blr

by powet

e reglster

descrlptions,)

lnterruprs

(unllke

go

and

!o

ar; reEurned

rRQEN

blr. This I't1l

rese!

by interrupr

ftnt;hed)

through

u..

cwo *o.e

proceed

and

Eurn

and port

rhe NMIST) has

zero ro

logic

to

sratus bi!

and

to

true

7 of

on,

B

*x -

NoTE:

An NMI

also

disables

the

II.29

I bit.

INTERRUPT SI]MMARY

NAME TUNCTIONS ENAB]-E STATUS

I

ulsPray

I

NMI

INTERRUPTS

llnstructlon

I

J9!9:

lReset

g]3gL

Button

(Bits

NorEally Zeio

6 rhru 7)

(Dtsabled)

(Blrs

NornaUy Zero

(no

|

NMI ST

5 thru 7)

lnlerruot)

STATUS

RESEl

Address

NMIRES

(Resets

lstatus toeether)

all NMI

(Blts

IRQEN

0 rhru 7)

KEYS rRQST

Serlal

.P.g.!!e

Tlners

IRQ

INTERRU?TS

E. CONTRO1LERS

A varlety of controllers can be

front of the console. Thts includes

keyboard, and ltght

The controtLer

and the PoT

vertlcal

PADD1o through PADDLT, PTRIG'S PoRTB for inpur. Thts is done by

blr 2 ro a 0

0's to the destred a I, allo$.'1ng the set up for outpu!

mode is selected.

Perlpheral

A

Perlpheral

B

pen

ports

a{d mIG regtsters. The OS reads these registers doring

blank and slores lnto its own RAM locatlons. These are

(to

seleci

port.

progrard

by \rrirlng 1's instead of 0's whtle the direcrion control

(Dlsabled)

I | |

D0 of PACTL I D7 of PACTL

I lNormally

(Dlsabled)

|

D0 of ?BCTL I D7 of

I lNornally

(Disabled)

|

(when

the dlrectlon control

avallable).

are read

and STRIG'S. The OS sets up PORTA AND

PACTL to

(PBCTL)

read

settlng

fron the

(Bits

Noroally True

't

Zero

plugged

joysttcks,

Lhrough the

(no

lNorrnally l(no

lNornalLy l(no

PACTI-

b1r 21s then changed back to

porl.

0 thru 7)

interrupl)

zero

interrupt)

PBCTL

zero

lnterruDt)

into the four

paddle

PORTA

or PORTB

register),

The

(pot),

ard

ports

Reset

Correspondlng Bit of IRQEN

(except

(to

Blt

rme)

I

Reset by

I

Reading PoRT A

I

Restster

|

Reading

Resister

|

jacks

PORTB regisers

(Port

then

can aLso be

PoRT B

on the

twelve-key

STIC(,

Control)

lJrlrlng

3)*

all

joysttcks

.I9J9!f9E9:

left

actlvated by

read fron TRIC0

been

(L),

back

These swltches

pressed

The

(B)

and

are read thlough PORTA and PORTB. A fifrh swltch is

presslng

through TRIG3. A value of 0 indicates that a button has

and a I indicares rhat it has not been

the red t!1gger button. The trigger buttons are

foruard

have four s\rltches, one each for righl

(F).

pressed.

II.30

(R),

The

ln a

latcheil and sets stlck

trlgger

the latch

th13 to

use

pressed

reglsters

IRIG

oode. wrltlng

them to

button

value r'l1L

deterrdne

durlng

1. Wrltlng ls change

whether

a certain

are trorroally

a zero to

read

btt

a I to bit

pushed al any ttne

to zero and

joystlck

the

perlod of tiEe.

directLy, 2 of GItAcTl-

2 enables

Ithlle bit 2

that

stay

trlgge!

bul they

dlsables

latches'

the

of GMCTL

qay.

buttons

A

Progran

have

can

the

be used

latches

joy_

If a

is I

can

been

ever

?addles: to th;=;I readlng lhe

jacks.

tOT

(wrth;he paddle The value rhlch

lo\.ers knob to the capacltor

readlng

nev

off the

reglster

up to lhe

tOt reglster

Cootrol)

to charge

21s flrst

pot

the

-2

Btt

capacltors

rh;d O to trlggers

lnallcates

ls the

the

serles

reslstance,

lef!

ilunp translstors

can be

du;p translstols

contalns

threshold

conlains

enables

up the

set !o

scan'

of SKCTL

wlll flever

228

for each

correspondhg

paildles cone ln

The

paddles are read

The

registers at

turned

how dany \.ith the

so the

lncreases

least

Lo the

TV llnes

potentioneter.

capacitor the reslstance are used to

rnode. The

to

blt for

ofle

value

the

fast

pot

capacltors

O lo

The fas!

durop lhe capacitors.

pol

rfirst be set to

dunP.

POTCO command

allow the

each the AJ,LPOT corlect scan.

to the scan

O to use

Note !ha!

due to illfferences

paalille

joystlck (PORTA

palr

are or

palrs,

228 llnes

rlght)

lo 228 1l takes

discharge

capacitors

paddle. l]hen

blt changes

readings.

In thls

maxllffln

is not as

ln the

read fron

PORTB).

elght

so

storlng

bv

later.

(Paddle

to

Turnlng lhe

charges

the

and

clears the

Blt

node,

lt takes

1eve1

Then

accurale

nornal

soue

scan

paddles

pots. The

the left

paddles can-be

lnto PoTGO'

The values

turned

charge up

knob

qllckly' l\rnlng

up

charging tlme'

capacltors

lhe

counters

charge up'

to the capacltor fron one

to zero

2 of SKCTL

only lwo

lnstead

Bit 2 is

of 228

as the

set nornal

mode' 0ther\tlse'

have

a range

left and

right

and

connected

then

range

fron 0 counter-clockrlse) the capacllor

to Lhe

righl the

The

so !ha!

a

and lurns

The ALLPOT

has charged

and the

(Serial

Port

scan llnes

lines' Btt

to I to start

t0ode'

scan

the

srnallel

rlght

paddle

bits for

the

'

Kevboard

pLugs

and teytoara tn itrng

. 0 to

deslred low

wrltten

!o then. controlLer Reference

flrst lhe

and seconil

padtlle reglsters. capacltors

(tire

rnaxiurn). When

capacltor

the glvlng

a POT

crltlcal,

Co[trol1ers:

lnlo

ts to

(see

PORT PlNoIn

Manual

conlro1lers,

Whe[ a

never charge

ls connected

value of about

the fast reqrired between co;ventton

If ls lt colunn ls

loysrick

has beefl

greater lhan 10

read through

trlgger

joystlck

a select a the blt

PORTA,

Colur0ns

contalns colunns

bultofl

the

pot

selectlng

adopled of cor0parlng

(0=but!on

Each keyboard

controller

ron by settlng

tn the PORTA

SECTION

III).

are read

ahart

ln sectlon

a Baslc

of the

plograro uhich

keyboard use

so they are

prished' the

is

up !o

lhe threshold

button 1n lhe

+5V through

to

(thls

2

mode can

scan

rol' and

the

then the

lhe

loysttck

pressed, I=not

ls

controller

pott. The flrst

port dlrectlon

the

or ?ORTB

reglster

The other

lhrough

lhe POT

rll).

Appendlx

the

by readlng

read

pot line

Level and lhe

selected

a relatively

rnay vary).

be used,

3o that

reading the

POT readlog

the

bullon

trigger

has been

ltne,

Pressed)

II.31

has a

slep

iThlch selects

should

rots

and TRIG

fl of the

reads the

plns as the

sane

the

grounded' so lhe

is

lolr and

coluEn sBall

Since the

only a 2 Une

POT reglster' pressed' The

so i! \torks

.

lwelve-key tn using

output

to

have

registers

BASIC

controllers'

(or

PoT

PADDI-)

reading

is not

reslstor'

readlng

wlth

l0

just

pad

the and lhe

l's

(see

The

pots for

po!

228

ls

pushed not

1s

wait

The

(declnar)' thtrd

ltke

a

1s

Llahr

as

lt sweeps

on

the l1nes. pfugged III).

PerI:

across the TV display. Tte

ATARI

lnto

any of

A llght pen

TV

screen.

Appltcatlons

400/800

the

hardware

joystlck

ts a

device

It

1s irsed

hclude

was

deslgned

controller

rhat

can detect

to

selecting

so

porte

polnt

memr

that

a light pen

(see

ena

the electron

dlrectly

ltens

and drawlng

if sectron

beaD

at an irnage

can

be

m:"

.---

ANTIC horlzofltal

any one

chlp takes

color slgnificant nuober per!

l1ght pen exanple, of-the PENH

width at

good

a

of delays

register,

screen

wt1l

dlsplay

a black

ldea

should

the

wrap around

area

rsll1 probably

of the rhe clock

blt

ls inaccurate

lnvotved

eech

systeE

contaln

user

could pol[t

and

the progran

because

of

the

to read

not

hold

joystick

current

value

VCOI]NT

(0-227

and 1n dtsplaytng mrst be cal

a

user-tBteractlve

the

could

fton

227 ro

of

lhe delay.

t\ro

screen,

(or

slnce

nore) values

the pen perfecrty

rrlgger

value

declnal)

should

be lgnored.

the

brated.

Ught pen

coruFnrre

O near

the fhe pen the

elecrron

anal sready.

lines

and

(pln

st;res tt

is storect

alata and

Softr"rare

caltblatlon

at

a crosshalt

the requtreil

rlght halld

rd11 not

besn is

average

6)

rs

pul1ed

in

pENt{.

1n

Slnce

changing

irhtch

routlne.

horlzontal

edge

l'ork lf

turneal

then,

slnce

PENV.

there

the ltghr

uses

tn

the

of a

1t

1or,

the

The

The teast

are

a

the

For

center

offset.

statdard

polnted

1s oif. the

It

user

ls

TI.32

I1I. HAR)WARE REOISTERS

\--

Thls

shadow reglsters.

In the fo1lo\"dng descrtptions,

1s l.

A. PAL

sectlon 1lsts the hardware registers and

(D014)

Not

Usedllllused

D3

I I I NTSC

0 0 0 PAI-

Thls byte can be read by a

progran

the

B.

INTERRIJPT CONTROL

ls runnlng ofl.

D3

I

D2 D]

D2 | DI

|

operatlng Systen

tme ahrays refers to a btt \'rhose value

lNor

(US

TV)

(European

prograrn

deternlne

to

TV)

edlch lype of systeE

(OS)

NMIEN

to the NMI lnlerrupt

(Non

Maskable Interrupt

0 = dlsabled

I - enab led

I

D7 Dtsplay l,tst

cleared by Power Reset, and nay be set or cleared

plocessor,

D6 Vertlcal Blank lnterrupt Enable.

Reeet, and

SYSTEM RESET Bulton

This lnterrup! no!

pressed

be

(ser

tnable)(D408):

enable blts.

(dasked)

Nor

Used

Instrucllon Interrupt Enable. This blr is

roay

be set or cleared by lhe

lnterrupt

always

ls alurlng

ro hex 40 by os IRQ code.)

eflab1ed. The SYSTEI{ RESET

power

turn on.

Thls

This

address

blt

1s cleared by Po\rer

processor.

wrltes

by lhe

button

data

should

1r1.1

NUIST

(Non

Status Reglsrer

0 - no intelrupt

I = lnterrupt

Maskable

(Read

by OS NMI

Interrupr

Status)(D40F)!

code).

Thls address read

the NMI

D7 D6

D7

D6 Thts

D5 This

NMIRES

the Non

IRQST

the IRq Interrupt

(NMI

Maskable

(IRQ

I

This btt Dlsplay

Not

ldenttfies an

List

blt ldentlfies

vertlcal

of

blt ldenttfles arl

RESET butron.

Status Reqtster

Interrupr

Not

Used

(

Wrttten by OS

lnrerrupt

Status)(D20E):

Status Reglster.

Nl,Il lnrerrup!

hstructton.

an NMI inrerrupt

blank-

NMI lntetruDt

Reset)(D40F):

Status Regtster

NMI code.)

caused by btt

caused by the beglnnl'tg

caused b\/ the SYSTn1

Thls wrtte address

(MIST).

This address

7 of a

resets

reads the dala

fron

0 = Interrupt

I - No

Inlerrupt

D5 D4 D3 D2

D7 = 0 Sreak

=

D6 D5

D4

D3 D2=0 Dl-0

Dn=n Tlnor I T^ra?r,,-r

* -

NoTE: Used

0 Other Key

=

0 Serial

=

0 Serial

=

0

Serlal Outpur

Tiner

Tlner 2 Inrerr:upt

generation

for

ln sectlon

Key Inlerrupt

Intertupt lnput Data Ready Tnterrupt Ortput Data Needed

(By!e)

Transntssion

Interrupt

4Interrupt

II

of 2 stop

(no

dlrect reset

blts, See IRQ descrlptlon

on btt

Finlshed

3).

fnterrupt

*

IAI.2

IROEN

Interrupt

Enable

=

0

dlsable,

lqcerrupt

correspondtng

EnabIe

D20E):

IRQST

Thls

blt is

address

se!

wriles

ro

I

data

to

the

IRQ

OS SIADOW:

U€e

.

the

c,

Llne

AND'S

olhers.

TV

LINE

Counter

\7 D6 D5

D4 D3 D2 DI DO

Break other Serlal Serlal

SerlaI Tlner Tlner TlEer

PoXMSK

and

Store

COMROL

Vertical

(ey

4 2 I

(hex

OR's the ilesired

nost

slgDlflcanr

Key

Interrup!

Interrupt Input 0utput 0ut

Interrupt

Cqunter)

Data

TransElsslon Inrerrupt Interrupt

lO)

to

change

Ready

Data

Enab Enable Enable

ialue

(D4OB)

btts).

Enab

le

Enable

Inlerrupt

Needeal

Elnlshed

le

one

bit

tn

both

Th{s

:

InterruDt

interrupr

pOre,ISK

tn

IRQEN

address

Enable

wilhqr!

and

reads

Enable

affec(ang

pOruSK:

the Vertlcal

-

TV

v8

17

Thls Dlcroplocessor' by

the

beglnntng

delayed

v6

address

by 1]lne

sets

caislnS

of

horlzontal

1f

wSyNC

a

1t

v3

latch

to nalr

ts

\2

vl

rhat pu1ls

until

b1ank.

used.

([sed

II1.3

V0

down

thrs

Dlsplay

by

V0 not Tlro resolutlon supplted.

on lhe

latch

fr"t

OS t"yt"".i

read.

llne

is i"t.r*ptr'."v

Rny

llne

autordaticafly

.ii"t-ro"ti"..t

to

1

the

U.

"a".a

reset

"f

D. GRAPHICS CONTROI.

Dl.tAcTL

lnto

the

Not

Used D5

(Dlrect

DMA Control

I

D4

=

D5

=

D4

-

D4

=

D3

=

D2

D1,D0

=

Medorv Access Control)

Register.

I Enable lnstruction

I I Llne P/!l resolutlon

0 2 ltne P/M resolutlon

1

Enable

t

Enable 0 0 No Playfteld 0 I

1 0 standard ?layfleld

Player DMA

Mtsslle DI,IA

Narror

(128

Color

(160

color clocks)

DI'IA

Playfteld

clocks)

(D400):

fetch

DI,IA

n4A

This address

DMA

nrites data

GRACTL.

See

GMCTL

craphlc Corllrol

0S

(Graphlcs

Notlll

Used

D2 = | Enable latches on

Dl = I Enable

D0 = I

DMA ls

DMACTI- only wtll

eenerated.

enabled by setthg

=

I I Wlde

Shadow: SDMCTL

Control)

Reglster.

cleared and TRIG0 control b1t 1s zero).

Enable Misslle DMA to

xe'sult ln cycles betng

?layfteld Dl4A

(

192

Color

(22F)

(D01D):

?1ayer DMA to Player Graphlcs

blts in bolh DMACTL and

clocks)

default

Ttls

D

1'RIG0 - TR1G3

-

TR1G3 act as normal

MlBslle Graphlca

stolen but ro

value hex 22

address \trites

tnprts

GRACTL. settlng

displsy k{11 be

dats to the

(latches

lnputs a'hen

Reglsters.

are

cflAcTl

Character Control Reelster.

(character

control)

(D401)

:

This address \rrltes data

lnto the

Not

Used D2 DI DO

D2

Dl Character Video

D0

OS SfiADO

1o!, byie of

: CHACT

DLISTL( Displav List Low

Character bepinninp of each

line of characters to reflect dofir chalacters).

only). If bit 7 of character code is true

that character

white on blue). Character Blank

o$ly). If bit 7 of charecler code ls true this flag causes lhal character setting bit 7 of changing D0 of CMCTL.

(2F3)

Dlsplay Llsl CounEer.

the

I

Vertlcal

to be blue

!o b1ank.

)(D402):

Reflect Blt. Thls blt ls sanpled at the

line of

Inverr llae

(Blink)

the characters

characters. If true l! causes the

(inverr)

(used

on

lrhlte

Flag

Blinklng characters

This address writes data lnto thc

for 40 Character Mode

(used

to I,

vertically

thls flag causes

(lf

nornal colors are

for 40 Characrer Mode

then

perlodlcally

(for

produced by

are

upstde

oS SHADOW: SDr,sTL

DLISTH

high byte of the Dlsplay

DT

ID6 ID

(Displav

t4 t2

OS SHADOW: SDLSTH

The Dlsplay l-1st lnstructlons regisrers deflnes the sec!1ons

are

I and Il,

(hex

List Hish)

D4

ID3 ID2

(}TEX

addr

essed by

)

TIt315 10

ls a llst of address of the

230)

List

231)

I

I 0

(D403):

Counler.

9

display lnstructlons in memory. These

Display List

the

,List

counter

\

lBtt (Posrtlon,

This address wrltes data into the

f?lserav

8

co'lnrer

\

lBit \?os1t1on.

Counter,

beginnlng of the Display List.

Loadtng these

(See

Not€: The top 6 birs

displav llst can

lhe instructlon ls

used.

are latches only and have no count capabll1ty, therefore

not cross a lK bvte nenorv boundarv unless a

lunD

DLISTL and DLISTIi should

Dl4A dtsabled. Other:rlse, the

in order to recelve

dlsplay list lnterrupts.

be changed only during

vettlcal blank or arllh

screen nay ro11. Bit 7 of NMIEN

r(rs! be set

@:

data lnto the Character Address slgnlflcant byte sectlon

l1), Note lhat the last

(MSB)

of

address of the deslred

the

40 characrer Modes

Base Address

20

Character

12 |lt [0

Base Address

oS SHADoI,J: CHBAS

(2F4)

Base Register. The

data specifies lhe nost

character set

I or 2 btts are assuroed

CI{BASE

Char Nane

Modes

CIIBASE

Char Nane

Llne Counter

Thls address writes

(see

to be 0.

PIfBASE

(?1aver-Mlsstle

Address l'rltes dala into lhe Player-Mlss1le spectftes

the l,tSB of the address

of lhe

sectton II).

One Llne Resofution

Base Address

Player-Mlsstfe

Select

Llne Resolution

Tl'o

Base Address

Player-Mlsslle

Select

Base Reeisler)

(D407):

Address Base Reglster.

player and .0iss11e DMA dala

PMBASE

Player-Missile

scan

Counters

PI{BASE

Player-Misstle Scan

Thls address

The data

(see

II I.6

HSCROL lnto Dlavers and Elss1les.

lhe llorlzofltal Sclol1 Reglster. Only

not

used

(florizontal

Scrolt

| | | |

Reelste!)

D3 D2 DI DO

(D404):

playfteld

This

address L.rltes

ls

scrolled, not

data

clo.k

The dtsplay ts shlfted

speclfted by IISCRoL for

Its ITSCROL Flag blt

When horizontal For a narro\r nunber of bytes

Stun11arly, for standard playfleld wtde bytes

playfleld.

and background color 1s shlfted ln.

VSCRoL

the Vertical Scroll Reslster.

not

used

playfleld

(Vertlcal

(blt

scrol1lng ls enabled, nole bytes of data are needed.

per

llne

ror wlde

Scro1l

lo the

each dlsplay

4 of lnsrruction byte).

(see

DI,IACTL blts I

for

as

playfleld,

Reslster)

I

D2 D1 DO

8

not used

lloe

display

I

Eodes

0 to 15

'iqht

rlght

standard

use the sane mnber

I

color

Fhl fl c

by the mrnber of color clocks

llst

there ls no change

lnstruction that contalns a 1 ir

and 0) there

playfleld

(D405):

Thls

should be

\rlth

no

scrol11ng.

of bytes

1n

the nunber of

address {rrltes

the sane

as for the

dara lnro

16 llne dlsplay

The dlsplay ts scrolled upward by the rnrrober of lines specified the VSCRoL reglster for each display l1st lnstruction that coflta1ns a I ln 1ts VSCROL llag btt termlnate II for

lrlth

Dore

PRIoR

the flrst lnstrucllon havlng a zero tn btt 5.

detalls).

(Prtorirv) (D0lB)

(bt!

nodes

5

of lrlslrucllon

:

This address writes data into the Prlorltv

byte),

The scrolled area rilf

(see

sectlon

1r

Control Reglster.

D7 D6

D7-D6 = 0 D5

l4rltlple Thls blt causes the toglcal

the colors of Player sith Player pLayers

D2 DI DO

Color Player Enable.

0 wlth Player

Thls perrlts

3.

wilh a choice of

3 colors

"or"

function of the bits of

I,

and also of Player 2

overlapping the

in

lhe overlapped reglon.

poslrlon

of 2

III.

7

D4 Flfth Plaver

This bit causes Type 3.

together with

(CoLPI3).

Enable.

all mtsstles

thls allovs

a coomon

to assune

color fot

rhe coLor

alsstles

use as a flfth

ro be

playfleld

of

posttloned

player.

D3, D2,

&

D0

EXA],IPI,E:PRIOR

!9:g:

D1,

The use of Prlority

blt rrue)

turnlng B]-ACK PlO

PF3. In plxel priority. character

Prlorltv These blts hlgher n'lth fol'er

D3=l

?F

0

t

?F

T PO P1

Pl

P2

l

P3

P3.J

?F2

a

+

1P1'3

*

or PFl.

P5

rAr I

code

the one-color

in a

Select

select

prlorlty

Drlorltv.

I

i ll

I

| |

\rl1l result

ln

=

1010

It will

character If a hlgher priority player

then

the color ls deterdtned

(}tutua1ly

one of 4 types

!,1111

PFO PF] PF2

+

P0-l

PI

P2 |

P3

-,1

lhe overlap regton.

Thrs w111

f

P5

I

l"o:-

-

I

blts tn a

in objecrs

also black P2 or

40 character

Is determined by

Exclustve).

appear to nove

Pc.l

J

PI

PFo PFr

i-s

Pzf

P3,J

',not-exclustve"

black

(lrhose

prlorlty.

of

tn

front of objects

D0=l

Pr I

P2 l

P3 _l pF0

Pr'l

PF2

+5

mode

prtorlttes

p0

oodes, the

pl

or p3

col,pFt, rQaii'ili!

or misslle

by

lf

if they

player's

the

Objects wtth

(nore

are ln confltct)

rhey are

are over

lunlnance of

overlaps

than 1

over

?F2 or

or

color.

a

che

the

OS

SHADOITI:

CoLPFO - C01PF3

addtesses

D6

(see

OS SHADOWS:

GPRIOR

$.rlte

ID5 ID

CoLBK for

data to

COLORO

(26I)

(Plavfield

the Playfield

2tDltD0

blt asslgnnent)

-

(2C4-2C7)

3

Color)(D016.

Color-t-ur0 Reglsters,

pol7.

D018. D0t9):

These

III.8

Co],BK

Background

Co

D7

(Backeround

Color-Lum Reglster.

D5 D4D6

Color)(D01A):

D3

This address

Not

DID2

Used

wrltes data ro

rhe

-

X

x x x

0000 0001 00r0 0011 0100

0I01 0110

0r1t

1000

I00l

10r0

l0r1

1100

ll01 I1l0

llll

OS SHADOI.I:

CoLORa

0 0

Grey Gold

Red-Orange Purple

Purple-Blue

Blue Bfue

1-igh!-Blue

quo

Tu r Green-Blue

Ye11ow-creen Orange-Green Llght-Orange

(2C8)

0 0

ETC.

I

ise

0

Zero Lunlnance

(black)

I

Max. Luninance

(white)

.-

E. PLAYERS

DMACTL, CoLPMo

addresses

the salle color-lun (see

bit 4 of PRIoR).

D

(see

OS SHADoWS: PCoLRo

GRAFPO P3 D0l0): Reglsters, independent I{iU be loaded page

II.3).

AND MISSII,ES

GRACTL, PMBASE and PRIOR

-

COLPM3

rr.rlte to

CoLBK for bit assignnents)

-

CMFP3

These

the as thelr

-

addresses

autonatlcally fron

D7 D6 D

Lefl

Playe!

on TV Screen

(Plaver-Missile

Player-Mlssile

5th player

A

D3

(Plaver

D2 D1 DO

(2C0-2C3)

3

of DMA.

player

craphlcs

r".rlte

unless

missile

dara dlrectly into

DMA

If

the

D3 D2 DI DO

R lgh

also affecr

Color)(D012, D013,

Color-Lun

rnissiles

gets

Reslsters):

enabled

ls

nenory area specified

r

players

Registers. Missiles have

are used as a 5th player

irs color frorn CoLPI3.

(PO

rhe

then the

nissl1es,

and

p014, p0l5):

D00p, ?1

player

graptllcs

p00E,

craphtcs

by PMBASE(see

These

p2

reglsters

p00I,

r11.9

GRAFM

dllectly lllto the Mlsslle Graphlcs Reglster, lndependent of Dl,tA.

(Mlsslle

Graphlcs Reqlsters)O01I): Thls address

r^'rltes

data

I

D7 ID6

LRLR]-R]-R

M3 M2 Ml l{0

SIZEP0 - SIZEP3

These addresses write data lnto the ?laver

I

D5 ID4 D2D3

(Plaver

stze)(?0 D008. ?1 D009, P2 D00A, ?3 D00B):

I

D1 IDO

Notll

used lDrlD0

0 0 Nornal stze

1 Twtce Noroal Size

I 1

Wlth nornal size to one color c1ock. one color clock.

0

I 0 Nornal slze

objecls,

laxger objects, each bit ts extended over nore than

Ior

each blt in the

Stze Control

liorlzontal Slze Register

(8

color clocks vide)

(16

color clocks h{de)

Tines Nornal size

4

(32

color cLocks wide)

graphlcs

Reeisters.

(Player)

register corresponds

SIZEM

Slze Control Register.

\__\r.--l

M3 M2 Ml MO

ttPOS?0 - H?0SP3

?3 D003)r These

Reglster deternlnes the color clock locatton of the left edge of the object. Hex 30

is the lefl standard

(Mlsslle

D6D7 D5 D4 D3 D2 D1 DO

(see

display

edge of a standerd wldth screen. Ilex D0 ls the rlght

screen.

Slze)(D00c): Thls address

0 0 Normal Slze 0

I I 4 Tlnes NorEal Slze

(Player

addresses wrlte data lnto the Player Horlzontal Posltlon

dlagran ln sectlon IV). fhe

Eorlzontal

I Twice Nornal

Posltlon)(P0 D000. ?1 D001. P2 D002,

I'rltes

Eorizontal Register

(2

color clocks \r'Ide)

(4

color clocks dde)

(8

color clocks \rrde)

data into the

Slze

(Misstle)

horizontal

Slze

ll1sslle

positon

edge of a

value

I

D6

7 DOD

D5 D4 D2 D1

III,IO

., _

u-

swwer

Positlon

D7

I D

uj

uuu/r;

Reglsrers

D5 ID

Inese

(see

D3

addresses

ItpOSpO

lD2 lDl

rN.rlte

descrlDtion).

data

into

the

t, ur

Misslle

ouo:.

itorlzontal

mpL4Y

-- .

vertlcal

I!|it------_l

p7

tp6

P3

VDELAY

-

sltlonlng Settlng TV flne.

If player-nlsslle of ar 1n the set.up

reglsters

h^^,

,vuz.

A I blt

oblect

MgtE!-YIPL-l-\a2PFr.l,13PP

uuurr:

Not

-(yc4LE-!-Uq!4dQ9.!O: rhls

Delay

P2

of an

s

blt tn

nenory by

assenbly at the

neans

used

o

forced)

Reglsrer.

lp5

?l ls used

by

nap.

Inese

that a

lp4

PO

to

object

VDELAy

nore

If Dl,tA

language

deslred

addresses

| J

lp3 | D2

M3

thar

colllslon

p3

M2

glve

when

Dl4A

one-Ilne lhe 2-1ine

to I noves

is enabled

one

line

is

dlsabled

code

line,

(Missl]e.ro ptavftetd

read

|

L

D2

| |

lDrlDO

l,1l

has

MO

resolutton

the

then

1s acconpllsied

whlch

stores

l,tisstte

been

I

Dt

DO

I

a.lclress t'rites

1n resolutlon corresponcltng

chang{ng

rhen

rhe

to

detected

dtsplay

vertical

data

colrisrons)(pOoO,

playfietd

since

dara irto

rhe

vertlcal

ts

otllct

the vertlcai

by ,."i"g

loiatlon

tnto ttre grafhics

Cotlisions.

the

last

po_

enabled.

aown

ty one

tocation

tii"

HITCLR.

the

._""a can

pOOr,

Ue

p005.

POPF.

Not

D00A.

Not

POPI.

D00F):

Not

p006.

used

zero

p00B):

Used

These

osed

rorced)

PlPF.

P2P

p007):

torced)

MIPI,.

PI

M2P1,.

These

P'IPL.

addresses

(Player

3PF

These

| |

addresses

I

p3

M3PL

D

P

read

I

addtesses

|

I

|

D2

J

read

2

Playe

Dt I DO

sl1e

D1

I

Mlsslle

r

lD3 lD2 lDI lD

I

to P1

Player

to

0

to Plaver

to

Player

0

Playfleld

efd

to

Playfteld

r Cofl

lo Player

Player

ollislons

Colllsions

Player

Type

Colltslons)

Playfield

Type

(D008

on)

Coltislons.

ltunber

Nunber

(D00

Collisions.

00c DOOD

(Player

0

against

player

O

ts

always

III.lI

a zero).

Erc.

IM!B-

(co1llslon

"HlT"

clesr)

DO IE

Ttls wrlte

AUDIO

I.

AUDCTL

(Audio

r'roa! C"trt.of

D6 D5 D2 DI DO

7

D1 D6 D5 D4 D3 D2

Change clock chan$el 1 r'tth 1.79 MHZ, clock Channel 3 Clock Channel

clock Chamel 4 Inser! Ill

(See

sectlon D] DO

Insext Chaflge

address

Not

Control)

r"gr"t.t.

D D

17 btt

Pass lllter in

11. l{i Pass llLter 1n Chan$el Normal 64 ICIZ frequeocy,

clears all colllslon

(D208):

{Ll*-"i"

poly

inlo a 9 blt below

with 1.79

2 with Channel 1, lnstead

nilh channeL

)

Thls address SKCTL

lnstead

}l1lz,

Channel

instead

3,

btts descrlbed

wrltes

tro-tone

poly'

of 64 relz. of 64 Klz.

of 64 ].JlZ

lnstead

I, clocked

2, clocked by Channel 4.

tnto 15 KlZ.

of 64 xllz

data lnto the

blt

3

(f6 (16

by chanflel 3.

Audlo

BlT). BIT)'

Ee9!-lEgSg!g1es:

Elact Frequency

(NTSC

orly,

FIN

t.79

64

(f1[)

?AL differert).

MItZ

KtZ

15

The Nornal

where N = The The MODIFIED FORMUI.A should

ls desired:

Tornula for output frequency

Iour

=

blnary nudber

Tne frequencles

that

t.789'19

63,

15.6999

Fin/2N

(AIIDF

2

glven

clocks the dlvtde by N counters

FIN

above are apProxinate.

modifled forldrla

Use

9210

-

Use norDal forlerla

is:

1r) be

+

the

ssed

M)

frequency

when I1rI

reglster =

r.t9 ttltL and a rlore

(AUDF),

ls

glve[

for fout

plus

I

The

below

(N=AUDF+1).

lihere:

M M

8 b1t

16 b1t

counter

counlex

(AUDCTI-

(AIJDCTL

rll.12

3or4=0)

blt

3or4=l)

AUpII. AUpr2.

These addresses

Reglsters.

Each reglster controls a dlvtde

AUpF3. AUpr4

(Audlo

lrrlte data lnlo each

p202.

t204. D206)

"N"

(p200.

counter.

Freouencv)

of lhe four Audlo Freqrency

by

Control

00000000 00000001

AUDCl. AUDC2, AUDC3. D205. D207): These Reglsters.

correspondlng

olse Cofltent

HEX

0

2

Each Reglster

Audio channel.

or Dlstorlion volune

D7 D6 D4D5 DID2

0 0

AUDC4

addresses wrlte data

controls lhe no13e

00

l0

(Audlo

Channel

into each of

Co$tro1)(D201.

content and

DO

"Nt'

Note:

than the 1n Ardlo Irequency

Reglster AUDF(x).

the four Ardlo

volurne of the

Dlvlsor by audlo

!egister.

-

17 BIT

poly

-5BITpoly-N-2

ls one

blnary nunber

D203.

"N"

set

frequency poly - 5 BIT

-

N

gleater

Control'

-

0

6

0

I

c

I

0

8

F

x

I

00

I

0

I

X

I

X

I

10 00

10

00

0000

1000 tlll

4 BIT

poly

-5BITpoly-N-2

-

17 BIT

-PureIone-N-r

-4BtTpoly-N

-

Force Output

(Volune

-

I-olrest

-

Ealf Volume

-

Eighest

poly ' 5 BIT

-

N

poly - N

onlY)

voluroe

Volune

(off)

Itr. l3

ItrGtt NOTES

I1IDDLE

L0w

NOTES

PITCIT VALUBS T'OR TIIE I.IUSICAL NoTXS-AUDCTL

t{ex

c

B Atl or Bb

e# or Ab

G l#

or Gb ! E

D# or Eb D

o! Db

C#

c

B

or Bb

AtA G# or Ab

G F# or cb

F E D/l or Eb D

C# or Db

C

c

B

A# or Bb

C# or Ab G

or

F# I

E D# or Eb D

c# or Db

Gb

c

=0.

AUDC = hex AX

ID 2l

23 25 28

2D 2l 32 35 39 3C 4A

48 4C 5I 55 5B 60 66 6c

72 79 80 88 90 99

A)D

CI

cc

D9

E6

AI'DF

Dec

29 3l 33 35

40 42 45 41 50

57

60 64 68 72 76 81 85 9I

96 102 108 II4 t2\ r28

I36

r44

153

r62 r73

182 193 204 2t7 230 243

STIUER frequency divtders internrpts $hen lRQST)

R-ANDOM order 8 blts of a 17

D7

D6 D5 D4

(Start

(Randon

Tirne!)(D209): This ts'rite address resets all audto

!q thelr

lhey coun! dolr'n to zero

Nunber

bit Dolvnonial counter

I'AUDF||

Generator)

2D

value. These dtviders

III.I4

(if

(D20A):

generate

enabled by

This eddress reads

(9

bit, 1f blt

IRQTN).

7 of AlrDcTL=t).

tlrtrer

(also

the

see

hlgh

G. KEYAOARD AND

SPEAKNR

CoNSoL fro.0 code.

the console )

Not used

ero forced)

Eex

08 should

Ones !.ritten

CONSOI, Btt

DI Caroe D3 Loudspeake!

KBCODE

and ls of IRQST).

SKCTL bits I

usually tead

(Console

Sr,'itch Port)(D0lF)r

snltches and

I I

D3 | D2

|

be wtlrten

w111 pul1

Assignnent:

Selecr

upElon

(Kevboard

See TRQEN

and 0 for key

serecE

Code)(D209):

1n response to

for lnfornarlon

Thls address

lndlcarors.

(Set

I I

DI I D0

|

to this address

down

scan and debounce

on the sl'itch

I

-

\

I

.,,,

0 neans

-

should except when noEenlarlly.

I durtng verttc

This address

a Keyboard

on enabling

snitch

be held

reads

to 8 by

before readlng

pressed,

at I

r.rltlng 0

OS nrlles

al blank.

reads the Keyboard

Interrupt

keyboard inrerruprs.

enable.

OS Vertlcal

llne.

(IRQ

or \,Iriles

the slrltches.

a

and blts

itata

Blank

Code,

6 or 7

See

-

D7 D6

Read by

functton

D4

D7 = Control D6 - Shifr

0S lnto shadoo

whtch converts

Key

D3 D2 DI

Key

CH trhen

the keycode

key ls hlt. to ATASCII

The OS has a

(Ararl

ASCII).

get

character

III.15

KEYCODE TO ATASCII

CON\,"ERSION

KNY CODE

00 OI 02

03 04 05 06

o7

08 09 OA OB

0c

OD OE OF

10

tl

I2

I3

t4

15

16

I7

l8

I9

1A

IB

lc

ID

IE

IF

KEY CAP

L J

;.

K

+

0

P U

RET

:

c

B

x

Z

3 6

ESC

5 2 I

L. C. u,c.

6C 3B

6B 2R

6F

70

75 98 69

4C 3A

4B 5C

50 55 9R

49 2D 3D

76

7C

56 63

62 18

34 33

36

42

58

24

23

26

IB 35 32 3I

25

22

2l

CTRL

0c

OA 7B

03 ]E

OI

r0

15 9B 09 lc 1D l6

03

02

l8 1A

IB

FD

KEY KEY

CA?

20 2\

SPACE

2Z 23

N

24 25

M

26 27 28

,|\

R

29 2L 2R 2C 2D 2E

E Y

TAB

T

w

a

30 3I 32 33 34 35 36 37 38 39 3A 3B 3C 3D

3F

9 0

BAC(S

8

T H D

CAPS

G

s

I-.C.

2C 20 2R 6E

6D

u.c. TRL

5B 20 5D 4E

4D

00 20 60 OE

OD

3I

12

52

T2

05

79 74

77 7l 39

30

7

37 7E 38

3C 3E 66 68 64

67 73

59 9I 54

5I 28

29 27 9C 40 7D 9D 46 48

4'l

53

4l

I9

9E

l4 I7

ll

FE 7D

FT 06 08 04

07

I3

01

*

=

speclal

handling

III.I6

H. SERIAL

PORT

(see perlpheral

conoeclor

on consofe)

sKcTI-

(Serial

Port control)(D20F):

reglsler that controls the conflguatlon

Fast

Pot scan and Keyboald Enable.

D6 D5 D4 D3 D2

D7 Force Break

(force

serial output to zero

DI

D6) D5 ) sertal Port Mode Control

D4) set]-a! D3 Tno

port

Tone

description,

(Serial

output transnltted as

(see

paee

loetc true/false.)

DZ Iast Po!

(Fast

Scar. The ?ot Scan Coonler

?ol seqrence tn tlro TV 1lne tlEes capacltor

DI Eoable Key Scan D0 Enable Debounce

dunp transislors are completely

(Enables (Enables

Keyboard Scanrlng Keyboard Debounce circrils)

This address vrltes data

of

the

(Bits

and

serial

port'

nordally zero

are

perforn

and also the

the functlons

sholrn belolr lrhen true.

(space))*

mode chalt at

end of

I1.34).

two tone slgnal lnsEead

coBPletes its

instead of one ftane

tlne. The

disabled.)

circuit)

lnlo lhe

)

of

D0-Dl

OS SHADOW: SSKCTI-

The oS enables

dlfferent I/O

(Borh chiP)

Zero) Inltialize *rt

(hex

key scan and debounce

operattons. In

leave the two tone b1t

Thts i0ay be corrected by

I/0 and/or

*

NOTE:

before nodlfylng the audlo

n'hen

powered ls cleared. To 00 or FF).

232)

particular, an aborled cassette operatlofl

1n ihe

true

\{rltlng

on, serial

get

S.?. hlgh

(State

used for lestlng and

and may change the

state, causlng undesirable

13 lo both SKCTL and

hex

reglslers.

port output nay

(nark)'

stay low even if this blt

a byte out

send

inltializing

other blts for

nay

audto signals.

SSKCTL after dotng

(reconnend

**NOTE:

Thele 1s no

original

polrer

III.I7

on state.

Pokey has no reset

pln.

status

SKSTAT

reglster

(Serial

glving

Port-Keyboard

inforBation

Slarus)(D20I):

about

the sellal

This address

Dor!

and

kevboard.

reads rhe

D7

bits

D5 D7= D6 D5 D4 D3 D2 DI DO

SKRES

0 = Serlal 0 = Serlal 0 = Keyboard 0 - Direct 0 = Shtft 0 = Last 0 = Sertal

I Not

(Reset

7, 6, and

D4 D

Data Input Data

from

Key Depressed

Key is

Input

Used

above

5 of the

Frane Error

hput Over-nrn

Over-run

Serlal Input

Stlll Depressed

Shlft Register

(Log1c

Status Reqister) Serlal

Tnre)

por!-Keyboard

port

Busy

(D20A):

(Blts

and lnformatior

Stalus Register

are nornally

provlde

(

SKRES

(D5

zero and

This wrile

the following

vhen zero.)

)

and

D6 are se!

when new data

sane blt of IRQST

true

to

address resets

to 1.

SERIN

holdlng

beeo

recelved.

inlerrup!

D7 D

Serial

l.

3.

5.

7.

9.

11.

(Sertal

register

(IRQ

lrlo Porr

Clock In Data Data Comand

Ardio

Input Dara)(D20D):

that

ls loaded

Thls

and

address ls

bit 5 of IRQST).

D4 D

Connector

6 8

In

to computer

Out of

In

Coopurer

Thls address I,hen a fult usually

Also

plnout;

10 t2

2.

10. +5

12. +t2

reads rhe

byte of

read in response

see IRQEN.

Clock Out

GND CND Moror Control

Ready

/

serlal input

8 bit

dara has

to a serial

parallel

data ln

See

serlal port

descrtprion

tn

0S

Eanual

III.

t8

for Eore deta1ls.

SERoUT

parallel

reglsier when a fu11 address ts usually \rritlen in response to a and btt 4 of IROST).

(Se!la1

holdlng reglsler

output

byte of serlal ortpul data

Data)(D2oD): This address rffites

tha! ls transferred to Ehe output

to the 8

serlal

has

been transmitted. This

serial data out inlerrupt

blt

shlft

(IRQ

D7 D6 D4

I. CONTRoI-LER

PoRTA

Player I cortroller

and wrltes to the dlrectlon both

Dara Reslster-Addressed

ports

Rlght

Left

(Jack

PORTS

(Port

(A

Back

A)(D300): Thls address

B)

and

stlck 0Deration

. l-eft ftrd.

2) Paddle

goes

Rlght Back

D

(front

jacks

of console)

if blt

conlrol register

through a 6520/6820

lf blt 2 of PACTL is l.

2 of PACTL is true.

srick0

(Jack

r)

reads or lrrltes lf bit 2 of PACTL ls

0=Swilch

l=Switch not

o=Str'itch

l=Sirltch

data from Player 0

Thls address

pressed

not

zeto.

I/o

for

board controller 0

Dlrectlon Control

Re

Each blt corresponds to

0-tnput

l=output

os ssADowS:

STICKo

(hex

Top

2nd 3rd 4rh

Row

Rol'

Row Ro\t

-Ad

jack

a

278),

.\

,

)

ptn

STICKI

ToP

2nd 3rd 4rd

Jack

2

if blt 2 of

(279),

III. 19

Rol.'

)

Row

\

Row

r

PBCTL ts 0

PTRIGO-3

Jack I

(27c-27I

PACTL

Port A Control Reglsler.

the

(Port

D6 D4 D3

A ControL)

x

X

(D302)

D2 DI

x

This addless \"'rites or

|

Port A Conrrol

Reglster

Set up register

-

(x

descrlbed

reads data froro

as

shown

below)

(Read

bus Proceed line.

Set by Pertpheral

D3 - Peripheral Moto! Control line

(0=0n

D2 - Controls

{I = Port A

D0 - Perlpheral A Interrupt Enable

Reset by

PORTB

Player 3 controller

and

lrrltes

borh Data Resiste!-Addressed

Right Back

to the dilectlon control register

ports

ggLI) Peripheral A Interrupt

-off)

I

Porl A addressing described

poi.'er

(Port

(A

B)(D301): This address

and B)

soes

Rtght

(Reset

A lncermpt.)

Reglsrer

turn-on ox

jacks

if bil 2 of PBCTI-

tf bil 2 of

throush a

by

=

Directlon Control Register).

0

processor.

5520/6820.

Back

Status Bit. Serial

readtng Port A Register.

on serlal bus

above

Blt.

reads or wriles

lf bll 2 of PBCTL

(wrlte)

Se!

PBCTL

ls I

ls true.

0=Swltch l=Switch not

(trite).

(wrlte).

I = Enable.

by Processor.

data fron Player 2

Thls address

ts zero. I/O for

pressed

(Jack

PTRIG6 ?TRIG7

board

4)

C tr

Top

znd 3rd 4th

srick2

(Jack

Ro\,r)

Ror' Rol.'

3)

PTRIG4

PTRlG5

\ f

Jack 4

Top

2nd 3rd 4rd

o=Swltch

1=Swltch

row

)

Rov

\

Ror'

I

pressed

not

Jack 3

r1r.20

Dlrectlon Contlo1 Reeister-Addressed if blt 2

m

lp7 lp6 lp5 lp4 lp3 lp2

lp1 lp0 I

of PBCTL is 0

tach blt corresponds

0-tnput

os SI1ADoI\IS:

PBCTI

the Port B Control Register.

D7

D3 D2

DO

STICK2

(Port

(Read

bus

Set Peripheral Command L1ne.

Controls ?or! B addresslng descrlbed

(l= Perlphetal Reset by

(Set

94I)

Interrupl line. Re8et by

by

Port B Regisrer 0 = Dlrection

to he). 3c br os IRQ code)

to a

(hex

27A), sTIcK3

B Control)

Peripheral B

Perlpheral

B lnterrupt Enable

power

turn-on

Jack

(278),

(D303):

B Inrernrpt.

Identlflcation. Serial bus CoEnand

This address

Interrupt Srarus Blt. Serlal

or processor.

PTRIG4-7

\rrltes ol reads data fron

Port B Conlrol

Reglster Sel up .egister as sholrn

bero!')

Readlng Port

above.

Control Register)

Bit. I = Enable.

Set by

(280-283)

(X=Described

B Reglster.

processor.

POT0 - P0T7

to 228) ot 8 pots

paddle

The console pot values.

"POTGO"

controllers

keyboard. Turning the

The values

connaod

(Pol

(paddLe

described beloi.' or after AJ-LPOT

D7 D6 D5 D

Each

0S SHADOWS: ?ADDLO

Va1ues)

are nuobered from left are

?or Value

-

(}],ex

7

(D200-D207):

controllers) connected to the 8

paddle

valld

only after 228 TV lines follor1ng

(0-228)

270-211)

III.2I

These addresses

right nhen

to

knob clockirise results in decreasing

chanees.

read the value

lines

por port.

facing the

the

(0

ALIPOT

present

(A11

Pot Lines Siw-rltaneouslv)

state of the 81ine

pot port!

(D208):

This address reads

the

Capacitor dunp transitors

pot

scan node

Pot runber: 0 - Pot register value

7 6 5 4 3 2 I 0 I = Pot register value

(blt

8 ?ot

2 of SKCTL) or starting

Lilre States

ftrst

ryL9gl!le:t-.3.e1--gse4

No

Data Birs Used

Thls write address

(POT0

the

-

POTT) should be read first. Thls sr1!e strobe ls

follo!,rlng

l. Scan Counter cleared

2. Capacitor dullp translslors turned off.

3. Scan Counter beglns counring.

4. Counter value captured in each of 8 registers P0TT) as each

5.

Counler reaches 228, capacitor dunp transistors turned

sequellce,

atarts the

pot

line crosses trigger voltage.

be turned off

:

pot

zero.

to

by elthe!

pot

scan

scan sequence. The

(PoTCO).

golng

pot values

then used causlog

(POTO

to fast

-

val1d.

ls ls not valld,

(Wrillen

TRIGo, TRIcl, TRIG2, TRIG3 3 D013): These addresses read por! controller trlgger buttons.

to by OS ver!1cal

(Trisqex

Not Used

ed DO

OS SHADOWS: STRIGo-3

NOTE: 1TIIGO

Ilowever,

they of GRACTL

lhru

go

(hex

284-287)

TRIG3

lf bil 2 of GRACTI, ls I, rhese inputs are latched

loglc zero.

to

ls set to 0.

are nornally read dlrectly by rhe nlcroprocessor.

These latches are rese!

I

blank

Ports)(0

plns

nordally connected to the

code)

D0I0, I D0I1. 2 D012.

0 = burton

I = butto[ not pressed

pressed

(true)

loystick

wheoever

when bl! 2

trl.22

PENIT

reads

counter occurs $hen the

and PENV are nodllled

(Llqht

the llorlzontal l,lght

1n hardnare).

Pen Horlzontal

pel!

4lD

Color

Pen Register

The values range

lf near the right

when any of the

Clock

(based

fron 0 !o declnal 227. Wraparound

edge of a standard-!,/ldth screen.

loystick

trtl

Posltlon)

on

trlgger llnes ts

(D40C

horlzontal

the

: Thts

)

address

color clock

pENtt

pulled

loir.

t\7

0S SHADOW: LPENH

the Vertlcal Light

H6 tr5 E4

PENV

(L1eht

Pen Vertlcal

D7 D6 D5

LP875

OS

SltADoW: LPENV

Front PaneI

PrA

?olt

(6s2016820)

Out: TIL tevels,

Io

: ml levels, 1 load

A

Circuit

n3 H2 r{1 l{0

(hex

234)

?en Register

(hex

23s)

(Conlrolfer)

I load

(lyp1cal):

TV Llne Pos ltton)

(8

most slgnlflcant

resolutlon

Jacks as T/O Parrs:

(D40D

: Thls

)

bits, sane as VCOUNT).

address

supplied.

reads

Port B Circult

6520 220

"Trlgger"

PorL

(typical):

(B)

Circult

ot5

4.7K

(

Jack

.00r

typl cal ) :

Jack

arl.23

ge.!!!.9.1f

9r-39:!-3.99s!

:

I 2 3

5 6

7 8

Male

(console)

I 2

JOYSTICK I PADDI,E

Iorward Back Left Rlght

Trigger Button

GND

3

Controllers

A(Left)rrisser

B(Risht)Trtsser

PoT B

5

(POT)

(Rlght)

GND

lemale

(connector)

54321

8 1 6

KEYBOA.R,D

I

Top

2nd

3rd Rc,l.'*

|

Bottono

I

Row,t

1st Colunn

colunn

3rd

+5+5

HARDI{ARE os

VARIASLES

Blt 0 or 4** B1t I or 5**

Blt 2 0r 5*:t Blt 3 or 7**

POl r,3,5,7

TR1G0,1,2,3

Btt

Blt 1:t,t*

PTRIGO, 2,4,6

Blr 2***

?TRTGI,3,5,7

Blt 3*** PADDLl,3,5,7

sTRrGo, 1,2,3

0***

9

*

Wrlte

**

?oRTA or PORTB

***

STICK 0,

1, 2 or 3

PoTA

(Left)

2nd coluBn

PoT

0,2,4,6

PA.DDLO,2,4,6

lat.24

IV.

SATPLE PROGRA}{

This asaeobly

and

dlsplay looks describe

1lke and whlch

1ists.

how lt

language progran

I'he dlagran on

oblects

works.

lllustrates

the next

are used.

the use of

page

shows shat

The conBents

in the

players,

lhe display

progran

Flsstles, listtng

rv.1

sl

d ,r.

al

n

------'

3l?

I

I I

I

E

qE

;l

i>:

IV.2

i2

.-

.-.

r-!r

: .?9 :q]

::3

-J

-

I$:

.

{ro

, rig

i :;i

'

::F :'r:4

'

i; _),,

:

:rn:--Et ;d'C'g'H

'rd

\.-

:s'

_:r

":-=

-:*' {-*5

i..r

ai

.t

.>;

i-.s

odw c:;:db

P'zo':z :-t1P99

F:6rF;'

: i:: I $*3[:- $ c Ece:,;s;; )

s

-

;" h,"",9,E:

:

t

"-!ii:jj-i:!!

.:

f \a:5--E'l[3

:

-

L

!

*

;

;"-"""9-9S;n,r,'r

o.J,:-.ta::

{ liQE:+:l: ^i E-!ftft:qiEf:ii $ !3 "iy2z2E;1

! il;i 3 ItJl;

J,;*

",.-= );.F-:!:+

i:"H-::8 "ri0:?i:

:!:s-lEi

-LdIJ .

:iY:i"i;*:

:rji:

;, ; ;:iE!!i!!E$$i::f;

o

5

;

'

s3h333are;s3ts

E 3:333$333XS3:

a

-r-ooorrrdaF

r'E6tlUd6'&gFE

u d ri = o

d o ; E d -

if;

f; f;

djdj6iodi!birjoo

!

E

-

:

. : . :

t r

qE:$:$E$fr

E$*EH;8$E}3$g

:-E:i

de n

:?t;tl:;"",,.;

3+93!

o

; d. i

oob 6d6,nddd,no

:R:ggSP

i < 6 6 6 6 6 o, d

$EE"9:FCE:

EEEEEEgE$E$g$;

6

IV.3

a^a

i

d

"

6

H

5K

E H

a

H

o

a-

:E

"9

ic

9p

s;

e

-d , E

-

; i E EJ .F

E P

u n

; L L -

. b E b b b b

t

I E

9a

t

'

d

L i

g

E "------,-----:6;6

IEgEEfi

;

- L r E

E rraitrrrrrr?zr-z

d

:

.

',

EEEEEEEEEIEEEE$$EEBR8;ggEgB$EEEE

- L L L L L E

3 B E 6 b b b

-

'

g

:

s *

E $ E$B*H$$EHEH*$EH3$

L L

b 6

6 6

'

' a j

s

r

',,""

$

" Y ! cr!

E

d>

''ii

d

r ic

-

v.

d 3

P

5 [

r "',,

il

x

S >y f

a

H

...Y.fididE.didi

: ;F

3 icU

g.

e

a q

:d

ci

gc

o."""

fEEER

B$H$H

ciHb

Cd3,4

5Q**

:::;i

o*U; ccco

F$H$

9Fq

"5ti.

,'"'

"

4EEr

EgEH

U

I

So

t

9t

dd

;

IV.5

f

dn=e

j-!n'-:

.3:

6

3+1 * 4 S:

{;qt3'ii

= V"d

;to

" ,2 d

-eut>

n o6$66o6

H 9: ::::

d

!l !

: i

d 3 """""

ui !i

g

:

b

d

:

E F ; 3 t S t d S 3 S f f

3 3 S S ,' S I S f 3 f f H 3 3 S 3 S

S 3 $ S 3 : f P fr S i S

IVi6

6

J

+-

&6

, a ao.

t

g

9":

t

+e P

-FE

iH5 SC trC

.r+

: i_:

-.rEq c

i

\E

FliJ

g

IV.7

i

n

6

;

i

6

fr

5

o

EA FCEEEi9

€

:

E

K

E

333.S

rv.8

p

6;g

3

[3hi=ts$Ets3

i;

SSRS$E$RA339

$e3s33E$3S$

g*sssssP

IV.9

5

zft

qq 6E

q

I

. .ii o Et

o rru66 og

d

vt

I 3"

6

9 -o 9r P

u

E

r!!

s*aer

!P

"

i6

t>L

EE

s

.'o

5

ts

q!

ii-

e$a*

BS3$ Pg

gfrsfr=:irilEd

r

E:EEE$rHH

3

5

.E

d d

3

fi fi R$fi $HHRHB$$B$$Bgi$939s$H$f

fi fi

P EgCS I

Lo

rU 6$i'i

$F EH HH!lHeesesJH

FF- PP PPPPKRTRRK,: ISXRRRR^"E

;i 6i6 i,nihniDhi

6rr.

s*$es$eE:

Na vouei'ltF\

i^i

d

*

" i

e

: : S

c x

fi fr fi

3

.i.

IV. l0

I

o

g

di

nJ

q

rv.11

HARDWARE REGISTER I,ISTS

ANDRESS ORDER

Address

D

OTF

CTIA ADDRESSES

READ

Descrt

t

I

i

D020

01r

DO lE

DO]D

9t3

0lA

D01

DO

I6

D0l5

D0t4

D0l

D0l2

D011 DOOT

DOOD

DOOB

D009 D008 D00 D006

D004 D002 D000

REPEAT AS BEI,OW

Wrlte Co

on

Vert. ?riori

Color-1um of 3

laver-Ulss1le

GraDhlcs A1l

GraDhlcs Plaver I

Slze A11 lttsstle

Slze Plaver 2

llorz. Poslt. Mlsslle Itorz. P

Ilorz. Itorz. P 1{orz.

orz. Poslt.

De

aDhlcs

Plaver I

rz, Posl!.

Poslr, l41sslle 0 Poslt. Plaver 2

Clear

sile 2

I

Plaver 3

Mlsslle 2

?laver 0

7 MORE

TIMES

Consol SW. Port

RXAN PAJ-/NTSCblts Read Joystlck Trlgge!

Buttons

Read PLayer

to Player ColllsLoDs

Read Mlsslle

To ?Iayer colllslons

Read To Playfield

Read Mlsstle To Playfteld

P]ayer

Colllslons

CollisloIrs

V.I

Address D4FF

ANTIC ADDRES

t

D4OT

D4OE D4OD D40C D4OB

D4OA

D409 D408

D40 7 D406

REPEAT

(AS

BELOW)

Reset NUI

Interrupt Status

Walt Character Base

Address

Player-Mlssile

Address Re

Ve!tlca1

for IIBLANK

Red

Scroll

Base

15

MORE TIMES

NMI Interrupt

Status Reglster

Llght Pen Reglster

VertlcaL Llght Pen Reglsrer Horlzontal Vertical Llne Counter

D402 D401 D400

D1-1ST11

Horizontal Dtsplay

olnrer

Display Character DMA

List

(H

Llst

Control

Scro11

Control

!.2

DzFI

POKEY A.DDRESSES

DescrlDtlon

READ

Descri

t

I

i

D2l0

D206 D205

D20 D202

REPEAT

(AS

BE].OW)

Serlal control IRQ lnterrupt lnable Serlal

Start Pot Scan

Reset

Sralt Tlmers

Audlo Channel Audlo Channel 4

Audio channel 4 Audio Audlo

control Andlo chanRel 2

Audto Channel

Port 4 Key

Port

Status

dio control

channel 3

channel

15

MORE

4

TIMES

Serlal Port 4

IRQ lnterrupt

s Reeister

Ser{al

Rendon Numb

Read

Porl

Resister

1ca1 ]-lne

oard code

Read

value each POT

the

of

Key

Ardlo channel I

v.3

ANDRESSES

READ

Add!ess

D3TF

D301

D300

*

Repeat

NoTE:

as shown

Directlon If

PBCTI, Bit

Jack2&Jack3 If

Dlrectlon

Dlrec!1oo If

PACTL

Jack0&Jackl If Dlrectlon

Ortpur data If dlrectlon !dlI

read

old dara

DescrlDtion

below rnany

Reglster

2-0

Blts

Register

tlt 2=0

Bits

is

retained

blts

are

from

tlnes

1n Jack

true,

these

Output

a read of

reslsters.

Same Jack2&Jack3

If Dlrectlon

Same

JACKUdJ

If

Registers.

the

iacks

as wrlce

e0

*

as wrlte

Dlrectlor

Bits

CKI

Bits

AIPHABETICAL ORIER

AI,LPOT AttDc

I

AUDC

2

ATIDC

3

AUDCTL AI'DF I AIJDF 2 AIDT3

CHACTL

CITBASE C01,BK COLPFO

COL?F2

coI-PF3 COLPMO COI,PMI

COLPlI3

coNsoL

DLISTII D],ISTL

TL

ERACTL

GRAI'M GRAI?O GRAFP 1

GRATP3 I{1TC]-R ITPOSMO ITPOSMl

IIPO SM3 HPOSPO HPOSPI

HPOSP2

HSCROT

IRQEN

IRqST

KBCODE

Itard

Read 81ine Audto Audlo Audlo Channel

Audlo Audio Audlo A[dto Audto

Character control Character base addless Color-l-umlnance of Background Color Luninance of Playfteld

Color Lunlnance of Playfield Color Lunlnance

Color Luninance of Player-l4isst1e

olor Luolnance Color Lunlnance of Player-Mlsslle Console Sldtch Port

Display Ltst Potnter Display list Potnter

DIrect Menorv Access Graphics for

Graphlcs for Player 0 Graphica GraDhlcB Graphics Collsslon Clear

l{orizontal llorlzontal

Hor{zontal Postlton of Mlsslle

Horlzontal ?ostrlon of Playet

norlzontal lorlzortal

rnEerrupE Keqresr

Keyboard

Channel I

Chafirel 2

o

Channel Control Channel 1 Channel 2 f'requency Channel 3 lrequency Channel 4 lreouenc

rizontal PoslEion of

lot Port

Colltrol CoDtrol

3 Control

Frequency

of P1a;er-l.tlss1le of Plaver-Misslle 2

all lllsslles

for Player I for Plaver 2 for Player 3

Posltlon of Mtssile 0 Posltlon of Missile 1

Posltlon

Posltlotr

Code

lster

State

(hlgh (1ow

byte)

(DMA)

Mlsslle 2

of Player I of Player 2 of Plaver

(1Kq)

EnaDre

0 2

byte) Control

Address Add!ess

Hex

Dec

53768 5376r 53763 53765 5316'l

53 768

53760 53762

2F3 2F4 2C8 2C4 2C5

'155 156

7t2 708 709 7t0 711 704 705

O

54273

54281

53274

53210

53272 53273

53266

I

53267

coLoR2 col-oR3

PCOLRO PCOLRI

70 D0l5 D OIF D403 D 402

D O1D D 01I. DOOD DOOE

53269

53279 5427 4 53271

53265

5326r 53262

PCOlR3

Set

to S'LSTE SDLSTL

TL

2C3

| 707

8

du r lng

23I | 56I

230

ts60

22F | 559

VBLANK

DOOF D0l0 DO lE

r004

53264 5327I 53252 s3253

3

0

D007 D000 D001 D002 D003

D404 D2OE D2OE D209

53255 53248 53249 53250 53251 54276 53714 53714 53769

764

MOPL MIPF MIPL M2?I IT2PL

Mlsslle 0 !o Player col1l6tons l,ltsst1e 1 Mlsslle I to Player colllslons Ulsslle 2 to Playfleld colllslons

Playfteld

to

Colltslons

53256 53249 53257 53250

llardnare ister

Address

0S Shadow

Address

},13PF M3PL NMIEN NMIRES NMIST ?OPF

POPL PIPF PIPL P2PF PzIL P3PF P3PL PACTL PA]PBCTL PENH PENV P}EASE ?ORTA PORTB POTO

POTl POT2 POT3 POT4 POT5 POT6 POTT POTGO PRIOR RANDOM

SERIN SEROUT

SIZE?O SIZEP 1 S'ZEP2 SIZEP3 SKCTI SXREST SKSTAT STlMER IRIGO

TRIG2 TRIG3T VCOIJNT VDELAY VSCROL WSYNC Wait

Misstle 3 ro Playfleld co1l1slons }llss11e Non-Maskable Interrupt NMl reset NMl Stahrs

Player 0 to Player Player l to Playfteld Player I to

Player 2

Player 3 to ?layfleld colllsions

Player 3 to Player Colllslons

Port A Cotltlol PAr,/NTsc tndtctor

Port B Conlrol Llght Pen Ilorlzontal Ltght Pen Vertlcal Poslllon

Player Misslle Base Address

Port A

Pot 0

Pot I

PoL 2

Pot 4

Pot 7

Star!

Dr'l^il rw Cale.r

Raodon

Serial Port Input serlal Port stzes for all nisslles stze of Player size of slze ot Slze

Serlal Port Control

Reset Sertal

Serial Slart Tiner Joysrick cortroller Joastick Controller Trisser I Joysrtck Controller'Irigget Joystlck Conlroller

Vertical Llne Counler

Vertcal Delay

vertical scrolf

Player

3 to

Playfield

0 to ?layer

Player Player

to

(rlght

POT Scan Sequence

number

of Player 3

Port Status

for Horizontal Sync

paddle

generator

output

0 Player I Player 2

Port Status

Colllslons

Co1llslons

Collisions

Colllslons Colllslons

Posilion

controller)

Trigger 0

T!1gger 3

(NMI)

(SKSTAT)

Enabte

2

D003 DOOB D4OE D4OF D4OF

D004 D00c D005 DOOD

53251 53259 54246

5 4287

54287 53252 53260 53253 53261

D006

DOOE

D007 DOOF D302

D014

D303

D40C

D4OD

D40 7

53262 53255 53263 54018 53268 5 4019 54284 54285 54279

D300

D 301

D200

D2 01

54017

53760

53761

D202

53163 DZ04 D 205 DZO6 D20'I D2OB

DOIB D 2OA D2OE

D2 OD D00c D008 D 009 DOOA DOOB D2OF

D2OA

53764

53765

53766

537 67

53771

53275

53770

53774

53773

53260

53256

53257

53258

53259

53770

D2OF D209 D0t0 D01l

D012 DO I3 D4OB D0IC D405 D4OA 54282

53769

53264

53265

53266

53267

54283

5

4216

5 4217

set to wrltten read

set to set to

LPENII IPENV

sTlCK0 - l

sTrcK2,3

PADDI-O PADDL I ?ADD]-2 ?ADDI-3 PADDL4 PADD],5 PADD]-6 PAI}D].7 WRITTEN

GPRIOR

SSKCTL

STRIGO STRIGL STRIG2 STRIG3

Used by

cltck routtne

$40

to by

bv NIlI code

iC

$

iC by

$

234 235

27 8.IR279 27 !,,21R 270, 271 272 273

274 275 276

27'I

26r

232 562

284 285

286 247

keyboald

by IRQ code

NMI code

by IR Code

Code

564

634,635 624 625 626

624

629 630 631

ILANK

623

644

646

641

v.6

vI.

FIGURES

MEMORY

FFTF

MAP

RE

D800

DOOO-D7TF C}FF

BFFF

8000

7}FF

Operatlng

And

Math

Routlnes

Ilardware

Reserved O.S. exDanslon

Rol,l

Cartrldge

(Col1een

slot and slo!

all address

RAM

Systen

Addresses

for

left Candy

Future

and right

single

to

s

IOK

2K 4K

16K

2000

lFTF

RAM expansion will

unlts are

to 2FFF

deselect

RAM

(16K)

Expanslon

RAM tnltially supplled product

can

actually the RAM. Deselectton expandable

when fully

exten

onty

exrended.

1n rhe

to BFEF.

at the

occurs

factory.

However,

on 8K

boundartes.

They

8K

lhe

ROM

cartrldges

can accepr

Atari

RAlt

400

up

vI.l

id

r'r'OalltvN

3d

tNAsts

>JN\?'IEH

ld 3Cl7\

N,|S

^/€r*Jwtl

A

ON=

ON=+

I:j\/IS

i3

rO'an-,OS:o 3Nr-r Z

(!Nri

:3lNfral

aNnan€)>#

r..\"s)

o

JO

nu)

po

:v

uu

$(l

qd

fi'fl.

-o

id

?0

<q

-J i]

^u

dY

{6

u(l

7-

<o

Fla

z(\t

-.l.Nnot^

'tYf,.i.!:^

c^rncEg>tx

o

trj

(o

J<.

rr

nl

Ad

Qoo iUY

(qd

trud ,,,0q

606

;dU

ON

,.9

z

<F

F

>J

--__l-

l.

tu ib

t9o

U

6

---r-

I

l

(,

q<

-r

I

\_

-J

,<s

-

l-

(,

0,<

w=

:-

6N

trN

RV

d-.

rJ

3<

it.r O r-r

-J

/\\7-1dS1C

>N(9. rgir

.LejnE EcrcD €N=-

3Nr€H

cN,|gH I3S

]!VJs

t:93d

IfS3-

d*/ \.. -

ls>1L Lt t

L9:rHflHftl

h$

H>dAE

HY

CNncljgtx'r€

at:1Nno,

(3Ntr

t

d

l'z

r

ul

iii

ET LU

'i0S

rjt

U

Nv?9

LONneE9>r

lY

o

sd $b

0<

I

()

t")

F

z.

I

_,l-

f

=<

LUn

>rn

--J .\

A{

-l

t2

U;

$ trl F

=

(r!rtosl

(rrraos)

tt3)13o5)

<f

il*

E

{JJ

F =

::r.!.'?!r: i::r

; ::r::r::r:!r

r:ii:::i:.:3::r:E:!:::i.:

rr::.:.:

::::r*:llfEh!S:;f

f

!

t::iatr::r::?n;!3rtr!:

ia

(D

Ll.j

'r

+

F

.:-

Ei

3e

Ei

9E

;E.

5R

E:

*

:E

E

E:

t

lD@

I<

rl-oYr.!>

(Maos)

xaos)

u!

G.

>;

N r'l

s3

tno 0!0 rA

o<

=

3tvts-rt.L

o

(I

c0

CC lrl

= F

o

;-

iitt

r:r

E r!i:i9!

=1

PJ

3*,:r;i,

i-{H.:;F+#

"FF+r

fFr

tsrl

iiil::lr+i11

rii

't"lllt

1

I

:9ci'!,:r!6!:::!.:

rEi!!

:l:!:ir:::::1!?!r.',"i

:Illr:ic.;itr:?:r:

::::;ria::.::lrir::

i:,3;

i-rH

!,?

x:::r"r;q

:rtrt!:;1

-.

r1;::!

llt l

:! I

P;ii111::r:::::!

i.r! 3>1

>i ,!

.';a

;9

i ,t ;!;!!

! !

>3>;

!,r

;a:!

3.t:

B!!:

ON

AF

o*

E.

IJ

F

o

_8:-

3o-$nf

Ei

r

3E

!i

; E

a

E

!-*-e

Er

Et'

:;::

(L

o

Lrl =

(L

:6

!

-!

F

:r

i6

:;G

;F

o9

;

-;<

-

t!

=

iE

tp

\r

,g*ils:i**iE

a-

ao

lrJ

G

=<

OF

o-<

;5 s .!:

:t

i4

g;

--

9;E

<5

;

E

-

tf

IJ =

i

o

iii EE:

Eis

;;33

I

iie:iiiEl

E:3i

iEiE:

lr,J

gF

6J

<=

F

7

u)

).

E<

lrl

F

J

F

0uvo8

u3HLolt

oi-

""1=r"="'.""

"1"-"r"'=i

.

"-"'r"

"

l'-'

:;::E3EE

1

=rt_D

-

E

i

9

:.-:::

r€;;:

::--.

F

a?

:

2@ G<

LIJ F

o-<

3;:3133;::l

i

-i"r.i

i:;

3

.i

t=]

."i

U

B

;

il

{

f'.

:i

:t

t

!"'

'i

):

'

d

l-(,.!

o

Y

o

J

o

!t

F

c,uJ

Q

z

Q= Jgl

ut

thE

0uvoE

Y

I

t,

dF

Hi 1;

A

a)z zo

u3H10r{

F

-99

OJ.

F

:I

::

!l

:::::

n

s

Eii

li!

3

sB;;

E*:

"

6.

.3iii

e!

3:E

:r::e

i

E3E:83;

E

ecE! lE

s

iE

,.s

d

,a

!

:"EE

5

E

!H

;;

"

r5:::;

E :re

j

<t!

* ar.

o

z

F

z

F

z

F

>2

<o

-JE

83X31dtt1n,{30

>.:

ss3c00v

c,

Ltl

2

rrl

o

-J FtD

F

(r<

rgz

ot!

tt lrJ

F

E|rl <J

OUVOE

lr

u3H10t^t

0I

1

1n

:l

,,,T, - r tllE

ll:rr?!::l!

ll:::::::13

P:lr....Bl!

!ri !i:

!t

!;3!

I ?

:

-

!

:

i

!

!::::a

i::::::

it,3,i9

:<:

l-t;e@

o

:

z

.^ t-

F

>t <o

F

u!x31dlttnFt3o

ss3800v

>t

JE

|rl-

*k

0UVOg

U3H10r'l

OJ

o

trJ

lrl

F

lEt!

<J

lrl

O @lt

13::!.r::l:i

l!r:rr:::13

E:::Tr.:rli

p::,1r.:Bli

rf"

;:

lrr.rTr.rnli

ii i E;;

!i !t:

! ii s

s

e

I

!

:::::::.

!'!'EJ.r

tn

UJ

=

(9

a

t-

IY

OUVOS U3HION

F

OJ-

lrl

o

tr

F

ty.

o

=

LIJ T

U)

!::?:l::::?:

s

9i

..."...-,.;

lr

l3l3iE3338a;

:i!?I?lll?q-

Atari 400 Personal Computer, 800 Personal Computer System System Hardware Manual

Specifications and Main Features

Frequently Asked Questions

User Manual