Asus X441UBR Schematics

SYSTEM PAGE REF.

Content

PAGE

001_Block Diagram

002_System Setting

003_CPU_DISPLAY

004_CPU_DDR3

005_CPU_LPC,SPI,SMB,CLINK

006_CPU_POEWR

008_CPU_MISC,JTAG

009_CPU_CFG,RSVD

010_CPU_POWER_CAP

013_DDR3L_TERMINATION

014_DDR3L_ON-BOARD_A(1)

015_DDR3L_ON-BOARD_A(2)

016_DDR3L SO-DIMM_B

019_DDR3L_CA_DQ_VOLTAGE

020_CPU_PCH_CSI2,EMMC

021_CPU_PCH_CGPIO, LPIO, MISC

022_CPU_PCH_AUDIO,SDIO,SDXC

023_CPU_PCH_PCIE,USB,SATA

024_CPU_PCH_CLOCK SIGNALS,RTC

025_CPU_PCH_SYS_POWER

026_CPU_PCH_POEWR,GND

027_CPU_PCH_POEWR,GND

028_PCH-SPI ROM,OTH

030_KBC_KB9026QC

031_KBC_KB,TP

032_RST_Reset Circuit

033_LAN_RTL8111GUX-CG

034_LAN RJ45

044_DEBUG PORT

045_CRT_LCD Panel_CMOS_DMIC

047_eDP to VGA & CRT D-SUB

048_HDMI-type D

050_FAN & SENSOR

051_SATA ODD

052_USB 3.0 CONNECTOR

053_MINICARD(WLAN)

056_PWR_BTN & LID_SW

057_DSG_Discharge

058_PRO_Protect

060_DC_DC & BAT IN

064_BD_HDD_SATA

065_SCREW HOLE, SMT NUT

066_DB_IO_USB*2 & CR & LED

067_MB_LED

068_B to B connector

069_EMI

070_VGA_nVIDIA_N16V/S_PCIE

071_VGA_nVIDIA_N16V/S_FB-IF

072_VGA_nVIDIA_N16V/S_FB-DDR3

073_VGA_nVIDIA_N16V/S_VDD

074_VGA_nVIDIA_N16V/S_DISPLAY

075_VGA_nVIDIA_N16V/S_ROM,XTAL

076_VGA_nVIDIA_N16V/S_GPIO

077_VGA_nVIDIA_N16V/S_POWER

080_PW_IMVP8 (1) (RT3601BCGQW)
081_PW_IMVP8 (2) (RT3601BCGQW)
083_PW_+1.0VSUS / +1.8VSUS
084_PW_+1.2VSUS/+1.2V
086_PW_1.35V/+0.675VS (UP9011Q)
087_PW_+3VADSW/+5VSUS (RT8249C)
088_PW_LOAD SWITCH

089.PW_CHARGER(BQ24780)
090_PW_PROTECTION
091_PW_DGPU_2PHASE(RT8815A)

BLOCK DIAGRAM

D-SUB

Touchpad

Page 31

Keyboard

Page 31

Charger

Page 88

CPU
Thermal Sensor

Page 50

DIMM
Thermal Sensor

Page 14

Audio Codec

Speaker L/R

HDD

ODD

CPU XDP

CX20752

Audio Jack

Page 7

X441UBR SCHEMATIC Revision 2.1

（UA：UMA）
（UV：DGPU = Nvidia N16V-GMR1 ）

Non Connected Standby

e

Page 45

Page 47

ITE 8995

Page 57

Page 32

DDI_2

DDI_1

Page 30

SPI ROM

W25Q64FVSSIQ

SATA_0

DC & BATT. Conn.

Page 44

Page 61

SATA_1

Skew Holes

DP

CPU

Skylake-U

DDI

SML1

I2C1

LPC

PCH
Wildcat_Point

SPI

Page 28

MCP

A

zalia

Page 20~28

SATA

SATA_0

SATA_1

PWM Fan

Page 60

Page 65

Page 48

PS2

SMB0

SMB1

Page 37

Discharge Circuit

DDI to VGA

RTD2168-VAS-CG

20 Pin, B to B conn.
To MB

HDD BD.

20 Pin, B to B conn.
To MB

HDD conn

ODD conn

Reset Circuit

eDP Panel

HDMI type D

Debug Conn.

EC

SPI

Power

+VCCGT
+VCCCORE
+VCCSA

Page 80 & 81

+1.0VSUS / +1.8VSUS

Page 83

+VCCPRIM_CORE

Page 84

+1.35V / +0.675VS

Page 86

Page 33

Page 52

Page 54

+3VADSW/+5VSUS

Load Switch

Charger

+NVVDD

RJ45

Page 34

<Variant Name>

Project Name

X441UBR

Title :

Block Diagram

Size

Dept.:

ASUSTeK COMPUTER INC.

Custom

Date: Sheet of

Friday, April 27, 2018

Page 87

Page 88

Page 89

Page 91

Rev

R2.1

Engineer:

SZ/EE

102

1

DDR4 on-board

512M x 8 x 8 (1 Rank)

DDR3L
1600MH

z

DDR4 so-dimm

Page 3~9Page 48

SMB

PCIE

USB 2.0

USB 3.0

Page 64

Page 50

Page 13~15, 19

Nvidia

N16V-GMR1

Page 70~ 79

GigaLAN

RTL8106E-CG

WLAN + BT

CMOS Camera

Page 45

Card Reader

Page 45

2XUSB 3.0 Standard Conn.

USB 3.0 TypeC Conn.

Page 64

Page 53

PCH_CPT
GPIO

Use as GPO N/A
GPIO setting to
GPO low

PCH_IBEX GPIO

GPP_A0

GPP_A1

GPP_A2

GPP_A3

GPP_A4

GPP_A5

GPP_A6

GPP_A7

GPP_A8

GPP_A9

GPP_A10

GPP_A11

GPP_A12

GPP_A13

GPP_A14

GPP_A15

GPP_A16

GPP_A17

GPP_A18

GPP_A19

GPP_A20

GPP_A21

GPP_A22

GPP_A23

GPP_B0

GPP_B1

GPP_B2

GPP_B3

GPP_B4

GPP_B5

GPP_B6

GPP_B7

GPP_B8

GPP_B9

GPP_B10

GPP_B11

GPP_B12

GPP_B13

GPP_B14

GPP_B15

GPP_B16

GPP_B17

GPP_B18

GPP_B19

GPP_B20

GPP_B21

GPP_B22

GPP_B23

GPP_C0

GPP_C1

GPP_C2

GPP_C3

GPP_C4

GPP_C5

GPP_C6

GPP_C7

GPP_C8

GPP_C9

GPP_C10

GPP_C11

GPP_C12

GPP_C13

GPP_C14

GPP_C15

GPP_C16

GPP_C17

GPP_C18

GPP_C19

GPP_C20

GPP_C21

GPP_C22

GPP_C23

GPP_D0

GPP_D1

GPP_D2

GPP_D3

GPP_D4

GPP_D5

GPP_D6

GPP_D7

GPP_D8

GPP_D9

GPP_D10

GPP_D11

GPP_D12

GPP_D13

GPP_D14

GPP_D15

GPP_D16

GPP_D17

GPP_D18

GPP_D19

GPP_D20

GPP_D21 GPO

GPP_D22

Power on
Default States

Signal NameUse As

RC_IN#

Native1

LPC_AD0

Native1

Native1

LPC_AD1

Native1

LPC_AD2

Native1

LPC_AD3

Native1

LPC_FRAME#

Native1

INT_SERIRQ

GPO

N/A

Native

PM_CLKRUN#

Native1

CLK_KBCPCI_PCH

Native

CLK_DEBUG

GPO

N/A

GPO

N/A

Native1

SUSWARN#

Native1

PCH_SUS_STAT#

Native1

PCH_SUSACK#

GPO

N/A

GPO

N/A

GPO

N/A

N/A

GPO

GPO

N/A

N/A

GPO

N/A

GPO

N/A

GPO

GPO

N/A (VCCPRIM_VID0)

GPO

N/A (VCCPRIM_VID1)

GPO

N/A

GPO

N/A

N/A

GPO

Native

Native

Native

Native

Native

Native

Native

Native

Native

DGPU CLK REQUEST

CK_REQ_P0#

GPO

N/A

GPO

N/A

N/AGPO

GLAN CLOCK REQUEST

CLKREQ_GLAN#

WLAN CLOCK REQUEST

CLKREQ_WLAN#

MPHY_PWREN (N/A)

PCH_SLP_S0#

PLT_RST#

N/A

GPO

GPO

N/A

GPO

N/A

N/A

GPO

N/A

GPO

BT_ON_PCH

GPO

GPU_EVENT#

GPO

GPI

GPO

GPO

GPO

GPO

GPO

GPO

GPO

GPO
GPO

GPO

GPO

GPI

GPI

GPI

GPO N/A

GPO

GPO

GPO

GPO

GPI

GPO

GPO

GPI

GPO

GPO

GPO

GPO

GPO

GPO

GPI

GPO

GPO

GPI

GPO

GPO

GPO

GPI

GPO

GPO

GPO

GPO

GPO

GPO

GPO

GPO

DGPU GC6 2.0 for X441UBR X441UA 設GPO NA

DGPU_FB_CLAMP_GPIO

DGPU GC6 2.0 for X441UBR. X441UA 設GPO NA

DGPU_PWR_EN#

DGPU GC6 2.0 for X441UBR X441UA 設GPO NA

SML1ALERT#

SMB_CK +3VS

SMB_DATA

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

DIMM_SEL0

DIMM_SEL1

DIMM_SEL2

N/A

N/A

N/A

N/A

DGPU_PWROK

GPU_RST#

DGPU_PWR_EN# +3VS

TPanel_INT#

N/A

N/A

N/A

N/A

N/A

SATA_ODD_PWRGT

SATA_ODD_DA#

N/A

N/A

PCB_ID0

High for DMIC/LOW for AMIC

N/A

N/A

N/A

TOUCHPAD_INTR#

N/A

N/A
N/A

N/A

N/A

N/A

N/A

N/A

N/A

Int.& Ext
Pull up / down

EXT PU 10K

EXT PU 10K

EXT PU10K

EXT PU 10K

EXT PU 10K

EXT PU 10K

EXT PU 10K

EXT PU 10K

EXT PU 10K

EXT PU 20K

EXT PU 150K

EXT PU 2.2K

EXT PU 2.2K

EXT PU/PL 10K

EXT PU/PL 10K

EXT PU/PL 10K

EXT PU 100K

EXT PD 10K

EXT PU 10K

EXT PU 10K

EXT PD 10K

EXT PU 10K

EXT PD 10K

EXT PU 10K

Power on

Int.& Ext

Power

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VSUS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VSUS

+3VS

+3VSUS

+3VS

+3VS

+3VSUS

+3VSUS

+3VSUS

+3VS

+3VS

+3VS

+3VS

+3VS

PCH_IBEX GPIO

Use As Signal Name

GPP_D23

GPO

DIRECT_ESATA_DETECT_R#

GPI

GPP_E0

SATA_ODD_PRSNT_R#

GPI

GPP_E1

N/A

GPO

GPP_E2

N/A

GPO

GPP_E3

GPO

GPP_E4

N/A

GPO

GPP_E5

N/A

GPO

GPP_E6

N/A

N/A

GPO

GPP_E7

GPP_E8

GPO N/A

GPP_E9

GPO

N/A

GPP_E10

GPO

N/A

GPP_E11

N/A

GPO

GPP_E12

GPO

N/A

DDPB_HPD_PCH

NATIVE

GPP_E13

HDMI_HP

NATIVE

GPP_E14

EXT_SMI# EXT PU 10K

GPI

GPP_E15

EXT_SCI#

GPP_E16

GPI

EDP_HPD_CON

GPP_E17

NATIVE

DDPB_SCL_PCH

GPP_E18

NATIVE

DDPB_SDA_PCH

GPP_E19

NATIVE

DDPC_SCL_PCH

GPP_E20

NATIVE

DDPC_SDA_PCH

GPP_E21

NATIVE

N/A

GPO

GPP_E22

N/A

GPO

GPP_E23

N/A

GPP_F0

GPO

N/A

GPP_F1

GPO

N/A

GPO

GPP_F2

N/A

GPP_F3

GPO

N/A

GPP_F4

GPO

N/A

GPO

GPP_F5

N/A

GPO

GPP_F6

N/A

GPO

GPP_F7

N/A

GPO

GPP_F8

N/A

GPO

GPP_F9

N/A

GPO

GPP_F10

N/A

GPO

GPP_F11

N/A

GPO

GPP_F12

N/A

GPP_F13

GPO

N/A

GPP_F14

GPO

N/A

GPO

GPP_F15

N/A

GPO

GPP_F16

N/A

GPO

GPP_F17

N/A

GPO

GPP_F18

N/A

+3VS

+3VS

GPO

GPP_F19

N/A

GPP_F20

GPO

N/A

GPP_F21

GPO

N/A

GPO

GPP_F22

N/A

GPP_F23

GPO

N/A (SDIO_CMD)

GPO

GPP_G0

N/A (SDIO_D0)

GPO

GPP_G1

N/A (SDIO_D1)

GPO

GPP_G2

N/A (SDIO_D2)

GPO

GPP_G3

N/A (SDIO_D3)

GPO

GPP_G4

N/A (SDIO_CD#)

GPO

GPP_G5

N/A (SDIO_CLK)

GPO

GPP_G6

N/A (SDIO_WP)

GPO

GPP_G7

PM_BATLOW_R#

Native

GPD0

ME_AC_PRESENT_PCH

Native

GPD1

PCH_GPD2#

GPI

GPD2

PM_PWRBTN#

Native

GPD3

PM_SUSB#

Native

GPD4

PM_SUSC#

Native

GPD5

PM_SLP_A_R#

GPD6

Native

WLAN_ON#

GPO

GPD7

NA (SUS_CK)

Native

GPD8

SLP_WLAN#

Native

GPD9

SLP_S5# (N/A)

Native

GPD10

LAN_PWREN (N/A)

Native

GPD11

Default States

N/A

N/A

N/A

Pull up / down

EXT PU 10K

EXT PU 10K

EXT PU 10K

EXT PD 100K

EXT PU 1M

EXT PU 10K

EXT PD 100K

EXT PU 10K

EXT PU 10K

EXT PU 2.2K

EXT PU 8.2K

EXT PU 100K

EXT PU 10K

EXT PD 10K

EXT PD 10K

EXT PD 1K

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VA_DSW

+3VA_DSW

+3VA_DSW

+3VA_DSW

Power

+3VS

+3VS

+3VSUS

BOM

Project Name

Rev

X441UBR

Title :

System Setting

Size

Dept.:

ASUSTeK COMPUTER INC.

Custom

Date: Sheet of

Friday, April 27, 2018

R2.1

Engineer:

EE

102

2

Main Board

Display Port

B VGA

C HDMI

VGA_LANE0_DN47
VGA_LANE0_DP47
VGA_LANE1_DN47
VGA_LANE1_DP47

HDMI_DATA2N_PCH48
HDMI_DATA2P_PCH48
HDMI_DATA1N_PCH48
HDMI_DATA1P_PCH48
HDMI_DATA0N_PCH48
HDMI_DATA0P_PCH48
HDMI_CLKN_PCH48
HDMI_CLKP_PCH48

+VCCIO

R0301

24.9Ohm
1%

1 2

EDP_COMP

COMPENSATION PU FOR DP

EDPA

DDPB_SCL_PCH
DDPB_SDA_PCH

DDPC_SCL_PCH48
DDPC_SDA_PCH48

PDG#543016 DDI1 mapping DDPB
DDI2 mapping DDPC
DDI0 port A

EDP_COMP

U0301A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL-ULT

DDI

DISPLAY SIDEBANDS

ASUS P/NIntel Version

C47

EDP_TXN[0]

C46

EDP_TXP[0]

D46

EDP_TXN[1]

C45

EDP_TXP[1]

A45

EDP_TXN[2]

B45

EDP_TXP[2]

A47

EDP_TXN[3]

B47

EDP_TXP[3]

E45

EDP_AUXN

EDP

EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

F45

B52

DP_UTIL

G50
F50
E48
F48
G46
F46

L9
L7
L6
N9

EXT_SMI#

L10

EXT_SCI#_X1

EDP_HPD_CON

R12
R11

LCD_BACKEN_PCH_X1

U13

L_BKLTCTL_PCH_X1

L_VDDEN_PCH_X1

R0302 0Ohm@

SL0304@

1 2

DDPB_AUXN_PCH 47
DDPB_AUXP_PCH 47

0402

SL0301@
SL0302@
SL0303@

EDP_TXN0 45
EDP_TXP0 45
EDP_TXN1 45
EDP_TXP1 45

EDP_AUXN 45
EDP_AUXP 45

DDPB_HPD_PCH 47
HDMI_HP 48
EXT_SMI# 30

21

EXT_SCI# 30
EDP_HPD_CON 45

21

0402

21

0402

21

0402

eDP_HDP

EC:OD

VGA

LCD_BACKEN_PCH 45
L_BKLTCTL_PCH 45
L_VDDEN_PCH 45

543016 844
DDPB_SDA_PCH: PU 2.2 enable port 1

BOM

Title :

CPU_DISPLAY

Size

Dept.:

Custom

Date: Sheet

Friday, April 27, 2018

EDP_HPD_CON
EXT_SMI#

EXT_SCI#_X1

DDPB_SCL_PCH
DDPB_SDA_PCH

Project Name

X441UBR

ASUSTeK COMPUTER INC.

R0303 10KOhm@

1 2

R0305 10KOhm

1 2

R0306 10KOhm

1 2

R0304 10KOhm @

12

1 2

R0307 2.2kOHM

Engineer:

SZ/EE

of

3

+3VS

Rev

R2.1

102

M_A_DQ[63:0]14

AL71
AL68

M_A_DQ0

AN68

M_A_DQ1

AN69

M_A_DQ2

AL70

M_A_DQ3

AL69

M_A_DQ4

AN70

M_A_DQ5

AN71

M_A_DQ6

AR70

M_A_DQ7

AR68

M_A_DQ8

AU71

M_A_DQ9

AU68

M_A_DQ10

AR71

M_A_DQ11

AR69

M_A_DQ12

AU70

M_A_DQ13

AU69

M_A_DQ14

BB65

M_A_DQ15

AW65

M_A_DQ16

AW63

M_A_DQ17

AY63

M_A_DQ18

BA65

M_A_DQ19

AY65

M_A_DQ20

BA63

M_A_DQ21

BB63

M_A_DQ22

BA61

M_A_DQ23

AW61

M_A_DQ24

BB59

M_A_DQ25

AW59

M_A_DQ26

BB61

M_A_DQ27

AY61

M_A_DQ28

BA59

M_A_DQ29

AY59

M_A_DQ30

AY39

M_A_DQ31

AW39

M_A_DQ32

AY37

M_A_DQ33

AW37

M_A_DQ34

BB39

M_A_DQ35

BA39

M_A_DQ36

BA37

M_A_DQ37

BB37

M_A_DQ38

AY35

M_A_DQ39

AW35

M_A_DQ40

AY33

M_A_DQ41

AW33

M_A_DQ42

BB35

M_A_DQ43

BA35

M_A_DQ44

BA33

M_A_DQ45

BB33

M_A_DQ46

AY31

M_A_DQ47

AW31

M_A_DQ48

AY29

M_A_DQ49

AW29

M_A_DQ50

BB31

M_A_DQ51

BA31

M_A_DQ52

BA29

M_A_DQ53

BB29

M_A_DQ54

AY27

M_A_DQ55

AW27

M_A_DQ56

AY25

M_A_DQ57

AW25

M_A_DQ58

BB27

M_A_DQ59

BA27

M_A_DQ60

BA25

M_A_DQ61

BB25

M_A_DQ62
M_A_DQ63

DDR_VTT_CTRL:
System Memory Power Gate Control:
Disables the pla.orm memory VT T regulator
in C8 and deeper and S3.
Ref:544924_544924_Skylake_EDS_Vol_1_Rev0.9.pdf P.120

VTT Enable

DDR_VTT_CTRL

R0402 0Ohm@

Memory Channel A

U0301B

DDR0_DQ[0]
DDR0_DQ[1]
DDR0_DQ[2]
DDR0_DQ[3]
DDR0_DQ[4]
DDR0_DQ[5]
DDR0_DQ[6]
DDR0_DQ[7]
DDR0_DQ[8]
DDR0_DQ[9]
DDR0_DQ[10]
DDR0_DQ[11]
DDR0_DQ[12]
DDR0_DQ[13]
DDR0_DQ[14]
DDR0_DQ[15]
DDR0_DQ[16]/DDR0_DQ[32]
DDR0_DQ[17]/DDR0_DQ[33]
DDR0_DQ[18]/DDR0_DQ[34]
DDR0_DQ[19]/DDR0_DQ[35]
DDR0_DQ[20]/DDR0_DQ[36]
DDR0_DQ[21]/DDR0_DQ[37]
DDR0_DQ[22]/DDR0_DQ[38]
DDR0_DQ[23]/DDR0_DQ[39]
DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41]
DDR0_DQ[26]/DDR0_DQ[42]
DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_DQ[29]/DDR0_DQ[45]
DDR0_DQ[30]/DDR0_DQ[46]
DDR0_DQ[31]/DDR0_DQ[47]
DDR0_DQ[32]/DDR1_DQ[0]
DDR0_DQ[33]/DDR1_DQ[1]
DDR0_DQ[34]/DDR1_DQ[2]
DDR0_DQ[35]/DDR1_DQ[3]
DDR0_DQ[36]/DDR1_DQ[4]
DDR0_DQ[37]/DDR1_DQ[5]
DDR0_DQ[38]/DDR1_DQ[6]
DDR0_DQ[39]/DDR1_DQ[7]
DDR0_DQ[40]/DDR1_DQ[8]
DDR0_DQ[41]/DDR1_DQ[9]
DDR0_DQ[42]/DDR1_DQ[10]
DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQ[44]/DDR1_DQ[12]
DDR0_DQ[45]/DDR1_DQ[13]
DDR0_DQ[46]/DDR1_DQ[14]
DDR0_DQ[47]/DDR1_DQ[15]
DDR0_DQ[48]/DDR1_DQ[32]
DDR0_DQ[49]/DDR1_DQ[33]
DDR0_DQ[50]/DDR1_DQ[34]
DDR0_DQ[51]/DDR1_DQ[35]
DDR0_DQ[52]/DDR1_DQ[36]
DDR0_DQ[53]/DDR1_DQ[37]
DDR0_DQ[54]/DDR1_DQ[38]
DDR0_DQ[55]/DDR1_DQ[39]
DDR0_DQ[56]/DDR1_DQ[40]
DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42]
DDR0_DQ[59]/DDR1_DQ[43]
DDR0_DQ[60]/DDR1_DQ[44]
DDR0_DQ[61]/DDR1_DQ[45]
DDR0_DQ[62]/DDR1_DQ[46]
DDR0_DQ[63]/DDR1_DQ[47]

SKL-ULT

REV = <REV>

1 2

DDR_PG_CTRL_RR

Memory Channel B

AU53

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

/DDR0_CAA[0]/DDR0_MA[5]

DDR0_MA[5]
DDR0_MA[9]

/DDR0_CAA[1]/DDR0_MA[9]

DDR0_MA[6]

/DDR0_CAA[2]/DDR0_MA[6]
/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[8]

/DDR0_CAA[4]/DDR0_MA[7]

DDR0_MA[7]

/DDR0_CAA[5]/DDR0_BG[0]

DDR0_BA[2]

/DDR0_CAA[6]/DDR0_MA[12]

DDR0_MA[12]

/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[11]

/DDR0_CAA[8]/DDR0_ACT#

DDR0_MA[15]

/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[14]

DDR0_MA[13]

/DDR0_CAB[0]/DDR0_MA[13]
/DDR0_CAB[1]/DDR0_MA[15]

DDR0_CAS#

DDR0_WE#

/DDR0_CAB[2]/DDR0_MA[14]
/DDR0_CAB[3]/DDR0_MA[16]

DDR0_RAS#

/DDR0_CAB[4]/DDR0_BA[0]

DDR0_BA[0]

/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[2]

/DDR0_CAB[6]/DDR0_BA[1]

DDR0_BA[1]

/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[10]

/DDR0_CAB[8]/DDR0_MA[1]

DDR0_MA[1]

/DDR0_CAB[9]/DDR0_MA[0]

DDR0_MA[0]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_ALERT#

DDR_VREF_CA

DDR0_VREF_DQ

DDR CH - A

DDR1_VREF_DQ

DDR_VTT_CNTL

U0401

1

NC

2

A

3 4

GND

U74AUP1G07G-AL5-R

DDR0_PAR

VCC

Y

AT53

AU55

AT55

BA56

BB56

AW56

AY56

AU45

AU43

AT45

AT43

BA51

BB54

M_A_A5

BA52

M_A_A9

AY52

M_A_A6

AW52

M_A_A8

AY55

M_A_A7

AW54
BA54

M_A_A12

BA55

M_A_A11

AY54

AU46
AU48

M_A_A13

AT46
AU50
AU52
AY51
AT48

M_A_A2

AT50
BB50

M_A_A10

AY50

M_A_A1

BA50

M_A_A0

BB52

M_A_A3

M_A_A4

AM70
AM69

M_A_DQS#0

AT69

M_A_DQS0

AT70

M_A_DQS#1

BA64

M_A_DQS1

AY64

M_A_DQS#2

AY60

M_A_DQS2

BA60

M_A_DQS#3

BA38

M_A_DQS3

AY38

M_A_DQS#4

AY34

M_A_DQS4

BA34

M_A_DQS#5

BA30

M_A_DQS5

AY30

M_A_DQS#6

AY26

M_A_DQS6

BA26

M_A_DQS#7

M_A_DQS7

AW50
AT52

AY67
AY68
BA67

AW67

DDR_VTT_CTRL

DDR0_Vref_DQ - Not in use in DDR4,
DDR1_Vref_DQ = DDR4_CA_ch1,
DDR_Vref_CA = DD4_CA_ch0

+1.2V

12

5

DDR_PG_CTRL_Y

M_A_CLK_DDR#0 13,14
M_A_CLK_DDR0 13,14

M_A_CKE0 13,14

M_A_CS#0 13,14

M_A_ODT0 13,14

M_A_BG0 13,14

M_A_ACT# 13,14

M_A_CAS# 13,14
M_A_WE# 13,14
M_A_RAS# 13,14
M_A_BA0 13,14

M_A_BA1 13,14

M_A_ALERT# 13,14

M_A_PAR 13,14

SA_DIMM_VREFCA 18

SB_DIMM_VREFCA 18

+3VS

12

C0402

R0404
300KOhm

0.1UF/16V

R0409 0Ohm

SUSB_EC#30,45,57,88

Control From EC SUSB

M_A_A[13:0] 13,14

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_DQS#[7:0] 14

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2

M_A_DQS[7:0] 14

M_A_DQS#3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

DDR_PG_CTRL 86

@

1 2

M_B_DQ[63:0]17

U0301C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

M_B_DQ0

DDR1_DQ[1]/DDR0_DQ[17]

AK65

M_B_DQ1

DDR1_DQ[2]/DDR0_DQ[18]

AK64

M_B_DQ2

DDR1_DQ[3]/DDR0_DQ[19]

AF66

M_B_DQ3

DDR1_DQ[4]/DDR0_DQ[20]

AF67

M_B_DQ4

DDR1_DQ[5]/DDR0_DQ[21]

AK67

M_B_DQ5

DDR1_DQ[6]/DDR0_DQ[22]

AK66

M_B_DQ6

DDR1_DQ[7]/DDR0_DQ[23]

AF70

M_B_DQ7

DDR1_DQ[8]/DDR0_DQ[24]

AF68

M_B_DQ8

DDR1_DQ[9]/DDR0_DQ[25]

AH71

M_B_DQ9

DDR1_DQ[10]/DDR0_DQ[26]

AH68

M_B_DQ10

DDR1_DQ[11]/DDR0_DQ[27]

AF71

M_B_DQ11

DDR1_DQ[12]/DDR0_DQ[28]

AF69

M_B_DQ12

DDR1_DQ[13]/DDR0_DQ[29]

AH70

M_B_DQ13

DDR1_DQ[14]/DDR0_DQ[30]

AH69

M_B_DQ14

AT66

M_B_DQ15

AU66

M_B_DQ16

AP65

M_B_DQ17

AN65

M_B_DQ18

AN66

M_B_DQ19

AP66

M_B_DQ20

AT65

M_B_DQ21

AU65

M_B_DQ22

AT61

M_B_DQ23

AU61

M_B_DQ24

AP60

M_B_DQ25

AN60

M_B_DQ26

AN61

M_B_DQ27

AP61

M_B_DQ28

AT60

M_B_DQ29

AU60

M_B_DQ30

AU40

M_B_DQ31

AT40

M_B_DQ32

AT37

M_B_DQ33

AU37

M_B_DQ34

AR40

M_B_DQ35

AP40

M_B_DQ36

AP37

M_B_DQ37

AR37

M_B_DQ38

AT33

M_B_DQ39

AU33

M_B_DQ40

AU30

M_B_DQ41

AT30

M_B_DQ42

AR33

M_B_DQ43

AP33

M_B_DQ44

AR30

M_B_DQ45

AP30

M_B_DQ46

AU27

M_B_DQ47

AT27

M_B_DQ48

AT25

M_B_DQ49

AU25

M_B_DQ50

AP27

M_B_DQ51

AN27

M_B_DQ52

AN25

M_B_DQ53

AP25

M_B_DQ54

AT22

M_B_DQ55

AU22

M_B_DQ56

AU21

M_B_DQ57

AT21

M_B_DQ58

AN22

M_B_DQ59

AP22

M_B_DQ60

AP21

M_B_DQ61

AN21

M_B_DQ62
M_B_DQ63

DDR1_DQ[15]/DDR0_DQ[31]
DDR1_DQ[16]/DDR0_DQ[48]
DDR1_DQ[17]/DDR0_DQ[49]
DDR1_DQ[18]/DDR0_DQ[50]
DDR1_DQ[19]/DDR0_DQ[51]
DDR1_DQ[20]/DDR0_DQ[52]
DDR1_DQ[21]/DDR0_DQ[53]
DDR1_DQ[22]/DDR0_DQ[54]
DDR1_DQ[23]/DDR0_DQ[55]
DDR1_DQ[24]/DDR0_DQ[56]
DDR1_DQ[25]/DDR0_DQ[57]
DDR1_DQ[26]/DDR0_DQ[58]
DDR1_DQ[27]/DDR0_DQ[59]
DDR1_DQ[28]/DDR0_DQ[60]
DDR1_DQ[29]/DDR0_DQ[61]
DDR1_DQ[30]/DDR0_DQ[62]
DDR1_DQ[31]/DDR0_DQ[63]
DDR1_DQ[32]/DDR1_DQ[16]
DDR1_DQ[33]/DDR1_DQ[17]
DDR1_DQ[34]/DDR1_DQ[18]
DDR1_DQ[35]/DDR1_DQ[19]
DDR1_DQ[36]/DDR1_DQ[20]
DDR1_DQ[37]/DDR1_DQ[21]
DDR1_DQ[38]/DDR1_DQ[22]
DDR1_DQ[39]/DDR1_DQ[23]
DDR1_DQ[40]/DDR1_DQ[24]
DDR1_DQ[41]/DDR1_DQ[25]
DDR1_DQ[42]/DDR1_DQ[26]
DDR1_DQ[43]/DDR1_DQ[27]
DDR1_DQ[44]/DDR1_DQ[28]
DDR1_DQ[45]/DDR1_DQ[29]
DDR1_DQ[46]/DDR1_DQ[30]
DDR1_DQ[47]/DDR1_DQ[31]
DDR1_DQ[48]
DDR1_DQ[49]
DDR1_DQ[50]
DDR1_DQ[51]
DDR1_DQ[52]
DDR1_DQ[53]
DDR1_DQ[54]
DDR1_DQ[55]
DDR1_DQ[56]
DDR1_DQ[57]
DDR1_DQ[58]
DDR1_DQ[59]
DDR1_DQ[60]
DDR1_DQ[61]
DDR1_DQ[62]
DDR1_DQ[63]

SKL-ULT

REV = <REV>

DDR1_MA[5]

DDR1_MA[9]

DDR1_MA[6]

DDR1_MA[8]

DDR1_MA[7]

DDR1_BA[2]

DDR1_MA[12]

DDR1_MA[11]

DDR1_MA[15]

DDR1_MA[14]

DDR1_MA[13]

DDR1_CAS#

DDR1_RAS#

DDR1_BA[0]

DDR1_MA[2]

DDR1_BA[1]

DDR1_MA[10]

DDR1_MA[1]
DDR1_MA[0]

DDR CH - B

AN45

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

/DDR1_CAA[0]/DDR1_MA[5]
/DDR1_CAA[1]/DDR1_MA[9]
/DDR1_CAA[2]/DDR1_MA[6]
/DDR1_CAA[3]/DDR1_MA[8]
/DDR1_CAA[4]/DDR1_MA[7]

/DDR1_CAA[5]/DDR1_BG[0]
/DDR1_CAA[6]/DDR1_MA[12]
/DDR1_CAA[7]/DDR1_MA[11]

/DDR1_CAA[8]/DDR1_ACT#

/DDR1_CAA[9]/DDR1_BG[1]

/DDR1_CAB[0]/DDR1_MA[13]
/DDR1_CAB[1]/DDR1_MA[15]
/DDR1_CAB[2]/DDR1_MA[14]

DDR1_WE#

/DDR1_CAB[3]/DDR1_MA[16]

/DDR1_CAB[4]/DDR1_BA[0]

/DDR1_CAB[5]/DDR1_MA[2]

/DDR1_CAB[6]/DDR1_BA[1]
/DDR1_CAB[7]/DDR1_MA[10]

/DDR1_CAB[8]/DDR1_MA[1]

/DDR1_CAB[9]/DDR1_MA[0]

DDR1_MA[3]
DDR1_MA[4]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET#

DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]

DRAMRST#

M_B_CLK_DDR#0 17

AN46

M_B_CLK_DDR#1 17

AP45

M_B_CLK_DDR0 17

AP46

M_B_CLK_DDR1 17

AN56

M_B_CKE0 17

AP55

M_B_CKE1 17

AN55
AP53

BB42

M_B_CS#0 17

AY42

M_B_CS#1 17

BA42

M_B_ODT0 17

AW42

M_B_ODT1 17

AY48
AP50

M_B_A5

BA48

M_B_A9

BB48

M_B_A6

AP48

M_B_A8

AP52

M_B_A7

M_B_BG0 17

AN50
AN48

M_B_A12

AN53

M_B_A11

M_B_ACT# 17

AN52

M_B_BG1 17

BA43
AY43

M_B_A13

M_B_CAS# 17

AY44

M_B_WE# 17

AW44

M_B_RAS# 17

BB44

M_B_BA0 17

AY47
BA44

M_B_A2

M_B_BA1 17

AW46
AY46

M_B_A10

BA46

M_B_A1

BB46

M_B_A0

BA47

M_B_A3

M_B_A4

AH66
AH65

M_B_DQS#0

AG69

M_B_DQS0

AG70

M_B_DQS#1

AR66

M_B_DQS1

AR65

M_B_DQS#2

AR61

M_B_DQS2

AR60

M_B_DQS#3

AT38

M_B_DQS3

AR38

M_B_DQS#4

AT32

M_B_DQS4

AR32

M_B_DQS#5

AR25

M_B_DQS5

AR27

M_B_DQS#6

AR22

M_B_DQS6

AR21

M_B_DQS#7

M_B_DQS7

AN43

M_B_ALERT# 17

AP43

DDR1_PAR

AT13

AR18

DRAMRST#

AT18

SM_RCOMP_0

AU18

SM_RCOMP_1

SM_RCOMP_2

OD

M_B_PAR 17

1 2

R0403 200Ohm 1%

1 2

R0406 80.6Ohm 1%

1 2

R0408 100Ohm 1%

+1.2V

12

R0401

470Ohm
1%

SL0401

21

0402

0.1UF/16V

@

C0401

M:X16 memory RCOMP0 改為200ohm.

12

N/A

GND

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

DDR4_DRAMRST# 14,17

M_B_A[13:0] 17

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_DQS#[7:0] 17

M_B_DQS[7:0] 17

Project Name

X441UBR

Title :

CPU_DDR4

Size

Dept.:

D

Date: Sheet

Friday, April 27, 2018

Rev

R2.1

Engineer:

SZ/EE

102

of

4

SPI_CLK_SPI_228,30
SPI_SO_SPI_228,30
SPI_SI_SPI_228,30
PCH_SPI_DQ228
PCH_SPI_DQ328

SPI_CS#0_SPI_228,30

+3VS

SML1ALERT# /PCHHOT#/GPP_B23
LOW during strap sampling:internal 20K PD;
When used as PCHHOT#, a 150k weak board
pull-up is recommended ;

R0522 10KOhm

R0519 10KOhm

+3VSUS

R0508 150KOHM

1 2

R0510 15Ohm

1 2

R0509 15Ohm

1 2

R0539 15Ohm

1 2

R0540 15Ohm
R0504

0402

CS# no need R1

RC_IN#30

INT_SERIRQ30

1 2

1 2

1 2

1 2

R0503 15Ohm

U0301E

Main Board

SPI - FLASH

AV2

SPI0_CLK

INT_SERIRQ

AW13

AW3
AV3
AW2
AU4
AU3
AU2
AU1

M2
M3
J4
V1
V2
M1

G3
G2
G1

AY11

SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#

C LINK

CL_CLK
CL_DATA
CL_RST#

GPP_A0/RCIN#

GPP_A6/SERIRQ

SKL-ULT

REV = <REV>

+3VSUS +3VSUS

R0507 10KOhm

GPP_C5: weak internal pull down 20k

PU

SPI_CLK_SPI_2_X1
SPI_SO_SPI_2_X1
SPI_SI_SPI_2_X1
PCH_SPI_DQ2_X1

21

PCH_SPI_DQ3_X1
SPI_CS#0_SPI_2_X1

PM_CLKRUN#

INT_SERIRQ

SML1ALERT#

PD

SMBUS, SMLINK

LPC

@

1 2

eSPI BUS

LPC is selected for EC (Default)

R7

GPP_C0/SMBCLK

R8

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_B23/SML1ALERT#/PCHHOT#

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

RN0503A

2.2KOHM

SMB_CK

SMB_DATA SMB_DATA_S3

GPP_C5 GPP_C2

SMB_CK

R10

SMB_DATA

GPP_C2

R9
W2
W1

GPP_C5

W3
V3
AM7

SML1ALERT#

AY13
BA13
BB13
AY12
BA12
BA11

AW9
AY9
AW11

+3VSUS +3VS

12

34

RN0503B

2.2KOHM

@

@

GPP_C2: weak internal pull down 20k

LPC_AD0 30,44
LPC_AD1 30,44
LPC_AD2 30,44
LPC_AD3 30,44

LPC_FRAME# 30,44
PCH_SUS_STAT# 30

R0512 22Ohm

R0514 22Ohm

CLK_KBCPCI_PCH_X1

CLK_TPMPCI_PCH_X1

PM_CLKRUN#

+12VS

2

61

@

Q0501A

EM6K1-G-T2R

5

34

@

Q0501B

EM6K1-G-T2R

R0501 0Ohm

12

R0513 0Ohm

12

Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).

@

R0506 10KOhm

1 2

PU Enable

Disable Intel ME TLS ipher suite
( no confodentiality)(Default)

PD

1 2
1 2

SMB_CK_S3

TO DIMM / VGA

RN0504A

2.2KOHM

Checking
Need add
PCH_SUS_STAT#
to EC

CLK_KBCPCI_PCH 30
CLK_DEBUG 44

PM_CLKRUN# 30

34

12

RN0504B

2.2KOHM

SMB_CK_S3 17,47

TO DIMM / VGA

SMB_DATA_S3 17,47

BOM

Title :

Size

Custom

Date: Sheet

CPU_LPC,SPI,SMB,CLINK

Dept.:

ASUSTeK COMPUTER INC.

Friday, April 27, 2018

Project Name

X441UBR

Engineer:

Rev

R2.1

SZ/EE

102

of

5

+VCCCORE +VCCCORE

U0301L

CPU POWER 1 OF 4

A30

VCC_A30

A34

VCC_A34

A39

VCC_A39

A44

VCC_A44

AK33

VCC_AK33

AK35

VCC_AK35

AK37

VCC_AK37

AK38

VCC_AK38

AK40

VCC_AK40

AL33

VCC_AL33

AL37

VCC_AL37

AL40

VCC_AL40

AM32

VCC_AM32

AM33

VCC_AM33

AM35

VCC_AM35

AM37

VCC_AM37

AM38

VCC_AM38

G30

VCC_G30

K32

RSVD_K32

AK32

RSVD_AK32

AB62

VCCOPC_AB62

P62

VCCOPC_P62

V62

VCCOPC_V62

H63

VCC_OPC_1P8_H63

G61

VCC_OPC_1P8_G61

REV = <REV>

AC63

VCCOPC_SENSE

AE63

VSSOPC_SENSE

AE62

VCCEOPIO_1

AG62

VCCEOPIO_2

AL63

VCCEOPIO_SENSE

AJ62

VSSEOPIO_SENSE

SKL-ULT N/A

unconnected for Processors without OPC

+VCCIO +VCCSTG

Volume Segment
+VCCIO is supplied +1.0VS (shared with +VCCSTG)

G32

VCC_G32

G33

VCC_G33

G35

VCC_G35

G37

VCC_G37

G38

VCC_G38

G40

VCC_G40

G42

VCC_G42

J30

VCC_J30

J33

VCC_J33

J37

VCC_J37

J40

VCC_J40

K33

VCC_K33

K35

VCC_K35

K37

VCC_K37

K38

VCC_K38

K40

VCC_K40

K42

VCC_K42

K43

VCC_K43

E32

VCC_SENSE

E33

VSS_SENSE

B63

VIDALERT#

A63

P_SVID_ALERT#_X3

VIDSCK

D64

VIDSOUT

P_SVID_DATA_X3

G20

VCCSTG_G20

21

SL0630@

0.04A

0603

P_VCCCORE_VCCSENSE 80
P_VCCCORE_VSSSENSE 80

U42 VCCCORE U22VccGT

+VCCST +1.2V

R1.0-3

R0606

SVID DATA

100Ohm

1%

1 2

N/A

21

P_SVID_DATA_X3

SL0609@

VR_SVID_DATA 80

0402

SVID CLOCK

21

P_SVID_CLK_X3P_SVID_CLK_X3

P_SVID_ALERT#_X3

U42/U22 colay

+VCCGT +VCCCORE/GT

+VCCCORE

+VCCGT

SL0617@

SVID ALERT

R0603

1 2

R0605

1 2

R0607

1 2

R0609

1 2

0Ohm

1 2

U22

0Ohm

U42

0Ohm

U42

0Ohm

/7020

+VCCSTG

VR_SVID_CLK 80

0402

+VCCST

R0601

56Ohm

N/A

1 2

R0604

VR_SVID_ALERT# 80

N/A

220Ohm

+VCCCORE/GTx+VCCCORE

+VCCGT +VCCGT +1.2V

+VCCCORE/GT

+VCCGT

P_VCCGT_VCCSENSE80
P_VCCGT_VSSSENSE80

CPU - VCCGT DECAPS- Underneath the package

+VCCGT

31A 2+2

1UF/6.3V N/A

U0301M

CPU POWER 2 OF 4

N70

VCCGT56
VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26

VCCGTX_AK42

VCCGT27

VCCGTX_AK43

VCCGT28

VCCGTX_AK45

VCCGT29

VCCGTX_AK46

VCCGT30

REV = <REV>

VCCGTX_AK48

VCCGT31

VCCGTX_AK50

VCCGT32

VCCGTX_AK52

VCCGT33

VCCGTX_AK53

VCCGT34

VCCGTX_AK55

VCCGT35

VCCGTX_AK56

VCCGT36

VCCGTX_AK58

VCCGT37

VCCGTX_AK60

VCCGT38

VCCGTX_AK70

VCCGT39

VCCGTX_AL43

VCCGT40

VCCGTX_AL46

VCCGT41

VCCGTX_AL50

VCCGT42

VCCGTX_AL53

VCCGT43

VCCGTX_AL56

VCCGT44

VCCGTX_AL60

VCCGT45

VCCGTX_AM48

VCCGT46

VCCGTX_AM50

VCCGT47

VCCGTX_AM52

VCCGT48

VCCGTX_AM53

VCCGT49

VCCGTX_AM56

VCCGT50

VCCGTX_AM58

VCCGT51

VCCGTX_AU58

VCCGT52

VCCGTX_AU63

VCCGT53

VCCGTX_BB57

VCCGT54

VCCGTX_BB66

VCCGT55

VCCGTX_SENSE

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

SKL-ULT N/A

12

C0607

@

10UF/6.3V

12

12

C0632

C0631

1UF/6.3V

1UF/6.3V

@

@

12

C0667

1UF/6.3V

@

12

12

C0611

C0678

1UF/6.3V
N/A

4.7UF/6.3V

VCCGT57

VCCGT58

VCCGT59

VCCGT60

VCCGT61

VCCGT62

VCCGT63

VCCGT64

VCCGT65

VCCGT66

VCCGT67

VCCGT68

VCCGT69

VCCGT70

VCCGT71

VCCGT72

VCCGT73

VCCGT74

VCCGT75

VCCGT76

VCCGT77

VCCGT78

VCCGT79

VCCGT80

12

@

N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

12

C0610
@

10UF/6.3V

12

C0634

C0652

1UF/6.3V

1UF/6.3V

N/A

SL0610@

+VCCCORE/GTx

U42: VCCCORE U2+3e: VccGTX

/7020

1 2

R0608
0Ohm

12

C0626
@

10UF/6.3V

12

12

12

C0654

C0638

C0636

1UF/6.3V

1UF/6.3V

1UF/6.3V

@

@

N/A

+1.2V

+VCCGT

A48
A53
A58
A62

A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

J43

J45

J46

J48

J50

J52

J53

J55

J56

J58

J60

K48

0Ohm

K50

K52

12

R0602

K53

K55

U22

K56

K58

K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62

N63

N64

N66

N67

N69

J70

J69

12

C0620

@

10UF/6.3V

12

12

12

C0629

C0628

C0630

@

1UF/6.3V@

1UF/6.3V

1UF/6.3V

@

12

12

12

C0640

C0613

C0656

N/A

@

1UF/6.3V

1UF/6.3V

+VCCCORE/GTx+VCCCORE/GT

12

12

C0608

C0679

1UF/6.3V
N/A

4.7UF/6.3V

21

0603

+VDDQ_CPU_CLK

SL0633 0Ohm

1 2

nbs_r0603_h24_000s

U0301N

CPU POWER 3 OF 4

AU23

VDDQ_AU23

AU28

VDDQ_AU28

AU35

12

C0615
N/A

10UF/6.3V

+VCCSTG

+VCCPLL_OC

@

100mA

12

C0663

1UF/6.3VN/A

VDDQ_AU35

AU42

VDDQ_AU42

BB23

VDDQ_BB23

BB32

VDDQ_BB32

BB41

VDDQ_BB41

BB47

VDDQ_BB47

BB51

VDDQ_BB51

+VCCST

AM40

VDDQC

+VDDQ_CPU_CLK

A18

VCCST

A22

VCCSTG_A22

AL23

VCCPLL_OC

+1.0V_VCCPLL

K20

VCCPLL_K20

K21

VCCPLL_K21

SKL-ULT N/A

REV = <REV>

+1.2V

2.8A

+1.0V_VCCPLL

+VCCST

21

SL0634@

120mA

0603

+VCCIO

3.1A

C0619

10UF/6.3V

N/A

+VCCSA

CPU - VCCSA DECAPS- Underneath the package

5.1A

12

12

C0651

C0633

N/A

1UF/6.3VN/A

1UF/6.3V

12

12

12

+VCCIO

AK28

VCCIO1

AK30

VCCIO2

AL30

VCCIO3

AL42

VCCIO4

AM28

VCCIO5

AM30

VCCIO6

AM42

+VCCSA

VCCIO7

AK23

VCCSA1

AK25

VCCSA2

G23

VCCSA3

G25

VCCSA4

G27

VCCSA5

G28

VCCSA6

J22

VCCSA7

J23

VCCSA8

J27

VCCSA9

K23

VCCSA10

K25

VCCSA11

K27

VCCSA12

K28

VCCSA13

K30

VCCSA14

AM23

VCCIO_SENSE

AM22

VSSIO_SENSE

H21

VSSSA_SENSE

H20

VCCSA_SENSE

CPU - VDDQ DECAPS- Place close to the package

12

12

C0662

C0618

10UF/6.3V
N/A

10UF/6.3V
@

C0616
N/A

1UF/6.3V

CPU - VCCIO DECAPS- Place close to the package

12

C0605

10UF/6.3V
N/A

12

12

C0653

C0635

N/A

1UF/6.3V

N/A

1UF/6.3V

12

@

12

12

C0641

@

10UF/6.3V

CAP option check OK

12

12

C0606

C0658

C0603

C0648

@

22UF/6.3V

10UF/6.3V

10UF/6.3V

10UF/6.3V

@

@

nbs_c0603_h39_000s

12

C0621

C0622

N/A

N/A

1UF/6.3V

1UF/6.3V

12

12

@
C0668

C0649

@

10UF/6.3V

10UF/6.3V

12

12

C0655

C0637

1UF/6.3V

1UF/6.3V

N/A

@

BOM

12

C0614

10UF/6.3V

N/A

Project Name

X441UBR

Title :

CPU_POEWR

Size

Dept.:

ASUSTeK COMPUTER INC.

D

Date: Sheet

Friday, April 27, 2018

Rev

R2.1

Engineer:

SZ/EE

103

of

6

+VCCST

R0802

1 2

1KOhm

1%

CPU SIDEBAND SIGNALS

H_PROCHOT_D# H_PROCHOT_D#_R

PECI_EC30

1 2

R0813

49.9Ohm
1%

1 2

499OHM

1

T0801@

H_CATERR#

PECI_EC

H_PROCHOT_D#
THERMTRIP#

R0812

R0811

49.9Ohm

49.9Ohm

1%

1%

1 2

1 2

+VCCSTG

12

R0809

R0808

1KOhm

12

C0801

43PF/50V

D63
A54
C65
C63
A65

C55
D55
B54
C56

BA5
AY5

AT16
AU16

H66
H65

R0810

49.9Ohm
1%

1 2

@

U0301D

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

CPU MISC

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

SKL-ULT

REV = <REV>

20150108
Checking
SL0801~0803 near device side

2 1

SL0802@

0402

2 1

SL0801@

0402

2 1

SL0803@

0402

JTAG

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

OD

THRO_CPU# 30

IMVP8_VRHOT# 80

PWRLIMIT#_CPU 89

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PCH_TRST#

Main Board

B61
D60

XDP_TCLK_CPU

A61

XDP_TDI_CPU

C60

XDP_TDO_CPU

B59

XDP_TMS_CPU

XDP_TRST_CPU#

B56
D59

PCH_JTAG_TCK

A56

PCH_JTAG_TDI

C59

PCH_JTAG_TDO

C61

PCH_JTAG_TMS

A59

JTAGX

XDP_TCK_JTAGX

+VCCSTG

XDP_TDO_CPU

XDP_TDI_CPU

XDP_TMS_CPU

XDP_TCLK_CPU

XDP_TRST_CPU#

1 2

R0820 51Ohm@

1 2

R0804 51Ohm@

1 2

R0805 51Ohm@

1 2

R0806 51Ohm@

1 2

R0807 51Ohm@

+VCCSTG

PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
XDP_TCK_JTAGX

PCH_JTAG_TCK

1 2

R0814 51Ohm@

1 2

R0817 51Ohm@

1 2

R0816 51Ohm@

1 2

R0819 51Ohm@

1 2

R0818 51Ohm@

BOM

Title :

Size

B

Date: Sheet

CPU_MISC,JTAG,CLK

Dept.:

Friday, April 27, 2018

Project Name

X441UBR

ASUSTeK COMPUTER INC.

Engineer:

SZ/EE

Rev

R2.1

102

of

8

Main Board

U0301S

RESERVED SIGNALS-1

E68

CFG[0]

B67

CFG[1]

D65

CFG[2]

D67

CFG[3]

E70

CFG[4]

C68

CFG4 XTAL24_R_OUT

CFG[5]

D68

CFG[6]

C67

CFG[7]

F71

CFG[8]

G69

CFG[9]

F70

CFG[10]

G68

CFG[11]

REV = <REV>

H70

CFG[12]

G71

CFG[13]

H69

CFG[14]

G70

CFG[15]

E63

CFG[16]

F63

CFG[17]

E66

CFG[18]

F66

CFG[19]

E60

CFG_RCOMP

E8

ITP_PMODE

AY2

RSVD_AY2

AY1

RSVD_AY1

D1

RSVD_D1

R0902

49.9Ohm
1%

1 2

D3

RSVD_D3

K46

RSVD_K46

K45

RSVD_K45

AL25

RSVD_AL25

AL27

RSVD_AL27

C71

RSVD_C71

B70

RSVD_B70

F60

RSVD_F60

A52

RSVD_A52

1

BA70

T0901@

RSVD_TP_BA70

1

BA68

T0902@

RSVD_TP_BA68

J71

RSVD_J71

J68

RSVD_J68

F65

VSS_F65

G65

VSS_G65

F61

RSVD_F61

E61

RSVD_E61

SKL-ULT

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

VSS_AY71

RSVD_TP_AW71
RSVD_TP_AW70

PROC_SELECT#

BB68

1

T0903 @

BB69

1

T0904 @

1

AK13

T0905 @

1

AK12

T0906 @

BB2
BA3

AU5

TP5

AT5

TP6

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

TP4

A69
B69

AY3

D71
C70

C54
D54

AY4

TP1

BB3

TP2

AY71
AR56

ZVM#

1

AW71

T0907 @

1

AW70

T0908 @

AP56

MSM#

R0905

C64

1 2

100KOhm

@

0402

SL0901

@

2 1

0402

SL0902

@

2 1

+VCCST

XTAL 24MHz

XTAL24_R_IN

U0301T

SPARE

AW69

RSVD_AW69

AW68

RSVD_AW68

AU56

RSVD_AU56

AW48

RSVD_AW48

C7

RSVD_C7

U12

RSVD_U12

U11

RSVD_U11

H11

RSVD_H11

REV = <REV>

SKL-ULT

R0904

21

@

0402

2nd: 07009-00063100/07009-00063200

RSVD_F6
RSVD_E3

RSVD_C11

RSVD_B11

RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

F6
E3
C11

XTAL24_R_IN

B11
A11
D12
C12
F52

C0901

12

X0902

24Mhz

12

R0903

1MOhm

U42

XTAL24_R_OUT_X1XTAL24_R_OUT

27PF/50V

U42

4

2

U42

C0903

1 3

12

27PF/50V

GND

U42

CFG STRAPS

CFG4

CFG4

1 2

R0901 1KOhm

01 NOTE

eDP ENABLEDISABLE ENABLE

BOM

Title :

Size

Custom

Date: Sheet

CPU_CFG,RSVD

Dept.:

Friday, April 27, 2018

Project Name

X441UBR

ASUSTeK COMPUTER INC.

Engineer:

SZ/EE

Rev

R2.1

102

of

9

CPU - VCC DECAPS- Underneath the package

+VCCCORE

12

12

12

C1030

C1031

4.7UF/6.3V

4.7UF/6.3V

12

12

12

C1046

C1047

C1048

4.7UF/6.3V

1UF/6.3V /X

1UF/6.3V

@

12

C1068

1UF/6.3V

@

CPU - VCC DECAPS- Place close to the package

CAP above 22UF move to PWR page

Disable: C1034, C1044, C1046, C1048, C1062, C1064, C1065, C1067

C1034

@

1UF/6.3V

12

C1062

1UF/6.3V

/X

12

C1041

4.7UF/6.3V

12

12

12

C1064

C1065

@

C1063

1UF/6.3V

1UF/6.3V

4.7UF/6.3V

@

換為0402_4.7uF: C1030, C1031, C1041, C1047, C1063, C1066

12

C1044

@

1UF/6.3V

12

12

C1067

C1066

1UF/6.3V

4.7UF/6.3V

/X

CAP option check OK

Project Name

X441UBR

Title :

CPU_POWER_CAP

Size

Dept.:

Engineer:

ASUSTeK COMPUTER INC.

C

Date: Sheet of

Friday, April 27, 2018

SZ/EE

10

Rev

R2.1

102

1 2
3 4
5 6
7 8

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

36Ohm
36Ohm
36Ohm
36Ohm

36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm

36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm

36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm
36Ohm

1 2

51.1Ohm

+VTT

12

C1302

RN1307A

10UF/6.3V

RN1307B

@

RN1307C
RN1307D

GND
RN1301A
RN1301B
RN1301C
RN1301D
RN1302A
RN1302B
RN1302C
RN1302D

RN1303A
RN1303B
RN1303C
RN1303D
RN1304A
RN1304B
RN1304C
RN1304D

RN1305A
RN1305B
RN1305C
RN1305D
RN1306A
RN1306B
RN1306C
RN1306D

C1304

12

M_A_CLK_DDR0_R

0.01UF/25V

+1.2V

R1306

1 2

1 2

R1305

M_A_CLK_DDR0 4,14

36OHM

12

C1301

3300PF/50V

R1303

M_A_CLK_DDR#0 4,14

36OHM

@

Title :

DDR4_TERMINATION_A

Engineer:

Size Project Name

X441UBR

C

Date: Sheet

SZ/EE

Rev

R2.1

of

13 102Friday, April 27, 2018

M_A_A[13:0]4,14

M_A_ODT04,14
M_A_CKE04,14
M_A_WE#4,14
M_A_CS#04,14

M_A_A7
M_A_A0
M_A_A6

M_A_A11

M_A_ACT#4,14
M_A_BG04,14
M_A_CAS#4,14
M_A_RAS#4,14

M_A_A10

M_A_BA14,14

M_A_BA1

M_A_A4

M_A_BA04,14

M_A_A8
M_A_A2
M_A_A13

M_A_PAR4,14

M_A_A3
M_A_A1

M_A_A12

M_A_A9

M_A_A5

M_A_ALERT#4,14

M_A_VREFCA

12

C1411

2.2UF/10V

GND

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12

M_A_A13

M_A_WE#
M_A_CAS#
M_A_RAS#

M_A_BA0
M_A_BA1

M_A_BG0

M_A_CLK_DDR0
M_A_CLK_DDR#0

M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_ACT#

+1.2V

M_A_ALERT#

M_A_PAR

DDR4_DRAMRST#

ZQ_U1401

+2.5V

TEN_U1401

8Gb (512*16): Micron (03012-00020500), Hynix (03012-00020300)
16Gb (1024*16): 三星 (03012-00040100), Micron (03012-00040200

Onboard Memory Source

Capacity

ASUS P/N

03012-00010000

03012-00010200

Vendor

4Gb 512X8

HYNIX/H5AN4G8NAFR-TFC

4Gb 512X8

SAMSUNG/K4A4G085WE-BCPB

M_A_DQS[7:0] 4
M_A_DQS#[7:0] 4
M_A_DQ[63:0] 4

M_A_A[13:0]4,13

M_A_BA[1:0]4,13

M_A_BG04,13
M_A_CLK_DDR#04,13
M_A_CLK_DDR04,13
M_A_CKE04,13
M_A_CS#04,13
M_A_ODT04,13
M_A_RAS#4,13
M_A_WE#4,13
M_A_CAS#4,13
M_A_ALERT#4,13
M_A_PAR4,13
M_A_ACT#4,13

DDR4_DRAMRST#4,17

R1402 240Ohm 1%

ZQ_U1401

R1404 240Ohm 1%

ZQ_U1402

R1401 240Ohm 1%

ZQ_U1403

ZQ_U1404

R1403 240Ohm 1%

1 2

R1405 1KOhm 1%

TEN_U1401

1 2

R1406 1KOhm 1%

TEN_U1402

1 2

R1407 1KOhm 1%

TEN_U1403

1 2

R1408 1KOhm 1%

TEN_U1404

M_A_VREFCA

U1402

U1401

A3

DQ8

B8

M1

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8
L2
M8
L8

N2
N8

M2

K7
K8

K2

K3
L7
L3
P9

E2
E7

T3

P1

F9

N9

B1
R9

T7

12

12

12

12

VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_n
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1

BG0

CK_t
CK_c

CKE

ODT
CS_n
ACT_n
ALERT_n

NF/UDM_n/UDBI_n
NF/LDM_n/LDBI_n

PAR

RESET_n

ZQ

TEN

VPP1
VPP2

NC

MT40A512M16JY-083E

/X

M_A_DQ7

DQ9

C3

M_A_DQ1

DQ10

C7

M_A_DQ3

DQ11

C2

M_A_DQ4

DQ12

C8

M_A_DQ6

DQ13

D3

M_A_DQ0

DQ14

D7

M_A_DQ5

DQ15

M_A_DQ2

B7

UDQS_t

A7

M_A_DQS0

UDQS_c

M_A_DQS#0

G2

DQ0

F7

M_A_DQ12

DQ1

H3

M_A_DQ10

DQ2

H7

M_A_DQ9

DQ3

H2

M_A_DQ14

DQ4

H8

M_A_DQ8

DQ5

J3

M_A_DQ15

DQ6

J7

M_A_DQ13

DQ7

M_A_DQ11

G3

LDQS_t

F3

M_A_DQS1

LDQS_c

M_A_DQS#1

B3

VDD1

B9

VDD2

D1

VDD3

G7

VDD4

J1

VDD5

M1

J9

VDD6

L1

VDD7

L9

VDD8

R1

VDD9

T9

VDD10

A1

VDDQ1

A9

VDDQ2

C1

VDDQ3

D9

VDDQ4

F2

VDDQ5

F8

VDDQ6

G1

VDDQ7

G9

VDDQ8

J2

VDDQ9

J8

VDDQ10

B2

VSS1

E1

VSS2

E9

VSS3

G8

VSS4

K1

VSS5

K9

VSS6

M9

VSS7

N1

VSS8

T1

VSS9

A2

VSSQ1

A8

VSSQ2

C9

VSSQ3

D2

VSSQ4

D8

VSSQ5

E3

VSSQ6

E8

VSSQ7

F1

VSSQ8

H1

VSSQ9

H9

VSSQ10

+1.2V

N/A

C1442

C1443

1 2

1 2

1UF/6.3V

1UF/6.3V

@

Close U1401 Close U1402 Close U1403

GND GND

+2.5V

C1431

C1432

1 2

1 2

1UF/6.3V

1UF/6.3V

@

Close U1401

GND

GND

12

C1410

2.2UF/10V

GND

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12

M_A_A13

+1.2V

M_A_WE#
M_A_CAS#
M_A_RAS#

M_A_BA0
M_A_BA1

M_A_BG0

M_A_CLK_DDR0
M_A_CLK_DDR#0

M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_ACT#

+1.2V

M_A_ALERT#

M_A_PAR

DDR4_DRAMRST#

ZQ_U1402

+2.5V

TEN_U1402

GND

+1.2V

C1402

C1444

C1445

C1403

C1404

1 2

1 2

1 2

1 2

n/a

1 2

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

@

+2.5V

1 2

Close U1402

GND

+2.5V

+2.5V

C1435

C1434

C1433

C1436

1 2

1 2

1 2

N/A

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

N/A

@

Close U1403

GND

GND

+VTT

+VTT

C1418

C1499

1 2

1 2

1UF/6.3V

1UF/6.3V

@

Close U1403

GND

GND

A3

DQ8

B8

M1

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7

M3

T2

M7

T8
L2

M8

L8

N2
N8

M2

K7
K8

K2

K3
L7
L3
P9

E2
E7

T3

P1

F9

N9

B1
R9

T7

C1405

1 2

N/A

1UF/6.3V

C1438

1 2

@
1UF/6.3V

Close U1404

C1421

1 2

1UF/6.3V

Close U1404

N/A

1 2

VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_n
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1

BG0

CK_t
CK_c

CKE

ODT
CS_n
ACT_n
ALERT_n

NF/UDM_n/UDBI_n
NF/LDM_n/LDBI_n

PAR

RESET_n

ZQ

TEN

VPP1
VPP2

NC

MT40A512M16JY-083E

/X

C1439

1 2

1UF/6.3V

C1420

1UF/6.3V

M_A_DQ17

DQ9

C3

M_A_DQ16

DQ10

C7

M_A_DQ23

DQ11

C2

M_A_DQ18

DQ12

C8

M_A_DQ22

DQ13

D3

M_A_DQ20

DQ14

D7

M_A_DQ19

DQ15

M_A_DQ21

B7

UDQS_t

A7

M_A_DQS2

UDQS_c

M_A_DQS#2

G2

DQ0

F7

M_A_DQ27

DQ1

H3

M_A_DQ24

DQ2

H7

M_A_DQ30

DQ3

H2

M_A_DQ28

DQ4

H8

M_A_DQ26

DQ5

J3

M_A_DQ29

DQ6

J7

M_A_DQ25

DQ7

M_A_DQ31

G3

LDQS_t

F3

M_A_DQS3

LDQS_c

M_A_DQS#3

B3

VDD1

B9

VDD2

D1

VDD3

G7

VDD4

J1

VDD5

M2

J9

VDD6

L1

VDD7

L9

VDD8

R1

VDD9

T9

VDD10

A1

VDDQ1

A9

VDDQ2

C1

VDDQ3

D9

VDDQ4

F2

VDDQ5

F8

VDDQ6

G1

VDDQ7

G9

VDDQ8

J2

VDDQ9

J8

VDDQ10

B2

VSS1

E1

VSS2

E9

VSS3

G8

VSS4

K1

VSS5

K9

VSS6

M9

VSS7

N1

VSS8

T1

VSS9

A2

VSSQ1

A8

VSSQ2

C9

VSSQ3

D2

VSSQ4

D8

VSSQ5

E3

VSSQ6

E8

VSSQ7

F1

VSSQ8

H1

VSSQ9

H9

VSSQ10

+1.2V

+1.2V

C1409

C1408

C1407

C1415

C1406

C1416

1 2

1 2

1 2

1 2

1 2

1 2

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

1UF/6.3V

@

@

@

GND

Close U1404

GND

M_A_VREFCA

U1403

A3

DQ8

B8

M1

12

C1413

2.2UF/10V

P3

GND

P7

M_A_A0

R3

M_A_A1

N7

M_A_A2

N3

M_A_A3

P8

M_A_A4

P2

M_A_A5

R8

M_A_A6

R2

M_A_A7

R7

M_A_A8

M3

M_A_A9
M_A_A10

M7

M_A_A11

+1.2V

GND

C1414

1 2

N/A

1UF/6.3V

@

M_A_A12

M_A_A13

M8

M_A_WE#
M_A_CAS#
M_A_RAS#

N2
N8

M_A_BA0
M_A_BA1

M2

M_A_BG0

K7
K8

M_A_CLK_DDR0
M_A_CLK_DDR#0

K2

M_A_CKE0

K3

M_A_ODT0
M_A_CS#0

P9

M_A_ACT#

+1.2V

M_A_ALERT#

E2
E7

M_A_PAR

P1

DDR4_DRAMRST#

ZQ_U1403

N9

+2.5V

TEN_U1403

B1
R9

+1.2V

C1417

1 2

1UF/6.3V

N/A

C1427

C1426

12

12

12

nbs_c0603_h37_000s

nbs_c0603_h37_000s

nbs_c0603_h37_000s

10UF/6.3V

10UF/6.3V

N/A

GND

+2.5V

C1446

C1440

C1437

12

12

12

12

nbs_c0603_h37_000s

nbs_c0603_h37_000s

nbs_c0603_h37_000s

@

nbs_c0603_h37_000s

@

10UF/6.3V

10UF/6.3V

10UF/6.3V

@

GND

+VTT

C1424

12

12

@

C1423

nbs_c0603_h37_000s

2.2UF/10V
10UF/6.3V

GND

T2

T8
L2

L8

L7
L3

T3

F9

T7

C1430

C1428

10UF/6.3V

10UF/6.3V

VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_n
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1

BG0

CK_t
CK_c

CKE

ODT
CS_n
ACT_n
ALERT_n

NF/UDM_n/UDBI_n
NF/LDM_n/LDBI_n

PAR

RESET_n

ZQ

TEN

VPP1
VPP2

NC

MT40A512M16JY-083E

/X

nbs_c0603_h37_000s

nbs_c0603_h37_000s

N/A

M_A_DQ39

DQ9

C3

M_A_DQ33

DQ10

C7

M_A_DQ32

DQ11

C2

M_A_DQ34

DQ12

C8

M_A_DQ38

DQ13

D3

M_A_DQ35

DQ14

D7

M_A_DQ37

DQ15

M_A_DQ36

B7

UDQS_t

A7

M_A_DQS4

UDQS_c

M_A_DQS#4

G2

DQ0

F7

M_A_DQ41

DQ1

H3

M_A_DQ40

DQ2

H7

M_A_DQ43

DQ3

H2

M_A_DQ42

DQ4

H8

M_A_DQ46

DQ5

J3

M_A_DQ45

DQ6

J7

M_A_DQ47

DQ7

M_A_DQ44

G3

LDQS_t

F3

M_A_DQS5

LDQS_c

M_A_DQS#5

B3

VDD1

B9

VDD2

D1

VDD3

G7

VDD4

J1

VDD5

M3

J9

VDD6

L1

VDD7

L9

VDD8

R1

VDD9

T9

VDD10

A1

VDDQ1

A9

VDDQ2

C1

VDDQ3

D9

VDDQ4

F2

VDDQ5

F8

VDDQ6

G1

VDDQ7

G9

VDDQ8

J2

VDDQ9

J8

VDDQ10

B2

VSS1

E1

VSS2

E9

VSS3

G8

VSS4

K1

VSS5

K9

VSS6

M9

VSS7

N1

VSS8

T1

VSS9

A2

VSSQ1

A8

VSSQ2

C9

VSSQ3

D2

VSSQ4

D8

VSSQ5

E3

VSSQ6

E8

VSSQ7

F1

VSSQ8

H1

VSSQ9

H9

VSSQ10

C1429

12

N/A

10UF/6.3V

C1441

12

@

10UF/6.3V

M_A_VREFCA

U1404

A3

DQ8

B8

M1

12

C1412

2.2UF/10V

P3

GND

P7

M_A_A0

R3

M_A_A1

N7

M_A_A2

N3

M_A_A3

P8

M_A_A4

P2

M_A_A5

R8

M_A_A6

R2

M_A_A7

R7

M_A_A8

M3

M_A_A9

T2

M_A_A10

M7

M_A_A11

T8

M_A_A12

M_A_A13

+1.2V

GND

M8

M_A_WE#
M_A_CAS#
M_A_RAS#

N2
N8

M_A_BA0
M_A_BA1

M2

M_A_BG0

K7
K8

M_A_CLK_DDR0
M_A_CLK_DDR#0

K2

M_A_CKE0

K3

M_A_ODT0
M_A_CS#0

P9

M_A_ACT#

+1.2V

M_A_ALERT#

E2
E7

T3

M_A_PAR

P1

DDR4_DRAMRST#

F9

ZQ_U1404

N9

+2.5V

TEN_U1404

B1
R9

T7

L2

L8

L7
L3

VREFCA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_n
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1

BG0

CK_t
CK_c

CKE

ODT
CS_n
ACT_n
ALERT_n

NF/UDM_n/UDBI_n
NF/LDM_n/LDBI_n

PAR

RESET_n

ZQ

TEN

VPP1
VPP2

NC

MT40A512M16JY-083E

/X

M_A_DQ55

DQ9

C3

M_A_DQ53

DQ10

C7

M_A_DQ54

DQ11

C2

M_A_DQ48

DQ12

C8

M_A_DQ50

DQ13

D3

M_A_DQ52

DQ14

D7

M_A_DQ51

DQ15

M_A_DQ49

B7

UDQS_t

A7

M_A_DQS6

UDQS_c

M_A_DQS#6

G2

DQ0

F7

M_A_DQ58

DQ1

H3

M_A_DQ60

DQ2

H7

M_A_DQ63

DQ3

H2

M_A_DQ56

DQ4

H8

M_A_DQ62

DQ5

J3

M_A_DQ61

DQ6

J7

M_A_DQ59

DQ7

M_A_DQ57

+1.2V

G3

LDQS_t

F3

M_A_DQS7

LDQS_c

M_A_DQS#7

B3

VDD1

B9

VDD2

D1

VDD3

G7

VDD4

J1

VDD5

M4

J9

VDD6

L1

VDD7

L9

VDD8

R1

VDD9

T9

VDD10

A1

VDDQ1

A9

VDDQ2

C1

VDDQ3

D9

VDDQ4

F2

VDDQ5

F8

VDDQ6

G1

VDDQ7

G9

VDDQ8

J2

VDDQ9

J8

VDDQ10

B2

VSS1

E1

VSS2

E9

VSS3

G8

VSS4

K1

VSS5

K9

VSS6

M9

VSS7

N1

VSS8

T1

VSS9

A2

VSSQ1

A8

VSSQ2

C9

VSSQ3

D2

VSSQ4

D8

VSSQ5

E3

VSSQ6

E8

VSSQ7

F1

VSSQ8

H1

VSSQ9

H9

VSSQ10

GND

Title :

DDR4_ON-BOARD_A_L32

Engineer:

SZ/EE

Size Project Name

D

Date: Sheet

X441UBR

Rev

R2.1

of

14 102Friday, April 27, 2018

M_B_VREFCA

12

12

C1704

C1701

0.1UF/16V

4.7UF/6.3V

GND

GND

Place close to SO-DIMM

Chip ID lines for 3DS for 2and4 high stack

'EVENT_N': INDICATES THERMAL EVENT ON DIMM.
NON-ECC DIMM: NOT CONNECTED

EVENT# ON ECC DIMM: KEEP A PULL UP IF NO PIN IN PCH

M_B_DQ[63:0] 4

M_B_CLK_DDR04
M_B_CLK_DDR#04
M_B_CLK_DDR14
M_B_CLK_DDR#14

M_B_CKE04
M_B_CKE14

M_B_CS#04
M_B_CS#14

M_B_ODT04
M_B_ODT14

M_B_BG04
M_B_BG14
M_B_BA04
M_B_BA14
M_B_A[13:0]4

M_B_WE#4
M_B_CAS#4
M_B_RAS#4

M_B_ACT#4

M_B_PAR4

M_B_ALERT#4

DDR4_DRAMRST#4,14

SMB_DATA_S35,47
SMB_CK_S35,47

+1.2V

1

T1702

1

@

T1701

@

M_B_DIMM0_SA2
M_B_DIMM0_SA1
M_B_DIMM0_SA0

DQ0

CK0_T

7

139

M_B_DQ0

DQ1

CK0_C

20

138

M_B_DQ4

D0

DQ2

CK1_T

21

140

M_B_DQ2

DQ3

CK1_C

4

M_B_DQ7

DQ4

3

109

M_B_DQ1

DQ5

CKE0

16

110

M_B_DQ5

DQ6

CKE1

17

M_B_DQ3

DQ7

28

149

M_B_DQ6

DQ8

S0*

29

157

M_B_DQ10

DQ9

S1*

41

M_B_DQ11

DQ10

42

155

M_B_DQ12

DQ11

ODT0

24

161

M_B_DQ9

D1

DQ12

ODT1

25

M_B_DQ15

DQ13

38

115

M_B_DQ14

DQ14

BG0

37

113

M_B_DQ8

DQ15

BG1

50

150

M_B_DQ13

DQ16

BA0

49

145

M_B_DQ19

DQ17

BA1

62

M_B_DQ17

DQ18

63

144

M_B_DQ23

D2

DQ19

A0

46

133

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

For ECC

M_B_DIMM0_S2
M_B_DIMM0_S3

M_B_DQ18

DQ20

A1

45

132

M_B_DQ21

DQ21

A2

58

131

M_B_DQ16

DQ22

A3

59

128

M_B_DQ22

DQ23

A4

70

126

M_B_DQ20

DQ24

A5

71

127

M_B_DQ27

DQ25

A6

83

122

M_B_DQ24

DQ26

A7

84

125

M_B_DQ30

D3

DQ27

A8

66

121

M_B_DQ28

DQ28

A9

67

146

M_B_DQ29

DQ29

A10_AP

79

120

M_B_DQ25

DQ30

A11

80

119

M_B_DQ26

DQ31

A12

174

158

M_B_DQ31

DQ32

A13

173

151

M_B_DQ37

DQ33

A14_WE*

187

156

M_B_DQ32

DQ34

A15_CAS*

186

152

M_B_DQ35

D4

DQ35

A16_RAS*

170

M_B_DQ34

DQ36

169

M_B_DQ36

DQ37

183

114

M_B_DQ33

DQ38

ACT*

182

M_B_DQ38

DQ39

195

143

M_B_DQ39

DQ40

PARITY

194

116

M_B_DQ40

DQ41

ALERT*

207

134

M_B_DQ41

DQ42

EVENT*

208

108

M_B_DQ42

D5

DQ43

RESET*

191

M_B_DQ46

DQ44

190

164

M_B_DQ45

DQ45

VREFCA

203

M_B_DQ44

DQ46

204

254

M_B_DQ43

DQ47

SDA

216

253

M_B_DQ47

DQ48

SCL

215

M_B_DQ52

DQ49

228

166

M_B_DQ48

DQ50

SA2

229

260

M_B_DQ51

D6

DQ51

SA1

211

256

M_B_DQ53

DQ52

SA0

212

M_B_DQ50

DQ53

224

M_B_DQ49

DQ54

225

M_B_DQ55

DQ55

237

92

M_B_DQ54

DQ56

CB0_NC

236

91

M_B_DQ56

DQ57

CB1_NC

249

101

M_B_DQ59

DQ58

CB2_NC

250

105

M_B_DQ61

D7

DQ59

CB3_NC

232

88

M_B_DQ63

DQ60

CB4_NC

233

87

M_B_DQ57

DQ61

CB5_NC

245

100

M_B_DQ58

DQ62

CB6_NC

246

104

M_B_DQ60

DQ63

CB7_NC

M_B_DQ62

M_B_DQS[7:0] 4

13

12

DQS0_T

DM0*/DBI0*

34

33

M_B_DQS0

DQS1_T

DM1*/DBI1*

55

54

M_B_DQS1

DQS2_T

DM2*/DBI2*

76

75

M_B_DQS2

DQS3_T

DM3*/DBI3*

179

178

M_B_DQS3

DQS4_T

DM4*/DBI4*

200

199

M_B_DQS4

DQS5_T

DM5*/DBI5*

221

220

M_B_DQS5

DQS6_T

DM6*/DBI6*

242

241

M_B_DQS6

DQS7_T

DM7*/DBI7*

97

96

M_B_DQS7

DQS8_T

DM8*/DBI8*

162

S2*/C0

165

S3*/C1

DDR4_DIMM_260P

M_B_DQS#[7:0] 4

11

DQS0_C

32

M_B_DQS#0

DQS1_C

53

M_B_DQS#1

DQS2_C

74

M_B_DQS#2

DQS3_C

177

M_B_DQS#3

DQS4_C

198

M_B_DQS#4

DQS5_C

219

M_B_DQS#5

DQS6_C

240

M_B_DQS#6

DQS7_C

95

M_B_DQS#7

DQS8_C

12002-00082600

J1701B

163

VDD19

160

VDD18

159

VDD17

154

VDD16

153

VDD15

148

VDD14

147

VDD13

142

VDD12

141

VDD11

136

VDD10

135

VDD9

130

VDD8

129

VDD7

124

VDD6

123

VDD5

118

VDD4

117

VDD3

112

VDD2

111

VDD1

251

VSS1

247

VSS2

243

VSS3

239

VSS4

235

VSS5

231

VSS6

227

VSS7

223

VSS8

217

VSS9

213

VSS10

209

VSS11

205

VSS12

201

VSS13

197

VSS14

193

VSS15

189

VSS16

185

VSS17

181

VSS18

175

VSS19

171

VSS20

167

VSS21

107

VSS22

103

VSS23

99

VSS24

93

VSS25

89

VSS26

85

VSS27

81

VSS28

77

VSS29

73

VSS30

69

VSS31

65

VSS32

61

VSS33

57

VSS34

51

VSS35

47

VSS36

43

VSS37

39

VSS38

35

VSS39

31

VSS40

27

VSS41

23

VSS42

19

VSS43

15

VSS44

9

VSS45

5

VSS46

1

VSS47

DDR4_DIMM_260P

GND GND

SWAP

J1701A

8

137

+2.5V+1.2V

+3VS

+VTT

258

VTT

259

VPP2

257

VPP1

255

VDDSPD

12

C1705

0.1UF/10V

GND

263

NP_NC1

264

NP_NC2

261

MT1

262

MT2

252

VSS48

248

VSS49

244

VSS50

238

VSS51

234

VSS52

230

VSS53

226

VSS54

222

VSS55

218

VSS56

214

VSS57

210

VSS58

206

VSS59

202

VSS60

196

VSS61

192

VSS62

188

VSS63

184

VSS64

180

VSS65

176

VSS66

172

VSS67

168

VSS68

106

VSS69

102

VSS70

98

VSS71

94

VSS72

90

VSS73

86

VSS74

82

VSS75

78

VSS76

72

VSS77

68

VSS78

64

VSS79

60

VSS80

56

VSS81

52

VSS82

48

VSS83

44

VSS84

40

VSS85

36

VSS86

30

VSS87

26

VSS88

22

VSS89

18

VSS90

14

VSS91

10

VSS92

6

VSS93

2

VSS94

Place close to SO-DIMM

GND GND GND

Place close to SO-DIMM Socket
(+VTT Pin)

+3VS+3VS+3VS

R1702

R1703

R1704

@

@

10KOhm

10KOhm

10KOhm

1 2

1 2

1 2

M_B_DIMM0_SA2
M_B_DIMM0_SA1
M_B_DIMM0_SA0

R1701

R1705

R1706

@

10KOhm

10KOhm

10KOhm

1 2

1 2

1 2

WRITE ADDRESS: 0XA4

+VTT

C1711

nbs_c0603_h37_000s

1 2

@

1UF/6.3V

GND

GND

+1.2V

@

nbs_c0603_h37_000s

10UF/6.3V

@

12

C1726

@

10UF/6.3V

@

GND

12

+

CE1701
330UF/2V
11020-0035Z000

GND

12

C1712
@

nbs_c0603_h37_000s

12

C1708
1UF/6.3V

12

C1717
1UF/6.3V

nbs_c0603_h37_000s

Place close to SO-DIMM Socket (VDD Pin)

nbs_c0603_h37_000s

12

12

12

C1707

C1715

10UF/6.3V

@

nbs_c0603_h37_000s

@

10UF/6.3V

GNDGNDGND GND

12

12

12

C1718

C1702

N/A

@

1UF/6.3V

1UF/6.3V

GNDGNDGND GND GNDGNDGNDGND

+2.5V

nbs_c0603_h37_000s

12

12

C1710

C1725

10UF/6.3V@

10UF/6.3V@

Place close to SO-DIMM Socket
(+VPP Pin)

nbs_c0603_h37_000s

12

12

C1719

C1722

N/A

@

nbs_c0603_h37_000s

10UF/6.3V

10UF/6.3V

GND

GND

12

12

C1723

C1714

1UF/6.3V

1UF/6.3V

N/A

12

12

C1727

C1721

1UF/6.3V

1UF/6.3V

N/A

GNDGNDGND GND

nbs_c0603_h37_000s

12

12

C1703

C1716

C1706

10UF/6.3V

10UF/6.3V

10UF/6.3V

nbs_c0603_h37_000s

@

@

N/A

GNDGND

12

12

C1720

C1713

C1724

N/A

1UF/6.3V

1UF/6.3V

1UF/6.3V

Title :

DDR4_SO-DIMM_1

Engineer:

X441UBR

SZ/EE

Rev

R2.1

of

17 102Friday, April 27, 2018

Size Project Name

D

Date: Sheet

All Vref trace must be 20 mils width

+1.2V M_B_VREFCA

R1822

1KOhm

1 2

SB_DIMM_VREFCA4

SB_DIMM_VREFCA_C

1 2

R1807 2.2Ohm

1%

12

C1801

0.022UF/16V
R1820

1KOhm

+V_VREF_RC1

12

R1806

1 2

24.9Ohm

1%

Close to SO-DIMM Close to Memory Down

GND

SA_DIMM_VREFCA4

12

C1802

4.7UF/6.3V

SA_DIMM_VREFCA_C

2.7 change to 2.2

12

C1803

0.022UF/16V

+V_VREF_CA_RC

12

R1810

24.9Ohm
1%

R1812

1 2

2.7Ohm

Date: Sheet

+1.2V

R1821

1.8KOHM

1%

1 2

R1818

1.8KOHM

1%

1 2

GND

Size Project Name

C

M_A_VREFCA

X441UBR

Title :

DDR4 CA VOLTAGE

Engineer:

SZ/EE

Rev

R2.1

of

18 102Friday, April 27, 2018

U0301I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

REV = <REV>

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL-ULT

EMMC

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD

EMMC_RCOMP

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

R2002 100Ohm@

1 2

R2001 200Ohm@

12

GND

GND

BOM

Title :

Size

B

Date: Sheet

Friday, April 27, 2018

Project Name

X441UBR

CPU_PCH_CSI2,EMMC

Dept.:

ASUSTeK COMPUTER INC.

Engineer:

SZ/EE

Rev

R2.1

102

of

20

U0301F

LPSS ISH

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

PCH_GPPB18

21

SL2138@

BT_ON_PCH#53

0402

GPU_EVENT#76
DGPU_FB_CLAMP_GPIO76,77

DGPU_PWROK70,77 TOUCHPAD_INTR# 31

GPU_RST#70
DGPU_PWR_EN#77

No Reboot

PCH_GPPB18

NOTE: Enable No Reboot
PCH will disable the TCO
Timer system reboot feature.
This function is useful when running ITP/XDP.

PCH_GPPB18: strap:weak internal pd 20K
default as GPO

PU Enable

PD Disable

AM5

GPP_B19/GSPI1_CS#

AN7

GSPI1_CS_R#

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

PCH_GPPB22

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

I2C1_DSA_PCH

TP

GPP_C19/I2C1_SCL

I2C1_DCL_PCH

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

REV = <REV>

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

SKL-ULT

+3VSUS

12

R2125

10KOhm

@

12

R2149

1KOhm

@

GPP_D13/ISH_UART0_RXD

GPP_D14/ISH_UART0_TXD

Boot BIOS Strap Bit BBS

+3VSUS

12

R2160

10KOhm

@

PCH_GPPB22

12

R2161

1KOhm

@

PCH_GPPB22: weal internal pull down 20k

PU LPC

PD SPI (Default)

GPP_D16

GPP_C14

GPP_C15

GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL

/SML0BDATA/I2C4B_SDA
/SML0BCLK/I2C4B_SCL

GPP_D15/ISH_UART0_RTS#

/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD

/UART1_RTS#/ISH_UART1_RTS#
/UART1_CTS#/ISH_UART1_CTS#

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

P2

GPP_D9

P3

PCB_ID0

GPP_D10

P4

PCB_ID1

GPP_D11

P1

PCB_ID2

GPP_D12

M4
N3

N1
N2

AD11
AD12

U1
U2

TOUCHPAD_INTR#

U3
U4

AC1
AC2

DIMM_SEL0

AC3

DIMM_SEL1

AB4

DIMM_SEL2

AY8
BA8
BB7
BA7
AY7
AW7
AP13

+3VS

34

12

RN2101B

RN2101A

2.2KOHM

2.2KOHM

I2C1_DSA_PCH

I2C1_DCL_PCH

SATA_ODD_PWRGT 61
SATA_ODD_DA# 61

I2C_DAT_PCH 31

I2C_CLK_PCH 31

20150106
Checking
Add for GPU_RST#
& DGPU_PWR_EN#

Main Board

+3VS

R1.1

20150204 Add

R2196 10KOhm

1 2

SATA_ODD_DA#

+3VS

R2122 10KOhm

1 2

DGPU_PWR_EN#

R2102 10KOhm@

1 2

GPU_RST#

R9199 10KOhm/VGA

1 2

R2168 10KOhm@

1 2

GSPI1_CS_R#

+3VS

R2154 10KOhm

1 2

TOUCHPAD_INTR#

+3VS +3VS +3VS

PCB ID0 GPP_D9 PCB ID1 GPP_D10

R2120

10KOhm

/DMIC

1 2

PCB_ID0

PCB_ID1

R2121

10KOhm
/AMIC

1 2

0 0 0

0

DIMM_SEL011DIMM_SEL2DIMM_SEL1

1

00

1

00

<Variant Name>

Project Name

Rev

X441UBR

Title :

CPU_CFG,RSVD,GND

Size

Dept.:

ASUSTeK COMPUTER INC.

D

Date: Sheet

Friday, April 27, 2018

R2.1

Engineer:

EE

102

of

21

Touch Pad ID
GPP_D11

12

R2139
10KOhm

@

R2123

10KOhm

/gc6/@

1 2

PCB_ID2

12

R2140
10KOhm

R2124

@

10KOhm

1 2

/nongc6/@

Onboard Memory PCB-ID:
GPP_C12 => DIMM_SEL0
GPP_C13 => DIMM_SEL1
GPP_C14=> DIMM_SEL2

R2181

10KOhm

/DRAM_4G_hynix

1 2

R2101

10KOhm

/DRAM_4G_SAM

1 2

DRAM Part Number

+3VSUS

03012-00010200 SAMSUNG/K4A4G085WE-BCPB

4G

03012-00010000 HYNIX/H5AN4G8NAFR-TFC

R2183

R2185

10KOhm

10KOhm

03012-00030000 SAMSUNG/K4A8G085WB-BCPB

@

@

1 2

1 2

8G

03012-00030300 HYNIX/H5AN8G8NMFR-TFC

DIMM_SEL2DIMM_SEL1DIMM_SEL0

R2184

R2182

10KOhm

10KOhm

/DRAM_4G

/DRAM_4G

1 2

1 2

HD Audio

RN2201 near PCH

5 6

RN2201C

ACZ_BCLK_AUD

ACZ_SDIN0_AUD

33OHM

3 4

33OHM

1 2

33OHM

7 8

33OHM

C2201 10PF/50V

C2202 15PF/50V

RF requirement

RN2201B
RN2201A
RN2201D

@

1 2

@

1 2

ACZ_BCLK_AUD36
ACZ_SYNC_AUD36
ACZ_RST#_AUD36
ACZ_SDOUT_AUD36

ACZ_SDOUT:(1) PCH: Internal PD 20k
ohm, VoLH =0.4V (2)
ALC3236:VIL<0.4xvddio, VIH>0.6xvddio

ACZ_SDOUT is a signal used for Flash
Descriptor security Override/ME debug mode
HIGH : get overrideen, LOW : disable override--default

ACZ_BCLK_AUD_X1
ACZ_SYNC_AUD_X1
ACZ_RST#_AUD_X1
ACZ_SDOUT_AUD_X1

U0301G

AUDIO

BA22

HDA_SYNC/I2S0_SFRM

ACZ_SYNC_AUD_X1
ACZ_BCLK_AUD_X1
ACZ_SDOUT_AUD_X1

ACZ_SDIN0_AUD36

ACZ_SDIN0_PCH

ACZ_RST#_AUD_X1

@

T2209

GND

+3VSUS_VCCPAZIO

R2201

3.4KOhm

1 2

ACZ_SDOUT_AUD_X1

R2203

330Ohm

1 2

Q2202

3

2N7002K

3

D

1

1

G

S

2

2

PCH_SPI_OV30

GND

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

1

Top-block Swap Override

PCH_GPPB14: weak internal pull down

I2S1_TXD

I2S_SDO_BT

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

REV = <REV>

GPP_B14/SPKR

PCH_GPPB14

SKL-ULT

(invert an upper two 64-KB bolck address on access to SPI and FWH)

+3VSUS

12

R2210

10KOhm

@

PCH_GPPB14

12

R2211

1KOhm

@

PU Enable

PD Disable top swap (default)

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

1 2

R2204 200Ohm

@

AF13

GPP_F23

GND

BOM

Project Name

X441UBR

Title :

CPU_PCH_AUDIO,SDIO,SDXC

Size

Dept.:

ASUSTeK COMPUTER INC.

C

Date: Sheet

Friday, April 27, 2018

Engineer:

Rev

R2.1

EE

102

of

22

PCIENB_RXN[3:0]70
PCIENB_RXP[3:0]70

PCIEG_RXN[3:0]70
PCIEG_RXP[3:0]70

PCIE_RXN_GLAN_C33
PCIE_RXP_GLAN_C33

PCIE_TXN_GLAN33
PCIE_TXP_GLAN33

PCIE_RXN_WLAN53
PCIE_RXP_WLAN53

PCIE_TXN_WLAN53
PCIE_TXP_WLAN53

PCIE RCOMP 100 OHM 1%

PCIE 1

PCIE 2

PCIE 3

PCIE 4

PCIE 5

PCIE 6

PCIE 7/SATA 0

PCIE 8/SATA 1A

PCIE 9

PCIE 10

PCIE 11/SATA 1B

SATA PORT

PORT 0

PORT 1

PORT 2

PORT 3

1 2

CX2304 0.22UF/6.3V

1 2

PCIEG_RXN0

CX2303 0.22UF/6.3V

1 2

CX2306 0.22UF/6.3V

1 2

CX2310 0.22UF/6.3V

PCIEG_RXN1
PCIEG_RXP1 PCIENB_TXP1

1 2

CX2308 0.22UF/6.3V

1 2

CX2305 0.22UF/6.3V

PCIEG_RXN2

1 2

CX2309 0.22UF/6.3V

1 2

CX2307 0.22UF/6.3V

PCIEG_RXN3 PCIENB_TXN3
PCIEG_RXP3

C2309 0.1UF/16V

1 2

C2310 0.1UF/16V

1 2

C2301 0.1UF/16V

1 2

C2302 0.1UF/16V

1 2

SATA_RXN061
SATA_RXP061

SATA_TXN061
SATA_TXP061

SATA_RXN161
SATA_RXP161

SATA_TXN161
SATA_TXP161

1 2

R2316 100Ohm

PCIE USAGE
DEFAULT/OPTION

DGPU

DGPU

DGPU

DGPU

GLAN

WLAN

HDD

ODD

N/A

N/A

N/A

SATA USAGE
DEFAULT/OPTION

HDD

ODD

N/A

N/A

OPTION PCIE

OPTION PCIE

Co-layPCI-E* X1

PCIE_RCOMPN
PCIE_RCOMPP

PCIENB_RXN0
PCIENB_RXP0
PCIENB_TXN0
PCIENB_TXP0PCIEG_RXP0

PCIENB_RXN1
PCIENB_RXP1
PCIENB_TXN1

PCIENB_RXN2
PCIENB_RXP2
PCIENB_TXN2
PCIENB_TXP2PCIEG_RXP2

PCIENB_RXN3
PCIENB_RXP3

PCIENB_TXP3

PCIE_TXN_GLAN_C
PCIE_TXP_GLAN_C

PCIE_TXN_WLAN_C
PCIE_TXP_WLAN_C

U0301H

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

REV = <REV>

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL-ULT

Clock

Port0

Port4

Port5

USB2

SSIC / USB3

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

USB3_1_RXN

USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN

USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2_COMP

USB2_VBUSSENSE

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E8/SATALED#

H8

U3_U3RXDN1 52

G8

U3_U3RXDP1 52

C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9

USB2N_1

AB10

USB2P_1

AD6

USB2N_2

AD7

USB2P_2

AH3

USB2N_3

AJ3

USB2P_3

AD9

USB2N_4

AD10

USB2P_4

AJ1

USB2N_5

AJ2

USB2P_5

AF6

USB2N_6

AF7

USB2P_6

AH1

USB2N_7

AH2

USB2P_7

AF8

USB2N_8

AF9

USB2P_8

AG1

USB2N_9

AG2

USB2P_9

AH7

USB2N_10

AH8

USB2P_10

AB6
AG3

USBCOMP

USB2_ID

AG4

USB2_ID

USB2_VBUSSENSE

A9
C9
D9
B9

J1
J2
J3

H2
H3

DIRECT_ESATA_DETECT_R#

G4

SATA_ODD_PRSNT_R#

H1

+3VS

12

R2302
10KOhm

DIRECT_ESATA_DETECT_R#

12

R2306
10KOhm

@

GND

U3_U3TXDN1 52
U3_U3TXDP1 52

U3_U3RXDN3 54
U3_U3RXDP3 54

U3_U3TXDN3 54
U3_U3TXDP3 54

U3_U3RXDN4 54
U3_U3RXDP4 54

U3_U3TXDN4 54
U3_U3TXDP4 54

USB_PN1 52
USB_PP1 52

USB_PN2 52
USB_PP2 52

USB_PN3 54
USB_PP3 54

USB_PN4 54
USB_PP4 54

USB_PN5 43
USB_PP5 43

USB_PN6 45
USB_PP6 45

USB_PN8 53
USB_PP8 53

R2315 113Ohm

R2321 1KOhm
R2322 1KOhm

1 2
1 2
1 2

+3VS

GND

12

R2303
10KOhm

SATA_ODD_PRSNT_R#

12

R2305
10KOhm

@

USB 3.0 Port

USB 3.0 Port

USB 3.0 TYPEC_A

USB 3.0 TYPEC_B

USB 3.0 Port

USB 3.0 Port

USB 2.0 TYPEC

USB 2.0 TYPEC

CARD READER

CAMERA

WLAN / BT combo

USB 2.0

1

USB2.0 FOR USB3.0 Port

2

USB2.0 FOR USB3.0 Port USB 3.0 Port

3

USB 2.0 TYPEC_A

4

USB 2.0 TYPEC_B

5

CARD READER

6

CAMERA

7

8

WLAN / BT combo

N/A

USB2_ID:OTG ID R2321
PD 1K: No use

Mapping

0

1

2

3

BOM

Title :

Size

C

Date: Sheet

Friday, April 27, 2018

USB 3.0

USB 3.0 Port

USB 3.0 TYPEC_A

USB 3.0 TYPEC_B

CPU_PCH_PCIE,USB,SATA

Dept.:

ASUSTeK COMPUTER INC.

Project Name

X441UBR

Engineer:

Rev

R2.1

EE

102

of

23

To NV VGA

+3VS

CHECK PCIEG CLK

To GLAN

To WLAN

5 6

3 4

1 2

7 8

U0301J

CLOCK SIGNALS

D42

CLK_PCIE_PEG#_PCH70
CLK_PCIE_PEG_PCH70

CK_REQ_P0#70

CLK_PCIE_GLAN#33
CLK_PCIE_GLAN33
CLKREQ_GLAN#33

CLK_PCIE_WLAN#53
CLK_PCIE_WLAN53
CLKREQ_WLAN#53

RN2401C

10KOHM

CK_REQ_P0#

RN2401B

10KOHM

CLKREQ_GLAN#

RN2401A

10KOHM

CLKREQ_WLAN#

RN2401D

10KOHM

CK_REQ_P0#

C42

AR10

B42

A42

AT7

D41

C41

AT8

D40

C40

AT10

B40

A40

AU8

E40

E38

AU7

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
GPP_B6/SRCCLKREQ1#

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
GPP_B7/SRCCLKREQ2#

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
GPP_B8/SRCCLKREQ3#

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

SKL-ULT

REV = <REV>

F43

CLKOUT_ITPXDP_N

E43

CLKOUT_ITPXDP_P

BA17

GPD8/SUSCLK

E37

XTAL24_IN

E35

XTAL24_OUT

E42

XCLK_BIASREF

AM18

RTCX1

AM20

RTCX2

AN18

SRTCRST#

AM16

RTCRST#

RTC CRYSTAL 32.768KHz

1

@

T2402

1

CLK_ITP_BCLK_PCH#
CLK_ITP_BCLK_PCH

XTAL24_IN
XTAL24_OUT

XCLK_BIASREF

RTC_X1
RTC_X2

SRTC_RST#
RTC_RST#

RTC_X1 RTC_X1_X1

RTC_X2

@

T2403

SL2401

21

@

0402

12

R2418

10MOhm

5%

2nd 07009-00112500、07009-00112000

Close E42

+1.0VSUS_PCH

R2417

1 2

2.7KOhm

C2404

1 2

12PF/50V

X2402

32.768KHZ

1 2

07009-00111800

C2405

1 2

12PF/50V

XTAL 24MHz

XTAL24_IN

GND

XTAL24_OUT

GND

12

R2407

1MOhm

/U22

R2409

21

@

0402

XTAL24_OUT_X1

2nd: 07009-00063100/07009-00063200

C2401

12

X2401

24Mhz

27PF/50V

/U22

4

2

C2402

/U22

1 3

12

27PF/50V

GND

/U22

+3VA_RTC

JA - SRTC RST_N
SAVE ME RTC REGISTER -(1-X) DEFAULT
CLEAR ME RTC REGISTER - (1-2)

JB - RTC REST_N
CLEAR CMOS - (1-2)
SAVE CMOS - (1-X) DEFAULT

R2421

R2420

nbs_r0402_h16_000s

20KOhm 1%
nbs_r0402_h16_000s

20KOhm 1%

+3VA

12

12

SRTC_RST#

12

C2407

1UF/6.3V

GND

12

C2406

1UF/6.3V

C

JA

RTC_RST#

1

JRST2402

1

SGL_JUMP

2

@

2

JB

GNDGND

An RC delay circuit with a
time delay in the range of
18 ms to 25 ms should be
provided.

There must not
be a jumper for SRTCRST# pin

R2401

1.8KOHM

1%

1 2

3.3A_RTC_D

12

R2426

40.2KOhm

1%

GND

+3VA_RTC

SL2402

21

@

0402

12

C2403
1UF/6.3V

GND

+V3.3A_RTC GENERATION

BOM

Project Name

X441UBR

Title :

CPU_PCH_CLOCK SIGNALS,RTC

Size

Dept.:

ASUSTeK COMPUTER INC.

C

Date: Sheet

Friday, April 27, 2018

Engineer:

Rev

R2.1

EE

102

of

24

PCH_SUSACK#30

ME_SusPwrDnAck_R

U2502

1

INB

2

INA

3

PLT_RST#

GND4OUTY

74LVC1G08GW

GND

1 2

R2518 0Ohm

PM_SYSPWROK30

ALL_SYSTEM_PWRGD30,58,80

ALL_SYSTEM_PWRGD

PM_PWROK30

PM_RSMRST#30

ME_AC_PRESENT30

D2505: EC pin +3VA

Power failure solution (S0-->G3,S5-->G3):

ALL_SYSTEM_PWRGD

3VA_DSW_PWRGD

PM_PWROK_PCH

U0301K

Main Board

VCCST_PWRGD_PCH58

DPWROK_EC30,58

PM_RSMRST#_PCH DPWROK_R

12

R2501
100KOhm

GND

SL2502@

21

SL2504@

R2541 10KOhm

D2505 1N4148WS

3VA_DSW_PWRGD

3VA_DSW_PWRGD

GND

SUSWARN#30

PCIE_WAKE#33,53

WLAN_ON#53

BUF_PLT_RST# 30,32,33,53,70

UX303CN 0311

21

0402

21

0402

12

@

12

D2501

3

BAT54CW

D2502

3

BAT54CW

R2514 0OHM@

1 2

+3V

5

VCC

/X

R2530 0OHM@

1 2

SL2503@

0402

12

12

R2539

R2538

100KOhm

10KOhm

GND

GND

3VA_DSW_PWRGD30,58,87

C2501

1 2

C2502

0.1UF/16V

@

1 2

C2503

0.1UF/16V

@

1 2

0.1UF/16V

@

SL2501@

0402

2 1

0402

SL2517@

+3VSUS +3VA_DSW

R2505

R2504

1 2

1 2

10KOhm

10KOhm

@

@

2

1

2

1

56Ohm

21

R25540OHM @

12

SL2512 @

ME_SusPwrDnAck_R

21

0402

@

T2504

@

T2503

R2503100KOhm

R2502

1 2

10KOhm

1 2

@

PLT_RST#
PM_SYSRST_R#
PM_RSMRST#_PCH

1

@

T2505

R2507

1 2

H_CPUPWRGD_R

VCCST_PWRGD_R

1

LAN_PWREN

PM_SYSPWROK_PCH

PM_RSMRST#_PCH

ME_AC_PRESENT_PCH

PM_SYSPWROK_PCH
PM_PWROK_PCH

SUSACK_R#

1

PCIE_WAKE#_R

PM_PWROK_PCH

PCH_GPD2#

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL-ULT

REV = <REV>

SYSTEM POWER MANAGEMENT

AN10

GPP_B13/PLTRST#

B5

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

SLP_SUS#

SLP_LAN#

INTRUDER#

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

AM10
AM11

PCH_SLP_S0_R#
SLP_S3_R#
SLP_S4_R#
SLP_S5#

SLP_LAN#
PCH_SLP_WLAN#

PM_SLP_A_R#

ME_AC_PRESENT_PCH

PM_BATLOW_R#

SM_INTRUDER#

MPHY_PWREN

2 1

SL2513 @

PCH_SLP_S0# 30

0402

2 1

SL2514 @

PM_SUSB# 30,58,88

0402

2 1

SL2515 @

PM_SUSC# 30,86

0402

1

@

T2502

PM_SLP_SUS# 30

1

@

T2506

1

T2501 @

1

@

T2580

21

SL2518@

PM_PWRBTN# 30

0402

SLP_LAN#

SUSWARN#

PM_SYSRST_R#

MPHY_PWREN

SM_INTRUDER#

Input:prevent from floating in G3

PM_BATLOW_R#

PCIE_WAKE#

PCH_GPD2#

LAN_PWREN

WLAN_ON#

PM_RSMRST#_PCH

DPWROK_EC

PM_PWROK_PCH

BOM

Project Name

X441UBR

Title :

CPU_PCH_SYS_POWER

Size

Dept.:

ASUSTeK COMPUTER INC.

C

Date: Sheet

Friday, April 27, 2018

1 2

R2527 10KOhm@

1 2

10KOHM

3 4

10KOHM

1 2

R2506 20KOhm

R2559

1 2

300KOhm

R2512 10KOhm

1 2

R2523 10KOhm

1 2

5 6

10KOHM

7 8

10KOHM

Intel Review 1221

R2555 10KOhm@

1 2

3 4

10KOHM

1 2

10KOHM

1 2

R2534 10KOhm@

Engineer:

EE

+3VSUS

RN2501A

RN2501B

+3VA_RTC

+3VA_DSW

RN2501C

RN2501D

RN2502B

RN2502A

Rev

R2.1

102

of

25

20151103
change VCCHDA to 3.3

+1.0VSUS_PCH

U0301O

CPU POWER 4 OF 4

AB19

VCCPRIM_1P0_1

+1.0VSUS_PCH

+1.0VSUS_PCH

+3VSUS_VCCPAZIO

+3VSUS

+1.0VSUS_PCH

+3VSUS

12

10UF/6.3V

+1.0VSUS_PCH

C2612

SL2613@

SL2622@

SL2629@

SL2630@

AB20

VCCPRIM_1P0_2

P18

VCCPRIM_1P0_3

AF18

VCCPRIM_CORE1

AF19

VCCPRIM_CORE2

V20

VCCPRIM_CORE3

V21

VCCPRIM_CORE4

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0_1

L1

VCCMPHYAON_1P0_2

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0_1

L15

VCCAMPHYPLL_1P0_2

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

REV = <REV>

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0_1

AF21

VCCSRAM_1P0_2

T19

VCCSRAM_1P0_3

T20

VCCSRAM_1P0_4

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

SKL-ULT

3.5A

12

12

C2603

1UF/6.3V

N/A

21

SL2605

0402

21

0603

21

0603

21

0603

21

0603

C2615
1UF/6.3V

+1.0VM_VCCAPLLEBB

+1.0VSUS_VCCAPLL

+1.0VSUS_VCCCLK6

+1.0VSUS_VCCCLK2

+1.0VSUS_VCCCLK4

12

C2623
22UF/6.3V

12

C2616
1UF/6.3V

12

C2624

10UF/6.3V

12

C2625

10UF/6.3V

+1.0VM_VCCAMPHYPLL

21

SL2606

0402

12

C2614
1UF/6.3V

+1.0VSUS_PCH +1.0VSUS_VCCCLK5

SL2631@

+1.0VSUS

2.6A

12

C2617

DCPDSW

1UF/6.3V

12

N/A

C2602
1UF/6.3V

12

C2601
1UF/6.3V

+1.0VM_VCCAMPHYPLL

+1.0VSUS_VCCAPLL

+3VDSW_VCCPDSW

+1.8VSUS

R2635

0OHM

12

12

@

+3VSUS

C2627

R2680

1UF/6.3V

0OHM

@

12

+1.0VSUS_PCH

+1.0VM_VCCAPLLEBB

12

C2604
1UF/6.3V

+1.0VSUS_PCH+1.0VSUS

21

SL2623@

0805

12

C7717
1UF/6.3V

@

C2603 near N15

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19
VCCRTC_BB14

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

0603

+VCCPGPP

+VCCPGPP

AK15

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

21

+VCCPGPP

AG15
Y16
Y15
T16
AF16
AD15

V19

T1

AA1

AK17

AK19
BB14

BB10

A14

K19

L21

N20

L19

A10

AN11
AN13

DCPRTC

VCCPRIM_VID0
VCCPRIM_VID1

12

+VCCPGPP

+VCCPGPP

+VCCPGPPF

1 2
1 2

21

+1.0VSUS_VCCCLK4

+1.0VSUS_VCCCLK5

+1.0VSUS_VCCCLK6

@
@

0.09A

0.46A

12

C2607
1UF/6.3V

@

+VCCPGPP

+1.8VSUS

+3VSUS

+3VA_RTC

12

12

12

C2608

C2610

C2609

1UF/6.3V

0.1UF/16V

0.1UF/16V

Place close to the AK19

+3VSUS

21

SL2601@

0402

+3VDSW_VCCPDSW+3VA_DSW

+3VSUS

+3VSUS +VCCPGPP

21

SL2603@

0603

12

C2628
1UF/6.3V

@

+1.8VSUS

21

SL2608@

0.48A

0603

12

C2605
1UF/6.3V

Place close to the AA1

12

+VCCPGPPF

12

C2622

C2613

1UF/6.3V

1UF/6.3V

@

@

BOM

Project Name

X441UBR

Title :

CPU_PCH_POEWR,GND

Size

Dept.:

ASUSTeK COMPUTER INC.

C

Date: Sheet

Friday, April 27, 2018

Engineer:

Rev

R2.1

EE

102

of

26

+3VSUS

+1.0VSUS_PCH

+1.0VSUS_PCH

+1.0VSUS_VCCCLK2

+1.0VSUS_PCH

R2601 10KOhm
R2602 10KOhm

SL2614@

0603

12

12

C2606

C2618

1UF/6.3V

0.1UF/16V

C2626

10UF/6.3V

U0301P

GND 1 OF 3

A5

VSS1

A67

VSS2

A70

VSS3

AA2

VSS4

AA4

VSS5

AA65

VSS6

AA68

VSS7

AB15

VSS8

AB16

VSS9

AB18

VSS10

AB21

VSS11

AB8

VSS12

AD13

VSS13

AD16

VSS14

AD19

VSS15

AD20

VSS16

AD21

VSS17

AD62

VSS18

AD8

VSS19

AE64

VSS20

AE65

VSS21

AE66

VSS22

AE67

VSS23

AE68

VSS24

AE69

VSS25

AF1

VSS26

AF10

VSS27

AF15

VSS28

AF17

VSS29

AF2

SKL-ULT

VSS30

AF4

VSS31

AF63

VSS32

AG16

VSS33

AG17

VSS34

AG18

VSS35

AG19

VSS36

AG20

VSS37

AG21

VSS38

AG71

VSS39

AH13

VSS40

AH6

VSS41

AH63

VSS42

AH64

VSS43

AH67

VSS44

AJ15

VSS45

AJ18

VSS46

AJ20

VSS47

AJ4

VSS48

AK11

VSS49

AK16

VSS50

AK18

VSS51

AK21

VSS52

AK22

VSS53

AK27

VSS54

AK63

VSS55

AK68

VSS56

AK69

VSS57

AK8

VSS58

AL2

VSS59

AL28

VSS60

AL32

VSS61

AL35

VSS62

AL38

VSS63

AL4

VSS64

AL45

VSS65

AL48

VSS66

AL52

VSS67

AL55

VSS68

AL58

VSS69

AL64

VSS70

REV = <REV>

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140

AL65

VSS71

AL66

VSS72

AM13

VSS73

AM21

VSS74

AM25

VSS75

AM27

VSS76

AM43

VSS77

AM45

VSS78

AM46

VSS79

AM55

VSS80

AM60

VSS81

AM61

VSS82

AM68

VSS83

AM71

VSS84

AM8

VSS85

AN20

VSS86

AN23

VSS87

AN28

VSS88

AN30

VSS89

AN32

VSS90

AN33

VSS91

AN35

VSS92

AN37

VSS93

AN38

VSS94

AN40

VSS95

AN42

VSS96

AN58

VSS97

AN63

VSS98

AP10

VSS99

AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

U0301Q

GND 2 OF 3

AT63

VSS141

AT68

VSS142

AT71

VSS143

AU10

VSS144

AU15

VSS145

AU20

VSS146

AU32

VSS147

AU38

VSS148

AV1

VSS149

AV68

VSS150

AV69

VSS151

AV70

VSS152

AV71

VSS153

AW10

VSS154

AW12

VSS155

AW14

VSS156

AW16

VSS157

AW18

VSS158

AW21

VSS159

AW23

VSS160

AW26

VSS161

AW28

VSS162

AW30

VSS163

AW32

VSS164

AW34

VSS165

AW36

VSS166

AW38

VSS167

AW41

VSS168

AW43

VSS169

AW45

VSS170

AW47

SKL-ULT

VSS171

AW49

VSS172

AW51

VSS173

AW53

VSS174

AW55

VSS175

AW57

VSS176

AW6

VSS177

AW60

VSS178

AW62

VSS179

AW64

VSS180

AW66

VSS181

AW8

VSS182

AY66

VSS183

B10

VSS184

B14

VSS185

B18

VSS186

B22

VSS187

B30

VSS188

B34

VSS189

B39

VSS190

B44

VSS191

B48

VSS192

B53

VSS193

B58

VSS194

B62

VSS195

B66

VSS196

B71

VSS197

BA1

VSS198

BA10

VSS199

BA14

VSS200

BA18

VSS201

BA2

VSS202

BA23

VSS203

BA28

VSS204

BA32

VSS205

BA36

VSS206

F68

VSS207

BA45

VSS208

REV = <REV>

VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

U0301R

GND 3 OF 3

F8

VSS278

G10

VSS279

G22

VSS280

G43

VSS281

G45

VSS282

G48

VSS283

G5

VSS284

G52

VSS285

G55

VSS286

G58

VSS287

G6

VSS288

G60

VSS289

G63

VSS290

G66

VSS291

H15

VSS292

H18

VSS293

H71

VSS294

J11

VSS295

J13

VSS296

J25

VSS297

J28

VSS298

J32

VSS299

J35

VSS300

J38

VSS301

J42

VSS302

J8

VSS303

K16

VSS304

K18

VSS305

K22

VSS306

K61

VSS307

K63

VSS308

K64

VSS309

K65

VSS310

K66

VSS311

K67

VSS312

K68

VSS313

K70

VSS314

K71

VSS315

L11

VSS316

L16

VSS317

L17

VSS318

BOM

REV = <REV>

VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348

SKL-ULT

VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359

Project Name

Title :

Size

B

Date: Sheet

Friday, April 27, 2018

X441UBR

CPU_PCH_POEWR,GND

Dept.:

ASUSTeK COMPUTER INC.

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

Rev

R2.1

Engineer:

EE

102

of

27