Asus TERESA Schematics

5

4

TERESA Block Diagram

3

2

PAGE 4

1

FAN + SENSOR

ADM1032ARMZ

D D

LVDS & INV

PAGE 12

CRT

C C

PAGE 13

T/P

PAGE 30

KEYPAD
MATRIX

PAGE 29

INSTANT KEY

PAGE 38

B B

LED Control

PAGE 30,38

EC IT8511E

PAGE 29,30

LPC
33MHz

Azalia

ISA
ROM

PAGE 24

MIC PHONE JACK

PAGE 23

HEADPHONE JACK

PAGE 22

A A

SPEAKER

PAGE 22

5

AUDIO AMP

PAGE 22

Azalia Codec

AD1986A

PAGE 21,22,23

MDC

PAGE 35

4

BTO

PAGE 28

PAGE 28

T2060
4xx,5xx Series

PAGE 2,3

GMCH-M
Calistoga

943GML

B0:02G010009121

PAGE 6,7,8,9,10,11

B0:02G010008811

PAGE
17,18,19,20

SATA

HDD

(SATA)

ODD

FSB
533MHz

DMI Interface

ICH7-M

IDE

3

USB

DDR2-533MHz

PCIE *1

PCIE *1

PCI
33MHz

USB 2.0
CON X3

PAGE 36

Dual Channel DDR2

SO-DIMM X 2

PAGE 14,15,16

MINI CARD

WLAN

PAGE 26

NEW
CARD

PAGE 25

10/100 LAN
RTL8100CL

PAGE 34,35

CardBus

R5C847

PAGE 43,44

2

BTO

BTO

BTO

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

TERESA

TERESA

TERESA

CPU

CLOCK GEN

ICS954310

PAGE 5

DISCHARGER
CIRCUIT

PAGE 37

Power On Sequence

PAGE 40

DC/BATT IN

PAGE 41

CPU VCORE

PAGE 50

SYSTEM PWR

PAGE 51

BAT & CHARGER

PAGE 57

PCMCIA

PAGE 44

MEDIA CARD SLOT

PAGE 33

Title :

Title :

Title :

BLOCK DIAGRAM

BLOCK DIAGRAM

Engineer:

Engineer:

Engineer:

BLOCK DIAGRAM

Horng Chou

Horng Chou

Horng Chou

1 57Tuesday, February 06, 2007

1 57Tuesday, February 06, 2007

1 57Tuesday, February 06, 2007

1

BTO

BTO

Rev

Rev

Rev

1.1

1.1

1.1

5

H_A#[16..3]6
H_REQ#[4..0]6
H_A#[31..17]6

4

3

2

1

T202T202

U201A

D D

H_ADSTB#06

C C

H_ADSTB#16
H_A20M#17

H_FERR#17
H_IGNNE#17

H_STPCLK#17
H_INTR17
H_NMI17
H_SMI#17

B B

H_A#3
H_A#4

H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1 H_PROCHOT_S#

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

U201A

J4

A[3]#

L4

A[4]#

M3

A[5]#

K5

A[6]#

M1
N2

J1

N3

P5
P2
L1
P4
P1

R1

L2
K3

H2

K2

J3

L5

Y2
U5
R3
W6
U4

Y5
U2
R4

T5

T3
W3
W5

Y4
W2

Y1

V4

A6

A5
C4

D5
C6

B4

A3

AA1
AA4
AB2
AA3

M4
N5

T2

V3

B2
C3

B25

(070122)Change CPU Socket
into PN=12G011204796

A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
RSVD[10]

RSVD[11]

ADDR GROUP 0

ADDR GROUP 0

ADDR GROUP 1

ADDR GROUP 1

THERMHCLKRESERVED

THERMHCLKRESERVED

CONTROL

CONTROL

XDP/ITP SIGNALS

XDP/ITP SIGNALS

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

RSVD[12]
RSVD[A2]

RSVD[13]
RSVD[14]
RSVD[15]
RSVD[16]
RSVD[17]
RSVD[18]
RSVD[19]
RSVD[20]

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
B1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

D21
A24
A25

C7

A22
A21

T22
A2

D2
F6
D3
C1
AF1
D22
C23
C24

1

H_ADS#
H_BNR#
H_BPRI#H_A#5

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_CPURST#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

PRDY#
H_PREQ#
H_TCK
H_TDI
H_TDO
H_TMS
H_TRST#
CPU_DBR#

CPU_THRM_DA
CPU_THRM_DC

PM_THRMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS# 6
H_BNR# 6
H_BPRI# 6

H_DEFER#6
H_DRDY# 6
H_DBSY#6

H_BR0# 6

H_INIT# 17
H_LOCK#6
H_CPURST#6

H_RS#0 6
H_RS#1 6
H_RS#2 6
H_TRDY#6

H_HIT# 6
H_HITM# 6

+VCCP_AGTL+

T203T203

1

R203 Do Not Stuff@R203 Do Not Stuff@

1 2

R204 56OhmR204 56Ohm

1 2

R205 56OhmR205 56Ohm

1 2

R206 Do Not Stuff@R206 Do Not Stuff@

1 2

R207 56OhmR207 56Ohm

1 2

R208 56OhmR208 56Ohm

1 2

CPU_THRM_DA 4
CPU_THRM_DC 4

PM_THRMTRIP#4,17

CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5

68 ± 5% pull-up to Vcc1_05
If PROCHOT# is not used, then it must be terminated with a
56 pull-up resistor to VCCP.
If PROCHOT# is routed between CPU, IMVP and MCH,
pull-up resistor has to be 75 Ohm ± 5%

1 2

1

T201T201

GND

1

Do Not Stuff

Do Not Stuff

R201

R201
56Ohm

56Ohm

R202

R202
Do Not Stuff@

Do Not Stuff@

T204

T204

12

+VCCP_AGTL+

+VCCP_AGTL+

C201

C201
Do Not Stuff

Do Not Stuff

@

@

GND

+VCCP_AGTL+

12

R213

R213

2KOhm

2KOhm

1%

1%

R209

R209

1KOhm

1KOhm

1%

1%

1 2

<500 mil (55 Ohm)
T/B trace 5
Space 25

1 2

GND

For Celeron M

BCLK

GND

H_DSTBN#06
H_DSTBP#06
H_DINV#06

H_DSTBN#16
H_DSTBP#16
H_DINV#16

CPU_BSEL05
CPU_BSEL15
CPU_BSEL25

@R214

@

R214

1 2

Do Not Stuff

Do Not Stuff

R216

R216

1 2

51Ohm

51Ohm

FSB

533MHz

BSEL2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

GTL_REF

AD26

TEST1
TEST2

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

BSEL1BSEL0

HL133MHz L

U201B

U201B

E22

D[0]#

F24

D[1]#

E26

D[2]#

H22

D[3]#

M23

R24

N24
M24
N25
M26

C26
D25

C21

F23
G25
E25
E23
K24
G24

H26
F26
K22
H25
H23
G22

N22
K25
P26
R23
L25
L22
L23

P25
P22
P23
T24

L26
T25

B22
B23

J24
J23

J26

DATA GRP 0

DATA GRP 0

D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

D[16]#
D[17]#
D[18]#
D[19]#

DATA GRP 1

DATA GRP 1

D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

GTLREF

MISC

MISC

TEST1
TEST2

BSEL[0]
BSEL[1]
BSEL[2]

(070122)Change CPU Socket
into PN=12G011204796

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23

AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20

R26
U26
U1
V1

E5
B5
D24
D6
D7
AE6

H_D#[0..63] 6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

H_COMP0

R210 27.4Ohm 1%R210 27.4Ohm 1%

H_COMP1
H_COMP2
H_COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD

1 2

R211 54.9Ohm 1%R211 54.9Ohm 1%

1 2

R212 27.4Ohm 1%R212 27.4Ohm 1%

1 2

R215 54.9Ohm 1%R215 54.9Ohm 1%

1 2

1

H_CPUSLP#
PM_PSI#

H_DSTBN#26
H_DSTBP#26
H_DINV#2 6

Layout Note:
Comp0,2 connect with Z0=27.4 ohm,
make trace length shorter than 0.5".
Comp1,3 connect with Z0=54.9 ohm,
make trace length shorter than 0.5".
Comp[3:0] at least 25 mils away from
any other toggling signal.

27.4 ohm connects with an ~18mil
wide trace to comp0.

54.9 ohm connect with 5mil-wide
to comp1

H_DSTBN#36
H_DSTBP#36
H_DINV#3 6

H_DPRSTP#17,50
H_DPSLP#17
H_DPWR# 6
H_PWRGD 17

T205T205

H_CPUSLP#6,17
PM_PSI# 50

GND

+VCCP_AGTL+ +VCCP

A A

+VCCP

+VCCP_AGTL+

JP201

JP201

1 2

Do Not Stuff

Do Not Stuff

2.5A

5

@

@

+VCCP 6,9,20,52
+VCCP_AGTL+3,5,6,9

H_PROCHOT_S#29

H_PROCHOT_S# H_PWRGD

4

+VCCP_AGTL+

R217

R217
56Ohm

56Ohm

1 2

+VCCP_AGTL+

R218

R218
Do Not Stuff@

Do Not Stuff@

1 2

3

PCMCIA

PCMCIA

PCMCIA

Title :

Title :

Title :

YONAH CPU (1)

YONAH CPU (1)

1

YONAH CPU (1)

Horng Chou

Horng Chou

Horng Chou

2 57Tuesday, February 06, 2007

2 57Tuesday, February 06, 2007

2 57Tuesday, February 06, 2007

Rev

Rev

Rev

1.1

1.1

1.1

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

TERESA

TERESA

TERESA

Engineer:

5

4

3

2

1

Celeron M FSB:533MHz
MIN TYP MAX
VCC 1.0V 1.2V 1.3V
C3 C2 C0
ICC 14.7A 16.5A 29Ah

D D

+VCORE

U201CU201C

A7

VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[65]
VCC[66]
VCC[67]

VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
VCC[77]
VCC[78]
VCC[79]
VCC[80]
VCC[81]
VCC[82]
VCC[83]
VCC[84]
VCC[85]
VCC[86]
VCC[87]
VCC[88]
VCC[89]
VCC[90]
VCC[91]
VCC[92]
VCC[93]
VCC[94]
VCC[95]
VCC[96]
VCC[97]
VCC[98]
VCC[99]

VCC[100]

VCCP[1]
VCCP[2]
VCCP[3]
VCCP[4]
VCCP[5]
VCCP[6]
VCCP[7]
VCCP[8]

VCCP[9]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

5

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17

C C

B B

A A

C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9

AC10
AB10
AB12
AB14
AB15
AB17
AB18

(070122)Change CPU Socket
into PN=12G011204796

Celeron M FSB:533MHz
MIN TYP MAX
VCCP 0.997V 1.05V 1.102V
MIN TYP MAX
ICCP 2.5A

Modity Table for Celeron M

+VCORE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26

AD6
AF5
AE5
AF4
AE3
AF2
AE2

AF7

AE7

+VCCA

JP301

JP301

Do Not Stuff

Do Not Stuff

@

@

+VCCP_AGTL+

7 8

+VCCA

120mA / 20mil
Close to Pin B26

12

C301

C301

10UF/10V

10UF/10V

12

0Ohm

0Ohm
0Ohm

0Ohm
0Ohm

0Ohm
0Ohm

0Ohm
0Ohm

0Ohm
0Ohm

0Ohm
0Ohm

0Ohm

1 2

R302

R302
100Ohm

100Ohm

R301

R301

100Ohm

100Ohm

GND

RN302A

RN302A
RN302B

RN302B
RN302C

RN302C
RN302D

RN302D
RN303A

RN303A
RN303B

RN303B
RN303C

RN303C

H_VID0

1 2

H_VID1

3 4

H_VID2

5 6

H_VID3

7 8

H_VID4

1 2

H_VID5

3 4

H_VID6

5 6

VCCSENSE

VSSSENSE

GND

Layout Note:
VCCSENSE/VSSSENSE lines between the
CPU and the VR should have a trace width of
18 mils on 7 mils spacing, with trace
impedance of Zo=27.4 Ohm.
The VCCSENSE/VSSSENSE should be
length matched to within 25 mils.
These resistors should be placed within 2
inch of the CPU.

2

112

0Ohm

0Ohm

12

C318

C318

0.01UF/25V

0.01UF/25V

checklist suggests
10uF POSCAP

+1.5VO

RN303D

RN303D

VR_VID0 50
VR_VID1 50
VR_VID2 50
VR_VID3 50
VR_VID4 50
VR_VID5 50
VR_VID6 50

+VCORE
VCCSENSE 50

VSSSENSE 50

A4

A8
A11
A14
A16
A19
A23
A26

B6

B8
B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3

E6

E8
E11
E14
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5

J22
J25

K1

K4
K23
K26

L3

L6

L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

P3

(070122)Change CPU Socket
into PN=12G011204796

4

U201DU201D

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]

VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24

+VCCP_AGTL+ 2,5,6,9
+VCORE 50

+1.5VS 7,9,10,20,25,26,37,52

+VCORE

1215---PWR comp

12

+

+

CE301

CE301

Do Not Stuff

Do Not Stuff

@

@

GND

Place the cap on North
of Secondary side

+VCCP_AGTL+

+VCORE

+1.5VS

Vcc Core Decoupling Caps
Primary side => Bottom side
Secondary side => Top side

(070131)Change 22UF into 10UF

Place these upper side inside socket cavity on L1

12

C302

C302

10UF/10V

10UF/10V

GND GND

12

C303

C303

10UF/10V

10UF/10V

12

10UF/10V

10UF/10V

GND

C304

C304

12

10UF/10V

10UF/10V

GND GND

C305

C305

12

C306

C306

10UF/10V

10UF/10V

12

10UF/10V

10UF/10V

GND

C307

C307

Place these lower side inside socket cavity on L1

12

C309

C309

10UF/10V

10UF/10V

GND GND

12

C311

C311

10UF/10V

10UF/10V

12

10UF/10V

10UF/10V

GND

C308

C308

12

10UF/10V

10UF/10V

GND

C310

C310

12

10UF/10V

10UF/10V

GND

C312

C312

12

10UF/10V

10UF/10V

GND

C313

C313

Place these upper side inside socket cavity on L6

C314

C314

12

10UF/10V

10UF/10V

GND

12

10UF/10V

10UF/10V

GND

Place these lower side inside socket cavity on L6

C319

C319

12

10UF/10V

10UF/10V

12

10UF/10V

10UF/10V

GND

(061228)Change into 10UF/10V PN:11G236322636360
C302,C303,C309,C311
C314,C315,C316,C317
C319,C320,C321,C322

GNDGND

3

C315

C315

C320

C320

12

10UF/10V

10UF/10V

GND

12

10UF/10V

10UF/10V

GNDGND

C316

C316

C321

C321

12

10UF/10V

10UF/10V

GND

12

10UF/10V

10UF/10V

GND

C317

C317

C322

C322

+VCCP_AGTL+

+1.05V Decoupling Capacitor
Place near CPU

12

12

C323

C323

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C324

C324

c0402

c0402

0.1UF/10V

0.1UF/10V

C325

C325

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C326

C326

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C327

C327

c0402

c0402

0.1UF/10V

0.1UF/10V

(070205)Change P/N: 11G232310436320

PCMCIA

PCMCIA

PCMCIA

Title :

Title :

Title :

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

TERESA

TERESA

TERESA

Engineer:

1

12

C328

C328

c0402

c0402

0.1UF/10V

0.1UF/10V

GND

Yonah CPU (2)

Yonah CPU (2)

Yonah CPU (2)

Horng Chou

Horng Chou

Horng Chou

3 57Tuesday, February 06, 2007

3 57Tuesday, February 06, 2007

3 57Tuesday, February 06, 2007

12

+

+

100UF/2.5V

100UF/2.5V

CE302

CE302

Rev

Rev

Rev

1.1

1.1

1.1

5

4

3

2

1

+5VS

Fan Speed Control

+5VS

D D

C C

B B

Route H_THERMDA and H_THERMDC
on the same layer

------------------OTHER SIGNALS
12 mils
===============GND
10 mils
=========H_THERMDA(10 mils)
10 mils

A A

=========H_THERMDC(10 mils)
10 mils
=========GND
12 mils

---------------------OTHER SIGNALS

Avoid BPSB,Power

5

KBC will issue a
analog ( a voltage
level ) signal.

SW: FAN_DA1 must
be low during S3

FAN_PWM29

FAN0_TACH29

C407

C407

0.01UF/50V

0.01UF/50V

1
2

GND

THRM_CPU#29

FAN_PWM

FAN0_TACH

12

U402

U402

NC

VCC
SUB
GND3VOUT

PST9013NR

PST9013NR

+3VA

T402

T402
Do Not Stuff

Do Not Stuff

1

R409

R409
10KOhm

10KOhm

r0402

r0402

5
4

+3VA_EC

T403

T403
Do Not Stuff

Do Not Stuff

1

R411

R411

7.68KOhm

7.68KOhm

1 2

GND

1 2

3 2

3

3

4

1

R412

R412

1
2

100KOhm

100KOhm

2

1

Do Not Stuff

Do Not Stuff
T401

T401

+5VS

D

D

Q403

Q403

2N7002

2N7002

THERMAL PROTECTION
PLACE UNDER CPU

(85 DEGREE C)

105 -> 85, R411 need to be tuned
(1204)maybe R411=14.7K Ohm(10G213147213010)

1

1

R413

R413

R414

R414

1

1

@

@

@

@

2

2

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

2

2

FORCE_OFF# 29,38,41,51,60

1

1

1

SMB1_CLK29

G

G

SMB1_DAT29

2

2

S

S

+3VS

+3VS

R403

R403
10KOhm

10KOhm

1 2

12

C401

C401

GND

1

R415

R415

1
2

Do Not Stuff

Do Not Stuff

2

1 2

R410

R410

4.7KOhm

4.7KOhm

2200PF/50V

2200PF/50V

1

R416

R416

1

@

@

@

@

2

Do Not Stuff

Do Not Stuff

2

(061214)Add 4 thermiters

+3VS

R408

R408

1 2

0Ohm

0Ohm

r0402

r0402

SMB1_CLK
SMB1_DAT
SMBALERT#

+3VS

R402

R402

10KOhm

10KOhm

1 2

Unmount: CE401 and D1 New addition

+3VS_THM

+3VS_THM

12

C405

C405

0.1UF/10V

0.1UF/10V

c0402

c0402

8

SCLK

7

SDATA

6

ALERT#

5

THERM#

GND

G781P8F

G781P8F

06G023048021

GND

06G023048021

(070110)
Add second sorce: 06G023048021

3

12

+

+

CE401

CE401

D1

D1

Do Not Stuff

Do Not Stuff

Do Not Stuff

Do Not Stuff

@

@

@

@

1 2

GND

12

C403

C403
Do Not Stuff

Do Not Stuff

@

@

GND

PM_THRMTRIP#2,17

GMCH_THRMTRIP#7

(070130)Add 0ohm resister

Standby Mode: 3uA(Max. 10uA)
Full Active: 0.5 mA(Max. 1mA)

U401

U401

1

VDD

CPU_THRM_DA

2

D+

CPU_THRM_DC

3

D-

4

GNDGND

12

12

C408

C408

10UF/10V

10UF/10V

R418

R418
10KOhm

10KOhm

12

GND

GND

R417

R417

1 2

0Ohm

0Ohm

+3VS_THM

1

1

1

G

G

2

2

S

S

Q404 2N7002

Q404 2N7002

+3VS
+3VA

C402

C402

0.1UF/10V

0.1UF/10V

WtoB_CON_4P

WtoB_CON_4P

4

4

3

3

2

2

1

1

CON401

CON401

(070122)Change CON401 into
PN:12G171000047

R407

R407

1 2

330Ohm

330Ohm

4"-8"

12

2200PF/50V

2200PF/50V

4"-8"

3

3

32

D

D

EC_RST_SW# 29,38,41,51,60

(070110)Add R418 and Q404
to avoid error action

2

+5VS 13,19,20,21,22,28,29,30,34,37,38,50,61
+3VS 5,7,9,11,12,13,14,15,19,20,21,22,25,26,27,28,29,30,33,37,40,43,50,52,60,61
+3VA 12,22,29,37,38,40,41,54,59,63

6

NC2

5

NC1

GND

+3VA

12

R405

1

1

1

G

G

R405
Do Not Stuff

Do Not Stuff

r0402

r0402
@

@

32

3

3

D

D

S

S

2

2

GND

TERESA

TERESA

TERESA

VSUS_ON

Q401

Q401
2N7002

2N7002

TRIP_R

C406

C406

Q402

Q402

B

1

B

1

PMBS3904

PMBS3904

+3VS

12

R406

R406
1MOhm

1MOhm

VSUS_ON_G

12

C404

C404

3

3

0.22UF/6.3V

0.22UF/6.3V

C

C

E

E
2

2

GND

GND

CPU_THRM_DA 2

CPU_THRM_DC 2

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

VSUS_ON 25,29,51

THER-SENSOR,FAN

THER-SENSOR,FAN

THER-SENSOR,FAN

Horng Chou

Horng Chou

Horng Chou

4 57Tuesday, February 06, 2007

4 57Tuesday, February 06, 2007

4 57Tuesday, February 06, 2007

Rev

Rev

Rev

1.1

1.1

1.1

5

Request

PCIE_REQ1# PCIE0(#),PCIE6(#)

PCIE_REQ2#

PCIE_REQ3#

D D

PCIE_REQ4#

C C

B B

SELPCIE0_LCD#:
0-->pin17,pin18=LCDCLK(96MHz) or
27M/27M_SS

A A

SELLCD_27#/PCICLK_F1:
1-->pin17,pin18=LCDCLK(96MHz)

PCICLK2/REQ_SEL:
1-->pin40,pin41=PREQ1#,PREQ2#

ITP_EN/PCICLK_F0:
1-->CPU_ITP pair

Control net

Net name

None

PCIE1(#),PCIE8(#)

PCIE2(#),PCIE4(#)

PCIE3(#),PCIE5(#),
PCIE7(#)

(070130)Change C516
from 27PF to 33PF

CLK_LCD_SSCG7
CLK_LCD_SSCG#7
CLK_USB4819

CPU_BSEL02
CPU_BSEL12

CLK_LAN_PCI34
CLK_CBPCI43

Delete CLK_TPMPCI(connect to pin3)

CLK_FWHPCI26
CLK_ECPCI29

CLK_ICHPCI18
SMB_CLK_S14,15,19,25,26
SMB_DAT_S14,15,19,25,26

5

None

CLK_PCIE_MINICARD(#)

CLK_MCH_3GPLL(#)

+/-30ppm/20PF

+/-30ppm/20PF

14.318Mhz

14.318Mhz

12

C516

C516
33PF/50V

33PF/50V

GND

X501

X501

1 2

1 2

12

C517

C517
33PF/50V

33PF/50V

C518 Do No t Stu ff@C518 Do No t Stu ff

@

@

1 2

1 2

GND

Realtek:Mount R519,Remove R550 R534

+VCCP_AGTL+

12

12

C514

C514

0.1UF/10V

0.1UF/10V

10UF/10V

10UF/10V

GND

GND

+3VS_CLK
+3VS_CLK

+3VS_CLK

C520 Do No t Stu ff@C520 Do No t Stu ff

C521 Do Not Stuff@C521 Do Not Stuff

C522 Do Not Stuff@C522 Do Not Stuff

C523 Do Not Stuff@C523 Do Not Stuff

C519 Do Not Stuff@C519 Do Not Stuff

@

@

@

@

1 2

1 2

1 2

1 2

4

R501

@R501

@

Do Not Stuff

Do Not Stuff

12

R503

@R503

@

Do Not Stuff

Do Not Stuff

12

R504

@R504

@

Do Not Stuff

Do Not Stuff

12

R506

@R506

@

Do Not Stuff

Do Not Stuff

12

GND

+3VS_CLK

R517

R517

12

2.2Ohm

2.2Ohm

C515

C515

GND

R530 33OhmR530 33Ohm

1 2

R532 33OhmR532 33Ohm

1 2

R535 33OhmR535 33Ohm

1 2

R536 2.2KOhmR536 2.2KOhm

1 2

R539 33OhmR539 33Ohm

1 2

R540 10KOhmR540 10KOhm

1 2

R541 33OhmR541 33Ohm

1 2

R544 33OhmR544 33Ohm

1 2

R546 33OhmR546 33Ohm

1 2

R548 10KOhmR548 10KOhm

1 2

R550 10KOhmR550 10KOhm

1 2

R552 33OhmR552 33Ohm

1 2

R553 10KOhmR553 10KOhm

1 2

4

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

R558

R558
475Ohm

475Ohm

1 2

GND

R502 0OhmR502 0Ohm

1 2

R505 0OhmR505 0Ohm

1 2

R507 0OhmR507 0Ohm

1 2

Pin34 is PWRSAVE#

+3VS_VDDA

ICS_X1
ICS_X2
LCD_SSCG
LCD_SSCG#
FSA

PCICLK5
PCICLK4
PCICLK3
PCICLK2

PCICLK_F0

ICS_IREF

GND

MCH_BSEL0 7

MCH_BSEL1 7

MCH_BSEL2 7

+3VS

12

12

0.1UF/10V

0.1UF/10V

GND

21
28
42

34
50
45
46
58
57
17
18
12
16

5
4
3

64

9

8
54
55
47

2

6
13
29
37
53
59

ICS954310CGLFT

ICS954310CGLFT

C502

C502

C501

C501

0.1UF/10V

0.1UF/10V

U501

U501

VDDPCIEX1
VDDPCIEX2
VDDPCIEX3

VDD
VDDCPU
VDDA
GNDA
X1
X2
27FIX/LCD_SSCGT/PCIEX0T
27SS/LCD_SSCGC/PCIEX0C
FSLA/USB_48MHz
FSLB/TEST_MODE

SELPCIEX0_LCD#PCICLK5
PCICLK4
PCICLK3
PCICLK2/REQ_SEL

SELLCD_27#/PCICLK_F1
ITP_EN/PCICLK_F0
SCLK
SDATA
IREF

GND1
GND2
GND3
GND4
GND5
GND6
GND7

1

VDDPCI1

internal
pull high

Internal Pull-Up Resistor

Internal Pull-Down Resistor

3

Bclk BSEL0FSB

133

533
667

166

L501

L501

21

120Ohm/100Mhz

120Ohm/100Mhz

21

L502

L502
120Ohm/100Mhz

120Ohm/100Mhz

+3VS_VDDPCI

12

C508

C508

0.1UF/10V

0.1UF/10V

7

VDDPCI2

PCI/PCIEX_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

CPUCLKT2_ITP/PCIEXT8
CPUCLKC2_ITP/PCIEXC8

PEREQ1#/PCIEXT7
PEREQ2#/PCIEXC7

SATACLKT
SATACLKC

DOTT_96MHz
DOTC_96MHz

Vtt_PwrGd#/PD

REF1/FSLC/TEST_SEL

3

FSLC FSLB FSLA

BSEL1

BSEL2

L
L H

+3VS_CLK

12

12

C504

C504

C503

C503

0.1UF/10V

0.1UF/10V

10UF/10V

10UF/10V

12

12

C509

C509

C510

C510

0.1UF/10V

0.1UF/10V

10UF/10V

10UF/10V

GND

+3VS_VDD48

11

VDD48

+3VS_VDDREF

56

VDDREF

PCIEXT6
PCIEXC6

PCIEXT5
PCIEXC5

PCIEXT4
PCIEXC4

PCIEXT3
PCIEXC3

PCIEXT2
PCIEXC2

PCIEXT1
PCIEXC1

PEREQ3#
PEREQ4#

REF0

63
62

49
48

52
51

44
43

41
40

39
38

36
35

30
31

24
25

22
23

19
20

26
27

14
15

32
33

10

61
60

STP_PCI#
STP_CPU#

CLK_CPU
CLK_CPU#

CLK_MCH
CLK_MCH#

PEREQ#1
PEREQ#2

PCIE6
PCIE#6

PCIE4
PCIE#4

PCIE3
PCIE#3

PCIE2
PCIE#2

CLK_SATA
CLK_SATA#

DOT96
DOT96#

REF1
REF0

HL
H

+3VS_CLK

12

12

C506

C506

C505

C505

0.1UF/10V

0.1UF/10V

0.1UF/10V

0.1UF/10V

12

C511

R513

R513

2.2Ohm

2.2Ohm

R526 33OhmR526 33Ohm
R527 33OhmR527 33Ohm

R523 33OhmR523 33Ohm
R524 33OhmR524 33Ohm

R537 33OhmR537 33Ohm
R538 33OhmR538 33Ohm

R542 33OhmR542 33Ohm
R543 33OhmR543 33Ohm

R545 33OhmR545 33Ohm
R547 33OhmR547 33Ohm

R549 33OhmR549 33Ohm
R551 33OhmR551 33Ohm

R556 33OhmR556 33Ohm
R557 33OhmR557 33Ohm

R563 2.2KOhmR563 2.2KOhm

R564 33OhmR564 33Ohm

C511

0.1UF/10V

0.1UF/10V

1 2

1 2
1 2

1 2
1 2

R531 10KOhmR531 10KOhm
R533 Do Not Stuff@R533 Do Not Stuff@

1 2

R534 10KOhmR534 10KOhm

12

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

R554 33OhmR554 33Ohm

1 2

R555 33OhmR555 33Ohm

1 2

1 2
1 2

Remove 0ohm

1 2
1 2

+VCCP_AGTL+

12

C507

C507

0.1UF/10V

0.1UF/10V

GND

12

C512

C512

10UF/10V

10UF/10V

GND

STP_PCI# 19
STP_CPU# 19,50

12

GND

2

+3VS

R514

R514
1Ohm

1Ohm

1 2

C513

C513

1 2

0.1UF/10V

0.1UF/10V

CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6

(070205)
R533 Remove

+3VS

CLK_NEWCARD_REQ# 25

CLK_PCIE_NEWCARD 25
CLK_PCIE_NEWCARD# 25

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_MINICARD 26
CLK_PCIE_MINICARD# 26

CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18

CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17

CLK_UMA_96M 7
CLK_UMA_96M# 7

MCH_CLK_REQ# 7
CLK_MINICARD_REQ# 26

CPU_BSEL2 2
CLK_ICH14 19

2

1

+VCCP_AGTL+ 2,3,6,9
+3VS 4,7,9,11,12,13,14,15,19,20,21,22,25,26,27,28,29,30,33,37,40,43,50,52,60,61

Layout Note:
Place termination close to source IC

GND

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_LCD_SSCG
CLK_LCD_SSCG#

CLK_UMA_96M
CLK_UMA_96M#

CLK_PCIE_MINICARD
CLK_PCIE_MINICARD#

CLK_PCIE_NEWCARD
CLK_PCIE_NEWCARD#

CLK_PCIE_SATA
CLK_PCIE_SATA#

R508 49.9Ohm

R508 49.9Ohm

1 2

r0402_h16

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

r0402_h16
r0402_h16

r0402_h16

r0402_h16

r0402_h16
r0402_h16

r0402_h16

r0402_h16

r0402_h16
r0402_h16

r0402_h16

r0402_h16

r0402_h16
r0402_h16

r0402_h16

r0402_h16

r0402_h16
r0402_h16

r0402_h16

r0402_h16

r0402_h16
r0402_h16

r0402_h16

r0402_h16

r0402_h16
r0402_h16

r0402_h16

r0402_h16

r0402_h16
r0402_h16

r0402_h16

r0402_h16

r0402_h16
r0402_h16

r0402_h16

R509 49.9Ohm

R509 49.9Ohm

R510 49.9Ohm

R510 49.9Ohm
R511 49.9Ohm

R511 49.9Ohm

R512 49.9Ohm

R512 49.9Ohm
R515 49.9Ohm

R515 49.9Ohm

R516 49.9Ohm

R516 49.9Ohm
R518 49.9Ohm

R518 49.9Ohm

R519 49.9Ohm

R519 49.9Ohm
R521 49.9Ohm

R521 49.9Ohm

R522 49.9Ohm

R522 49.9Ohm
R525 49.9Ohm

R525 49.9Ohm

R528 49.9Ohm

R528 49.9Ohm
R529 49.9Ohm

R529 49.9Ohm

R566 49.9Ohm

R566 49.9Ohm
R567 49.9Ohm

R567 49.9Ohm

R568 49.9Ohm

R568 49.9Ohm
R569 49.9Ohm

R569 49.9Ohm

PREQ#1
0=PCIEX 6/0 Not Controlled
1=PCIEX 6/0 Controlled

PREQ#2
0=PCIEX 8/1 Not Controlled
1=PCIEX 8/1 Controlled

+3VS_CLK

12

PREQ#3
0=PCIEX 4/2 Not Controlled
1=PCIEX 4/2 Controlled

R560

R560
Do Not Stuff

Do Not Stuff

@

@

CLK_EN# 50

PREQ#4
0=PCIEX 7/5/3 Not Controlled
1=PCIEX 7/5/3 Controlled

PCMCIA

PCMCIA

PCMCIA

Title :

Title :

Title :

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

TERESA

TERESA

TERESA

Engineer:

1

CLOCK GEN

CLOCK GEN

CLOCK GEN

Horng Chou

Horng Chou

Horng Chou

5 57Tuesday, February 06, 2007

5 57Tuesday, February 06, 2007

5 57Tuesday, February 06, 2007

GND

Rev

Rev

Rev

1.1

1.1

1.1

5

H_D#[0..63]2 H_A#[31..3] 2

U601A

H_D#0
H_D#1
H_D#2
H_D#3

5

H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP
H_XSWING

H_YRCOMP
H_YSCOMP
H_YSWING

CLK_MCH_BCLK
CLK_MCH_BCLK#

D D

C C

B B

CLK_MCH_BCLK5

A A

CLK_MCH_BCLK#5

U601A

F1

H_D#_0

J1

H_D#_1

H1

H_D#_2

J6

H_D#_3

H3

H_D#_4

K2

H_D#_5

G1

H_D#_6

G2

H_D#_7

K9

H_D#_8

K1

H_D#_9

K7

H_D#_10

J8

H_D#_11

H4

H_D#_12

J3

H_D#_13

K11

H_D#_14

G4

H_D#_15

T10

H_D#_16

W11

H_D#_17

T3

H_D#_18

U7

H_D#_19

U9

H_D#_20

U11

H_D#_21

T11

H_D#_22

W9

H_D#_23

T1

H_D#_24

T8

H_D#_25

T4

H_D#_26

W7

H_D#_27

U5

H_D#_28

T9

H_D#_29

W6

H_D#_30

T5

H_D#_31

AB7

H_D#_32

AA9

H_D#_33

W4

H_D#_34

W3

H_D#_35

Y3

H_D#_36

Y7

H_D#_37

W5

H_D#_38

Y10

H_D#_39

AB8

H_D#_40

W2

H_D#_41

AA4

H_D#_42

AA7

H_D#_43

AA2

H_D#_44

AA6

H_D#_45

AA10

H_D#_46

Y8

H_D#_47

AA1

H_D#_48

AB4

H_D#_49

AC9

H_D#_50

AB11

H_D#_51

AC11

H_D#_52

AB3

H_D#_53

AC2

H_D#_54

AD1

H_D#_55

AD9

H_D#_56

AC1

H_D#_57

AD7

H_D#_58

AC6

H_D#_59

AB5

H_D#_60

AD10

H_D#_61

AD4

H_D#_62

AC8

H_D#_63

E1

H_XRCOMP

E2

H_XSCOMP

E4

H_XSWING

Y1

H_YRCOMP

U1

H_YSCOMP

W1

H_YSWING

AG2

H_CLKIN

AG1

H_CLKIN#

CALISTOGA_Q137

CALISTOGA_Q137

4

H_A#3

H9

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_AVREF

H_BNR#

H_BPRI#

H_BREQ#0

H_CPURST#

HOST

H OST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

4

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#
H_DVREF

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_SLPCPU#

H_TRDY#

C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13

J7
W8
U3
AB10

K4
T7
Y5
AC4

K3
T6
AA5
AC5

D3
D4
B3

D8
G8
B8
F8
A8

B4
E6
D6

E3
E7

H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_HIT#
H_HITM#
H_LOCK#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

N_CPUSLP#
H_TRDY#

H_ADS# 2
H_ADSTB#0 2
H_ADSTB#1 2

H_BNR# 2
H_BPRI# 2
H_BR0# 2
H_CPURST# 2
H_DBSY# 2
H_DEFER# 2
H_DPWR# 2
H_DRDY# 2

H_DINV#0 2
H_DINV#1 2
H_DINV#2 2
H_DINV#3 2

H_DSTBN#0 2
H_DSTBN#1 2
H_DSTBN#2 2
H_DSTBN#3 2

H_DSTBP#0 2
H_DSTBP#1 2
H_DSTBP#2 2
H_DSTBP#3 2

H_HIT# 2
H_HITM# 2
H_LOCK# 2

R611

R611
0Ohm

0Ohm

12

3

+VCCP_AGTL+

R601

R601
100Ohm

100Ohm

1%

1%

1 2

R606

R606
200Ohm

200Ohm

1%

1%

1 2

GND

Layout Note:

0.1uF should be placed 100mils or
less from GMCH pin.

H_REQ#[4..0] 2

H_RS#[0..2] 2

H_CPUSLP# 2,17
H_TRDY# 2

3

<500 mil (55 Ohm)
T/B trace 5.5 ,
Space 25

12

C601

C601

0.1UF/10V

0.1UF/10V

GND

+VCCP

GND

+VCCP

GND

+VCCP

GND

2

R602

R602

54.9Ohm

54.9Ohm

1%

1%

1 2

H_XSCOMP

H_XRCOMP

R604

R604

24.9Ohm

24.9Ohm

1%

1%

1 2

R607

R607
221Ohm

221Ohm

1%

1%

1 2

R608

R608
100Ohm

100Ohm

1%

1%

1 2

R609

R609
221Ohm

221Ohm

1%

1%

1 2

R610

R610
100Ohm

100Ohm

1%

1%

1 2

2

+VCCP

+VCCP_AGTL+

+VCCP

R603

5.5/20 mils

10/20mils

H_XSWING

12

C602

C602

0.1UF/10V

0.1UF/10V

GND

H_YSWING

12

C603

C603

0.1UF/10V

0.1UF/10V

GND

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

R603

54.9Ohm

54.9Ohm

1%

1%

1 2

H_YSCOMP

H_YRCOMP

R605

R605

24.9Ohm

24.9Ohm

1%

1%

1 2

GND

10/20mils

Signal voltage level =

0.3125*VCCP
Trace should be 10 mil wide
with 20 mil spacing

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

TERESA

TERESA

TERESA

1

+VCCP 2,9,20,52
+VCCP_AGTL+2,3,5,9

Calistoga GMCH (1)

Calistoga GMCH (1)

Calistoga GMCH (1)

Horng Chou

Horng Chou

Horng Chou

6 57Tuesday, February 06, 2007

6 57Tuesday, February 06, 2007

6 57Tuesday, February 06, 2007

1

Rev

Rev

Rev

1.1

1.1

1.1

5

4

3

2

1

+1.5VS_PCIE

R702

+3VS

L_BKLTCTL12

R703 10KOhmR703 10KOhm

1 2

R704 10KOhmR704 10KOhm

1 2

R705 10KOhmR705 10KOhm

1 2

R706 10KOhmR706 10KOhm

L_BKLTEN

R710

R710
100KOhm

100KOhm

R707

R707

1.5KOhm

1.5KOhm

1%

1%

1 2

12

GND

D D

1 2

GND

T702T702

GND

1

L_BKLTCTL
L_BKLTEN
L_CTLA_CLK
L_CTLB_DATA
EDID_CLK
EDID_DAT
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL

LVDS_LCLKN
LVDS_LCLKP

LVDS_L0N
LVDS_L1N
LVDS_L2N

LVDS_L0P
LVDS_L1P
LVDS_L2P

Remove LVDS channel B

C C

+1.5VS

TV OUT disable way

R720 150Ohm

R720 150Ohm
R721 150Ohm

R721 150Ohm
R722 150Ohm

R722 150Ohm

GND

B B

A A

DAC_HSYNC_GM
DAC_VSYNC_GM

LVDS_L0N
LVDS_L2N
LVDS_L0P

LVDS_L1P
LVDS_L2P

CRT_BLUE

12

1%

1%

CRT_GREEN

12

1%

1%

CRT_RED

12

1%

1%

CRT_DDC_CLK
CRT_DDC_DATA

LVDS_L0N 12
LVDS_L1N 12
LVDS_L2N 12

LVDS_L0P 12
LVDS_L1P 12
LVDS_L2P 12

R725

R725
255Ohm

255Ohm

1%

1%

GND

D32

J30
H30
H29
G26
G25
B38
C35
F32
C33
C32

A33
A32
E27
E26

C37
B35
A37

B37
B34
A36

G30
D30
F29

F30
D29
F28

A16
C18
A19

J20
B16
B18
B19

E23
D23
C22
B22
A21
B21

GND

C26
C25
G23

J22
H23

CRT_IREF

12

U601C

U601C

L_BKLTCTL
L_BKLTEN
L_CLK_CTLA
L_DATA_CTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL

LA_CLK#
LA_CLK
LB_CLK#
LB_CLK

LA_DATA#_0
LA_DATA#_1
LA_DATA#_2

LA_DATA_0
LA_DATA_1
LA_DATA_2

LB_DATA#_0
LB_DATA#_1
LB_DATA#_2

LB_DATA_0
LB_DATA_1
LB_DATA_2

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC

CALISTOGA_Q137

CALISTOGA_Q137

LVDS_LCLKN
LVDS_LCLKPLVDS_L1N

L_BKLTEN
EDID_CLK

EDID_DAT
L_VDDEN

LVDS

LVD S

TV

TV

VGA

VGA

LVDS_LCLKN 12
LVDS_LCLKP 12

L_BKLTEN 12
EDID_CLK 12

EDID_DAT 12
L_VDDEN 12

PCI-EXPRESS GRAPHICS

PCI- EX PRES S GRAP HICS

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8

EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15

EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8

EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15

EXP_A_TXN_0

EXP_A_TXN_1

EXP_A_TXN_2

EXP_A_TXN_3

EXP_A_TXN_4

EXP_A_TXN_5

EXP_A_TXN_6

EXP_A_TXN_7

EXP_A_TXN_8

EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15

EXP_A_TXP_0

EXP_A_TXP_1

EXP_A_TXP_2

EXP_A_TXP_3

EXP_A_TXP_4

EXP_A_TXP_5

EXP_A_TXP_6

EXP_A_TXP_7

EXP_A_TXP_8

EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15

EXP_A_COMP

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

CRT_RED
CRT_GREEN
CRT_BLUE

DAC_HSYNC_GM
DAC_VSYNC_GM

CRT_DDC_CLK
CRT_DDC_DATA

R702

1 2

24.9Ohm

24.9Ohm

1%

1%

PM_DPRSLPVR19,50

CRT_RED 13
CRT_GREEN 13
CRT_BLUE 13

CRT_DDC_CLK 13
CRT_DDC_DATA 13

U601B

U601B

T32

RSVD_1

R32

RSVD_2

F3

+3VS

R708

R708

1 2

1 2

MCH_BSEL05
MCH_BSEL15
MCH_BSEL25

MCH_CFG_511
MCH_CFG_711
MCH_CFG_911
MCH_CFG_1111

MCH_CFG_1611
MCH_CFG_1811

MCH_CFG_1911

PM_BMBUSY#19

GMCH_THRMTRIP#4

ICH_PWROK19,29

PLT_RST#18,19,25,26,28,29

MCH_ICH_SYNC#18
MCH_CLK_REQ#5

PM_EXTTS#0

10KOhm

10KOhm
R709

R709

PM_EXTTS#1

10KOhm

10KOhm

R718 Do Not Stuff

R718 Do Not Stuff

1 2

@

@

T703T703
T701T701

T704T704
T705T705
T706T706
T707T707

T708T708
T709T709
T710T710

T711T711

T712T712

MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
MCH_CFG_3

1

MCH_CFG_4

1

MCH_CFG_5
MCH_CFG_6

1

MCH_CFG_7
MCH_CFG_8

1

MCH_CFG_9
MCH_CFG_10

1

MCH_CFG_11
MCH_CFG_12

1

MCH_CFG_13

1

MCH_CFG_14

1

MCH_CFG_15

1

MCH_CFG_16
MCH_CFG_17

1

MCH_CFG_18
MCH_CFG_19
MCH_CFG_20

1

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1

PM_THRMTRIP#

ICH_PWROK

RST_IN#_MCH

MCH_ICH_SYNC#
MCH_CLK_REQ#

AG11

AF11

G16

G15

G18

G28

AH33
AH34

BA41
BA40
BA39

AY41

AW41

AW1

F7

H7

J19

K30

J29
A41
A35
A34
D28
D27

K16
K18

J18
F18
E15
F15
E18
D19
D16

E16
D15

K15
C15
H16

H15

J25
K27

J26

F25
H26

G6

H28
H27
K28
H32

D1

C41

C1

BA3
BA2
BA1
B41

B2

AY1

A40

A4

A39

A3

RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
TV_DCONSEL_0
TV_DCONSEL_1
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#

SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC#
CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

CALISTOGA_Q137

CALISTOGA_Q137

RSVD

RSVD

DDR MUXINGCLK

DDR M UX INGC LK

CFG

CFG

PM

PM

MISC NC

MISC NC

DMI

DMI

(070123)Add 39ohm resisters

R715

R715
39Ohm

DAC_VSYNC_GM

DAC_HSYNC_GM

39Ohm

1 2

R716

R716
39Ohm

39Ohm

1 2

+3VS

M_VREF_MCH

+1.5VS

+1.5VS_PCIE

+1.8V

SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3

SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_OCDCOMP_0
SM_OCDCOMP_1

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP#

SM_RCOMP
SM_VREF_0

SM_VREF_1

G_CLKIN#

G_CLKIN

D_REFCLKIN#

D_REFCLKIN

D_REFSSCLKIN#

D_REFSSCLKIN

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

+3VS 4,5,9,11,12,13,14,15,19,20,21,22,25,26,27,28,29,30,33,37,40,43,50,52,60,61
M_VREF_MCH 14,15,16
+1.5VS 9,10,20,25,26,37,52

+1.5VS_PCIE 9
+1.8V 10,14,15,16,37,53

M_CLK_DDR0

AY35

M_CLK_DDR1

AR1

M_CLK_DDR2

AW7

M_CLK_DDR3

AW40

M_CLK_DDR#0

AW35

M_CLK_DDR#1

AT1

M_CLK_DDR#2

AY7

M_CLK_DDR#3

AY40

M_CKE0

AU20

M_CKE1

AT20

M_CKE2

BA29

M_CKE3

AY29

M_CS#0

AW13

M_CS#1

AW12

M_CS#2

AY21

M_CS#3

AW21

M_OCDCOMP0

AL20

M_OCDCOMP1

AF10

M_ODT0

BA13

M_ODT1

BA12

M_ODT2

AY20

M_ODT3

AU21

M_RCOMP#

AV9

M_RCOMP

AT9

M_VREF_MCH

AK1
AK41

CLK_MCH_3GPLL#

AF33

CLK_MCH_3GPLL

AG33

CLK_UMA_96M#

A27

CLK_UMA_96M

A26

CLK_LCD_SSCG#

C40

CLK_LCD_SSCG

D41

DMI_TXN0

AE35

DMI_TXN1

AF39

DMI_TXN2

AG35

DMI_TXN3

AH39

DMI_TXP0

AC35

DMI_TXP1

AE39

DMI_TXP2

AF35

DMI_TXP3

AG39

DMI_RXN0

AE37

DMI_RXN1

AF41

DMI_RXN2

AG37

DMI_RXN3

AH41

DMI_RXP0

AC37

DMI_RXP1

AE41

DMI_RXP2

AF37

DMI_RXP3

AG41

DAC_VSYNC_BUF 28

DAC_HSYNC_BUF 28

M_CLK_DDR0 14
M_CLK_DDR1 14
M_CLK_DDR2 15
M_CLK_DDR3 15

M_CLK_DDR#0 14
M_CLK_DDR#1 14
M_CLK_DDR#2 15
M_CLK_DDR#3 15

Layout Note:
Route as short as possible

R711 Do Not Stuff@R711 Do Not Stuff@

12
12

R712 Do Not Stuff@R712 Do Not Stuff@

R713 80.6Ohm 1%R713 80.6Ohm 1%

1 2
1 2

R714 80.6Ohm 1%R714 80.6Ohm 1%

GND

+1.8V

GND

CLK_MCH_3GPLL# 5
CLK_MCH_3GPLL 5
CLK_UMA_96M# 5
CLK_UMA_96M 5
CLK_LCD_SSCG# 5
CLK_LCD_SSCG 5

DMI_TXN[0..3] 18

DMI_TXP[0..3] 18

DMI_RXN[0..3] 18

DMI_RXP[0..3] 18

M_CKE[0..3] 14,15,16
M_CS#[0..3] 14,15,16
M_ODT[0..3] 14,15,16

PCMCIA

PCMCIA

PCMCIA

Title :

Title :

Title :

Calistoga PCI-E (2)

Calistoga PCI-E (2)

Calistoga PCI-E (2)

Horng Chou

Horng Chou

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

TERESA

TERESA

TERESA

Engineer:

Horng Chou

Rev

Rev

Rev

1.1

1.1

7 57Tuesday, February 06, 2007

7 57Tuesday, February 06, 2007

7 57Tuesday, February 06, 2007

1

1.1

5

D D

U601D

AJ35

AJ34
AM31
AM33

AJ36

AK35

AJ32

AH31
AN35
AP33
AR31
AP31

AN38
AM36
AM34

AN33

AK26

AL27
AM26

AN24

AK28

AL28
AM24

AP26

AP23

AL22

AP21

AN20

AL23

AP24

AP20

AT21

AR12

AR14

AP13

AP12

AT13

AT12

AL14

AL12

AW2

AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2

AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8

U601D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

CALISTOGA_Q137

CALISTOGA_Q137

DDR SYSTEM MEMORY A

DDR SYSTEM M EMORY A

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23

C C

B B

M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

4

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

SA_WE#

AU12
AV14
BA20

AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

AW14
AK23
AK24
AY14

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CAS#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_RAS#
M_A_RCVENIN#
M_A_RCVENOUT#
M_A_WE#

M_A_DM[0..7] 14
M_A_DQS[0..7] 14
M_A_DQS#[0..7] 14
M_A_A[0..13] 14,16
M_A_DQ[0..63] 14

M_A_BS0 14,16
M_A_BS1 14,16
M_A_BS2 14,16

M_A_CAS# 14,16

T802T802

1

T801T801

1

M_A_WE# 14,16

3

U601E

AK39

AJ37

AP39

AR41

AJ38

AK38

AN41

AP41
AT40
AV41

AU38

AV38

AP38
AR40
AW38

AY38

BA38

AV36
AR36

AP36

BA36
AU36

AP35

AP34

AY33

BA33

AT31
AU29
AU31
AW31

AV29
AW29
AM19

AL19

AP14
AN14
AN17
AM16

AP15

AL15

AJ11

AH10
AN10

AK13
AH11

AK10

BA10
AW10

BA4

AW4

AY10

AY9

AW5

AY5
AV4

AR5

AK4
AK3
AT4
AK5

AJ9

AJ8

AJ5
AJ3

U601E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

CALISTOGA_Q137

CALISTOGA_Q137

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

2

DDR SYSTEM MEMORY B

DDR SYSTEM M EMORY B

SB_RCVENOUT#

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVENIN#

SB_WE#

AT24
AV23
AY28

AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

AU23
AK16
AK18
AR27

M_B_BS#0
M_B_BS#1
M_B_BS#2

M_B_CAS#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_RAS#
M_B_RCVENIN#
M_B_RCVENOUT#
M_B_WE#

M_B_BS0 15,16
M_B_BS1 15,16
M_B_BS2 15,16

M_B_CAS# 15,16

T803T803

1

T804T804

1

M_B_DM[0..7] 15
M_B_DQS[0..7] 15
M_B_DQS#[0..7] 15
M_B_A[0..13] 15,16
M_B_DQ[0..63] 15

1

M_B_RAS# 15,16M_A_RAS# 14,16

M_B_WE# 15,16

A A

PCMCIA

PCMCIA

PCMCIA

Title :

Title :

Title :

Calistoga DDR2 (3)

Calistoga DDR2 (3)

Calistoga DDR2 (3)

Horng Chou

Horng Chou

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

TERESA

TERESA

TERESA

Engineer:

Horng Chou

Rev

Rev

Rev

1.1

1.1

8 57Tuesday, February 06, 2007

8 57Tuesday, February 06, 2007

8 57Tuesday, February 06, 2007

1

1.1

5

Layout Note:
Place filter components

+1.5VS

close to GMCH

L902

L902

120Ohm/100Mhz

120Ohm/100Mhz

D D

L901

L901

30Ohm/100Mhz

30Ohm/100Mhz

L903

L903
80Ohm/100Mhz

80Ohm/100Mhz

(070131)
220UF=>150UF

L904

L904

30Ohm/100Mhz

30Ohm/100Mhz

C C

L906

L906

30Ohm/100Mhz

30Ohm/100Mhz

L907

L907

120Ohm/100Mhz

120Ohm/100Mhz

L908

L908

120Ohm/100Mhz

120Ohm/100Mhz

B B

Layout Note:
Caps should be on Top layer

21

12

+

+

CE902

CE902
Do Not Stuff

Do Not Stuff

@

@

GND

21

12

C904

C904

0.1UF/10V

0.1UF/10V

GND

21

12

+

+

CE903

CE903
150UF/4V

150UF/4V

GND

21

12

+

CE904

Do Not Stuff

Do Not Stuff

GND

21

12

+

CE905

Do Not Stuff

Do Not Stuff

GND

21

12

C923

C923

Do Not Stuff

Do Not Stuff

@

@

GND

21

12

C927

C927

Do Not Stuff

Do Not Stuff

@

@

GND

@+CE904

@

@+CE905

@

12

C902

C902
10UF/10V

10UF/10V

GND

12

10UF/10V

10UF/10V

GND

12

C909

C909

0.1UF/10V

0.1UF/10V

GND

12

C912

C912

0.1UF/10V

0.1UF/10V

GND

12

C918

C918

0.1UF/10V

0.1UF/10V

GND

12

C924

C924

0.1UF/10V

0.1UF/10V

GND

12

C928

C928

0.1UF/10V

0.1UF/10V

GND

C905

C905

(070131)C923, C927:unmount

+2.5VS

VCC_SYNC
Pin H22

12

C932

C932

0.1UF/10V

0.1UF/10V

R905

R905

10Ohm

10Ohm

A A

70 mA

L909

L909

21

120Ohm/100Mhz

120Ohm/100Mhz

+VCCP_GMCH_R

12

VCCA_CRTDAC
Pin E21 F21

12

0.022UF/25V

0.022UF/25V

GND GND

VCCA_LVDS
Pin A38 10 mA

12

C933

C933

0.01UF/25V

0.01UF/25V

GND GND

GND GNDGND

3

12

C901

C901

C946

C946

0.1UF/10V

0.1UF/10V

5

+1.5VS_VCCAUX

12

C934

C934

0.1UF/10V

0.1UF/10V

D902

D902

BAT54C

BAT54C

+1.5VS_PCIE

VCC3G

12

C903

C903
10UF/10V

10UF/10V

+1.5VS_3GPLL

GND

VCCA_3GPLL

VCCAUX
1900 mA

+1.5VS_DPLLA

VCCA_DPLLA
50 mA

+1.5VS_DPLLB

VCCA_DPLLB
50 mA

+1.5VS_HPLL

VCCA_HPLL
45 mA

+1.5VS_MPLL

VCCA_MPLL
45 mA

VCCA_3GBG
Pin G41 2 mA

1
2

+2.5VS_CRTDAC

Layout Note:
These Caps should
be within 250 mils of
edge of GMCH

+VCCP

1500 mA

+1.5VS

VCCD_LVDS 20 mA
Pin A28 B28 C28

12

C910

C910

0.1UF/10V

0.1UF/10V

GND

+1.5VS

VCCD_TVDAC
Pin D21

12

C913

C913

0.022UF/25V

0.022UF/25V

GND

+1.5VS

VCCD_QTVDAC
H19 C28

12

C919

C919

0.022UF/25V

0.022UF/25V

GND

Layout Note:
These Caps should be within
250 mils of edge of GMCH

Layout Note:

0.1uF caps in 1.5VS_xPLL
need to be located as edge
caps within 200 mils.

VCCTX_LVDS 60 mA
Pin A30 B30 C30

12

C935

C935

0.1UF/10V

0.1UF/10V

GND

+VCCP_GMCH

12

C936

C936

0.1UF/10V

0.1UF/10V

4

GMCH VCORE

+1.05VS

JP902

JP902

3500 mA

1 2

Do Not Stuff

Do Not Stuff

@

@

JP901

JP901

1 2

Do Not Stuff

Do Not Stuff

@

@

12

C911

C911
10UF/10V

10UF/10V

GND

12

C914

C914

0.1UF/10V

0.1UF/10V

GND

24 mA

12

C920

C920

0.1UF/10V

0.1UF/10V

GND

12

C937

C937

4.7UF/10V

4.7UF/10V

+3VS

VCC_HV 40 mA
Pin A23 B23 B25

12

C944

C944
10UF/10V

10UF/10V

GND

4

+VCCP_GMCH+VCCP

+1.5VS_3GPLL

+2.5VS

+2.5VS_CRTDAC

+1.5VS_DPLLA

GND

+1.5VS_DPLLB

+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL

+1.5VS

+1.5VS

TV OUT disable way

Layout Note:
These 0.1uF caps should
be placed within 200 mils
of edge

12

C945

C945

0.1UF/10V

0.1UF/10V

GND

+1.5VS

+1.5VS

+1.5VS

+3VS

+1.5VS

+1.5VS_VCCAUX

+1.5VS_PCIE

GND

GND

+2.5VS

GND

AJ41

AB41

AC33

G41

G21

G20

AH1
AH2

AK31
AF31
AE31
AC31

AL30

AK30

AJ30

AH30

AG30

AF30
AE30
AD30
AC30

AG29

AF29
AE29
AD29
AC29

AG28

AF28
AE28
AH22

AJ21

AH21

AJ20
AH20
AH19

AH15
AH14

AG14

AF14
AE14

AF13
AE13
AF12
AE12
AD12

H22
C30

B30
A30

Y41
V41
R41
N41

L41

H41
F21

E21

B26
C39
AF1

A38
B39

AF2
H20

E19
F19
C20
D20
E20
F20

A28
B28
C28

D21
A23

B23
B25

H19

P19
P16

P15

Y14

U601H

U601H

VCCSYNC
VCC_TXLVDS0

VCC_TXLVDS1
VCC_TXLVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC
VCC_HV0

VCC_HV1
VCC_HV2

VCCD_QTVDAC
VCCAUX0

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

CALISTOGA_Q137

CALISTOGA_Q137

3

3

POWER

POWER

+VCCP_AGTL+
+VCCP_GMCH

+1.5VS_PCIE

+3VS
+2.5VS
+1.5VS

VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76

2

+VCCP_AGTL+ 2,3,5,6
+VCCP_GMCH 10
+1.5VS_PCIE 7

+3VS 4,5,7,11,12,13,14,15,19,20,21,22,25,26,27,28,29,30,33,37,40,43,50,52,60,61

+2.5VS 37,54

+1.5VS 7,10,20,25,26,37,52

+VCCP_AGTL+

AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

NOTE:0.1UF CAPS USED IN +1.5VS,
+3.3VS
+2.5VS should be placed within
200 mils of edge.

VTTLF_CAP3

C929

C929

0.47UF/16V

0.47UF/16V

VTTLF_CAP2
VTTLF_CAP1

C938

C938

0.47UF/16V

0.47UF/16V

+VCCP_AGTL+

Layout Note:
Place in cavity

12

GND

12

GND

GND

2

12

C906

C906

4.7UF/10V

4.7UF/10V

0.22UF/6.3V

0.22UF/6.3V

12

C939

C939

Layout Note:
Place on the edge

800 mA

12

+

+

12

C907

C907

2.2UF/6.3V

2.2UF/6.3V

12

C908

C908

0.22UF/6.3V

0.22UF/6.3V

GND

CE901

CE901

100UF/2.5V

100UF/2.5V

Remove TV OUT Power

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

TERESA

TERESA

TERESA

1

(070118)
change into 11G08D210791

Title :

Title :

Title :

Calistoga Power (4)

Calistoga Power (4)

Calistoga Power (4)

Horng Chou

Horng Chou

Engineer:

Engineer:

Engineer:

Horng Chou

9 57Tuesday, February 06, 2007

9 57Tuesday, February 06, 2007

1

9 57Tuesday, February 06, 2007

Rev

Rev

Rev

1.1

1.1

1.1

5

U601F

U601F

AA33

VCC_0

W33

VCC_1

P33

VCC_2

N33

VCC_3

L33

VCC_4

J33

VCC_5

AA32

VCC_6

Y32

VCC_7

W32

VCC_8

V32

D D

C C

B B

A A

P32
N32

M32

L32

J32

AA31

W31

V31
T31
R31
P31
N31

M31

AA30

Y30

W30

V30
U30
T30
R30
P30
N30

M30

L30

AA29

Y29

W29

V29
U29
R29
P29

M29

L29
AB28
AA28

Y28

V28

U28

T28

R28

P28

N28

M28

L28

P27

N27

M27

L27

P26

N26

L26

N25

M25

L25

P24

N24

M24
AB23
AA23

Y23
P23
N23

M23

L23
AC22
AB22

Y22

W22

P22

N22

M22

L22
AC21
AA21

W21

N21

M21

L21
AC20
AB20

Y20

W20

P20

N20

M20

L20
AB19
AA19

Y19

N19

M19

L19

N18

M18

L18

P17

N17

M17

N16

M16

L16

CALISTOGA_Q137

CALISTOGA_Q137

VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110

5

VCC

VCC

VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107

VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8

VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

VCC_SM_1
VCC_SM_2

C1002

C1002

0.47UF/16V

0.47UF/16V

VCC_SM_3

VCC_SM_4

VCC_SM_5
VCC_SM_6

0.47UF/16V

0.47UF/16V

+1.8V

C1013

C1013

4

+VCCP_GMCH+VCCP_GMCH

12

12

C1003

C1003

0.47UF/16V

0.47UF/16V

GND GND

12

C1004

C1004

0.47UF/16V

0.47UF/16V

GND

12

C1005

C1005

0.47UF/16V

0.47UF/16V

GND

+VCCP_GMCH

12

+

+

CE1001

CE1001
220UF/2V

220UF/2V

11G08D222795

11G08D222795

(070205)
changed to 11G08D222795 220uF/2V

12

12

C1014

C1014

0.47UF/16V

0.47UF/16V

GNDGND

4

U601G

U601G

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

CALISTOGA_Q137

CALISTOGA_Q137

VCC(GMCH Core)

+1.5VS (5500 mA) or +1.05VS (3500 mA)

12

CE1002

CE1002

+

+

12

C1006

C1006

10UF/10V

10UF/10V

Do Not Stuff

Do Not Stuff

@

@

+1.8V

12

C1012

C1012

10UF/10V

10UF/10V

12

C1007

C1007

10UF/10V

10UF/10V

Layout Note:
Place in cavity

12

C1001

C1001

10UF/10V

10UF/10V

NCTF

NCTF

12

1UF/10V

1UF/10V

12

+

CE1003

150UF/4V

150UF/4V

C1008

C1008

N/A+CE1003

N/A

12

0.22UF/6.3V

0.22UF/6.3V

3200 mA

12

+

+

CE1004

CE1004

Do Not Stuff

Do Not Stuff

@

@

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

C1009

C1009

GND

3

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

12

C1010

C1010

0.22UF/6.3V

0.22UF/6.3V

12

+

+

CE1005

CE1005

Do Not Stuff

Do Not Stuff

@

@

3

12

0.22UF/6.3V

0.22UF/6.3V

GND

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

C1011

C1011

GND

+1.5VS

GND

AV10
AP10

AL10

AJ10
AG10
AC10

W10
BA9

AW9
AR9
AH9
AB9

AG8
AD8
AA8

BA7
AV7
AP7

AH7
AC7

AG6
AD6
AB6

AV5
AD5
AR4

AP4

AW3
AV3

AH3
AG3

AD3
AC3
AA3

AR2
AP2
AK2

AD2
AB2

J11
D11
B11

U10

Y9
R9
G9
E9
A9

U8
K8
C8

AL7
AJ7

AF7

R7
G7
D7

Y6
U6
N6
K6
H6
B6

AF5
AY4

AL4
AJ4

Y4
U4
R4

J4

F4
C4

AY3

AL3

AF3

G3

AT2

AJ2

Y2
U2

T2
N2

J2
H2

F2
C2

AL1

U601J

U601J

VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

CALISTOGA_Q137

CALISTOGA_Q137

+1.5VS

+1.8V

+VCCP_GMCH

2

VSS

VSS

+1.5VS 7,9,20,25,26,37,52
+1.8V 7,14,15,16,37,53
+VCCP_GMCH 9

2

VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272

AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11

GND

1

U601I

U601I

AK34

VSS_97

AG34

VSS_98

AF34

VSS_99

AE34

VSS_100

AC34

VSS_101

C34

VSS_102

AW33

VSS_103

AV33

VSS_104

AR33

VSS_105

AE33

VSS_106

AB33

VSS_107

Y33

VSS_108

V33

VSS_109

T33

VSS_110

R33

VSS_111

M33

VSS_112

H33

VSS_113

G33

VSS_114

F33

VSS_115

D33

VSS_116

B33

VSS_117

AH32

VSS_118

AG32

VSS_119

AF32

VSS_120

AE32

VSS_121

AC32

VSS_122

AB32

VSS_123

G32

VSS_124

B32

VSS_125

AY31

VSS_126

AV31

VSS_127

AN31

VSS_128

AJ31

VSS_129

AG31

VSS_130

AB31

VSS_131

Y31

VSS_132

AB30

VSS_133

E30

VSS_134

AT29

VSS_135

AN29

VSS_136

AB29

VSS_137

T29

VSS_138

N29

VSS_139

K29

VSS_140

G29

VSS_141

E29

VSS_142

C29

VSS_143

B29

VSS_144

A29

VSS_145

BA28

VSS_146

AW28

VSS_147

AU28

VSS_148

AP28

VSS_149

AM28

VSS_150

AD28

VSS_151

AC28

VSS_152

W28

VSS_153

J28

VSS_154

E28

VSS_155

AP27

VSS_156

AM27

VSS_157

AK27

VSS_158

J27

VSS_159

G27

VSS_160

F27

VSS_161

C27

VSS_162

B27

VSS_163

AN26

VSS_164

M26

VSS_165

K26

VSS_166

F26

VSS_167

D26

VSS_168

AK25

VSS_169

P25

VSS_170

K25

VSS_171

H25

VSS_172

E25

VSS_173

D25

VSS_174

A25

VSS_175

BA24

VSS_176

AU24

VSS_177

AL24

VSS_178

AW23

VSS_179

GND

CALISTOGA_Q137

CALISTOGA_Q137

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

VSS

VSS

TERESA

TERESA

TERESA

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

AC41

VSS_0

AA41

VSS_1

W41

VSS_2

T41

VSS_3

P41

VSS_4

M41

VSS_5

J41

VSS_6

F41

VSS_7

AV40

VSS_8

AP40

VSS_9

AN40

VSS_10

AK40

VSS_11

AJ40

VSS_12

AH40

VSS_13

AG40

VSS_14

AF40

VSS_15

AE40

VSS_16

B40

VSS_17

AY39

VSS_18

AW39

VSS_19

AV39

VSS_20

AR39

VSS_21

AN39

VSS_22

AJ39

VSS_23

AC39

VSS_24

AB39

VSS_25

AA39

VSS_26

Y39

VSS_27

W39

VSS_28

V39

VSS_29

T39

VSS_30

R39

VSS_31

P39

VSS_32

N39

VSS_33

M39

VSS_34

L39

VSS_35

J39

VSS_36

H39

VSS_37

G39

VSS_38

F39

VSS_39

D39

VSS_40

AT38

VSS_41

AM38

VSS_42

AH38

VSS_43

AG38

VSS_44

AF38

VSS_45

AE38

VSS_46

C38

VSS_47

AK37

VSS_48

AH37

VSS_49

AB37

VSS_50

AA37

VSS_51

Y37

VSS_52

W37

VSS_53

V37

VSS_54

T37

VSS_55

R37

VSS_56

P37

VSS_57

N37

VSS_58

M37

VSS_59

L37

VSS_60

J37

VSS_61

H37

VSS_62

G37

VSS_63

F37

VSS_64

D37

VSS_65

AY36

VSS_66

AW36

VSS_67

AN36

VSS_68

AH36

VSS_69

AG36

VSS_70

AF36

VSS_71

AE36

VSS_72

AC36

VSS_73

C36

VSS_74

B36

VSS_75

BA35

VSS_76

AV35

VSS_77

AR35

VSS_78

AH35

VSS_79

AB35

VSS_80

AA35

VSS_81

Y35

VSS_82

W35

VSS_83

V35

VSS_84

T35

VSS_85

R35

VSS_86

P35

VSS_87

N35

VSS_88

M35

VSS_89

L35

VSS_90

J35

VSS_91

H35

VSS_92

G35

VSS_93

F35

VSS_94

D35

VSS_95

AN34

VSS_96

GND

Clistoga GND (5)

Clistoga GND (5)

Clistoga GND (5)

Horng Chou

Horng Chou

Horng Chou

10 57Tuesday, February 06, 2007

10 57Tuesday, February 06, 2007

10 57Tuesday, February 06, 2007

Rev

Rev

Rev

1.1

1.1

1.1

5

4

3

2

1

MCH_CFG_57

12

R1101

R1101
Do Not Stuff

Do Not Stuff

r0402_h16

GND

GND

GND

GND

r0402_h16

12

R1104

R1104
Do Not Stuff

Do Not Stuff

r0402_h16

r0402_h16

12

R1105

R1105
Do Not Stuff

Do Not Stuff

r0402_h16

r0402_h16

12

R1107

R1107
Do Not Stuff

Do Not Stuff

r0402_h16

r0402_h16

D D

MCH_CFG_77

C C

B B

MCH_CFG_97

MCH_CFG_117

CFG5 : DMI X2 Select

LOW = DMI X 2

@

@

HIGH = DMI X 4 (Default)

CFG7 : CPU STRAP

LOW = Reserved

@

@

HIGH = Mobility CPU (Default)

CFG9 : PCIE GRAPHIC LANE

@

@

HIGH = NORMAL OPERATION (Default)

CFG11 : Reserved but need to be pull low

@

@

MCH_CFG_167

12

R1102

R1102
Do Not Stuff

Do Not Stuff

r0402_h16

r0402_h16

GND

+3VS

12

R1103
Do Not Stuff

Do Not Stuff

r0402

r0402

MCH_CFG_187

+3VS

12

MCH_CFG_197

(061215)Remove +2.5VS power supply

CFG16 : FSB DYNAMIC ODT

LOW = Dynamic ODT Disabled

@

@

HIGH = Dynamic ODT Enabled (Default)

CFG18 : GMCH Core Voltage Level

LOW = 1.05V

HIGH = 1.5V (default)

@R1103

@

CFG19 : DMI LANE REVERSAL

LOW = NORMALLOW = REVERSE LANES
HIGH = LANES REVERSED

R1106

@

R1106

@

Do Not Stuff

Do Not Stuff

r0402

r0402

CFG

2:0
4:3

5
6

7
8

9
11:10

13:12

15:14

16
17

SDVO_C
TRLDATA

18

19

20

CFG[17..3] have internal pullup resistors.
CFG[19..18] have internal pulldown resistors.
SDVOCRTL_DATA has internal pulldown
resistors.

All are sampled with respect to the
leading edge of the GMCH PWROK

FSB Freq select

DMI X 2 Select

CPU Strap

PCIE Graphics
Lane Reversal

XOR/ALLZ

FSB Dynamic ODT

SDVO Present

VCC select
DMI Lane

Reversal
SDVO/PCIE
concurrent

001 = FSB533
011 = FSB667

0 = DMI X 2
1 = DMI X 4 (Default)

0 = Reserved
1 = Mobile CPU (Default)

0 = Reverse Lanes
1 = Normal (Default)

00 = Partial Clock Gating Disable
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
11 = Normal operation (Default)

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = No SDVO Card Present (Default)
1 = SDVO Card Present
0 = 1.05V (Default)
1 = 1.5V
0 = Normal (Default)
1 = Reverse Lanes
0 = Only SDVO or PCIE x1 is
operational(Default)
1 = SDVO and PCIE x1 are operating
simultaneously via the PEG port

A A

PCMCIA

PCMCIA

PCMCIA

Title :

Title :

Title :

Calistoga Strapping

Calistoga Strapping

Calistoga Strapping

Horng Chou

Horng Chou

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

TERESA

TERESA

TERESA

Engineer:

Horng Chou

11 57Tuesday, February 06, 2007

11 57Tuesday, February 06, 2007

11 57Tuesday, February 06, 2007

1

Rev

Rev

Rev

1.1

1.1

1.1

5

LCD Panel Power

R1202

R1202
100KOhm

100KOhm

+12VS

12

R1203

R1203
22kOhm

22kOhm

+3VSLCD_G

32

3

3

D

D

1

1

1

G

G

S

S

2

2

GND

Q1203

Q1203
2N7002

2N7002

+3VSLCD_DG

GND

12

C1204

C1204

1UF/25V

1UF/25V

12

Q1202

Q1202

2N7002

2N7002

R1204

R1204
100KOhm

100KOhm

+3V

12

32

3

3

D

D

1

1

1

G

G

S

S

2

2

GND

D D

L_VDDEN7

GND

C C

Q1201

Q1201

1
2
3

G

G

SI3456BDV

SI3456BDV

4

3~3.6V
Full Active: 410 mA(Max. 500 mA)

3~3.6V
S0-S1 M: 410 mA(Max. 500 mA)

+3VS

12

12

C1202

C1202

C1203

C1203

0.1UF/10V

0.1UF/10V

0.01UF/25V

0.01UF/25V

L1202

+3VSLCD

GND

L1202
80Ohm/100Mhz

80Ohm/100Mhz

12

0.1UF/10V

0.1UF/10V

21

C1201

C1201

R1206

R1206
120Ohm

120Ohm

3

3

1

1

1

G

G

2

2

GND

(070124)Mount R1206 and Q1204

1 2
32

D

D

Q1204

Q1204
2N7002

2N7002

S

S

GND

12

12

C1205

C1205

10UF/10V

10UF/10V

1UF/10V

1UF/10V

Refer to V1J

6

D

D

5

S

S

4

C1206

C1206

+3VS_LCD

12

0.1UF/10V

0.1UF/10V

GND

3

C1207

C1207

2

Remove CMOS Camera(USB4)

1

LCD Backlight Control

Inverter Board

BIOS
LCD_BACKOFF#
When user push "Fn+F7" button
BIOS active this pin to turn On/Off backlight

EC
INVTER_DA:
EC output D/A signal ( adjust voltage level) to
adjust backlight

+3VS +3VAAC_BAT_SYS

built in 15.4W
LCD Panel

12

R1205

12

C1214

C1214
1000PF/50V

1000PF/50V

R1205
10KOhm

10KOhm

r0402

r0402

L1210

L1210
1KOhm

1KOhm

1 2

12

C1215

C1215

1000PF/50V

1000PF/50V

4

LCD_BACKOFF#29
PCI_RST#18,34,43

B B

A A

L_BKLTEN7
LID_SW#29

L_BKLTCTL7

INVTER_DA29

BRIGHT_PWM29

5

LCD_BACKOFF#
PCI_RST#
L_BKLTEN
LID_SW#

L1209

L1209

120Ohm/100Mhz

120Ohm/100Mhz

L1211

L1211

Do Not Stuff

Do Not Stuff

@

@

L1213

L1213

Do Not Stuff

Do Not Stuff

@

@

21

21

21

D1204RB717FD1204RB717F

1
2
1
2

D1201RB717FD1201RB717F

L1212

L1212

120Ohm/100Mhz

120Ohm/100Mhz

3

3

21

BL_EN_L

12

C1216

C1216

0.1UF/25V

0.1UF/25V

L1207

L1207

l0805_h43

l0805_h43

80Ohm/100Mhz

80Ohm/100Mhz

2 1

12

C1217

C1217

1UF/25V

1UF/25V

12

C1218

C1218

1000PF/50V

1000PF/50V

L1208

L1208

l0805_h43

l0805_h43

80Ohm/100Mhz

80Ohm/100Mhz

2 1

LID_SW#_CON
ADJ_BL_CON
BL_EN_CON
+3VA_CON

12

C1219

C1219

0.1UF/10V

0.1UF/10V

GND

AC_INV

Combine Inverter interface
into LVDS interface

21

L1206

L1206

80Ohm/100Mhz

80Ohm/100Mhz

(061206,EMI)
Add bead

3

+3VS

80Ohm/100Mhz

80Ohm/100Mhz

LCD LVDS & INVERTER Interface

Delete LVDS channel B

Rearrange pin location(061201)

+3VS_LVDS

21

12

L1203

L1203

+3VS_LCD

GND

C1208

C1208

0.1UF

0.1UF

c0402

c0402

CON1202

CON1202

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29

GND

(061220)Change CON1202 into
PN:12G17001030G

2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

WTOB_CON_30P

WTOB_CON_30P

SIDE2

SIDE1

32
2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

EDID_CLK_LCD

26

26

EDID_DAT_LCD

28

28

30

30

31

+3VS_LCD

GND

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

LVDS_L0N 7
LVDS_L0P 7

LVDS_L1N 7
LVDS_L1P 7

LVDS_L2N 7
LVDS_L2P 7

LVDS_LCLKN 7
LVDS_LCLKP 7

12

GND

12

GND

TERESA

TERESA

TERESA

C1209

C1209

47PF/50V

47PF/50V

N/A

N/A
c0402

c0402

C1210

C1210

47PF/50V

47PF/50V

N/A

N/A
c0402

c0402

L1204 33OhmL1204 33Ohm

1 2

L1205 33OhmL1205 33Ohm

1 2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

EDID_CLK 7

EDID_DAT 7

LVDS & INVERTER

LVDS & INVERTER

LVDS & INVERTER

Horng Chou

Horng Chou

Horng Chou

12 57Tuesday, February 06, 2007

12 57Tuesday, February 06, 2007

12 57Tuesday, February 06, 2007

Rev

Rev

Rev

1.1

1.1

1.1

5

4

3

2

1

CRT OUT

D D

C C

D1309

D1309

2

+3VS

1

BAV99

BAV99

GND

D1307

+3VS

D1307

2
1

BAV99

BAV99

GND

D1308

D1308

2
1

BAV99

BAV99

GND

D1305

D1305

2
1

BAV99

BAV99

GND

D1301

D1301

2
1

BAV99

BAV99

GND

4

D1306

B B

+5VS_CRT

+3VS

A A

D1306

1 2

+5VS +5VS_CRT

1N4148W

1N4148W

Remove Bidirectional Port(061201)

R1309 6.8KOhmR1309 6.8KOhm
R1310 6.8KOhmR1310 6.8KOhm

R1311 2.2KOhmR1311 2.2KOhm
R1312 2.2KOhmR1312 2.2KOhm

1 2
1 2

1 2
1 2

5

DDC2BD_5
DDC2BC_5

CRT_DDC_DATA
CRT_DDC_CLK

+3VS

+3VS

+3VS

3

3

3

3

3

CRT_RED

CRT_GREEN

CRT_BLUE

HSYNC_5

VSYNC_5

CRT_RED7

CRT_GREEN7

CRT_BLUE7

(061225)Modify into +12VS

(061225)Modify into +12VS

CRT_RED CRT_R_CON

CRT_GREEN

CRT_HSYNC28

+12VS

CRT_VSYNC28

CRT_DDC_DATA7

CRT_DDC_CLK7

+12VS

3

(061206,EMI)
Add L1307, L1308, L1309
(070205) tune performance
changed to 09G023821009 0.082uH

L1304

L1304

0.082uH

0.082uH

1 4

GND

L1305

L1305

0.082uH

0.082uH

1 4

GND

L1306

L1306

0.082uH

0.082uH

1 4

GND

D

D

HSYNC_5

32

3

3

3

3

VSYNC_5

32

D

D

D

D

DDC2BD_5 DDC_DAT_CON

32

3

3

3

3

DDC2BC_5

32

D

D

1 2

1 2

1 2

R1301

R1301
150Ohm

150Ohm

r0402

r0402

R1305

R1305
150Ohm

150Ohm

r0402

r0402

R1306

R1306
150Ohm

150Ohm

r0402

r0402

C1309

C1309
10PF/50V

10PF/50V

1 2

GND

C1311

C1311
10PF/50V

10PF/50V

1 2

GND

C1301

C1301
10PF/50V

10PF/50V

1 2

GND

Q1302

Q1302

2N7002

2N7002

S

S

2

2

G

G

1

1

1

1

1

1

G

G

2

2

S

S

2N7002

2N7002

Q1304

Q1304

Q1301

Q1301

2N7002

2N7002

S

S

2

2

G

G

1

1

1

1

1

1

G

G

2

2

S

S

2N7002

2N7002

Q1303

Q1303

21

L1307

L1307

Do Not Stuff

Do Not Stuff

2 3

@

@

21

L1308

L1308

Do Not Stuff

Do Not Stuff

2 3

@

@

21

L1309

L1309

Do Not Stuff

Do Not Stuff

2 3

@

@

R1307

R1307
39Ohm

39Ohm

1 2

R1308

R1308
39Ohm

39Ohm

1 2

R1313

R1313

1 2

0Ohm

0Ohm

R1314

R1314

1 2

0Ohm

0Ohm

checklist suggests 47ohm/100MHz

C1308

C1308
10PF/50V

10PF/50V

1 2

GND

CRT_G_CON

C1310

C1310
10PF/50V

10PF/50V

1 2

GND

CRT_B_CONCRT_BLUE

CRT_B_CON

C1312

C1312
10PF/50V

10PF/50V

1 2

GND

HSYNC_CON

C1313

C1313
22PF/50V

22PF/50V

1 2

GND

VSYNC_CON

C1314

C1314
22PF/50V

22PF/50V

1 2

(0670122)
Mount 10PF

GND

(070205) tune performance
changed to 11G232022004360 22pF

C1315

C1315
47PF/50V

47PF/50V

c0402

c0402

1 2

GND

DDC_CLK_CON

C1316

C1316
47PF/50V

47PF/50V

c0402

c0402

1 2

GND

2

(070201)
Remove 0om resister

CRT_R_CON
CRT_G_CON
CRT_B_CON

New addition for Teresa

+5VS_CRT

(070130)
Change fuse into 1A

F1302

F1302
1A/32V

1A/32V

1 2

12

C1317

C1317

0.1UF/10V

0.1UF/10V

GND

Change D-SUB into PN:12G10111015M

CON1302

CON1302

1617

6
1
7
2
8
3
9
4

10

5

GND

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

11
12
13
14
15

D_SUB_15P

D_SUB_15P

12G10111015M

TERESA

TERESA

TERESA

DDC_DAT_CON
HSYNC_CON
VSYNC_CON
DDC_CLK_CON

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

CRT & TV OUT

CRT & TV OUT

CRT & TV OUT

Horng Chou

Horng Chou

Horng Chou

13 57Tuesday, February 06, 2007

13 57Tuesday, February 06, 2007

13 57Tuesday, February 06, 2007

Rev

Rev

Rev

1.1

1.1

1.1

5

4

3

2

1

(061221)Change CON1401 into PN:12G02502200R

12

C1405

C1405

0.1UF/16V

0.1UF/16V

GND

M_VREF_MCH

12

C1410

C1410

0.1UF/16V

0.1UF/16V

GND

12

+

+

CE1402

CE1402
Do Not Stuff

Do Not Stuff

@

@

12

C1412

C1412

1UF/6.3V

1UF/6.3V

+1.8V

12

C1401

C1401

1UF/6.3V

1UF/6.3V

GND

Layout Note: Place these Caps near SO DIMM 0

(061221)Change CON1401 into PN:12G02502200R

M_CLK_DDR0

D D

C1406

C1406

PLACE NEAR SO-DIMM_1

Do Not Stuff

Do Not Stuff

1 2

@

@

M_CLK_DDR#0

M_CLK_DDR1

C1408

C1408

PLACE NEAR SO-DIMM_1

Do Not Stuff

Do Not Stuff

1 2

@

@

M_CLK_DDR#1

C C

SMBus Slave Address:A0H

GND

B B

M_A_A[0..13]8,16

M_A_BS28,16
M_A_BS08,16

M_A_BS18,16

M_CS#07,16
M_CS#17,16

M_CLK_DDR07

M_CLK_DDR#07

M_CLK_DDR17

M_CLK_DDR#17

M_CKE07,16

M_CKE17,16
M_A_CAS#8,16
M_A_RAS#8,16

M_A_WE#8,16

SMB_CLK_S5,15,19,25,26
SMB_DAT_S5,15,19,25,26

M_ODT07,16

M_ODT17,16

M_A_DM[0..7]8

M_A_DQS[0..7]8

M_A_DQS#[0..7]8

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

102
101
100

99
98
97
94
92
93
91

105

90
89

116

86
84
85

107
106
110
115

30

32
164
166

79

80
113
108
109
198
200
197
195

114
119

10

26

52

67
130
147
170
185

13

31

51

70
131
148
169
188

11

29

49

68
129
146
167
186

CON1401A

CON1401A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2

BA0
BA1
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

DDR_DIMM_200P

DDR_DIMM_200P

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_A_DQ0

5

M_A_DQ4

7

M_A_DQ2

17

M_A_DQ3

19

M_A_DQ1

4

M_A_DQ6

6

M_A_DQ5

14

M_A_DQ7

16

M_A_DQ12

23

M_A_DQ8

25

M_A_DQ9

35

M_A_DQ10

37

M_A_DQ13

20

M_A_DQ14

22

M_A_DQ11

36

M_A_DQ15

38

M_A_DQ16

43

M_A_DQ17

45

M_A_DQ18

55

M_A_DQ19

57

M_A_DQ20

44

M_A_DQ21

46

M_A_DQ22

56

M_A_DQ23

58

M_A_DQ24

61

M_A_DQ25

63

M_A_DQ26

73

M_A_DQ27

75

M_A_DQ28

62

M_A_DQ29

64

M_A_DQ30

74

M_A_DQ31

76

M_A_DQ37

123

M_A_DQ36

125

M_A_DQ34

135

M_A_DQ35

137

M_A_DQ33

124

M_A_DQ32

126

M_A_DQ38

134

M_A_DQ39

136

M_A_DQ40

141

M_A_DQ41

143

M_A_DQ42

151

M_A_DQ43

153

M_A_DQ45

140

M_A_DQ44

142

M_A_DQ46

152

M_A_DQ47

154

M_A_DQ48

157

M_A_DQ49

159

M_A_DQ50

173

M_A_DQ54

175

M_A_DQ52

158

M_A_DQ53

160

M_A_DQ51

174

M_A_DQ55

176

M_A_DQ60

179

M_A_DQ56

181

M_A_DQ57

189

M_A_DQ58

191

M_A_DQ61

180

M_A_DQ63

182

M_A_DQ62

192

M_A_DQ59

194

M_A_DQ[0..63] 8

SWAP

SWAP

SWAP

SWAP

SWAP

SWAP

12

0.1UF/16V

0.1UF/16V

12

C1403

C1403

C1402

C1402

0.1UF/16V

0.1UF/16V

+3VS

GND

C1409

C1409

2.2UF/6.3V

2.2UF/6.3V

VREF -> 10/10 mils

+1.8V +1.8V

12

GND

+1.8V

12

C1404

C1404

0.1UF/16V

0.1UF/16V

12

C1407

C1407

0.1UF/16V

0.1UF/16V

12

GND

+

+

CE1401

CE1401
Do Not Stuff

Do Not Stuff

@

@

GND

+1.8V

12

C1411

C1411

1UF/6.3V

1UF/6.3V

Layout Note: Place these Caps near SO DIMM 0

112
111
117

118

103
104
199

120

163

201
202

203
204

133
183

184

121
122
196
193

12

C1413

C1413

1UF/6.3V

1UF/6.3V

CON1401B

CON1401B

VDD1
VDD2
VDD3

96

VDD4

95

VDD5
VDD6

81

VDD7

82

VDD8

87

VDD9
VDD10

88

VDD11
VDD12

VDDSPD

83

NC1
NC2

50

NC3

69

NC4
NCTEST

1

VREF
GND0

GND1
NP_NC1

NP_NC2

47

VSS1
VSS2
VSS3

77

VSS4

12

VSS5

48

VSS6
VSS7

78

VSS8

71

VSS9

72

VSS10
VSS11
VSS12
VSS13
VSS14

8

VSS15

DDR_DIMM_200P

DDR_DIMM_200P

12

1UF/6.3V

1UF/6.3V

GND

C1414

C1414

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162

GND

GND

12

C1419

C1419

2.2UF/6.3V

2.2UF/6.3V

12

C1420

C1420

2.2UF/6.3V

2.2UF/6.3V

GND

12

C1421

C1421

2.2UF/6.3V

2.2UF/6.3V

12

GND GNDGND

C1422

C1422

2.2UF/6.3V

2.2UF/6.3V

12

C1423

C1423

2.2UF/6.3V

2.2UF/6.3V

SO-DIMM 0 is placed farther from the

A A

5

4

3

GMCH than SO-DIMM 1

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

TERESA

TERESA

TERESA

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

DDR2 SO-DIMM0

DDR2 SO-DIMM0

DDR2 SO-DIMM0

Horng Chou

Horng Chou

Horng Chou

14 57Tuesday, February 06, 2007

14 57Tuesday, February 06, 2007

14 57Tuesday, February 06, 2007

1

Rev

Rev

Rev

1.1

1.1

1.1

5

D D

SMBus Slave Address:A4H

M_CLK_DDR2

C1507

C1507

PLACE NEAR SO-DIMM_0

Do Not Stuff

Do Not Stuff

1 2

@

@

M_CLK_DDR#2

M_CLK_DDR3

C1509

C1509

PLACE NEAR SO-DIMM_0

Do Not Stuff

Do Not Stuff

1 2

@

@

C C

B B

A A

M_CLK_DDR#3

+3VS

10KOhm

10KOhm

R1501

R1501

1 2

GND

M_B_A[0..13]8,16

M_B_BS28,16
M_B_BS08,16

M_B_BS18,16

M_CS#27,16
M_CS#37,16

M_CLK_DDR37

M_CLK_DDR#37

M_CLK_DDR27

M_CLK_DDR#27

M_CKE27,16

M_CKE37,16
M_B_CAS#8,16
M_B_RAS#8,16

M_B_WE#8,16

SMB_CLK_S5,14,19,25,26
SMB_DAT_S5,14,19,25,26

M_ODT27,16

M_ODT37,16

M_B_DM[0..7]8

M_B_DQS[0..7]8

M_B_DQS#[0..7]8

+3VS_SET

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM6
M_B_DM7
M_B_DM5

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS6
M_B_DQS7
M_B_DQS5
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#6
M_B_DQS#7
M_B_DQS#5

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

4

M_B_DQ[0..63]8

(061227)Update PCB footprint
PN:12G025032008

CON1501A

CON1501A

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0#

115

S1#

30

CK0

32

CK0#

164

CK1

166

CK1#

79

CKE0

80

CKE1

113

CAS#

108

RAS#

109

WE#

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS#0

29

DQS#1

49

DQS#2

68

DQS#3

129

DQS#4

146

DQS#5

167

DQS#6

186

DQS#7

DDR_DIMM_200P

DDR_DIMM_200P

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

3

Address reference +1.8V, add four

0.1uF decoupling CAP.

12

C1502

C1502

0.1UF/16V

0.1UF/16V

c0402

c0402

GND

M_B_DQ[0..63]

M_B_DQ5

5

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

M_B_DQ0

7

M_B_DQ7

17

M_B_DQ3

19

M_B_DQ4

4

M_B_DQ1

6

M_B_DQ6

14

M_B_DQ2

16

M_B_DQ8

23

M_B_DQ9

25

M_B_DQ10

35

M_B_DQ11

37

M_B_DQ12

20

M_B_DQ13

22

M_B_DQ14

36

M_B_DQ15

38

M_B_DQ16

43

M_B_DQ17

45

M_B_DQ18

55

M_B_DQ19

57

M_B_DQ20

44

M_B_DQ21

46

M_B_DQ22

56

M_B_DQ23

58

M_B_DQ24

61

M_B_DQ25

63

M_B_DQ26

73

M_B_DQ27

75

M_B_DQ28

62

M_B_DQ29

64

M_B_DQ30

74

M_B_DQ31

76

M_B_DQ36

123

M_B_DQ32

125

M_B_DQ34

135

M_B_DQ35

137

M_B_DQ33

124

M_B_DQ37

126

M_B_DQ38

134

M_B_DQ39

136

M_B_DQ49

141

M_B_DQ53

143

M_B_DQ54

151

M_B_DQ55

153

M_B_DQ48

140

M_B_DQ52

142

M_B_DQ51

152

M_B_DQ50

154

M_B_DQ62

157

M_B_DQ57

159

M_B_DQ59

173

M_B_DQ58

175

M_B_DQ56

158

M_B_DQ60

160

M_B_DQ61

174

M_B_DQ63

176

M_B_DQ42

179

M_B_DQ47

181

M_B_DQ40

189

M_B_DQ45

191

M_B_DQ43

180

M_B_DQ46

182

M_B_DQ41

192

M_B_DQ44

194

SWAP

Layout Note: Place these Caps near SO DIMM 0

SWAP

SWAP

VREF -> 10/10 mils

+1.8V

12

C1510

C1510

0.1UF/16V

0.1UF/16V

+1.8V

+1.8V

12

12

C1503

C1503

0.1UF/16V

0.1UF/16V

c0402

c0402

GND GND GND

+3VS

12

C1506

C1506

0.1UF/16V

0.1UF/16V

GND

C1504

C1504

0.1UF/16V

0.1UF/16V

c0402

c0402

12

C1508

C1508

1UF/6.3V

1UF/6.3V

12

C1505

C1505

0.1UF/16V

0.1UF/16V

c0402

c0402

M_VREF_MCH

12

C1501

C1501

0.1UF/16V

0.1UF/16V

GND

Layout Note: Place these Caps near SO DIMM 0

12

12

C1512

C1512

C1511

C1511

0.1UF/16V

0.1UF/16V

0.1UF/16V

0.1UF/16V

Layout Note: Place these High-Freq decoupling Caps near the GMCH

12

C1514

C1514

0.1UF/16V

0.1UF/16V

c0402

c0402

GND

Layout Note: Place these CAPs near the GMCH

C1518

C1518

2.2UF/6.3V

2.2UF/6.3V

GND

12

C1519

C1519

2.2UF/6.3V

2.2UF/6.3V

12

GND

2

(061227)Update PCB footprint

+1.8V

PN:12G025032008

CON1501B

CON1501B

112

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

203

NP_NC1

204

NP_NC2

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

DDR_DIMM_200P

12

C1513

C1513

0.1UF/16V

0.1UF/16V

GND

12

C1520

C1520

2.2UF/6.3V

2.2UF/6.3V

12

GNDGND

DDR_DIMM_200P

C1516

C1516

0.1UF/16V

0.1UF/16V

c0402

c0402

GND

12

12

C1517

C1517

0.1UF/16V

0.1UF/16V

c0402

c0402

C1521

C1521

2.2UF/6.3V

2.2UF/6.3V

GND GND

12

C1515

C1515

0.1UF/16V

0.1UF/16V

c0402

c0402

GND

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

GNDGND

12

C1522

C1522

2.2UF/6.3V

2.2UF/6.3V

18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162

1

PCMCIA

PCMCIA

PCMCIA

Title :

Title :

Title :

DDR2 SO-DIMM1

DDR2 SO-DIMM1

DDR2 SO-DIMM1

Horng Chou

Horng Chou

1

Horng Chou

15 57Tuesday, February 06, 2007

15 57Tuesday, February 06, 2007

15 57Tuesday, February 06, 2007

Rev

Rev

Rev

1.1

1.1

1.1

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

TERESA

TERESA

TERESA

Engineer:

5

4

3

2

1

+0.9VS

D D

C C

B B

A A

1 16

56Ohm

56Ohm

2 15

56Ohm

56Ohm

3 14

56Ohm

56Ohm

4 13

56Ohm

56Ohm

5 12

56Ohm

56Ohm

6 11

56Ohm

56Ohm

7 10

56Ohm

56Ohm

8 9

56Ohm

56Ohm

1 16

56Ohm

56Ohm

2 15

56Ohm

56Ohm

3 14

56Ohm

56Ohm

4 13

56Ohm

56Ohm

5 12

56Ohm

56Ohm

6 11

56Ohm

56Ohm

7 10

56Ohm

56Ohm

8 9

56Ohm

56Ohm

1 16

56Ohm

56Ohm

2 15

56Ohm

56Ohm

3 14

56Ohm

56Ohm

4 13

56Ohm

56Ohm

5 12

56Ohm

56Ohm

6 11

56Ohm

56Ohm

7 10

56Ohm

56Ohm

8 9

56Ohm

56Ohm

1 2

56Ohm

56Ohm

3 4

56Ohm

56Ohm

5 6

56Ohm

56Ohm

7 8

56Ohm

56Ohm

1 16

56Ohm

56Ohm

2 15

56Ohm

56Ohm

3 14

56Ohm

56Ohm

4 13

56Ohm

56Ohm

5 12

56Ohm

56Ohm

6 11

56Ohm

56Ohm

7 10

56Ohm

56Ohm

8 9

56Ohm

56Ohm

1 16

56Ohm

56Ohm

2 15

56Ohm

56Ohm

3 14

56Ohm

56Ohm

4 13

56Ohm

56Ohm

5 12

56Ohm

56Ohm

6 11

56Ohm

56Ohm

7 10

56Ohm

56Ohm

8 9

56Ohm

56Ohm

1 16

56Ohm

56Ohm

2 15

56Ohm

56Ohm

3 14

56Ohm

56Ohm

4 13

56Ohm

56Ohm

5 12

56Ohm

56Ohm

6 11

56Ohm

56Ohm

7 10

56Ohm

56Ohm

8 9

56Ohm

56Ohm

1 2

56Ohm

56Ohm

3 4

56Ohm

56Ohm

5 6

56Ohm

56Ohm

7 8

56Ohm

56Ohm

RN1602A

RN1602A
RN1602B

RN1602B
RN1602C

RN1602C
RN1602D

RN1602D
RN1602E

RN1602E
RN1602F

RN1602F
RN1602G

RN1602G
RN1602H

RN1602H
RN1603A

RN1603A
RN1603B

RN1603B
RN1603C

RN1603C
RN1603D

RN1603D
RN1603E

RN1603E
RN1603F

RN1603F
RN1603G

RN1603G
RN1603H

RN1603H
RN1604A

RN1604A
RN1604B

RN1604B
RN1604C

RN1604C
RN1604D

RN1604D
RN1604E

RN1604E
RN1604F

RN1604F
RN1604G

RN1604G
RN1604H

RN1604H
RN1605A

RN1605A
RN1605B

RN1605B
RN1605C

RN1605C
RN1605D

RN1605D
RN1606A

RN1606A
RN1606B

RN1606B
RN1606C

RN1606C
RN1606D

RN1606D
RN1606E

RN1606E
RN1606F

RN1606F
RN1606G

RN1606G
RN1606H

RN1606H
RN1607A

RN1607A
RN1607B

RN1607B
RN1607C

RN1607C
RN1607D

RN1607D
RN1607E

RN1607E
RN1607F

RN1607F
RN1607G

RN1607G
RN1607H

RN1607H
RN1608A

RN1608A
RN1608B

RN1608B
RN1608C

RN1608C
RN1608D

RN1608D
RN1608E

RN1608E
RN1608F

RN1608F
RN1608G

RN1608G
RN1608H

RN1608H
RN1609A

RN1609A
RN1609B

RN1609B
RN1609C

RN1609C
RN1609D

RN1609D

M_CKE2
M_CKE3
M_B_BS2
M_B_A9
M_B_A12
M_B_A8
M_B_A11
M_B_A6

M_B_A7
M_B_A5
M_B_A3
M_B_A4
M_B_A2
M_B_A1
M_B_A0
M_B_WE#

M_B_BS1
M_B_A10
M_B_RAS#
M_B_BS0
M_B_A13
M_B_CAS#
M_ODT2
M_CS#2

M_CS#3

M_ODT3
M_A_A12

M_A_BS2
M_A_A11
M_A_A7
M_A_A6
M_CKE1
M_CKE0
M_A_A9

M_A_A5
M_A_A4
M_A_A3
M_A_A0
M_A_A2
M_A_A8

M_A_A10
M_A_BS1
M_A_RAS#
M_A_BS0
M_A_A1
M_A_A13
M_A_CAS#
M_A_WE#

M_ODT0
M_CS#0
M_CS#1
M_ODT1

+0.9VS

+0.9VS

12

C1602

C1602

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1614

C1614

c0402

c0402

0.1UF/10V

0.1UF/10V

M_A_A[0..13] 8,14
M_A_BS[0..2] 8,14
M_A_CAS# 8,14

M_A_RAS# 8,14
M_A_WE# 8,14

M_B_A[0..13] 8,15
M_B_BS[0..2] 8,15
M_B_CAS# 8,15

M_B_RAS# 8,15
M_B_WE# 8,15

Add Voltage Follower

+1.8V

R1601

R1601

10KOhm

10KOhm

1 2

M_CS#[0..3] 7,14,15
M_ODT[0..3] 7,14,15
M_CKE[0..3] 7,14,15

12

C1603

C1603

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1604

C1604

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1605

C1605

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1606

C1606

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1607

C1607

c0402

c0402

0.1UF/10V

0.1UF/10V

C1628

0.01UF/50V

0.01UF/50V

12

C1608

C1608

c0402

c0402

0.1UF/10V

0.1UF/10V

GND

10KOhm

10KOhm

1 2

R1602

R1602

12

C1609

C1609

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1628

Layout note:
Place one cap close to every 2 pull-up resistors terminated to +0.9VS

12

C1615

C1615

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1616

C1616

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1617

C1617

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1618

C1618

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1619

C1619

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1620

C1620

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1621

C1621

c0402

c0402

0.1UF/10V

0.1UF/10V

M_VREF_MCH

+5V

U1601

U1601

1

+

+

3

-

-

GND

12

C1610

C1610

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1622

C1622

c0402

c0402

0.1UF/10V

0.1UF/10V

PCMCIA

PCMCIA

PCMCIA

+0.9VS

12

52

GND

V+

V+

4

V-

V-

LMV321IDBVR

LMV321IDBVR

12

C1611

C1611

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1623

C1623

c0402

c0402

0.1UF/10V

0.1UF/10V

C1627

C1627

0.1UF/16V

0.1UF/16V

M_VREF_MCH 7,14,15
+0.9VS 37,53

T1601T1601

1

12

C1612

C1612

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1624

C1624

c0402

c0402

0.1UF/10V

0.1UF/10V

M_VREF_MCH

12

C1629

C1629
1UF/10V

1UF/10V

c0603

c0603

GND

12

C1601

C1601

c0402

c0402

0.1UF/10V

0.1UF/10V

12

C1625

C1625

c0402

c0402

0.1UF/10V

0.1UF/10V

12

GND

12

GND

C1613

C1613

c0402

c0402

0.1UF/10V

0.1UF/10V

C1626

C1626

c0402

c0402

0.1UF/10V

0.1UF/10V

Title :

Title :

Title :

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

TERESA

TERESA

TERESA

Engineer:

DDR2 TERM

DDR2 TERM

DDR2 TERM

Horng Chou

Horng Chou

Horng Chou

16 57Tuesday, February 06, 2007

16 57Tuesday, February 06, 2007

16 57Tuesday, February 06, 2007

1

1.1

1.1

1.1

Rev

Rev

Rev

5

+VCC_RTC

R1701

R1701

20KOhm

20KOhm

C1704

C1704

1UF/16V

1UF/16V

D D

RTCRST#

12

12

JRST1@JRST1

2

112

GND

@

(061227)Change reference from JRST1701 to JRST1

4

C1702

C1702

12

18PF/50V

18PF/50V

X1701

X1701

1

1

3

SIDE

2

32.768KHZ

32.768KHZ

12

2

GND

C1703

C1703

18PF/50V

18PF/50V

1 2

RTC_X1

R1702

R1702
10MOhm

10MOhm

RTC_X2

3

+1.5VS_PCIE_ICH

+VCCP_ICH

+VCC_RTC

+VCCP

+1.5VS

+5VS
+3VS
+3VA

2

+1.5VS_PCIE_ICH 18,20
+VCCP_ICH 20
+VCC_RTC 20
+VCCP 2,6,9,20,52
+1.5VS 7,9,10,20,25,26,37,52
+5VS 4,13,19,20,21,22,28,29,30,34,37,38,50,61
+3VS 4,5,7,9,11,12,13,14,15,19,20,21,22,25,26,27,28,29,30,33,37,40,43,50,52,60,61
+3VA 4,12,22,29,37,38,40,41,54,59,63

1

Delete LPC interface of TPM

U1701A

LPC_AD0_ICH

LPC_AD1_ICH LPC_AD1

LPC_AD3_ICH

LPC_FRAME#_ICH

C C

R1728 33OhmR1728 33Ohm

1 2

R1720 33OhmR1720 33Ohm

1 2

R1722 33OhmR1722 33Ohm

1 2

R1724 33OhmR1724 33Ohm

1 2

R1726 33OhmR1726 33Ohm

1 2

LPC_AD0

LPC_AD2LPC_AD2_ICH

LPC_AD3

LPC_FRAME#

LPC_AD0 26,29

LPC_AD1 26,29

LPC_AD2 26,29

LPC_AD3 26,29

LPC_FRAME# 26,29

+VCC_RTC

R1703

R1703
1MOhm

1MOhm

1 2
1 2

R1704

R1704
330KOhm

330KOhm

close to ICH7

R1708

R1708
39Ohm

39Ohm

ACZ_BCLK_AUD21
ACZ_BCLK_MDC35

ACZ_SYNC_AUD21
ACZ_SYNC_MDC35

ACZ_RST#_AUD21,22

ACZ_RST#_MDC35

B B

ACZ_SDOUT_AUD21

ACZ_SDOUT_MDC35

Check with EMI: remove 0 ohm
=>IDE_PDIOR#_ICH
IDE_PDD1_ICH
IDE_PDD2_ICH
IDE_PDD9_ICH
IDE_PDD10_ICH

A A

1 2
1 2

R173239OhmR173239Ohm
R1710

R1710
39Ohm

39Ohm

1 2
1 2

R1731 39OhmR1731 39Ohm

R1714 39OhmR1714 39Ohm

1 2

R1729 39OhmR1729 39Ohm

1 2

R1717

R1717
39Ohm

39Ohm

1 2

R1730

R1730
39Ohm

39Ohm

1 2

5

ACZ_BCLK

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

SATA_RXN028
SATA_RXP028
SATA_TXN028
SATA_TXP028

SATA_LED#30

Change to 3900PF

CLK_PCIE_SATA#5

CLK_PCIE_SATA5

1 2

1 2

IDE_PDIOR#28

4

ACZ_SDIN021
ACZ_SDIN135

C1705 3900PF/50VC1705 3900PF/50V

C1701 3900PF/50VC1701 3900PF/50V

Remove 0 ohm

GND

R1719 24.9Ohm 1%R1719 24.9Ohm 1%

GND

IDE_PDIOW#28
IDE_PDDACK#28
INT_IRQ1428
IDE_PIORDY28
IDE_PDDREQ28

T1703T1703

T1704T1704
T1705T1705

IDE_PDIOR#_ICH

ACZ_SDOUT PWROK rising

ACZ_SYNC PWROK rising PD

EE_CS PD

EE_DOUT

GNT2#

GNT5#/GPIO17#
GNT4#/GPIO48

RTC_X1
RTC_X2

RTCRST#
INTRUNDER#

INTVRMEN

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

1

ACZ_SDOUT

SATA_TXN0_ICH
SATA_TXP0_ICH

SATA2_R

SATA2_TN

1

SATA2_TP

1

SATA2_RBIAS

12

IDE_PDIOW#
IDE_PDDACK#
INT_IRQ14
IDE_PIORDY
IDE_PDDREQ

PWROK rising

PWROK rising

U1701A

AB1

RTCX1

AB2

RTCX2

AA3

RTCRST#

Y5

INTRUDER#

W4

INTVRMEN

W1

EE_CS

Y1

EE_SHCLK

Y2

EE_DOUT

W3

EE_DIN

V3

LAN_CLK

U3

LAN_RSTSYNC

U5

LAN_RXD0

V4

LAN_RXD1

T5

LAN_RXD2

U7

LAN_TXD0

V6

LAN_TXD1

V7

LAN_TXD2

U1

ACZ_BCLK

R6

ACZ_SYNC

R5

ACZ_RST#

T2

ACZ_SDIN0

T3

ACZ_SDIN1

T1

ACZ_SDIN2

T4

ACZ_SDOUT

AF18

SATALED#

AF3

SATA0RXN

AE3

SATA0RXP

AG2

SATA0TXN

AH2

SATA0TXP

AF7

SATA2RXN

AE7

SATA2RXP

AG6

SATA2TXN

AH6

SATA2TXP

AF1

SATA_CLKN

AE1

SATA_CLKP

AH10

SATARBIASN

AG10

SATARBIASP

AF15

DIOR#

AH15

DIOW#

AF16

DDACK#

AH16

IDEIRQ

AG16

IORDY

AE15

DDREQ

ICH7M

ICH7M

TP3 pull low: allow entrance to XOR Chain testing
TP3 not pull low: sets bit 1 of RPC.PC

sets bit 0 of RPC.PC

should not be pulled high

should not be pulled low

should not be pulled low

low: "top-block swap" mode

GNT5# GNT4#
0 1 SPI
1 0 PCI
1 1 LPC

RTC

RTC

LDRQ1#/GPIO23

CPU LPC

CPU LPC

TP1/DPRSTP#

LAN

LAN

TP2/DPSLP#

GPIO49/CPUPWRGD

AC-97/AZALIASATA

AC-97/AZALIASATA

IDE

IDE

3

THERMTRIP#

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LFRAME#
A20GATE

A20M#

CPUSLP#

FERR#

IGNNE#

INIT3_3V#

INIT#
INTR

RCIN#

SMI#

STPCLK#

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

LPC_AD0_ICH

AA6

LPC_AD1_ICH

AB5

LPC_AD2_ICH

AC4

LPC_AD3_ICH

Y6

LPC_DRQ#0

AC3

LPC_DRQ#1

AA5

LPC_FRAME#_ICH

AB3

A20GATE

AE22

H_A20M#

AH28

S_CPUSLP#

AG27

S_DPRSTP#

AF24

H_DPSLP#

AH25

H_FERR#

AG26

H_PWRGD

AG24

H_IGNNE#

AG22

INIT3_3V#

AG21

H_INIT#

AF22

H_INTR

AF25

RCIN#

AG23

H_NMI

AH24

NMI

H_SMI#

AF23

H_STPCLK#

AH22

S_THRMTRIP#

AF26

IDE_PDD0

AB15

IDE_PDD1_ICH

AE14

IDE_PDD2_ICH

AG13

IDE_PDD3

AF13

IDE_PDD4

AD14

IDE_PDD5

AC13

IDE_PDD6

AD12

IDE_PDD7

AC12

IDE_PDD8

AE12

IDE_PDD9_ICH

AF12

IDE_PDD10_ICH

AB13

IDE_PDD11

AC14

IDE_PDD12

AF14

IDE_PDD13

AH13

IDE_PDD14

AH14

IDE_PDD15

AC15

IDE_PDA0

AH17

DA0

IDE_PDA1

AE17

DA1

IDE_PDA2

AF17

DA2

IDE_PDCS1#

AE16

IDE_PDCS3#

AD16

PD

PU

PU

PUGNT3#

PU

1

1 2
1 2

R1713

R1713

1%

1%

IDE_PDD0 28

IDE_PDD3 28
IDE_PDD4 28
IDE_PDD5 28
IDE_PDD6 28
IDE_PDD7 28
IDE_PDD8 28

IDE_PDD11 28
IDE_PDD12 28
IDE_PDD13 28
IDE_PDD14 28
IDE_PDD15 28

IDE_PDA0 28
IDE_PDA1 28
IDE_PDA2 28

IDE_PDCS1# 28
IDE_PDCS3# 28

GPIO16
/DPRSLPVR
GPIO25

INTVRMEN

LINKALERT#

REQ[4:1]#

SATALED#

SPKR

TP3

2

LPC_DRQ#0 19

T1702T1702

A20GATE 29
H_A20M# 2

R1705

@R1705

@

Do Not Stuff

Do Not Stuff
R1707

@R1707

@

Do Not Stuff

Do Not Stuff

H_PWRGD 2

H_IGNNE# 2
H_INIT# 2

H_INTR 2
RCIN# 29
H_NMI 2

H_SMI# 2
H_STPCLK# 2

12

24.9Ohm

24.9Ohm

RSMRST# rising

PWROK rising

PWROK rising

PWROK rising

+VCCP_ICH

H_CPUSLP# 2,6
H_DPRSTP# 2,50

H_DPSLP# 2

T1701T1701

1

+VCCP_ICH

R1711

R1711
56Ohm

56Ohm

1 2

IDE_PDD1 28
IDE_PDD2 28

IDE_PDD9 28

IDE_PDD10 28

should not be pulled high

should not be pulled low

high: Enable integrated VccSus1_05 VRMALWAYS

REQUIRE an extenal pull-up R

should not be pulled low

high: "No reboot" mode

should not be pulled low unless
using XOR Chain testing

PCMCIA

PCMCIA

PCMCIA

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

R1706

R1706
56Ohm

56Ohm

1 2

H_FERR# 2

DPRSTP# routing from Intel 82801GBM to
Yonah processor is required. Routing to VR
must be done last and must have de-bounce
filtering to handle daisy chain topology.

PM_THRMTRIP# 2,4

24 ± 5% series termination resistor
placed within 2" from Intel 82801GBM,
56 ± 5% pull-up resistor has to be
within 2" from the series resistor

PD

PU

Need
PU

Conditional
PU
PD

PU

Title :

Title :

Title :

ICH7-M (1/4)

ICH7-M (1/4)

ICH7-M (1/4)

Horng Chou

Horng Chou

1

Horng Chou

17 57Tuesday, February 06, 2007

17 57Tuesday, February 06, 2007

17 57Tuesday, February 06, 2007

TERESA

TERESA

TERESA

Engineer:

Engineer:

Engineer:

Rev

Rev

Rev

1.1

1.1

1.1

5

PCI_AD[31:0]34,43

PCI Device

Device

D D

CardBus
LAN

C C

B B

+3VSUS

A A

IDSEL#REQ#/GNT# Interrupts

AD17

REQ1#/GNT1#AB, C, D

AD23

REQ2#/GNT2#

RN1802A

RN1802A
RN1802B

RN1802B
RN1802C

RN1802C
RN1802D

RN1802D
RN1803A

RN1803A
RN1803B

RN1803B
RN1803C

RN1803C
RN1803D

RN1803D

1 2

100KOhm

100KOhm

3 4

100KOhm

100KOhm

5 6

100KOhm

100KOhm

7 8

100KOhm

100KOhm

1 2

10KOhm

10KOhm

3 4

10KOhm

10KOhm

5 6

10KOhm

10KOhm

7 8

10KOhm

10KOhm

USB_CON_OC0#
USB_CON_OC23#
USB_OC_7#
NEWCARD_OC#
USB_OC_5#
USB_OC_14#
SYS_RST#
PM_RI#

5

PCI_INTA#19,34
PCI_INTB#19,43
PCI_INTC#19,43
PCI_INTD#19,43

T1804T1804

1

T1806T1806

1

T1808T1808

1

T1810T1810

1

T1812T1812

1

PCIE_RXN2_MINICARD26
PCIE_RXP2_MINICARD26
PCIE_TXN2_MINICARD26
PCIE_TXP2_MINICARD26

PCIE_RXN3_NEWCARD25
PCIE_RXP3_NEWCARD25
PCIE_TXN3_NEWCARD25
PCIE_TXP3_NEWCARD25

USB_CON_OC0#36

SYS_RST#19
PM_RI# 19

USB_CON_OC23#36

NEWCARD_OC#25

C1806 0.1UF/10V

C1806 0.1UF/10V

C1805 0.1UF/10V

C1805 0.1UF/10V

Connect to OC14#

4

U1701B

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#

S_RSVD1
S_RSVD2
S_RSVD3
S_RSVD4
S_RSVD5

T1813T1813
T1814T1814
T1815T1815
T1816T1816

C1801 0.1UF/10VC1801 0.1UF/10V

1 2

1 2

C1804 0.1UF/10VC1804 0.1UF/10V

1 2

1 2

T1817T1817
T1818T1818
T1819T1819
T1820T1820

T1821T1821
T1822T1822
T1801T1801
T1823T1823

T1824T1824
T1825T1825
T1826T1826
T1827T1827

T1828T1828
T1829T1829
T1830T1830

T1831T1831
T1832T1832

U1701B

E18

AD0

C18

AD1

A16

AD2

F18

AD3

E16

AD4

A18

AD5

E17

AD6

A17

AD7

A15

AD8

C14

AD9

E14

AD10

D14

AD11

B12

AD12

C13

AD13

G15

AD14

G13

AD15

E12

AD16

C11

AD17

D11

AD18

A11

AD19

A10

AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

AE5

RSVD_1

AD5

RSVD_2

AG4

RSVD_3

AH4

RSVD_4

AD9

RSVD_5

ICH7M

ICH7M

PE_RN1

1

PE_RP1

1

PE_TN1

1

PE_TP1

1

c0402

c0402

c0402

c0402

PE_RN4

1

PE_RP4

1

PE_TN4

1

PE_TP4

1

PE_RN5

1

PE_RP5

1

PE_TN5

1

PE_TP5

1

PE_RN6

1

PE_RP6

1

PE_TN6

1

PE_TP6

1

SPI_CLK

1

SPI_CS#

1

SPI_ARB

1

SPI_MOSI

1

SPI_MISO

1

USB_CON_OC0#

USB_OC_14#

USB_CON_OC23#

USB_OC_14#

USB_OC_5#

NEWCARD_OC#

USB_OC_7#

4

PCI

PCI

Interrupt I/F

Interrupt I/F

MISC

MISC

U1701D

U1701D

F26

PERn1

F25

PERp1

E28

PETn1

E27

PETp1

H26

PERn2

H25
G28
G27

K26

K25

M26
M25

L28

L27

P26

P25

N28

N27

T25

T24
R28
R27

J28
J27

R2
P6
P1

P5
P2

D3
C4
D5
D4
E5
C3
A2
B3

PERp2
PETn2
PETp2

PERn3
PERp3
PETn3
PETp3

PERn4
PERp4
PETn4
PETp4

PERn5
PERp5
PETn5
PETp5

PERn6
PERp6
PETn6
PETp6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

ICH7M

ICH7M

PE_TN2
PE_TP2

PE_TN3
PE_TP3

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

REQ4#/GPIO22

GNT4#/GPIO48

GPIO1/REQ5#

GPIO17/GNT5#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

GPIO2/PIRQE#
GPIO3/PIRQF#

GPIO4/PIRQG#

GPIO5/PIRQH#

RSVD_6
RSVD_7
RSVD_8
RSVD_9

MCH_SYNC#

PCI-ExpressSPI

PCI-ExpressSPI

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

Direct Media Interface

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USB

USB

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3
PCI_REQ#4
PCI_GNT#4
PCI_REQ#5
PCI_GNT#5

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_IRDY#
PCI_PAR
PCI_RST#_ICH
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLT_RST#_SB
CLK_ICHPCI
PCI_PME#

PCI_INTE#
PCI_INTF#
PCI_INTG#
PCI_INTH#

S_RSVD6
S_RSVD7
S_RSVD8
S_RSVD9
MCH_ICH_SYNC#

DMI0RXN
DMI0RXP

DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP

DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP

DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP

DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS#

USBRBIAS

3

V26
V25
U28
U27

Y26
Y25
W28
W27

AB26
AB25
AA28
AA27

AD25
AD24
AC28
AC27

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

3

T1805T1805

1

T1807T1807

1

T1809T1809

1

T1811T1811

1

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_COMP

USB_PN0_B
USB_PP0_B

USB_PN2_B
USB_PP2_B
USB_PN3_B
USB_PP3_B

USB_PN6_B
USB_PP6_B

USBRBIAS_PN

PCI_REQ#0 19

1

PCI_REQ#1 19,43
PCI_GNT#1 43
PCI_REQ#2 19,34
PCI_GNT#2 34
PCI_REQ#3 19

1

PCI_REQ#4 19
PCI_REQ#5 19

PCI_C/BE#0 34,43
PCI_C/BE#1 34,43
PCI_C/BE#2 34,43
PCI_C/BE#3 34,43

PCI_IRDY# 19,34,43
PCI_PAR 34,43

PCI_DEVSEL# 19,34,43
PCI_PERR# 19,34,43
PCI_LOCK# 19
PCI_SERR# 19,34,43
PCI_STOP# 19,34,43
PCI_TRDY# 19,34,43
PCI_FRAME# 19,34,43

CLK_ICHPCI 5
PCI_PME# 19,34,43

PCI_INTE# 19
PCI_INTF# 19
PCI_INTG# 19
PCI_INTH# 19

MCH_ICH_SYNC# 7

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN07
DMI_TXP07

DMI_RXN1 7
DMI_RXP1 7
DMI_TXN17
DMI_TXP17

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN27
DMI_TXP27

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN37
DMI_TXP37

CLK_PCIE_ICH# 5
CLK_PCIE_ICH 5

R180424.9Ohm 1%R180424.9Ohm 1%

1 2

USB_PN0 36
USB_PP0 36

T1838T1838

1

T1837T1837

1

1
1
1
1

1
1

T1834T1834
T1833T1833
T1835T1835
T1836T1836

T1840T1840
T1839T1839

R1805

R1805

1 2

22.6Ohm 1%

22.6Ohm 1%

USB_PN2 36
USB_PP2 36
USB_PN3 36
USB_PP3 36

Add test points

USB_PN6 25
USB_PP6 25

T1802T1802

T1803T1803

LPC
PCI 0

R1802

R1802
Do Not Stuff@

Do Not Stuff@

1 2
1 2

R1803

R1803
Do Not Stuff@

Do Not Stuff@

0ohm replace AND gates

+1.5VS_PCIE_ICH

GND

2

GNT#4

GNT#5

11

1
10
01SPI

GND

PCI_RST#_ICH

PLT_RST#_SB

(default)1
1
0

1

(061215)Add AND gates

GND

GND

(061204)CRT H/VSYNC buffer circuit move to page-28

Layout Note:
Pull-ups must be placed within 500
mils from Intel 82801GBM pins

2

1

+3V

U1801

U1801

A

A

1
2
3 4

1
2
3 4

VCC

VCC

B

B

GND

GND

Do Not Stuff

Do Not Stuff

@

@

U1802

U1802

A

A

VCC

VCC

B

B

GND

GND

Do Not Stuff

Do Not Stuff

@

@

R1806

R1806

1 2

0Ohm

0Ohm

R1801

R1801

1 2

0Ohm

0Ohm

5

Y

Y

+3V

5

Y

Y

PCI_RST# 12,34,43

PLT_RST#7,19,25,26,28,29

Modify USB Device table

USB Devices

Port 0

CON3602

Port 1

Unused

Port 2

CON3601

Port 3

CON3601

Port 4

Unused

Port 5

Unused

Port 6

NewCard

Port 7

Unused

PCMCIA

PCMCIA

PCMCIA

Title :

Title :

Title :

ICH7-M (2/4)

ICH7-M (2/4)

1

ICH7-M (2/4)

Horng Chou

Horng Chou

Horng Chou

18 57Tuesday, February 06, 2007

18 57Tuesday, February 06, 2007

18 57Tuesday, February 06, 2007

Engineer:

Engineer:

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

ASUSALPHATeK COMPUTER INC.

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

TERESA

TERESA

TERESA

Engineer:

Rev

Rev

Rev

1.1

1.1

1.1