THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
B
D
Date:Sheetof
Compal Electronics, Inc.
Cover Page
QBL60 LA-7552P
E
153Monday, April 25, 2011
1.0
A
Compal Confidential
Model Name : QBL60
B
C
D
E
11
VRAM 1G/2G
128M16 x 4/8
page 23, 24
Sabine
DDR3
Thermal Sensor
ADM1032
page 19
Vancuver Whistler
ATI
uFCBGA-962
Page 18~22
GFX x 4
APU HDMI
(UMA / Muxless)
DP x1 (DP0 TXP/N0)
Gen2GFX x 8
AMD FS1 APU
Llano
uPGA-722 Package
Memory BUS(DDR3)
Dual Channel
1.5V DDRIII 800~1333MHz
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
Page 11,12
HDMI Conn.
page 28
22
LVDS Conn.
page 27
LVDS
CRT Conn.
page 27
Travis LVDS
Translator
page 26
FCH CRT (VGA DAC)
GPP0GPP1
P_GPP x 2
GEN1
DP x 4
(DP1 TXP/N 0~4)
Hudson-M2/M3
uFCBGA-656
MINI Card 1
WLAN
33
page 32
LAN(GbE)
RTL8111E-VL
RJ45
page 29
page 29
Page 6~10
FCH
Page 13~17
UMI
LPC BUS
USB2
page 34
USB
3.3V 48MHz
HD Audio
S-ATA
Gen2
port 0
SATA HDD1
Conn.
page 33
USB2
page 34page 27
Port 0Port 1
3.3V 24.576MHz/48Mhz
USB2
(LS-7322P)
page 30
Port 10
CMOS
Camera
ODD
Conn.
page 33
Mini Card
(with BT)
Port2Port 3
port 1
HDA Codec
ALC269
page 32
Card Reader
RTS5137
page 31
Port 4
page 30
ENE KB930
page 36
Touch PadInt.KBD
LED
page 37
RTC CKT.
44
page 13
DC/DC
Interface CKT.
page 38
External board
LS-7326P
Power/B
page 35
BIOS ROM
LS-7322P
Power Circuit
page 39~49
A
Audio BD
page 30
EC BIOS (2M)
page 35
B
page 37
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
CLOCK / DISPLAY DISTRIBUTION
Size Document NumberRev
Custom
QBL60 LA-7552P
2
Date:Sheetof
LS
HDMI CONNCRT CONN
1
353Monday, April 25, 2011
1.0
A
B
C
D
E
Voltage Rails
Power PlaneDescription
VIN
B+
+CPU_CORE
11
+CPU_CORE_NBONOFFOFFVoltage for On-die VGA of APU
+VGA_COREOFFOFFON0.95-1.2V switched power rail
+0.75VSONONOFF0.75V switched power rail for DDR terminator
+1.0VSGONOFFOFF1.0V switched power rail for VGA
+1.1ALW1.1V switched power rail for FCHONON*ON
+1.1VS
+1.2VSONOFFOFF
+1.5VON
+1.5VS
+1.8VSGOFFONOFF1.8V switched power rail
+2.5VS
+3VALW
+LAN_IOONONON
+3VS
+5VALW
+5VS
22
+VSBONON*
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2V switched power rail for APU
1.5V power rail for CPU VDDIO and DDR
1.5V switched power rail
2.5V for CPU_VDDA
3.3V always on power rail
3.3V power rail for LAN
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
S1S3S5
N/AN/AN/A
ONOFF
ONOFFOFF1.1V switched power rail for FCH
ONOFF
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
ON
OFF
OFF
OFF
ONON*
OFF
OFF
ON
ON*
OFF
OFFON
ONON
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)LOW
BTO Option Table
VGA@Use VGA (Mux)
M2@Use Hudson-M2
M3@Use Hudson-M3
USB30@USB30 on M/B
USB20@USB20 on M/B
SIGNAL
SLP_S3# SLP_S4# SLP_S5# +VALW+V+VSClock
ON
ON
ON
ON
OFF
OFF
M3@
U25
ONON
ON
OFF
OFF
OFF
LOW
OFF
OFF
OFF
HIGHHIGHHIGH
HIGHHIGHHIGH
LOW
HIGH
HIGH
LOWLOW
LOW
HIGH
LOW
ON
ON
ON
ON
BTO ItemBOM Structure
VRAM ID TableX76@
FCH M3
Part Number = SA000043ID0
BOM Config
x = 1 is read cmd, x= 0 is writee cmd.
External PCI Devices
DeviceIDSEL#REQ#/GNT#Interrupts
33
EC SM Bus1 addressEC SM Bus2 address
DeviceAddressHEX
Smart Battery
0001 011X b
FCH
SM Bus 0 address
44
DeviceAddressDeviceAddress
DDR DIMM1
DDR DIMM2
1101 000X b
1101 001X b
A
DeviceAddressHEX
16H
ADI ADM1032 (VGA)
(APU)
RTD2132S (TL)
1001 101X b
FCH
SM Bus 1 address
HEX
D0
D2
9AH
HEX
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
B
D
Date:Sheetof
Compal Electronics, Inc.
Notes List
QBL60 LA-7552P
E
453Monday, April 25, 2011
1.0
5
4
3
2
1
BATTERY
12.6V
AC ADAPTOR
DD
19V 90W
CC
BB
BATT+
VIN
PU101
CHARGER
FAN Control
APL5607
+5VS 500mA
B+
U54/U55
AP2301MPG
+INVPWR_B+
LCD panel
15.6"
B+ 300mA
+3.3 350mA
+USB_VCCA
+USB_VCCB
PU201
ISL6267HRZ-T
PU501
RT8209MGQW
PU801
RT8209MGQW
PU901
RT8237CZQW
PU701
RT8209MGQW
PU301
RT8205LZQW
+3VS
+5VS
+CPU_CORE
+CPU_CORE_NB
+1.5V
+1.2VS
+VGA_CORE
+1.1VALW
+3VALW
+5VALW
+5VALW
+3VS
U33
SI4800
+2.5VS
PU603
APL5508-25DC
U40
SI4800
PU602
APL5930KAI
U41
AO4430L
PU401
SY8033BDBC
PU601
APL5336KAI
+1.0VSG
+1.5VSG
+1.8VSG
PJ14
U39
AO4430L
+0.75VS
+3VSG
+1.1VS
+CPU_CORE
+CPU_CORE_NB
+2.5VS
+1.5V
+1.2VS
+0.75VS
+VGA_CORE
+VDDCI
+1.0VSG
+1.5VSG
+1.8VSG
+3VSG
+1.1VS
+1.1VALW
+3VS
USB X3
+5V
Dual+1
2.5A
SATA
HDD*2
ODD*1
+5V 3A
+3.3V
AA
Audio Codec
ALC269-GR
+5V 45mA
+3.3VS 25mA
EC
ENE KB930
+3.3VALW 30mA
+3.3VS 3mA
+3VALW
LAN
RTL8111E
+3.3VALW 201mA
+1.5VS
Mini Card
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
RTC
Bettary
+3VALW
AMD APU FS1
0.7~1.475V
0.7~1.475V
+2.5VS
+1.5V
+1.2VS
VDD CORE 54A
VDDNB 27.5A
VDDA 500mA
VDDIO 4.6A
VDDR 6.7A
RAM DDRIII SODIMMX2
+1.5V
+0.75VS
0.85~1.1V
0.9~1.0V
+1.0VSG
+1.5VSG
+1.8VSG
+3VSG
VDD_MEM 4A
VTT_MEM 0.5A
VGA ATI
W
histler/Seymour/Granville
VDDC 47A
VDDCI 4.6A
DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VDDR1: 3400 mA
PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
A2VDD: 130 mA
VDDR3: 60 mA
FCH AMD Hudson M2/M3
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
+1.1VS
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
+1.1VALW
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA
VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
+3VS
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA
VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
+3VALW
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA
VDDIO_33_GBE_S
VDDCR_11_GBE_S
GND
VDDIO_GBE_S
VDDBT_RTC_GRTC BAT
VRAM 1GB/2GB
64M / 128Mx16 * 4 / 8
+1.5VSG2.4 A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
2
Title
POWER DELIVERY CHART
Size Document NumberRev
Custom
QBL60 LA-7552P
Date:Sheet
1
553Monday, April 25, 2011
of
1.0
A
PCIE_GTX_C_FRX_P[0..7]18
JCPU1A
PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
11
22
PCIE_DTX_C_FRX_P029
33
44
PCIE_DTX_C_FRX_N029
PCIE_DTX_C_FRX_P132
PCIE_DTX_C_FRX_N132
UMI_MTX_C_FRX_P013
UMI_MTX_C_FRX_N013
UMI_MTX_C_FRX_P113
UMI_MTX_C_FRX_N113
UMI_MTX_C_FRX_P213
UMI_MTX_C_FRX_N213
UMI_MTX_C_FRX_P313
UMI_MTX_C_FRX_N313
+1.2VS
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7
12
R539196_0402_1%
P_ZVDDP
AA8
AA9
Y7
Y8
W5
W6
W8
W9
V7
V8
U5
U6
U8
U9
T7
T8
R5
R6
R8
R9
P7
P8
N5
N6
N8
N9
M7
M8
L5
L6
L8
L9
AC5
AC6
AC8
AC9
AB7
AB8
AA5
AA6
AF8
AF7
AE6
AE5
AE9
AE8
AD8
AD7
K5
AMD_TOPEDO_FS-1
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3
P_ZVDDP
PCI EXPRESS
GPPUMI-LINKGRAPHICS
B
CONN@
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
P_ZVSS
PCIE_FTX_GRX_P0
AA2
PCIE_FTX_GRX_N0
AA3
PCIE_FTX_GRX_P1
Y2
PCIE_FTX_GRX_N1
Y1
PCIE_FTX_GRX_P2
Y4
PCIE_FTX_GRX_N2
Y5
PCIE_FTX_GRX_P3
W2
PCIE_FTX_GRX_N3
W3
PCIE_FTX_GRX_P4
V2
PCIE_FTX_GRX_N4
V1
PCIE_FTX_GRX_P5
V4
PCIE_FTX_GRX_N5
V5
PCIE_FTX_GRX_P6
U2
PCIE_FTX_GRX_N6
U3
PCIE_FTX_GRX_P7
T2
PCIE_FTX_GRX_N7
T1
T4
T5
R2
R3
P2
P1
P4
P5
PCIE_FTX_GRX_P12
N2
PCIE_FTX_GRX_N12
N3
PCIE_FTX_GRX_P13
M2
PCIE_FTX_GRX_N13
M1
PCIE_FTX_GRX_P14
M4
PCIE_FTX_GRX_N14
M5
PCIE_FTX_GRX_P15
L2
PCIE_FTX_GRX_N15
L3
PCIE_FTX_DRX_P0
AD4
PCIE_FTX_DRX_N0
AD5
PCIE_FTX_DRX_P1
AC2
PCIE_FTX_DRX_N1
AC3
AB2
AB1
AB4
AB5
UMI_FTX_MRX_P0
AF1
UMI_FTX_MRX_N0
AF2
UMI_FTX_MRX_P1
AF5
UMI_FTX_MRX_N1
AF4
UMI_FTX_MRX_P2
AE3
UMI_FTX_MRX_N2
AE2
UMI_FTX_MRX_P3
AD1
UMI_FTX_MRX_N3
AD2
P_ZVSS
K4
C9170.1U_ 0402_16V7KVGA@
C9180.1U_ 0402_16V7KVGA@
C9190.1U_ 0402_16V7KVGA@
C9200.1U_ 0402_16V7KVGA@
C9210.1U_ 0402_16V7KVGA@
C9220.1U_ 0402_16V7KVGA@
C9230.1U_ 0402_16V7KVGA@
C9240.1U_ 0402_16V7KVGA@
C9250.1U_ 0402_16V7KVGA@
C9260.1U_ 0402_16V7KVGA@
C9270.1U_ 0402_16V7KVGA@
C9280.1U_ 0402_16V7KVGA@
C9290.1U_ 0402_16V7KVGA@
C9300.1U_ 0402_16V7KVGA@
C9310.1U_ 0402_16V7KVGA@
C9320.1U_ 0402_16V7KVGA@
12
R540196_0402_1%
C
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
1
To HDMI
0
CK
C9500.1U_0402_16V7K
12
C9510.1U_0402_16V7K
12
C9520.1U_0402_16V7K
12
C9530.1U_0402_16V7K
12
C9560.1U_0402_16V7K
12
C9570.1U_0402_16V7K
12
C9580.1U_0402_16V7K
12
C9590.1U_0402_16V7K
12
C9600.1U_0402_16V7K
12
C9610.1U_0402_16V7K
12
C9620.1U_0402_16V7K
12
C9630.1U_0402_16V7K
12
PCIE_FTX_C_GRX_P[0..7] 18
PCIE_FTX_C_GRX_N[0..7] 18PCIE_GTX_C_FRX_N[0..7]18
PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7
PCIE_FTX_C_DRX_P0 29
PCIE_FTX_C_DRX_N0 29
PCIE_FTX_C_DRX_P1 32
PCIE_FTX_C_DRX_N1 32
UMI_FTX_C_MRX_P0 13
UMI_FTX_C_MRX_N0 13
UMI_FTX_C_MRX_P1 13
UMI_FTX_C_MRX_N1 13
UMI_FTX_C_MRX_P2 13
UMI_FTX_C_MRX_N2 13
UMI_FTX_C_MRX_P3 13
UMI_FTX_C_MRX_N3 13
For UMA Mux.
GLAN
WLAN
D
APU To HDMI
CPU TSI interface level shift
C9350.1U_0402_16V4Z
12
R535
12
+3VS
31.6K_0402_1%
APU_SID8,14
APU_SIC8,14
APU_SID
BSH111 1N_SOT23-3
APU_SIC
BSH111 1N_SOT23-3
G
S
G
S
12
30K_0402_1%
2
Q9
13
D
2
Q10
13
D
Power Sequence of APU
+1.5V
+2.5VS
+1.5VS
+CPU_CORE
+CPU_CORE_NB
+1.2VS
R536
EC_SMB_DA
EC_SMB_CK
PCIE_FTX_GRX_P[12..15] 28
PCIE_FTX_GRX_N[12..15] 28
BSH111, the Vgs is:
min = 0.4V
Max = 1.3V
R537
12
0_0402_5%
R538
12
0_0402_5%
E
EC_SMB_DA2 19,36
To EC
EC_SMB_CK2 19,36
Group A
Group B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Custom
D
Date:Sheetof
Title
Size Document NumberRev
Compal Electronics, Inc.
AMD FS1 DDRIII I/F
QBL60 LA-7552P
753Monday, April 25, 2011
E
1.0
A
Place near APU
C9710.1U_0402_16V7K
To LVDS
Translator
11
To FCH VGA ML
100MHz
22
100MHz_NSS
+1.5V
R5751K_0402_5%
12
R5761K_0402_5%
12
+1.5V
33
R5791K_0402_5%
12
R5811K_0402_5%
12
R7911K_0402_5%
12
+1.5V
Close to Header
R5921K_0402_5%
12
R5931K_0402_5%
12
R5941K_0402_5%
12
R5951K_0402_5%
12
R596300_0402_5%
12
Route as differential
with VSS_SENSE
APU_VDDNB_RUN_FB_L
APU_VDDNB_SEN route as differential
44
APU_VDD_RUN_FB_L
APU_VDD_SEN route as differential
DP0_TXP0_C26
DP0_TXN0_C26
ML_VGA_TXP015
ML_VGA_TXN015
ML_VGA_TXP115
ML_VGA_TXN115
ML_VGA_TXP215
ML_VGA_TXN215
ML_VGA_TXP315
ML_VGA_TXN315
APU_CLKP13
APU_CLKN13
APU_DISP_CLKP13
APU_DISP_CLKN13
APU_SVC47
APU_SVD47
Chang to PU +1.5VS (DG ref.)
20101111
APU_SVC
APU_SVD
APU_SIC
APU_SID
ALERT_L
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
APU_VDDNB_RUN_FB_ L47
APU_VDD_RUN_FB_L47
A
12
C9730.1U_0402_16V7K
12
T25
T28
T19
T20
T21
T22
Place near APU
C9770.1U_0402_16V7K
12
C9680.1U_0402_16V7K
12
C9690.1U_0402_16V7K
12
C9700.1U_0402_16V7K
12
C9780.1U_0402_16V7K
12
C9790.1U_0402_16V7K
12
C9800.1U_0402_16V7K
12
C9810.1U_0402_16V7K
12
APU_CLKP
APU_CLKN
APU_DISP_CLKP
APU_DISP_CLKN
APU_SVC
APU_SVD
APU_SIC6,14
TSI
APU_SID6,14
APU_RST#13
APU_PWRGD13
Serial VID
R5970_0402_5%
R6000_0402_5%
APU_VDDNB_SEN47
APU_VDD_SEN47
APU_SIC
APU_SID
APU_RST#
APU_PWRGD
APU_PROCHOT#
APU_THERMTRIP#
ALERT_L
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
12
12
APU_VDDNB_SEN
APU_VDD_SEN
DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_TXP2
DP0_TXN2
DP0_TXP3
DP0_TXN3
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
B
JCPU1D
F2
DP0_TXP0
F1
DP0_TXN0
E3
DP0_TXP1
E2
DP0_TXN1
D2
DP0_TXP2
D1
DP0_TXN2
C2
DP0_TXP3
C3
DP0_TXN3
K2
DP1_TXP0
K1
DP1_TXN0
J3
DP1_TXP1
J2
DP1_TXN1
H2
DP1_TXP2
H1
DP1_TXN2
G2
DP1_TXP3
G3
DP1_TXN3
AH7
CLKIN_H
AH6
CLKIN_L
AH4
DISP_CLKIN_H
AH3
DISP_CLKIN_L
B8
SVC
A8
SVD
AH11
SIC
AG11
SID
AF10
RESET_L
AE10
PWROK
AD10
PROCHOT_L
AG12
THERMTRIP_L
AH12
ALERT_L
C12
TDI
A12
TDO
A11
TCK
D12
TMS
B12
TRST_L
B11
DBRDY
C11
DBREQ_L
E8
RSVD_1
K21
RSVD_2
AC11
RSVD_3
B9
VSS_SENSE
C8
VDDP_SENSE
A9
VDDNB_SENSE
B10
VDDIO_SENSE
C9
VDD_SENSE
A10
VDDR_SENSE
AMD_TOPEDO_FS-1
B
DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE
System DP
CONN@
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
DP2_AUXP
DP2_AUXN
DP3_AUXP
DP3_AUXN
DP4_AUXP
DP4_AUXN
DP5_AUXP
DP5_AUXN
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD
DP_BLON
DP_DIGON
DP_VARY_BL
DP_AUX_ZVSS
TEST6
TEST9
TEST10
TEST12
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST21
TESTDISPLAY PORT MISC.
TEST22
TEST23
TEST24
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST31
TEST32_H
TEST32_L
TEST35
FS1R1
DMAACTIVE_L
THERMDA
THERMDC
C
Place near APU
DP0_AUXP
D4
DP0_AUXN
D5
ML_VGA_AUXP
E5
ML_VGA_AUXN
E6
J5
J6
H4
H5
G5
G6
APU_HDMI_CLK
F4
APU_HDMI_DATA
F5
D7
E7
J7
H7
G7
F7
C6
C5
C7
D8
AA10
G10
H10
H12
D9
E9
G9
H9
H11
G11
F12
E11
D11
F10
G12
AH10
AH9
K7
K8
AA12
AB12
K22
AB11
AA11
D10
Y11
AB10
AE12
AD12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C9720.1U_0402_16V7K
12
C9740.1U_0402_16V7K
12
C9750.1U_0402_16V7K
12
C9760.1U_0402_16V7K
12
APU_HDMI_CLK 28
APU_HDMI_DATA 28
DP0_HPD
DP1_HPD
DP5_HPD
DP_ENBKL
DP_ENVDD
DP_INT_PWM
DP_AUX_ZVSS
T6
T7
T8
T9
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST21
APU_TEST22
T10
APU_TEST24
TEST25_H
TEST25_L
T11
T12
M_TEST
T13
T14
TEST35
FS1R1
ALLOW_STOP
T15
T16
Llano do not support this thermal die
DP0_HPD 10
DP1_HPD 10
DP5_HPD 10
DP_ENBKL 10
DP_ENVDD 10
DP_INT_PWM 10
R569150_0402_1%
12
Chang to unpop (DG ref.)
20101111
R5730_0402_5%@
12
R5741K_0402_5%
12
R5821K_0402_5%
12
R5831K_0402_5%
12
R5841K_0402_5%
12
R5851K_0402_5%
12
R5891K_0402_5%
12
R5901K_0402_5%
12
ALLOW_STOP 13
C6390.1U_0402_16V4Z
12
@
2011/04/252012/04/25
C
DP0_AUXP_C 26
DP0_AUXN_C 26
ML_VGA_AUXP_C 15
ML_VGA_AUXN_C 15
LVDS
CRT
HDMI
HDT Debug conn
Compal Secret Data
AUX 2~5 are for GFX interface
use, they could be selected to I2C
or AUX logic
VDDIO level
Need Level shift
VDDIO level
Need Level shift
VDDIO level
Need Level shift
APU_TRST#
R5980_0402_5%
R60110K_0402_5%
R60310K_0402_5%
R60510K_0402_5%
Deciphered Date
D
To LVDS
Translator
To FCH
Asserted as an input to force the
processor into the HTC-active state
APU_PROCHOT#
THERMTRIP shutdown
temperature: 125 degree
APU_THERMTRIP#
+1.5V
12
12
12
12
D
MISC
12
+1.5V
R610
1K_0402_5%
12
MMBT3904_NL_SOT23-3
JP1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
SAMTE_ASP-136446-07-B
CONN@
Custom
Date:Sheetof
E
If not used, pins are left unconnected (DG ref.)
20101111
DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN
TEST25_L
TEST25_H
TEST35
M_TEST
FS1R1
FS1R1 : Control S5 Dual PWR plane
In laptop, seems no use
ALLOW_STOP
APU_RST#
APU_PWRGD
R586
1K_0402_5%
R591
12
0_0402_5%
Indicates to the FCH that a thermal trip
12
has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
22U_0805_6.3V6M
C984
22U_0805_6.3V6M
C985
1
1
2
C1003
1
2
C15
1
2
C1030
1
2
Decoupling betw een CPU and DI MMs
across VDDIO an d VSS split
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
12
R6372.2K_0402_5%
12
R638
4.7K_0402_5%
2011/04/252012/04/25
Compal Secret Data
+3VS
12
R635
47K_0402_5%
C
Q21
2
B
E
31
Deciphered Date
12
R636
4.7K_0402_5%
13
D
Q20
2
G
2N7002K_SOT23-3
S
MMBT3904_NL_SOT23-3
2
APU_INVT_PWM 26,27
Q15 / Q19 / Q21 change to SB000006A00
20101228
Title
AMD FS1 Singal Level Shifter
Size Document NumberRev
Custom
QBL60 LA-7552P
Date:Sheetof
1
1053Monday, April 25, 2011
1.0
A
+1.5V+1.5V+VREF_DQ
JDIMM2
15mil
VREF_DQ1VSS1
3
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDM0
DDRA_SDQ2
11
DDRA_SDQS1#7
DDRA_SDQS17
DDRA_SDQS2#7
DDRA_SDQS27
DDRA_CKE07
22
33
44
C1080
2.2U_0603_6.3V4Z
DDRA_SBS2#7
DDRA_CLK07
DDRA_CLK0#7
DDRA_SBS0#7
DDRA_SWE#7
DDRA_SCAS#7DDRA_ODT0 7
DDRA_SCS1#7
DDRA_SDQS4#7
DDRA_SDQS47
DDRA_SDQS6#7
DDRA_SDQS67
+3VS
1
1
C1081
0.1U_0402_16V4Z
2
2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#DDRA_ODT0
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R643 10K_0402_5%
+3VS
12
12
R645
10K_0402_5%
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013310-1
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A11
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
B
2
DDRA_SDQ4
4
DDRA_SDQ5
6
8
DDRA_SDQS0#
10
DDRA_SDQS0
12
14
DDRA_SDQ6
16
DDRA_SDQ7
18
20
DDRA_SDQ12
22
DDRA_SDQ13
24
26
DDRA_SDM1
28
MEM_MA_RST#
30
32
DDRA_SDQ14
34
DDRA_SDQ15
36
38
DDRA_SDQ20
40
DDRA_SDQ21
42
44
DDRA_SDM2
46
48
DDRA_SDQ22
50
DDRA_SDQ23
52
54
DDRA_SDQ28
56
DDRA_SDQ29
58
60
DDRA_SDQS3#
62
DDRA_SDQS3
64
66
DDRA_SDQ30
68
DDRA_SDQ31
70
72
DDRA_CKE1
74
76
DDRA_SMA15
78
DDRA_SMA14
80
82
DDRA_SMA11
84
DDRA_SMA7
86
A7
88
DDRA_SMA6
90
A6
A4
A2
A0
G2
DDRA_SMA4
92
94
DDRA_SMA2
96
DDRA_SMA0
98
100
DDRA_CLK1
102
DDRA_CLK1#
104
106
DDRA_SBS1#
108
DDRA_SRAS#
110
112
DDRA_SCS0#
114
116
118
DDRA_ODT1
120
122
124
15mil
126
128
DDRA_SDQ36
130
DDRA_SDQ37
132
134
DDRA_SDM4
136
138
DDRA_SDQ38
140
DDRA_SDQ39
142
144
DDRA_SDQ44
146
DDRA_SDQ45
148
150
DDRA_SDQS5#
152
DDRA_SDQS5
154
156
DDRA_SDQ46
158
DDRA_SDQ47
160
162
DDRA_SDQ52
164
DDRA_SDQ53
166
168
DDRA_SDM6
170
172
DDRA_SDQ54
174
DDRA_SDQ55
176
178
DDRA_SDQ60
180
DDRA_SDQ61
182
184
DDRA_SDQS7#
186
DDRA_SDQS7
188
190
DDRA_SDQ62
192
DDRA_SDQ63
194
196
MEM_MA_EVENT#
198
200
202
204
206
+0.75VS
DDRA_SDQS0# 7
DDRA_SDQS0 7
MEM_MA_RST# 7
DDRA_SDQS3# 7
DDRA_SDQS3 7
DDRA_CKE1 7
DDRA_CLK1 7
DDRA_CLK1# 7
DDRA_SBS1# 7
DDRA_SRAS# 7
DDRA_SCS0# 7
DDRA_ODT1 7
1
C1066
1000P_0402_50V7K
2
DDRA_SDQS5# 7
DDRA_SDQS5 7
DDRA_SDQS7# 7
DDRA_SDQS7 7
MEM_MA_EVENT# 7
FCH_SDATA0 12,14,32
FCH_SCLK0 12,14,32
+VREF_CA
C
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
Place near DIMM1
+1.5V
0.1U_0402_16V4Z
2
C1067
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1077
1
0.1U_0402_16V4Z
15mil
4.7U_0603_6.3V6K
+VREF_DQ
1
1
@
C1060
2
2
0.1U_0402_16V4Z
DDRA_SDQ[0..63] 7
DDRA_SDM[0..7] 7
DDRA_SMA[0..15] 7
2
C1068
1
0.1U_0402_16V4Z
2
C1078
1
4.7U_0603_6.3V6K
1
C1061
2
1000P_0402_50V7K
2
1
C1062
0.1U_0402_16V4Z
2
C1070
C1069
1
C11060.1U_0402_16V4Z
1
C1079
2
+1.5V+VREF_DQ
R639
1K_0402_1%
12
R641
1K_0402_1%
12
D
2
C1071
1
0.1U_0402_16V4Z
+1.5V+0.75VS
@
12
Add C1106
20101101
0.1U_0402_16V4Z
2
C1072
1
4.7U_0603_6.3V6K
1
2
2
C1073
1
0.1U_0402_16V4Z
15mil
+VREF_CA
1
@
C1063
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1074
1
1
C1064
2
1000P_0402_50V7K
2
C1075
1
0.1U_0402_16V4Z
+1.5V+VREF_CA
C1065
0.1U_0402_16V4Z
2
C1076
1
R640
1K_0402_1%
12
R642
1K_0402_1%
12
E
Security Classification
DIMM_A STD H:9.2mm
<Address: 00>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
Custom
D
Date:Sheetof
Compal Electronics, Inc.
DDRIII SO-DIMM 1
QBL60 LA-7552P
E
1153Monday, April 25, 2011
1.0
A
B
C
D
E
DQ4
DQ5
DQ6
DQ7
DM1
DM2
NC2
DM4
DM6
SDA
A15
A14
A11
CK1
BA1
S0#
SCL
+1.5V+1.5V
2
DDRB_SDQ4
4
DDRB_SDQ5
6
8
DDRB_SDQS0#
10
DDRB_SDQS0
12
14
DDRB_SDQ6
16
DDRB_SDQ7
18
20
DDRB_SDQ12
22
DDRB_SDQ13
24
26
DDRB_SDM1
28
MEM_MB_RST#
30
32
DDRB_SDQ14
34
DDRB_SDQ15
36
38
DDRB_SDQ20
40
DDRB_SDQ21
42
44
DDRB_SDM2
46
48
DDRB_SDQ22
50
DDRB_SDQ23
52
54
DDRB_SDQ28
56
DDRB_SDQ29
58
60
DDRB_SDQS3#
62
DDRB_SDQS3
64
66
DDRB_SDQ30
68
DDRB_SDQ31
70
72
DDRB_CKE1
74
76
DDRB_SMA15
78
DDRB_SMA14
80
82
DDRB_SMA11
84
DDRB_SMA7
86
A7
88
DDRB_SMA6
90
A6
A4
A2
A0
G2
DDRB_SMA4
92
94
DDRB_SMA2
96
DDRB_SMA0
98
100
DDRB_CLK1
102
DDRB_CLK1#
104
106
DDRB_SBS1#
108
DDRB_SRAS#
110
112
DDRB_SCS0#
114
DDRB_ODT0DDRB_SCAS#
116
118
DDRB_ODT1
120
122
124
15mil
126
128
DDRB_SDQ36
130
DDRB_SDQ37
132
134
DDRB_SDM4
136
138
DDRB_SDQ38
140
DDRB_SDQ39
142
144
DDRB_SDQ44
146
DDRB_SDQ45
148
150
DDRB_SDQS5#
152
DDRB_SDQS5
154
156
DDRB_SDQ46
158
DDRB_SDQ47
160
162
DDRB_SDQ52
164
DDRB_SDQ53
166
168
DDRB_SDM6
170
172
DDRB_SDQ54
174
DDRB_SDQ55
176
178
DDRB_SDQ60
180
DDRB_SDQ61
182
184
DDRB_SDQS7#
186
DDRB_SDQS7
188
190
DDRB_SDQ62
192
DDRB_SDQ63
194
196
MEM_MB_EVENT#
198
200
202
204
206
+0.75VS
DDRB_SDQS0# 7
DDRB_SDQS0 7
MEM_MB_RST# 7
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_CKE1 7
DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
DDRB_ODT1 7
1
C1088
1000P_0402_50V7K
2
DDRB_SDQS5# 7
DDRB_SDQS5 7
DDRB_SDQS7# 7
DDRB_SDQS7 7
MEM_MB_EVENT# 7
FCH_SDATA0 11,14,32
FCH_SCLK0 11,14,32
+VREF_CA
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
DDRB_SDQ[0..63] 7
DDRB_SDM[0..7] 7
DDRB_SMA[0..15] 7
Place near DIMM2
+1.5V
0.1U_0402_16V4Z
2
2
C1089
1
0.1U_0402_16V4Z
+0.75VS
0.1U_0402_16V4Z
+VREF_DQ+VREF_CA
15mil15mil
4.7U_0603_6.3V6K
1
@
C1082
2
C1090
1
0.1U_0402_16V4Z
2
2
C1099
1
1
+VREF_DQ+VREF_CA
0.1U_0402_16V4Z
1
C1083
2
1000P_0402_50V7K
2
C1091
1
0.1U_0402_16V4Z
1
C1101
C1100
2
4.7U_0603_6.3V6K
1
C1084
2
0.1U_0402_16V4Z
2
1
C11070.1U_0402_16V4Z
4.7U_0603_6.3V6K
1
2
C1092
0.1U_0402_16V4Z
@
12
0.1U_0402_16V4Z
@
C1085
2
1
1
2
C1093
Add C1107
20101101
C1086
0.1U_0402_16V4Z
2
C1094
1
1
C1087
2
1000P_0402_50V7K
2
C1095
1
0.1U_0402_16V4Z
+1.5V+1.5V
1
+
C9
330U_X_2VM_R6M@
2
0.1U_0402_16V4Z
2
C1096
1
2
C1097
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1098
1
+VREF_DQ
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDM0
DDRB_SDQ2
+3VS
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_CLK0
DDRB_CLK0#
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R646 10K_0402_5%
12
12
<BOM Structure>
R648
<BOM Structure>
10K_0402_5%
11
DDRB_SDQS1#7
DDRB_SDQS17
DDRB_SDQS2#7
DDRB_SDQS27
DDRB_CKE07
22
33
44
DDRB_SBS2#7
DDRB_CLK07
DDRB_CLK0#7
DDRB_SBS0#7
DDRB_SWE#7
DDRB_SCAS#7
DDRB_SCS1#7
DDRB_SDQS4#7
DDRB_SDQS47
DDRB_SDQS6#7
DDRB_SDQS67
15mil
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
DQ14
DQ15
DQ20
DQ21
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
Security Classification
DIMM_B STD H:5.2mm
<Address: 01>
A
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
Custom
D
Date:Sheetof
Compal Electronics, Inc.
DDRIII SO-DIMM 2
QBL60 LA-7552P
E
1253Monday, April 25, 2011
1.0
A
C1195150P_0402_50V8J
12
R82933_ 0402_5%
PCI Host Bus Reset (To EC)
11
GPP Port0 For USB30 on SUS/B
GPP Port0 For USB30 on SUS/B
GPP Port0 For USB30 on SUS/BGPP Port0 For USB30 on SUS/BGPP Port1 For USB30 on M/B 20101103
GPP Port1 For USB30 on M/B 20101103
GPP Port1 For USB30 on M/B 20101103GPP Port1 For USB30 on M/B 20101103
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
APU_PG/APU_RST#/LDT_STP# : OD pin
DMA_ACTIVE# : IN/OD, 0.8V threshold
PROCHOT# : IN, 0.8V threshold
LDT_STP : No use, NC
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.
12
CLRP1
SHORT PADS
@
Custom
Date:Sheetof
E
+3VALW
C1193
@
12
0.1U_0402_16V4Z
5
@
2
P
B
4
Y
1
A
G
U26
NC7SZ08P5X_NL_SC70-5
3
12
R8350_0402_5%
+3VALW
C1199
@
12
0.1U_0402_16V4Z
5
U27
2
P
B
1
A
G
3
R8320_0402_5%
+1.5VS
12
R834
B
2
E
31
C
Q38
MMBT3904_NL_SOT23-3
+RTCVCC
1
C1204
2
Title
Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
Size Document NumberRev
QBL60 LA-7552P
12
4
Y
R8300_0402_5%@
12
R831 100K_0402_5%@
12
+3VS
R836
4.7K_0402_5%
12
+RTCBATT
CONN@
D23
1
DAN202UT106_SC70-3
0.1U_0402_16V4Z
Compal Electronics, Inc.
PLT_RST# 18,26,29,32
Q38 change to SB000006A00
20101228
APU_PWRGD_L 47
1
JRTC1
+
SUYIN_060003HA002G202ZL
-
2
+RTCBATT
12
2
3
1353Monday, April 25, 2011
E
R857
1K_0402_5%
+CHGRTC
1.0
A
B
C
D
E
PCIE_RST2 : Reset PCIE device on Hudson2
U25D
AB6
EC_LID_OUT#36
SLP_S3#36
SLP_S5#36
PBTN_OUT#36
FCH_PWRGD36
11
EC_GA2036
EC_KBRST#36
EC_SCI#36
EC_SMI#36
HDA_BITCLK_AUDIO30
HDA_SDOUT_AUDIO30
HDA_SDIN030
HDA_SYNC_AUDIO30
HDA_RST_AUDIO#30
USB_OC2#
USB_OC0#
USB_OC1#
H_THERMTRIP#
FCH_SCLK1
FCH_SDATA1
EC_LID_OUT#
FCH_PCIE_WAKE#
FCH_SCLK0
FCH_SDATA0
MINI1_CLKREQ#
LAN_CLKREQ#_1
Modify 20101111
EC_RSMRST#
HDA_BITCLK
HDA_SDIN0
HDA_SDIN1
A
FCH_PCIE_WAKE#29,32,36
H_THERMTRIP#8
EC_RSMRST#36
LAN_CLKREQ#29
FCH_SCLK011,12,32
FCH_SDATA011,12,32
MINI1_CLKREQ#32
VGA_PD16
USB_OC2#34
USB_OC1#34
USB_OC0#34
+3VALW
@
+3VALW
THERMTRIP:
Need level shift from +3VALW to +1.5V
SM bus 0-->S0 PWR domain
M bus 1-->S5 PWR domain
S
VGA_PD: Support MLDAC power
save if connect
0: MLDAC power on
1: MLDAC power off
22
+3VALW
12
R56100K_0402_5%
33
44
R55100K_0402_5%
12
R54100K_0402_5%
12
R87110K_0402_5%
12
R8742.2K_0402_5%
12
R8762.2K_0402_5%
12
R87710K_0402_5%
12
R87810K_0402_5%
+3VS
12
R8802.2K_0402_5%
12
R8812.2K_0402_5%
12
R8828.2K_0402_5%
12
R9408.2K_0402_5%
12
R8842.2K_0402_5%
12
R88510K_0402_5%
12
R88610K_0402_5%
12
R88810K_0402_5%
12
@
@
@
@
@
Modify 2010212-AMD request
Modify 2010212-AMD request
+3VALW
FCH_PCIE_WAKE#
+3VS
R810_0402_5%
Modify 2010212-AMD request
8.2K_0402_5%
@
12
8.2K_0402_5%
12
12
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
MINI1_CLKREQ#
VGA_PD
USB_OC2#
USB_OC1#
USB_OC0#
R86633_0402_5%
12
R86733_0402_5%
12
R86833_0402_5%
12
R86933_0402_5%
12
8.2K_0402_5%
@
8.2K_0402_5%
@
12
12
R47
R45
R43
FCH_GPIO189
FCH_GPIO190
FCH_GPIO191
8.2K_0402_5%
@
8.2K_0402_5%
@
R48
12
12
Project SKU ID
GPIO189 (use VGA)L(NO)
R46
R44
GPIO190 (use PX)
GPIO191
Add Project ID Table
201011301600
For FCH internal debug use
@
12
R8872.2K_0402_5%
@
12
R8892.2K_0402_5%
@
12
R8902.2K_0402_5%
EC_LID_OUT#
TEST0
TEST1
TEST2
SYS_RESET#
@
12
R18 10K_0402_5%
12
R862 10K_0402 _5%
12
R87310K_0402_5%
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SYNC
HDA_RST#
TEST0
TEST1
TEST2
LAN_CLKREQ#_1
T29
T31
T35
T27
FCH_GPIO189
FCH_GPIO190
FCH_GPIO191
H(YES)
R44
R43
H(YES)
L(NO)
R46
R45
L(15")
H(17")
R48
R47
B
PCIE_RST2#/PCI_PME#/GEVENT4#
R2
RI#/GEVENT22#
W7
SPI_CS3#/GBE_STAT1/GEVENT21#
T3
SLP_S3#
W2
SLP_S5#
J4
PWR_BTN#
N7
PWR_GOOD
T9
TEST0
T10
TEST1/TMS
V9
TEST2
AE22
GA20IN/GEVENT0#
AG19
KBRST#/GEVENT1#
R9
LPC_PME#/GEVENT3#
C26
LPC_SMI#/GEVENT23#
T5
LPC_PD#/GEVENT5#
U4
SYS_RESET#/GEVENT19#
K1
WAKE#/GEVENT8#
V7
IR_RX1/GEVENT20#
R10
THRMTRIP#/SMBALERT#/GEVEN T2#
AF19
WD_PWRGD
U2
RSMRST#
AG24
CLK_REQ4#/SATA_IS0#/GPIO64
AE24
CLK_REQ3#/SATA_IS1#/GPIO63
AE26
SMARTVOLT1/SATA_IS2#/GPIO50
AF22
CLK_REQ0#/SATA_IS3#/GPIO60
AH17
SATA_IS4#/FANOUT3/GPIO55
AG18
SATA_IS5#/FANIN3/GPIO59
AF24
SPKR/GPIO66
AD26
SCL0/GPIO43
AD25
SDA0/GPIO47
T7
SCL1/GPIO227
R7
SDA1/GPIO228
AG25
CLK_REQ2#/FANIN4/GPIO62
AG22
CLK_REQ1#/FANOUT4/GPIO61
J2
IR_LED#/LLB#/GPIO184
AG26
SMARTVOLT2/SHUTDOWN #/GPIO51
V8
DDR3_RST#/GEVENT7#/VGA_PD
W8
GBE_LED0/GPIO183
Y6
SPI_HOLD#/GBE_LED1/GEVENT9#
V10
GBE_LED2/GEVENT10#
AA8
GBE_STAT0/GEVENT11#
AF25
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
M7
BLINK/USB_OC7#/GEVENT18#
R8
USB_OC6#/IR_TX1/GEVENT6#
T1
USB_OC5#/IR_TX0/GEVENT17#
P6
USB_OC4#/IR_RX0/GEVENT16#
F5
USB_OC3#/AC_PRES/TDO/GEVENT15#
P5
USB_OC2#/TCK/GEVENT14#
J7
USB_OC1#/TDI/GEVENT13#
T8
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12 #
AB3
AZ_BITCLK
AB1
AZ_SDOUT
AA2
AZ_SDIN0/GPIO167
Y5
AZ_SDIN1/GPIO168
Y3
AZ_SDIN2/GPIO169
Y1
AZ_SDIN3/GPIO170
AD6
AZ_SYNC
AE4
AZ_RST#
K19
PS2_DAT/SDA4/GPIO187
J19
PS2_CLK/CEC/SCL4/GPIO188
J21
SPI_CS2#/GBE_STAT2/GPIO166
D21
PS2KB_DAT/GPIO189
C20
PS2KB_CLK/GPIO190
D23
PS2M_DAT/GPIO191
C22
PS2M_CLK/GPIO192
F21
KSO_0/GPIO209
E20
KSO_1/GPIO210
F20
KSO_2/GPIO211
A22
KSO_3/GPIO212
E18
KSO_4/GPIO213
A20
KSO_5/GPIO214
J18
KSO_6/GPIO215
H18
KSO_7/GPIO216
G18
KSO_8/GPIO217
B21
KSO_9/GPIO218
K18
KSO_10/GPIO219
D19
KSO_11/GPIO220
A18
KSO_12/GPIO221
C18
KSO_13/GPIO222
B19
KSO_14/GPIO223
B17
KSO_15/GPIO224
A24
KSO_16/GPIO225
D17
KSO_17/GPIO226
HUDSON-M2_FCBGA656
M2@
HUDSON-2
EMBEDDED CTRL
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
GL-02/10/2011: Please enabled integrated pull-up/pull-down and left unconnected.
FCH_SPI_CS1#
FCH_SPI_WP#
FCH_SPI_HOLD#
FCH_SPI_CLK
Add for EMI 201011291330
Change to PD 20101112
Add SYS BIOS ROM
20101111
FCH_CRT_HPD
1
3
7
4
@
GBE_MDIO
GBE_PHY_INTR
GBE_COL
GBE_CRS
GBE_RXERR
E
U28
CS#
WP#
HOLD#
GND
MX25L1606EM2I-12G SOP 8P
SA000041N00
R36
@
12
8
VCC
6
SCLK
5
SI
2
SO
10_0402_5%
12
R89110K_0402_5%
12
R89210K_0402_5%
12
R89310K_0402_5%
12
R89410K_0402_5%
12
R89510K_0402_5%
@
+3VALW
C4660.1U_0402_16V4Z
12
@
FCH_SPI_CLK
FCH_SPI_MOSI
FCH_SPI_MISO
C23
@
12
10P_0402_50V8J
+3VALW
+FCH_VDDAN_33_DAC_R
12
R90410K_0402_5%
44
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
Custom
D
Date:Sheetof
Compal Electronics, Inc.
Hudson-M2/M3-SATA/GBE/HWM
QBL60 LA-7552P
1553Monday, April 25, 2011
E
1.0
A
STRAP PINS
B
C
D
E
PCI_CLK1
11
22
PULL
HIGH
PULL
LOW
PCI_CLK113
PCI_CLK313
PCI_CLK413
LPC_CLK0_EC13,36
LPC_CLK113
EC_PWM214
RTC_CLK13,36
ALLOW
PCIE GEN2
DEFAULT
FORCE
PCIE GEN1
@
PCI_CLK3
USE
DEBUG
STRAPS
IGNORE
DEBUG
STRAP
DEFAULT
R905 10K_0402_5%
12
@
R915 1 0K_0402_5%
12
PCI_CLK4LPC_CLK0
NON_FUSION
CLOCK MODE
FUSION
CLOCK
MODE
DEFAULT
R906 10K_0402 _5%
12
@
R917 1 0K_0402_5%
12
EC
ENABLED
EC
DISABLED
DEFAULT
R907 10K_0402 _5%
12
@
R918 1 0K_0402_5%
12
CLKGEN
ENABLED
DEFAULT
CLKGEN
DISABLE
R908 10K_0402 _5%
12
R919 1 0K_0402_5%
12
@
EC_PWM2
LPC ROM
DEFAULT
SPI ROM
R909 10K_0402 _5%
12
R920 1 0K_0402_5%
12
@
DEBUG STRAPS
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
33
PULL
HIGH
PULL
LOW
PCI_AD27PCI_AD26
USE PCI
PLL
DEFAULT
BYPASS
PCI PLL
DISABLE
ILA
AUTORUN
DEFAULT
ENABLE
ILA
AUTORUN
PCI_AD25PCI_AD24
USE FC
PLL
BYPASS
FC PLL
USE DEFAULT
PCIE STRAPS
DEFAULT
USE EEPROM
PCIE STRAPS
PCI_AD23
DISABLE PCI
MEM BOOT
DEFAULTD EFAULT
ENABLE PCI
MEM BOOT
RTC_CLKLPC_CLK1
S5 PLUS
MODE
DISABLED
DEFAULT
S5 PLUS
MODE
ENABLED
+3VALW+3VALW+3VALW+3VALW+3VS+3VS+3VS
R910 10K_0402 _5%
12
R921 2 .2K_0402_5%
12
R911 10K_0402 _5%
12
R922 2 .2K_0402_5%
12
@
VGA_PD: Support MLDAC power
save if not connect
0: MLDAC power on
1: MLDAC power off
Check VGA_PD states
If support ML DAC power down when no VGA plug
L47
12
FBMA-L11-201209-221LMA30T_0805
+3VS+FCH_VDDAN_33_DAC_R
AP2301GN-HF_SOT23-3
VGA_PD#
+1.1VS+FCH_VDDAN_11_MLDAC
AP2301GN-HF_SOT23-3
VGA_PD#
VGA_PD14
220 ohm
Q39
@
31
2
AO3413 Vgs(max)=1V
R9120_0402_5%
12
Q40
@
31
2
R923
1K_0402_5%
@
12
R925
2.2K_0402_5%
C1212
12
FBMA-L11-201209-221LMA30T_0805
12
R9130_0402_5%
@
12
1U_0402_6.3V4Z
30mil
+FCH_VDDAN_33_DAC
0_0402_5%
R924
@
1
2
L48
@
12
20 ohm
2
12
34
5
C1210
C1209
1
1
2
2
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
30mil
+3VS
R914
100K_0402_5%
R916
100K_0402_5%
12
VGA_PD#
DMN66D0LDW-7_SOT363-6
61
Q41B
DMN66D0LDW-7_SOT363-6
2
1U_0402_6.3V4Z
C1211
1
@
2
Q41A
PCI_AD2713
PCI_AD2613
PCI_AD2513
PCI_AD2413
PCI_AD2313
44
A
R926 2.2K_0402_5%
12
@
R927 2.2K_0402_5%
12
@
R928 2.2K_0402_5%
12
@
R929 2.2K_0402_5%
12
@
B
R930 2.2K_0402_5%
12
@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
Custom
D
Date:Sheetof
Compal Electronics, Inc.
Hudson-M2/M3-STRAP
QBL60 LA-7552P
E
1653Monday, April 25, 2011
1.0
A
B
C
D
E
C1218 / C1219 / C1247 Change to SE00000I10
20101228
131mA
R20
12
+3VS
11
+FCH_VDDAN_33_DAC_R
+3VS
+3VALW
22
+VDDAN_33_USB
+3VS
+3VS
33
For FCH M2 - BOM option
VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S
Connected to VSS.
44
L3
12
MBK1608221YZF_2P
220 ohm
12
0_0603_5%
12
220 ohm
L6
M3@
12
+FCH_VDDPL_33_MLDAC
+FCH_VDDPL_33_SSUSB_S
R19
L4
@
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm
L7
+FCH_VDDPL_33_USB_S
12
0_0603_5%
Change to 0ohm-AMD request
20110212
L15
12
MBK1608221YZF_2P
220 ohm
L22
12
MBK1608221YZF_2P
220 ohm
M2@
M2@
C1281
C1275
0_0402_5%
0_0402_5%
21
21
+VDDPL_3.3V
2.2U_0603_6.3V4Z
C1222
1
2
2.2U_0603_6.3V4Z
C1227
1
2
2.2U_0603_6.3V4Z
C1238
1
M3@
M3@
2
2.2U_0603_6.3V4Z
C1248
1
2
+VDDPL_33_PCIE
2.2U_0603_6.3V4Z
C1258
1
2
+VDDPL_33_SATA
2.2U_0603_6.3V4Z
C1266
1
2
A
.1U_0402_16V7K
C1229
1
2
.1U_0402_16V7K
C1231
VDDPL_33_SSUSB_S
1
For Hudson3 USB3.0 only
For Hudson2, connect to GND
2
LDO_CAP: Internally generated 1.8V
supply for the RGB outputs
+FCH_VDDAN_11_MLDAC
.1U_0402_16V7K
C1239
1
2
.1U_0402_16V7K
C1249
1
2
.1U_0402_16V7K
C1259
1
2
.1U_0402_16V7K
C1267
1
2
+1.1VALW
+3VS
+VDDPL_3.3V
+FCH_VDDPL_33_MLDAC
12
MBK1608221YZF_2P
2
20 ohm/2A
+3VALW
FBMA-L11-201209-221LMA30T_0805
+1.1VALW
+1.1VALW
0_0603_5%
For A11: Cap = 1nF
For A12, Cap = DNI
L24
+VDDPL_11_DAC_L+VDDPL_11_DAC
L54
12
220 ohm/2A
L57
12
MBK1608221YZF_2P
220 ohm
L59
12
MBK1608221YZF_2P
2
20 ohm
+FCH_VDD_11_SSUSB_S
40mils
M3@
+FCH_VDD_11_SSUSB_S
12
L61
FBMA-L11-201209-221LMA30T_0805
42 ohm/4A
47mA
20mA
20mA
200mA
+FCH_VDDAN_33_DAC_R
R9360_0402_5%M2@
+FCH_VDDPL_33_USB_S
+VDDPL_33_PCIE
+VDDPL_33_SATA
658mA
140mA
197mA
R11490_0603_5%
R11500_0603_5%
22U_0805_6.3V6M
C1218
1
2
12
R220_0402_5%
12
R230_0402_5%
20mA
12
17mA
43mA
93mA
7mA
12
R240_0402_5%
226mA
12
R1148
0_0603_5%
R1242 change to 2.2uf-AMD request
20110212
1U_0402_6.3V6K
C1254
C1253
1
1
2
2
2.2U_0603_6.3V4Z
C1263
C1262
1
1
2
2
2.2U_0603_6.3V4Z
C1268
C1269
1
1
2
2
282mA
M3@
12
M3@
424mA
M3@
12
B
+VDDIO_33_PCIGP
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
C1221
C1220
C1228
1
2
C12322.2U_0603_6.3V4Z
C1240
4.7U_0603_6.3V6K
1
2
12
R9450_0402_5%
1U_0402_6.3V6K
C1255
.1U_0402_16V7K
.1U_0402_16V7K
C1270
1U_0402_6.3V6K
C1273
1
2
C1278
M3@
1
1
2
2
+VDDPL_33_DAC
+VDDPL_33_ML
+FCH_VDDPL_33_SSUSB_S
@
12
+VDDAN_11_ML
2.2U_0603_6.3V4Z
.1U_0402_16V7K
C1242
C1241
1
1
2
2
+VDDAN_33_USB
10U_0603_6.3V6M
10U_0603_6.3V6M
C1256
C1257
1
1
2
+VDDAN_11_USB_S
+VDDCR_1.1V_USB
.1U_0402_16V7K
1
2
+VDDAN_SSUSB
C1274
M3@
+VDDCR_11_SSUSB
10U_0603_6.3V6M
1
2
1
2
M3@
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
C1275
1
M3@
2
1U_0402_6.3V6K
C1280
C1279
1
1
M3@
2
2
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
10mils
20mils
30mils
.1U_0402_16V7K
10mils
10mils
20mils
30mils
.1U_0402_16V7K
M3@
C1281
U25C
AB17
VDDIO_33_PCIGP_1
AB18
VDDIO_33_PCIGP_2
AE9
VDDIO_33_PCIGP_3
AD10
VDDIO_33_PCIGP_4
AG7
VDDIO_33_PCIGP_5
AC13
VDDIO_33_PCIGP_6
AB12
VDDIO_33_PCIGP_7
AB13
VDDIO_33_PCIGP_8
AB14
VDDIO_33_PCIGP_9
AB16
VDDIO_33_PCIGP_10
H24
VDDPL_33_SYS
V22
VDDPL_33_DAC
U22
VDDPL_33_ML
T22
VDDAN_33_DAC
L18
VDDPL_33_SSUSB_S
D7
VDDPL_33_USB_S
AH29
VDDPL_33_PCIE
AG28
VDDPL_33_SATA
M31
LDO_CAP
V21
VDDPL_11_DAC
Y22
VDDAN_11_ML_1
V23
VDDAN_11_ML_2
V24
VDDAN_11_ML_3
V25
VDDAN_11_ML_4
AB10
VDDIO_33_GBE_S
AB11
VDDCR_11_GBE_S_1
AA11
VDDCR_11_GBE_S_2
AA9
VDDIO_GBE_S_1
AA10
VDDIO_GBE_S_2
G7
VDDAN_33_USB_S_1
H8
VDDAN_33_USB_S_2
J8
VDDAN_33_USB_S_3
K8
VDDAN_33_USB_S_4
K9
VDDAN_33_USB_S_5
M9
VDDAN_33_USB_S_6
M10
VDDAN_33_USB_S_7
N9
VDDAN_33_USB_S_8
N10
VDDAN_33_USB_S_9
M12
VDDAN_33_USB_S_10
N12
VDDAN_33_USB_S_11
M11
VDDAN_33_USB_S_12
U12
VDDAN_11_USB_S_1
U13
VDDAN_11_USB_S_2
T12
VDDCR_11_USB_S_1
T13
VDDCR_11_USB_S_2
P16
VDDAN_11_SSUSB_S_1
M14
VDDAN_11_SSUSB_S_2
N14
VDDAN_11_SSUSB_S_3
P13
VDDAN_11_SSUSB_S_4
P14
VDDAN_11_SSUSB_S_5
N16
VDDCR_11_SSUSB_S_1
N17
VDDCR_11_SSUSB_S_2
P17
VDDCR_11_SSUSB_S_3
M17
VDDCR_11_SSUSB_S_4
HUDSON-M2_FCBGA656
.1U_0402_16V7K
M2@
1
Security Classification
2
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
<DIGON>
Controls panel digital power on/off.
Active High ,external PD need
U8G
LVDS CONTROL
LVTMDP
2160809000A11SEYMOU_FCBGA962
VGA@
VARY_BL
DIGON
TXCLK_U P_DPF3P
TXCLK_U N_DPF3N
TXOUT_U 0P_DPF2P
TXOUT_U 0N_DPF2N
TXOUT_U 1P_DPF1P
TXOUT_U 1N_DPF1N
TXOUT_U 2P_DPF0P
TXOUT_U 2N_DPF0N
TXOUT_U 3P
TXOUT_U 3N
TXCLK_L P_DPE3P
TXCLK_L N_DPE3N
TXOUT_L 0P_DPE2P
TXOUT_L 0N_DPE2N
TXOUT_L 1P_DPE1P
TXOUT_L 1N_DPE1N
TXOUT_L 2P_DPE0P
TXOUT_L 2N_DPE0N
TXOUT_L 3P
TXOUT_L 3N
PE_GPIO013
PLT_RST#13,26,29,32
2.2K_0402_5%
<VARY_BL>
LCD PWM (pulse width modulated)
output to adjust LCD brightness
Active High ,external PD need
R38610K_0402_5%VGA@
AK27
AJ27
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36
AP34
AR34
AW3 7
AU35
AR37
AU39
AP35
AR35
AN36
AP37
@
R394
12
R38710K_0402_5%VGA@
12
+3VSG
12
VGA@
U21
5
2
P
B
1
A
G
3
NC7SZ08P5X_NL_SC70-5
@
12
R1590_0402_5%
E
VGA_RST#
4
Y
44
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
VGA@
VGA@
C331
22U_0805_6.3V6M
AMD ref:120ohm/0.3A
12
+1.8VSG
+VDD1DI
@
@
C343
0.1U_0402_16V4Z
C344
10U_0603_6.3V6M
1
2
12
+1.8VSG
NC on Whistler
and Seymour
Whistler and Seymour
Except A2VSSQ change to TSVSSQ,
others are NC
+3VSG
+1.8VSG
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
D
External VGA Thermal Sensor
U9
VGA@
1
VDD
2
2200P_0402_50V7K
1 2
C325
VGA@
R80
@
12
0_0402_5%
R82
@
12
0_0402_5%
3
ADM1032ARMZ-2REEL_MSOP8
+3VSG
R392
4.7K_0402_5%
VGA@
SM_CK2
SM_DA2
D+
D-
THERM#4GND
R393
4.7K_0402_5%
VGA@
12
12
SM_DA2
R780_0402_5%VGA@
R790_0402_5%VGA@
AUD Strap
GPIO8 Serial-ROM output from ROM.
GPIO9 Serial-ROM input to ROM.
GPIO10 Serial-ROM clock to ROM.
GPIO22 erternal BIOS-ROM enable
GPIO8,GPIO9,GPIO10 no use can NC
GPIO22
Enable need 3K PH ,no use must NC
E
VGA_SMB_CK2
8
SCLK
7
SDATA
ALERT#
SM_CK2
12
12
Title
Vancouver_Strape/DP/HDMI//CRT
Size Document NumberRev
Custom
Date:Sheetof
THM_ALERT#
6
5
HSYNC:VSYNC
11: Audio for both DisplayPort and HDMI
VSYNC
HSYNC
12
R3914.7K_0402_5%VGA@
+3VSG
2
VGA@
EC_SMB_CK2
61
Q8A DMN66D0LDW-7_SOT363-6
5
VGA@
EC_SMB_DA2
34
Q8B DMN66D0LDW-7_SOT363-6
VGA_GPIO4
VGA_GPIO3
R41710K_0402_5%@
12
R41810K_0402_5%@
12
if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD
Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2
Park&Seymour is single channel for
MAB[0..12]
B_BA[0..2]
DQMB#[0..7]
QSB[0..7]
QSB#[0..7]
ODTB0 24
ODTB1 24
CLKB0 24
CLKB0# 24
CLKB1 24
CLKB1# 24
RASB0# 24
RASB1# 24
CASB0# 24
CASB1# 24
CSB0#_0 24
CSB1#_0 24
CKEB0 24
CKEB1 24
WEB0# 24
WEB1# 24
MAB13 24
12
MAB[0..12] 24
B_BA[0..2] 24
DQMB#[0..7] 24
QSB[0..7] 24
QSB#[0..7] 24
VRAM_RST# 23,24
memory (channel B only)
44
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
c
DPC_VDD18,DPC_PVDD,DPD_VDD18,DPD_PVDD
can combian to DPCD_VDD18
(DPD_VDD18,DPD_PVDD not applicable on Robson/Park)
DPE_VDD18,DPE_PVDD,DPF_VDD18,DPF_PVDD
can combian to DPEF_VDD18
DPx-VSSR,DPx_PVSS can combian to DP_VSSR
(Manhatann should have individual GND)
where x is A,B,C,D,E,F
PX_EN
PX_EN: PU at P.20
SBIOS will control VGA power on/off.
High :BACO mode enable
LOW:BACO disable
B
Seymour/Whistler
DPA_VDD10,DPB_VDD10
can combian to DPAB_VDD10
DPC_VDD10,DPD_VDD10
can combian to DPCD_VDD10
DPE_VDD10,DPD_VDD10
can combian to DPEF_VDD10
Manhatann:300mA
S
eymour:150mA
Manhatann:220mA
Seymour:110mA
PX_EN 25,36
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
+1.8VSG
L26
MBK1608221YZF_2P
VGA@
FootPrint
SM01000BL00
1000ma 470ohm@100mhz DCR 0.2
+1.0VSG
L27
MBK1608221YZF_2P
VGA@
FootPrint
DP mode:300mA
LVDS mode:440mA
12
VGA@
C478
10U_0603_6.3V6M
1
2
DP mode:220mA
LVDS mode:240mA
12
VGA@
C481
10U_0603_6.3V6M
1
2
Park/Madison :AL21left NC
eymour/Whistler:
S
AL21:PX_EN
use to control discreate GPU regulators
for power express BACO mode
Support BACO:
output High3.3V:turn off regulators (BACO mode on)
output Low0V:turn on regulators (BACO mode off)
need PD resistor
No support BACO:
left NC
B
C
D
::::
U8H
20mil
+DPABCD_VDD18
2
0mil
+DPABCD_VDD10
20mil
+DPABCD_VDD18
20mil
+DPABCD_VDD10
R467
150_0402_1%
12
VGA@
20mil
VGA@
0.1U_0402_16V4Z
+DPEF_VDD18
C480
20mil
+DPEF_VDD10
20mil
+DPEF_VDD18
1
2
VGA@
1U_0402_6.3V6K
C479
1
2
20mil
+DPEF_VDD10
VGA@
C483
0.1U_0402_16V4Z
R470
VGA@
150_0402_1%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
VGA@
VGA@
VGA@
C502
1U_0402_6.3V6K
C503
1U_0402_6.3V6K
1
2
+1.5VSG
VGA@
C519
10U_0603_6.3V6M
1
2
2011/04/252012/04/25
1U_0402_6.3V6K
1
1
2
2
VGA@
VGA@
10U_0603_6.3V6M
C520
10U_0603_6.3V6M
1
1
2
2
Compal Secret Data
Deciphered Date
VGA@
VGA@
C506
1U_0402_6.3V6K
C505
1U_0402_6.3V6K
C504
1
1
2
2
VGA@
C517
C518
10U_0603_6.3V6M
1
2
D
+1.5VSG
VGA@
VGA@
VGA@
1U_0402_6.3V6K
C507
1U_0402_6.3V6K
1
1
2
2
Title
Size Document NumberRev
Custom
Date:Sheetof
VGA@
VGA@
C509
1U_0402_6.3V6K
C510
C508
1U_0402_6.3V6K
C511
1
2
1U_0402_6.3V6K
1
1
2
2
Compal Electronics, Inc.
VRAM_DDR3 / Channel A
QBL60 LA-7552P
E
2353Monday, April 25, 2011
1.0
A
VREFCB_A1
VREFDB_Q1
11
B_BA020
B_BA120
R499
243_0402_1%
ODTB0_1
12
12
12
12
ODTB1_1
VGA@
VGA@
B_BA220
CLKB0CLKB0
CLKB0#
CKEB020
ODTB0_1
CSB0#_020
RASB0#20
CASB0#20
WEB0#20
QSB3
QSB1
DQMB#3
DQMB#1
QSB#3
QSB#1
VRAM_RST#
12
VGA@
+1.5VSG
R512
56_0402_1%
VGA@
R514
56_0402_1%
VGA@
1
C530
0.01U_0402_16V7K
2
1
C559
0.01U_0402_16V7K
2
MDB[0..63]20
MAB[13..0]20
DQMB#[7..0]20
QSB[7..0]20
22
QSB#[7..0]20
MDB[0..63]
VRAM_RST#20,23
Pull high for Madison and Park...
33
ODTB020
ODTB120
CLKB020
CLKB0#20
CLKB120
44
CLKB1#20
ODTB0
ODTB1
R511
0_0402_5%
R513
0_0402_5%
R523 56_0402_1%
12
VGA@
R524 56_0402_1%
12
VGA@
R525
56_0402_1%
12
VGA@
R526
56_0402_1%
12
VGA@
A
U15
M8
VREFCA
H1
VREFDQ
MAB0
N3
A0
MAB1
P7
A1
MAB2
P3
A2
MAB3
N2
A3
MAB4
P8
A4
MAB5
P2
A5
MAB6
R8
A6
MAB7
R2
A7
MAB8
T8
A8
MAB9
R3
A9
MAB10
L7
A10/AP
MAB11
R7
A11
MAB12
N7
A12
MAB13MAB13MAB13MAB13
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4B1G1646E-HC12_FBGA96
X76@
4.99K_0402_1% VGA@
4.99K_0402_1% VGA@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
96-BALL
SDRAM DDR3
+1.5VSG+1.5VSG+1.5VSG+1.5VSG
12
R503
VREFCB_A1VREFCB_A2VREFDB_Q2VREFDB_Q1
12
VGA@
1
2
1U_0402_6.3V6K
C522
VGA@
C531
1
2
VGA@
1
2
1U_0402_6.3V6K
R515
+1.5VSG+1.5VSG
B
MDB26
E3
MDB28
F7
MDB27
F2
MDB31
F8
MDB25
H3
MDB30
H8
MDB24
G2
MDB29
H7
MDB15
D7
MDB10
C3
MDB12
C8
MDB11
C2
MDB13
A7
MDB9
A2
MDB14
B8
MDB8
A3
+1.5VSG
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSG
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
R504
4.99K_0402_1% VGA@
0.1U_0402_16V4Z
R516
4.99K_0402_1% VGA@
VGA@
VGA@
C532
1U_0402_6.3V6K
C533
1U_0402_6.3V6K
1
1
2
2
B
R500
243_0402_1%
12
12
VGA@
C534
1
2
1U_0402_6.3V6K
VREFCB_A2
VREFDB_Q2
B_BA0
B_BA1
B_BA2B_BA2
CLKB0#
CKEB0
ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#
QSB2
QSB0
DQMB#2
DQMB#0
QSB#2
QSB#0
VRAM_RST#
12
VGA@
0.1U_0402_16V4Z
1
C523
VGA@
2
C535
+1.5VSG
VGA@
C551
10U_0603_6.3V6M
1
2
U16
M8
VREFCA
H1
VREFDQ
MAB0
N3
A0
MAB1
P7
A1
MAB2
P3
A2
MAB3
N2
A3
MAB4
P8
A4
MAB5
P2
A5
MAB6
R8
A6
MAB7
R2
A7
MAB8
T8
A8
MAB9
R3
A9
MAB10
L7
A10/AP
MAB11
R7
A11
MAB12
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4B1G1646E-HC12_FBGA96
X76@
4.99K_0402_1% VGA@
4.99K_0402_1% VGA@
VGA@
VGA@
C552
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
96-BALL
SDRAM DDR3
R505
R517
C554
1
2
12
12
VGA@
1
2
VGA@
10U_0603_6.3V6M
1U_0402_6.3V6K
C553
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
C524
VGA@
C536
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
2
VGA@
1
2
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
0.1U_0402_16V4Z
C537
1U_0402_6.3V6K
C
MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16
MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5
+1.5VSG
+1.5VSG
R506
4.99K_0402_1% VGA@
R518
4.99K_0402_1% VGA@
VGA@
VGA@
C539
1U_0402_6.3V6K
C538
1U_0402_6.3V6K
1
1
2
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
12
12
VGA@
1
2
1U_0402_6.3V6K
R501
243_0402_1%
1
C525
VGA@
2
C540
VREFCB_A3
VREFDB_Q3
B_BA0
B_BA1
CLKB1
CKEB120
ODTB1_1
CSB1#_020
RASB1#20
CASB1#20
WEB1#20
QSB4
QSB5
DQMB#4
DQMB#5
QSB#4
QSB#5
VRAM_RST#
12
VGA@
4.99K_0402_1% VGA@
0.1U_0402_16V4Z
4.99K_0402_1% VGA@
2011/04/252012/04/25
U17
M8
VREFCA
H1
VREFDQ
MAB0
N3
A0
MAB1
P7
A1
MAB2
P3
A2
MAB3
N2
A3
MAB4
P8
A4
MAB5
P2
A5
MAB6
R8
A6
MAB7
R2
A7
MAB8
T8
A8
MAB9
R3
A9
MAB10
L7
A10/AP
MAB11
R7
A11
MAB12
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG+1.5VSG+1.5VSG+1.5VSG
12
R507
12
R519
+1.5VSG
VGA@
1
2
96-BALL
SDRAM DDR3
1
C526
VGA@
2
VGA@
C541
1U_0402_6.3V6K
1
2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
4.99K_0402_1% VGA@
0.1U_0402_16V4Z
4.99K_0402_1% VGA@
VGA@
C542
1U_0402_6.3V6K
1
2
Compal Secret Data
Deciphered Date
D
MDB35
E3
MDB37
F7
MDB34
F2
MDB39
F8
MDB33
H3
MDB38
H8
MDB32
G2
MDB36
H7
MDB44
D7
MDB43
C3
MDB47
C8
MDB41
C2
MDB45
A7
MDB40
A2
MDB46
B8
MDB42
A3
+1.5VSG
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSG
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
R508
R520
VGA@
C544
1U_0402_6.3V6K
C543
1U_0402_6.3V6K
1
2
D
VREFCB_A4
VREFDB_Q4
B_BA0
B_BA1
B_BA2
CLKB1
CLKB1#CLKB1#
CKEB1
ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#
QSB6
QSB7
DQMB#6
DQMB#7
QSB#6
QSB#7
VRAM_RST#
12
R502
243_0402_1%
12
VREFDB_Q3VREFCB_A 3VREFCB_A4VREFDB_Q4
12
0.1U_0402_16V4Z
1
C527
VGA@
2
VGA@
C545
1U_0402_6.3V6K
1
2
+1.5VSG
1
VGA@
10U_0603_6.3V6M
2
VGA@
4.99K_0402_1% VGA@
4.99K_0402_1% VGA@
1
1
VGA@
VGA@
C556
10U_0603_6.3V6M
C555
2
2
R509
R521
U18
M8
VREFCA
H1
VREFDQ
MAB0
N3
A0
MAB1
P7
A1
MAB2
P3
A2
MAB3
N2
A3
MAB4
P8
A4
MAB5
P2
A5
MAB6
R8
A6
MAB7
R2
A7
MAB8
T8
A8
MAB9
R3
A9
MAB10
L7
A10/AP
MAB11
R7
A11
MAB12
N7
A12
T3
A13
T7
A14
M7
A15/BA3
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE/CKE0
K1
ODT/ODT0
L2
CS/CS0
J3
RAS
K3
CAS
L3
WE
F3
DQSL
C7
DQSU
E7
DML
D3
DMU
G3
DQSL
B7
DQSU
T2
RESET
L8
ZQ/ZQ0
J1
NC/ODT1
L1
NC/CS1
J9
NC/CE1
L9
NCZQ1
K4B1G1646E-HC12_FBGA96
X76@
12
12
C528
VGA@
+1.5VSG
VGA@
VGA@
C546
1U_0402_6.3V6K
1
1
2
2
1
VGA@
C558
10U_0603_6.3V6M
C557
10U_0603_6.3V6M
2
Title
VRAM_DDR3 / Channel B
Size Document NumberRev
Custom
QBL60 LA-7552P
Date:Sheetof
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
96-BALL
SDRAM DDR3
4.99K_0402_1%VGA@
0.1U_0402_16V4Z
1
4.99K_0402_1% VGA@
2
VGA@
C548
1U_0402_6.3V6K
C547
1U_0402_6.3V6K
1
2
Compal Electronics, Inc.
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R510
R522
VGA@
1
2
E
MDB55
E3
MDB49
F7
MDB52
F2
MDB50
F8
MDB53
H3
MDB48
H8
MDB54
G2
MDB51
H7
MDB56
D7
MDB59
C3
MDB63
C8
MDB62
C2
MDB57
A7
MDB61
A2
MDB58
B8
MDB60
A3
+1.5VSG
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSG
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
12
12
0.1U_0402_16V4Z
1
C529
VGA@
2
VGA@
C550
1U_0402_6.3V6K
C549
1U_0402_6.3V6K
1
2
E
2453Monday, April 25, 2011
1.0
5
4
3
2
1
Power Sequence of Whistler and Seymour
SUSP#
+3VSG
(JUMP form +3VS)
VGA_ON
DD
VGA_PWR_ON
10ms
1.5_VDDC_PWREN
+VGA_CORE
+1.5VSG
VGA Muxless with BACO Status Mapping table
Normal mode
PX_EN
1.5_VDDC_PWREN
VDDC_EN
1.0_ENVGA_PWR_ON source signal
01
10VGA Power Enable Signal Mapping table
1
01
+3.3VSGON
+1.8VSG
+1.0VSG
+VGA_CORE
+1.5VSG
ON+1.8VSG
ON
ON
ON
+BIF_VDDC+VGA_CORE
BACO mode
0
ON
ON
ON
OFF
OFF
+1.0VSG
+3.3VSG
+1.0VSG
+VDDCI
+VGA_CORE
+1.5VSG
Whislter
VGA_ON
SUSP#
VGA_PWR_ON
VGA_PWR_ON
Combine with +VGA_CORE
1.5_VDDC_PWREN
1.5_VDDC_PWREN
+1.0VSG
+1.8VSG
For PX sequence, >2mS delay is required between
P
E_GPIO1 and VGA_PWR_ON
PE_GPIO1
CC
Delay SUSP# 10ms
PE_GPIO113,36
BB
VGA@
12
R1110_0402_5%
@
R119
12
10K_0402_1%
VGA_PWR_ON>2ms
For VGA Power on control
VGA_PWR_ON
VGA_PWR_ON 38,42,45VGA_ON36
20ms
PX_EN22,36
VGA_PWRGD13,48
R6510_0402_5%
12
VGA@
R652
5.11K_0402_1%
From +VGA_CORE regulator
VGA_PWR_ON
R65010K_0402_5%
+3VS
VGA@
12
1.5_VDD_PWREN
12
VGA@
13
D
2
G
S
VGA@
0.1U_0402_16V4Z
VGA@
12
R6550_0402_5%
2
1
Q22
VGA@
2N7002K_SOT23-3
+3VS
C1104
12
2
B
1
A
@
R6490_0402_5%
12
+3VS
C1103
VGA@
0.1U_0402_16V4Z
12
VGA@
5
U19
P
B
A
5
P
G
NC7SZ08P5X_NL_SC70-5
3
1.5_VDD_PWREN
4
Y
G
NC7SZ08P5X_NL_SC70-5
3
VGA@
R653
1K_0402_5%
VGA@
U20
4
Y
2
+5VS+5VS
VGA@
R654
1K_0402_5%
12
Q23A
DMN66D0LDW-7_SOT363-6
61
5
VGA@
1.5_VDD_PWREN 38,48
12
Q23B
DMN66D0LDW-7_SOT363-6
34
VGA@
VDDC_EN
1.0_EN
+1.0VSG
AO3416_SOT23-3
1.0_EN
VDDC_EN
AA
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Place via on each trace bus and let resistor very close the via
AA
Security Class ification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/04/ 252012/04/ 25
3
Compal Secret Data
Deciphered Date
Title
Size Docu ment NumberRev
Custom
2
Date:Sheetof
Compal Electronics, Inc.
LVDS Translator-ANX3110
QBL60 LA-7552P
2653Monday, April 25, 2011
1
1.0
5
C R T
DD
C1578
1 2
C1579
1 2
0.1U_0402_16V4Z
FCH_CRT_R
FCH_CRT_G
FCH_CRT_B
+CRT_VCC
0.1U_0402_16V4Z
+CRT_VCC
FCH_CRT_R15
FCH_CRT_G15
FCH_CRT_B15
R1641
FCH_CRT_HSYNC_R
FCH_CRT_HSYNC15
CC
FCH_CRT_VSYNC15
12
0_0402_5%
R1651
FCH_CRT_VSYNC_RVSYNC_L
12
0_0402_5%
Close to APU
Panel LCDVDD Control
+LCDVDD
+LCDVDD
1
1
C1587
BB
0.1U_0402_16V4Z
C1588
0.1U_0402_16V4Z
2
2
APU_ENVDD10
TL_ENVDD26
R1652
100_0805_5%
R1659
R7120_0402_5%
12
61
@
12
12
2
2N7002DW-7-F_SOT363-6
Q99A
0_0402_5%
12
R1660
100K_0402_5%
+5VALW
12
3
5
4
Q99B
2N7002DW-7-F_SOT363-6
Panel Backlight Control
@
D14 RB751V_SOD323
21
AA
TL_BKOFF#26,36
BKOFF#36
TL_BKOFF#
BKOFF#
R7180_0402_5%@
12
@
D8 RB751V_SOD323
21
R16340_0402_5%
R16350_0402_5%
R16360_0402_5%
R1640
12
1
5
P
4
OE#
A2Y
G
U87
74AHCT1G125GW_SOT353-5
3
R1648
12
1
5
P
4
OE#
A2Y
G
U88
74AHCT1G125GW_SOT353-5
3
R1653
47K_0402_5%
4.7U_0805_10V4Z
R1656
12
220K_0402_1%
+3VS
12
@
12
12
12
1K_0402_5%
CRT_HSYNC_D
1K_0402_5%
CRT_VSYNC_D
C1585
0.047U_0402_16V7K
R1670
10K_0402_5%
DISPOFF#
+LCDVDD
1
2
C1589
W=60mils
4
12
R1637
Q93
SI2301BDS-T1-E3_SOT23-3
13
R1643
12
0_0603_5%
R1650
12
0_0603_5%
D
2
150_0402_1%
S
G
C1586
Panel PWM Control
TL_INVT_PWM26
APU_INVT_PWM10,26
EC_INVT_PWM36
+CRT_VCC
R1638
C1583
+3VS
3
RED
12
1
2
D1
2
3
AZC199-02SPR7G_SOT23-3
D2
2
3
AZC199-02SPR7G_SOT23-3
150_0402_1%
HSYNC_L
15P_0402_50V8J
L116
12
L117
12
L118
12
For EMI
HSYNC_L
VSYNC_L
VGA_DDC_DATA_C
VGA_DDC_CLK_C
R4 0_0402_5%@
12
12
R31 0_0402_5%@
2
1
1
3
2
1
1
3
CHILISIN NBQ160808T-800Y-N 0603
CHILISIN NBQ160808T-800Y-N 0603
CHILISIN NBQ160808T-800Y-N 0603
1
2
10P_0402_50V8J
FCH_CRT_DDC_SDA
FCH_CRT_DDC_SCL
FCH_CRT_DDC_SDA
FCH_CRT_DDC_SCLVGA_DDC_CLK_C
C1572
1
1
C1573
C1574
2
2
10P_0402_50V8J
10P_0402_50V8J
FCH_CRT_DDC_SDA15
FCH_CRT_DDC_SCL15
BLUE
GREEN
CRT_R_R
CRT_G_R
12
R1639
150_0402_1%
1
C1584
2
15P_0402_50V8J
D3
2
2
3
3
AZC199-02SPR7G_SOT23-3
D6
2
2
3
3
AZC199-02SPR7G_SOT23-3
1
C1575
C1576
2
10P_0402_50V8J
12
R1644
R1645
12
2.2K_0402_5%
2.2K_0402_5%
5
Q101BDMN66D0LDW-7_SOT363-6
VGA_DDC_DATA_C
For AMD DG-47520-1-10
1
1
1
1
1
2
10P_0402_50V8J
2
Q101A
DMN66D0LDW-7_SOT363-6
34
For EMI, close to JLVDS1.
C19
12
R1662
R1661
@
@
2.2K_0402_5%
AZC199-02SPR7G_SOT23-3
ESD
@
+3VS
12
1
2
4.7U_0805_10V4Z
DMIC_CLK30
DMIC_DATA30
APU_LVDS_CLK26
APU_LVDS_DAT26
TL_INVT_PWM
12
R7220_0402_5%
R1654
@
12
R1655
@
12
0_0402_5%
0_0402_5%
INVTPWM
12
R1657
10K_0402_5%
1
2
12
C1577
4.7K_0402_5%
22P_0402_50V8J
R21
0_0402_5%
@
2.2K_0402_5%
D30
@
ESD
1
2
12
R1646
61
USB20_N214
USB20_P214
2
RED
GREEN
BLUECRT_B_R
10P_0402_50V8J
+CRT_VCC+3VS
4.7K_0402_5%
12
R1642
VGA_DDC_DATA_C
VGA_DDC_CLK_C
L119
B+
FBMA-L11-201209-221LMA30T_0805
APU_TXOUT0-26
APU_TXOUT0+26
APU_TXOUT1-26
APU_TXOUT1+26
APU_TXOUT2-26
APU_TXOUT2+26
APU_TXOUT_CLK-26
APU_TXOUT_CLK+26
+LCDVDD
+3VS
@
C1590
3
223
1
1
+5VS
W=60mils
12
Camera
USB20_N2
USB20_P2
W=60mils
1
2
0.1U_0402_16V4Z
3
223
D29
@
1
AZC199-02SPR7G_SOT23-3
1
2
3
C1580
B+_L
INVTPWM
DISPOFF#
W=40mils
D4
RB491D_SOT23-3
DDC_MD2
1
2
100P_0402_50V8J
1 2
C1581
@
C122680P_0402_50V7K @
Q92
1
VIN
VOUT
GND
@
2
AP2230_SOT23-3
L115
+5VS_CRTVCC
1
1
2
21
SMD1812P075TF .75A 13.2V
C1570
+CRT_VCC
1
@
2
T69
VGA_DDC_DATA_C
VGA_DDC_CLK_C
100P_0402_50V8J
RED
GREEN
HSYNC_L
BLUE
VSYNC_L
C1582
100P_0402_50V8J
For EMI, close to JLVDS1.
JLVDS1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
37
38
39
40
41
36
G1
42
37
G2
43
38
G3
44
39
G4
45
40
G5
HONDA_LVD-A40SFYG+
CONN@
3
W=40mils
1
2
0.1U_0402_16V4Z
PAD
1
+CRT_VCC
1
C1571
@
2
0.1U_0402_16V4Z
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
SUYIN_070546FR015S263ZR
CONN@
16
G
17
G
R7190_0402_5%
12
5
12
R1677
10K_0402_5%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
2
+LAN_VDD
1
C1618
2
0.1U_0402_16V7K
1
1
C1619
2
0.1U_0402_16V7K
1
C1620
2
2
0.1U_0402_16V7K
These caps close to Pin 3,6,9,13,29,41,45
R658
12
0_0603_5%
JLAN1
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
SANTA_130452-C
+LAN_EVDD10
C1627
15P_0402_50V8J
RJ45_TX0+
RJ45_RX1+
RJ45_TX2+
RJ45_TX3+
1
2
C1633
12
12
1
1
1
1
0.1U_0402_16V7K
D38
D39
D40
D41
ESD
Title
Size Document NumberRev
Custom
Date:Sheetof
Compal Electronics, Inc.
P25-LAN RTL8111E
QBL60 LA-7552P
1
1
C1622
C1621
2
0.1U_0402_16V7K
0.1U_0402_16V7K
1
C1628
2
1U_0402_6.3V6K
R550
0_0402_5%
Y6
25MHZ_12PF_X5H025000FC1H-H
C163412P_0402_50V8J
12
9
SHLD1
10
SHLD2
AZC199-02SPR7G_SOT23-3
@
1
@
1
@
1
@
1
@
RJ45_TX0-
2
2
PD10943-T7_SOD323-2
RJ45_RX1-
2
2
PD10943-T7_SOD323-2
RJ45_TX2-
2
2
PD10943-T7_SOD323-2
RJ45_TX3-
2
2
PD10943-T7_SOD323-2
SOD323 package
1
1
1
C1623
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
XTLI
12
XTLO
3
223
D7
GND_LAN
1
1
2953Monday, April 25, 2011
1.0
A
B
C
D
E
F
G
H
12
12
12
12
12
R1538
@
1
C1492
2
@
0_0402_5%
22P_0402_50V8J
12
12
470P_0402_50V7K
12
12
L111
L112
SPK_L1
SPK_L2
SPK_R1
SPK_R2
MIC2
MIC1
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
C1502
220P_0402_50V7K
HPRH P_RHP_OUTR
HPL
1
1
C1504
470P_0402_50V7K
2
2
12
12
12
C240.22U_0603_16V7K
1
C14741U_0603_10V6K@
2
12
C14780.22U_0603_16V7K
12
C14800.22U_0603_16V7K
1
C14831U_0603_10V6K@
2
12
C14840.22U_0603_16V7K
L109
MIC-2
BLM18PG121SN1D_0603
L110
MIC-1
BLM18PG121SN1D_0603
1
C1495
2
@
@
@
@
Close to JSPK1
1
C1496
220P_0402_50V7K
2
SPK_L1
SPK_L2
SPK_R1
SPK_R2
+USB_VCCB
USB20_N114
USB20_P114
MIC_JD
HP_JD
HPR
HPL
SPK_L1 37
SPK_L2 37
SPK_R1 37
SPK_R2 37
ACES_87213-1400G
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
JAU1
1
2
1
2
12
R1546
33_0402_5%
R1547
0_0402_5%
+MIC1_VREFO_R
R1552
+5VS_PVDD
C1477
0.1U_0402_16V7K
MBK1608800YZF 0603
10U_0805_10V6K
R1590
0_0402_5%
C1499
1
2
0.1U_0402_16V7K
L108
12
HDA_SYNC_AUDIO 14
HDA_BITCLK_AUDIO 14
HDA_SDOUT_AUDIO 14
HDA_SDIN0 14
EAPD 36
1
1
C1500
@
2
2
10U_0805_10V6K
+5VS
HDA_SDOUT_AUDIO
HDA_SYNC_AUDIO
1
C1501
2
0.1U_0402_16V7K
SPKOUT_L1
SPKOUT_L2
SPKOUT_R1
SPKOUT_R2
2
C1491
1
@
10P_0402_50V8J
2
C1494
1
@
+MIC1_VREFO_R
+MIC1_VREFO_L
10U_0805_10V6K
HP_OUTLHP_L
R15320_0603_5%
R15330_0603_5%
R15350_0603_5%
R15360_0603_5%
HDA_BITCLK_AUDIO
10P_0402_50V8J
R15412.2K_0402_1%
R15422.2K_0402_1%
R1554
75_0603_1%
12
R1555
12
75_0603_1%
R1531
38
0_0805_5%
C1485
U50
40
41
45
44
32
33
10
6
5
8
47
48
20
29
30
28
27
19
34
26
37
12
1
C1475
C1476
2
10U_0805_10V6K
1
1
C1486
C1487
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
SPKOUT_L1
SPKOUT_L2
SPKOUT_R1
SPKOUT_R2
HP_OUTL
HP_OUTR
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO_R
HDA_SDOUT_AUDIO
HDA_SDIN_AUDIO
AC97_VREF
AC_JDREF
12
12
12
20K_0402_1%
12
C1498
2.2U_0603_16V6K
+5VS
11
+3VS
R1539
22
DMIC_DATA27
DMIC_CLK27
EMI request 12.24
EC_MUTE#36
33
+1.5VS
12
MIC2MIC2_R
R1540
12
DMIC_DATA
DMIC_CLK
EC_MUTE#
12
4.7K_0402_5%
R1553
@
HDA_RST_AUDIO#
@
1
0.1U_0402_16V7K
C1503
2
+3VS_DVDD
R1537
0_0603_5%
C1488
MIC1_RMIC1
1K_0402_5%
1K_0402_5%
12
12
R15430_0402_5%
12
L121
12
FBMA-L10-160808-301LMT_2P
R15450_0402_5%
12
HDA_RST_AUDIO#14
MIC_JD
+MIC1_VREFO_L
R1534
0_0603_5%
+3VS_DVDD
12
1
C1505
2
10U_0603_6.3V6M
C1490 4.7U_0603_6.3V6K
C1493 4.7U_0603_6.3V6K
DMIC_CLK_CODEC
HDA_RST_AUDIO#
R1548
12
20K_0402_1%
R1549
12
39.2K_0402_1%
+3VS_DVDD_R
12
1
C1481
2
0.1U_0402_16V7K
1
2
0.1U_0402_16V7K
MIC1_C
MIC2_C
DMIC_DATA_CODEC
PD#
SENSE_AHP_ JD
12
C1497 2.2U_0603_16V 6K
1
C1482
2
+5VS_PVDD
10U_0603_6.3V6M
1
9
DVDD
PVDD139PVDD2
DVDD_IO
23
LINE1_L
24
LINE1_R
14
LINE2_L
15
LINE2_R
21
MIC1_L
22
MIC1_R
16
MIC2_L
17
MIC2_R
2
GPIO0/DMIC_DATA
3
GPIO1/DMIC_CLK
4
PD#
11
RESET#
12
PCBEEP
13
SENSE A
18
SENSE B
36
CBP
35
CBN
31
MIC1_VREFO_L
43
PVSS2
42
PVSS1
49
DVSS2
7
DVSS1
ALC269-GR_QFN48_7X7
MIC1_VREFO_R
R15560.1U_0402_16V7K
12
R15570.1U_0402_16V7K
12
R15580.1U_0402_16V7K
12
R15590.1U_0402_16V7K
12
+VDDA
46
AVDD125AVDD2
SPK_OUT_L+
SPK_OUT_L-
SPK_OUT_R+
SPK_OUT_R-
HP_OUT_L
HP_OUT_R
SYNC
BCLK
SDATA_OUT
SDATA_IN
EAPD
SPDIFO
MONO_OUT
MIC2_VREFO
LDO_CAP
VREF
JDREF
CPVEE
AVSS1
AVSS2
Change to 0.1U for EMI
44
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
D
2011/04/252012/04/25
E
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
Custom
F
Date:Sheetof
Compal Electronics, Inc.
P26-HD CODEC ALC259
QBL60 LA-7552P
G
3053Monday, April 25, 2011
H
1.0
5
4
3
2
1
Card Reader RTS5137
(only SD/MMC/MS function)
+3VS+3VS_CR
USB20_N4
USB20_P4
+CARDPWR
10mil
R529
MS_INS#
SDD1
SDD0
MSD3
30mil
12mil
+RREF
1
2
3
4
5
6
7
8
9
10
11
12
U51
REFE
DM
DP
3V3_IN
CARD_3V3
V18
NC
SP1
SP2
SP3
SP4
SP5
GPIO0
CLK_IN
NC
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
EPAD
RTS5137-GR_QFN24_4X4
25
R1561
33_0402_5%
17
24
23
22
21
20
19
18
16
15
14
13
12
CLK_SD_48M
MS_BS
SDD2
SDD3_MSD1
SDCMD
MSD0
SDCLKMSD2SDCLK_MSD2
SDCD#
EMI
12
R4410_0402_5%
C1509
12
22P_0402_50V8J
CLK_SD_48M 13
<BOM Structure>
DD
+RREF & +VREF need 12mils
1
C1510
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
R15600_0603_5%
+VREG
2
C1511
1
C1512
1U_0402_6.3V6K
1
2
12
@
12
C1507100P_0402_50V8J
R1733
12
6.2K_0603_1%
USB20_N414
USB20_P414
+3VS_CR
30mil
SDWP_MSCLKSD WP_MSCLK_R
12
0_0402_5%
Card Reader Connector
CC
+CARDPWR
SDCLK_MSD2
30mil
@
1
R1562
100K_0402_5%
BB
12
C1514
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
C1515
1
2
1
C1513
0.1U_0402_16V4Z
2
Close to connector
SDWP_MSCLK
EMIClose to U51
@
C787
12
0.1U_0402_16V4Z
@
C788
12
0.1U_0402_16V4Z
SDCD#
SDWP_MSCLK
SDD1
SDD0
MS_BS
SDCLK_MSD2
MSD0
MS_INS#
MSD3
SDCMD
SDD3_MSD1
SDD2
+CARDPWR
JCR1
1
SD-CD
2
SD-WP
3
SD-D1
4
SD-D0
5
MS-GND
6
SD-GND
7
MS-BS
8
SD-CLK
9
MS-D1
10
MS-D0
11
SD-VCC
12
MS-D2
13
SD-GND
14
MS-INS
15
MS-D3
16
SD-CMD
17
MS-SCLK
18
MS-VCC
19
SD-D3
20
MS-GND
21
SD-D2
22
GND
23
GND
TAITW_R009-142-HM
CONN@
AA
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
D
Compal Electronics, Inc.
Title
Size Document NumberRev
Date:Sheet
P28-Mini PCIE/LED
QBL60 LA-7552P
E
3253Monday, April 25, 2011
of
1.0
A
B
C
D
E
F
G
H
SATA HDD Conn.
JHDD1
1
SATA_STX_DRX_P015
SATA_STX_DRX_N015
SATA_DTX_C_SRX_N015
11
22
SATA_DTX_C_SRX_P015
SATA_STX_DRX_P0
SATA_STX_DRX_N0
SATA_DTX_C_SRX_N0
SATA_DTX_C_SRX_P0
R15950_0805_5%
+5VS
C6560.01U_0402_16V7K
C6580.01U_0402_16V7K
C15190.01U_0402_16V7K
C15200.01U_0402_16V7K
12
10U_0603_6.3V6M
C660
12
12
12
12
1
C661
2
1U_0402_6.3V4Z
1
2
+3VS
1
2
+5VS_HDD
0.1U_0402_16V4Z
1
C662
2
1000P_0402_50V7K
SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0
SATA_DTX_SRX_N0
SATA_DTX_SRX_P0
C22
0.1U_0402_16V4Z
1
C663
2
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
V33
9
V33
10
V33
11
GND
12
GND
13
GND
14
V5
15
V5
16
V5
17
GND
18
Reserved
19
GND
20
21
22
SUYIN_127043FR022S21MZR
23
V12
GND1
24
V12
GND2
V12
SATA ODD FFC Conn.
JODD1
1
C6480.01U_0402_16V7K
SATA_STX_DRX_P115
SATA_STX_DRX_N115
SATA_DTX_C_SRX_N115
SATA_DTX_C_SRX_P115
80mils
+5VS
33
R15980_0805_5%
+3VS
12
C6490.01U_0402_16V7K
12
C15210.01U_0402_16V7K
12
C15220.01U_0402_16V7K
12
12
+5VS_ODD
@
12
R67010K_0402_5%
SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1
SATA_DTX_SRX_N1
SATA_DTX_SRX_P1
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
DP
9
+5V
10
+5V
11
MD
12
GND
13
GND
GND
GND
OCTEK_SLS-13DC1G_RV
15
14
44
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Place SW5 for TP Left switch.Place SW6 for TP Right switch.
Security Class ification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/04/ 252012/04/ 25
Compal Secret Data
Deciphered Date
Title
Size Docu ment NumberRev
Custom
Date:Sheetof
Compal Electronics, Inc.
P33-Other IO/USB (right)
QBL60 LA-7552P
3753Monday, April 25, 2011
1.0
A
+5VALW TO +5VS (5A)
+5VALW TO +5VS (5A)+1.1VALW TO +1.1VS (1.1A)
+5VALW TO +5VS (5A)+5VALW TO +5VS (5A)
10U_0805_10V4Z
11
12
+VSB
R1103 47K_0402_5%
+3VALW TO +3VS (3.3A)
+3VALW TO +3VS (3.3A)
+3VALW TO +3VS (3.3A)+3VALW TO +3VS (3.3A)
10U_0603_6.3V6M
1
2
+VSB
22
+1.5V TO +1.5VS (1.5A)
+1.5V TO +1.5VS (1.5A)
+1.5V TO +1.5VS (1.5A)+1.5V TO +1.5VS (1.5A)
33
R1112200K_0402_5%
SSM3K7002FU_SC70-3
SUSP#
+1.0VSG
+5VALW
U38
SI4800BDY-T1-GE3_SO8
8
7
10U_0805_10V4Z
C1443
1
2
SUSP
SSM3K7002FU_SC70-3
C1453
12
SUSP
R1122
47K_0402_5%
0.22U_0603_16V4Z
5
1
C1445
2
5VS_GATE
13
D
Q56
2
G
S
+3VALW+3VS
U40
SI4800BDY-T1-GE3_SO8
8
7
10U_0603_6.3V6M
5
1
C1454
2
3VS_GATE
13
D
Q59
2
G
S
R1116
100K_0402_5%
12
C1463
+VGA_CORE
12
2
G
1
2
4
1
C1450
0.1U_0603_25V7K
2
1
2
36
4
1
C1456
0.1U_0603_25V7K
2
AP2301GN-HF_SOT23-3
Q63
31
2
13
D
Q60
S
SSM3K7002FU_SC70-3
+5VS
1
2
10U_0805_10V4Z
36
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
+1.8VSG
C1446
1
2
1
C1452
2
+1.5VS+1.5V
C1461
12
13
D
S
SSM3K7002FU_SC70-3
1U_0603_10V6K
1U_0402_6.3V4Z
C1455
1
2
R1117
470_0603_5%
Q61
2
G
12
C1444
D
S
R1110
470_0603_5%
12
13
D
Q58
S
SSM3K7002FU_SC70-3
SUSP
B
R1099
470_0603_5%
12
13
Q55
SUSP
2
G
SSM3K7002FU_SC70-3
SUSP
2
G
+1.2VS
C
+1.1VALW TO +1.1VS (1.1A)
+1.1VALW TO +1.1VS (1.1A)+1.1VALW TO +1.1VS (1.1A)
R1100
1K_0402_5%
12
+VSB
R1105 47K_0402_5%
VLDT_EN#
SSM3K7002FU_SC70-3
VGA Power
VGA Power
VGA PowerVGA Power
+1.1VALW
U39
AO4430L_SO8
8
7
10U_0603_6.3V6M
Q64
2
G
1
C1448
2
1.1VS_GATE
13
D
S
6
5
12
+1.5V to +1.5VSG (1.5A)
10U_0603_6.3V6M
10U_0603_6.3V6M
VGA@
1
C1459
2
VGA@
12
+VSB
R1118 100K_0402_5%
1.5_VDDC_PWREN#
0.1U_0402_16V7K
R1120 47K_0402_5%VGA@
SSM3K7002FU_SC70-3
VGA@
C1464
12
VGA@
1
2
1
2
3
4
1
C1451
0.1U_0603_25V7K
2
+1.5V
8
7
6
5
1
C1460
VGA@
2
1.5VSG_GATE
13
D
Q74
2
G
S
+1.1VS
10U_0603_6.3V6M
1
2
U41
VGA@
AO4430L_SO8
C1447
4
1U_0402_6.3V4Z
C1449
1
2
+1.5VSG
1
2
10U_0603_6.3V6M
3
1
C1462
VGA@
0.1U_0603_25V7K
2
R1101
470_0603_5%
12
13
D
Q57
VLDT_EN#
2
G
<BOM Structure>
S
SSM3K7002FU_SC70-3
VGA@
1
1
VGA@
C1458
C1457
1U_0402_6.3V4Z
2
2
D
VLDT_EN36,46
10K_0402_5%
VGA@
R1114
470_0603_5%
12
13
D
Q73
1.5_VDDC_PWREN#
2
G
VGA@
S
SSM3K7002FU_SC70-3
R1102
VLDT_EN#
2
G
12
+5VALW
Q51
R1097
100K_0402_5%
12
13
D
S
SSM3K7002FU_SC70-3
E
+5VALW
R1098
100K_0402_5%
12
SYSON#
13
D
Q52
SYSON36,43
100K_0402_5%
SUSP28,45
SUSP#32,36
10K_0402_5%
VGA_PWR_ON25,42,45
100K_0402_5%
12
R1104
SUSP
R1109
VGA_PWR_ON#
12
R1123
2
G
12
2
G
2
G
Q68
Q53
+5VALW
S
+5VALW
R1108
100K_0402_5%
12
13
D
S
R1119
100K_0402_5%
12
13
D
SSM3K7002FU_SC70-3
S
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
R1125
470_0603_5%
VGA@
12
13
D
Q67
VGA_PWR_ON#
2
G
VGA@
S
SSM3K7002FU_SC70-3
+1.5V
44
R1135
470_0603_5%
12
13
D
Q71
S
SSM3K7002FU_SC70-3
2
G
<BOM Structure>
SYSON#
R1126
470_0603_5%
VGA@
12
13
D
Q66
2
G
S
SSM3K7002FU_SC70-3
R1136
470_0603_5%
12
13
D
Q72
2
G
S
SSM3K7002FU_SC70-3
A
1.5_VDDC_PWREN#
VGA@
<BOM Structure>
R1127
33_0603_5%
VGA@
12
13
D
Q65
VGA_PWR_ON#
2
G
VGA@
S
SSM3K7002FU_SC70-3
+0.75VS+2.5VS
R1137
470_0603_5%
12
13
D
Q70
2
G
<BOM Structure>
S
SSM3K7002FU_SC70-3
R1128
470_0603_5%
12
13
D
Q62
VLDT_EN#
2
G
<BOM Structure>
S
SSM3K7002FU_SC70-3
SUSPSUSP
B
+3VS to +3VSG (3.3A)
Change to Jump
201012062000
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
PJ14
VGA@
C
2
112
JUMP_43X118
+3VSG+3VS
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
1.5_VDDC_PWREN#
1.5_VDD_PWREN25,48
10K_0402_5%
Title
Size Document NumberRev
B
D
Date:Sheetof
Compal Electronics, Inc.
DC Interface
QBL60 LA-7552P
R1134
E
+5VALW
Q77
2
G
12
3853Monday, April 25, 2011
R1131
100K_0402_5%
12
13
D
S
SSM3K7002FU_SC70-3
1.0
A
B
C
D
(B+ 6A,240mils ,Via NO.= 12)
B+
4
3
VIN
RB751V-40TE17_SOD323- 2
12
PC109
2.2U_0603_6.3V6K
6251_ENCSON
PR130
CHG_ICOMP
CHG_VCOMP
CHG_ICM
6251VREF
6251aclim
CHG_VADJ
PR106
22K_0402_1%
12
12
CHG_VIN
12
PU101
10_1206_5%
1
VDD
2
ACSET
ACPRN
3
EN
4
CELLS
5
ICOMP
6
VCOMP
7
PHASE
ICM
8
UGATE
VREF
9
CHLIM
10
ACLIM
11
VADJ
LGATE
12
GND
ISL6251AHAZ-T QSOP 24P
1
2
36
12
PQ107B
P2
12
PC108
0.1U_0603_25V7K
12
CHG_N_002
34
5
PQ102
AO4409L_SO8
1
2
36
4
PR107
200K_0402_1%
CHG_N_003
PR116
150K_0402_1%
FSTCHG36
PC120 must close EC pin.
13
IREF36
PQ111
LTC015EUBFS8TL NPN UMT3F
PR103
150K_0402_1%
140K_0402_1%
12
PR104
8
7
5
12
PC107
@5600P_0402_25V7K
0.01U_0402_25V7K
ADP_I3 6
12
PQ101
PQ104
2
CHG_N_009
PACIN
ACOFF
AO4435L_SO8
8
7
5
4
2
CHG_N_010
13
13
PQ105
LTC015EUBFS8TL NPN UMT3F
SSM6N7002FU_US6
PR124
22K_0402_5%
12
2
VIN
11
LTA044EUBFS8TL PNP UMT3F
12
2
ACOFF36
PR109
CHG_N_001
61
PQ107A
SSM6N7002FU_US6
47K_0402_1%
22
33
P3
PR114
10K_0402_1%
2S: Float
3S: GND
PC116 6800P_0402_25V7K
12
PR121 10K_0402_1%
PC117
12
12
PC120
0.1U_0402_16V7K
6251VREF
12
Rtop
PC122
0.01U_0402_25V7K
CHGVADJ36
1
2
12
12
PR127
12
12.4K_0402_1%
20K_0402_1%
PR101
0.02_1206_1%
6251VDD
ACSETIN
12
PR117
100K_0402_1%
0_0402_5%
12
PR123 100_0402_1%
12
CHG_CHLIM
12
PR128
PR105
10K_0402_1%
12
CP= 85%*Iada;
Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K
90W for Dis:Rtop:SD00000AJ80
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K
65W for UMA:Rtop:SD034226380
Astro2010_01_15 need confirm P/N
CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A
44
when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A
PR113
DCIN
CSON
CSOP
CSIN
CSIP
BOOT
VDDP
PGND
PD101
12
PC111
@10U_0805_25V6K
PR108
191K_0402_1%
12
DCIN
24
23
22
21
20
19
12
18
17
BST_CHG
16
6251VDDP
15
DL_CHG
14
13
PL102
1.2UH_1231AS-H-1R2 N=P3_2.9A_30%
1U_0603_25V6K
12
ACPRN
CHG_CSON
PC113
0.047U_0603_16V7K
12
CHG_CSIN
PC118
0.1U_0603_25V7K
CHG_CSIP
LX_CHG
DH_CHG
0_0603_5%
12
ACSETIN
12
12
PC110
1000P_0402_50V7K
PC112
20_0603_5%
12
12
20_0603_5%
12
2.2_0603_1%
PR126
PC123
12
4.7U_0805_6.3V6K
12
CSIP
PR111
14.3K_0402_1%
PR118
PR119
PR120
20_0603_5%
PR122
PR134
0_0402_5%
12
0.1U_0603_25V7K
BST_CHGA
12
PD106
RB751V-40TE17_SOD323- 2
12
PR129
4.7_0603_5%
PR131
47K_0402_1%
MMBT3904W H NPN SOT323-3
CSIN
12
ACPRN
PC121
CSOPCHG_CSOP
12
6251VDD
12
2
B
12
PC119
@10U_0805_25V6K
6251VDD
12
C
E
31
12
PC103
4.7U_0805_25V6-K
PR132
10K_0402_1%
PQ112
PC104
10U_0805_25V6K
12
12
12
PC115
@10U_0805_25V6K
LTC015EUBFS8TL NPN UMT3F
35
5
4
PQ110
AO4468L_SO8
PR133
10K_0402_1%
12
12
PR136
20K_0402_1%
CHG_B+
12
PC105
PC106
0.1U_0402_25V6
2200P_0402_25V7K
47K_0402_1%
PQ106
PQ108
AON7408L_DFN8-5
241
10UH +-20% MSC DRI-104A-100M-E
786
12
PR125
123
CHG_SNUB
12
PC124
PACIN
PR112
12
CHG_N_008
13
PL101
12
@4.7_1206_5%
@680P_0402_50V7K
ACIN 36
B+
AO4407AL 1P SO8
1
2
36
CHG_N_005
PR110
200K_0402_1%
12
CHG_N_006
2
PC114
@2200P_0402_25V7K
PR102
0.02_1206_1%
CHG
1
2
PQ103
4
VIN
PR115
100K_0402_1%
12
12
4
3
8
7
5
CHG_N_001
13
D
ACPRN
2
G
PQ109
S
@SSM3K7002FU_SC7 0-3
12
12
PC102
PC101
10U_0805_25V6K
10U_0805_25V6K
BATT+
12
PC125
10U_0805_25V6K
CC=0.25A~3A
IREF=1.016*Icharge
IREF=0.254V~3.048V
VCHLIM need over 95mV
A
CHGVADJ=(Vcell-4)/0.10627
Vcell
4V
4.2V
CHGVADJ
0V
1.882V
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
C
Title
Size D ocument NumberRev
Date:Sheetof
Compal Electronics, Inc.
CHARGER
NCL61 LA-6321P M/B
D
3953Monday, April 25, 2011
1.0
A
B
C
D
PL1
HCB2012KF-121T50_0805
12
PL2
12
PC14
@10U_0805_25V6K
HCB2012KF-121T50_0805
12
12
PC2
100P_0402_50V8J
12
PC3
1000P_0402_50V7K
PJPDC1
4
4
3
3
11
2
2
1
1
@CVILU_CI0104P1VRB-N H_4P-T
PJP2
1
1
2
2
3
3
4
4
5
6
GND
GND
7
8
9
10
11
22
@SUYIN_200275MR009G 186ZL
EC_SMCA
5
EC_SMDA
6
TS_A
7
8
9
ADPIN
PD1
12
PC1
1000P_0402_50V7K
PR27
1
2
3
1K_0402_1%
12
VIN
12
PC13
12
PC4
@10U_0805_25V6K
100P_0402_50V8J
HCB2012KF-121T50_0805
VMB
HCB2012KF-121T50_0805
12
PC6
1000P_0402_50V7K
PL3
12
PL4
12
0.01U_0402_25V7K
PC7
PC5
0.1U_0603_16V7K
X7R type
12
12
PC15
10U_0805_25V6K
PH1 under CPU botten side :
CPU thermal protection at 92 +-3 degree C
Recovery at 80 +-3 degree C
VL
12
BATT+
OTP_N_003
PU1
1
VCC
2
GND
3
OT1
4
OT2
G718TM1U_SOT23-8
PR4
0_0402_5%
TMSNS1
RHYST1
TMSNS2
RHYST2
12
8
OTP_N_002
7
6
5
VS_ON 41
OTP_N_001
PR1
12
12
PR2 2 2.1K_0402_1%
12
PH1
100K_0402_1%_NCP15W F104F03RC
22K_0402_1%
@PJSOT24CW_SOT323-3
PD2
2
1
3
PR28
100_0402_1%
12
12
PR31
100_0402_1%
PR30
12
1K_0402_1%
33
@PJSOT24CW _SOT323-3
PR29
12
100K_0402_5%
+3VALW
BATT_TEMP 36
EC_SMB_CK1 36
EC_SMB_DA1 36
100K_0402_1%
SPOK41,44
PR13
VIN
VL
12
B+
PR16
0_0402_5%
12
VSB_N_002
12
12
12
PC8
PR10
2
G
PR12
22K_0402_1%
12
VSB_N_003
13
D
PQ2
SSM3K7002FU_SC70-3
S
100K_0402_1%
TP0610K-T1-GE3_SOT2 3-3
0.22U_0603_25V7K
VSB_N_001
PC10
13
2
PQ1
+VSBP
12
PC9
0.1U_0603_25V7K
0.1U_0402_16V7K
PD3
RLS4148_LL34-2
12
BATT+
RLS4148_LL34-2
PD4
12
PQ3
TP0610K-T1-GE3_SOT2 3-3
N1
12
12
PR21
44
51_ON#35
100K_0402_1%
12
PR22
22K_0402_1%
PC11
0.22U_0603_25V7K
VS_N_002
2
PR17
68_1206_5%
13
VS_N_001
12
12
PR18
68_1206_5%
12
PC12
0.1U_0603_25V7K
VS
+VSBP+VSB
(120mA,40mils ,Via NO.= 1)
PJ2
2
@JUMP_43X39
112
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
12
PAD-OPEN 4x4m
PJP305
12
PAD-OPEN 4x4m
PJP303
12
PAD-OPEN 4x4m
C
2011/04/252012/04/25
(5A,200mils ,Via NO.= 10)
+5VALW
(5A,200mils ,Via NO.= 10)
+5VALW
(4A,120mils ,Via NO.= 8)
+3VALW
Compal Secret Data
Deciphered Date
VL
Title
Size Document NumberRev
Custom
D
Date:Sheet
PJP302
21
PAD-OPEN 2x2m
PJP301
21
PAD-OPEN 2x2m
Compal Electronics, Inc.
+CHGRTC
3.3VALWP/5VALWP
QBL60 LA-7552P
4153Monday, April 25, 2011
E
1.0
of
A
11
B
C
D
+5VALW
12
12
22
VGA_PWR_ON25,38,45
12
PR404 200K_0402_5%
PD401
12
PC403
22U_0805_6.3VAM
EN_1.8VSP
@47K_0402_5%
1.8VSP_VIN
12
PR405
PL402
HCB1608KF-121T30_0603
ISS355_SOD323-2
PU401
4
10
PVIN
PG
9
PVIN
8
SVIN
5
EN
TP
NC
7
11
12
PC405
RT8061AZQW WDFN 10P
1.8VSP_LX
2
LX
3
LX
1.8VSP_FB
6
FB
NC
1
0.1U_0402_10V7K
PL401
1UH_VLS252012T-1R0N1R7_ 2.4A_30%
12
12
20K_0402_1%
PR403
4.7_1206_5%
12
PR401
12
PR402
10K_0402_1%
SNUB_1.8VSP
12
<Vo=1.8V> VFB=0.6V
+1.8VSGP
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V
12
PC404
12
68P_0402_50V8J
12
PC401
PC402
22U_0805_6.3VAM
22U_0805_6.3VAM
PC406
680P_0402_50V7K
+1.8VSGP
12
(4A, 160mils, Via NO.= 8)
+1.8VSG
PJP401
PAD-OPEN 3x3m
33
44
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Deciphered Date
C
2012/04/252011/04/25
Title
Size D ocument NumberRev
Date:Sheetof
Compal Electronics, Inc.
+1.8VSGP
NCL61 LA-6321P M/B
D
4253Monday, April 25, 2011
1.0
5
DD
4
3
2
1
PQ502
1.5V_B+
35
578
36
PQ501
AON7408 L_DFN8-5
241
241
12
12
PC503
PC504
10U_0805_25V6K
@4.7U_0805_25V6-K
PL501
1UH +-20% VMPI0703AR-1R0M-Z 01 11A
12
12
PR509
@4.7_1206_5%
SNUB_1.5V
12
PC511
@680P_0402_50V7K
12
PC506
2200P_0402_50V7K
PR503
SYSON36,38
CC
+5VALW
BB
+1.5V
12
PR507
100_040 2_1%
PC509
4.7U_060 3_10V6K
0_0402_ 5%
V5FILT_1.5 V+5VALW
+1.5V
12
12
PC505
12
@0.1U_04 02_10V7K
PR506
255K_04 02_1%
12
PR501
12
2.21K_04 02_1%
2.15K_04 02_1%
PR502
TON_1.5V
FB_1.5V
12
EN_1.5V
2
3
4
5
6
PU501
TON
VOUT
VDD
FB
PGOOD
14NC15
1
BOOT
EN/DEM
UGATE
PHASE
VDDP
LGATE
GND7PGND
8
RT8209M GQW_W QFN14_3P5X3P 5
CS
PR504
2.2_0402 _5%
12
UG_1.5V
13
LX_1.5V
12
TRIP_1.5V
11
10
LG_1.5V
9
BST1_1.5 VBST_1.5V
0.1U_040 2_10V7K
PR508
12
+5VALW
12
PC508
15K_040 2_1%
+5VALW
12
PC510
4.7U_080 5_10V6K
PR505
0_0402_ 5%
12
FDS6690 AS-G_SO8
PL502
HCB1608 KF-121T30_060 3
12
PC507
0.1U_0402_25V6
+1.5V
1
+
PC501
220U_B2 _2.5VM_R15M
2
B+
12
(8A,320mils ,Via NO.= 16)
AA
Security Class ification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/04/ 252012/04/ 25
3
Compal Secret Data
Deciphered Date
Title
Size Docu ment NumberRev
2
Date:Sheetof
Compal Electronics, Inc.
+1.5VP
QBL60 LA-7552P
4353Monday, April 25, 2011
1
1.0
5
4
3
2
1
DD
SPOK40,41
+1.1VALW P
+5VALW
CC
BB
12
PR707
100_040 2_1%
4.7U_060 3_6.3V6M
PC708
PR703
0_0402_ 5%
V5FILT_1.1 V+5VALW
+1.1VALW P
12
12
PC704
12
@0.1U_04 02_10V7K
255K_04 02_1%
12
12
4.64K_04 02_1%
10K_040 2_1%
PR705
PR701
PR702
TON_1.1V
FB_1.1V
12
EN_1.1V
2
3
4
5
6
PU701
TON
VOUT
VDD
FB
PGOOD
1
EN/DEM
GND7PGND
PR704
2.2_0402 _5%
12
14NC15
13
BOOT
UGATE
12
PHASE
11
CS
10
VDDP
9
LGATE
RT8209M GQW_W QFN14_3P5X3P 5
8
BST1_1.1 VBST _1.1V
UG_1.1V
LX_1.1V
TRIP_1.1V
+5VALW
LG_1.1V
12
PC707
0.1U_040 2_10V7K
PR708 14 K_0402_1%
12
+5VALW
12
PC709
4.7U_080 5_10V6K
PR710
0_0402_ 5%
12
AO4468L _SO8
PQ702
1.1V_B+
5
4
+1.1VALW P
PQ701
AON7408 L_DFN8-5
35
241
786
123
1
1
PC703
2
@10U_0805_25V6K
12
SNUB_1.1V
12
PJP701
12
PAD-OPEN 4x4m
12
PC702
2
10U_0805_25V6K
2.2UH_PC MC063T-2R2MN_ 8A_20%
12
PR709
@4.7_1206_5%
PC710
@680P_0402_50V7K
HCB1608 KF-121T30_060 3
12
PC705
PC706
2200P_0402_50V7K
PL701
PR706
@100K_0 402_5%
+1.1VALW
PL702
0.1U_0402_25V6
B+
12
1
PC711
2
@10U_0805_25V6K
+1.1VALWP
1
+
PC701
220U_6.3 VM_R15
2
12
(5A,200mils ,Via NO.=20)
AA
Security Class ification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/04/ 252012/04/ 25
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
PWR+1.1VALWP
Size Docu ment NumberRev
Custom
QBL60 LA-7552P
2
Date:Sheetof
4453Monday, April 25, 2011
1
1.0
5
+1.5V
DD
SUSP28,38
PR604
0_0402_5%
4.7U_0805_6.3V6K
SSM3K7002FU_SC70-3
0.75VS_N_002
12
PC601
PQ602
2
G
12
PC606
@0.1U_0402_10V7K
12
VREF_G2992
13
D
S
12
PR601
1K_0402_1%
12
PR602
1K_0402_1%
4
PU601
1
2
3
4
APL5336KAI-TRL_SOP8P8
VIN
GND
VREF
VOUT
VCNTL
8
NC
7
NC
6
5
NC
9
TP
12
PC603
1U_0603_10V6K
+3VALW
3
2
1
+0.75VSP
12
12
PC605
10U_0805_6.3V6M
0.1U_0402_16V7K
PC604
PR609
15K_0402_1%
12
PD601
12
ISS355_SOD323-2
PJP601
12
PAD-OPEN 3x3m
+1.5V
12
PC611
4.7U_0805_6.3V6K
0.1U_0402_16V7K
+5VALW
PC613
+1.0VSP
(2A,80mils ,Via NO.= 4)
+0.75VS
12
PC612
1U_0603_10V6K
PU602APL5930KAI-TRG_SO8
6
VCNTL
5
VIN
VOUT
9
VIN
VOUT
8
EN
7
POK
GND
12
1
PJP603
12
PAD-OPEN 3x3m
PU603
APL5508-25DC-TRL_SOT89-3
PC607
2
IN
PJP602
12
PAD-OPEN 3x3m
+3VS
12
1U_0402_6.3V6K
+2.5VSP
3
4
2
FB
12
PR610
1.82K_0402_1%
PR611
7.32K_0402_1%
+1.0VSG
12
12
(2.5A,100mils ,Via NO.= 5)
+1.0VSP
12
PC615
PC614
180P_0402_50V8J
22U_0805_6.3V6M
GND
3
OUT
1
12
PC608
4.7U_0805_6.3V6K
+2.5VS
12
PR605
@150_1206_5%
+2.5VSP
CC
BB
VGA_PWR_ON25,38,42
AA
+0.75VSP
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
2
Title
Size Document NumberRev
Date:Sheetof
Compal Electronics, Inc.
PWR 0.75VSP/1.0VSP/2.5VSP
QBL60 LA-7552P
1
4553Monday, April 25, 2011
1.0
A
11
B
C
D
PQ802
4
1.2V_B+
35
5
PQ801
AON7408L_DFN8-5
241
786
123
12
PC802
10U_0805_25V6K
2.2UH_PCMC063T-2R 2MN_8A_20%
12
12
PR809
@4.7_1206_5%
SNUB_1.2V
12
PC810
@680P_0402_50V7K
12
2200P_0402_50V7K
PL801
PL802
HCB1608KF-121T30_0603
12
PC806
PC805
0.1U_0402_25V6
+1.2VSP
1
+
PC801
2
PR803
VLDT_EN36, 38
22
+5VALW
33
12
PR807
100_0402_1%
PC808
4.7U_0603_6.3V6M
0_0402_5%
V5FILT_1.2V+5VALW
+1.2VSP
12
12
PC804
12
@0.1U_0402_10V7K
PR805
255K_0402_1%
12
+1.2VSP
PR801
12
3.24K_0402_1%
5.36K_0402_1%
PR802
TON_1.2V
FB_1.2V
12
EN_1.2V
2
3
4
5
6
+1.2VSP
PU801
TON
VOUT
VDD
FB
PGOOD
1
15
14
NC
BOOT
UGATE
EN/DEM
PHASE
VDDP
LGATE
GND7PGND
RT8209MGQW _WQFN14_3P5X3P5
8
<BOM Struct ure>
PJP801
12
PAD-OPEN 4x4m
CS
PR804
2.2_0402_5%
12
13
LX_1.2V
12
TRIP_1.2V
11
10
LG_1.2V
9
BST1_1.2VBST_1.2V
12
PC807
0.1U_0402_10V7K
PR808
15K_0402_1%
12
+5VALW
+1.2VS
+5VALW
12
PC809
4.7U_0805_10V6K
(6A,240mils ,Via NO.=12)
PR806
0_0402_5%
12
AO4406AL 1N SO8
B+
12
12
PC811
@10U_0805_25V6K
220U_6.3VM_R15
44
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Deciphered Date
C
2012/04/252011/04/25
Title
Size D ocument NumberRev
Date:Sheetof
Compal Electronics, Inc.
+1.2VSP
NCL61 LA-6321P M/B
D
4653Monday, April 25, 2011
1.0
5
PR202
10_0402 _5%
PR204
10_0402 _5%
12
12
DD
APU_VDDNB _RUN_FB_L8
APU_VDDNB _SEN8
+CPU_CORE_ NB
PC231
0.01U_04 02_16V7K
1 2
12
PC266
@330P_0 402_50V7K
PC232
@330P_0 402_50V7K
1 2
PLACE NEAR NB L -MOS
PC236
470P_04 02_50V7K
12
12
PR209
100K_04 02_1%
PR216
8.06K_0 402_1%
12
Rfset(Kohm)=(Pe riod(uS))-0.29 )*2.65
CC
+3VS
12
PR221
100K_04 02_5%
PR225
@100K_0 402_5%
VGATE36
EC_THERM#8,13,36
PLACE NEAR Phas e1 L-MOS
BB
Rfset(Kohm)=(Pe riod(uS))-0.29 )*2.65
PR238
100K_04 02_1%
12
470P_04 02_50V7K
APU_VDD_ SEN8
APU_VDD_ RUN_FB_L8
AA
COMP_NB_ 1
12
PC238
100P_04 02_50V8J
1 2
12
APU_PW RGD_L13
PR232 3.83K_040 2_1%
PC255
12
PR207
143K_04 02_1%
PC241
1000P_0 402_50V7 K
APU_SVD8
APU_SVC8
VR_ON36
8.06K_0 402_1%
68P_040 2_50V8J
COMP_CPU_ 1
PR208
2.49K_0 402_1%
12
FB_NB_1
12
PR210
324_040 2_1%
PH202_CP U
12
PH202 47 0K_0402_ 5%_TSM0B474 J4702RE
12
PR236
1000P_0 402_50V7 K
PC251
12
PR241
12
143K_04 02_1%
+CPU_CORE
12
12
PC239
1000P_0 402_50V7 K
PR223 0_ 0402_5%
PR227 0_ 0402_5%
PR229 0_ 0402_5%
PR233 27.4K_040 2_1%
12
12
PC247
PR239
FB_CPU_1
12
324_040 2_1%
PR242
2.43K_0 402_1%
PR248
10_0402 _5%
PR252
10_0402 _5%
FB_NB
COMP_NB
VW_NB
12
12
12
NTC_CPU
12
1000P_0 402_50V7 K
12
12
12
SDA
ALERT#
SCLK
PC248 33P_040 2_50V8J
PC252
12
0.01U_04 02_16V7K
PU201
1
FB2_NB
2
FB_NB
3
COMP_NB
4
VW_NB
5
PGOOD_NB
6
SVD
7
PWROK
8
SVC
9
ENABLE
10
PGOOD
11
PROC_HOT
12
NTC
VW_CPU
COMP_CPU
1 2
@330P_0 402_50V7K
1 2
ISEN2
ISEN1
VSUM-
PC264
FB_CPU
12
PC261
+5VS
48
VW
13
44
46
45
RTN_NB
VSEN_NB
ISEN2_NB47ISEN1_NB
ISL6267 HRZ-T_QFN48_6X 6
ISEN3/FB216COMP
15
14
ISEN3_FB2_CPU
12
PC256
PC257
0.22U_0402_10V6K
12
PC263
@330P_0 402_50V7K
4
12
12
PC233
PC234
0.1U_0402_10V7K
PH204
12
470K_04 02_5%_TSM0B 474J4702R E
12
PR206
27.4K_0 402_1%
845_0402_1%
12
PR217
12
ISUMN_NB
PROG2
NTC_NB
41
43
42
PROG2
NTC_NB
ISUMP_NB
ISUMN_NB
VSEN19ISEN217FB
RTN20ISEN1
18
12
0.22U_0402_10V6K
PLACE NEAR NB c hoke
VSUMG+
12
PR203
12
2.61K_0402_1%
PR201
11K_0402_1%
0.047U_0402_16V7K
PR211
6.65K_0402_1%
BOOT1_NB
40
BOOT1_NB
ISUMN21VDD
ISUMN_CPU
NTC_NB_1
PR254
0_0603_ 5%
2.2_060 3_5%
UGATE_NB
38
39
PH1_NB
UG1_NB
ISUMP
22
23
VDD_CPU
12
PC249 1U_0603_10V6K
PR244
976_040 2_1%
PH203_NB
12
PH203
10K_040 2_5%_ERTJ0E R103J
VSUMG-
12
PC235
0.1U_060 3_50V7K
12
PR212
3.83K_0 402_1%
12
PR215
BOOST1_NB 1
12
37
LG1_NB
PWM2_NB
BOOT2
UG2
PH2
LG2
VCCP
PWM3
LG1
PH1
UG1
BOOT1
PROG1
VIN
TP
24
49
PR235
VIN_CPU
12
PC250
0.22U_0603_25V7K
12
PC258
0.22U_0402_16V7K
12
0.1U_060 3_50V7K
36
35
34
33
32
31
30
29
28
27
26
25
12
0_0603_ 5%
12
PR237
1_0603_ 5%
12
PC259
PLACE NEAR Phas e1 choke
PC240
BOOT2
UGATE2
PHASE2
LGATE2
6267_VC CP
PWM3
LGATE1
PHASE1
UGATE1
BOOT1
PROG1_CP U
+5VS
PR243
0.01U_0402_16V7K
12
PR224
12
0_0402_ 5%
12
6.65K_0 402_1%
CPU_B+
12
11K_0402_1%
PR234
12
PH201_CPU
12
12
5
4
123
5
PQ206
4
123
<BOM Struct ure>
LGATE_NB
+5VS
12
12
PR219
0_0603_ 5%
PR218
0_0402_5%
BOOT2
6267_VCCP1
12
PC245
1U_0603_10V6K
VSUM+
PR240
2.61K_0 402_1%
PH201
10K_040 2_5%_ERTJ0E R103J
VSUM-
PC262
0.1U_060 3_50V7K
3
PQ205
TPCA8065-H_ PPAK56-8-5
<BOM Struct ure>
PHASE_NB
TPCA8059-H_PPAK56-8-5
PC237
680P_04 02_50V7K
UGATE2
PHASE2
PR226
2.2_060 3_5%
BOOT2_1
12
LGATE2
UGATE1
PHASE1
PR247
2.2_060 3_5%
BOOT1
LGATE1
12
PR205
4.7_120 6_5%
SNUB_NB
VSUMG+
12
VSUMG-
PR255
0_0603_ 5%
PC244
0.1U_060 3_50V7K
0.1U_060 3_50V7K
BOOT1_1
12
12
CPU_B+
12
12
PC226
PC228
PC225
10U_0805_25V6K
10U_0805_25V6K
0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%
PR213
3.65K_0 805_1%
12
PR214
1_0402_ 1%
12
5
PQ203
4
TPCA8065-H_ PPAK56-8-5
123
5
12
4
123
<BOM Struct ure>
4
PC260
12
4
12
PC229
0.01U_0402_25V7K
2200P_0402_50V7K
1
2
VSUMG+_1
PQ204
TPCA8059-H_PPAK56-8-5
5
PQ201
TPCA8065-H_ PPAK56-8-5
123
<BOM Struct ure>
5
PQ202
123
<BOM Struct ure>
12
PL203
12
PR228
4.7_120 6_5%
SNUB_CPU2
PC246
12
680P_04 02_50V7K
TPCA8059-H_PPAK56-8-5
2
PL204
HCB2012K F-121T50_080 5
12
PL205
HCB2012K F-121T50_080 5
12
4
3
VSUMG-_1
CPU_B+
12
12
PC224
PC223
10U_0805_25V6K
10U_0805_25V6K
0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%
PR220
12
PR230
3.65K_0 805_1%
PR231
1_0402_ 1%
CPU_B+
12
PC221
10U_0805_25V6K
10U_0805_25V6K
ISEN1
VSUM+
1
2
VSUM+_2
12
VSUM-_2VSUM-
12
12
12
PC254
PC253
0.01U_0402_25V7K
0.36UH_V MPI1004AR-R3 6M-Z03_30A_ 20%
PR245
12
10K_040 2_1%
PR250
12
3.65K_0 805_1%
PR251
1_0402_ 1%
12
ISEN2
10K_040 2_1%
VSUM+
If the layout o f each phase t o CPU
s symmetric, th e two res. can be
i
removed.
They are used f or phase curre nt
balance adjustm ent.
PC222
12
PR249
4.7_120 6_5%
SNUB_CPU1
PC265
12
680P_04 02_50V7K
+CPU_CORE_NB
12
PC243
PC242
0.01U_0402_25V7K
PL202
4
3
12
2200P_0402_50V7K
1
2
VSUM+_1
VSUM-_1VSUM-
1
+
PC230
2
12
2200P_0402_50V7K
PR222
12
10K_040 2_1%
PL201
@68U_25V_M
4
3
1
+
PC227
68U_25V_M
2
ISEN1
PR246
12
10K_040 2_1%
1
B+
+CPU_CORE
ISEN2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
2
Title
Size Document Numb erRev
Date:Sheetof
Compal Electronics, Inc.
PWR_+CPU_CORE/+CPU_CORE_NB
QBL60 LA-7552P
Monday, April 25, 2011
1
4753
1.0
A
PL902
HCB2012 KF-121T50_080 5
12
12
12
73.2K_06 03_1%
12
PC917
B+
12
PC923
@10U_0805_25V6K
PU901
1
RF_VGA
PR911
470K_04 02_1%
12
PGOOD
2
TRIP
3
EN
4
VFB
5
RF
RT8237C ZQW(2) W DFN
PR901
TRIP_VGADH_V GA
PR907
EN_VGA
FB_VGA
@0.1U_0402_16V7K
11
+3VS
PR905
10K_040 2_1%
VGA_PW RGD13 ,25
PR908
1.5_VDD_ PWREN25,38
22
33
Rtrip = 73.2K, OCP = 34.42A
12
0_0402_ 5%
Rrf = 470K, FSW = 290KHz
PR902
Whistler ProGPU VID1 GPU VID0
6.98K_04 02_1%
10U_0805_25V6K
VBST
DRVH
DRVL
2.94K_0402_1%
VGA_B+
12
PC912
SW
V5IN
TP
12
12
10
9
8
7
6
11
12
PC911
10U_0805_25V6K
BST_VGA
LX_VGA
DL_VGA
B
PC913
@10U_0805_25V6K
V5IN_VGA
+VGA_CO RE1
0.1U_0402_25V6
PC914
12
12
PR906
12
2.2_0603 _5%
PR919 0_ 0603_5%
PR909
12
0_0603_ 5%
PC919
2.2U_060 3_6.3V6K
12
PR904
@10K_0402_1%
D
PQ904
S
@SSM3K7002FU_SC70-3
12
BST1_VG A
12
12
FB1_VGA
13
2200P_0402_50V7K
PC915
@10U_0805_25V6K
PC916
12
0.1U_060 3_25V7K
+5VALW
GPU_VID1_ 1
2
G
12
12
PC925
PC924
@10U_0805_25V6K
TPCA805 9-H_PPAK56-8-5
PR915
@5.1K_04 02_1%
12
@10K_04 02_5%
PC921
@0.1U_0402_16V7K
12
PR916
PQ901
PQ902
+3VSG
12
12
5
4
5
4
PR913
@10K_04 02_1%
GPU_VID119
SSM3K70 02FU_SC70-3
123
123
PR903
PQ905
C
5
2
G
5
GPU_VID0_ 1
12
PQ906
@TPCA80 65-H_PPAK56-8-5
123
0.36UH_P DME104T-R36MS 0R825_37A_20 %
TPCA8059-H_PPAK56-8-5
123
PR917
5.1K_040 2_1%
12
PC922
0.1U_0402_16V7K
PL901
12
12
PR910
@4.7_120 6_5%
0.1U_040 2_10V7K
SNUB_VGA
12
PC920
@680P_0 402_50V7K
+3VSG
PR914
10K_0402_1%
PC918
12
PR918
@10K_04 02_5%
12
1
+
12
GPU_VID019
2
PC901
330U_D2_2V_Y
100_040 2_1%
4
TPCA8065-H_PPAK56-8-5
PQ903
4
12
6.19K_0402_1%
FB0_VGA
13
D
S
+VGA_CO RE
PR912
12
D
GCORE_S EN 2 1
XL
X
H
H0.9V
L
1.0V
HH
44
Security Class ification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
2011/04/ 252012/04/ 25
Compal Secret Data
Deciphered Date
C
Title
Size Docu ment NumberRev
Date:Sheetof
Compal Electronics, Inc.
VGA_CORE
QBL60 LA-7552P
D
4853Monday, April 25, 2011
1.0
5
4
3
2
Version change list (P.I.R. List)Power sectionPage 1 of 1
1
ItemReason for changePG#Modify List
DatePhase
1
2
DD
3
4
5
6
7
CC
BB
AA
Security Classification
Issued Date
THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEE T NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR D ISCLOSED TO ANY THIRD PA RTY WITHOUT PRIOR WRITTEN CONSENT OF COMPA L ELECTRONICS, INC.
3
Compal Secret Data
2011/04/252012/04/25
Deciphered Date
2
Compal Electronics, Inc.
Title
Changed-List History
Size Document NumberRev
Date:Sheet
QBL60 LA-7552P
of
4953Monday, April 25, 2011
1
1.0
5
4
3
2
1
POWER SEQUENCE
ACIN/BATT-IN
+5VALW
DD
+3VALW
+1.1VALW
EC_RSMRST#
RTC_CLK
PBTN_OUT#
SLP_S5#
SLP_S3#
SYSON
+1.5V
SUSP#
CC
+5VS
+3VS
+1.8VS
+1.05VS/+0.75VS
VLDT_EN
+1.1VS
VGA_ON
1.5_VDDC_PWREN
+VGA_CORE/+1.5VSG
BB
+1.8VSG/+1.0VSG
VGA_PWRGD
VR_ON
+APU_CORE/+APU_CORE_NB
T2>10ms
T2A<50ms
T13>8ns
T3>16ms
Delay SLP_S5#
Delay SLP_S3#
Delay SUSP# 10ms
Delay SUSP# 10ms
AND from VGA_ON & PX_EN
T<20ms
T13A>80ns
FCH_PWRGD
+3VSG to +1.0VSG power up
VGA_ON Delay 20ms
VGATE
FCH_PWRGD
APU_PWRGD
AA
A_RST#
PLT_RST#
APU_RST#
5
T7A<50ms
98ms<T7<150ms
101ms<T9A<113ms
101ms<T9<113ms
T8A<100ns
1ms<T8C<2.3ms
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE IN FORMATION IT CONTAINS
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
2011/04/252012/04/25
Deciphered Date
2
T7B<1ms
Title
Power Sequence
Size Document NumberRev
QBL60 LA-7552P
Monday, April 25, 2011
Date:Sheet
1
50 53
of
1.0
5
4
3
2
Version change list (P.I.R. List)Page 1 of 3 for HW
Reason for changeRev.PG#Modify ListDatePhaseFixed IssueItem
1
1
DD
2
3
4
5
6
7
8
9
CC
10
11
12
For PBL60 MEMO
For switch quality of ME.Change SW5,SW6 to 100g switch for ME.0.11PG#3703/15ER
For LED brightness.
For DFB.0.12PG#11 JDIMM1 footprint change to FOX_AS0A626-J8SG-7H_204P-T03/17ER
For USB3.0 & AI charge.0.12PG#34 USBP0 connect to JUSB1 and USBP10 connect to JUSB2.03/17ER
For Back light function.0.12PG#36 U31.15 connect to ENBKL from APU.03/17ER
For HDMI HPD issue.0.12PG#10 Q34 change to 2N7002(ESD)
For DP0_HPD & DP1_HPD from AMD recommend.0.12PG#10 Swap Q13.1 & Q13.3, R618 unmount.
For Travis Vendor requestDel DP0_TXN0_C & DP0_TXP0_C0.12PG#2603/22ER
For LED10.12LED1 connect to +3VALW03/22ERPG#32
0.11
0.11PG#3203/15ER
13
14
15
16
17
BB
18
19
20
21
22
23
24
25
AA
26
27
5
For Sourcer recommend
0.2For Sourcer recommend
For Sourcer recommendSB000006A00 change to SB000006A100.2
For Thermal0.2Del H403/24ERPG#37
For +5VS rising time0.2PG#38 R1103 change to 47K03/24ER
For Crystal EA0.2C1634 change to 12P & C1633 change to 15P03/24ER
For Crystal EA
For Crystal EA
For EMI request0.2PG#36 R1033 change to SM01000DI00
For EMI request0.2PG#28 L38,L39,L40,L41 change to SM070001S0003/24ER
For EMI request03/24D1,D2,D3,D6 change to installPG#270.2ER
For Crystal EA0.2PG#13 C1205,C1206 change to 10P03/24ER
For AI charge0.2PG#36
For AMD spec0.2PG#27 R1642 & R1646 change to 4.6K ohm03/29ER
4
0.2
0.2
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Add U2 & U56For AI charge function
PG#340.11
PG#32
Change R1584 to 200 ohm.
Change R1586,R1588,R1591,R1592,R1593 to 100 ohm
Add R469 to +1.5VS.
Swap Q16.1 & Q16.3, R627 unmount.
R1021,R1022 change to install.0.2PG#36For EC SMBUS03/24ER
SE100105Z80 change to SE000000K8003/24ER0.2
SE103225Z80 change to SE000008880
PG#29
C1200 & C1201 change to 12P
PG#13
C353 change to 15P & C354 change to 12P
PG#19
R1055 change to 33 ohm
U2 reserve CEN# to EC03/25ER
PG#34
Issued Date
2011/04/252012/04/25
3
Compal Secret Data
Deciphered Date
2
03/15ERPG#260.11For AMD reuqestTranslator change to ANX3110
03/15
03/15Change LED1 to Green color.
03/19
03/19ERER
03/24ER
03/24ER
03/24ER
03/24ER
03/24ER
Title
Size Document NumberRev
Custom
Date:Sheetof
ER
ER
Compal Electronics, Inc.
HW-PIR1
QBL60 LA-7552P
1
5153Monday, April 25, 2011
1.0
5
4
3
2
Version change list (P.I.R. List)Page 2 of 3 for HW
Reason for changeRev.PG#Modify ListDatePhaseFixed IssueItem
1
1
DD
2
3
4
5
6
7
8
9
CC
10
11
12
13
14
15
16
17
BB
18
19
20
21
22
23
24
25
AA
26
For share ROM reuqest0.2PG#15
For EMI reuqest0.2PG#34 D5 change to SC300001Y0003/29ER
For +3VS leakage from CRT 0.21PG#27 Add Q101,R1644,R1645
For Crystal EA0.21PG#13 Y4 change to SJ100007N00 (32.768KHZ 7PF)03/31ER
For HDMI EA0.21PG#34 D32.5 change to connect +5VALW from +5VS03/31ER
For EMC team requirement (ISN).0.22PG#29 Change C1636 from 1000pF to 120pF.04/19PR
For Thermal team recommend.0.22PG#19 Add R78, R79 and reserve R80, R82.04/19PR
Reserve PX_EN signal.0.22PG#36 Reserve PX_EN in EC pin 74.04/19PR
Follow ME BOM.0.22PG#11
Don't use for MP.0.22PG#35 Unstuff SW4.04/19PR
Update Board ID for PR (R1.0).0.22PG#37 Change R1026 to 46.4K ohm.04/19PR
DFM team requirement.0.22PG#35 Delete SW3.04/19PR
DMC team requirement.0.23PG#29 Reserve D7 between GND_LAN and GND.04/21PR
0.23PG#29 Unstuff C1193.Don't use for MP.04/21PR
0.23Key Part list is updated from the customer.PG#4
Update TS1 as ER build Memo.0.23PG#29
For VGA Sequence.0.23PG#38 Change R1127 from 470 ohm to 33 ohm.04/21PR
DFB team requirement.0.23PG#34 Del R664~R667 and R672~R675.04/21PR
ESD team requirement.0.23PG#34
DMC team requirement.0.23PG#29
DMC team requirement.0.23
DMC team requirement.1.0PG#13 Change R657 from 22 ohm to 33 ohm.04/25PR
U28,R626,R934,R935,R35 change to Un-install
PG#16
R921 change un-install & U910 change to install
Del R4,R31
Swap the location of JDIMM1 & JDIMM2.04/19PR
PG#12
Update U25 (M3-FCH) P/N to SA000043ID0
(S IC 218-0755042 A13 02G050005815 T88!)
Update U25 (M2-FCH) P/N to SA000042C80
(S IC 218-0755046 A13 02G050005814 T88!)
Change TS1 from SP050005L00 to SP050006F00.
(S X'FORM_ IH-160 LAN)
Add R1644, R1645, Q101 and Del R4, R31.0.23PG#27Prevent the leakage from CRT monitor.04/21PR
Change D5 from SC300001D00 (YSCLAMP0524P SLP2510P8)
to SC300001Y00 (AZ1045-04F DFN2510P10E ESD).
Change the ground of D21, D22, D31, D34 and H8.
from GND_LAN to LAN.
PG#19 Add R83, R84.04/22PR
03/29ERPG#300.2For EMI reuqestR1555,R1556,R1557,R1558 change to 0.1uf
03/29ER
03/31ER
04/21PR
04/21PRKey Part list is updated from the customer.0.23PG#13
04/21PR
04/21PR
04/22PR
04/25PRPG#13 Stuff R1561 to 33 ohm and C1509 to 22pF.DMC team requirement.1.0
27
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
Custom
2
Date:Sheetof
Compal Electronics, Inc.
HW-PIR2
QBL60 LA-7552P
1
5253Monday, April 25, 2011
1.0
5
4
3
2
Version change list (P.I.R. List)Page 3 of 3 for HW
Reason for changeRev.PG#Modify ListDatePhaseFixed IssueItem
1
1
DD
2
04/25PR1.0Reduce the component count for MP.Change below the footprints from 0 ohm to R short.
3
4
5
6
7
8
9
CC
10
11
12
13
14
15
16
17
BB
18
19
20
21
22
23
24
25
AA
26
27
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/04/252012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document NumberRev
Custom
2
Date:Sheetof
Compal Electronics, Inc.
HW-PIR3
QBL60 LA-7552P
1
5353Monday, April 25, 2011
1.0
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