Asus K43T,K43TA,K43TK,K43TY Schematic

A

Dr-Bios.com

1 1

B

C

D

E

Compal Confidential

2 2

QBL50 Schematics Document

AMD Sabine

APU Llano / Hudson M2_M

UMA only / PX

3 3

Muxless with BACO

3 / Vancouver Whistler

2011-04-25

Rev:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/03/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal E

Cover Page

QB

L50 LA-7551P

lectronics, Inc.

153Wednesday, April 27, 2011

E

1.0

A

Dr-Bios.com

B

C

D

E

Com

Model Nam

1 1

pal Confidential

e : QBL50

VRAM 128M16 x 4/8

1G/2G

page 23, 24

Sabine

DDR3

hermal Sensor

T

AD

M1032

page 19

Vancuver Whistler

ATI

uF

CBGA-962

Page 18~22

8

GF

X x 4

APU HDMI (UMA / Muxless)

D

P x1 (DP0 T XP/N0)

Gen2GFX x

AMD FS1 APU

Llano

uP

GA-722 Package

Memory BUS(

D

ual Channel

1

.5V DDRIII 800~1333MHz

DDR3)

204pin DDRIII-SO-DIMM X

BANK 0, 1, 2, 3

Page 11,12

2

HDMI Conn.

page 28

LV

2 2

LVDS Conn.

DS

Reserve eDP

page 27

RT Conn.

C

page 27

Travis LVDS Translator

page 26

F

CH CRT (VGA DAC)

GPP0GPP1

P_

GPP x 2

GEN1

DP (DP1 TXP/ N 0~4)

Hudson-M2/M3

uFCBGA-656

MINI Card 1 WLAN

3 3

page 32

LAN(GbE) RTL8111E-VL

RJ

45

page 29

Page 6~10

x 4

FCH

Page 13~17

UMI

LPC BUS

USB

B

US

3V 48MHz

3.

HD Au

dio

S-ATA

S

ATA HDD1

Conn.

page 33

2

page 34

Port 0 Port 5

3V 24.576MHz/48Mhz

3.

Gen

2

2/

USB USB3.0

page 34

Port 10

USB (LS-7322P)

port 0

2

page 30

CMOS Ca

ODD C

onn.

page 33

page 27

mera

Port2 Port 3

port 1

(with BT)

HDA Co ALC269

Mi

ni Card

page 32

dec

page 30

C

ard Reader

RTS5137

page 31

Port 4

ENE KB930

page 36

ouch Pad Int.KBD

T

LED

page 37

RTC CKT.

4 4

page 25

DC/DC Interface CKT

Po

wer Circuit

.

page 39

page 40~48

A

ernal board

Ext

L

S-7321P

Power/B

S-7322P

L Audio BD

page 35

page 30

BIOS ROM

EC BIOS

(2M)

B

page 35

page 38

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/03/04 2011/12/31

page 38

pal Secret Data

Com

Deciphered Date

D

lectronics, Inc.

Compal E

Title

Size Document Number Rev

B

Date: Sheet of

Compal E

B

lock Diagrams

QB

L50 LA-7551P

lectronics, Inc.

253Wednesday, April 27, 2011

E

1.0

5

Dr-Bios.com

4

3

2

1

CL

OCK DISTRIBUTION

MEM_MB_CLK1_P/N

MEM_MB_CLK7_P/N

AM

S1 SOCKET

_AUX

DP0

A_ SODIMM

MEM_MA_CLK1_P/N

MEM_MA_CL

1066~1600MHz

K7_P/N

D

U_DISP_CLKP/N

AP

100M

Hz

U_CLKP/N

AP

100M

Hz

AM

I VGA

AT

histler

W

AMD

FCH Huds

on-M2/M3

Internal CLK GEN

32.768KHz 25MHz

D

C

LK_PEG_VGAP/N

100M

Hz

PP_CLK

G

100M

Hz

D D

C C

B_ SODIMM

1066~1600MHz

CPU F

VDS Transtator

L

DISPLAY DISTRIBUTION

LVDS PATH

:

APU HDMI PATH

:

U_TXOUT[0:2]+/-

AP APU_TXOUT_CLK+/APU_TZOUT[0:2]+/APU_TZOUT_CLK+/APU_LVDS_CLK/DATA

LVDS_OUT

R

TD2132

_IN

DP

TX

OUT[0:2]+/TXCLK+/TZOUT[0:2]+/TZCLK+/I2CC_SCL/DA

VDS CONN

L

R

C

0_TXP/N[0:1]

DP

0_AUXP/N

DP

B B

W

LAN

PP1

G

Gb

Mini PCI Socket

E LAN

25MHz

GPP0

AP

DP

FC

DP0

U

PC

IE_GFX[0:7]

1

PCIE_GFX[12:15]

C

PC

IE_GFX[0:7]

VGA

H

LS

R

A A

HDM

I CONNCRT CONN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/04 2011/12/31

3

C

ompal Secret Data

Deciphered Date

Title

CLOCK / DI

Size Document Number Rev

Custom

QBL50 LA-7551P

Date: Sheet of

2

Date: Sheet of

SPLAY DISTRIBUTION

1

1.0

353Wednesday, April 27, 2011

1.0

A

Dr-Bios.com

oltage Rails

V

Power Plane Description

VIN

B+

PU_CORE

+C

1 1

+C

PU_CORE_NB ON OFF OFF

+VGA_CORE OFFOFFON0.95-1.2V switched power rail

+0.75VS ONON OFF0.75V switc hed power rail f or DDR terminat or

+1.0VSG ON OFF OFF1.0V switched power rail for VGA

1ALW 1.1V switched power rail for FCH ON ON*ON

+1.

+1.1VS

+1.2VS ON OFF OFF

+1.5V ON

5VS

+1.

8VSG OFFON OFF1.8V switched power rail

+1.

+2.5VS

+3VALW

+LAN_IO ONONON

+3VS

+5VALW

+5VS

2 2

+VSB ON ON*

+R

TCVCC

ote : ON* means that t his power plane is ON only with A C power available, otherwise it is OFF .

N

Adapter power supply ( 19V)

AC or battery power rail for power circuit.

Core voltage for CPU

Vo

ltage for On-die VGA of A PU

1.2V switched power rail for APU

1

.5V power rail for CPU VDDIO and DDR

1.5V switched power rail

2.5V for CP U_VDDA

3.3V always on power rail

3.3V power rail for LAN

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

RTC power

B

S3 S5

S1

N/A N/A N/A

ON OFF

ON OFF OFF1.1V switched power rail for FCH

ON OFF

ON

N/AN/AN/A

OFF

ON

OFF

ON ON*

OFF

ON

ON*

OFF

OFFON

ONON

STATE

SIGNAL

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

BTO Opt

ion Table

BTO ItemBOM Structure

V

GA@ Use VGA (Mux)

M2@ Use Hudson-M2

M3@ Use Hudson-M3

RAM ID TableX76@

V

C

SLP_S3#

SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH

HIGHHIGHHIGH

HIGH

LOW

HIGH

LOW

ON

OFF

M3@U25

M3@

F

Part Number = SA000043ID0

BOM

CH M3

ON

OFF

5

U2

Config

D

E

ON

LOW

OFF

USB30@ USB30 on M/B

USB20@ USB20 on M/B

x =

1 is read cmd, x= 0 is writee cmd.

External PCI Devices

D

evice

3 3

E

C SM Bus1 address EC SM Bus2 address

D

evice Address HEX

art Battery

Sm

FCH

Bus 0 address

SM

4 4

D

evice Address Device Address

DDR DIMM1

DDR DIMM2

ID

SEL#

0001 011X b

1101 000X b

1101 001X b

A

RE

Q#/GNT#

D

evice Address HEX

DI ADM1032 (VGA)

A

16H

(

APU)

TD2132S (TL)

R

I

nterrupts

FCH

Bus 1 address

SM

HE

X

D0

D2

1001 101X b

9A

H

HE

X

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Title

Size Document Number Rev

B

Date: Sheet of

D

Date: Sheet of

Compal E

Notes List

QB

L50 LA-7551P

lectronics, Inc.

453Friday, April 29, 2011

E

1.0

5

Dr-Bios.com

BAT

TERY

12.6V

AC ADAPTO

D D

19V 90W

BATT+

R

VI

PU101 CHARGER

N

B+

C C

+INVPWR_B+

LCD panel

15.6"

B+ 300mA

+3.

3 350mA

FA

B B

N Control

APL5607

+

5VS 500mA

U54/U55 AP2301MPG

+USB_VCCA +USB_VCCB

P

U201

ISL6267HRZ-T

P

U501

RT8209MGQW

PU801 RT8209MGQW

P

U901

RT8237CZQW

U701

P RT8209MGQW

U301

P RT8205LZQW

+3VS

+5VS

USB X3

+5

V

Dual+1

2.5A

SA

TA HDD*2 ODD*1

V 3A

+5

+3.3V

A A

A

udio Codec

ALC269-GR

+5V 45mA

+3.3VS 25mA

4

+CPU_CORE

+CPU_CORE_NB

+1.5V

+1.2VS

+VGA_CORE

+1.1VALW

+3VALW

+5VALW

EC ENE KB930

+3.3VALW 30mA +3.3VS 3mA

+3VS

+3VALW

LA

N

RTL8111E

+3.3VALW 201mA

U3

3

SI4800

3

+1.5VS

M

ini Card

+1.5VS 500mA +3.3VS 1A +3.3VALW 330mA

+2.5VS

PU603 APL5508-25DC

U4

0

SI4800

P

U602

APL5930KAI

U4

1

AO4430L

P

U401

SY8033BDBC

2

U601

P APL5336KAI

+1.0VSG

+1.5VSG

+1.8VSG

J14

P

U3

9

AO4430L

RTC Bettary

+0.75VS

+3VSG

+1.1VS

+CPU_CORE

+CPU_CORE_NB

+2.5VS

+1.5V

+1.2VS

+0.75VS

+VGA_CORE

+VDDCI

+1.0VSG

+1.5VSG

+1.8VSG

+3VSG

+1.1VS

+1.1VALW

+3VS

+3VALW

D APU FS1

AM

0.

+2.5VS

+1.5V

+1.2VS

+1

+0.75VS

0.85~1.1V

0.

+1.

+1.5VSG

+1.8VSG

+3VSG

+1.1VS

+1.

+3VS

+3VALW

GND

VDD CORE 54A

7~1.475V

VDDNB 27.5A

VDDA 500mA

VDDIO 4.6A

VDDR 6.7A

R

AM DDRIII SODIMM X2

VDD_

.5V

V

GA ATI

Whistler/Seymour/Granville

9~1.0V

0VSG

CH AMD Hudson M2/M3

F

1VALW

MEM 4A

TT_MEM 0.5A

V

VDDC 47A

VDDCI 4.6A

DPLL_VDDC: 125 mA SPV10: 120 mA PCIE_VDDC: 2000 mA D

P[A:E]_VDD10: 680 mA

3400 mA

VDDR1:

PLL_PVDD:

75 mA TSVDD: 20 mA AVDD: 70 mA VDD1DI: 100 mA VDD2DI: 50 mA A2VDDQ: 1.5 mA VDD_CT: 110 mA VDDR4: 170 mA PCIE_PVDD: 40 mA MPV18: 150 mA SPV18: 75 mA PCIE_VDDR: 400 mA DP[A:F]_VDD18: 920 mA DP[A:F]_PVDD: 120 mA

130 mA

A2VDD: VDDR3: 60 mA

VDDPL_11_DAC: 7 mA VDDAN_11_ML: 226 mA VDDCR_11: 1007 mA VDDAN_11_CLK: 340 mA VDDAN_11_PCIE: 1088 mA VDDAN_11_SATA: 1337 mA

VDDAN_11_USB_S: 140 mA VDDCR_11_USB_S: 197 mA VDDAN_11_SSUSB_S: 282 mA VDDCR_11_SSUSB_S: 424 mA VDDCR_11_S: 187 mA VDDPL_11_SYS: 70 mA

V

DDIO_33_PCIGP: 131 mA VDDPL_33_SYS: VDDPL_33_DAC: 20 mA VDDPL_33_ML: 20 mA VDDAN_33_DAC: 200 mA VDDPL_33_PCIE: 43 mA VDDPL_33_SATA: 93 mA VDDIO_AZ_S: 26 mA

VDDPL_33_SSUSB_S: 20 mA VDDPL_33_USB_S: 17 mA VDDAN_33_USB_S: 658 mA VDDIO_33_S: 59 mA VDDXL_33_S: 5 mA VDDAN_33_HWM_S: 12 mA

VDDIO_33_GBE_S VDDCR_11_GBE_S VDDIO_GBE_S

VDDBT_RTC_GRTC BAT

47 mA

1

RAM 1GB/2GB

V 64M / 128Mx16 * 4 / 8

5VSG 2.4 A

+1.

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/08/04 2011/12/31

Compal Secret Dat a

Deciphered Dat e

2

Title

POWER DELIVE RY CHART

Size Document Number Rev

Custom

QBL50 LA-7551P

Date: Sheet

1

553Wednesday, April 27, 2011

of

1.0

A

Dr-Bios.com

CIE_GTX_C_FRX_P[0..7]18

P

CIE_GTX_C_FRX_N[0..7]18

P

JC

PU1A

PCI EXPRESS

P

CIE_GTX_C_FRX_P0

CIE_GTX_C_FRX_N0

P

1 1

2 2

P

CIE_DTX_C_FRX_P029

CIE_DTX_C_FRX_N029

3 3

4 4

P

CIE_DTX_C_FRX_P132

CIE_DTX_C_FRX_N132

P

UMI_MTX_C_FRX_P013

UMI_MTX_C_FRX_N013

UMI_MTX_C_FRX_P113

UMI_MTX_C_FRX_N113

UMI_MTX_C_FRX_P213

UMI_MTX_C_FRX_N213

UMI_MTX_C_FRX_P313

UMI_MTX_C_FRX_N313

+1.2VS

CIE_GTX_C_FRX_P1

P

CIE_GTX_C_FRX_N1

P

CIE_GTX_C_FRX_P2

CIE_GTX_C_FRX_N2

P

CIE_GTX_C_FRX_P3

P

CIE_GTX_C_FRX_N3

P

CIE_GTX_C_FRX_P4

P

CIE_GTX_C_FRX_N4

P

CIE_GTX_C_FRX_P5

P

CIE_GTX_C_FRX_N5

CIE_GTX_C_FRX_P6

P

CIE_GTX_C_FRX_N6

P

CIE_GTX_C_FRX_P7

P

CIE_GTX_C_FRX_N7

1 2

R539 196_0402_1%R539 196_0402_1%

P_ZVDDP

AA8

AA9

Y7

Y8

W5

W6

W8

W9

V7

V8

U5

U6

U8

U9

T7

T8

R5

R6

R8

R9

P7

P8

N5

N6

N8

N9

M7

M8

L5

L6

L8

L9

AC5

AC6

AC8

AC9

AB7

AB8

AA5

AA6

AF8

AF7

AE6

AE5

AE9

AE8

AD8

AD7

K5

AMD_TOPEDO_FS-1

GFX_RXP0

P_

GFX_RXN0

P_

GFX_RXP1

P_

GFX_RXN1

P_

GFX_RXP2

GFX_RXN2

P_

P_GFX_RXP3

GFX_RXN3

P_

GFX_RXP4

GFX_RXN4

P_

GFX_RXP5

P_

GFX_RXN5

P_GFX_RXP6

GFX_RXN6

P_

GFX_RXP7

P_

GFX_RXN7

P_

GFX_RXP8

P_

GFX_RXN8

P_

GFX_RXP9

P_

GFX_RXN9

GFX_RXP10

P_

P_GFX_RXN10

GFX_RXP11

P_

GFX_RXN11

GFX_RXP12

P_

GFX_RXN12

P_

GFX_RXP13

P_

GFX_RXN13

GFX_RXP14

P_

GFX_RXN14

P_

GFX_RXP15

P_

GFX_RXN15

P_

GPP_RXP0

P_

GPP_RXN0

P_GPP_RXP1

P_

GPP_RXN1

GPP_RXP2

P_

GPP_RXN2

P_

P_GPP_RXP3

P_GPP_RXN3

P_UMI_RXP0

P_UMI_RXN0

P_UMI_RXP1

P_UMI_RXN1

P_UMI_RXP2

P_UMI_RXN2

P_UMI_RXP3

P_UMI_RXN3

P_ZVDDP

PCI EXPRESS

GPPUMI-LINK GRAPHICS

B

CONN@

GFX_TXP0

P_

GFX_TXN0

P_

GFX_TXP1

P_

GFX_TXN1

P_

GFX_TXP2

GFX_TXN2

P_

P_GFX_TXP3

GFX_TXN3

P_

GFX_TXP4

GFX_TXN4

P_

GFX_TXP5

P_

GFX_TXN5

P_GFX_TXP6

GFX_TXN6

P_

GFX_TXP7

P_

GFX_TXN7

P_

GFX_TXP8

P_

GFX_TXN8

P_

GFX_TXP9

P_

GFX_TXN9

GFX_TXP10

P_

P_GFX_TXN10

GFX_TXP11

P_

GFX_TXN11

GFX_TXP12

P_

GFX_TXN12

P_

GFX_TXP13

P_

GFX_TXN13

GFX_TXP14

P_

GFX_TXN14

P_

GFX_TXP15

P_

GFX_TXN15

P_

GPP_TXP0

P_

GPP_TXN0

P_GPP_TXP1

P_

GPP_TXN1

GPP_TXP2

P_

GPP_TXN2

P_

P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0

P_UMI_TXN0

P_UMI_TXP1

P_UMI_TXN1

P_UMI_TXP2

P_UMI_TXN2

P_UMI_TXP3

P_UMI_TXN3

P_ZVSS

PC

AA2

PC

AA3

PC

Y2

PC

Y1

PC

Y4

PC

Y5

PC

W2

PC

W3

PC

V2

PC

V1

PC

V4

PC

V5

PC

U2

PC

U3

PC

T2

PC

T1

T4

T5

R2

R3

P2

P1

P4

P5

P

N2

P

N3

P

M2

PCIE_FTX_GRX_N13

M1

P

M4

P

M5

P

L2

P

L3

PCIE_FTX_DRX_P0

AD4

PC

AD5

PC

AC2

PCIE_FTX_DRX_N1

AC3

AB2

AB1

AB4

AB5

UMI_FTX_MRX_P0

AF1

UMI_FTX_MRX_N0

AF2

UMI_FTX_MRX_P1

AF5

UMI_FTX_MRX_N1

AF4

UMI_FTX_MRX_P2

AE3

UMI_FTX_MRX_N2

AE2

UMI_FTX_MRX_P3

AD1

UMI_FTX_MRX_N3

AD2

P_ZVSS

K4

IE_FTX_GRX_P0

IE_FTX_GRX_N0

IE_FTX_GRX_P1

IE_FTX_GRX_N1

IE_FTX_GRX_P2

IE_FTX_GRX_N2

IE_FTX_GRX_P3

IE_FTX_GRX_N3

IE_FTX_GRX_P4

IE_FTX_GRX_N4

IE_FTX_GRX_P5

IE_FTX_GRX_N5

IE_FTX_GRX_P6

IE_FTX_GRX_N6

IE_FTX_GRX_P7

IE_FTX_GRX_N7

CIE_FTX_GRX_P12

CIE_FTX_GRX_N12

CIE_FTX_GRX_P13

CIE_FTX_GRX_P14

CIE_FTX_GRX_N14

CIE_FTX_GRX_P15

CIE_FTX_GRX_N15

IE_FTX_DRX_N0

IE_FTX_DRX_P1

1 2

R540 196_0402_1%R540 196_0402_1%

917 0.1U_0402_16V7KVGA@C917 0.1U_0402_16V7KVGA@

C

1 2

C

918 0.1U_0402_16V7KVGA@C918 0.1U_0402_16V7KVGA@

1 2

919 0.1U_0402_16V7KVGA@C919 0.1U_0402_16V7KVGA@

C

1 2

C

920 0.1U_0402_16V7KVGA@C920 0.1U_0402_16V7KVGA@

1 2

C

921 0.1U_0402_16V7KVGA@C921 0.1U_0402_16V7KVGA@

1 2

C

922 0.1U_0402_16V7KVGA@C922 0.1U_0402_16V7KVGA@

1 2

923 0.1U_0402_16V7KVGA@C923 0.1U_0402_16V7KVGA@

C

1 2

924 0.1U_0402_16V7KVGA@C924 0.1U_0402_16V7KVGA@

C

1 2

C

925 0.1U_0402_16V7KVGA@C925 0.1U_0402_16V7KVGA@

1 2

926 0.1U_0402_16V7KVGA@C926 0.1U_0402_16V7KVGA@

C

1 2

C

927 0.1U_0402_16V7KVGA@C927 0.1U_0402_16V7KVGA@

1 2

C928 0.1U_0402_16V7KVGA@C928 0.1U_0402_16V7KVGA@

1 2

C

929 0.1U_0402_16V7KVGA@C929 0.1U_0402_16V7KVGA@

1 2

930 0.1U_0402_16V7KVGA@C930 0.1U_0402_16V7KVGA@

C

1 2

931 0.1U_0402_16V7KVGA@C931 0.1U_0402_16V7KVGA@

C

1 2

932 0.1U_0402_16V7KVGA@C932 0.1U_0402_16V7KVGA@

C

1 2

C

950 0.1U_0402_16V7K

1 2

C

951 0.1U_0402_16V7K

1 2

C952 0.1U_0402_16V7KC952 0.1U_0402_16V7K

1 2

953 0.1U_0402_16V7K

C

1 2

C956 0.1U_0402_16V7KC956 0.1U_0402_16V7K

1 2

C957 0.1U_0402_16V7KC957 0.1U_0402_16V7K

1 2

C958 0.1U_0402_16V7KC958 0.1U_0402_16V7K

1 2

C959 0.1U_0402_16V7KC959 0.1U_0402_16V7K

1 2

C960 0.1U_0402_16V7KC960 0.1U_0402_16V7K

1 2

C961 0.1U_0402_16V7KC961 0.1U_0402_16V7K

1 2

C962 0.1U_0402_16V7KC962 0.1U_0402_16V7K

1 2

C963 0.1U_0402_16V7KC963 0.1U_0402_16V7K

1 2

2

1

0

CK

C

To H

DMI

CIE_FTX_C_GRX_P[0..7] 18

P

CIE_FTX_C_GRX_N[0..7] 18

P

CIE_FTX_C_GRX_P0

CIE_FTX_C_GRX_N0

P

CIE_FTX_C_GRX_P1

P

CIE_FTX_C_GRX_N1

P

CIE_FTX_C_GRX_P2

CIE_FTX_C_GRX_N2

P

CIE_FTX_C_GRX_P3

P

CIE_FTX_C_GRX_N3

P

CIE_FTX_C_GRX_P4

P

CIE_FTX_C_GRX_N4

P

CIE_FTX_C_GRX_P5

P

CIE_FTX_C_GRX_N5

CIE_FTX_C_GRX_P6

P

CIE_FTX_C_GRX_N6

P

CIE_FTX_C_GRX_P7

P

CIE_FTX_C_GRX_N7

PC

IE_FTX_C_DRX_P0 29

IE_FTX_C_DRX_N0 29

PC

IE_FTX_C_DRX_P1 32

IE_FTX_C_DRX_N1 32

PC

UMI_FTX_C_MRX_P0 13

UMI_FTX_C_MRX_N0 13

UMI_FTX_C_MRX_P1 13

UMI_FTX_C_MRX_N1 13

UMI_FTX_C_MRX_P2 13

UMI_FTX_C_MRX_N2 13

UMI_FTX_C_MRX_P3 13

UMI_FTX_C_MRX_N3 13

For U

GLAN

WLAN

MA Mux.

D

APU To HDM

CP

U TSI interface level shift

+3V

S

31.6K_0402_1%

APU_

SID8,14

APU_

SIC8,14

Sequence of APU

Power

+1.

+2.5VS

+1.

+CPU_CORE

+CPU_CORE_NB

+1.2VS

R

535

1 2

SID

APU_

SH111 1N_SOT23-3

B

SIC

APU_

BSH111 1N_SOT23-3

5V

5VS

I

P

C

935 0.1U_0402_16V4Z

1 2

R

536

1 2

30K_0402_1%

G

2

Q9

C_SMB_DA

E

13

D

S

D

S

G

2

0

Q1

C_SMB_CK

E

13

D

S

D

S

P

CIE_FTX_GRX_P[12..15] 28

CIE_FTX_GRX_N[12..15] 28

BS

H111, the Vgs is: min = 0.4V Max = 1.3V

R537

1 2

0_0402_5%

R538

1 2

0_0402_5%

E

C_SMB_DA2 19,36

To

EC

E

C_SMB_CK2 19,36

Gr

oup A

Group B

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

pal Secret Data

Com

2010/08/04 2011/12/31

Com

Deciphered Date

D

lectronics, Inc.

Compal E

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal E

A

MD FS1 PCIE / UMI / TSI

QB

L50 LA-7551P

lectronics, Inc.

653Wednesday, April 27, 2011

E

1.0

A

Dr-Bios.com

1 1

JC

PU1B

M

EMORY CHANNEL A

DDRA_

SMA[15..0]11

DDRA_

SBS0#11

DDRA_

SBS1#11 SBS2#11

DDRA_ DDRA_

SDM[7..0]11

2 2

SDQS011

DDRA_

SDQS0#11

DDRA_

SDQS111

DDRA_ DDRA_SDQS1#11 DDRA_

SDQS211 SDQS2#11

DDRA_ DDRA_SDQS311

SDQS3#11

DDRA_ DDRA_

SDQS411 SDQS4#11

DDRA_

SDQS511

DDRA_ DDRA_

SDQS5#11 DDRA_SDQS611 DDRA_

SDQS6#11

SDQS711

DDRA_ DDRA_SDQS7#11

DDRA_

CLK011

CLK0#11

DDRA_

CLK111

DDRA_ DDRA_

CLK1#11

DDRA_

CKE011

CKE111

DDRA_

ODT011

ODT111

DDRA_

SCS0#11

3 3

DDRA_ DDRA_

DDRA_ DDRA_ DDRA_SWE#11

M_MA_RST#11

ME M

EM_MA_EVENT#11

+MEM_VREF

SCS1#11

SRAS#11

SCAS#11

+1.5V

Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#

Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#Qmbdf!uifn!dmptf!up!BQV!xjuijo!2#

DDRA_

SMA0 SMA1

DDRA_ DDRA_

SMA2 SMA3

DDRA_

SMA4

DDRA_ DDRA_

SMA5 DDRA_SMA6 DDRA_

SMA7

SMA8

DDRA_ DDRA_

SMA9 DDRA_

SMA10 DDRA_

SMA11

SMA12

DDRA_

SMA13

DDRA_ DDRA_

SMA14

SMA15

DDRA_

SBS0#

DDRA_ DDRA_

SBS1#

DDRA_

SBS2#

SDM0

DDRA_

SDM1

DDRA_ DDRA_

SDM2

SDM3

DDRA_ DDRA_SDM4

SDM5

DDRA_ DDRA_

SDM6 DDRA_

SDM7

DDRA_

SDQS0

SDQS0#

DDRA_ DDRA_

SDQS1

SDQS1#

DDRA_ DDRA_SDQS2 DDRA_

SDQS2# DDRA_

SDQS3 DDRA_

SDQS3#

SDQS4

DDRA_ DDRA_

SDQS4#

SDQS5

DDRA_ DDRA_

SDQS5#

SDQS6

DDRA_ DDRA_SDQS6# DDRA_

SDQS7

SDQS7#

DDRA_

CLK0

DDRA_ DDRA_

CLK0# CLK1

DDRA_

CLK1#

DDRA_

DDRA_CKE0 DDRA_

CKE1

DDRA_ODT0

ODT1

DDRA_

SCS0#

DDRA_

SCS1#

DDRA_

DDRA_SRAS# DDRA_

SCAS# SWE#

DDRA_

ME

M_MA_RST#

M

EM_MA_EVENT#

15m

1 2

R541 39.2_0402_1%R541 39.2_0402_1%

M_ZVDDIO

il

U20

M

R20

MA_ADD1

R21

M

P22

M

P21

MA_ADD4

N24

M

N23

M

N20

M

N21

M

M21

M

U23

M

M22

M

L24

M

AA25

MA_ADD13

L21

M

L20

M

U24

M

U21

M

L23

M

E14

MA

J17

MA_DM1

E21

MA

F25

MA

AD27

MA

AC23

MA

AD19

MA

AC15

MA

G14

M

H14

MA_DQS_L0

G18

M

H18

M

J21

M

H21

M

E27

M

E26

M

AE26

M

AD26

M

AB22

M

AA22

M

AB18

M

AA18

M

AA14

M

AA15

M

T21

M

T22

M

R23

M

R24

MA_CLK_L1

H28

M

H27

M

Y25

MA

AA27

MA

V22

M

AA26

MA_CS_L1

V21

M

W24

M

W23

MA

H25

M

T24

M

W20

M_VREF

W21

M_ZVDDIO

AMD_TOPEDO_FS-1

EMORY CHANNEL A

A_ADD0

A_ADD2 A_ADD3

A_ADD5 A_ADD6 A_ADD7 A_ADD8 A_ADD9 A_ADD10 A_ADD11 A_ADD12

A_ADD14 A_ADD15

A_BANK0 A_BANK1 A_BANK2

_DM0

_DM2 _DM3 _DM4 _DM5 _DM6 _DM7

A_DQS_H0

A_DQS_H1 A_DQS_L1 A_DQS_H2 A_DQS_L2 A_DQS_H3 A_DQS_L3 A_DQS_H4 A_DQS_L4 A_DQS_H5 A_DQS_L5 A_DQS_H6 A_DQS_L6 A_DQS_H7 A_DQS_L7

A_CLK_H0 A_CLK_L0 A_CLK_H1

A_CKE0 A_CKE1

_ODT0 _ODT1

A_CS_L0

A_RAS_L A_CAS_L

_WE_L

A_RESET_L A_EVENT_L

CONN@

M

A_DATA0 MA_DATA1 M

A_DATA2

A_DATA3

M MA_DATA4 M

A_DATA5 M

A_DATA6

A_DATA7

M

A_DATA8

A_DATA9

M

A_DATA10 A_DATA11

M MA_DATA12 M

A_DATA13 A_DATA14

M

A_DATA15

M

A_DATA16 A_DATA17

M

A_DATA18

M

A_DATA19

M MA_DATA20 M

A_DATA21 A_DATA22

M M

A_DATA23

M

A_DATA24 A_DATA25

M

A_DATA26

M M

A_DATA27

MA_DATA28 M

A_DATA29 A_DATA30

M M

A_DATA31

M

A_DATA32 A_DATA33

M

A_DATA34

M M

A_DATA35 A_DATA36

M M

A_DATA37 A_DATA38

M M

A_DATA39

A_DATA40

M

A_DATA41

M

A_DATA42

M M

A_DATA43 A_DATA44

M MA_DATA45

A_DATA46

M M

A_DATA47

A_DATA48

M M

A_DATA49 A_DATA50

M M

A_DATA51 A_DATA52

M MA_DATA53 M

A_DATA54

M

A_DATA55

A_DATA56

M M

A_DATA57 A_DATA58

M M

A_DATA59

MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

B

DDRA_

E13 J13 H15 J15 H13 F13 F15 E15

H17 F17 E19 J19 G16 H16 H19 F19

H20 F21 J23 H23 G20 E20 G22 H22

G24 E25 G27 G26 F23 H24 E28 F27

AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25

Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21

AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17

AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13

DDRA_

SDQ0 SDQ1

DDRA_ DDRA_

SDQ2 SDQ3

DDRA_

SDQ4

DDRA_ DDRA_

SDQ5 DDRA_SDQ6 DDRA_

SDQ7

DDRA_

SDQ8 DDRA_

SDQ9 DDRA_

SDQ10

SDQ11

DDRA_

SDQ12

DDRA_ DDRA_

SDQ13

SDQ14

DDRA_ DDRA_

SDQ15

DDRA_

SDQ16 DDRA_

SDQ17

SDQ18

DDRA_

SDQ19

DDRA_

SDQ20

DDRA_ DDRA_

SDQ21

SDQ22

DDRA_ DDRA_SDQ23

DDRA_

SDQ24 DDRA_

SDQ25

SDQ26

DDRA_ DDRA_

SDQ27

SDQ28

DDRA_ DDRA_

SDQ29

SDQ30

DDRA_ DDRA_SDQ31

DDRA_

SDQ32 DDRA_

SDQ33

SDQ34

DDRA_ DDRA_

SDQ35

SDQ36

DDRA_ DDRA_

SDQ37

SDQ38

DDRA_ DDRA_SDQ39

SDQ40

DDRA_ DDRA_

SDQ41

SDQ42

DDRA_ DDRA_

SDQ43

SDQ44

DDRA_

SDQ45

DDRA_

SDQ46

DDRA_ DDRA_SDQ47

SDQ48

DDRA_ DDRA_SDQ49

SDQ50

DDRA_ DDRA_

SDQ51

SDQ52

DDRA_

SDQ53

DDRA_ DDRA_

SDQ54 DDRA_SDQ55

SDQ56

DDRA_ DDRA_SDQ57 DDRA_

SDQ58 DDRA_

SDQ59

SDQ60

DDRA_ DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63

SDQ[63..0] 11

C

DDRB_

DDRB_ DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_SDQS1#12 DDRB_ DDRB_ DDRB_SDQS312 DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_SDQS612 DDRB_ DDRB_ DDRB_SDQS7#12

DDRB_ DDRB_ DDRB_ DDRB_

DDRB_ DDRB_

DDRB_ DDRB_ DDRB_SWE#12

M_MB_RST#12

ME M

EM_MB_EVENT#12

SMA[15..0]12

SBS0#12 SBS1#12 SBS2#12 SDM[7..0]12

SDQS012 SDQS0#12 SDQS112

SDQS212 SDQS2#12

SDQS3#12 SDQS412 SDQS4#12 SDQS512 SDQS5#12

SDQS6#12 SDQS712

CLK012 CLK0#12 CLK112 CLK1#12

CKE012 CKE112

ODT012 ODT112

SCS0#12 SCS1#12

SRAS#12 SCAS#12

DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_SMA6 DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_ DDRB_SDM4 DDRB_ DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_ DDRB_SDQS2 DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_ DDRB_SDQS6# DDRB_ DDRB_

DDRB_ DDRB_ DDRB_ DDRB_

DDRB_CKE0 DDRB_

DDRB_ODT0 DDRB_

DDRB_ DDRB_

DDRB_SRAS# DDRB_ DDRB_

ME

M_MB_RST#

M

EM_MB_EVENT#

SMA0 SMA1 SMA2 SMA3 SMA4 SMA5

SMA7 SMA8 SMA9 SMA10 SMA11 SMA12 SMA13 SMA14 SMA15

SBS0# SBS1# SBS2#

SDM0 SDM1 SDM2 SDM3

SDM5 SDM6 SDM7

SDQS0 SDQS0# SDQS1 SDQS1#

SDQS2# SDQS3 SDQS3# SDQS4 SDQS4# SDQS5 SDQS5# SDQS6

SDQS7 SDQS7#

CLK0 CLK0# CLK1 CLK1#

CKE1

ODT1

SCS0# SCS1#

SCAS# SWE#

D

T27 P24 P25 N27 N26 M28 M27 M24 M25

L26

U26

L27

K27

W26

K25 K24

U27 T28 K28

D14 A18 A22 C25

AF25 AG22 AH18 AD14

C15 B15 E18 D18 E22 D22 B26

A26 AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14

R26

R27

P27

P28

J26 J27

W27

Y28

V25

Y27

V24

V27

V28

J25

T25

JC

PU1C

M

EMORY CHANNEL B

M

B_ADD0 MB_ADD1 M

B_ADD2

B_ADD3

M MB_ADD4 M

B_ADD5 M

B_ADD6

B_ADD7

M

B_ADD8

M M

B_ADD9

B_ADD10

M M

B_ADD11

B_ADD12

M MB_ADD13 M

B_ADD14

B_ADD15

M

B_BANK0

M M

B_BANK1

B_BANK2

M

_DM0

MB MB_DM1 MB

_DM2 _DM3

MB MB

_DM4 _DM5

MB MB

_DM6 _DM7

MB

M

B_DQS_H0 MB_DQS_L0 M

B_DQS_H1

B_DQS_L1

M M

B_DQS_H2 M

B_DQS_L2 M

B_DQS_H3

B_DQS_L3

M

B_DQS_H4

M M

B_DQS_L4

B_DQS_H5

M M

B_DQS_L5

B_DQS_H6

M M

B_DQS_L6 M

B_DQS_H7

B_DQS_L7

M

B_CLK_H0

M M

B_CLK_L0

B_CLK_H1

M MB_CLK_L1

M

B_CKE0 M

B_CKE1

MB

_ODT0 _ODT1

MB

B_CS_L0

M MB_CS_L1

M

B_RAS_L M

B_CAS_L

_WE_L

MB

B_RESET_L

M M

B_EVENT_L

AMD_TOPEDO_FS-1

CONN@

M

B_DATA0 MB_DATA1 M

B_DATA2

B_DATA3

M MB_DATA4 M

B_DATA5 M

B_DATA6

B_DATA7

M

B_DATA8

B_DATA9

M

B_DATA10 B_DATA11

M MB_DATA12 M

B_DATA13 B_DATA14

M

B_DATA15

M

B_DATA16 B_DATA17

M

B_DATA18

M

B_DATA19

M MB_DATA20 M

B_DATA21 B_DATA22

M M

B_DATA23

M

B_DATA24 B_DATA25

M

B_DATA26

M M

B_DATA27

MB_DATA28 M

B_DATA29 B_DATA30

M M

B_DATA31

M

B_DATA32 B_DATA33

M

B_DATA34

M M

B_DATA35 B_DATA36

M M

B_DATA37 B_DATA38

M M

B_DATA39

B_DATA40

M

B_DATA41

M

B_DATA42

M M

B_DATA43 B_DATA44

M MB_DATA45

B_DATA46

M M

B_DATA47

B_DATA48

M M

B_DATA49 B_DATA50

M M

B_DATA51 B_DATA52

M MB_DATA53 M

B_DATA54

M

B_DATA55

B_DATA56

M M

B_DATA57 B_DATA58

M M

B_DATA59

MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

A14 B14 D16 E16 B13 C13 B16 A16

C17 B18 B20 A20 E17 B17 B19 C19

C21 B22 C23 A24 D20 B21 E23 B23

E24 B25 B27 D28 B24 D24 D26 C27

AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24

AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20

AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16

AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13

DDRB_

SDQ0 SDQ1

DDRB_ DDRB_

SDQ2 SDQ3

DDRB_

SDQ4

DDRB_ DDRB_

SDQ5 DDRB_SDQ6 DDRB_

SDQ7

DDRB_

SDQ8 DDRB_

SDQ9 DDRB_

SDQ10

SDQ11

DDRB_

SDQ12

DDRB_ DDRB_

SDQ13

SDQ14

DDRB_ DDRB_

SDQ15

DDRB_

SDQ16 DDRB_

SDQ17

SDQ18

DDRB_

SDQ19

DDRB_

SDQ20

DDRB_ DDRB_

SDQ21

SDQ22

DDRB_ DDRB_SDQ23

DDRB_

SDQ24 DDRB_

SDQ25

SDQ26

DDRB_ DDRB_

SDQ27

SDQ28

DDRB_ DDRB_

SDQ29

SDQ30

DDRB_ DDRB_SDQ31

DDRB_

SDQ32 DDRB_

SDQ33

SDQ34

DDRB_ DDRB_

SDQ35

SDQ36

DDRB_ DDRB_

SDQ37

SDQ38

DDRB_ DDRB_SDQ39

SDQ40

DDRB_ DDRB_

SDQ41

SDQ42

DDRB_ DDRB_

SDQ43

SDQ44

DDRB_

SDQ45

DDRB_

SDQ46

DDRB_ DDRB_SDQ47

SDQ48

DDRB_ DDRB_SDQ49

SDQ50

DDRB_ DDRB_

SDQ51

SDQ52

DDRB_

SDQ53

DDRB_ DDRB_

SDQ54 DDRB_SDQ55

SDQ56

DDRB_ DDRB_SDQ57 DDRB_

SDQ58 DDRB_

SDQ59

SDQ60

DDRB_ DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63

E

DDRB_

SDQ[63..0] 12

ENT# pull high 0.75V reference voltage

EV

+1.5V

4 4

R544 1K_0402_5%R544 1K_0402_5%

1 2

R545 1K_0402_5%R545 1K_0402_5%

1 2

MEM_MA_EVENT#

MEM_MB_EVENT# +MEM_VREF

A

R542

1K_0402_1%

R543

1K_0402_1%

+1.5V

1 2

B

1

C964

1000P_0402_50V7K

2

15m

2

C965

0.1U_0402_16V7K

1

il

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal E

A

MD FS1 DDRIII I/F

QB

L50 LA-7551P

lectronics, Inc.

753Wednesday, April 27, 2011

E

1.0

A

Dr-Bios.com

P

lace near APU

971 0.1U_0402_16V7K

C

To LVD

S

Translator

1 1

T

o FCH VGA ML

100MHz

2 2

100MHz_NSS

+1.5V

R

575 1K_0402_5%

576 1K_0402_5%

R

+1.

5V

3 3

R579 1K_0402_5%R579 1K_0402_5%

581 1K_0402_5%

R

791 1K_0402_5%

R

+1.

5V

R592 1K_0402_5%R592 1K_0402_5%

R593 1K_0402_5%R593 1K_0402_5%

R594 1K_0402_5%R594 1K_0402_5%

R595 1K_0402_5%R595 1K_0402_5%

R596 300_0402_5%R596 300_0402_5%

ute as differentia l

Ro with VSS_SENSE

APU_VDDNB_RUN_FB_L APU_VDDNB_SEN route as differential

4 4

APU_VDD_RUN_FB_L APU_VDD_SE N route as differential

C 20101111

1 2

Close to Header

1 2

P0_TXP0_C26

D

P0_TXN0_C26

D

L_VGA_TXP015

M

L_VGA_TXN015

M

L_VGA_TXP115

L_VGA_TXN115

M

L_VGA_TXP215

ML_VGA_TXN215

M

L_VGA_TXP315

M

L_VGA_TXN315

APU_CLKP13

PU_CLKN13

A

APU_

DISP_CLKP13

DISP_CLKN13

APU_

SVC47

APU_

SVD47

APU_

hang to PU +1.5VS (DG ref. )

APU_SVC

APU_

APU_SID

ERT_L

AL

APU_TDI

APU_TCK

APU_TMS

APU_TRST#

APU_DBREQ#

APU_VDDNB_RUN_FB_L47

APU_VDD_RUN_FB_L47

SVD

SIC

1 2

973 0.1U_0402_16V7K

C

1 2

T25T25

T28T28

T19T19

T20T20

T21T21

T22T22

P

lace near APU

977 0.1U_0402_16V7K

C

1 2

C

968 0.1U_0402_16V7K

1 2

969 0.1U_0402_16V7K

C

1 2

970 0.1U_0402_16V7K

C

1 2

C

978 0.1U_0402_16V7K

1 2

979 0.1U_0402_16V7K

C

1 2

C

980 0.1U_0402_16V7K

1 2

C981 0.1U_0402_16V7K

1 2

CLKP

APU_

CLKN

APU_

DISP_CLKP

APU_

DISP_CLKN

APU_

SVC

APU_

SVD

SIC6,14

APU_

TSI

APU_SID6,14

APU_

RST#13

PWRGD13

APU_

rial VID

Se

R597 0_0402_5%R597 0_0402_5%

R600 0_0402_5%R600 0_0402_5%

APU_VDDNB_SEN47

APU_VDD_SEN47

1 2

DP0

D

DP0

D

DP0_TXP2

D

DP0

D

DP1

D

DP1

D

DP1

D

DP1

D

SIC

APU_

SID

APU_

RST#

APU_

PWRGD

PROCHOT#

APU_

THERMTRIP#

ALERT_L

TDI

APU_

APU_TDO

TCK

APU_

TMS

TRST#

APU_

APU_DBRDY

APU_DBREQ#

APU_VDDNB_SEN

APU_VDD_SEN

A

_TXP0

P0_TXN0

_TXP1

P0_TXN1

P0_TXN2

_TXP3

P0_TXN3

_TXP0

P1_TXN0

_TXP1

P1_TXN1

_TXP2

P1_TXN2

_TXP3

P1_TXN3

B

PU1D

JC

F2

DP0

F1

D

E3

DP0

E2

D

D2

DP0

D1

D

C2

DP0

C3

D

K2

DP1

K1

D

J3

DP1

J2

D

H2

DP1_TXP2

H1

D

G2

DP1

G3

D

AH7

CL

AH6

CL

AH4

DI

AH3

DISP_CLKIN_L

B8

SVC

A8

SVD

AH11

SI

AG11

SI

AF10

RESET_

AE10

PW

AD10

PRO

AG12

THERM

AH12

AL

C12

TDI

A12

TD

A11

TC

D12

TM

B12

TRST_L

B11

DBRDY

C11

DBREQ_L

E8

RSVD_1

K21

RSVD_2

AC11

RSVD_3

B9

VSS_SENSE

C8

VDDP_SENSE

A9

VDDNB_SENSE

B10

VDDIO_SENSE

C9

VDD_SENSE

A10

VDDR_SENSE

AMD_TOPEDO_FS-1

B

_TXP0

P0_TXN0

_TXP1

P0_TXN1

_TXP2

P0_TXN2

_TXP3

P0_TXN3

_TXP0

P1_TXN0

_TXP1

P1_TXN1

P1_TXN2

S

_TXP3

P1_TXN3

KIN_H

KIN_L

SP_CLKIN_H

C

D

L

ROK

CHOT_L

TRIP_L

ERT_L

O

K

S

DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE

ystem DP

CONN@

_AUXP

DP0

_AUXN

_AUXP

DP1

_AUXN

DP1

DP2

_AUXP

_AUXN

DP2

DP3

_AUXP

_AUXN

DP3

DP4

_AUXP

DP4_AUXN

_AUXP

DP5

_AUXN

P0_HPD

D

P1_HPD

P2_HPD

D

P3_HPD

P4_HPD

D

DP5_HPD

DP_

BLON

D

P_DIGON

VARY_BL

DP_

AUX_ZVSS

TEST6

TEST9

TEST10

TEST12

TEST14

TEST15

TEST16

TEST17

TEST18

TEST19

TEST20

TEST21

TEST DISPLAY PORT MISC.

TEST22

TEST23

TEST24

TE

ST25_H

TEST25_L

TEST28_H

TEST28_L

TEST30_H

TEST30_L

TEST31

TEST32_H

TEST32_L

TEST35

FS1R1

DMAACTIVE_L

THERMDA

THERMDC

C

Place near APU

_AUXP

DP0

D4

DP0

D5

L_VGA_AUXP

M

E5

M

L_VGA_AUXN

E6

J5

J6

H4

H5

G5

G6

APU_

F4

APU_

F5

D7

E7

J7

H7

G7

F7

C6

C5

C7

D8

AA1

0

G1

0

H1

2

H1

D9

E9

G9

H9

H1

1

G1

F12

1

E1

D1

1

F10

G1

2

AH10

AH9

K7

K8

AA12

AB12

K22

AB11

AA11

D10

Y11

AB10

AE12

AD12

Llano do not support this thermal die

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

972 0.1U_0402_16V7K

C

_AUXN

974 0.1U_0402_16V7K

C

C975 0.1U_0402_16V7K

976 0.1U_0402_16V7K

C

HDMI_CLK

HDMI_DATA

P0_HPD

D

P1_HPD

P5_HPD

D

DP_ENBKL

DP_

ENVDD

INT_PWM

DP_

AUX_ZVSS

hang to unpop (DG ref.)

C 20101111

T6T6

T7T7

T8T8

T9T9

APU_TEST18

TEST19

APU_

TEST20

APU_

TEST21

APU_

TEST22

T10T10

APU_TEST24

TE

ST25_H

TEST25_L

T11T11

T12T12

M_TEST

T13T13

T14T14

TEST35

FS1R1

ALLOW_STOP

C639 0.1U_0402_16V4Z

T15T15

T16T16

C

1 2

HDMI_CLK 28

APU_

HDMI_DATA 28

P0_HPD 10

D

P1_HPD 10

D

P5_HPD 10

D

P_ENBKL 10

DP_

D

P_INT_PWM 10

R

569 150_0402_1%

1 2

R573 0_0402_5%@R573 0_0402_5%@

1 2

574 1K_0402_5%

R

1 2

R

582 1K_0402_5%

1 2

583 1K_0402_5%

R

1 2

584 1K_0402_5%

R

1 2

585 1K_0402_5%

R

1 2

R

589 1K_0402_5%

1 2

R

590 1K_0402_5%

1 2

ALLOW_STOP 13

1 2

@

2010/08/04 2011/12/31

LVDS

CRT

ENVDD 10

_AUXP_C 26

DP0

_AUXN_C 26

DP0

M

L_VGA_AUXP_C 15

L_VGA_AUXN_C 15

M

2~5 are for GFX interface

AUX use, they could be selected to I2C or AUX logic

VDDIO level Need Level shift

I

HDM

V

DDIO level

Need Level shift

H

DT Debug conn

APU_TRST#

R601 10K_0402_5%R601 10K_0402_5%

R603 10K_0402_5%R603 10K_0402_5%

R605 10K_0402_5%R605 10K_0402_5%

pal Secret Data

Com

Deciphered Date

D

To LVD

S

Translator

To FCH

Asserted as an input to force the processor into the HTC-active state

APU_

THERMTRIP shutdown temperature: 125 degree

APU_

+1.5V

R598 0_0402_5%R598 0_0402_5%

1 2

D

PROCHOT#

THERMTRIP#

E

I

f not used, pins are left unconnected (DG ref.)

20101111

_AUXP

DP0

M

L_VGA_AUXP

L_VGA_AUXN

M

TEST25_L

TEST25_H

TEST35

_TEST

M

FS1R

FS1R In laptop, seems no use

A

LLOW_STOP

MI

5V

+1.

R

R 1K_0402_5%

1K_0402_5%

1 2

R

591 0_0402_5%

+1.

5V

R

610

1K_0402_5%

1 2

MMBT3904_NL_SOT23-3

JP1

1

3

5

7

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

CONN@

Title

Size Document Number Rev

Custom

Date: Sheet of

APU_

SC

APU_PWRGD

586

1 2

E

3 1

2

4

6

8

10K_0402_5%

Indicates to the FCH that a thermal trip

12

has occurred. Its assertion will cause th e FCH to transition the system to S5 immediately

609

R

10K_0402_5%

B

2

Q1

2

C

R

APU_TCK

2

APU_TMS

4

APU_TDI

6

APU_TDO

8

10

12

APU_DBRDY

14

APU_DBREQ#

16

R606 0_0402_5%R606 0_0402_5%

1 2

18

R608 0_0402_5%R608 0_0402_5%

1 2

20

Compal E

AM

D FS1 Display / MISC / HDT

QB

L50 LA-7551P

554 1.8K_0402_5%

R

_AUXN

1

1 : Control S5 Dual PWR plane

RST#

R

1

Q1

MMBT3904_NL_SOT23-3

1 2

611 0_0402_5%

R555 1.8K_0402_5%

547 1.8K_0402_5%

R

556 1.8K_0402_5%

548 510_0402_1%

R

1 2

R

557 510_0402_1%

1 2

R

558 300_0402_5%

1 2

559 300_0402_5%@

R

1 2

564 39.2_0402_1%@

R

1 2

R

567 39.2_0402_1%

1 2

571 10K_0402_5%

R

1 2

612 1K_0402_5%

R

1 2

R

577 1K_0402_5%

1 2

@

R

578 300_0402_5%

1 2

R

580 300_0402_5%

1 2

S

+3V

12

R

587

10K_0402_5%

2

B

E

31

C

Cut on CPU side, Debug mount

R599 0_0402_5%@R599 0_0402_5%@

1 2

R602 0_0402_5%@R602 0_0402_5%@

1 2

lectronics, Inc.

E

12

588

H_

APU_TEST19

APU_TEST18

+1.

3VALW

+

+1.

E

C_THERM# 13,36,47

THERMTRIP# 14

APU_PWRGD

APU_RST#

853Wednesday, April 27, 2011

2VS

5V

5VS

1.0

A

Dr-Bios.com

C

Power Name

D

VD +C

PU_CORE

DDNB

V +CPU_CORE_NB

V

DDIO

+1.5V

DDP / VDDR

V +1.

2VS

DDA

V

1 1

+2.5VS

CORE_NB 330uF X 2 22uF X 4

2 2

3 3

+2.5VS

4 4

onsumption

50A

22.

5A

4A

/ 3.5A

3A

75A

0.

U_CORE

CP 330uF X 4 22uF X 11

+

CPU_CORE_NB

L1

L1 FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12

C

3300P_0402_50V7K

C

3300P_0402_50V7K

C

0.22U_0603_16V4Z

C

0.22U_0603_16V4Z

1040

1041

1

12

2

+CPU_CORE

5V

+1.

2VS

+1.

+1.2VS

il

40m

+VDDA_APU

4.7U_0805_10V4Z

C

180P_0402_50V8J@C

180P_0402_50V8J

1043

C1

1

8

2

C18 & C1043 follow A MD request 201012061900

Keep trace from resistor to APU

@

within 0.6"

2

Keep trace from Caps to APU within 1.2"

JC

PU1E

C1

VDD

D3

VDD

D6

VDD

E1

VDD

F3

VDD

F6

VDD

F8

VDD

G1

VDD

H3

VDD

H6

VDD

H8

VDD

J1

VDD

K3

VDD

K6

VDD

L1

VDD

L11

VDD

L19

VDD

M3

VDD

M6

VDD

M10

VDD

M1

8

VDD

N1

VDD

1

N1

VDD

9

N1

VDD

P3

VDD

P6

VDD

0

P1

VDD

8

P1

VDD

R1

VDD

R1

1

VDD

9

R1

VDD

T3

VDD

J9

VDDNB

J10

VDDNB

J11

VDDNB

J12

VDDNB

J14

VDDNB

J16

VDDNB

K9

VDDNB

K1

0

VDDNB

G28

VDDI

H26

VDDI

J28

VDDI

K20

VDDI

K23

VDDI

K26

VDDI

L22

VDDI

L25

VDDI

L28

VDDI

M20

VDDI

M23

VDDI

M26

VDDI

N22

VDDIO

N25

VDDI

N28

VDDI

P20

VDDI

P23

VDDI

P26

VDDI

AG2

DDP_A_1

V

AG3

VDDP_A_2

AG4

V

DDP_A_3

AG5

V

DDP_A_4

AG

6

VDDR

7

AG

VDDR

AG

8

VDDR

AG9

VDDR

AE11

VDDA

AF11

VDDA

AMD_TOPEDO_FS-1

CONN@

VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB

O O O O O O O O O O O O

O O O O O

VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDIO VDDI VDDI VDDI VDDI VDDI

VDDP_ VDDP_B_2 VDDP_ VDDP_

VDDR VDDR VDDR VDDR

A

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

B

CPU BOTTOM

PU_CORE

+C

C

22U_0805_6.3V6M

982

C7

C

C 1045

1045

C

C 1053

1053

1

2

1

2

1

2

CPU_CORE_NB

+

+1.

10U

_0603_6.3V6M

C6

1

2

180P_0402_50V8J

C1046

1

2

C1054

0.22U_0603_16V4Z

1

2

982

C

C 1000

1000

C

C 1012

1012

C

C 1027

1027

10U_0603_6.3V6MC610U_0603_6.3V6M

180P_0402_50V8J

0.22U_0603_16V4Z

1

2

22U_0805_6.3V6M

1

2

5V

22U_0805_6.3V6M

1

2

5V

0.22U_0603_16V4Z

1

2

C

C 1034

1034

1

2

C

C 1047

1047

1

2

C

C 1055

1055

1

2

2000mil2000mil

+CPU_CORE

T6 T10 T18 U1

1

U1

9

U1 V3 V6 V1

0 8

V1 W1 W1

1

W1

3 5

W1

7

W1 W1

9 Y3 Y6

0

Y1 Y12 Y1

4 6

Y1

8

Y1

0

Y2 AA1 AB3 AB6 AC1 AD3 AD6 AE1

900mil900mil

1

K1

2

K1 K1

3 K14 K1

6

7

K1 K1

8 L18

160mil160mil

R22

O

R25

O

R28

O

T20

O

T23

O

T26

O

U22

O

U25

O

U28

O

V20

O

V23

O

V26

O

W22 W25

O

W28

O

Y24

O

Y26

O

AA28

O

A3

B_1

A4 B3

B_3

B4

B_4

A5 A6 B5 B6

+

CPU_CORE_NB

5V

+1.

DP decoupling

VD

120mil120mil

160mil160mil

B

10U

_0603_6.3V6M

C8

1

2

DDR decoupling

V

180P_0402_50V8J

C

C 1044

1044

1

2

C

0.22U_0603_16V4Z

C

0.22U_0603_16V4Z

1052

1

2

22U_0805_6.3V6M

983

996

1

2

22U_0805_6.3V6M

C

1001

1002

1

2

4.7U_0603_6.3V6K

C

22U_0805_6.3V6M

1013

C1

1

4

2

C

0.22U_0603_16V4Z

180P_0402_50V8J

1028

1029

1

2

180P_0402_50V8J

C

1036

1035

1

2

1000P_0402_50V7K

180P_0402_50V8J

C

1049

1048

1

2

4.7U_0603_6.3V6K

0.22U_0603_16V4Z

0.22U_0603_16V4Z C1

C1

1

0

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SIDE DECOUPLING

C985

C986

22U_0805_6.3V6M

0.22U_0603_16V4Z

4.7U_0603_6.3V6K

C

C 1051

1051

C1

C1 3

3

1

2

C1005

1

2

C17

1

2

+1.

+

1000P_0402_50V7K

1

2

4.7U_0603_6.3V6K

2

1

C986

C987

22U_0805_6.3V6M

1

2

0.22U_0603_16V4Z

180P_0402_50V8J

C1007

C1006

1

2

4.7U_0603_6.3V6K

C1019

C1018

0.22U_0603_16V4Z

1

2

2VS

1

1038

C

C 220U_6.3V_M

220U_6.3V_M

2

C1038 change to SF000002Y00 20101228

+1.2VS

2010/08/04 2011/12/31

C

C997

22U_0805_6.3V6M

984

1

2

22U_0805_6.3V6M

C1004

C

C 1003

1003

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K C16

C16

C1

1

5

2

C

180P_0402_50V8J

1030

1

2

Decoupling between CPU and DIMMs across VDDIO and VSS split

2VS

+1.

0.22U_0603_16V4Z

C

C 1037

1037

1

2

1000P_0402_50V7K

C

C 1050

1050

1

2

4.7U_0603_6.3V6K

C1

1

2

C

D

C991

C988

0.22U_0603_16V4Z

1

2

180P_0402_50V8J

C1008

1

2

C1020

0.22U_0603_16V4Z

1

2

C989

0.22U_0603_16V4Z

1

2

180P_0402_50V8J

C1009

1

+

2

C1021

0.22U_0603_16V4Z

1

2

pal Secret Data

Com

C998

0.01U_0402_16V7K

1

2

390U_2.5V_10M

C1022

0.22U_0603_16V4Z

1

2

D

CP 470uF x 6 22uF x 9

0.22uF x 2 180pF x 2 10nF x 3

Deciphered Date

C991

C990

0.01U_0402_16V7K

1

2

C1023

0.22U_0603_16V4Z

1

2

emo Board Capacitor (include PWM side)

U_CORE

0.01U_0402_16V7K

0.22U_0603_16V4Z

180P_0402_50V8J

1

2

C1024

180P_0402_50V8J

1

2

CORE_NB 470uF x 4 22uF x 6

0.22uF x 2 180uF x 3

D

C992

C1025

1

2

1

2

180P_0402_50V8J

C5

@

330U_D2_2V_Y

1

+

2

VDDIO_SUS (CPU side) 680uF x 1 330uF x 1 22uF x 3

4.7uF x 4

0.22uF x 6 180pF x 4

VDDIO_SUS (DIMM x2) 100uF x 4

0.1uF

Title

AM

Size Document Number Rev

Custom

Date: Sheet of

QB

A1 A15 A1 A1 A2 A2 A2

C1 C1 C1 C18 C2 C2 C24 C2 C2 D1 D1 D1 D1 D2 D2 D25 D2

E1 E1

F11 F14 F16 F18 F20 F22 F24 F26 F28

G1 G15 G1 G1 G2 G2 G2

J18 J20 J22 J24

K1

L10

M1 M1

N1 N1

P1 P1

R10 R1

V

DDP/R_PWM 470uF x 2 10uF x 1

Compal E

D FS1 PWR / GND

L50 LA-7551P

PU1F

JC

A7

VSS

3

VSS VSS

7

VSS

9

VSS

1

VSS

3

VSS

5

VSS

B7

VSS

C4

VSS

0

VSS

4

VSS

6

VSS VSS

0

VSS

2

VSS VSS

6

VSS

8

VSS

3

VSS

5

VSS

7

VSS

9

VSS

1

VSS

3

VSS VSS

7

VSS

E4

VSS

0

VSS

2

VSS

F9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

G4

VSS

G8

VSS

3

VSS VSS

7

VSS

9

VSS

1

VSS

3

VSS

5

VSS

J4

VSS

J8

VSS VSS VSS VSS VSS

9

VSS

L4

VSS

L7

VSS VSS

M9

VSS

1

VSS

9

VSS

N4

VSS

N7

VSS

0

VSS

8

VSS

P9

VSS

1

VSS

9

VSS

R4

VSS

R7

VSS VSS

8

VSS

T9

VSS

AMD_TOPEDO_FS-1

lectronics, Inc.

E

CONN@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDDP 10uF x 3

0.22uF x 2 180pF x 2

E

T11 T19 U4 U7 U1 U1 V9 V1 V1 W4 W7 W1 W1 W14 W1 W1 Y9 Y2 AA4 AA7 AB9 AB1 AB1 AB1 AB1 AB21 AB2 AB2 AB2 AC4 AC7 AC1 AC1 AC1 AC16 AC1 AC2 AC2 AC2 AC2 AC2 AD9 AD1 AE4 AE7 AE1 AE1 AE1 AE1 AE2 AE2 AE2 AE2 AF3 AF6 AF9 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG AH5 AH8 AH1 AH1 AH1 AH19 AH2 AH2 AH2

0 8

1 9

2

10

0 2

6 8

3 5 7 9

3 5 7

0 2 4

8 0 2 4 6 8

1

3 5 7 9 1 3 5 7

3 5 7

1 3 5

VDDR

4.7uF x 4

0.22uF x 4 1nF x 4 180pF x 4

953Wednesday, April 27, 2011

1.0

5

Dr-Bios.com

S

1 2

+3V

12

R

613

10K_0402_5%

2

G

1 3

D

S

D

S

3

Q1

Q1 2N7002K_SOT23-3

2N7002K_SOT23-3

+3V

S

12

621

R

R 10K_0402_5%

10K_0402_5%

2

G

1 3

D

S

D

S

Q16

Q16 2N7002K_SOT23-3

2N7002K_SOT23-3

1K_0402_5%

˛ˣ˗

˛ˣ˗ ˣ˴˸˿ʳ˘ˡ˕˞˟

˛ˣ˗˛ˣ˗

@

R

615

1K_0402_5%

12

R

622

1K_0402_5%

12

@

D D

Translator HPD

From Translator

LV

DS_HPD26

DS_HPD

LV

618 100K_0402_5%

R

CRT HPD

From FCH

F

CH_CRT_HPD15

C C

CH_CRT_HPD

F

627 100K_0402_5%

R

HDMI HPD

From HDMI Conn

HDMI_HPD28

APU_

HDMI_HPD

APU_

@

12

659 100K_0402_5%

R

1 2

R677 0_0402_5%R677 0_0402_5%

R

616

623

+1.5VS

1 2

5VS

+1.

1 2

5VS

+1.

12

@

R

4.7K_0402_5%

4

DP0

_HPD 8

DP1

_HPD 8

630

_HPD 8

DP5

3

ˣ˴˸˿ʳ˘ˡ˕˞˟

ˣ˴˸˿ʳ˘ˡ˕˞˟ˣ˴˸˿ʳ˘ˡ˕˞˟

ENBKL8

DP_

ˣ˴˸˿ʳ˘ˡ˩˗˗

ˣ˴˸˿ʳ˘ˡ˩˗˗ˣ˴˸˿ʳ˘ˡ˩˗˗

DP_

ENVDD8

@

1 2

R

619 2.2K_0402_5%

@

620

R

100K_0402_5%

1 2

R633 2.2K_0402_5%

@

R

634

100K_0402_5%

1 2

2

+3V

S

12

@

R

614

@

617

R

R 100K_0402_5%

100K_0402_5%

1 2

@

C

Q1

5

2

B

E

3 1

MMBT3904_NL_SOT23-3

ENBKL

DP_

@

1 2

R

676 0_0402_5%

+3V

S

@

R

100K_0402_5%

1 2

@

C

9

Q1

2

B

E

3 1

614

4.7K_0402_5%

APU_

ENBKL

R

624 0_0402_5%@R624 0_0402_5%@

1 2

13

D

Q1

4

@

4

@

2

G

2N7002K_SOT23-3

S

ENBKL

12

@

632

R

2

@

G

R

4.7K_0402_5%

13

D

8

Q1

2N7002K_SOT23-3

S

APU_

ENVDD 27

631

MMBT3904_NL_SOT23-3

ENBKL

1

36

B B

A A

5

4

ˣ˴˸˿ʳˣ˪ˠ

ˣ˴˸˿ʳˣ˪ˠˣ˴˸˿ʳˣ˪ˠ

DP_INT_PWM8

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1 2

R637 2.2K_0402_5%

12

R638

4.7K_0402_5%

ompal Secret Data

C

2010/08/04 2011/12/31

C

S

+3V

12

R635

R635 47K_0402_5%

47K_0402_5%

C

Q21

2

B

E

3 1

Deciphered Date

12

R636

4.7K_0402_5%

13

D

Q20

2

G

2N7002K_SOT23-3

S

MMBT3904_NL_SOT23-3

2

APU_INVT_PWM 26,27

Q15 /

Q19 / Q21 change to SB000006A00

20101228

Title

MD FS1 Singal Level Shifter

A

Size Document Number Rev

Custom

Q

BL50 LA-7551P

Date: Sheet of

1

1.0

10 53Wednesday, April 27, 2011

1.0

A

Dr-Bios.com

B

C

D

E

SDQ0 SDQ1

SDM0

SDQ3

SDQ8 SDQ9

SDQS1# SDQS1

SDQ10 SDQ11

SDQ16 SDQ17

SDQS2# SDQS2

SDQ18 SDQ19

SDQ24 SDQ25

SDM3

SDQ26 SDQ27

CKE0

SBS2#

SMA12 SMA9

SMA8 SMA5

SMA3 SMA1

CLK0 CLK0#

SMA10 SBS0#

SWE# SCAS#

SMA13 SCS1#

SDQ33

SDQS4

SDQ34 SDQ35

SDQ41

SDQ42 SDQ43

12

R645

10K_0402_5%

+1.

5V

15mil

DIMM2

J

1

VREF_

3

VSS2

5

0

DQ

7

DQ

1

9

VSS4

11

DM0

13

VSS5

15

DQ

2

17

3

DQ

19

VSS7

21

DQ

8

23

9

DQ

25

VSS9

27

S#1

DQ

29

S1

DQ

31

VSS1

33

DQ10

35

DQ

11

37

VSS1

39

DQ16

41

DQ

17

43

VSS1

45

S#2

DQ

47

S2

DQ

49

VSS1

51

18

DQ

53

DQ

19

55

VSS2

57

DQ24

59

DQ

25

61

VSS2

63

3

DM

65

VSS2

67

DQ

26

69

27

DQ

71

VSS2

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

2/BC#

A1

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0

105

VDD1

107

A

10/AP

109

BA0

111

VDD1

113

WE

115

CAS#

117

VDD1

119

3

A1

121

S1

#

123

VDD1

125

NCTEST

127

VSS2

129

DQ

32

131

DQ

33

133

VSS2

135

DQ

S#4

137

S4

DQ

139

VSS3

141

34

DQ

143

DQ35

145

VSS3

147

DQ

40

149

DQ

41

151

VSS3

153

DM

5

155

VSS3

157

DQ

42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013310-1

DQ

VSS1

DQ DQ

VSS3

S#0

DQ

DQS0

VSS6

DQ

DQ VSS8 DQ DQ

VSS1

DM

RESET#

VSS1

1

DQ14 DQ

3

VSS1

DQ20 DQ

VSS1

5

DM

VSS1

DQ

8

DQ

VSS1

0

DQ DQ29

VSS2

2

S#3

DQ

3

VSS2

DQ DQ

5

VSS2

CKE1 VDD2

A1 A1

VDD4

A1

VDD6

VDD8

VDD1

CK1 CK1

#

1

VDD1

BA1

RAS#

VDD1

3

#

S0

OD

5

VDD1

OD

NC2

7

VDD1

VREF_CA

7

VSS2

DQ DQ

9

VSS3

DM

VSS3

DQ

2

DQ

VSS33

DQ

4

DQ

VSS3

6

S#5

DQ

7

VSS3

DQ DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

VREF_DQ

+

DDRA_ DDRA_

DDRA_

DDRA_SDQ2

+3VS

DDRA_

DDRA_ DDRA_

DDRA_

DDRA_ DDRA_

DDRA_

DDRA_ DDRA_

DDRA_SDQ32 DDRA_

DDRA_SDQS4# DDRA_

DDRA_ DDRA_

DDRA_SDQ40 DDRA_

DDRA_SDM5

DDRA_ DDRA_

DDRA_SDQ48 DDRA_SDQ49

DDRA_SDQS6# DDRA_SDQS6

DDRA_SDQ50 DDRA_SDQ51

DDRA_SDQ56 DDRA_SDQ57

DDRA_SDM7

DDRA_SDQ58 DDRA_SDQ59

R643 10K_0402_5%

1 2

R645

1 1

SDQS1#7

DDRA_ DDRA_

SDQS17

SDQS2#7

DDRA_ DDRA_

SDQS27

DDRA_CKE07

2 2

3 3

4 4

C1080

2.2U_0603_6.3V4Z

DDRA_

SBS2#7

CLK07

DDRA_

CLK0#7

DDRA_

DDRA_SBS0#7

DDRA_SWE#7

DDRA_SCAS#7 DDRA_ODT0 7

SCS1#7

DDRA_

SDQS4#7 SDQS47

DDRA_

DDRA_SDQS6#7 DDRA_SDQS67

+3VS

1

C1081

0.1U_0402_16V4Z

2

5V

+1.

2

DDRA_

4

6

5

8 10 12 14 16

6

18

7

20 22

12

24

13

26

0

28

1

30 32

2

34 36

15

38

4

40 42

21

44

6

46

2

48

7

50

22

52

23

54

9

56

28

58 60

1

62 64

S3

66

4

68

30

70

31

72

6

74 76 78

5

80

4

82 84

1

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100

0

102 104

#

106

2

108 110 112

4

114

#

116

T0

118

6

120

T1

122 124

8

126 128

8

130

36

132

37

134

0

136

4

138

1

140

38

142

39

144 146

44

148

45

150

5

152 154

S5

156

8

158

46

160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

SDQ4 SDQ5

DDRA_

SDQS0# SDQS0

DDRA_

DDRA_SDQ6 DDRA_

SDQ7

DDRA_

SDQ12 SDQ13

DDRA_

SDM1

DDRA_

M_MA_RST#

ME

SDQ14

DDRA_ DDRA_

SDQ15

SDQ20

DDRA_ DDRA_

SDQ21

DDRA_

SDM2

DDRA_

SDQ22

DDRA_

SDQ23

SDQ28

DDRA_

SDQ29

DDRA_

SDQS3#

DDRA_ DDRA_

SDQS3

DDRA_

SDQ30

DDRA_

SDQ31

CKE1

DDRA_

SMA15

DDRA_ DDRA_

SMA14

SMA11

DDRA_ DDRA_

SMA7

DDRA_

SMA6 SMA4

DDRA_

SMA2

DDRA_

SMA0

CLK1

DDRA_ DDRA_

CLK1#

DDRA_

SBS1# SRAS#

DDRA_

SCS0# ODT0

DDRA_

ODT1

DDRA_

15m

il

DDRA_SDQ36 DDRA_

SDQ37

DDRA_SDM4

DDRA_

SDQ38 SDQ39

DDRA_

SDQ44

DDRA_SDQ45

SDQS5#

DDRA_ DDRA_SDQS5

DDRA_

SDQ46 SDQ47

DDRA_

DDRA_SDQ52 DDRA_SDQ53

DDRA_SDM6

DDRA_SDQ54 DDRA_SDQ55

DDRA_SDQ60 DDRA_SDQ61

DDRA_SDQS7# DDRA_SDQS7

DDRA_SDQ62 DDRA_SDQ63

MEM_MA_EVENT#

+0.75VS

SDQS0# 7

DDRA_ DDRA_

SDQS0 7

ME

M_MA_RST# 7

DDRA_SDQS3# 7 DDRA_

SDQS3 7

DDRA_CKE1 7

DDRA_

CLK1 7 CLK1# 7

DDRA_

SBS1# 7

DDRA_SRAS# 7

SCS0# 7

DDRA_

ODT1 7

1

1066

C

1000P_0402_50V7K

2

DDRA_SDQS5# 7 DDRA_

SDQS5 7

DDRA_SDQS7# 7 DDRA_SDQS7 7

MEM_MA_EVENT# 7

FCH_SDATA0 12,14,32 FCH_SCLK0 12,14,32

VREF_CA

+

SDQ[0..63]

DDRA_

SDM[0..7]

DDRA_

SMA[0..15]

lace near DIMM1

P

+1.

5V

0.1U_0402_16V4Z

2

1067

C

1

0.1U_0402_16V4Z

+0.

75VS

2

C

1077

1

0.1U_0402_16V4Z

+

VREF_DQ

15mil

4.7U_0603_6.3V6K

1

@

C1060

2

DDRA_

2

1068

C

1

0.1U_0402_16V4Z

2

C

1078

1

+

VREF_DQ

1

1061

C

2

0.1U_0402_16V4Z

1000P_0402_50V7K

SDQ[0..63] 7

SDM[0..7] 7

SMA[0..15] 7

0.1U_0402_16V4Z

2

1069

C

1

C

1079

2

4.7U_0603_6.3V6K

+1.

1 2

1

1062

C

2

1 2

2

1070

C

1

0.1U_0402_16V4Z

@

1 2

1106 0.1U_0402_16V4Z

C

A

dd C1106

20101101

5V

639

R

R 1K_0402_1%

1K_0402_1%

R641

R641 1K_0402_1%

1K_0402_1%

0.1U_0402_16V4Z

2

1071

C

1

+1.

5V

VREF_CA

+

1072

C

0.1U_0402_16V4Z

15mil

4.7U_0603_6.3V6K

1

@

C1063

2

1

0.1U_0402_16V4Z

1073

C

+VREF_CA

1

2

0.1U_0402_16V4Z

2

1074

C

1

C

1064

2

1000P_0402_50V7K

2

1075

C

1

0.1U_0402_16V4Z

+1.

C

1065

0.1U_0402_16V4Z

2

1076

C

1

5V

R

640

1K_0402_1%

1 2

642

R

R 1K_0402_1%

1K_0402_1%

1 2

Security Classification

Issued Date

DIM

M_A STD H:9.2mm

<A

A

ddress: 00>

B

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

pal Secret Data

Com

2010/08/04 2011/12/31

Com

Deciphered Date

D

lectronics, Inc.

Compal E

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal E

DDRIII S

QB

L50 LA-7551P

lectronics, Inc.

O-DIMM 1

E

11 53Wednesday, April 27, 2011

1.0

A

Dr-Bios.com

B

C

D

E

5V

+1.

2

DDRB_

4

6

5

8 10 12 14 16

6

18

7

20 22

12

24

13

26

0

28

1

30 32

2

34 36

15

38

4

40 42

21

44

6

46

2

48

7

50

22

52

23

54

9

56

28

58 60

1

62 64

S3

66

4

68

30

70

31

72

6

74 76 78

5

80

4

82 84

1

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100

0

102 104

#

106

2

108 110 112

4

114

#

116

T0

118

6

120

T1

122 124

8

126 128

8

130

36

132

37

134

0

136

4

138

1

140

38

142

39

144 146

44

148

45

150

5

152 154

S5

156

8

158

46

160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

SDQ4 SDQ5

DDRB_

SDQS0# SDQS0

DDRB_

DDRB_SDQ6 DDRB_

SDQ7

DDRB_

SDQ12 SDQ13

DDRB_

SDM1

DDRB_

M_MB_RST#

ME

SDQ14

DDRB_ DDRB_

SDQ15

SDQ20

DDRB_ DDRB_

SDQ21

DDRB_

SDM2

DDRB_

SDQ22

DDRB_

SDQ23

SDQ28

DDRB_

SDQ29

DDRB_

SDQS3#

DDRB_ DDRB_

SDQS3

DDRB_

SDQ30

DDRB_

SDQ31

CKE1

DDRB_

SMA15

DDRB_ DDRB_

SMA14

SMA11

DDRB_ DDRB_

SMA7

DDRB_

SMA6 SMA4

DDRB_

SMA2

DDRB_

SMA0

CLK1

DDRB_ DDRB_

CLK1#

DDRB_

SBS1# SRAS#

DDRB_

SCS0# ODT0

DDRB_

ODT1

DDRB_

15mil

DDRB_SDQ36 DDRB_

SDQ37

DDRB_SDM4

DDRB_

SDQ38 SDQ39

DDRB_

SDQ44

DDRB_SDQ45

SDQS5#

DDRB_ DDRB_SDQS5

DDRB_

SDQ46 SDQ47

DDRB_

DDRB_SDQ52 DDRB_SDQ53

DDRB_SDM6

DDRB_SDQ54 DDRB_SDQ55

DDRB_SDQ60 DDRB_SDQ61

DDRB_SDQS7# DDRB_SDQS7

DDRB_SDQ62 DDRB_SDQ63

MEM_MB_EVENT#

+0.75VS

SDQS0# 7

DDRB_ DDRB_

SDQS0 7

ME

M_MB_RST# 7

DDRB_SDQS3# 7 DDRB_

SDQS3 7

DDRB_CKE1 7

DDRB_

CLK1 7 CLK1# 7

DDRB_

SBS1# 7

DDRB_SRAS# 7

SCS0# 7

DDRB_ DDRB_ODT0 7

DDRB_

ODT1 7

1

1088

C

C 1000P_0402_50V7K

1000P_0402_50V7K

2

DDRB_SDQS5# 7 DDRB_

SDQS5 7

DDRB_SDQS7# 7 DDRB_SDQS7 7

MEM_MB_EVENT# 7

FCH_SDATA0 11,14,32 FCH_SCLK0 11,14,32

VREF_CA

+

VREF_DQ

SDQ[0..63]

DDRB_

SDM[0..7]

SMA[0..15]

DDRB_

Place near DIMM2

+1.

5V

0.1U_0402_16V4Z

2

C

1089

1

0.1U_0402_16V4Z

+0.

75VS

0.1U_0402_16V4Z

2

1099

C

1

0.1U_0402_16V4Z

15mil 15mil

VREF_DQ

+

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

1

1083

C1082

1083

C

2

@

2

C

1090

1

2

C

1

1000P_0402_50V7K

2

1

0.1U_0402_16V4Z

1

1100

2

4.7U_0603_6.3V6K

1

1084

C

2

SDQ[0..63] 7

SDM[0..7] 7

SMA[0..15] 7

0.1U_0402_16V4Z

2

C

1091

1092

1

1 2

1107 0.1U_0402_16V4Z

C

1101

C

+

VREF_CA

4.7U_0603_6.3V6K

1

@

C1085

2

C

1093

1

0.1U_0402_16V4Z

+1.

5V

@

A

dd C1107

20101101

VREF_CA

+

0.1U_0402_16V4Z

1

1086

C

2

0.1U_0402_16V4Z

2

C

1094

1

1087

C

2

1000P_0402_50V7K

2

C

1095

1

0.1U_0402_16V4Z

+1.

5V

1

+

C9

330U

2

0.1U_0402_16V4Z

2

C

1096

1

_X_2VM_R6M@

2

C

1097

1

0.1U_0402_16V4Z

2

C

1098

1

SDQ0 SDQ1

SDM0

SDQ3

SDQ8 SDQ9

SDQS1# SDQS1

SDQ10 SDQ11

SDQ16 SDQ17

SDQS2# SDQS2

SDQ18 SDQ19

SDQ24 SDQ25

SDM3

SDQ26 SDQ27

CKE0

SBS2#

SMA12 SMA9

SMA8 SMA5

SMA3 SMA1

CLK0 CLK0#

SMA10 SBS0#

SWE# SCAS#

SMA13 SCS1#

SDQ33

SDQS4

SDQ34 SDQ35

SDQ41

SDQ42 SDQ43

12

R648

10K_0402_5%

5V

+1.

15m

J

il

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

DIMM1

DQ

VREF_ VSS2

0

DQ DQ

1 VSS4 DM0 VSS5 DQ

2

3

DQ VSS7 DQ

8

9

DQ VSS9

S#1

DQ

S1

DQ VSS1

1 DQ10 DQ

11

3

VSS1 DQ16 DQ

17

VSS1

5

S#2

DQ

S2

DQ VSS1

8

18

DQ DQ

19

0

VSS2 DQ24 DQ

25

2

VSS2

3

DM

3

VSS2 DQ

26 27

DQ

5

VSS2

CKE0 VDD1 NC1 BA2 VDD3

2/BC#

A1 A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0

#

1

VDD1 A

10/AP BA0 VDD1

3

WE

#

CAS#

5

VDD1

3

A1 S1

#

7

VDD1 NCTEST

VREF_CA

7

VSS2 DQ

32

DQ

33

9

VSS2 DQ

S#4 S4

DQ VSS3

2

34

DQ DQ35 VSS3

4

DQ

40

DQ

41

6

VSS3 DM

5

7

VSS3 DQ

42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

TYCO_2-2013289-1

VSS1

DQ DQ

VSS3

DQ

DQS0

VSS6

DQ

DQ VSS8 DQ DQ

VSS1

DM

RESET#

VSS1

DQ14 DQ

VSS1

DQ20 DQ

VSS1

DM

VSS1

DQ DQ

VSS1

DQ DQ29

VSS2

DQ

VSS2

DQ DQ

VSS2

CKE1 VDD2

VDD4

VDD6

VDD8

VDD1

CK1

VDD1

RAS#

VDD1

OD

VDD1

OD

NC2

VDD1

VSS2

DQ DQ

VSS3

DM

VSS3

DQ DQ

VSS33

DQ DQ

VSS3

DQ

VSS3

DQ DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

S#0

S#3

A1 A1

A1

CK1

BA1

S0

S#5

SCL

VREF_DQ

+

DDRB_ DDRB_

DDRB_

DDRB_SDQ2

1 1

SDQS1#7

DDRB_ DDRB_

SDQS17

SDQS2#7

DDRB_ DDRB_

SDQS27

DDRB_CKE07

2 2

3 3

4 4

DDRB_ DDRB_

DDRB_SDQS6#7 DDRB_SDQS67

DDRB_

DDRB_ DDRB_

DDRB_SBS0#7

DDRB_SWE#7

DDRB_SCAS#7

DDRB_

SBS2#7

CLK07 CLK0#7

SCS1#7

SDQS4#7 SDQS47

+3VS

DDRB_

DDRB_ DDRB_

DDRB_

DDRB_ DDRB_

DDRB_

DDRB_ DDRB_

DDRB_SDQ32 DDRB_

DDRB_SDQS4# DDRB_

DDRB_ DDRB_

DDRB_SDQ40 DDRB_

DDRB_SDM5

DDRB_ DDRB_

DDRB_SDQ48 DDRB_SDQ49

DDRB_SDQS6# DDRB_SDQS6

DDRB_SDQ50 DDRB_SDQ51

DDRB_SDQ56 DDRB_SDQ57

DDRB_SDM7

DDRB_SDQ58 DDRB_SDQ59

R646 10K_0402_5%

1 2

<BOM Structure>R648

Security Classification

Issued Date

DIM

M_B STD H:5.2mm

<A

A

ddress: 01>

B

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

pal Secret Data

Com

2010/08/04 2011/12/31

Com

Deciphered Date

D

lectronics, Inc.

Compal E

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal E

DDRIII S

lectronics, Inc.

O-DIMM 2

QB

L50 LA-7551P

12 53Wednesday, April 27, 2011

E

1.0

A

Dr-Bios.com

C

1195 150P_0402_50V8J

12

APU_

A_

829 33_0402_5%

R

RST#36

CI Host Bus Reset (To EC)

P

1 1

˚ˣˣʳˣ˃ʳ˙ʳ˨˦˕ˆ˃ʳʳ˦˨˦˂˕

˚ˣˣʳˣ˃ʳ˙ʳ˨˦˕ˆ˃ʳʳ˦˨˦˂˕˚ˣˣʳˣ˃ʳ˙ʳ˨˦˕ˆ˃ʳʳ˦˨˦˂˕ ˚ˣˣʳˣ˄ʳ˙ʳ˨˦˕ˆ˃ʳʳˠ˂˕ʳʳ˅˃˄˃˄˄˃ˆ

˚ˣˣʳˣ˄ʳ˙ʳ˨˦˕ˆ˃ʳʳˠ˂˕ʳʳ˅˃˄˃˄˄˃ˆ

˚ˣˣʳˣ˄ʳ˙ʳ˨˦˕ˆ˃ʳʳˠ˂˕ʳʳ˅˃˄˃˄˄˃ˆ˚ˣˣʳˣ˄ʳ˙ʳ˨˦˕ˆ˃ʳʳˠ˂˕ʳʳ˅˃˄˃˄˄˃ˆ

2 2

SS

APU DISP

NSS

AP

U

VGA

GLA

N

AN

WL

A_

UM

I_MTX_C_FRX_P06

UM

I_MTX_C_FRX_N06

UM

I_MTX_C_FRX_P16 I_MTX_C_FRX_N16

UM UM

I_MTX_C_FRX_P26 I_MTX_C_FRX_N26

UM UM

I_MTX_C_FRX_P36 I_MTX_C_FRX_N36

UM

I_FTX_C_MRX_P06 I_FTX_C_MRX_N06

UM

I_FTX_C_MRX_P16

UM

I_FTX_C_MRX_N16

UM UM

I_FTX_C_MRX_P26 I_FTX_C_MRX_N26

UM

I_FTX_C_MRX_P36

UM

I_FTX_C_MRX_N36

UM

+

PCIE_VDDR_FCH

1.1VS_CKVDD

+

"EXT" CLK mode, input to PCIE,

For

APU_

DISP_CLKP8 DISP_CLKN8

APU_

S_CLKP26

TRAVI TRAVI

S_CLKN26

CLKP8

APU_ APU_

CLKN8

CL

K_PEG_VGA18 K_PEG_VGA#18

CL

K_PCIE_LAN29

CL

K_PCIE_LAN#29

LK_PCIE_M INI132

C C

LK_PCIE_M INI1#32

1 2

C

1189 0.1U_0402_16V7K

1 2

C1190 0.1U_0402_16V7KC1190 0.1U_0402_16V7K

1 2

C

1191 0.1U_0402_16V7K

1 2

1192 0.1U_0402_16V7K

C

1 2

C1196 0.1U_0402_16V7KC1196 0.1U_0402_16V7K

1 2

C

1197 0.1U_0402_16V7K

1 2

C

1198 0.1U_0402_16V7K

1 2

1194 0.1U_0402_16V7K

C

1 2

R

827 590_0402_1%

1 2

R

828 2K_0402_1%

1 2

R

833 2K_0402_1%

1 2

APU_DISP_CLKP APU_

DISP_CLKN

TRAVI

S_CLKP S_CLKN

TRAVI

CLKP

APU_ APU_

CLKN

CLK_PEG_VGA CL

K_PEG_VGA#

CL

K_PCIE_LAN K_PCIE_LAN#

CL

LK_PCIE_M INI1

C

LK_PCIE_M INI1#

C

R

604 0_0402_5%

1 2

R625 0_0402_5%R625 0_0402_5%

1 2

644 0_0402_5%

R

1 2

R572 0_0402_5%R572 0_0402_5%

1 2

RST#_R

UM

I_MTX_FRX_P0 I_MTX_FRX_N0

UM UM

I_MTX_FRX_P1

UM

I_MTX_FRX_N1 I_MTX_FRX_P2

UM

I_MTX_FRX_N2

UM UMI_MTX_FRX_P3 UM

I_MTX_FRX_N3

UM

I_FTX_C_MRX_P0 I_FTX_C_MRX_N0

UM UM

I_FTX_C_MRX_P1 I_FTX_C_MRX_N1

UM

I_FTX_C_MRX_P2

UM UM

I_FTX_C_MRX_N2 I_FTX_C_MRX_P3

UM UM

I_FTX_C_MRX_N3

E_CALRP

PCI PCI

E_CALRN

CL

K_CALRN

CL CL

LK_PCIE_M INI1_R

C

LK_PCIE_MINI1#_R

C

SS

3 3

EMI

R657 22_0402_5%R657 22_0402_5%

CLK_SD_48M31

C1200

12

12P_0402_50V8J

HZ_20PF_7A25000012

25M

12

C1201

12P_0402_50V8J

C1205

4 4

A

C1205

1 2

10P_0402_50V8J

R861

20M_0402_5%

C1206

1 2

10P_0402_50V8J

1 2

R856 0_0402_5%R856 0_0402_5%

12

1 2

R858

X1

1M_0402_5%

Y4

4

1

32.768KHZ_7PF_Q13MC1461000100

Close to HUDSON-M2

3

2

PCIE_RST#_C

K_PCIE_LAN_R K_PCIE_LAN#_R

CLK_SD_48M_R

25M_X1

25M_X2

32K_X1

32K_X2

B

U

AE2

PCI

AD5

A_

AE30

UM

AE32

UM

AD33

UM

AD31

UM

AD28

UMI_TX2P

AD29

UM

AC30

UM

AC32

UM

AB33

UM

AB31

UM

AB28

UM

AB29

UM

Y33

UM

Y31

UM

Y28

UMI_RX3P

Y29

UM

AF29

PCIE_CALRP

AF31

PCI

V33

G

V31

G

W30

G

W32

G

AB26

G

AB27

G

AA24

GPP_TX3P

AA23

G

AA27

G

AA26

G

W27

G

V27

G

V26

G

W26

G

W24

GPP_RX3P

W23

G

F27

CL

G30

PCIE_RCLKP

G28

PCI

R26

DI

T26

DI

H33

D

H31

D

T24

A

T23

A

J30

SL

K29

SL

H27

G

H28

G

J27

G

K26

GPP_CLK1N

F33

G

F31

G

E33

G

E31

G

M23

G

M24

GPP_CLK4N

M27

G

M26

G

N25

G

N26

G

R23

GPP_CLK7P

R24

GPP_CLK7N

N27

GPP_CLK8P

R27

GPP_CLK8N

J26

14M_25M_48M_OSC

C31

25M_X1

C33

25M_X2

HUDSON-M2_FCBGA656

M2@

B

25A

E_RST#

RST#

I_TX0P I_TX0N I_TX1P I_TX1N

I_TX2N I_TX3P I_TX3N

I_RX0P I_RX0N I_RX1P I_RX1N I_RX2P I_RX2N

I_RX3N

E_CALRN

PP_TX0P PP_TX0N PP_TX1P PP_TX1N PP_TX2P PP_TX2N

PP_TX3N

PP_RX0P PP_RX0N PP_RX1P PP_RX1N PP_RX2P PP_RX2N

PP_RX3N

K_CALRN

E_RCLKN

SP_CLKP SP_CLKN

ISP2_CLKP ISP2_CLKN

PU_CLKP PU_CLKN

T_GFX_CLKP T_GFX_CLKN

PP_CLK0P PP_CLK0N

PP_CLK1P

PP_CLK2P PP_CLK2N

PP_CLK3P PP_CLK3N

PP_CLK4P

PP_CLK5P PP_CLK5N

PP_CLK6P PP_CLK6N

HUDSON-2

PCI CLKS

CICLK4/14M_OSC/GPO39

P

PCI EXPRESS INTERFACES

PCI INTERFACE

EQ2#/CLK_RE Q8#/GPIO41

R R

EQ3#/CLK_RE Q5#/GPIO42

G

NT3#/CLK_REQ7#/GPIO46

CLOCK GENERATOR

LPCAPUS5 PLUS

DRQ1#/CLK_REQ6#/GPIO49

L

C

AF3

PCI

CLK0

RST#

PCI

A

D0/GPIO0 D1/GPIO1

A

D2/GPIO2

A A

D3/GPIO3 D4/GPIO4

A A

D5/GPIO5 D6/GPIO6

A

D7/GPIO7

A A

D8/GPIO8

AD9/GPIO9 D10/GPIO10 D11/GPIO11

D13/GPIO13 D14/GPIO14 D15/GPIO15 D16/GPIO16 D17/GPIO17 D18/GPIO18 D19/GPIO19 D20/GPIO20

D22/GPIO22 D23/GPIO23 D24/GPIO24 D25/GPIO25 D26/GPIO26 D27/GPIO27 D28/GPIO28 D29/GPIO29

D31/GPIO31

CBE0 CBE1 CBE2 CBE3

FRAM

DEVSEL

I

RDY#

TRDY#

PAR STO PERR# SERR# REQ

GN

T1#/GPO44

CL

KRUN#

CK#

LO

TE#/GPIO32 TF#/GPIO33

TG#/GPIO34

PCCLK0

L

PCCLK1

L

LA LA LAD2 LA

LFRAM

L

DRQ0#

PROCHOT#

APU_PG

LDT_STP#

APU_RST#

RTCCLK

32K_X1

32K_X2

AF1 AF5 AG2 AF6

AB5

AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13

A_PWRGD_R

VG

AH14 AD15 AC15 AE16 AN3

#

AJ8

#

AN10

#

AD12

#

AG10

E#

AK9

#

AL10 AF10 AE1

0

AH1

P#

AM

9 AH8 AG15

0#

AG13 AF15 AM17 AD16

T0#

AD13 AD21 AK17 AD19 AH9

AF18 AE18 AC16 AD18

L

B25

L

D25

LP

D27

D0

LP

C28

D1

LP

A26

LP

A29

D3

A31

E#

B27 AE27 AE19

G25 E28 E26 G26 F26

H7 F1 F3 E6

32K_X1

G2

32K_X2

G4

C

T23T23

R842 0_0402_5%R842 0_0402_5%

T24T24

PC_CLK0_EC_R

PC_CLK1_R

C_AD0 C_AD1 C_AD2 C_AD3

APU_PWRGD

R

R R

R

844

R

R855 22_0402_5%R855 22_0402_5%

2010/08/04 2011/12/31

P

CICLK1/GPO36 CICLK2/GPO37

P

CICLK3/GPO38

P

A A AD12/GPIO12 A A A A A A A A AD21/GPIO21 A A A A A A A A AD30/GPIO30 A

EQ1#/GPIO40

R

GN

NT2#/SD_LED/GPO45

IN

IN IN INTH#/GPIO35

S

ERIRQ/GPIO48

DMA_ACTIVE#

S5_CORE_EN

INTRUDER_ALERT#

VDDBT_RTC_G

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

843

1 2

22_0402_5%

671

1 2

22_0402_5%

1 2

0_0402_5%

R853 0_0402_5%@R853 0_0402_5%@

1 2

CI_CLK1 16

P

CI_CLK3 16

P

CI_CLK4 16

P

PC_CLK0_EC

L

C1202

0.1U_0402_16V4Z

pal Secret Data

Com

Deciphered Date

APU_

PCIE_RST#_C

E_GPIO1

1 2

109 10K_0402_5%

R

@

RTCVCC_R

C1203

1

2

D

For PCIE device reset on FS1 (GLAN,WLAN)

R

825 33_0402_5%

1 2

150P_0402_50V8J

VG

A_PWRGD25,48

PCI_AD23 16 PCI

_AD24 16

PCI

_AD25 16

PCI

_AD26 16 _AD27 16

PCI

P

E_GPIO0 18

PE_GPIO1 25,36

LPC_CLK0_EC 16,36 CL

K_PCI_DB 32

PC_CLK1 16

L

C_AD0 32,36

LP

C_AD1 32,36

LP

C_AD2 32,36

LP

C_AD3 32,36

LP

C_FRAME# 32,36

LP

RQ 36

SERI

ALLOW_STOP 8 EC_THERM# 8,36,47 APU_PWRGD 8

APU_RST# 8

RTC_CLK 16,36

1 2

R859 510_0402_5%R859 510_0402_5%

W=20mils

for Clear CMOS

1U_0402_6.3V6K

D

C

1188

+3

VALW

1193

@C1193

@

C

1 2

0.1U_0402_16V4Z

5

@

2

P

B

4

Y

1

A

G

U2

6

2

1

VG

A_PWRGD

826

R

8.2K_0402_5%@

1 2

U2

7

@U27

@

2

1

NC7SZ08P5X_NL_SC70-5

3

1 2

835 0_0402_5% R835 0_0402_5%

R

+3

VALW

@C1199

@

1 2

0.1U_0402_16V4Z

5

P

B

4

Y

A

G

3

1 2

832 0_0402_5% R832 0_0402_5%

R

6

C

1199

1 2

830 0_0402_5%@R830 0_0402_5%@

R

1 2

R

831 100K_0402_5%@R831 100K_0402_5%@

˟˸˸˿ʳ˻˼˹ʳʳ˜˦˟ˉ˅ˉˊ

+3V

1 2

S

836

R

4.7K_0402_5%

APU_

10K_0402_5%

PWRGD

5VS

+1.

12

834

R

B

2

E

3 1

C

Q38

Q38 MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

˥˧˖ʳ˕˔˧˧ʳ˖ˁ

CONN@

APU_PG/APU_RST#/L DT_STP# : OD pin DMA_ACTIVE# : IN/OD, 0.8V threshold PROCHOT# : IN, 0.8V threshold LDT_STP : No use, NC

DM

A active. The FCH drives the DMA_ACTIVE# to APU to notify D MA activity. This will cause the APU to reestablish the UMI link quicker.

D23

1

DAN202UT106_SC70-3

12

CLRP1

SHORT PADS

@

+RTCVCC

1

C1204

2

0.1U_0402_16V4Z

Compal E

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal E

Hudson-M2/M3-UMI/P

QB

L50 LA-7551P

E

P

LT_RST# 18,26,29,32

VG

Q38 ch

ange to SB000006A00

20101228

APU_PWRGD_L 47

+RTCBATT

1

JR

TC1

+

SUYIN_060003HA002G202ZL

-

2

+RTCBATT

12

2

3

lectronics, Inc.

CI/CLOCK/LPC/RTC

13 53Wednesday, April 27, 2011

E

A_PWRGD_R

R857

R857 1K_0402_5%

1K_0402_5%

+CHGRTC

1.0

A

Dr-Bios.com

P

CIE_RST2 : Reset PCIE device on Hudson2

EC_

LID_OUT#36

SL

P_S3#36 P_S5#36

SL

PBTN_

OUT#36

CH_PWRGD36

F

1 1

GA2036

EC_

KBRST#36 SCI#36

EC_

SMI#36

EC_

PCIE_WAKE#

FCH_

THERMTRIP: Need level shift f rom +3VALW to +1.5V

SM bus 0-->S0 PWR domain SM bus 1-->S5 PWR domain

VGA_PD: Support MLDAC power save if connect 0: MLDAC power on 1: MLDAC power off

2 2

HDA_ HDA_

HDA_

+3

VALW

1 2

R

56 100K_0402_5%

3 3

4 4

1 2

54 100K_0402_5%

R

1 2

871 10K_0402_5%

R

1 2

874 2.2K_0402_5%

R

1 2

876 2.2K_0402_5%

R

1 2

R877 10K_0402_5%

1 2

R878 10K_0402_5%

+3VS

1 2

R880 2.2K_0402_5%R880 2.2K_0402_5%

1 2

R881 2.2K_0402_5%R881 2.2K_0402_5%

1 2

R882 8.2K_0402_5%

1 2

R940 8.2K_0402_5%R940 8.2K_0402_5%

1 2

R884 2.2K_0402_5%R884 2.2K_0402_5%

1 2

R885 10K_0402_5%

1 2

R886 10K_0402_5%

1 2

R888 10K_0402_5%

1 2

R55 100K_0402_5%R55 100K_0402_5%

@

HDA_

Modify 2010212-AMD request

FCH_SCLK0

FCH_SDATA0

MINI1_CLKREQ#

Modify 2010212-AMD request

LAN_CLKREQ#_1

Modify 20101111

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

HDA_SDIN1

H_THERMTRIP#8

EC_

AN_CLKREQ#29

L

F FCH_

INI1_CLKREQ#32

M

BITCLK_AUDIO30 SDOUT_AUDIO30

SDIN030

SYNC_AUDIO30

RST_AUDIO#30

OC2#

USB_

OC0#

USB_

OC1#

H_

THERMTRIP#

FCH_SCLK1

FCH_

SDATA1

EC_LID_OUT#

FCH_PCIE_WAKE#

PCIE_WAKE#29,32,36

CH_SCLK011,12,32

USB_ USB_ USB_

RSMRST#36

SDATA011,12,32

A_PD16

VG

OC2#34 OC1#34

OC0#34

FCH_

R

M

odify 2010212-AMD request

F FCH_ F FCH_

M

VG

USB_ USB_ USB_

R

866 33_0402_5%

1 2

R867 33_0402_5%R867 33_0402_5%

1 2

R

868 33_0402_5%

1 2

869 33_0402_5%

R

1 2

VALW

+3

8.2K_0402_5%

@

8.2K_0402_5%

@

12

R4

7

5

R488.2K_0402_5%@R488.2K_0402_5%

8.2K_0402_5%

@

8.2K_0402_5%

@

12

@

R4

R4 6

6

+3VALW

For FCH internal debug use

1 2

R887 2.2K_0402_5%

1 2

R889 2.2K_0402_5%

1 2

R890 2.2K_0402_5%

1 2

VALW

+3

R

1 2

+3VS

R

81 0_0402_5%

1 2

CH_SCLK0

SDATA0

CH_SCLK1

SDATA1

INI1_CLKREQ#

A_PD

OC2# OC1# OC0#

8.2K_0402_5%

@

8.2K_0402_5%

@

R4

R4 3

3

FCH_GPIO189 FCH_GPIO190 FCH_GPIO191

8.2K_0402_5%

@

8.2K_0402_5%

@

Pr

oject SKU ID

GPIO189 (use VGA) L(NO)

R4

R4 4

4

GPIO190 (use PX)

GPIO191

Add Project ID Table 201011301600

@

A

B

EC

TEST0 TEST1 TEST2

SY

@

18 10K_0402_5%

862 10K_0402_5%

1 2

R

873 10K_0402_5%

HDA_ HDA_ HDA_ HDA_

HDA_SYNC HDA_

R44 L(NO) R46 L(15") R48

TEST0

TEST1

TEST2

B

_LID_OUT#

S_RESET#

L

AN_CLKREQ#_1

T29T29

BITCLK SDOUT SDIN0 SDIN1

T31T31 T35T35

RST#

T27T27

FCH_GPIO189 F

CH_GPIO190

F

CH_GPIO191

H(YES) R43 H(YES) R45 H(17") R47

25D

U

AB6

E_RST2#/PCI_PME#/GEVENT4#

PCI

R2

#/GEVENT22#

RI

W7

_CS3#/GBE_STAT1/GEVENT21#

SPI

T3

SL

P_S3#

W2

P_S5#

SL

J4

PWR_BTN#

N7

WR_GOOD

P

T9

TEST0

T10

TMS

TEST1/

V9

TEST2

AE22

G

A20IN/GEVENT0#

AG19

AF19

AG24 AE24 AE26 AF22 AH17 AG18 AF24 AD26 AD25

AG25 AG22

AG26

AF25

/GEVENT1#

KBRST#

R9

L

PC_PME#/GEVENT3#

C26

LPC_SMI#/GEVENT23#

T5

L

PC_PD#/GEVENT5#

U4

S_RESET#/GEVENT19#

SY

K1

WAKE#/GEVENT8#

V7

I

R_RX1/GEVENT20#

R10

THRM

TRIP#/SMBALERT#/GEVENT2#

_PWRGD

WD

U2

RSM

RST#

C

LK_REQ4#/SA TA_IS0#/GPIO64 LK_REQ3#/SA TA_IS1#/GPIO63

C SMARTVOLT1/SATA_IS2#/GPIO50 C

LK_REQ0#/SA TA_IS3#/GPIO60

ATA_IS4#/FA NOUT3/GPIO55

S

IS5#/FANIN3/GPIO59

SATA_

GPIO66

SPKR/ S

CL0/GPIO43

/GPIO47

SDA0

T7

CL1/GPIO227

S

R7

/GPIO228

SDA1 CLK_REQ2#/FANIN4/GPIO62 CL

K_REQ1#/FANOUT4/GPIO61

J2

R_LED#/LLB#/GPIO184

I SM

ARTVOLT2/SHUTDOWN#/GPIO51

V8

_RST#/GEVENT7#/VGA_PD

DDR3

W8

GB

E_LED0/GPIO18 3

Y6

_HOLD#/GBE_LED1/GEVENT9#

SPI

V10

BE_LED2/GEVENT10#

G

AA8

G

BE_STAT0/GEVENT11#

CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

M7

BL

INK/USB_OC7#/GEVENT18#

R8

USB_

OC6#/IR_TX1/GEVENT6#

T1

USB_

OC5#/IR_TX0/GEVENT17#

P6

OC4#/IR_RX0/GEVENT16#

USB_

F5

OC3#/AC_PRES/TDO/GEVENT15#

USB_

P5

USB_

OC2#/TCK/GEVENT14#

J7

OC1#/TDI/GEVENT13#

USB_

T8

USB_

OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

AB3

BITCLK

AZ_

AB1

SDOUT

AZ_

AA2

A

Z_SDIN0/GPIO1 67

Y5

Z_SDIN1/GPIO1 68

A

Y3

AZ_SDIN2/GP IO169

Y1

Z_SDIN3/GPIO1 70

A

AD6

AZ_SY

NC

AE4

AZ_RST#

K19

S2_DAT/SD A4/GPIO187

P

J19

PS2_CLK/CEC/SCL4/GPIO188

J21

SPI

_CS2#/GBE_STAT2/GPIO166

D21

PS2

KB_DAT/GPIO189

C20

KB_CLK/GPIO190

PS2

D23

PS2

M_DAT/GPIO191

C22

PS2M_CLK/GPIO192

F21

KSO_0/GPIO209

E20

KSO_1/GPIO210

F20

KSO_2/GPIO211

A22

KSO_3/GPIO212

E18

KSO_4/GPIO213

A20

KSO_5/GPIO214

J18

KSO_6/GPIO215

H18

KSO_7/GPIO216

G18

KSO_8/GPIO217

B21

KSO_9/GPIO218

K18

KSO_10/GPIO219

D19

KSO_11/GPIO220

A18

KSO_12/GPIO221

C18

KSO_13/GPIO222

B19

KSO_14/GPIO223

B17

KSO_15/GPIO224

A24

KSO_16/GPIO225

D17

KSO_17/GPIO226

HUDSON-M2_FCBGA656

M2@

C

HUDSON-2

USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO

EMBEDDED CTRL

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

SBCLK/14M_25M_48M_OSC

U

USB MISCUSB 1.1USB 2.0USB 3.0

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198

EC_PWM2/EC_TIMER2/WOL_EN/GPIO199

EC_PWM3/EC_TIMER3/GPIO200

2010/08/04 2011/12/31

USB_

FSD1P/GPIO186

USB_

FSD0P/GPIO185

USB_ USB_

USB_HSD11P USB_

USB_HSD10P USB_

USBSS_

USB_ USB_

USB_

USB_ USB_

USB_

USB_SS_RX2N

USB_ USB_

USB_

USB_ USB_SS_TX0N

USB_

CL2/GPIO193

S

SDA2 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201

KSI_1/GPIO202

KSI_2/GPIO203

KSI_3/GPIO204

KSI_4/GPIO205

KSI_5/GPIO206

KSI_6/GPIO207

KSI_7/GPIO208

RCOMP

USB_FSD1N

FSD0N

USB_

HSD13P HSD13N

HSD12P HSD12N

HSD11N

HSD10N

HSD9P

USB_

HSD9N

USB_

HSD8P

USB_ USB_

HSD8N

USB_HSD7P USB_

HSD7N

HSD6P

USB_

HSD6N

USB_

HSD5P

USB_

HSD5N

USB_

USB_HSD4P USB_

HSD4N

USB_

HSD3P HSD3N

USB_

HSD2P

USB_

HSD2N

USB_

USB_HSD1P USB_

HSD1N

USB_

HSD0P

USB_

HSD0N

CALRP CALRN

SS_TX3P SS_TX3N

SS_RX3P

SS_RX3N

SS_TX2P SS_TX2N

SS_RX2P

SS_TX1P SS_TX1N

SS_RX1P

SS_RX1N

SS_TX0P

SS_RX0P

SS_RX0N

/GPIO194

Com

G8

USB_

B9

H1 H3

H6 H5

H10 G10

K10 J12

G12 F12

U

K12

U

K13

B11 D11

E10 F10

C10 A10

H9 G9

A8 C8

U

F8

U

E8

USB20_P3

C6

U

A6

U

C5

U

A5

U

C1

U

C3

USB20_P0

E1

U

E3

USBSS_

C16

USBSS_

A16

A14 C14

C12 A12

D15 B15

E14 F14

F15 G15

H13 G13

USB30_M

J16

USB30_M

H16

USB30_MRX_DTX_P0

J15

USB30_M

K15

870 10K_0402_5%

R

H19

872 10K_0402_5%

R

G19

APU_

G22

APU_SID

G21 E22 H22

EC_PWM2

J22 H21

K21 K22 F22 F24 E24 B23 C24 F18

pal Secret Data

Deciphered Date

SB20_P10 SB20_N10

SB20_P4 SB20_N4

SB20_N3

SB20_P2 SB20_N2

SB20_P1 SB20_N1

SB20_N0

D

RCOMP

R863 11.8K_0402_1%R863 11.8K_0402_1%

1 2

CALRP

864 1K_0402_1%M3@

R

CALRN

1 2 1 2

SIC

1 2

R865 1K_0402_1%

1 2

M3@

TX_DRX_P0 TX_DRX_N0

RX_DTX_N0

C

C37 0.1U_0402_16V7K

D

U

SB20_P10 34 SB20_N10 34

U

SB20_P4 31 SB20_N4 31

U

SB20_P3 32 SB20_N3 32

U

SB20_P2 27

U U

SB20_N2 27

SB20_P1 30

U

SB20_N1 30

U

SB20_P0 34 SB20_N0 34

U

39 0.1U_0402_16V7K

1 2

M3@

APU_SIC 6,8 APU_SID 6,8

EC_PWM2 16

USB1

CardReder

WLAN(BT)

CMOS

USB3

USB2

M3@

E

Hudson-M2 Hudson-M3 E

HCI CTL DEV 22, Fn 2 <Disable CTL of M2>

Hudson-M2/M3 EHCI CTL DEV 19, Fn 2

Hudson-M2/M3 EHCI CTL DEV 18, Fn 2

H_VDD_11_SSUSB_S

+FC

TX_C_DRX_P0 34

USB30_M USB30_M

SB30_MRX_DTX_P0 34

U

SB30_MRX_DTX_N0 34

U

Title

Hudson-M2/M3-A

Size Document Number Rev

Custom

QB

Date: Sheet of

TX_C_DRX_N0 34

Compal E

L50 LA-7551P

On board US

lectronics, Inc.

CPI/USB/EC

E

B Conn

14 53Friday, April 29, 2011

xHCI CTL DEV 16, Fn 1 x

HCI CTL

DEV 16, Fn 0

Hudson-M3 xHCI CTL DEV 16, Fn 1 x

HCI CTL

DEV 16, Fn 0

1.0

A

Dr-Bios.com

STX_DRX_P033

SATA_ SATA_

HDD1

ODD

1 1

2 2

+AVDD_SATA

3 3

STX_DRX_N033

SATA_

DTX_C_SRX_N033

SATA_

DTX_C_SRX_P033

SATA_

STX_DRX_P133 STX_DRX_N133

SATA_

DTX_C_SRX_N133

SATA_ SATA_

DTX_C_SRX_P133

+3V

S

W

L_OFF#32

B

8991K_0402_1%

R

12

9001K_0402_1%

R

12

LED#32

SATA_

902 10K_0402_5%

R

1 2

T40T40

N32

BT_O

1 2

R13 10K_0402_5%R 13 10K_0402_5%

1 2

R14 10K_0402_5%R 14 10K_0402_5%

1 2

R15 10K_0402_5%R 15 10K_0402_5%

1 2

R16 10K_0402_5%R 16 10K_0402_5%

SATA_

BT_ON

WL_OFF#

CALRP

CALRN

LED#

U

25B

AK19

SATA_

TX0P

AM19

TX0N

SATA_

AL20

RX0N

SATA_

AN20

SATA_

RX0P

AN22

SATA_TX1P

AL22

TX1N

SATA_

AH20

RX1N

SATA_

AJ20

RX1P

SATA_

AJ22

TX2P

SATA_

AH22

SATA_

TX2N

AM23

RX2N

SATA_

AK23

SATA_

RX2P

AH24

SATA_

TX3P

AJ24

TX3N

SATA_

AN24

SATA_

RX3N

AL24

SATA_

RX3P

AL26

TX4P

SATA_

AN26

SATA_

TX4N

AJ26

SATA_

RX4N

AH26

RX4P

SATA_

AN29

SATA_

TX5P

AL28

TX5N

SATA_

AK27

RX5N

SATA_

AM27

SATA_

RX5P

L29

A

NC6

1

AN3

NC7

A

L31

NC8

L33

A

NC9

AH33

0

NC1

AH31

NC1

1

AJ33

2

NC1

AJ31

NC1

3

AF28

SATA_

CALRP

AF27

CALRN

SATA_

AD22

ACT#/GPIO67

SATA_

AF21

SATA_

X1

AG21

SATA_

X2

AH16

FANOUT0/GPIO5 2

AM15

F

ANOUT1/GPIO53

AJ16

F

ANOUT2/GPIO54

AK15

N0/GPIO56

FANI

AN16

FANI

N1/GPIO57

AL16

N2/GPIO58

FANI

K6

TEMPIN0/GPIO1 71

K5

TEMPIN1/GPIO1 72

K3

TEMPIN2/GPIO1 73

M6

TEMPIN3/TALERT#/GPIO174

HUDSON-M2_FCBGA656

M2@

HUDSON-2

SERIAL ATA

HW MONITOR

C

S

D_CLK/SCL K_2/GPIO73

D_CMD/SL OAD_2/GPIO74

S

D_DATA0/S DATI_2/GPIO77

D_DATA1/S DATO_2/GPIO78

S

SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK

M_RST#/SPI_WP#/GPIO161

RO

VG VG

M

V

IN3/SDATO_1 /GPIO178

V

VIN4/SLOAD_ 1/GPIO179

VIN5/SCLK_ 1/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

D_CD/GPIO75

S

D_WP/GPIO7 6

S

SD_DATA2/GPIO79

DATA3/GPIO80

SD_

BE_COL

G

BE_CRS

G

BE_MDCK

BE_MDIO

G

BE_RXCLK

BE_RXD3

G

BE_RXD2

G G

BE_RXD1

GBE_RXD0

G

BE_RXCTL/RXDV

BE_RXERR

G

GBE_TXCLK

G

BE_TXD3

G

BE_TXD2 BE_TXD1

G

BE_TXD0

G

BE_TXCTL/TXEN

BE_PHY_PD

G

BE_PHY_RST#

BE_PHY_INTR

G

PI_DI/GPIO164

S

PI_DO/GPIO163

S

PI_CLK/GPIO162

S

PI_CS1#/GPIO165

VGA_RED

VG

A_GREEN

A_BLUE

VG

VGA_HSYNC/GPO68 VG

A_VSYNC/GPO69

A_DDC_SDA/GPO70 A_DDC_SCL/GPO71

A_DAC_RSET

VG

AUX_

VGA_CH_P

VGA_CH_N

AUX_

AUXCAL

L_VGA_L0P

M

L_VGA_L0N

M

L_VGA_L1P L_VGA_L1N

M

ML_VGA_L2P

L_VGA_L2N

M

L_VGA_L3P

M

L_VGA_L3N

L_VGA_HPD/GPIO229

VIN0/GPIO175

V

IN1/GPIO176

IN2/SDATI_1 /GPIO177

NC1 NC2 NC3 NC4 NC5

AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14

AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9

V6 V5 V3 T6 V1

L30

L32

M29

M28 N30

M33 N32

K31

V28 V29

U2

T31 T33 T29 T28 R32 R30 P29 P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16 AH10 A28 G27 L4

G

BE_COL BE_CRS

G

BE_MDIO

G

BE_RXERR

G

BE_PHY_INTR

G

H_SPI_CLK_R

FC

R

896 150_0402_1%

1 2

897 150_0402_1%

R

1 2

R898 150_0402_1%R898 150_0402_1%

1 2

R901 715_0402_1%R901 715_0402_1%

1 2

AUXCAL

1 2

8

903 100_0402_1%

R

CH_CRT_HPD

F

1 2

R

5 10K_0402_5%

1 2

6 10K_0402_5%

R

1 2

R

7 10K_0402_5%

1 2

8 10K_0402_5%

R

1 2

R9 10K_0402_5%R9 10K_0402_5%

1 2

R10 10K_0402_5%R 10 10K_0402_5%

1 2

R11 10K_0402_5%@R11 10K_0402_5%@

1 2

R12 10K_0402_5%R 12 10K_0402_5%

35 0_0402_5%@R35 0_0402_5%@

R

D

SYS BIO

VALW

+3

R626 1K_0402_5%

R626 1K_0402_5% R

R R

R

SPI_MISO

FCH_ FCH_

SPI_MOSI

1 2

FCH_

SPI_CS1#

FCH_

SPI_WP#

M

L_VGA_AUXP_C 8

ML_VGA_AUXN_C 8

M

L_VGA_TXP0 8

M

L_VGA_TXN0 8 L_VGA_TXP1 8

M

L_VGA_TXN1 8

M M

L_VGA_TXP2 8 L_VGA_TXN2 8

M M

L_VGA_TXP3 8 L_VGA_TXN3 8

M

CH_CRT_HPD 10

F

S ROM

U2

FCH_

L

SPI_CS1# SPI_WP#

FCH_ FCH_

SPI_HOLD#

FC

H_SPI_CLK

dd for EMI 201011291330

A

A 20101111

F

1 2 1 2

934 10K_0402_5%

1 2

@

935 10K_0402_5%

@

@ @

@

SPI_CLK

FCH_

F

CH_CRT_R 27

F

CH_CRT_G 27

CH_CRT_B 27

F

CH_CRT_HSYNC 27

F

CH_CRT_VSYNC 27

F

CH_CRT_DDC_SDA 27 CH_CRT_DDC_SCL 27

F

+VDDAN_11_M

GL-02/10/2011: Please enabled integrated pull -up/pull-down and left unconnected.

U2

1

CS#

3

WP

7

HO

4

GN

@

MX25L1606EM2I-12G SOP 8P

SA000041N00

1 2

BE_MDIO

G

hange to PD 20101112

C

BE_PHY_INTR

G

BE_COL

BE_CRS

G

BE_RXERR

dd SYS BIOS ROM

CH_CRT_HPD

8

#

LD# D

@R36

@

R3

6

E

8

VCC

6

K

SCL

5

SI

2

SO

@C23

@

1 2

10_0402_5%

1 2

R

891 10K_0402_5%

1 2

R

892 10K_0402_5%

1 2

R893 10K_0402_5%R893 10K_0402_5%

1 2

R

894 10K_0402_5%

1 2

895 10K_0402_5%

R

+

FCH_VDDAN_33_DAC_R

12

R

90410K_0402_5%

@

C

@

H_SPI_CLK

FC FCH_ FCH_

3

C2

10P_0402_50V8J

4660.1U_0402_16V4Z

12

SPI_MOSI SPI_MISO

+3

VALW

+3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal E

Hudson-M2/M3-S

QB

L50 LA-7551P

lectronics, Inc.

ATA/GBE/HWM

15 53Wednesday, April 27, 2011

E

1.0

A

Dr-Bios.com

STRA

P PINS

B

C

D

E

R 909 10K_0402_5%R909 10K_0402_5%

12

R

R 920 10K_0402_5%

920 10K_0402_5%

12

_PWM2

EC

LPC ROM

DEFAULT

SPI ROM

12

@

CI_CLK1

P

1 1

2 2

PCI_CLK113

P

L

EC_

RTC_CLK13,36

PU HIGH

PU LOW

CI_CLK313

CI_CLK413

PC_CLK0_EC13,36

PC_CLK113

PWM214

ALLOW

LL

P

CIE GEN2

DE

FAULT

ORCE

F

LL

P

CIE GEN1

@

DEBUG STRA

12

R 905 10K_0402_5%R905 10K_0402_5%

R

R 915 10K_0402_5%

915 10K_0402_5%

CI_CLK3

P

USE DEBUG STRAPS

GNORE

I DEBUG STRAP

FAULT

DE

@

12

R906 10K_0402_5%@R906 10K_0402_5%

R917 10K_0402_5%R917 10K_0402_5%

PS

P

NON_FUSION CLOCK MODE

FUSI CLOCK MODE

DE

CI_CLK4 LPC_CLK0

EC ENABLED

ON

EC DI

SABLED

FAULT

@

R

R 907 10K_0402_5%

907 10K_0402_5%

12

R 918 10K_0402_5%R918 10K_0402_5%

12

FAULT

DE

R

R 908 10K_0402_5%

908 10K_0402_5%

12

@

R 919 10K_0402_5%R919 10K_0402_5%

12

CLKGEN ENABLED

DE

FAULT

KGEN

CL DISABLE

@

FCH HAS 15K INTERNAL PU FOR PCI_AD[27: 23]

3 3

PU HIGH

PULL LOW

PC

I_AD27PCI_AD26

PLL

DISABLE ILA AUTORUN

FAULT

DE

ENABLE

A

IL AUTORUN

USE PCI

LL

PLL

FAULT

DE

BYPASS PCI

PC

I_AD25 PCI_AD24

USE FC PLL

FAULT

DE

BYPASS FC PLL

USE DEFAULT PCIE STRAPS

DE

USE EEPROM PCI

FAULT

E STRAPS

PC

I_AD23

DISABLE PCI MEM BOOT

FAULT

DE

ENABLE PCI MEM BOOT

R

R 910 10K_0402_5%

910 10K_0402_5%

R

R 921 2.2K_0402_5%

921 2.2K_0402_5%

C_CLKLPC_CLK1

RT

S5 PLUS MODE DISABLED

DE

FAULT

S5 PLUS MODE ENABLED

+3VALW+3VALW+3VALW+3VALW+3VS+3VS+3VS

12

@

R 911 10K_0402_5%R911 10K_0402_5%

R

R 922 2.2K_0402_5%

922 2.2K_0402_5%

S

+3V

AP2301GN-HF_SOT23-3

1VS

+1.

AP2301GN-HF_SOT23-3

VGA_PD: Support MLDAC power save if not conne ct 0: MLDAC power on 1: MLDAC power off

Check VGA_PD states

A_PD14

VG

If support ML DAC power down when no VGA plug

L47

1 2

FB

MA-L11-201209-221LMA30T_0805

220 ohm

9

@Q39

@

Q3

3 1

2

A_PD#

VG

@Q40

@

A_PD#

VG

AO3413 Vgs(max)=1V

1 2

912 0_0402_5%

R

0

Q4

3 1

2

R923

1K_0402_5%

@

1 2

925

1212

R

C

2.2K_0402_5%

C

1 2

FB

MA-L11-201209-221LMA30T_0805

1 2

R

913 0_0402_5%

@

1 2

1U_0402_6.3V6K

30m

+FCH_VDDAN_33_D

@

1 2

220 ohm

@

0_0402_5%

R924

5

1

2

L48

12

34

il

AC

30mil

R916

100K_0402_5%

Q41B

DMN66D0LDW-7_SOT363-6

+FCH_VDDAN_33_D

C1210

C1209

1

2

2.2U_0603_6.3V4Z

+FCH_VDDAN_11_M

+3V

S

R914

100K_0402_5%

12

1U_0402_6.3V6K

C1211

1

@

2

AC_R

1

2

0.1U_0402_16V4Z

LDAC

VGA_PD#

Q41A

DMN66D0LDW-7_SOT363-6

61

2

PCI_AD2713

PCI_AD2613

PCI_AD2513

PCI_AD2413

PCI_AD2313

R

4 4

R 926 2.2K_0402_5%

926 2.2K_0402_5%

12

@

R

R 927 2.2K_0402_5%

927 2.2K_0402_5%

12

@

R928 2.2K_0402_5%@R928 2.2K_0402_5%

12

@

R

R 929 2.2K_0402_5%

929 2.2K_0402_5%

12

@

A

B

R

R 930 2.2K_0402_5%

930 2.2K_0402_5%

12

@

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/08/04 2011/12/31

pal Secret Data

Com

Deciphered Date

lectronics, Inc.

Compal E

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal E

Hudson-M2/M3-S

QB

L50 LA-7551P

lectronics, Inc.

TRAP

16 53Wednesday, April 27, 2011

E

1.0

Asus K43T,K43TA,K43TK,K43TY Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual