Asus K43T Schematic Rev1.0
A
Dr-Bios.com
1 1
B
C
D
E
Compal Confidential
2 2
QBL60 Schematics Document
AMD Sabine
APU Llano / Hudson M2_M3 / Vancouver Whistler
UMA only / PX Muxless with BACO
3 3
2010-04-25
LA-7552P REV: 1.0
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
QBL60 LA-7552P
E
1 53Monday, April 25, 2011
1.0
A
Dr-Bios.com
Compal Confidential
Model Name : QBL60
B
C
D
E
1 1
VRAM 1G/2G
128M16 x 4/8
page 23, 24
Sabine
DDR3
Thermal Sensor
ADM1032
page 19
Vancuver Whistler
ATI
uFCBGA-962
Page 18~22
GFX x 4
APU HDMI
(UMA / Muxless)
DP x1 (DP0 TXP/N0)
Gen2GFX x 8
AMD FS1 APU
Llano
uPGA-722 Package
Memory BUS(DDR3)
Dual Channel
1.5V DDRIII 800~1333MHz
204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
Page 11,12
HDMI Conn.
page 28
2 2
LVDS Conn.
page 27
LVDS
CRT Conn.
page 27
Travis LVDS
Translator
page 26
FCH CRT (VGA DAC)
GPP0GPP1
P_GPP x 2
GEN1
DP x 4
(DP1 TXP/N 0~4)
Hudson-M2/M3
uFCBGA-656
MINI Card 1
WLAN
3 3
page 32
LAN(GbE)
RTL8111E-VL
RJ45
page 29
page 29
Page 6~10
FCH
Page 13~17
UMI
LPC BUS
USB2
page 34
USB
3.3V 48MHz
HD Audio
S-ATA
Gen2
port 0
SATA HDD1
Conn.
page 33
USB2
page 34 page 27
Port 0 Port 1
3.3V 24.576MHz/48Mhz
USB2
(LS-7322P)
page 30
Port 10
CMOS
Camera
ODD
Conn.
page 33
Mini Card
(with BT)
Port2 Port 3
port 1
HDA Codec
ALC269
page 32
Card Reader
RTS5137
page 31
Port 4
page 30
ENE KB930
page 36
Touch Pad Int.KBD
LED
page 37
RTC CKT.
4 4
page 13
DC/DC
Interface CKT.
page 38
External board
LS-7326P
Power/B
page 35
BIOS ROM
LS-7322P
Power Circuit
page 39~49
A
Audio BD
page 30
EC BIOS (2M)
page 35
B
page 37
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
page 37
Compal Secret Data
Deciphered Date
D
Date: Sheet of
Title
Size Document Number Rev
B
Compal Electronics, Inc.
Block Diagrams
QBL60 LA-7552P
2 53Monday, April 25, 2011
E
1.0
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Dr-Bios.com
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2
1
CLOCK DISTRIBUTION
DISPLAY DISTRIBUTION
: LVDS PATH
D D
B_SODIMM
A_SODIMM
AMD
MEM_MA_CLK7_P/N
MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N
1066~1600MHz
C C
AMD
CPU FS1 SOCKET
DP0_AUX
MEM_MA_CLK1_P/N
1066~1600MHz
APU_DISP_CLKP/N
100MHz
APU_CLKP/N
100MHz
LVDS Transtator
ATI VGA
Whistler
CLK_PEG_VGAP/N
100MHz
AMD
FCH
Hudson-M2/M3
Internal CLK GEN
GPP_CLK
100MHz
32.768KHz 25MHz
: APU HDMI PATH
APU_TXOUT[0:2]+/APU_TXOUT_CLK+/APU_TZOUT[0:2]+/APU_TZOUT_CLK+/APU_LVDS_CLK/DATA
LVDS_OUT
RTD2132
DP_IN
C
TXOUT[0:2]+/TXCLK+/TZOUT[0:2]+/TZCLK+/I2CC_SCL/DA
LVDS CONN
R
DP0_TXP/N[0:1]
DP0_AUXP/N
B B
WLAN
GbE LAN
Mini PCI Socket
25MHz
GPP0GPP1
APU
DP1
DP0
PCIE_GFX[0:7]
PCIE_GFX[12:15]
C
C
PCIE_GFX[0:7]
VGA
FCH
R
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
2011/04/25 2012/04/25
3
Compal Secret Data
Deciphered Date
Title
CLOCK / DISPLAY DISTRIBUTION
Size Document Number Rev
Custom
QBL60 LA-7552P
2
Date: Sheet of
LS
HDMI CONNCRT CONN
3 53Monday, April 25, 2011
1
1.0
A
Dr-Bios.com
B
C
D
E
Voltage Rails
Power Plane Description
VIN
B+
+CPU_CORE
1 1
+CPU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU
+VGA_CORE OFFOFFON0.95-1.2V switched power rail
+0.75VS ONON OFF0.75V switched power rail for DDR terminator
+1.0VSG ON OFF OFF1.0V switched power rail for VGA
+1.1ALW 1.1V switched power rail for FCH ON ON*ON
+1.1VS
+1.2VS ON OFF OFF
+1.5V ON
+1.5VS
+1.8VSG OFFON OFF1.8V switched power rail
+2.5VS
+3VALW
+LAN_IO ON ON ON
+3VS
+5VALW
+5VS
2 2
+VSB ON ON*
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2V switched power rail for APU
1.5V power rail for CPU VDDIO and DDR
1.5V switched power rail
2.5V for CPU_VDDA
3.3V always on power rail
3.3V power rail for LAN
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
S1 S3 S5
N/A N/A N/A
ON OFF
ON OFF OFF1.1V switched power rail for FCH
ON OFF
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
ON
OFF
OFF
OFF
ON ON*
OFF
OFF
ON
ON*
OFF
OFFON
ONON
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF) LOW
BTO Option Table
SIGNAL
BTO ItemBOM Structure
SLP_S4# SLP_S5#
SLP_S3#
HIGH HIGH HIGH
LOW
HIGH
LOW LOW
LOW
HIGHHIGHHIGH
HIGH
HIGH
LOW
+VALW +V
ON
ON
ON
ON
ON
VGA@ Use VGA (Mux)
VRAM ID TableX76@
M2@ Use Hudson-M2
M3@ Use Hudson-M3
BOM Config
USB30@ USB30 on M/B
USB20@ USB20 on M/B
+VS Clock
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
U25
M3@
FCH M3
Part Number = SA000043ID0
LOW
OFF
OFF
OFF
x = 1 is read cmd, x= 0 is writee cmd.
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
3 3
EC SM Bus1 address EC SM Bus2 address
Device Address HEX
Smart Battery
0001 011X b
FCH
SM Bus 0 address
4 4
Device Address Device Address
DDR DIMM1
DDR DIMM2
1101 000X b
1101 001X b
A
Device Address HEX
16H
ADI ADM1032 (VGA)
(APU)
RTD2132S (TL)
1001 101X b
FCH
SM Bus 1 address
HEX
D0
D2
9AH
HEX
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
B
D
Date: Sheet of
Compal Electronics, Inc.
Notes List
QBL60 LA-7552P
E
4 53Monday, April 25, 2011
1.0
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1
BATTERY
12.6V
AC ADAPTOR
D D
19V 90W
C C
B B
BATT+
VIN
PU101
CHARGER
FAN Control
APL5607
+5VS 500mA
B+
U54/U55
AP2301MPG
+INVPWR_B+
LCD panel
15.6"
B+ 300mA
+3.3 350mA
+USB_VCCA
+USB_VCCB
PU201
ISL6267HRZ-T
PU501
RT8209MGQW
PU801
RT8209MGQW
PU901
RT8237CZQW
PU701
RT8209MGQW
PU301
RT8205LZQW
+3VS
+5VS
+CPU_CORE
+CPU_CORE_NB
+1.5V
+1.2VS
+VGA_CORE
+1.1VALW
+3VALW
+5VALW
+5VALW
+3VS
U33
SI4800
+2.5VS
PU603
APL5508-25DC
U40
SI4800
PU602
APL5930KAI
U41
AO4430L
PU401
SY8033BDBC
PU601
APL5336KAI
+1.0VSG
+1.5VSG
+1.8VSG
PJ14
U39
AO4430L
+0.75VS
+3VSG
+1.1VS
+CPU_CORE
+CPU_CORE_NB
+2.5VS
+1.5V
+1.2VS
+0.75VS
+VGA_CORE
+VDDCI
+1.0VSG
+1.5VSG
+1.8VSG
+3VSG
+1.1VS
+1.1VALW
+3VS
USB X3
+5V
Dual+1
2.5A
SATA
HDD*2
ODD*1
+5V 3A
+3.3V
A A
Audio Codec
ALC269-GR
+5V 45mA
+3.3VS 25mA
EC
ENE KB930
+3.3VALW 30mA
+3.3VS 3mA
+3VALW
LAN
RTL8111E
+3.3VALW 201mA
+1.5VS
Mini Card
+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA
RTC
Bettary
+3VALW
AMD APU FS1
0.7~1.475V
0.7~1.475V
+2.5VS
+1.5V
+1.2VS
VDD CORE 54A
VDDNB 27.5A
VDDA 500mA
VDDIO 4.6A
VDDR 6.7A
RAM DDRIII SODIMMX2
+1.5V
+0.75VS
0.85~1.1V
0.9~1.0V
+1.0VSG
+1.5VSG
+1.8VSG
+3VSG
VDD_MEM 4A
VTT_MEM 0.5A
VGA ATI
Whistler/Seymour/Granville
VDDC 47A
VDDCI 4.6A
DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VDDR1: 3400 mA
PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
A2VDD: 130 mA
VDDR3: 60 mA
FCH AMD Hudson M2/M3
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
+1.1VS
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
+1.1VALW
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA
VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
+3VS
VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA
VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
+3VALW
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA
VDDIO_33_GBE_S
VDDCR_11_GBE_S
GND
VDDIO_GBE_S
RTC BAT
VDDBT_RTC_G
VRAM 1GB/2GB
64M / 128Mx16 * 4 / 8
+1.5VSG 2.4 A
5
4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
3
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
2
Title
POWER DELIVERY CHART
Size Document Number Rev
Custom
QBL60 LA-7552P
Date: Sheet of
1
5 53Monday, April 25, 2011
1.0
C
Dr-Bios.com
PCIE_FTX_C_GRX_P[0..7] 18
PCIE_FTX_C_GRX_N[0..7] 18
2
2
2
2
2
2
2
2
PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7
For UMA Mux.
2
1
To HDMI
0
CK
2
2
2
2
2
2
2
2
PCIE_FTX_C_DRX_P0 29
PCIE_FTX_C_DRX_N0 29
PCIE_FTX_C_DRX_P1 32
PCIE_FTX_C_DRX_N1 32
UMI_FTX_C_MRX_P0 13
UMI_FTX_C_MRX_N0 13
UMI_FTX_C_MRX_P1 13
UMI_FTX_C_MRX_N1 13
UMI_FTX_C_MRX_P2 13
UMI_FTX_C_MRX_N2 13
UMI_FTX_C_MRX_P3 13
UMI_FTX_C_MRX_N3 13
GLAN
WLAN
GPPUMI-LINK GRAPHICS
B
CONN@
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
P_ZVSS
PCIE_FTX_GRX_P0
AA2
PCIE_FTX_GRX_N0
AA3
PCIE_FTX_GRX_P1
Y2
PCIE_FTX_GRX_N1
Y1
PCIE_FTX_GRX_P2
Y4
PCIE_FTX_GRX_N2
Y5
PCIE_FTX_GRX_P3
W2
PCIE_FTX_GRX_N3
W3
PCIE_FTX_GRX_P4
V2
PCIE_FTX_GRX_N4
V1
PCIE_FTX_GRX_P5
V4
PCIE_FTX_GRX_N5
V5
PCIE_FTX_GRX_P6
U2
PCIE_FTX_GRX_N6
U3
PCIE_FTX_GRX_P7
T2
PCIE_FTX_GRX_N7
T1
T4
T5
R2
R3
P2
P1
P4
P5
PCIE_FTX_GRX_P12
N2
PCIE_FTX_GRX_N12
N3
PCIE_FTX_GRX_P13
M2
PCIE_FTX_GRX_N13
M1
PCIE_FTX_GRX_P14
M4
PCIE_FTX_GRX_N14
M5
PCIE_FTX_GRX_P15
L2
PCIE_FTX_GRX_N15
L3
PCIE_FTX_DRX_P0
AD4
PCIE_FTX_DRX_N0
AD5
PCIE_FTX_DRX_P1
AC2
PCIE_FTX_DRX_N1
AC3
AB2
AB1
AB4
AB5
UMI_FTX_MRX_P0
AF1
UMI_FTX_MRX_N0
AF2
UMI_FTX_MRX_P1
AF5
UMI_FTX_MRX_N1
AF4
UMI_FTX_MRX_P2
AE3
UMI_FTX_MRX_N2
AE2
UMI_FTX_MRX_P3
AD1
UMI_FTX_MRX_N3
AD2
P_ZVSS
K4
C917 0.1U_0 402_16V7KVGA@
C918 0.1U_0 402_16V7KVGA@
C919 0.1U_0 402_16V7KVGA@
C920 0.1U_0 402_16V7KVGA@
C921 0.1U_0 402_16V7KVGA@
C922 0.1U_0 402_16V7KVGA@
C923 0.1U_0 402_16V7KVGA@
C924 0.1U_0 402_16V7KVGA@
C925 0.1U_0 402_16V7KVGA@
C926 0.1U_0 402_16V7KVGA@
C927 0.1U_0 402_16V7KVGA@
C928 0.1U_0 402_16V7KVGA@
C929 0.1U_0 402_16V7KVGA@
C930 0.1U_0 402_16V7KVGA@
C931 0.1U_0 402_16V7KVGA@
C932 0.1U_0 402_16V7KVGA@
2
1
R540 196_0402_1%
1
1
1 2
1
1 2
1 2
1 2
1 2
1
1
1
1 2
1
1
1 2
1 2
C950 0.1U_0402_16V7K
1
C951 0.1U_0402_16V7K
1 2
C952 0.1U_0402_16V7K
1
C953 0.1U_0402_16V7K
1
C956 0.1U_0402_16V7K
1 2
C957 0.1U_0402_16V7K
1
C958 0.1U_0402_16V7K
1 2
C959 0.1U_0402_16V7K
1
C960 0.1U_0402_16V7K
1
C961 0.1U_0402_16V7K
1
C962 0.1U_0402_16V7K
1 2
C963 0.1U_0402_16V7K
1
A
PCIE_GTX_C_FRX_P[0..7]18
PCIE_GTX_C_FRX_N[0..7]18
JCPU1A
PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
1 1
2 2
PCIE_DTX_C_FRX_P029
3 3
4 4
PCIE_DTX_C_FRX_N029
PCIE_DTX_C_FRX_P132
PCIE_DTX_C_FRX_N132
UMI_MTX_C_FRX_P013
UMI_MTX_C_FRX_N013
UMI_MTX_C_FRX_P113
UMI_MTX_C_FRX_N113
UMI_MTX_C_FRX_P213
UMI_MTX_C_FRX_N213
UMI_MTX_C_FRX_P313
UMI_MTX_C_FRX_N313
+1.2VS
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7
1 2
R539 196_0402_1%
P_ZVDDP
AA8
AA9
Y7
Y8
W5
W6
W8
W9
V7
V8
U5
U6
U8
U9
T7
T8
R5
R6
R8
R9
P7
P8
N5
N6
N8
N9
M7
M8
L5
L6
L8
L9
AC5
AC6
AC8
AC9
AB7
AB8
AA5
AA6
AF8
AF7
AE6
AE5
AE9
AE8
AD8
AD7
K5
AMD_TOPEDO_FS-1
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3
P_ZVDDP
PCI EXPRESS
D
APU To HDMI
CPU TSI interface level shift
C935 0.1U_0402_16V4Z
1 2
R535
2
1
+3VS
31.6K_0402_1%
APU_SID8,14
APU_SIC8,14
APU_SID
BSH111 1N_SOT23-3
APU_SIC
BSH111 1N_SOT23-3
G
S
G
S
1 2
30K_0402_1%
2
Q9
13
D
2
Q10
13
D
Power Sequence of APU
+1.5V
+2.5VS
+1.5VS
+CPU_CORE
+CPU_CORE_NB
+1.2VS
R536
EC_SMB_DA
EC_SMB_CK
PCIE_FTX_GRX_P[12..15] 28
PCIE_FTX_GRX_N[12..15] 28
R537
1 2
0_0402_5%
R538
1 2
0_0402_5%
E
BSH111, the Vgs is:
min = 0.4V
Max = 1.3V
EC_SMB_DA2 19,36
To EC
EC_SMB_CK2 19,36
Group A
Group B
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Rev
Custom
Date: Sheet of
Compal Electronics, Inc.
AMD FS1 PCIE / UMI / TSI
QBL60 LA-7552P
E
6 53Monday, April 25, 2011
1.0
C
Dr-Bios.com
DDRB_SMA[15..0]12
DDRB_SBS0#12
DDRB_SBS1#12
DDRB_SBS2#12
DDRB_SDM[7..0]12
DDRB_SDQS012
DDRB_SDQS0#12
DDRB_SDQS112
DDRB_SDQS1#12
DDRB_SDQS212
DDRB_SDQS2#12
DDRB_SDQS312
DDRB_SDQS3#12
DDRB_SDQS412
DDRB_SDQS4#12
DDRB_SDQS512
DDRB_SDQS5#12
DDRB_SDQS612
DDRB_SDQS6#12
DDRB_SDQS712
DDRB_SDQS7#12
DDRB_CLK012
DDRB_CLK0#12
DDRB_CLK112
DDRB_CLK1#12
DDRB_CKE012
DDRB_CKE112
DDRB_ODT012
DDRB_ODT112
DDRB_SCS0#12
DDRB_SCS1#12
DDRB_SRAS#12
DDRB_SCAS#12
DDRB_SWE#12
MEM_MB_RST#12
MEM_MB_EVENT#12
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE0
DDRB_CKE1
DDRB_ODT0
DDRB_ODT1
DDRB_SCS0#
DDRB_SCS1#
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
MEM_MB_RST#
MEM_MB_EVENT#
CONN@
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
B
E13
J13
H15
J15
H13
F13
F15
E15
H17
F17
E19
J19
G16
H16
H19
F19
H20
F21
J23
H23
G20
E20
G22
H22
G24
E25
G27
G26
F23
H24
E28
F27
AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25
Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21
AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17
AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ[63..0] 11
A
1 1
JCPU1B
DDRA_SMA[15..0]11
DDRA_SBS0#11
DDRA_SBS1#11
DDRA_SBS2#11
DDRA_SDM[7..0]11
2 2
DDRA_SDQS011
DDRA_SDQS0#11
DDRA_SDQS111
DDRA_SDQS1#11
DDRA_SDQS211
DDRA_SDQS2#11
DDRA_SDQS311
DDRA_SDQS3#11
DDRA_SDQS411
DDRA_SDQS4#11
DDRA_SDQS511
DDRA_SDQS5#11
DDRA_SDQS611
DDRA_SDQS6#11
DDRA_SDQS711
DDRA_SDQS7#11
DDRA_CLK011
DDRA_CLK0#11
DDRA_CLK111
DDRA_CLK1#11
DDRA_CKE011
DDRA_CKE111
DDRA_ODT011
DDRA_ODT111
3 3
DDRA_SCS0#11
DDRA_SCS1#11
DDRA_SRAS#11
DDRA_SCAS#11
DDRA_SWE#11
MEM_MA_RST#11
MEM_MA_EVENT#11
+MEM_VREF
+1.5V
Place them close to APU within 1"
Place them close to APU within 1"
Place them close to APU within 1"Place them close to APU within 1"
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE0
DDRA_CKE1
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1#
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
MEM_MA_RST#
MEM_MA_EVENT#
15mil
1 2
R541 39.2_0402_1%
M_ZVDDIO
U20
MA_ADD0
R20
MA_ADD1
R21
MA_ADD2
P22
MA_ADD3
P21
MA_ADD4
N24
MA_ADD5
N23
MA_ADD6
N20
MA_ADD7
N21
MA_ADD8
M21
MA_ADD9
U23
MA_ADD10
M22
MA_ADD11
L24
MA_ADD12
AA25
MA_ADD13
L21
MA_ADD14
L20
MA_ADD15
U24
MA_BANK0
U21
MA_BANK1
L23
MA_BANK2
E14
MA_DM0
J17
MA_DM1
E21
MA_DM2
F25
MA_DM3
AD27
MA_DM4
AC23
MA_DM5
AD19
MA_DM6
AC15
MA_DM7
G14
MA_DQS_H0
H14
MA_DQS_L0
G18
MA_DQS_H1
H18
MA_DQS_L1
J21
MA_DQS_H2
H21
MA_DQS_L2
E27
MA_DQS_H3
E26
MA_DQS_L3
AE26
MA_DQS_H4
AD26
MA_DQS_L4
AB22
MA_DQS_H5
AA22
MA_DQS_L5
AB18
MA_DQS_H6
AA18
MA_DQS_L6
AA14
MA_DQS_H7
AA15
MA_DQS_L7
T21
MA_CLK_H0
T22
MA_CLK_L0
R23
MA_CLK_H1
R24
MA_CLK_L1
H28
MA_CKE0
H27
MA_CKE1
Y25
MA_ODT0
AA27
MA_ODT1
V22
MA_CS_L0
AA26
MA_CS_L1
V21
MA_RAS_L
W24
MA_CAS_L
W23
MA_WE_L
H25
MA_RESET_L
T24
MA_EVENT_L
W20
M_VREF
W21
M_ZVDDIO
AMD_TOPEDO_FS-1
MEMORY CHANNEL A
D
T27
P24
P25
N27
N26
M28
M27
M24
M25
L26
U26
L27
K27
W26
K25
K24
U27
T28
K28
D14
A18
A22
C25
AF25
AG22
AH18
AD14
C15
B15
E18
D18
E22
D22
B26
A26
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14
R26
R27
P27
P28
J26
J27
W27
Y28
V25
Y27
V24
V27
V28
J25
T25
JCPU1C
MEMORY CHANNEL B
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CKE0
MB_CKE1
MB_ODT0
MB_ODT1
MB_CS_L0
MB_CS_L1
MB_RAS_L
MB_CAS_L
MB_WE_L
MB_RESET_L
MB_EVENT_L
AMD_TOPEDO_FS-1
CONN@
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
A14
B14
D16
E16
B13
C13
B16
A16
C17
B18
B20
A20
E17
B17
B19
C19
C21
B22
C23
A24
D20
B21
E23
B23
E24
B25
B27
D28
B24
D24
D26
C27
AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24
AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20
AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16
AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
E
DDRB_SDQ[63..0] 12
EVENT# pull high 0.75V reference voltage
+1.5V
4 4
R544 1K_0402_5%
1 2
R545 1K_0402_5%
2
1
MEM_MA_EVENT#
MEM_MB_EVENT# +MEM_VREF
A
R542
1K_0402_1%
R543
1K_0402_1%
+1.5V
1 2
1 2
B
1
C964
1000P_0402_50V7K
2
15mil
2
C965
0.1U_0402_16V7K
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
Custom
D
Date: Sheet of
Title
Size Document Number Rev
Compal Electronics, Inc.
AMD FS1 DDRIII I/F
QBL60 LA-7552P
7 53Monday, April 25, 2011
E
1.0
A
Dr-Bios.com
Place near APU
C971 0.1U_0402_16V7K
2
To LVDS
Translator
1 1
To FCH VGA ML
100MHz
2 2
100MHz_NSS
+1.5V
R575 1K_0402_5%
R576 1K_0402_5%
+1.5V
3 3
R579 1K_0402_5%
R581 1K_0402_5%
R791 1K_0402_5%
+1.5V
R592 1K_0402_5%
R593 1K_0402_5%
R594 1K_0402_5%
R595 1K_0402_5%
R596 300_0402_5%
Route as differential
with VSS_SENSE
APU_VDDNB_RUN_FB_L
APU_VDDNB_SEN route as differential
4 4
APU_VDD_RUN_FB_L
APU_VDD_SEN route as differential
2
1
2
1
1 2
1 2
2
1
Close to Header
2
1
2
1
2
1
1 2
2
1
DP0_TXP0_C26
DP0_TXN0_C26
ML_VGA_TXP015
ML_VGA_TXN015
ML_VGA_TXP115
ML_VGA_TXN115
ML_VGA_TXP215
ML_VGA_TXN215
ML_VGA_TXP315
ML_VGA_TXN315
APU_CLKP13
APU_CLKN13
APU_DISP_CLKP13
APU_DISP_CLKN13
APU_SVC47
APU_SVD47
Chang to PU +1.5VS (DG ref.)
20101111
APU_SVC
APU_SVD
APU_SIC
APU_SID
ALERT_L
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
APU_VDDNB_RUN_FB_ L47
APU_VDD_RUN_FB_L47
1
C973 0.1U_0402_16V7K
1 2
T25
T28
T19
T20
T21
T22
Place near APU
C977 0.1U_0402_16V7K
1 2
C968 0.1U_0402_16V7K
1 2
C969 0.1U_0402_16V7K
1 2
C970 0.1U_0402_16V7K
1 2
C978 0.1U_0402_16V7K
2
1
C979 0.1U_0402_16V7K
2
1
C980 0.1U_0402_16V7K
2
1
C981 0.1U_0402_16V7K
1 2
APU_CLKP
APU_CLKN
APU_DISP_CLKP
APU_DISP_CLKN
APU_SVC
APU_SVD
APU_SIC6,14
TSI
APU_SID6,14
APU_RST#13
APU_PWRGD13
Serial VID
R597 0_0402_5%
R600 0_0402_5%
APU_VDDNB_SEN47
APU_VDD_SEN47
1 2
1 2
DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_TXP2
DP0_TXN2
DP0_TXP3
DP0_TXN3
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
APU_SIC
APU_SID
APU_RST#
APU_PWRGD
APU_PROCHOT#
APU_THERMTRIP#
ALERT_L
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
APU_VDDNB_SEN
APU_VDD_SEN
B
JCPU1D
F2
DP0_TXP0
F1
DP0_TXN0
E3
DP0_TXP1
E2
DP0_TXN1
D2
DP0_TXP2
D1
DP0_TXN2
C2
DP0_TXP3
C3
DP0_TXN3
K2
DP1_TXP0
K1
DP1_TXN0
J3
DP1_TXP1
J2
DP1_TXN1
H2
DP1_TXP2
H1
DP1_TXN2
G2
DP1_TXP3
G3
DP1_TXN3
AH7
CLKIN_H
AH6
CLKIN_L
AH4
DISP_CLKIN_H
AH3
DISP_CLKIN_L
B8
SVC
A8
SVD
AH11
SIC
AG11
SID
AF10
RESET_L
AE10
PWROK
AD10
PROCHOT_L
AG12
THERMTRIP_L
AH12
ALERT_L
C12
TDI
A12
TDO
A11
TCK
D12
TMS
B12
TRST_L
B11
DBRDY
C11
DBREQ_L
E8
RSVD_1
K21
RSVD_2
AC11
RSVD_3
B9
VSS_SENSE
C8
VDDP_SENSE
A9
VDDNB_SENSE
B10
VDDIO_SENSE
C9
VDD_SENSE
A10
VDDR_SENSE
AMD_TOPEDO_FS-1
DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE
System DP
DP0_AUXP
DP0_AUXN
DP1_AUXP
DP1_AUXN
DP2_AUXP
DP2_AUXN
DP3_AUXP
DP3_AUXN
DP4_AUXP
DP4_AUXN
DP5_AUXP
DP5_AUXN
DP0_HPD
DP1_HPD
DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD
DP_BLON
DP_DIGON
DP_VARY_BL
DP_AUX_ZVSS
TEST DISPLAY PORT MISC.
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
TEST32_H
TEST32_L
DMAACTIVE_L
THERMDA
THERMDC
CONN@
TEST6
TEST9
TEST10
TEST12
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST20
TEST21
TEST22
TEST23
TEST24
TEST31
TEST35
FS1R1
D4
D5
E5
E6
J5
J6
H4
H5
G5
G6
F4
F5
D7
E7
J7
H7
G7
F7
C6
C5
C7
D8
AA10
G10
H10
H12
D9
E9
G9
H9
H11
G11
F12
E11
D11
F10
G12
AH10
AH9
K7
K8
AA12
AB12
K22
AB11
AA11
D10
Y11
AB10
AE12
AD12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
Place near APU
DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN
APU_HDMI_CLK
APU_HDMI_DATA
C972 0.1U_0402_16V7K
2
1
C974 0.1U_0402_16V7K
1 2
C975 0.1U_0402_16V7K
2
1
C976 0.1U_0402_16V7K
1 2
APU_HDMI_CLK 28
APU_HDMI_DATA 28
DP0_HPD
DP1_HPD
DP5_HPD
DP_ENBKL
DP_ENVDD
DP_INT_PWM
DP_AUX_ZVSS
T6
T7
T8
T9
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST21
APU_TEST22
T10
APU_TEST24
TEST25_H
TEST25_L
T11
T12
M_TEST
T13
T14
TEST35
FS1R1
ALLOW_STOP
T15
T16
Llano do not support this thermal die
DP0_HPD 10
DP1_HPD 10
DP5_HPD 10
DP_ENBKL 10
DP_ENVDD 10
DP_INT_PWM 10
R569 150_0402_1%
1 2
Chang to unpop (DG ref.)
20101111
R573 0_0402_5%@
R574 1K_0402_5%
R582 1K_0402_5%
R583 1K_0402_5%
R584 1K_0402_5%
R585 1K_0402_5%
R589 1K_0402_5%
R590 1K_0402_5%
C639 0.1U_0402_16V4Z
1
1
1
1
1 2
1
1
1
ALLOW_STOP 13
2
1
@
2
2
2
2
2
2
2
2011/04/25 2012/04/25
C
DP0_AUXP_C 26
DP0_AUXN_C 26
ML_VGA_AUXP_C 15
ML_VGA_AUXN_C 15
LVDS
CRT
HDMI
HDT Debug conn
Compal Secret Data
AUX 2~5 are for GFX interface
use, they could be selected to I2C
or AUX logic
VDDIO level
Need Level shift
VDDIO level
Need Level shift
VDDIO level
Need Level shift
APU_TRST#
R598 0_0402_5%
R601 10K_0402_5%
R603 10K_0402_5%
R605 10K_0402_5%
Deciphered Date
D
To LVDS
Translator
To FCH
Asserted as an input to force the
processor into the HTC-active state
APU_PROCHOT#
THERMTRIP shutdown
temperature: 125 degree
APU_THERMTRIP#
+1.5V
2
1
1 2
1 2
1 2
D
If not used, pins are left unconnected (DG ref.)
20101111
DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN
TEST25_L
TEST25_H
TEST35
M_TEST
FS1R1
FS1R1 : Control S5 Dual PWR plane
In laptop, seems no use
ALLOW_STOP
MISC
R586
1K_0402_5%
1 2
+1.5V
R610
1K_0402_5%
1 2
MMBT3904_NL_SOT23-3
JP1
1
1
3
3
5
5
7
7
9
10
9
11
12
11
13
14
13
15
16
15
17
18
17
19
20
19
SAMTE_ASP-136446-07-B
CONN@
Title
Size Document Number Rev
Custom
Date: Sheet
APU_RST#
APU_PWRGD
10K_0402_5%
R591
1
0_0402_5%
12
10K_0402_5%
B
2
E
3 1
2
2
4
4
6
6
8
8
10
12
14
16
18
20
Q11
2
MMBT3904_NL_SOT23-3
Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately
R609
Q12
R611
1
C
0_0402_5%
APU_TCK
APU_TMS
APU_TDI
APU_TDO
APU_DBRDY
APU_DBREQ#
R606 0_0402_5%
1
R608 0_0402_5%
1 2
Compal Electronics, Inc.
AMD FS1 Display / MISC / HDT
QBL60 LA-7552P
E
R554 1.8K_04 02_5%
R555 1.8K_04 02_5%
R547 1.8K_04 02_5%
R556 1.8K_04 02_5%
R548 510_0402_1%
R557 510_0402_1%
R558 300_0402_5%
R559 300_0402_5%
R564 39.2_0402_1%@
R567 39.2_0402_1%
R571 10K_0402_5%
R612 1K_0402_5%
R577 1K_0402_5%
R578 300_0402_5%
R580 300_0402_5%
+3VS+1.5V
12
R587
2
B
E
31
C
2
2
2
2
1 2
1
1
1 2
@
1 2
1 2
1 2
1
1 2
@
1 2
1
12
R588
10K_0402_5%
12
1
1
1
2
2
2
2
H_THERMTRIP# 14
Cut on CPU side, Debug mount
R599 0_0402_5%@
R602 0_0402_5%@
2
1
2
1
APU_TEST19
2
APU_TEST18
8 53Monday, April 25, 2011
E
+1.2VS
+1.5V
+1.5V
+3VALW
+1.5V
+1.5VS
EC_THERM# 13,36,47
APU_PWRGD
APU_RST#
1.0
of
JCPU1F
Dr-Bios.com
A7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B7
VSS
C4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E4
VSS
VSS
VSS
F9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J4
VSS
J8
VSS
VSS
VSS
VSS
VSS
VSS
L4
VSS
L7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
T9
VSS
AMD_TOPEDO_FS-1
E
CONN@
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDP
10uF x 3
0.22uF x 2
180pF x 2
E
T11
T19
U4
U7
U10
U18
V9
V11
V19
W4
W7
W10
W12
W14
W16
W18
Y9
Y22
AA4
AA7
AB9
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AC4
AC7
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AD9
AD11
AE4
AE7
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE27
AF3
AF6
AF9
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AH5
AH8
AH13
AH15
AH17
AH19
AH21
AH23
AH25
VDDR
4.7uF x 4
0.22uF x 4
1nF x 4
180pF x 4
9 53Monday, April 25, 2011
of
1.0
0.01U_0402_16V7K
0.22U_0603_16V4Z
C991
180P_0402_50V8J
1
2
C1024
180P_0402_50V8J
1
2
CORE_NB
470uF x 4
22uF x 6
0.22uF x 2
180uF x 3
D
C992
1
2
+CPU_CORE
C1025
1
2
D
C993
180P_0402_50V8J
1
+
2
C1014
180P_0402_50V8J
C5
390U_2.5V_10M
C994
390U_2.5V_10M
1
+
2
390U_2.5V_10M
C1015
1
1
+
2
2
330U_D2_2V_Y
1
+
2
VDDIO_SUS
(CPU side)
680uF x 1
330uF x 1
22uF x 3
4.7uF x 4
0.22uF x 6
180pF x 4
C999
390U_2.5V_10M
1
+
2
390U_2.5V_10M
+
VDDIO_SUS
(DIMM x2)
100uF x 4
0.1uF
Title
AMD FS1 PWR / GND
Size Document Number Rev
Custom
QBL60 LA-7552P
Date: Sheet
A13
A15
A17
A19
A21
A23
A25
C10
C14
C16
C18
C20
C22
C24
C26
C28
D13
D15
D17
D19
D21
D23
D25
D27
E10
E12
F11
F14
F16
F18
F20
F22
F24
F26
F28
G4
G8
G13
G15
G17
G19
G21
G23
G25
J18
J20
J22
J24
K19
L10
M9
M11
M19
N4
N7
N10
N18
P11
P19
R4
R7
R10
R18
VDDP/R_PWM
470uF x 2
10uF x 1
Compal Electronics, Inc.
C
C986
22U_0805_6.3V6M
C985
C984
22U_0805_6.3V6M
1
2
C1003
22U_0805_6.3V6M
1
2
4.7U_0603_6.3V6K
C15
1
2
C1030
180P_0402_50V8J
1
2
Decoupling betw een CPU and DI MMs
across VDDIO an d VSS split
+1.2VS
0.22U_0603_16V4Z
C1037
1
1
2
2
1000P_0402_50V7K
C1050
1
1
2
2
4.7U_0603_6.3V6K
C12
1
1
2
2
22U_0805_6.3V6M
C997
22U_0805_6.3V6M
1
2
C1004
0.22U_0603_16V4Z
1
2
4.7U_0603_6.3V6K
C16
1
2
0.22U_0603_16V4Z
1000P_0402_50V7K
C1051
4.7U_0603_6.3V6K
C13
1
2
C1005
0.22U_0603_16V4Z
1
2
4.7U_0603_6.3V6K
C17
1
2
+1.2VS
1
+
2
1000P_0402_50V7K
+1.2VS
1
2
4.7U_0603_6.3V6K
2
1
1
2
C1006
180P_0402_50V8J
1
2
C1018
0.22U_0603_16V4Z
1
2
C1038
220U_6.3V_M
C1038 change to SF000002Y00
20101228
2011/04/25 2012/04/25
C
C987
0.22U_0603_16V4Z
C989
0.01U_0402_16V7K
C988
0.22U_0603_16V4Z
1
2
C1007
1
2
C1019
0.22U_0603_16V4Z
1
2
1
1
2
2
C1008
180P_0402_50V8J
180P_0402_50V8J
C1009
1
1
+
2
2
C1021
C1020
0.22U_0603_16V4Z
1
1
2
2
C990
C998
0.01U_0402_16V7K
1
1
2
2
390U_2.5V_10M
C1022
0.22U_0603_16V4Z
0.22U_0603_16V4Z
C1023
1
1
2
2
Demo Board Capacitor (include PWM side)
CPU_CORE
470uF x 6
22uF x 9
0.22uF x 2
180pF x 2
10nF x 3
Compal Secret Data
Deciphered Date
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
2000mil2000mil
T6
T10
T18
U1
U11
U19
V3
V6
V10
V18
W1
W11
W13
W15
W17
W19
Y3
Y6
Y10
Y12
Y14
Y16
Y18
Y20
AA1
AB3
AB6
AC1
AD3
AD6
AE1
K11
K12
K13
K14
K16
K17
K18
L18
R22
R25
R28
T20
T23
T26
U22
U25
U28
V20
V23
V26
W22
W25
W28
Y24
Y26
AA28
A3
A4
B3
B4
A5
A6
B5
B6
B
+CPU_CORE
900mil900mil
160mil160mil
120mil120mil
160mil160mil
+CPU_CORE_NB
+1.5V
VDDP decoupling
10U_0603_6.3V6M
C7
C8
1
1
2
2
VDDR decoupling
180P_0402_50V8J
C1044
C1045
1
1
2
2
C1052
0.22U_0603_16V4Z
C1053
1
1
2
2
CPU BOTTOM SIDE DECOUPLING
+CPU_CORE
C983
C982
+CPU_CORE_NB
C1000
+1.5V
C1012
+1.5V
C1027
10U_0603_6.3V6M
10U_0603_6.3V6M
C6
1
2
180P_0402_50V8J
180P_0402_50V8J
C1046
1
2
C1054
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
2
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
1
2
22U_0805_6.3V6M
1
2
0.22U_0603_16V4Z
1
2
C1034
1
2
C1047
1
2
C1055
1
2
22U_0805_6.3V6M
C996
22U_0805_6.3V6M
1
1
2
2
C1002
22U_0805_6.3V6M
C1001
22U_0805_6.3V6M
1
1
2
2
4.7U_0603_6.3V6K
C1013
22U_0805_6.3V6M
C14
1
1
2
2
C1029
180P_0402_50V8J
C1028
0.22U_0603_16V4Z
1
1
2
2
180P_0402_50V8J
180P_0402_50V8J
C1035
C1036
1
2
1000P_0402_50V7K
180P_0402_50V8J
C1048
C1049
1
2
4.7U_0603_6.3V6K
0.22U_0603_16V4Z
C10
C11
1
2
A
Power Name
VDD
+CPU_CORE
VDDNB
+CPU_CORE_NB
VDDIO
+1.5V
VDDP / VDDR
+1.2VS
VDDA
1 1
+2.5VS
CORE_NB
330uF X 2
22uF X 4
2 2
3 3
+2.5VS
4 4
Consumption
50A
22.5A
4A
3A / 3.5A
0.75A
CPU_CORE
330uF X 4
22uF X 11
+CPU_CORE_NB
L1
FBMA-L11-201209-221LMA30T_0805
2
1
C1040
3300P_0402_50V7K
C1041
1
12
2
+CPU_CORE
+1.5V
+1.2VS
+1.2VS
40mil
+VDDA_APU
C1043
180P_0402_50V8J
4.7U_0805_10V4Z
0.22U_0603_16V4Z
C18
1
1
@
2
2
C18 & C1043 follow AMD request
201012061900
JCPU1E
C1
VDD
D3
VDD
D6
VDD
E1
VDD
F3
VDD
F6
VDD
F8
VDD
G1
VDD
H3
VDD
H6
VDD
H8
VDD
J1
VDD
K3
VDD
K6
VDD
L1
VDD
L11
VDD
L19
VDD
M3
VDD
M6
VDD
M10
VDD
M18
VDD
N1
VDD
N11
VDD
N19
VDD
P3
VDD
P6
VDD
P10
VDD
P18
VDD
R1
VDD
R11
VDD
R19
VDD
T3
VDD
J9
VDDNB
J10
VDDNB
J11
VDDNB
J12
VDDNB
J14
VDDNB
J16
VDDNB
K9
VDDNB
K10
VDDNB
G28
VDDIO
H26
VDDIO
J28
VDDIO
K20
VDDIO
K23
VDDIO
K26
VDDIO
L22
VDDIO
L25
VDDIO
L28
VDDIO
M20
VDDIO
M23
VDDIO
M26
VDDIO
N22
VDDIO
N25
VDDIO
N28
VDDIO
P20
VDDIO
P23
VDDIO
P26
VDDIO
AG2
VDDP_A_1
AG3
VDDP_A_2
AG4
VDDP_A_3
AG5
VDDP_A_4
AG6
VDDR
AG7
VDDR
AG8
VDDR
AG9
VDDR
AE11
VDDA
AF11
VDDA
AMD_TOPEDO_FS-1
Keep trace from resistor to A PU
within 0.6"
Keep trace from Caps to APU
within 1.2"
CONN@
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDP_B_1
VDDP_B_2
VDDP_B_3
VDDP_B_4
VDDR
VDDR
VDDR
VDDR
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
Dr-Bios.com
4
3
2
1
1 2
1 2
1 3
Q13
2N7002K_SOT23-3
1 3
Q16
2N7002K_SOT23-3
R677 0_0402_5%
1
+3VS
12
2
D
+3VS
12
2
D
R613
10K_0402_5%
1K_0402_5%
G
S
R621
10K_0402_5%
1K_0402_5%
G
S
2
R616
R623
+1.5VS
+1.5VS
+1.5VS
1 2
1 2
12
@
R630
4.7K_0402_5%
Panel ENBKL
Panel ENBKLPanel ENBKL
DP_ENBKL8
Panel ENVDD
Panel ENVDD
Panel ENVDDPanel ENVDD
DP_ENVDD8
@
1
R619 2.2K_0402_5%
@
R620
100K_0402_5%
1 2
1 2
R633 2.2K_0402_5%
@
R634
100K_0402_5%
1 2
2
DP_ENBKL
@
HPD
HPD Panel ENBKL
HPDHPD
@
@
R615
1K_0402_5%
12
R622
1K_0402_5%
1
@
@
D D
Translator HPD
From Translator
LVDS_HPD26 DP0_HPD 8
LVDS_HPD
R618 100K_0402_5%
CRT HPD
From FCH
FCH_CRT_HPD15 DP1_HPD 8
C C
FCH_CRT_HPD
2
R627 100K_0402_5%
HDMI HPD
From HDMI Conn
APU_HDMI_HPD28 DP5_HPD 8
APU_HDMI_HPD
@
2
1
R659 100K_0402_5%
+3VS
@
R617
100K_0402_5%
1 2
@
2
C
E
3 1
MMBT3904_NL_SOT23-3
1 2
+3VS
1 2
C
2
B
E
3 1
G
@
R631
100K_0402_5%
2
G
MMBT3904_NL_SOT23-3
@
Q15
2
B
R676 0_0402_5%
@
Q19
12
@
R614
4.7K_0402_5%
APU_ENBKL
13
D
Q14
2N7002K_SOT23-3
S
ENBKL
12
@
R632
4.7K_0402_5%
13
D
@
2N7002K_SOT23-3
S
R624 0_0402_5%@
1 2
APU_ENVDD 27
Q18
ENBKL 36
B B
A A
5
4
Panel PWM
Panel PWM
Panel PWMPanel PWM
2
DP_INT_PWM8
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
1
R637 2.2K_0402_5%
12
R638
4.7K_0402_5%
2011/04/25 2012/04/25
Compal Secret Data
+3VS
12
R635
47K_0402_5%
C
Q21
2
B
E
3 1
Deciphered Date
12
R636
4.7K_0402_5%
13
D
Q20
2
G
2N7002K_SOT23-3
S
MMBT3904_NL_SOT23-3
2
APU_INVT_PWM 26,27
Q15 / Q19 / Q21 change to SB000006A00
20101228
Title
AMD FS1 Singal Level Shifter
Size Document Number Rev
Custom
QBL60 LA-7552P
Date: Sheet of
1
10 53Monday, April 25, 2011
1.0
A
Dr-Bios.com
B
C
D
E
+VREF_DQ
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDM0
DDRA_SDQ2
1 1
DDRA_SDQS1#7
DDRA_SDQS17
DDRA_SDQS2#7
DDRA_SDQS27
DDRA_CKE07
2 2
3 3
4 4
C1080
2.2U_0603_6.3V4Z
DDRA_SBS2#7
DDRA_CLK07
DDRA_CLK0#7
DDRA_SBS0#7
DDRA_SWE#7
DDRA_SCAS#7 DDRA_ODT0 7
DDRA_SCS1#7
DDRA_SDQS4#7
DDRA_SDQS47
DDRA_SDQS6#7
DDRA_SDQS67
+3VS
1
1
C1081
0.1U_0402_16V4Z
2
2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS# DDRA_ODT0
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R643 10K_0402_5%
+3VS
1
+1.5V +1.5V
JDIMM2
15mil
1
VREF_DQ
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
29
DQS1
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
61
VSS22
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
2
12
R645
10K_0402_5%
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013310-1
VSS1
VSS3
DQS#0
DQS0
VSS6
VSS8
DQ12
DQ13
VSS10
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A11
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
2
DDRA_SDQ4
4
DDRA_SDQ5
6
8
DDRA_SDQS0#
10
DDRA_SDQS0
12
14
DDRA_SDQ6
16
DDRA_SDQ7
18
20
DDRA_SDQ12
22
DDRA_SDQ13
24
26
DDRA_SDM1
28
MEM_MA_RST#
30
32
DDRA_SDQ14
34
DDRA_SDQ15
36
38
DDRA_SDQ20
40
DDRA_SDQ21
42
44
DDRA_SDM2
46
48
DDRA_SDQ22
50
DDRA_SDQ23
52
54
DDRA_SDQ28
56
DDRA_SDQ29
58
60
DDRA_SDQS3#
62
DDRA_SDQS3
64
66
DDRA_SDQ30
68
DDRA_SDQ31
70
72
DDRA_CKE1
74
76
DDRA_SMA15
78
DDRA_SMA14
80
82
DDRA_SMA11
84
DDRA_SMA7
86
A7
88
DDRA_SMA6
90
A6
A4
A2
A0
G2
DDRA_SMA4
92
94
DDRA_SMA2
96
DDRA_SMA0
98
100
DDRA_CLK1
102
DDRA_CLK1#
104
106
DDRA_SBS1#
108
DDRA_SRAS#
110
112
DDRA_SCS0#
114
116
118
DDRA_ODT1
120
122
124
15mil
126
128
DDRA_SDQ36
130
DDRA_SDQ37
132
134
DDRA_SDM4
136
138
DDRA_SDQ38
140
DDRA_SDQ39
142
144
DDRA_SDQ44
146
DDRA_SDQ45
148
150
DDRA_SDQS5#
152
DDRA_SDQS5
154
156
DDRA_SDQ46
158
DDRA_SDQ47
160
162
DDRA_SDQ52
164
DDRA_SDQ53
166
168
DDRA_SDM6
170
172
DDRA_SDQ54
174
DDRA_SDQ55
176
178
DDRA_SDQ60
180
DDRA_SDQ61
182
184
DDRA_SDQS7#
186
DDRA_SDQS7
188
190
DDRA_SDQ62
192
DDRA_SDQ63
194
196
MEM_MA_EVENT#
198
200
202
204
206
+0.75VS
DDRA_SDQS0# 7
DDRA_SDQS0 7
MEM_MA_RST# 7
DDRA_SDQS3# 7
DDRA_SDQS3 7
DDRA_CKE1 7
DDRA_CLK1 7
DDRA_CLK1# 7
DDRA_SBS1# 7
DDRA_SRAS# 7
DDRA_SCS0# 7
DDRA_ODT1 7
1
C1066
1000P_0402_50V7K
2
DDRA_SDQS5# 7
DDRA_SDQS5 7
DDRA_SDQS7# 7
DDRA_SDQS7 7
MEM_MA_EVENT# 7
FCH_SDATA0 12,14,32
FCH_SCLK0 12,14,32
+VREF_CA
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
Place near DIMM1
+1.5V
0.1U_0402_16V4Z
2
C1067
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1077
1
0.1U_0402_16V4Z
+VREF_DQ
15mil
4.7U_0603_6.3V6K
+VREF_DQ
1
1
@
C1060
2
2
0.1U_0402_16V4Z
DDRA_SDQ[0..63] 7
DDRA_SDM[0..7] 7
DDRA_SMA[0..15] 7
2
C1068
1
0.1U_0402_16V4Z
2
C1078
1
4.7U_0603_6.3V6K
1
C1061
2
1000P_0402_50V7K
2
1
C1062
0.1U_0402_16V4Z
2
C1069
C1070
1
C1106 0.1U_0402_16V4Z
1
C1079
2
+1.5V
R639
1K_0402_1%
1 2
R641
1K_0402_1%
1 2
2
C1071
1
0.1U_0402_16V4Z
+1.5V+0.75VS
@
2
1
Add C1106
20101101
0.1U_0402_16V4Z
2
C1072
1
+VREF_CA
4.7U_0603_6.3V6K
1
2
2
C1073
1
0.1U_0402_16V4Z
15mil
+VREF_CA
1
@
C1063
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1074
1
1
C1064
2
1000P_0402_50V7K
2
C1075
1
0.1U_0402_16V4Z
+1.5V
C1065
0.1U_0402_16V4Z
2
C1076
1
R640
1K_0402_1%
1 2
R642
1K_0402_1%
1 2
Security Classification
DIMM_A STD H:9.2mm
A
<Address: 00>
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Rev
Custom
Date: Sheet of
Compal Electronics, Inc.
DDRIII SO-DIMM 1
QBL60 LA-7552P
E
11 53Monday, April 25, 2011
1.0
A
Dr-Bios.com
B
C
D
E
+VREF_DQ
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDM0
DDRB_SDQ2
+3VS
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_CLK0
DDRB_CLK0#
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R646 10K_0402_5%
1
<BOM Structure>
1 1
DDRB_SDQS1#7
DDRB_SDQS17
DDRB_SDQS2#7
DDRB_SDQS27
DDRB_CKE07
2 2
3 3
4 4
DDRB_SBS2#7
DDRB_CLK07
DDRB_CLK0#7
DDRB_SBS0#7
DDRB_SWE#7
DDRB_SCAS#7
DDRB_SCS1#7
DDRB_SDQS4#7
DDRB_SDQS47
DDRB_SDQS6#7
DDRB_SDQS67
2
12
<BOM Structure>
R648
10K_0402_5%
+1.5V
15mil
JDIMM1
1
VREF_DQ
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
29
DQS1
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
61
VSS22
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
A15
A14
A11
CK1
BA1
S0#
SCL
+1.5V
2
DDRB_SDQ4
4
DDRB_SDQ5
6
8
DDRB_SDQS0#
10
DDRB_SDQS0
12
14
DDRB_SDQ6
16
DDRB_SDQ7
18
20
DDRB_SDQ12
22
DDRB_SDQ13
24
26
DDRB_SDM1
28
MEM_MB_RST#
30
32
DDRB_SDQ14
34
DDRB_SDQ15
36
38
DDRB_SDQ20
40
DDRB_SDQ21
42
44
DDRB_SDM2
46
48
DDRB_SDQ22
50
DDRB_SDQ23
52
54
DDRB_SDQ28
56
DDRB_SDQ29
58
60
DDRB_SDQS3#
62
DDRB_SDQS3
64
66
DDRB_SDQ30
68
DDRB_SDQ31
70
72
DDRB_CKE1
74
76
DDRB_SMA15
78
DDRB_SMA14
80
82
DDRB_SMA11
84
DDRB_SMA7
86
A7
88
DDRB_SMA6
90
A6
A4
A2
A0
G2
DDRB_SMA4
92
94
DDRB_SMA2
96
DDRB_SMA0
98
100
DDRB_CLK1
102
DDRB_CLK1#
104
106
DDRB_SBS1#
108
DDRB_SRAS#
110
112
DDRB_SCS0#
114
DDRB_ODT0
116
118
DDRB_ODT1
120
122
124
15mil
126
128
DDRB_SDQ36
130
DDRB_SDQ37
132
134
DDRB_SDM4
136
138
DDRB_SDQ38
140
DDRB_SDQ39
142
144
DDRB_SDQ44
146
DDRB_SDQ45
148
150
DDRB_SDQS5#
152
DDRB_SDQS5
154
156
DDRB_SDQ46
158
DDRB_SDQ47
160
162
DDRB_SDQ52
164
DDRB_SDQ53
166
168
DDRB_SDM6
170
172
DDRB_SDQ54
174
DDRB_SDQ55
176
178
DDRB_SDQ60
180
DDRB_SDQ61
182
184
DDRB_SDQS7#
186
DDRB_SDQS7
188
190
DDRB_SDQ62
192
DDRB_SDQ63
194
196
MEM_MB_EVENT#
198
200
202
204
206
+0.75VS
DDRB_SDQS0# 7
DDRB_SDQS0 7
MEM_MB_RST# 7
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_CKE1 7
DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
DDRB_ODT1 7
1
C1088
1000P_0402_50V7K
2
DDRB_SDQS5# 7
DDRB_SDQS5 7
DDRB_SDQS7# 7
DDRB_SDQS7 7
MEM_MB_EVENT# 7
FCH_SDATA0 11,14,32
FCH_SCLK0 11,14,32
+VREF_CA
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
DDRB_SDQ[0..63] 7
DDRB_SDM[0..7] 7
DDRB_SMA[0..15] 7
Place near DIMM2
+1.5V
0.1U_0402_16V4Z
2
2
1
0.1U_0402_16V4Z
+0.75VS
0.1U_0402_16V4Z
+VREF_DQ +VREF_CA
15mil 15mil
4.7U_0603_6.3V6K
1
@
C1082
2
2
1
C1089
C1099
0.1U_0402_16V4Z
1
2
C1090
1
0.1U_0402_16V4Z
2
1
+VREF_DQ
C1083
1000P_0402_50V7K
2
C1091
1
0.1U_0402_16V4Z
1
C1100
C1101
2
4.7U_0603_6.3V6K
1
C1084
2
0.1U_0402_16V4Z
C1107 0.1U_0402_16V4Z
4.7U_0603_6.3V6K
2
C1092
1
0.1U_0402_16V4Z
@
1 2
1
@
C1085
2
0.1U_0402_16V4Z
2
C1093
1
+VREF_CA
1
C1086
2
Add C1107
20101101
0.1U_0402_16V4Z
2
C1094
1
1
C1087
2
1000P_0402_50V7K
2
C1095
1
0.1U_0402_16V4Z
+1.5V+1.5V
1
+
C9
330U_X_2VM_R6M@
2
0.1U_0402_16V4Z
2
C1096
1
2
C1097
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1098
1
Security Classification
DIMM_B STD H:5.2mm
A
<Address: 01>
B
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Rev
Custom
Date: Sheet of
Compal Electronics, Inc.
DDRIII SO-DIMM 2
QBL60 LA-7552P
E
12 53Monday, April 25, 2011
1.0
1 2
Dr-Bios.com
2
1
R836
4.7K_0402_5%
1 2
+RTCBATT
CONN@
D23
1
DAN202UT106_SC70-3
E
PLT_RST# 18,26,29,32
Q38 change to SB000006A00
20101228
APU_PWRGD_L 47
1
JRTC1
+
SUYIN_060003HA002G202ZL
-
2
+RTCBATT
12
2
3
13 53Monday, April 25, 2011
E
R857
1K_0402_5%
+CHGRTC
1.0
D
For PCIE device reset on FS1
(GLAN,WLAN)
R825 33_0402_5%
1 2
150P_0402_50V8J
VGA_PWRGD25,48
PCI_AD23 16
PCI_AD24 16
PCI_AD25 16
PCI_AD26 16
PCI_AD27 16
PE_GPIO0 18
PE_GPIO1 25,36
2
LPC_CLK0_EC 16,36
CLK_PCI_DB 32
LPC_CLK1 16
LPC_AD0 32,36
LPC_AD1 32,36
LPC_AD2 32,36
LPC_AD3 32,36
LPC_FRAME# 32,36
SERIRQ 36
ALLOW_STOP 8
EC_THERM# 8,36,47
APU_PWRGD 8
APU_RST# 8
RTC_CLK 16,36
1
R859 510_0402_5%
W=20mils
for Clear CMOS
1U_0402_6.3V4Z
D
+3VALW
C1193
@
1 2
0.1U_0402_16V4Z
5
@
2
P
B
4
Y
1
A
G
2
C1188
R826
8.2K_0402_5%@
1
1 2
U27
VGA_PWRGD VGA_PWRGD_R
@
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
R835 0_0402_5%
+3VALW
5
2
P
B
1
A
G
3
R832 0_0402_5%
U26
1 2
C1199
@
2
1
0.1U_0402_16V4Z
4
Y
R830 0_0402_5%@
R831 100K_0402_5%@
2
1
Level shift to ISL6267
10K_0402_5%
APU_PWRGD
+1.5VS
12
R834
B
2
E
3 1
Q38
MMBT3904_NL_SOT23-3
+3VS
C
RTC BATT Conn.
APU_PG/APU_RST#/LDT_STP# : OD pin
DMA_ACTIVE# : IN/OD, 0.8V threshold
PROCHOT# : IN, 0.8V threshold
LDT_STP : No use, NC
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.
2
12
CLRP1
SHORT PADS
@
+RTCVCC
1
C1204
2
0.1U_0402_16V4Z
Title
Size Document Number Rev
Custom
Date: Sheet of
Compal Electronics, Inc.
Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
QBL60 LA-7552P
PCICLK0
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
GNT0#
GNT1#/GPO44
CLKRUN#
LOCK#
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#
S5_CORE_EN
RTCCLK
32K_X1
32K_X2
C
AF3
AF1
AF5
AG2
AF6
AB5
AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
VGA_PWRGD_R
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9
AF18
AE18
AC16
AD18
B25
D25
D27
C28
A26
A29
A31
B27
AE27
AE19
G25
E28
E26
G26
F26
H7
F1
F3
E6
G2
G4
LPC_CLK1_R
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
32K_X1
32K_X2
T23
T24
APU_PWRGD
2011/04/25 2012/04/25
C
PCI_CLK1 16
PCI_CLK3 16
PCI_CLK4 16
APU_PCIE_RST#_C
1 2
R842 0_0402_5%
PE_GPIO1
1
22_0402_5%
1 2
22_0402_5%
1 2
0_0402_5%
R853 0_0402_5%@
1 2
1
LPC_CLK0_ECLPC_CLK0_EC_R
2
C1202
2
RTCVCC_R
1
2
0.1U_0402_16V4Z
R843
R671
R844
R855 22_0402_5%
Compal Secret Data
Deciphered Date
1
R109 10K_0402_5%
@
C1203
1
2
CLK_SD_48M_R
25M_X1
25M_X2
32K_X1
32K_X2
B
U25A
AE2
PCIE_RST#
AD5
A_RST#
AE30
UMI_TX0P
AE32
UMI_TX0N
AD33
UMI_TX1P
AD31
UMI_TX1N
AD28
UMI_TX2P
AD29
UMI_TX2N
AC30
UMI_TX3P
AC32
UMI_TX3N
AB33
UMI_RX0P
AB31
UMI_RX0N
AB28
UMI_RX1P
AB29
UMI_RX1N
Y33
UMI_RX2P
Y31
UMI_RX2N
Y28
UMI_RX3P
Y29
UMI_RX3N
AF29
PCIE_CALRP
AF31
PCIE_CALRN
V33
GPP_TX0P
V31
GPP_TX0N
W30
GPP_TX1P
W32
GPP_TX1N
AB26
GPP_TX2P
AB27
GPP_TX2N
AA24
GPP_TX3P
AA23
GPP_TX3N
AA27
GPP_RX0P
AA26
GPP_RX0N
W27
GPP_RX1P
V27
GPP_RX1N
V26
GPP_RX2P
W26
GPP_RX2N
W24
GPP_RX3P
W23
GPP_RX3N
F27
CLK_CALRN
G30
PCIE_RCLKP
G28
PCIE_RCLKN
R26
DISP_CLKP
T26
DISP_CLKN
H33
DISP2_CLKP
H31
DISP2_CLKN
T24
APU_CLKP
T23
APU_CLKN
J30
SLT_GFX_CLKP
K29
SLT_GFX_CLKN
H27
GPP_CLK0P
H28
GPP_CLK0N
J27
GPP_CLK1P
K26
GPP_CLK1N
F33
GPP_CLK2P
F31
GPP_CLK2N
E33
GPP_CLK3P
E31
GPP_CLK3N
M23
GPP_CLK4P
M24
GPP_CLK4N
M27
GPP_CLK5P
M26
GPP_CLK5N
N25
GPP_CLK6P
N26
GPP_CLK6N
R23
GPP_CLK7P
R24
GPP_CLK7N
N27
GPP_CLK8P
R27
GPP_CLK8N
J26
14M_25M_48M_OSC
C31
25M_X1
C33
25M_X2
HUDSON-M2_FCBGA656
M2@
B
HUDSON-2
PCICLK1/GPO36
PCICLK2/GPO37
PCI CLKS
PCI EXPRESS INTERFACES
PCI INTERFACE
CLOCK GENERATOR
LPCAPU
S5 PLUS
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
INTRUDER_ALERT#
VDDBT_RTC_G
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
C1195 150P_0402_50V8J
12
APU_PCIE_RST#_C
PCI Host Bus Reset (To EC)
1 1
GPP Port0 For USB30 on SUS/B
GPP Port0 For USB30 on SUS/B
GPP Port0 For USB30 on SUS/BGPP Port0 For USB30 on SUS/B
GPP Port1 For USB30 on M/B 20101103
GPP Port1 For USB30 on M/B 20101103
GPP Port1 For USB30 on M/B 20101103GPP Port1 For USB30 on M/B 20101103
2 2
SS
APU DISP
NSS
APU
VGA
GLAN
WLAN
A_RST#36
UMI_MTX_C_FRX_P06
UMI_MTX_C_FRX_N06
UMI_MTX_C_FRX_P16
UMI_MTX_C_FRX_N16
UMI_MTX_C_FRX_P26
UMI_MTX_C_FRX_N26
UMI_MTX_C_FRX_P36
UMI_MTX_C_FRX_N36
UMI_FTX_C_MRX_P06
UMI_FTX_C_MRX_N06
UMI_FTX_C_MRX_P16
UMI_FTX_C_MRX_N16
UMI_FTX_C_MRX_P26
UMI_FTX_C_MRX_N26
UMI_FTX_C_MRX_P36
UMI_FTX_C_MRX_N36
+PCIE_VDDR_FCH
+1.1VS_CKVDD
For "EXT" CLK mode, input to PCIE,
APU_DISP_CLKP8
APU_DISP_CLKN8
TRAVIS_CLKP26
TRAVIS_CLKN26
APU_CLKP8
APU_CLKN8
CLK_PEG_VGA18
CLK_PEG_VGA#18
CLK_PCIE_LAN29
CLK_PCIE_LAN#29
CLK_PCIE_MINI132
CLK_PCIE_MINI1#32
R829 33_0 402_5%
C1189 0.1U_0402_16V7K
C1190 0.1U_0402_16V7K
C1191 0.1U_0402_16V7K
C1192 0.1U_0402_16V7K
C1196 0.1U_0402_16V7K
C1197 0.1U_0402_16V7K
C1198 0.1U_0402_16V7K
C1194 0.1U_0402_16V7K
R827 590_0402_1%
R828 2K_0402_1%
R833 2K_0402_1%
APU_DISP_CLKP
APU_DISP_CLKN
TRAVIS_CLKP
TRAVIS_CLKN
APU_CLKP
APU_CLKN
CLK_PEG_VGA
CLK_PEG_VGA#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
1
2
1
1 2
2
1
2
1
2
1
1 2
2
1
2
1
1
1
1 2
R604 0_0402_5%
R625 0_0402_5%
R644 0_0402_5%
R572 0_0402_5%
2
2
2
1 2
1
1 2
1
A_RST#_R
UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3
UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3
PCIE_CALRP
PCIE_CALRN
CLK_CALRN
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
2
CLK_PCIE_MINI1_R
CLK_PCIE_MINI1#_R
2
SS
3 3
EMI
R657 33_0402_5%
CLK_SD_48M31
C1200
2
1
12P_0402_50V8J
25MHZ_20PF_7A25000012
12
C1201
12P_0402_50V8J
4 4
A
C1205
2
1
10P_0402_50V8J
R861
20M_0402_5%
C1206
2
1
10P_0402_50V8J
1 2
1
12
12
R856 0_0402_5%
R858
X1
1M_0402_5%
Y4
4
OSC
1
OSC
32.768KHZ 7PF Q13MC1461000100
Close to HUDSON-M2
2
3
NC
2
NC
A
Dr-Bios.com
B
C
D
E
PCIE_RST2 : Reset PCIE device on Hudson2
U25D
AB6
EC_LID_OUT#36
SLP_S3#36
SLP_S5#36
PBTN_OUT#36
FCH_PWRGD36
1 1
EC_GA2036
EC_KBRST#36
EC_SCI#36
EC_SMI#36
THERMTRIP:
Need level shift from +3VALW to +1.5V
SM bus 0-->S0 PWR domain
SM bus 1-->S5 PWR domain
VGA_PD: Support MLDAC power
save if connect
0: MLDAC power on
1: MLDAC power off
2 2
+3VALW
2
1
R56 100K_0402_5%
3 3
4 4
R55 100K_0402_5%
1
R54 100K_0402_5%
1 2
R871 10K_0402_5%
1 2
R874 2.2K_0402_5%
1
R876 2.2K_0402_5%
1 2
R877 10K_0402_5%
1
R878 10K_0402_5%
+3VS
1
R880 2.2K_0402_5%
1 2
R881 2.2K_0402_5%
1
R882 8.2K_0402_5%
1
R940 8.2K_0402_5%
1
R884 2.2K_0402_5%
1
R885 10K_0402_5%
1
R886 10K_0402_5%
1 2
R888 10K_0402_5%
1 2
@
@
@
@
@
2
2
2
Modify 2010212-AMD request
2
2
Modify 2010212-AMD request
2
2
2
2
FCH_PCIE_WAKE#29,32,36
HDA_BITCLK_AUDIO30
HDA_SDOUT_AUDIO30
HDA_SDIN030
HDA_SYNC_AUDIO30
HDA_RST_AUDIO#30
USB_OC2#
USB_OC0#
USB_OC1#
H_THERMTRIP#
FCH_SCLK1
FCH_SDATA1
EC_LID_OUT#
FCH_PCIE_WAKE#
FCH_SCLK0
FCH_SDATA0
MINI1_CLKREQ#
LAN_CLKREQ#_1
Modify 20101111
EC_RSMRST#
HDA_BITCLK
HDA_SDIN0
HDA_SDIN1
H_THERMTRIP#8
EC_RSMRST#36
LAN_CLKREQ#29
FCH_SCLK011,12,32
FCH_SDATA011,12,32
MINI1_CLKREQ#32
VGA_PD16
USB_OC2#34
USB_OC1#34
USB_OC0#34
+3VALW
@
+3VALW
+3VALW
FCH_PCIE_WAKE#
+3VS
R81 0_0402_5%
Modify 2010212-AMD request
8.2K_0402_5%
@
12
8.2K_0402_5%
12
1
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
MINI1_CLKREQ#
VGA_PD
USB_OC2#
USB_OC1#
USB_OC0#
R866 33_0402_5%
1 2
R867 33_0402_5%
1 2
R868 33_0402_5%
1 2
R869 33_0402_5%
8.2K_0402_5%
12
R47
R48
8.2K_0402_5%
12
1
8.2K_0402_5%
@
@
12
R43
R45
FCH_GPIO189
FCH_GPIO190
FCH_GPIO191
8.2K_0402_5%
@
@
12
R44
R46
2
Project SKU ID
GPIO189 (use VGA) L(NO)
GPIO190 (use PX)
GPIO191
Add Project ID Table
201011301600
For FCH internal debug use
@
1 2
R887 2.2K_0402_5%
@
2
1
R889 2.2K_0402_5%
@
1 2
R890 2.2K_0402_5%
EC_LID_OUT#
TEST0
TEST1
TEST2
SYS_RESET#
@
2
1
R18 10K_0402_5%
2
1
R862 10K_0402 _5%
2
1
R873 10K_0402_5%
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
HDA_SYNC
HDA_RST#
TEST0
TEST1
TEST2
LAN_CLKREQ#_1
2
T29
T31
T35
T27
FCH_GPIO189
FCH_GPIO190
FCH_GPIO191
H(YES)
R44
R43
H(YES)
L(NO)
R45
R46
L(15")
H(17")
R48
R47
PCIE_RST2#/PCI_PME#/GEVENT4#
R2
RI#/GEVENT22#
W7
SPI_CS3#/GBE_STAT1/GEVENT21#
T3
SLP_S3#
W2
SLP_S5#
J4
PWR_BTN#
N7
PWR_GOOD
T9
TEST0
T10
TEST1/TMS
V9
TEST2
AE22
GA20IN/GEVENT0#
AG19
KBRST#/GEVENT1#
R9
LPC_PME#/GEVENT3#
C26
LPC_SMI#/GEVENT23#
T5
LPC_PD#/GEVENT5#
U4
SYS_RESET#/GEVENT19#
K1
WAKE#/GEVENT8#
V7
IR_RX1/GEVENT20#
R10
THRMTRIP#/SMBALERT#/GEVEN T2#
AF19
WD_PWRGD
U2
RSMRST#
AG24
CLK_REQ4#/SATA_IS0#/GPIO64
AE24
CLK_REQ3#/SATA_IS1#/GPIO63
AE26
SMARTVOLT1/SATA_IS2#/GPIO50
AF22
CLK_REQ0#/SATA_IS3#/GPIO60
AH17
SATA_IS4#/FANOUT3/GPIO55
AG18
SATA_IS5#/FANIN3/GPIO59
AF24
SPKR/GPIO66
AD26
SCL0/GPIO43
AD25
SDA0/GPIO47
T7
SCL1/GPIO227
R7
SDA1/GPIO228
AG25
CLK_REQ2#/FANIN4/GPIO62
AG22
CLK_REQ1#/FANOUT4/GPIO61
J2
IR_LED#/LLB#/GPIO184
AG26
SMARTVOLT2/SHUTDOWN #/GPIO51
V8
DDR3_RST#/GEVENT7#/VGA_PD
W8
GBE_LED0/GPIO183
Y6
SPI_HOLD#/GBE_LED1/GEVENT9#
V10
GBE_LED2/GEVENT10#
AA8
GBE_STAT0/GEVENT11#
AF25
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
M7
BLINK/USB_OC7#/GEVENT18#
R8
USB_OC6#/IR_TX1/GEVENT6#
T1
USB_OC5#/IR_TX0/GEVENT17#
P6
USB_OC4#/IR_RX0/GEVENT16#
F5
USB_OC3#/AC_PRES/TDO/GEVENT15#
P5
USB_OC2#/TCK/GEVENT14#
J7
USB_OC1#/TDI/GEVENT13#
T8
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12 #
AB3
AZ_BITCLK
AB1
AZ_SDOUT
AA2
AZ_SDIN0/GPIO167
Y5
AZ_SDIN1/GPIO168
Y3
AZ_SDIN2/GPIO169
Y1
AZ_SDIN3/GPIO170
AD6
AZ_SYNC
AE4
AZ_RST#
K19
PS2_DAT/SDA4/GPIO187
J19
PS2_CLK/CEC/SCL4/GPIO188
J21
SPI_CS2#/GBE_STAT2/GPIO166
D21
PS2KB_DAT/GPIO189
C20
PS2KB_CLK/GPIO190
D23
PS2M_DAT/GPIO191
C22
PS2M_CLK/GPIO192
F21
KSO_0/GPIO209
E20
KSO_1/GPIO210
F20
KSO_2/GPIO211
A22
KSO_3/GPIO212
E18
KSO_4/GPIO213
A20
KSO_5/GPIO214
J18
KSO_6/GPIO215
H18
KSO_7/GPIO216
G18
KSO_8/GPIO217
B21
KSO_9/GPIO218
K18
KSO_10/GPIO219
D19
KSO_11/GPIO220
A18
KSO_12/GPIO221
C18
KSO_13/GPIO222
B19
KSO_14/GPIO223
B17
KSO_15/GPIO224
A24
KSO_16/GPIO225
D17
KSO_17/GPIO226
HUDSON-M2_FCBGA656
M2@
A
B
HUDSON-2
EMBEDDED CTRL
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
USBCLK/14M_25M_48M_OSC
USB MISCUSB 1.1
ACPI / WAKE UP EVENTSHD AUDIO
USB 2.0USB 3.0
USB OC GPIO
EC_PWM0/EC_TIMER 0/GPIO197
EC_PWM1/EC_TIMER 1/GPIO198
EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER 3/GPIO200
USB_RCOMP
USB_FSD1P/GPIO186
USB_FSD1N
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
USBSS_CALRP
USBSS_CALRN
USB_SS_TX3P
USB_SS_TX3N
USB_SS_RX3P
USB_SS_RX3N
USB_SS_TX2P
USB_SS_TX2N
USB_SS_RX2P
USB_SS_RX2N
USB_SS_TX1P
USB_SS_TX1N
USB_SS_RX1P
USB_SS_RX1N
USB_SS_TX0P
USB_SS_TX0N
USB_SS_RX0P
USB_SS_RX0N
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
2011/04/25 2012/04/25
G8
USB_RCOMP
B9
H1
H3
H6
H5
H10
G10
K10
J12
G12
F12
USB20_P10
K12
USB20_N10
K13
B11
D11
E10
F10
C10
A10
H9
G9
A8
C8
USB20_P4
F8
USB20_N4
E8
USB20_P3
C6
USB20_N3
A6
USB20_P2
C5
USB20_N2
A5
USB20_P1
C1
USB20_N1
C3
USB20_P0
E1
USB20_N0
E3
USBSS_CALRP
C16
USBSS_CALRN
A16
A14
C14
C12
A12
D15
B15
E14
F14
F15
G15
H13
G13
USB30_MTX_DRX_P0
J16
USB30_MTX_DRX_N0
H16
USB30_MRX_DTX_P0
J15
USB30_MRX_DTX_N0
K15
R870 10K_0402_5%
H19
R872 10K_0402_5%
G19
APU_SIC
G22
APU_SID
G21
E22
H22
EC_PWM2
J22
H21
K21
K22
F22
F24
E24
B23
C24
F18
Compal Secret Data
Deciphered Date
R863 11.8K_0402_1%
1
USB20_P10 34
USB20_N10 34
USB20_P4 31
USB20_N4 31
USB20_P3 32
USB20_N3 32
USB20_P2 27
USB20_N2 27
USB20_P1 30
USB20_N1 30
USB20_P0 34
USB20_N0 34
R864 1K_0402_1%M3@
1 2
R865 1K_0402_1%
1 2
M3@
C39 0.1U_0402_16V7K
C37 0.1U_0402_16V7K
1 2
1 2
D
M3@
2
1
1
2
2
M3@
APU_SIC 6,8
APU_SID 6,8
EC_PWM2 16
USB1
CardReder
WLAN(BT)
CMOS
USB3
USB2
Custom
Date: Sheet of
Hudson-M2 Hudson-M3
EHCI CTL
DEV 22, Fn 2
<Disable CTL of M2>
Hudson-M2/M3
EHCI CTL
DEV 19, Fn 2
Hudson-M2/M3
EHCI CTL
DEV 18, Fn 2
+FCH_VDD_11_SSUSB_S
USB30_MTX_C_DRX_P0 34
USB30_MTX_C_DRX_N0 34
USB30_MRX_DTX_P0 34
USB30_MRX_DTX_N0 34
Title
Size Document Number Rev
Compal Electronics, Inc.
Hudson-M2/M3-ACPI/USB/EC
QBL60 LA-7552P
E
On board
USB Conn
14 53Monday, April 25, 2011
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0
Hudson-M3
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0
1.0
A
Dr-Bios.com
SATA_STX_DRX_P033
+3VS
SATA_STX_DRX_N033
SATA_DTX_C_SRX_N033
SATA_DTX_C_SRX_P033
SATA_STX_DRX_P133
SATA_STX_DRX_N133
SATA_DTX_C_SRX_N133
SATA_DTX_C_SRX_P133
WL_OFF#32
HDD1
ODD
1 1
2 2
+AVDD_SATA
3 3
B
SATA_CALRP
R8991K_0402_1%
2
1
SATA_CALRN
R9001K_0402_1%
12
SATA_LED#32
R902 10K_0402_5%
1
T40
BT_ON32
R13 10K_0402_5%
R14 10K_0402_5%
R15 10K_0402_5%
R16 10K_0402_5%
2
1
1
1 2
1
SATA_LED#
BT_ON
WL_OFF#
2
2
2
U25B
AK19
SATA_TX0P
AM19
SATA_TX0N
AL20
SATA_RX0N
AN20
SATA_RX0P
AN22
SATA_TX1P
AL22
SATA_TX1N
AH20
SATA_RX1N
AJ20
SATA_RX1P
AJ22
SATA_TX2P
AH22
SATA_TX2N
AM23
SATA_RX2N
AK23
SATA_RX2P
AH24
SATA_TX3P
AJ24
SATA_TX3N
AN24
SATA_RX3N
AL24
SATA_RX3P
AL26
SATA_TX4P
AN26
SATA_TX4N
AJ26
SATA_RX4N
AH26
SATA_RX4P
AN29
SATA_TX5P
AL28
SATA_TX5N
AK27
SATA_RX5N
AM27
SATA_RX5P
AL29
NC6
AN31
NC7
AL31
NC8
AL33
NC9
AH33
NC10
AH31
NC11
AJ33
NC12
AJ31
NC13
AF28
SATA_CALRP
AF27
SATA_CALRN
AD22
SATA_ACT#/GPIO67
AF21
SATA_X1
AG21
SATA_X2
AH16
FANOUT0/GPIO52
AM15
FANOUT1/GPIO53
AJ16
FANOUT2/GPIO54
AK15
FANIN0/GPIO56
AN16
FANIN1/GPIO57
AL16
FANIN2/GPIO58
K6
TEMPIN0/GPIO171
K5
TEMPIN1/GPIO172
K3
TEMPIN2/GPIO173
M6
TEMPIN3/TALERT#/GPIO174
HUDSON-M2_FCBGA656
M2@
SERIAL ATA
C
HUDSON-2
SD CARD
GBE LANSPI ROMVGA DAC
ROM_RST#/SPI_WP#/GPIO161
VGA MAINLINK
HW MONITOR
SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
VGA_RED
VGA_GREEN
VGA_BLUE
VGA_HSYNC/GPO68
VGA_VSYNC/GPO69
VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71
VGA_DAC_RSET
AUX_VGA_CH_P
AUX_VGA_CH_N
AUXCAL
ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N
ML_VGA_HPD/GPIO229
VIN0/GPIO175
VIN1/GPIO176
VIN2/SDATI_1/GPIO177
VIN3/SDATO_1/GPIO178
VIN4/SLOAD_1/GPIO179
VIN5/SCLK_1/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
NC1
NC2
NC3
NC4
NC5
AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14
AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9
V6
V5
V3
T6
V1
L30
L32
M29
M28
N30
M33
N32
K31
V28
V29
U28
T31
T33
T29
T28
R32
R30
P29
P28
C29
N2
M3
L2
N4
P1
P3
M1
M5
AG16
AH10
A28
G27
L4
GBE_COL
GBE_CRS
GBE_MDIO
GBE_RXERR
GBE_PHY_INTR
FCH_SPI_CLK_R
R896 150_0402_1%
1 2
R897 150_0402_1%
1
R898 150_0402_1%
1 2
R901 715_0402_1%
1
AUXCAL
1
R903 100_0402_1%
FCH_CRT_HPD
1
R5 10K_0402_5%
1 2
R6 10K_0402_5%
1
R7 10K_0402_5%
1
R8 10K_0402_5%
1
R9 10K_0402_5%
1 2
R10 10K_0402_5%
1 2
R11 10K_0402_5%@
1 2
R12 10K_0402_5%
R35 0_0402_5%@
D
SYS BIOS ROM
+3VALW
R626 1K_0402_5%
R934 10K_0402_5%
R935 10K_0402_5%
FCH_SPI_MISO
FCH_SPI_MOSI
2
1
FCH_SPI_CS1#
FCH_SPI_WP#
2
2
ML_VGA_AUXP_C 8
ML_VGA_AUXN_C 8
2
ML_VGA_TXP0 8
ML_VGA_TXN0 8
ML_VGA_TXP1 8
ML_VGA_TXN1 8
ML_VGA_TXP2 8
ML_VGA_TXN2 8
ML_VGA_TXP3 8
ML_VGA_TXN3 8
FCH_CRT_HPD 10
2
2
2
2
1 2
1 2
1 2
@
@
@
FCH_SPI_CLK
FCH_CRT_R 27
FCH_CRT_G 27
FCH_CRT_B 27
FCH_CRT_HSYNC 27
FCH_CRT_VSYNC 27
FCH_CRT_DDC_SDA 27
FCH_CRT_DDC_SCL 27
+VDDAN_11_ML
GL-02/10/2011: Please enabled integrated pull-up/pull-down and left unconnected.
FCH_SPI_CS1#
FCH_SPI_WP#
FCH_SPI_HOLD#
FCH_SPI_CLK
Add for EMI 201011291330
1
3
7
4
@
GBE_MDIO
Change to PD 20101112
GBE_PHY_INTR
GBE_COL
GBE_CRS
GBE_RXERR
Add SYS BIOS ROM
20101111
FCH_CRT_HPD
E
U28
CS#
WP#
HOLD#
GND
MX25L1606EM2I-12G SOP 8P
SA000041N00
R36
@
1 2
8
VCC
6
SCLK
5
SI
2
SO
10_0402_5%
1 2
R891 10K_0402_5%
1 2
R892 10K_0402_5%
1
R893 10K_0402_5%
1
R894 10K_0402_5%
1 2
R895 10K_0402_5%
@
+3VALW
C4660.1U_0402_16V4Z
12
@
FCH_SPI_CLK
FCH_SPI_MOSI
FCH_SPI_MISO
C23
@
2
1
10P_0402_50V8J
+3VALW
2
2
+FCH_VDDAN_33_DAC_R
12
R90410K_0402_5%
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Hudson-M2/M3-SATA/GBE/HWM
QBL60 LA-7552P
15 53Monday, April 25, 2011
E
of
1.0
A
Dr-Bios.com
STRAP PINS
B
C
D
E
PCI_CLK1
1 1
2 2
PULL
HIGH
PULL
LOW
PCI_CLK113
PCI_CLK313
PCI_CLK413
LPC_CLK0_EC13,36
LPC_CLK113
EC_PWM214
RTC_CLK13,36
ALLOW
PCIE GEN2
DEFAULT
FORCE
PCIE GEN1
@
DEBUG STRAPS
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PULL
HIGH
PULL
LOW
+3VS
PCI_CLK3
USE
DEBUG
STRAPS
IGNORE
DEBUG
STRAP
DEFAULT
R905 10K_0402_5%
12
@
R915 1 0K_0402_5%
12
PCI_AD27PCI_AD26
USE PCI
PLL
DEFAULT
BYPASS
PCI PLL
PCI_CLK4 LPC_CLK0
NON_FUSION
CLOCK MODE
FUSION
CLOCK
MODE
DEFAULT
R906 10K_0402 _5%
12
@
R917 1 0K_0402_5%
12
DISABLE
ILA
AUTORUN
DEFAULT
ENABLE
ILA
AUTORUN
EC
ENABLED
EC
DISABLED
DEFAULT
+3VS+3VS
R907 10K_0402 _5%
12
@
R918 1 0K_0402_5%
12
PCI_AD25 PCI_AD24
USE FC
PLL
BYPASS
FC PLL
R908 10K_0402 _5%
12
R919 1 0K_0402_5%
12
CLKGEN
ENABLED
DEFAULT
CLKGEN
DISABLE
+3VALW+3VALW
12
12
@
USE DEFAULT
PCIE STRAPS
DEFAULT
USE EEPROM
PCIE STRAPS
R909 10K_0402 _5%
R920 1 0K_0402_5%
EC_PWM2
LPC ROM
DEFAULT
SPI ROM
12
12
@
PCI_AD23
DISABLE PCI
MEM BOOT
DEFAULTD EFAULT
ENABLE PCI
MEM BOOT
RTC_CLKLPC_CLK1
S5 PLUS
MODE
DISABLED
DEFAULT
S5 PLUS
MODE
ENABLED
+3VALW+3VALW
R910 10K_0402 _5%
R921 2 .2K_0402_5%
R911 10K_0402 _5%
12
R922 2 .2K_0402_5%
12
@
VGA_PD: Support MLDAC power
save if not connect
0: MLDAC power on
1: MLDAC power off
Check VGA_PD states
If support ML DAC power down when no VGA plug
L47
2
1
FBMA-L11-201209-221LMA30T_0805
+3VS
AP2301GN-HF_SOT23-3
VGA_PD#
+1.1VS
AP2301GN-HF_SOT23-3
VGA_PD#
VGA_PD14
220 ohm
Q39
@
3 1
2
AO3413 Vgs(max)=1V
R912 0_0402_5%
1
Q40
@
3 1
2
R923
1K_0402_5%
@
1 2
C1212
R925
2.2K_0402_5%
1 2
FBMA-L11-201209-221LMA30T_0805
2
R913 0_0402_5%
@
1 2
1U_0402_6.3V4Z
30mil
+FCH_VDDAN_33_DAC
@
1
220 ohm
@
2
1
0_0402_5%
R924
5
1
2
L48
+FCH_VDDAN_33_DAC_R
2
C1209
1
2
2.2U_0603_6.3V4Z
+FCH_VDDAN_11_MLDAC
C1210
1
2
0.1U_0402_16V4Z
30mil
+3VS
R916
100K_0402_5%
12
DMN66D0LDW-7_SOT363-6
34
R914
100K_0402_5%
12
VGA_PD#
Q41A
DMN66D0LDW-7_SOT363-6
61
Q41B
2
1U_0402_6.3V4Z
C1211
1
@
2
PCI_AD2713
PCI_AD2613
PCI_AD2513
PCI_AD2413
PCI_AD2313
4 4
R926 2.2K_0402_5%
12
@
R927 2.2K_0402_5%
12
@
R928 2.2K_0402_5%
12
@
A
R929 2.2K_0402_5%
12
@
B
R930 2.2K_0402_5%
12
@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/04/25 2012/04/25
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Hudson-M2/M3-STRAP
QBL60 LA-7552P
E
16 53Monday, April 25, 2011
1.0
of
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