ASUS A6M Schematic Diagram
A
01.BLOCK DIAGRAM
5
02.RESET MAP
03.CLOCK MAP
04.S1_HT_C51
05.S1_DDR2
06.S1_CNTL/DEBUG/THERM
07.S1_POWER
08.DDR2_SODIMM
D D
09.DDR2 TER/FETGAGE
10.C51_HT_CPU
11.C51_HT_MCP
12.C51_PCIE
13.C51_VIDEO
14.C51_VCC_GND
15.FAN/THERM SENSOR
16.MCP51_HT
17.MCP51_PCI/LPC
18.MCP51_IDE/SATA
19.MCP51_USB/AC97/SMB
20.MCP51_RGMI/XTAL
21.MCP51_VCC
22.G73M_PCIE
23.G73M_FB I/F
24.G73M_LVDS/GND
25.G73M_VGA/TV
26.G73M_TMDS/GPIO
27.G73M_XTAL/ROM STRAP
C C
28.G73M_STRAPS
29.G73M_MEM_PART1
30.G73M_MEM_PART2
31.HDD/CDROM
32.MINI PCI
33.CARD BUS
34.PCMCIA
35.1394/SD_CARD
36.SIO/SIR
37.FWH
38.KBC
39.USB/BLUE TOOTH
40.CRT/TV CON
41.LVDS/INVERTER
42.ALC880
43.AMP
44.MIC/LINE-IN JACK
45.RJ45/11/MDC
B B
46.LAN
47.BLANK
48.FUNCTION KEY
49.LED
50.POWER SEQEUNCE(1)
51.POWER SEQUENCE(2)
52.SCREW HOLE
53.Battery
54.CHARGE
55.BATLOW/SD#
56.LOAD SWITCH
57.BLANK
58.BLANK
59.BLANK
60.POWER SEQUENCE BLCOK
61.POWER BUDGET BLOCK
62.BLANK
5
SIR
AUDIO DJ KEY
INSTANT KEY
SUPPER I/O
LPC47N217
KBC 38857
AZALIA CODEC
ALC660
MDC
HEADER
4
A6M
Gigabit
Ethernet
RTL8111B
FWH
LPC BUS
4
33MHz
PCI-E x1
CD-ROM
HDD
Pri
Sec
3
AMD S1g1
638 PIN
PACKAGE
x16
200/400/800
MHz
HyperTransport
nVIDIA
C51MV
BGA 468
X8 /X4
200/400/800
HyperTransport
nVIDIA
MCP51
BGA 508
IDE BUS
3
REVISION: 2.0
128-BIT
Channel A/B
LVDS
CRT
TV OUT
MHz
33MHz
PCI BUS
MINI-PCI
/WIRE LESS
SATA 2 /SATA
USB BUS
USB
CCD
USB 2.0 X4
2
Unbuffer
DDR2
SO-DIMM
R5C841
BLUE
TOOTH
2
PCMCIA
1394
CARD READER
MiniCard
/WIRE LESS
1
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
C
Date: Sheet
Engineer:
A6M
1
BLOCK DIAGRAM
Jefing_Li
of
173Friday, March 10, 2006
Rev
1.0
A
5
A
4
3
2
1
SKT638 S1 CPU
D D
RESET#
PWROK
C51MV
G73M
HT_CPU_PWRGD
C C
PE_RESET#
PCIE RST*
HT_CPU_RST#
HT_MCP_PWRGD
HT_MCP_RESET#
CPU_PWROK
CPU_RESET#
RESET MAP
MCP51
POWER SWTCH
RESET Button
KBC
B B
PWRBTN#
RSTBTN#
KBRST#
HT_VLD
HTVDD_EN
CPU_VLD
CPUVDD_EN
PWRGD
SUSB#
MEM_VLD
SUSC#
PWRGD_SB
PWRBTN#
RSTBTN#
KBRDRSTIN#
HT_VLD
HTVDD_EN
CPU_VLD
CPUVDD_EN
PWRGD
SLP_S3#
MEM VLD
SLP_S5#
PWRGD_SB
HT_MCP_RST#
HT_MCP_PWRGD
PCI RST0#
PCI RST1#
PCI RST2#
PCI RST3#
LPC_RST#
AC_RESET#
HT_MCP_RST#
HT_MCP_PWRGD
MINI_PCI_RST#
CARD_PCI_RST#
LAN_PCI_RST#
PCI_IDE_RST#
LPC_RST#
AC_RESET#
MDC
AUDIO
SIO
FLASH
KBC
IDE
CD ROM
88E8001.
CARDBUS
MINI PCI
A
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
A3
5
4
3
2
Date: Sheet
A6T
Engineer:
1
RESET MAP
Jefing_Li
of
273Monday, March 06, 2006
Rev
1.0
5
A
4
3
2
1
CLOCK MAP
SKT638 S1 CPU
HT_CPU_RXCLK0
D D
C C
B B
HT_CPU_RXCLK0*
HT_CPU_TXCLK0
HT_CPU_TXCLK0*
HT_CPU_RXCLK1
HT_CPU_RXCLK1*
HT_CPU_TXCLK1
HT_CPU_TXCLK1*
CPUCLK_IN*
CPUCLK_IN
CLKOUT_200MHZ
CLKOUT_200MHZ*
HT_CPU_RXCLK1*
HT_CPU_RXCLK1
HT_CPU_TXCLK1*
HT_CPU_TXCLK1
HT_CPU_RXCLK0*
HT_CPU_RXCLK0
HT_CPU_TXCLK0*
HT_CPU_TXCLK0
HT_MCP_RXCLK0
HT_MCP_RXCLK0*
HT_MCP_TXCLK0
HT_MCP_TXCLK0*
CLKIN_25MHZ
CLKIN_200MHZ*
CLKIN_200MHZ
MCPCLK_OUT
MCPCLK_OUT*
25MHZ_CLKOUT
HT_MCP_RXCLK0*
HT_MCP_RXCLK0
HT_MCP_TXCLK0*
HT_MCP_TXCLK0
C51M
MCP51M
MEMORY_A_CLK[2:1]
MEMORY_A_CLK[2:1]*
MEMORY_B_CLK[2:1]
MEMORY_B_CLK[2:1]*
PE0_REFCLK
PE0_REFCLK*
PE1_REFCLK
PE1_REFCLK*
PE2_REFCLK
PE2_REFCLK*
XTAL_IN
XTAL_OUT
BUF_SIO
SUSCLK
LPC_CLK0
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK_FB
LPC_CLK1
14.31818MHZ
33MHZ
33MHZ
33MHZ
2
2
2
2
SO-DIMM 0
G73M
SO-DIMM 1
SIO
MINI PCI
R5C841
CARDBUS
CONTROLLER
KBC
32.768 KHZ
25.0 MHZ
RTC_XTAL
XTAL_IN
XTAL_OUT
BUF_25MHZ
MII_RXCLK
MII_TXCLK
AC_BITCLK
AC_BITCLK
FLASH
MDC
88E8001
A
24MHZ
5
4
3
ALC880
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
A3
Date: Sheet
A6T
Engineer:
2
1
CLOCK MAP
Jefing_Li
373Monday, March 06, 2006
of
Rev
1.0
5
A
4
3
2
1
HT_CPU_TX_CLK_H1[10]
D D
LAYOUT: PLACE NEAR CPU
STUFF WHEN CONFIGURED AS
16-BIT LINK
+1.2V_HT
R401 49.9Ohm
1 2
R402 49.9Ohm
1 2
HT_CPU_TX_CAD_L[0..15][10]
HT_CPU_TX_CAD_H[0..15][10]
HT_CPU_TX_CLK_L1[10]
HT_CPU_TX_CLK_H0[10]
HT_CPU_TX_CLK_L0[10]
HT_CPU_TX_CTL_H0[10]
HT_CPU_TX_CTL_L0[10]
C C
HT_CPU_TX_CLK_H1
HT_CPU_TX_CLK_L1
HT_CPU_TX_CLK_H0
HT_CPU_TX_CLK_L0
HT_CPU_TX_CTL_H1
HT_CPU_TX_CTL_L1
HT_CPU_TX_CTL_H0
HT_CPU_TX_CTL_L0
HT_CPU_TX_CAD_H15
HT_CPU_TX_CAD_L15
HT_CPU_TX_CAD_H14
HT_CPU_TX_CAD_L14
HT_CPU_TX_CAD_H13
HT_CPU_TX_CAD_L13
HT_CPU_TX_CAD_H12
HT_CPU_TX_CAD_L12
HT_CPU_TX_CAD_H11
HT_CPU_TX_CAD_L11
HT_CPU_TX_CAD_H10
HT_CPU_TX_CAD_L10
HT_CPU_TX_CAD_H9
HT_CPU_TX_CAD_L9
HT_CPU_TX_CAD_H8
HT_CPU_TX_CAD_L8
HT_CPU_TX_CAD_H7
HT_CPU_TX_CAD_L7
HT_CPU_TX_CAD_H6
HT_CPU_TX_CAD_L6
HT_CPU_TX_CAD_H5
HT_CPU_TX_CAD_L5
HT_CPU_TX_CAD_H4
HT_CPU_TX_CAD_L4
HT_CPU_TX_CAD_H3
HT_CPU_TX_CAD_L3
HT_CPU_TX_CAD_H2
HT_CPU_TX_CAD_L2
HT_CPU_TX_CAD_H1
HT_CPU_TX_CAD_L1
HT_CPU_TX_CAD_H0
HT_CPU_TX_CAD_L0
J5
K5
J3
J2
P3
P4
N1
P1
N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2
U1A
SOCKET638
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
HYPERTRANSPORT
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
HT_CPU_RX_CLK_H1
Y4
HT_CPU_RX_CLK_L1
Y3
HT_CPU_RX_CLK_H0
Y1
HT_CPU_RX_CLK_L0
W1
HT_CPU_RX_CTL_H1
T5
HT_CPU_RX_CTL_L1
R5
HT_CPU_RX_CTL_H0
R2
HT_CPU_RX_CTL_L0
R3
HT_CPU_RX_CAD_H15
T4
HT_CPU_RX_CAD_L15
T3
HT_CPU_RX_CAD_H14
V5
HT_CPU_RX_CAD_L14
U5
HT_CPU_RX_CAD_H13
V4
HT_CPU_RX_CAD_L13
V3
HT_CPU_RX_CAD_H12
Y5
HT_CPU_RX_CAD_L12
W5
HT_CPU_RX_CAD_H11
AB5
HT_CPU_RX_CAD_L11
AA5
HT_CPU_RX_CAD_H10
AB4
HT_CPU_RX_CAD_L10
AB3
HT_CPU_RX_CAD_H9
AD5
HT_CPU_RX_CAD_L9
AC5
HT_CPU_RX_CAD_H8
AD4
HT_CPU_RX_CAD_L8
AD3
HT_CPU_RX_CAD_H7
T1
HT_CPU_RX_CAD_L7
R1
HT_CPU_RX_CAD_H6
U2
HT_CPU_RX_CAD_L6
U3
HT_CPU_RX_CAD_H5
V1
HT_CPU_RX_CAD_L5
U1
HT_CPU_RX_CAD_H4
W2
HT_CPU_RX_CAD_L4
W3
HT_CPU_RX_CAD_H3
AA2
HT_CPU_RX_CAD_L3
AA3
HT_CPU_RX_CAD_H2
AB1
HT_CPU_RX_CAD_L2
AA1
HT_CPU_RX_CAD_H1
AC2
HT_CPU_RX_CAD_L1
AC3
HT_CPU_RX_CAD_H0
AD1
HT_CPU_RX_CAD_L0
AC1
HT_CPU_RX_CLK_H1 [10]
HT_CPU_RX_CLK_L1 [10]
HT_CPU_RX_CLK_H0 [10]
HT_CPU_RX_CLK_L0 [10]
T401 TPC26TN/A
1
T402 TPC26TN/A
1
HT_CPU_RX_CTL_H0 [10]
HT_CPU_RX_CTL_L0 [10]
HT_CPU_RX_CAD_L[0..15] [10]
HT_CPU_RX_CAD_H[0..15] [10]
Do not cross plane.
U1E
P20
RSVD_MA0_CLK_H3
P19
RSVD_MA0_CLK_L3
N20
RSVD_MA0_CLK_H0
N19
RSVD_MA0_CLK_L0
B B
R26
RSVD_MB0_CLK_H3
R25
RSVD_MB0_CLK_L3
P22
RSVD_MB0_CLK_H0
R22
RSVD_MB0_CLK_L0
SOCKET638
RSVD_MA_RESET_L
RSVD_MB_RESET_L
RSVD_VIDSTRB1
RSVD_VIDSTRB0
RSVD_VDDNB_FB_H
RSVD_VDDNB_FB_L
RSVD_CORE_TYPE
MISC
INTERNAL
FREE5
FREE6
FREE4
FREE1
FREE2
FREE3
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
A
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
A3
5
4
3
2
Date: Sheet
A6T
Engineer:
1
S1_HT_C51
Jefing_Li
473Thursday, March 09, 2006
of
Rev
1.0
5
A
4
3
2
1
C502
1.5PF/50V
C504
1.5PF/50V
MEM_MB0_CLK_H2
12
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
12
MEM_MB0_CLK_L1
U1C
AF18
MB0_CLK_H2
AF17
MB0_CLK_L2
A17
MB0_CLK_H1
A18
MB0_CLK_L1
Y26
MB0_CS_L3
J24
MB0_CS_L2
W24
MB0_CS_L1
U23
MB0_CS_L0
W23
MB0_ODT1
W26
MB0_ODT0
V26
MB_CAS_L
U22
MB_WE_L
U24
MB_RAS_L
K26
MB_BANK2
T26
MB_BANK1
U26
MB_BANK0
H26
MB_CKE1
J23
MB_CKE0
J25
MB_ADD15
J26
MB_ADD14
W25
MB_ADD13
L23
MB_ADD12
L25
MB_ADD11
U25
MB_ADD10
L24
MB_ADD9
M26
MB_ADD8
L26
MB_ADD7
N23
MB_ADD6
N24
MB_ADD5
N25
MB_ADD4
N26
MB_ADD3
P24
MB_ADD2
P26
MB_ADD1
T24
MB_ADD0
AF12
MB_DQS_H7
AE12
MB_DQS_L7
AE16
MB_DQS_H6
AD16
MB_DQS_L6
AF21
MB_DQS_H5
AF22
MB_DQS_L5
AC25
MB_DQS_H4
AC26
MB_DQS_L4
F26
MB_DQS_H3
E26
MB_DQS_L3
A24
MB_DQS_H2
A23
MB_DQS_L2
D16
MB_DQS_H1
C16
MB_DQS_L1
C12
MB_DQS_H0
B12
MB_DQS_L0
AD12
MB_DM7
AC16
MB_DM6
AE22
MB_DM5
AB26
MB_DM4
E25
MB_DM3
A22
MB_DM2
B16
MB_DM1
A12
MB_DM0
SOCKET638
MEMORY
INTERFACE
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11
MEM_MB_DATA63
MEM_MB_DATA62MEM_MA0_CLK_L1
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41MEM_MB_ADD15
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MA0_CLK_H2
MEM_MA0_CLK_H2[8]
MEM_MA0_CLK_L2[8]
MEM_MA0_CLK_H1[8]
D D
C C
MEM_MA0_CLK_L1[8]
MEM_MA0_CS_L[0..3][8,9]
MEM_MA0_ODT[0..1][8,9]
MEM_MA_CAS_L[8,9]
MEM_MA_WE_L[8,9]
MEM_MA_RAS_L[8,9]
MEM_MA_BANK[0..2][8,9]
MEM_MA_CKE[0..1][8,9]
MEM_MA_ADD[0..15][8,9]
MEM_MA_DQS_H[0..7][8]
MEM_MA_DQS_L[0..7][8]
B B
MEM_MA_DM[0..7][8]
12
C501
MEM_MA0_CLK_L2
1.5PF/50V
MEM_MA0_CLK_H1
12
C503
MEM_MA0_CLK_L1
1.5PF/50V
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CS_L3
MEM_MA0_CS_L2
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT1 MEM_MB_DATA55
MEM_MA0_ODT0 MEM_MB_DATA54
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
the cap close to cpu less than 1200mil
max neckdown to & from caps is 500mil
U1B
Y16
MA0_CLK_H2
AA16
MA0_CLK_L2
M19
M20
M24
M22
N22
N21
R21
W12
W13
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
AB16
AC24
E19
C15
E12
E16
F16
V19
J22
V22
T19
V20
U19
U20
U21
T20
K22
R20
T22
J20
J21
K19
K20
V24
K24
L20
R19
L19
L22
L21
Y15
Y13
Y19
F24
MA0_CLK_H1
MA0_CLK_L1
MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0
MA0_ODT1
MA0_ODT0
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK2
MA_BANK1
MA_BANK0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
SOCKET638
MEMORY
INTERFACE
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
AA12
MEM_MA_DATA62
AB12
MEM_MA_DATA61
AA14
MEM_MA_DATA60
AB14
MEM_MA_DATA59
W11
MEM_MA_DATA58
Y12
MEM_MA_DATA57
AD13
MEM_MA_DATA56
AB13
MEM_MA_DATA55
AD15
MEM_MA_DATA54
AB15
MEM_MA_DATA53
AB17
MEM_MA_DATA52
Y17
MEM_MA_DATA51
Y14
MEM_MA_DATA50
W14
MEM_MA_DATA49
W16
MEM_MA_DATA48 MEM_MB_BANK2
AD17
MEM_MA_DATA47
Y18
MEM_MA_DATA46
AD19
MEM_MA_DATA45
AD21
MEM_MA_DATA44
AB21
MEM_MA_DATA43
AB18
MEM_MA_DATA42
AA18
MEM_MA_DATA41
AA20
MEM_MA_DATA40
Y20
AA22
MEM_MA_DATA38
Y22
MEM_MA_DATA37
W21
MEM_MA_DATA36
W22
MEM_MA_DATA35
AA21
MEM_MA_DATA34
AB22
MEM_MA_DATA33
AB24
MEM_MA_DATA32
Y24
MEM_MA_DATA31
H22
H20
MEM_MA_DATA29
E22
MEM_MA_DATA28
E21
MEM_MA_DATA27
J19
MEM_MA_DATA26
H24
MEM_MA_DATA25
F22
MEM_MA_DATA24
F20
MEM_MA_DATA23
C23
MEM_MA_DATA22
B22
MEM_MA_DATA21
F18
MEM_MA_DATA20
E18
MEM_MA_DATA19
E20
MEM_MA_DATA18
D22
MEM_MA_DATA17
C19
MEM_MA_DATA16
G18
MEM_MA_DATA15
G17
MEM_MA_DATA14
C17
MEM_MA_DATA13
F14
MEM_MA_DATA12
E14
MEM_MA_DATA11
H17
MEM_MA_DATA10
E17
MEM_MA_DATA9
E15
MEM_MA_DATA8
H15
MEM_MA_DATA7
E13
MEM_MA_DATA6
C13
MEM_MA_DATA5
H12
MEM_MA_DATA4
H11
MEM_MA_DATA3
G14
MEM_MA_DATA2
H14
MEM_MA_DATA1
F12
MEM_MA_DATA0
G12
MEM_MA_DATA[0..63] [8] MEM_MB_DATA[0..63] [8]
MEM_MB0_CS_L[0..3][8,9]
MEM_MB0_ODT[0..1][8,9]
MEM_MB_CAS_L[8,9]
MEM_MB_WE_L[8,9]
MEM_MB_RAS_L[8,9]
MEM_MB_BANK[0..2][8,9]
MEM_MB_CKE[0..1][8,9]
MEM_MB_ADD[0..15][8,9]
MEM_MB_DQS_H[0..7][8]
MEM_MB_DQS_L[0..7][8]
MEM_MB_DM[0..7][8]
MEM_MB0_CLK_H2[8]
MEM_MB0_CLK_L2[8]
MEM_MB0_CLK_H1[8]
MEM_MB0_CLK_L1[8]
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1MEM_MA_DATA63
MEM_MB0_CLK_L1
MEM_MB0_CS_L3
MEM_MB0_CS_L2
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT1
MEM_MB0_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MB_ADD14
MEM_MB_ADD13MEM_MA_DATA39
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4MEM_MA_DATA30
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
A
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
A3
5
4
3
2
Date: Sheet
A6T
Engineer:
S1_DDR2
Jefing_Li
573Thursday, March 09, 2006
Rev
1.0
of
1
5
A
+2.5VS
R601
1KOhm
1 2
CPU_PWROK[10]
1 2
147
U2A
VCC
GND
SN74LVC07APWR
+1.8V
R602 300Ohm
_CPU_PWROK
1 2
D D
+1.8V+3VSUS+2.5VS
147
U2B
VCC
3 4
GND
SN74LVC07APWR
147
U2C
VCC
GND
SN74LVC07APWR
+3VSUS
147
VCC
9 8
GND
147
U2E
VCC
GND
SN74LVC07APWR
R604 300Ohm
1 2
+1.8V+3VSUS
R610 300Ohm
_CPU_RESET#
1 2
+3VS
U2D
SN74LVC07APWR
+3VSUS
R7119 0Ohm
1 2
_CPU_LDTSTOP#
R629
1KOhm
/X
1 2
_PWROK
_CPU_PWROK
R7113
0Ohm
1 2
147
U2F
VCC
13 12
GND
SN74LVC07APWR
R7117 0Ohm
1 2
R603
1KOhm
/X
_PWROK
+2.5VS
1 2
1 2
R7114
0Ohm
/X
_PWROK
1 2
R609
1KOhm
5 6
11 10
CPU_LDTSTOP#[10]
CPU_RESET#[10]
C C
3/1
HT_VLD
_HT_MCP_PWRGD[16]
R7115 0Ohm
1 2
R7150 0Ohm
1 2
HT_VLD[16,64]
_HT_MCP_PWRGD
CPU_CLK_H[10]
CPU_CLK_L[10]
CPU_VDD_FB[61]
CPU_VDD_FB#[61]
Keep trace to
resistors less
than 1.5" from
CPU pin
_CPU_LDTSTOP#
4
+2.5VS +2.5V_VDDA+3VSUS
C601
12
100UF/6.3V
close to the ferrite bead
Keep trace to resistors
less than 600mils from
CPU pin and trace to AC
caps less than 1250mils
CPU_CLK_H
CPU_CLK_L
Not use,
pull up.
C606
12
3900PF/50V
C607
12
3900PF/50V
R607 300Ohm
route as diff
pair
5/5/5,10mil
+1.8V
R612 39.2Ohm
1 2
R615 39.2Ohm
1 2
R616 300Ohm
1 2
R618 300Ohm
1 2
CPU_THERMADC[15]
CPU_THERMADA[15]
169Ohm
4.7UF/6.3V
R605
12
30Ohm/100Mhz
T614 TPC26TN/A
T616 TPC26TN/A
T618 TPC26TN/A
T619 TPC26TN/A
T621 TPC26TN/A
L601
21
12
C602
0.22UF/6.3V
1 2
_CPU_PWROK
_CPU_LDTSTOP#
_CPU_RESET#
CPU_PRESENT#
CPU_SIC
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS
CPU_DBREQ#
CPU_VCORE_FB_H
CPU_VCORE_FB_L
CPU_VTT_SENSE
CPU_M_VREF
CPU_TEST25_H
CPU_TEST25_L
1
1
1
1
1
CPU_THERMADC
CPU_THERMADA
12
C603
+2.5V_VDDA
12
C604
3300PF/50V
Need decoupling
capacitors
U1D
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
A7
PWROK
F10
LDTSTOP_L
B7
RESET_L
AC6
CPU_PRESENT_L
AF4
SIC
AF5
SID
AF9
TDI
AD9
TRST_L
AC9
TCK
AA9
TMS
E10
DBREQ_L
F6
VDD_FB_H
E6
VDD_FB_L
Y10
VTT_SENSE
W17
M_VREF
AE10
M_ZN
AF10
M_ZP
E9
TEST25_H
E8
TEST25_L
G9
TEST19
H10
TEST18
AA7
TEST13
C2
TEST9
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
AC8
TEST12
C3
TEST7
AA6
TEST6
W7
THERMDC
W8
THERMDA
Y6
TEST3
AB6
TEST2
SOCKET638
3
THERMTRIP_L
PROCHOT_L
MISC
VDDIO_FB_H
VDDIO_FB_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
0.1UF/10V
VID5
VID4
VID3
VID2
VID1
VID0
TDO
DBRDY
PSI_L
TEST8
C605
+1.8V
12
A5
C6
A6
A4
C5
B5
AF6
AC7
AE9
G10
W9
Y9
A3
P6
R6
C9
C8
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
2
VDDIO +1.8V
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
+1.8V
Required for
R606
compatibility
with future
300Ohm
processors
1 2
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
_CPU_THERMTRIP#
_CPU_PROCHOT# +1.8V_DRAM_FB
CPU_TDO
CPU_DBRDY
+1.8V_DRAM_FB
+1.8V_DRAM_FB#
CPU_PSI#
CPU_TEST29_H
CPU_TEST29_L
T613 TPC26TN/A
T615 TPC26TN/A
T617 TPC26TN/A
CPU_TEST21
T620 TPC26TN/A
CPU_TEST26
R611 44.2Ohm
R613 44.2Ohm
1 2
1 2
1
1
1
1
CPU_PSI# [61]
R617
80.6Ohm
CPU_VID[0..5] [61]
_CPU_THERMTRIP# [9]
_CPU_PROCHOT# [9]
+1.2V_HT
Route as 80Ohm
differential
impedance.
Keep trace to
resistors less
1 2
than 1" from
CPU pin
Keep trace to
resistors less
than 1.5" from
CPU pin
+1.8V
CPU_VTT_SENSE
Erratum 133,
Revision Guide
for AMD NPT
0Fh Processors
CPU_TEST26
CPU_PRESENT#
CPU_TEST25_H
CPU_TEST25_L
CPU_TEST21
P601
1
NC
3
DBREQ_L1
5
DBRDY1
7
DBREQ_L2
9
DBRDY2
11
DBREQ_L3
13
DBRDY3
15
DBREQ_L4
17
DBRDY4
19
DBREQ_L5
DBREQ_L7
21
DBRDY5
23
DBREQ_L6
ASP_68200_07_K25
/X
CPU_CLK_H
CPU_CLK_L
CPU_VCORE_FB_H
CPU_VCORE_FB_L
CPU_TEST29_H
CPU_TEST29_L
+1.8V_DRAM_FB#
_CPU_PWROK
_CPU_LDTSTOP#
_CPU_RESET#
_CPU_THERMTRIP#
1 2
R619 300Ohm
1 2
R620 1KOhm
1 2
R621 510Ohm
1 2
R622 510Ohm
1 2
R623 300Ohm
1 2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
DBRDY7
DBRDY6
GND9
GND10
T601 TPC26TN/A
T602 TPC26TN/A
T603 TPC26TN/A
T604 TPC26TN/A
T605 TPC26TN/A
T606 TPC26TN/A
T607 TPC26TN/A
T608 TPC26TN/A
T609 TPC26TN/A
T610 TPC26TN/A
T611 TPC26TN/A
T612 TPC26TN/A
R614
0Ohm /x
1
2
4
6
8
10
12
14
16
18
20
22
H_CPU_RESET#
24
26
1
1
1
1
1
1
1
1
1
1
1
1
+0.9V
+1.8V
R634
8.2KOhm
Q601A
UM6K1N
2
3/1
+3VS
12
H_CPU_RESET#
61
3/1
+1.8V
CPU_M_VREF
15mil trace.20mil space
R624
2KOhm
shorter than 6 inches
1%
R628
2KOhm
CPU_M_VREF
12
12
C608
C609
1000PF/50V
1%
0.1UF/10V
final_1.00
Title :
S1_CNTL/DEBUG/THERM
ASUSTECH CO.,LTD.
Size Project Name
C
3
2
Date: Sheet
Engineer:
A6T
Jefing_Li
Rev
1.0
of
673Thursday, March 09, 2006
1
1 2
1 2
4
B B
12
R633
8.2KOhm
34
Q601B
UM6K1N
CPU_RESET#
5
GND
5
A
5
A
4
3
2
1
DRAM_VTT 0.9V
+VCORE
+VCORE
D D
C C
+VCORE
12
C701
22UF/6.3V
C735
22UF/6.3V
AC4
AD2
K10
K12
K14
L11
L13
M10
N11
P10
R11
T10
T12
T14
U11
U13
V10
V12
V14
12
G4
H2
J9
J11
J13
K6
L4
L7
L9
M2
M6
M8
N7
N9
P8
R4
R7
R9
T2
T6
T8
U7
U9
V6
V8
W4
Y2
22UF/6.3V
U1F
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
SOCKET638
C736
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
VDD
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
place under socket on bottom side
12
C737
22UF/6.3V
12
C738
22UF/6.3V
12
C739
22UF/6.3V
+1.8V
12
+1.2V_HT
+0.9V
D10
C10
B10
AD10
W10
H25
K18
K21
K23
K25
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
D4
D3
D2
D1
J17
L17
U1H
VLDT_A4
VLDT_A3
VLDT_A2
VLDT_A1
VTT8
VTT7
VTT6
VTT5
VTT9
VDDIO23
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO24
VDDIO25
VDDIO26
VDDIO27
SOCKET638
I O
POWER
VLDT_B4
VLDT_B3
VLDT_B2
VLDT_B1
VTT4
VTT3
VTT2
VTT1
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
AE5
AE4
AE3
AE2
AC10
AB10
AA10
A10
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
4.7UF/16V
C706
+0.9V
12
J15
K16
L15
M16
P16
T16
U15
V16
U1G
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD
SOCKET638
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS130
VSS131
VSS132
VSS133
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
+1.8V
+1.8V
+1.8V
+1.8V
place close to socket
C702
0.22UF/6.3V
C707
4.7UF/6.3V
C711
0.01UF/10V
12
12
12
C703
0.22UF/6.3V
C708
4.7UF/6.3V
C712
0.01UF/10V
12
12
12
C704
0.22UF/6.3V
C709
4.7UF/6.3V
C713
180PF/50V
12
12
12
0.22UF/6.3V
4.7UF/6.3V
place under socket on bottom side
C715
22UF/6.3V
+0.9V
4.7UF/6.3V
+0.9V
0.22UF/6.3V
+0.9V
1000PF/50V
+0.9V
180PF/50V
C719
C723
C727
C731
12
C716
22UF/6.3V
12
4.7UF/6.3V
12
0.22UF/6.3V
12
1000PF/50V
12
12
C720
C724
C728
C732
180PF/50V
12
C717
0.22UF/6.3V
place close to socket
12
12
12
12
0.22UF/6.3V
C721
4.7UF/6.3V
C725
0.22UF/6.3V
C729
1000PF/50V
C733
180PF/50V
C718
12
12
12
12
4.7UF/6.3V
0.22UF/6.3V
1000PF/50V
C705
C710
C714
180PF/50V
12
C722
C726
C730
C734
180PF/50V
12
12
12
12
12
12
12
B B
+VCORE
C743
22UF/6.3V
12
C744
22UF/6.3V
5
12
C745
22UF/6.3V
12
C746
0.22UF/6.3V
12
0.22UF/6.3V
C747
12
0.01UF/10V
C748
12
180PF/50V
4
C749
12
3
C740
4.7UF/6.3V
+1.2V_HT
0.22UF/6.3V
2
C750
+1.2V_HT
12
12
C751
0.22UF/6.3V
+1.2V_HT
4.7UF/6.3V
12
final_1.00
place close to socket
12
C741
12
C752
180PF/50V
C742
4.7UF/6.3V
180PF/50V
C753
12
12
Title :
ASUSTECH CO.,LTD.
Size Project Name
A3
Date: Sheet
A6T
Engineer:
1
S1_POWER
Jefing_Li
773Monday, March 06, 2006
of
Rev
1.0
A
5
A
4
3
2
1
MEM_MA_DATA[0..63] [5]
MEM_MA_ADD[0..15][5,9]
D D
MEM_MA_BANK2[5,9]
MEM_MA_BANK0[5,9]
MEM_MA_BANK1[5,9]
MEM_MA0_CS_L0[5,9]
MEM_MA0_CS_L1[5,9]
MEM_MA0_CLK_H1[5]
MEM_MA0_CLK_L1[5]
MEM_MA0_CLK_H2[5]
MEM_MA0_CLK_L2[5]
MEM_MA_CKE0[5,9]
MEM_MA_CKE1[5,9]
MEM_MA_CAS_L[5,9]
MEM_MA_RAS_L[5,9]
MEM_MA_WE_L[5,9]
MEM_MA0_ODT0[5,9]
MEM_MA0_ODT1[5,9]
C C
MEM_MA_DM[0..7][5]
MEM_MA_DQS_H[0..7][5]
MEM_MA_DQS_L[0..7][5]
+1.8V
12
12
C801
4.7UF/6.3V
B B
+1.8V
12
C813
10UF/10V
C802
4.7UF/6.3V
12
0.1UF/10V
C814
12
C803
1UF/16V
12
0.1UF/10V
12
C815
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3 MEM_MB_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
I2C_CLK0_S[15,19]
I2C_DATA0_S[15,19]
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DQS_H0
MEM_MA_DQS_H1
MEM_MA_DQS_H2
MEM_MA_DQS_H3
MEM_MA_DQS_H4
MEM_MA_DQS_H5
MEM_MA_DQS_H6
MEM_MA_DQS_H7
MEM_MA_DQS_L0
MEM_MA_DQS_L1
MEM_MA_DQS_L2
MEM_MA_DQS_L3
MEM_MA_DQS_L4
MEM_MA_DQS_L5
MEM_MA_DQS_L6
MEM_MA_DQS_L7
+3VS
MEM_M_VREF
C812
12
12
+1.8V
12
1KOhm
1KOhm
0.1UF/10V
C804
1UF/16V
12
0.1UF/10V
C816
R801
R804
12
C805
1UF/16V
CON1A
A102
A:A0
A101
A:A1
A100
A:A2
A99
A:A3
A98
A:A4
A97
A:A5
A94
A:A6
A92
A:A7
A93
A:A8
A91
A:A9
A105
A:A10/AP
A90
A:A11
A89
A:A12
A116
A:A13
A86
A:A14
A84
A:A15
A85
A:A16_BA2
A107
A:BA0
A106
A:BA1
A110
A:S0#
A115
A:S1#
A30
A:CK0
A32
A:CK0#
A164
A:CK1
A166
A:CK1#
A79
A:CKE0
A80
A:CKE1
A113
A:CAS#
A108
A:RAS#
A109
A:WE#
A198
A:SA0
A200
A:SA1
A197
A:SCL
A195
A:SDA
A114
A:ODT0
A119
A:ODT1
A10
A:DM0
A26
A:DM1
A52
A:DM2
A67
A:DM3
A130
A:DM4
A147
A:DM5
A170
A:DM6
A185
A:DM7
A13
A:DQS0
A31
A:DQS1
A51
A:DQS2
A70
A:DQS3
A131
A:DQS4
A148
A:DQS5
A169
A:DQS6
A188
A:DQS7
A11
A:DQS0#
A29
A:DQS1#
A49
A:DQS2#
A68
A:DQS3#
A129
A:DQS4#
A146
A:DQS5#
A167
A:DQS6#
A186
A:DQS7#
A112
A:VDD1
A96
A:VDD4
A118
A:VDD6
A82
A:VDD8
A88
A:VDD11
A104
A:VDD12
A12
A:VSS5
A48
A:VSS6
A184
A:VSS7
A78
A:VSS8
A72
A:VSS10
A122
A:VSS12
A196
A:VSS13
A8
A:VSS15
A18
A:VSS16
A24
A:VSS17
A42
A:VSS20
A199
A:VDDSPD
A1
A:VREF
DDR_DIMM_331P
MEM_MA_DATA3
A5
A:DQ0
MEM_MA_DATA7
A7
A:DQ1
MEM_MA_DATA5
A17
A:DQ2
MEM_MA_DATA2
A19
A:DQ3
MEM_MA_DATA0
A4
A:DQ4
MEM_MA_DATA6
A6
A:DQ5
MEM_MA_DATA4
A14
A:DQ6
MEM_MA_DATA1
A16
A:DQ7
MEM_MA_DATA8
A23
A:DQ8
MEM_MA_DATA9
A25
A:DQ9
MEM_MA_DATA15
A35
A:DQ10
MEM_MA_DATA11
A37
A:DQ11
MEM_MA_DATA12
A20
A:DQ12
MEM_MA_DATA13
A22
A:DQ13
MEM_MA_DATA14
A36
A:DQ14
MEM_MA_DATA10
A38
A:DQ15
MEM_MA_DATA23
A43
A:DQ16
MEM_MA_DATA22
A45
A:DQ17
MEM_MA_DATA19
A55
A:DQ18
MEM_MA_DATA18
A57
A:DQ19
MEM_MA_DATA17
A44
A:DQ20
MEM_MA_DATA20
A46
A:DQ21
MEM_MA_DATA16
A56
A:DQ22
MEM_MA_DATA21
A58
A:DQ23
MEM_MA_DATA24
A61
A:DQ24
MEM_MA_DATA25
A63
A:DQ25
MEM_MA_DATA26
A73
A:DQ26
MEM_MA_DATA31
A75
A:DQ27
MEM_MA_DATA28
A62
A:DQ28
MEM_MA_DATA29
A64
A:DQ29
MEM_MA_DATA30
A74
A:DQ30
MEM_MA_DATA27
A76
A:DQ31
MEM_MA_DATA36
A123
A:DQ32
MEM_MA_DATA38
A125
A:DQ33
MEM_MA_DATA34
A135
A:DQ34
MEM_MA_DATA35
A137
A:DQ35
MEM_MA_DATA33
A124
A:DQ36
MEM_MA_DATA32
A126
A:DQ37
MEM_MA_DATA39
A134
A:DQ38
MEM_MA_DATA37
A136
A:DQ39
MEM_MA_DATA45
A141
A:DQ40
MEM_MA_DATA44
A143
A:DQ41
MEM_MA_DATA47
A151
A:DQ42
MEM_MA_DATA46
A153
A:DQ43
MEM_MA_DATA40
A140
A:DQ44
MEM_MA_DATA41
A142
A:DQ45
MEM_MA_DATA42
A152
A:DQ46
MEM_MA_DATA43
A154
A:DQ47
MEM_MA_DATA48
A157
A:DQ48
MEM_MA_DATA53
A159
A:DQ49
MEM_MA_DATA50
A173
A:DQ50
MEM_MA_DATA51
A175
A:DQ51
MEM_MA_DATA49
A158
A:DQ52
MEM_MA_DATA52
A160
A:DQ53
MEM_MA_DATA55
A174
A:DQ54
MEM_MA_DATA54
A176
A:DQ55
MEM_MA_DATA57
A179
A:DQ56
MEM_MA_DATA56
A181
A:DQ57
MEM_MA_DATA62
A189
A:DQ58
MEM_MA_DATA58
A191
A:DQ59
MEM_MA_DATA60
A180
A:DQ60
MEM_MA_DATA61
A182
A:DQ61
MEM_MA_DATA63
A192
A:DQ62
MEM_MA_DATA59
A194
A:DQ63
A54
A:VSS21
A60
A:VSS24
A66
A:VSS25
A128
A:VSS28
A172
A:VSS32
A178
A:VSS35
A190
A:VSS36
A34
A:VSS41
A132
A:VSS42
A144
A:VSS43
A156
A:VSS44
A168
A:VSS45
A2
A:VSS46
A28
A:VSS53
A40
A:VSS54
A138
A:VSS55
A150
A:VSS56
A162
A:VSS57
A83
A:NC1
A120
A:NC2
A50
A:NC3
A69
A:NC4
A163
NP_NC1
201
202
A:NCTEST
NP_NC2
NP_NC3
NP_NC4
GND1
GND2
GND4
GND3
203
204
205
206
207
208
MEM_MA0_CS_L2 [5,9]
MEM_MA0_CS_L3 [5,9]
4.7UF/6.3V
+3VS
C806
+1.8V
+1.8V
12
12
C817
10UF/10V
MEM_MB_ADD[0..15][5,9]
MEM_MB_DM[0..7][5]
MEM_MB_DQS_H[0..7][5]
MEM_MB_DQS_L[0..7][5]
12
C807
4.7UF/6.3V
12
0.1UF/10V
C818
1KOhm
1KOhm
B102
B101
B100
B99
B98
B97
B94
B92
B93
B91
B105
B90
B89
B116
B86
B84
B85
B107
B106
B110
B115
B30
B32
B164
B166
B79
B80
B113
B108
B109
B198
B200
B197
B195
B114
B119
B10
B26
B52
B67
B130
B147
B170
B185
B13
B31
B51
B70
B131
B148
B169
B188
B11
B29
B49
B68
B129
B146
B167
B186
B111
B117
B95
B81
B87
B103
B47
B133
B183
B77
B71
B121
B193
B41
B53
B59
B65
B199
B1
CON1B
B:A0
B:A1
B:A2
B:A3
B:A4
B:A5
B:A6
B:A7
B:A8
B:A9
B:A10/AP
B:A11
B:A12
B:A13
B:A14
B:A15
B:A16_BA2
B:BA0
B:BA1
B:S0#
B:S1#
B:CK0
B:CK0#
B:CK1
B:CK1#
B:CKE0
B:CKE1
B:CBS#
B:RAS#
B:WE#
B:SA0
B:SA1
B:SCL
B:SDA
B:ODT0
B:ODT1
B:DM0
B:DM1
B:DM2
B:DM3
B:DM4
B:DM5
B:DM6
B:DM7
B:DQS0
B:DQS1
B:DQS2
B:DQS3
B:DQS4
B:DQS5
B:DQS6
B:DQS7
B:DQS0#
B:DQS1#
B:DQS2#
B:DQS3#
B:DQS4#
B:DQS5#
B:DQS6#
B:DQS7#
B:VDD2
B:VDD3
B:VDD5
B:VDD7
B:VDD9
B:VDD10
B:VSS1
B:VSS2
B:VSS3
B:VSS4
B:VSS9
B:VSS11
B:VSS14
B:VSS18
B:VSS19
B:VSS22
B:VSS23
B:VDDSPD
B:VREF
DDR_DIMM_331P
B:DQ0
B:DQ1
B:DQ2
B:DQ3
B:DQ4
B:DQ5
B:DQ6
B:DQ7
B:DQ8
B:DQ9
B:DQ10
B:DQ11
B:DQ12
B:DQ13
B:DQ14
B:DQ15
B:DQ16
B:DQ17
B:DQ18
B:DQ19
B:DQ20
B:DQ21
B:DQ22
B:DQ23
B:DQ24
B:DQ25
B:DQ26
B:DQ27
B:DQ28
B:DQ29
B:DQ30
B:DQ31
B:DQ32
B:DQ33
B:DQ34
B:DQ35
B:DQ36
B:DQ37
B:DQ38
B:DQ39
B:DQ40
B:DQ41
B:DQ42
B:DQ43
B:DQ44
B:DQ45
B:DQ46
B:DQ47
B:DQ48
B:DQ49
B:DQ50
B:DQ51
B:DQ52
B:DQ53
B:DQ54
B:DQ55
B:DQ56
B:DQ57
B:DQ58
B:DQ59
B:DQ60
B:DQ61
B:DQ62
B:DQ63
B:VSS26
B:VSS27
B:VSS29
B:VSS30
B:VSS31
B:VSS33
B:VSS34
B:VSS37
B:VSS38
B:VSS39
B:VSS40
B:VSS47
B:VSS48
B:VSS49
B:VSS50
B:VSS51
B:VSS52
B:NC1
B:NC2
B:NC3
B:NC4
B:NCTEST
B5
B7
B17
B19
B4
B6
B14
B16
B23
B25
B35
B37
B20
B22
B36
B38
B43
B45
B55
B57
B44
B46
B56
B58
B61
B63
B73
B75
B62
B64
B74
B76
B123
B125
B135
B137
B124
B126
B134
B136
B141
B143
B151
B153
B140
B142
B152
B154
B157
B159
B173
B175
B158
B160
B174
B176
B179
B181
B189
B191
B180
B182
B192
B194
B127
B139
B145
B165
B171
B177
B187
B9
B21
B33
B155
B3
B15
B27
B39
B149
B161
B83
B120
B50
B69
B163
MEM_MB_DATA5
MEM_MB_DATA7
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DATA6
MEM_MB_DATA4
MEM_MB_DATA13
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA8
MEM_MB_DATA12
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA22
MEM_MB_DATA20
MEM_MB_DATA18
MEM_MB_DATA16
MEM_MB_DATA21
MEM_MB_DATA17
MEM_MB_DATA19
MEM_MB_DATA23
MEM_MB_DATA29
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA24
MEM_MB_DATA28
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA44
MEM_MB_DATA40
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA41
MEM_MB_DATA45
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA57
MEM_MB_DATA63
MEM_MB_DATA56
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_BANK2[5,9]
MEM_MB_BANK0[5,9]
MEM_MB_BANK1[5,9]
MEM_MB0_CS_L0[5,9]
MEM_MB0_CS_L1[5,9]
MEM_MB0_CLK_H1[5]
MEM_MB0_CLK_L1[5]
MEM_MB0_CLK_H2[5]
MEM_MB0_CLK_L2[5]
MEM_MB_CKE0[5,9]
MEM_MB_CKE1[5,9]
MEM_MB_CAS_L[5,9]
MEM_MB_RAS_L[5,9]
MEM_MB_WE_L[5,9]
MEM_MB0_ODT0[5,9]
MEM_MB0_ODT1[5,9]
12
C808
1UF/16V
12
C819
0.1UF/10V
MEM_MB_ADD15
R802
12
R803
12
I2C_CLK0_S
I2C_DATA0_S
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB_DQS_H0
MEM_MB_DQS_H1
MEM_MB_DQS_H2
MEM_MB_DQS_H3
MEM_MB_DQS_H4
MEM_MB_DQS_H5
MEM_MB_DQS_H6
MEM_MB_DQS_H7
MEM_MB_DQS_L0
MEM_MB_DQS_L1
MEM_MB_DQS_L2
MEM_MB_DQS_L3
MEM_MB_DQS_L4
MEM_MB_DQS_L5
MEM_MB_DQS_L6
MEM_MB_DQS_L7 MEM_MB_DATA62
+1.8V
12
12
C809
C810
1UF/16V
1UF/16V
+3VS
MEM_M_VREF
12
C811
0.1UF/10V
12
C820
0.1UF/10V
MEM_MB_DATA[0..63] [5]
MEM_MB0_CS_L2 [5,9]
MEM_MB0_CS_L3 [5,9]
MEM_M_VREF
+1.8V
15mil trace.20mil space
shorter than 6 inches
R805
2KOhm
1%
1 2
1 2
5
R806
2KOhm
1%
12
C821
0.1UF/10V
1000PF/50V
C822
MEM_M_VREF
12
A
final_1.00
Title :
DDR2_SODIMM
ASUSTECH CO.,LTD.
Size Project Name
C
4
3
2
Date: Sheet
Engineer:
A6T
1
Jefing_Li
873Thursday, March 09, 2006
Rev
1.0
of
A
DDR2 TERMINATION
D D
MEM_MA_ADD[0..15][5,8]
MEM_MA_CAS_L[5,8]
MEM_MA_RAS_L[5,8]
MEM_MA_WE_L[5,8]
MEM_MA_BANK0[5,8]
MEM_MA_BANK1[5,8]
MEM_MA_BANK2[5,8]
MEM_MA_CKE1[5,8]
MEM_MA_CKE0[5,8]
MEM_MA0_CS_L[0..3][5,8]
MEM_MA0_ODT0[5,8]
MEM_MA0_ODT1[5,8]
5
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MA_CAS_L
MEM_MA_RAS_L
MEM_MA_WE_L
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L2
MEM_MA0_CS_L3
MEM_MA0_ODT0
MEM_MA0_ODT1
1 2
47OHM
3 4
47OHM
1 2
47OHM
5 6
47OHM
3 4
47OHM
3 4
47OHM
1 2
47OHM
7 8
47OHM
7 8
47OHM
1 2
47OHM
5 6
47OHM
5 6
47OHM
1 2
47OHM
5 6
47OHM
5 6
47OHM
3 4
47OHM
3 4
47OHM
1 2
47OHM
1 2
47OHM
3 4
47OHM
7 8
47OHM
7 8
47OHM
5 6
47OHM
7 8
47OHM
7 8
47OHM
5 6
47OHM
3 4
47OHM
7 8
47OHM
5 6
47OHM
3 4
47OHM
1 2
47OHM
7 8
47OHM
RN908A
RN908B
RN913A
RN913C
RN914B
RN913B
RN914A
RN914D
RN913D
RN906A
RN907C
RN914C
RN905A
RN911C
RN905C
RN905B
RN911B
RN907A
RN912A
RN907B
RN907D
RN905D
RN906C
RN906D
RN912D
RN912C
RN906B
RN911D
RN908C
RN912B
RN911A
RN908D
4
+0.9V +0.9V
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_ADD[0..15][5,8]
MEM_MB_CAS_L[5,8]
MEM_MB_RAS_L[5,8]
MEM_MB_WE_L[5,8]
MEM_MB_BANK0[5,8]
MEM_MB_BANK1[5,8]
MEM_MB_BANK2[5,8]
MEM_MB_CKE1[5,8]
MEM_MB_CKE0[5,8]
MEM_MB0_CS_L[0..3][5,8]
MEM_MB0_ODT0[5,8]
MEM_MB0_ODT1[5,8]
MEM_MB_CAS_L
MEM_MB_RAS_L
MEM_MB_WE_L
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MB0_CS_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L2
MEM_MB0_CS_L3
MEM_MB0_ODT0
MEM_MB0_ODT1
3
3 4
47OHM
7 8
47OHM
5 6
47OHM
7 8
47OHM
1 2
47OHM
1 2
47OHM
3 4
47OHM
1 2
47OHM
3 4
47OHM
5 6
47OHM
3 4
47OHM
7 8
47OHM
5 6
47OHM
1 2
47OHM
5 6
47OHM
3 4
47OHM
7 8
47OHM
7 8
47OHM
5 6
47OHM
1 2
47OHM
5 6
47OHM
7 8
47OHM
7 8
47OHM
1 2
47OHM
3 4
47OHM
5 6
47OHM
3 4
47OHM
3 4
47OHM
1 2
47OHM
1 2
47OHM
7 8
47OHM
5 6
47OHM
RN916B
RN916D
RN901C
RN910D
RN901A
RN910A
RN901B
RN902A
RN910B
RN910C
RN903B
RN901D
RN909C
RN904A
RN902C
RN902B
RN903D
RN915D
RN903C
RN903A
RN915C
RN909D
RN902D
RN909A
RN915B
RN904C
RN909B
RN904B
RN916A
RN915A
RN904D
RN916C
+0.9V
0.1UF/10V
+0.9V
0.1UF/10V
C901
C908
2
12
12
C902
0.1UF/10V
C909
0.1UF/10V
12
12
C903
0.1UF/10V
C910
0.1UF/10V
12
12
C904
0.1UF/10V
C911
0.1UF/10V
12
12
place behind DIMMs
12
C905
0.1UF/10V
12
C912
0.1UF/10V
C906
0.1UF/10V
C913
0.1UF/10V
1
C907
0.1UF/10V
C914
0.1UF/10V
12
12
0.1UF/10V
C915
12
12
12
C C
LAYOUT :COULD BE SWAP
3/7
R918
300Ohm
5
+1.8V
1 2
34
Q908B
UM6K1N
_CPU_PROCHOT# [6]CPU_THERMTRIP# [15,16]
4.7KOhm
Q906B
UM6K1N
+3VS
R912
1 2
+1.8V +3VS
12
R914
300Ohm
1 2
_CPU_THERMTRIP#[6] CPU_PROCHOT#[15,19]
R905
10KOhm
61
Q906A
2
UM6K1N
34
5
R916
4.7KOhm
12
R906
10KOhm
1 2
61
Q908A
2
UM6K1N
B B
GND
2/8
GND
2/8
A
final_1.00
Title :
DDR2 TER/FETGAGE
ASUSTECH CO.,LTD.
Size Project Name
A3
5
4
3
2
Date: Sheet
A6T
Engineer:
Jefing_Li
Rev
1.0
of
973Thursday, March 09, 2006
1
5
HT_CPU_RX_CAD_H[0..15][4]
D D
HT_CPU_RX_CAD_L[0..15][4]
C C
HT_CPU_RX_CLK_H0[4]
HT_CPU_RX_CLK_L0[4]
HT_CPU_RX_CLK_H1[4]
HT_CPU_RX_CLK_L1[4]
HT_CPU_RX_CTL_H0[4]
HT_CPU_RX_CTL_L0[4]
+1.2V_HT
B B
R1001
150Ohm
1 2
R1003 150Ohm
+1.2V_C51_PLL
12
L1001
21
30Ohm/100Mhz
C1001
1UF/16V
HT_CPU_RX_CAD_H0
HT_CPU_RX_CAD_H1
HT_CPU_RX_CAD_H2
HT_CPU_RX_CAD_H3
HT_CPU_RX_CAD_H4
HT_CPU_RX_CAD_H5
HT_CPU_RX_CAD_H6
HT_CPU_RX_CAD_H7
HT_CPU_RX_CAD_H8
HT_CPU_RX_CAD_H9
HT_CPU_RX_CAD_H10
HT_CPU_RX_CAD_H11
HT_CPU_RX_CAD_H12
HT_CPU_RX_CAD_H13
HT_CPU_RX_CAD_H14
HT_CPU_RX_CAD_H15
HT_CPU_RX_CAD_L0
HT_CPU_RX_CAD_L1
HT_CPU_RX_CAD_L2
HT_CPU_RX_CAD_L3
HT_CPU_RX_CAD_L4
HT_CPU_RX_CAD_L5
HT_CPU_RX_CAD_L6
HT_CPU_RX_CAD_L7
HT_CPU_RX_CAD_L8
HT_CPU_RX_CAD_L9
HT_CPU_RX_CAD_L10
HT_CPU_RX_CAD_L11
HT_CPU_RX_CAD_L12
HT_CPU_RX_CAD_L13
HT_CPU_RX_CAD_L14
HT_CPU_RX_CAD_L15
HT_CPU_RX_CLK_H0
HT_CPU_RX_CLK_L0
HT_CPU_RX_CLK_H1
HT_CPU_RX_CLK_L1
HT_CPU_RX_CTL_H0
HT_CPU_RX_CTL_L0
HT_CPU_CAL_1P2V
HT_CPU_CAL_GND
+1.2V_PLLHTCPU
12
C1004
0.1UF/10V
12
Y23
HT_CPU_RXD0_P
W24
HT_CPU_RXD1_P
V24
HT_CPU_RXD2_P
U22
HT_CPU_RXD3_P
R24
HT_CPU_RXD4_P
P24
HT_CPU_RXD5_P
P22
HT_CPU_RXD6_P
N22
HT_CPU_RXD7_P
Y21
HT_CPU_RXD8_P
V21
HT_CPU_RXD9_P
W21
HT_CPU_RXD10_P
T21
HT_CPU_RXD11_P
R18
HT_CPU_RXD12_P
P16
HT_CPU_RXD13_P
N20
HT_CPU_RXD14_P
M17
HT_CPU_RXD15_P
Y22
HT_CPU_RXD0_N
W23
HT_CPU_RXD1_N
V23
HT_CPU_RXD2_N
U21
HT_CPU_RXD3_N
R23
HT_CPU_RXD4_N
P23
HT_CPU_RXD5_N
P21
HT_CPU_RXD6_N
N21
HT_CPU_RXD7_N
Y20
HT_CPU_RXD8_N
W20
HT_CPU_RXD9_N
W22
HT_CPU_RXD10_N
U20
HT_CPU_RXD11_N
R19
HT_CPU_RXD12_N
P17
HT_CPU_RXD13_N
N19
HT_CPU_RXD14_N
N18
HT_CPU_RXD15_N
T23
HT_CPU_RX_CLK0_P
T22
HT_CPU_RX_CLK0_N
R21
HT_CPU_RX_CLK1_P
R20
HT_CPU_RX_CLK1_N
M23
HT_CPU_RXCTL_P
M22
HT_CPU_RXCTL_N
W19
HT_CPU_CAL_1P2V
Y19
HT_CPU_CAL_GND
N16
+1.2V_PLLHTCPU
T13
+1.2V_PLLHTMCP
U3A
C51MV
4
HT_CPU_TXD0_P
HT_CPU_TXD1_P
HT_CPU_TXD2_P
HT_CPU_TXD3_P
HT_CPU_TXD4_P
HT_CPU_TXD5_P
HT_CPU_TXD6_P
HT_CPU_TXD7_P
HT_CPU_TXD8_P
HT_CPU_TXD9_P
HT_CPU_TXD10_P
HT_CPU_TXD11_P
HT_CPU_TXD12_P
HT_CPU_TXD13_P
HT_CPU_TXD14_P
HT_CPU_TXD15_P
HT_CPU_TXD0_N
HT_CPU_TXD1_N
HT_CPU_TXD2_N
HT_CPU_TXD3_N
HT_CPU_TXD4_N
HT_CPU_TXD5_N
HT_CPU_TXD6_N
HT_CPU_TXD7_N
HT_CPU_TXD8_N
HT_CPU_TXD9_N
HT_CPU_TXD10_N
HT_CPU_TXD11_N
HT_CPU_TXD12_N
HT_CPU_TXD13_N
HT_CPU_TXD14_N
HT_CPU_TXD15_N
HT_CPU_TX_CLK0_P
HT_CPU_TX_CLK0_N
HT_CPU_TX_CLK1_P
HT_CPU_TX_CLK1_N
HT_CPU_TXCTL_P
HT_CPU_TXCTL_N
CLKOUT_PRI_200MHZ_P
CLKOUT_PRI_200MHZ_N
CLKOUT_SEC_200MHZ_P
CLKOUT_SEC_200MHZ_N
HT_CPU_REQ*
HT_CPU_STOP*
HT_CPU_RESET*
HT_CPU_PWRGD
+2.5V_PLLHTCPU
C23
D23
E22
F23
H22
J21
K21
K23
D21
F19
F21
G20
J19
L17
L20
L18
C24
D24
E23
F24
H23
J22
K22
K24
D22
E20
E21
G19
J18
K17
K19
L19
G23
G24
G22
G21
L23
L24
B24
B23
A22
B21
F18
G18
D20
E19
L16
C1002
4.7UF/6.3V
3
HT_CPU_TX_CAD_H0
HT_CPU_TX_CAD_H1
HT_CPU_TX_CAD_H2
HT_CPU_TX_CAD_H3
HT_CPU_TX_CAD_H4
HT_CPU_TX_CAD_H5
HT_CPU_TX_CAD_H6
HT_CPU_TX_CAD_H7
HT_CPU_TX_CAD_H8
HT_CPU_TX_CAD_H9
HT_CPU_TX_CAD_H10
HT_CPU_TX_CAD_H11
HT_CPU_TX_CAD_H12
HT_CPU_TX_CAD_H13
HT_CPU_TX_CAD_H14
HT_CPU_TX_CAD_H15
HT_CPU_TX_CAD_L0
HT_CPU_TX_CAD_L1
HT_CPU_TX_CAD_L2
HT_CPU_TX_CAD_L3
HT_CPU_TX_CAD_L4
HT_CPU_TX_CAD_L5
HT_CPU_TX_CAD_L6
HT_CPU_TX_CAD_L7
HT_CPU_TX_CAD_L8
HT_CPU_TX_CAD_L9
HT_CPU_TX_CAD_L10
HT_CPU_TX_CAD_L11
HT_CPU_TX_CAD_L12
HT_CPU_TX_CAD_L13
HT_CPU_TX_CAD_L14
HT_CPU_TX_CAD_L15
HT_CPU_TX_CLK_H0
HT_CPU_TX_CLK_L0
HT_CPU_TX_CLK_H1
HT_CPU_TX_CLK_L1
HT_CPU_TX_CTL_H0
HT_CPU_TX_CTL_L0
CPU_CLK_H
CPU_CLK_L
T1001 TPC26TN/A
1
T1002 TPC26TN/A
1
CPU_LDTSTOP#
CPU_RESET#
CPU_PWROK
+2.5V_PLLTHCPU
12
C1003
0.1UF/10V
HT_CPU_TX_CLK_H0 [4]
HT_CPU_TX_CLK_L0 [4]
HT_CPU_TX_CLK_H1 [4]
HT_CPU_TX_CLK_L1 [4]
HT_CPU_TX_CTL_H0 [4]
HT_CPU_TX_CTL_L0 [4]
CPU_CLK_H [6]
CPU_CLK_L [6]
CPU_LDTSTOP# [6]
CPU_RESET# [6]
CPU_PWROK [6]
L1002
30Ohm/100Mhz
12
HT_CPU_TX_CAD_H[0..15] [4]
HT_CPU_TX_CAD_L[0..15] [4]
+2.5VS
R1002
22KOHM
1 2
+2.5VS
21
2
1
Place on back side
A A
5
4
3
2
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
B
Date: Sheet
A6T
Engineer:
1
C51_HT_CPU
Jefing_Li
of
10 73Thursday, March 09, 2006
Rev
1.0
5
4
3
2
1
D D
HT_MCP_RX_H[0..7][16]
49.9Ohm
R1101
/X
1 2
HT_MCP_RX_H0
HT_MCP_RX_H1
HT_MCP_RX_H2
HT_MCP_RX_H3
HT_MCP_RX_H4
HT_MCP_RX_H5
HT_MCP_RX_H6
HT_MCP_RX_H7
FOR 4X4 LINK TO FLOAT UNUSED PIN
HT_MCP_RX_L[0..7][16]
C C
R1102
+1.2VS
49.9Ohm
/X
1 2
HT_MCP_RX_L0
HT_MCP_RX_L1
HT_MCP_RX_L2
HT_MCP_RX_L3
HT_MCP_RX_L4
HT_MCP_RX_L5
HT_MCP_RX_L6
HT_MCP_RX_L7
FOR 4X4 LINK TO FLOAT UNUSED PIN
HT_MCP_RX_CLK_H0[16]
HT_MCP_RX_CLK_L0[16]
T1101TPC26T N/A
T1103TPC26T N/A
B B
A A
5
HT_MCP_RX_CTL_H[16]
HT_MCP_REQ#[16]
HT_MCP_STOP#[16]
HT_MCP_RST#[16]
HT_MCP_PWRGD[16]
MCP_OUT_25M[16]
MCP_OUT_200M_H[16]
MCP_OUT_200M_L[16]
HT_MCP_RX_CLK_H0
HT_MCP_RX_CLK_L0
HT_MCP_C_CLK_H1
1
HT_MCP_C_CLK_L1
1
HT_MCP_RX_CTL_H
HT_MCP_RX_CTL_L
HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_RST#
HT_MCP_PWRGD
MCP_OUT_25M
MCP_OUT_200M_H
MCP_OUT_200M_L
4
U3B
AD6
HT_MCP_RXD0_P
AC7
HT_MCP_RXD1_P
AA8
HT_MCP_RXD2_P
AA9
HT_MCP_RXD3_P
AD10
HT_MCP_RXD4_P
AD11
HT_MCP_RXD5_P
AC12
HT_MCP_RXD6_P
AC13
HT_MCP_RXD7_P
AA6
HT_MCP_RXD8_P
W7
HT_MCP_RXD9_P
Y8
HT_MCP_RXD10_P
V9
HT_MCP_RXD11_P
Y10
HT_MCP_RXD12_P
AA11
HT_MCP_RXD13_P
V11
HT_MCP_RXD14_P
W12
HT_MCP_RXD15_P
AC6
HT_MCP_RXD0_N
AB7
HT_MCP_RXD1_N
AB8
HT_MCP_RXD2_N
AB9
HT_MCP_RXD3_N
AC10
HT_MCP_RXD4_N
AC11
HT_MCP_RXD5_N
AB12
HT_MCP_RXD6_N
AB13
HT_MCP_RXD7_N
Y6
HT_MCP_RXD8_N
Y7
HT_MCP_RXD9_N
AA7
HT_MCP_RXD10_N
W9
HT_MCP_RXD11_N
W10
HT_MCP_RXD12_N
Y12
HT_MCP_RXD13_N
W11
HT_MCP_RXD14_N
V13
HT_MCP_RXD15_N
AD9
HT_MCP_RX_CLK0_P
AC9
HT_MCP_RX_CLK0_N
U10
HT_MCP_RX_CLK1_P
T10
HT_MCP_RX_CLK1_N
AD14
HT_MCP_RXCTL_P
AC14
HT_MCP_RXCTL_N
AB5
HT_MCP_REQ*
AA5
HT_MCP_STOP*
AC5
HT_MCP_RESET*
AD5
HT_MCP_PWRGD
AC4
CLKIN_25MHZ
Y5
CLKIN_200MHZ_P
W5
CLKIN_200MHZ_N
C51MV
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P
HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
HT_MCP_TXD8_N
HT_MCP_TXD9_N
HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N
HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N
HT_MCP_TXCTL_P
HT_MCP_TXCTL_N
CLKOUT_CTERM_GND
SCLKIN_MCLKOUT_200MHZ_P
SCLKIN_MCLKOUT_200MHZ_N
HT_MCP_CAL_1P2V
HT_MCP_CAL_GND
3
HT_MCP_TX_H0
AC24
HT_MCP_TX_H1
AD23
HT_MCP_TX_H2
AC22
HT_MCP_TX_H3
AC20
HT_MCP_TX_H4
AB18
HT_MCP_TX_H5
AA17
HT_MCP_TX_H6
AB16
HT_MCP_TX_H7
AC16
AB21
AB20
AB19
W18
W15
AA15
Y14
W13
HT_MCP_TX_L0
AC23
HT_MCP_TX_L1
AD22
HT_MCP_TX_L2
AC21
HT_MCP_TX_L3
AD20
HT_MCP_TX_L4
AC18
HT_MCP_TX_L5
AB17
HT_MCP_TX_L6
AB15
HT_MCP_TX_L7
AD16
AB22
AA20
AA19
V17
V15
Y15
W14
Y13
HT_MCP_TX_CLK_H0
AC19
HT_MCP_TX_CLK_L0
AD19
HT_C_MCP_CLK_H1
Y17
HT_C_MCP_CLK_L1
W17
HT_MCP_TX_CTL_H
AC15
HT_MCP_TX_CTL_L
AD15
B22
T1105 TPC26TN/A
A20
T1106 TPC26TN/A
B20
AB23
AB24
R1103
1 2
1
1
HT_MCP_CAL_1P2V
HT_MCP_CAL_GND
2.37KOhm
HT_MCP_TX_H[0..7] [16]
HT_MCP_TX_L[0..7] [16]
T1102N/A
1
T1104N/A
1
1%
150Ohm
1%
150Ohm
1%
HT_MCP_TX_CLK_H0 [16]
HT_MCP_TX_CLK_L0 [16]
HT_MCP_TX_CTL_H [16]
HT_MCP_TX_CTL_L [16]HT_MCP_RX_CTL_L[16]
+1.2VS
R1104
1 2
R1105
1 2
2
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
B
Date: Sheet
A6T
Engineer:
1
C51_HT_MCP
Jefing_Li
of
11 73Thursday, March 09, 2006
Rev
1.0
5
4
3
2
1
D D
C C
PE0_PRSENT#
12
R1201
10KOhm
B B
+3VS
A A
5
PE1_X1_RX_P[46]
PE1_X1_RX_N[46]
R1202
10KOhm
R1203
10KOhm
+1.2V_C51_PLL
L1201
30Ohm/100Mhz
1UF/16V
Place on back side
PE1_X1_RX_P
PE1_X1_RX_N
PE1_PRSENT#
12
PE2_PRSENT#
12
C1234
1
1
1
1
12
T1201TPC26T N/A
T1202TPC26T N/A
T1203TPC26T N/A
T1204TPC26T N/A
21
12
C1233
0.1UF/10V
U3C
J8
PE0_RX0_P
J6
PE0_RX1_P
K9
PE0_RX2_P
L6
PE0_RX3_P
L7
PE0_RX4_P
M9
PE0_RX5_P
N8
PE0_RX6_P
N6
PE0_RX7_P
R6
PE0_RX8_P
P3
PE0_RX9_P
R8
PE0_RX10_P
U6
PE0_RX11_P
T8
PE0_RX12_P
U7
PE0_RX13_P
V4
PE0_RX14_P
Y3
PE0_RX15_P
J7
PE0_RX0_N
J5
PE0_RX1_N
J9
PE0_RX2_N
L5
PE0_RX3_N
L8
PE0_RX4_N
M8
PE0_RX5_N
N7
PE0_RX6_N
N5
PE0_RX7_N
R5
PE0_RX8_N
P4
PE0_RX9_N
R7
PE0_RX10_N
U5
PE0_RX11_N
T9
PE0_RX12_N
U8
PE0_RX13_N
V3
PE0_RX14_N
AA3
PE0_RX15_N
D1
PE0_PRSNT*
G6
PE1_RX_P
H6
PE1_RX_N
E2
PE1_PRSNT*
J4
PE2_RX_P
K3
PE2_RX_N
E3
PE2_PRSNT*
D3
PE1_CLKREQ*/CLK
E4
PE2_CLKREQ*/DATA
AC3
PE_REFCLKIN_P
AB3
PE_REFCLKIN_N
T11
+1.2V_PLLPE
C51MV
4
PE0_TX0_P
PE0_TX1_P
PE0_TX2_P
PE0_TX3_P
PE0_TX4_P
PE0_TX5_P
PE0_TX6_P
PE0_TX7_P
PE0_TX8_P
PE0_TX9_P
PE0_TX10_P
PE0_TX11_P
PE0_TX12_P
PE0_TX13_P
PE0_TX14_P
PE0_TX15_P
PE0_TX0_N
PE0_TX1_N
PE0_TX2_N
PE0_TX3_N
PE0_TX4_N
PE0_TX5_N
PE0_TX6_N
PE0_TX7_N
PE0_TX8_N
PE0_TX9_N
PE0_TX10_N
PE0_TX11_N
PE0_TX12_N
PE0_TX13_N
PE0_TX14_N
PE0_TX15_N
PE0_REFCLK_P
PE0_REFCLK_N
PE1_TX_P
PE1_TX_N
PE1_REFCLK_P
PE1_REFCLK_N
PE2_TX_P
PE2_TX_N
PE2_REFCLK_P
PE2_REFCLK_N
PE_TSTCLK_P
PE_TSTCLK_N
PE_RESET*
PE_CTERM_GND
L1
L3
L4
M4
P1
R1
R3
R4
U4
V1
W1
W3
AA1
AB1
AC1
AD2
L2
M2
M3
N3
P2
R2
T2
T3
U3
V2
W2
Y2
AA2
AB2
AC2
AD3
K1
K2
RPE1_X1_TX_P
G4
RPE1_X1_TX_N
G5
G2
G3
H4
J3
H2
H3
F1
F2
G1
PE_CTERM_GND+1.2V_PLLPE
D2
PE1_X1_CLK_P
PE1_X1_CLK_N
PE_RESET#
3
1 2
C1235 0.1UF/10V
PE1_X1_CLK_P [46]
PE1_X1_CLK_N [46]
R1204
100Ohm
/X
PE_RESET# [46]
R1205 2.37KOhm
1 2
1 2
C1236 0.1UF/10V
1 2
PE1_X1_TX_P
PE1_X1_TX_N
2
PE1_X1_TX_P [46]
PE1_X1_TX_N [46]
final_1.00
ASUSTECH CO.,LTD.
Size Project Name
B
Date: Sheet
A6M
Title :
Engineer:
1
C51_PCIE
Jefing_Li
12 73Thursday, March 09, 2006
Rev
1.0
of
5
4
3
2
+5VS
1
D D
CRT_HSYNC[40]
CRT_VSYNC[40]
R1350
1 2
1KOhm
3/1
R1323
1 2
+3VS
47Ohm/100Mhz
/C61MP
C C
C61M_XTAL_OUT C61M_XTAL_IN
C1313
18PF/50V
1 2
/C61M
B B
+2.5VS
X1301
12
27Mhz
/C61M
30Ohm/100Mhz
/C61MP
R1324
1 2
C1314
18PF/50V
/C61M
+1.2V_C51_PLL
L1301
L1302
0.1UF/10V
C61M_RED
C61M_GREEN
C61M_BLUE
CRT_HSYNC
CRT_VSYNC
R1304 124Ohm
1 2
12
C1301
0.01UF/10V
0Ohm
/C61M0
C1302
4.7UF/6.3V
/C61MP
C1304
4.7UF/6.3V
/C61MP
12
0.1UF/10V
+3.3V_DAC
12
0.1UF/10V
/C61MP
+2.5V_PLLGPU
12
0.1UF/10V
/C61MP
C61M_XTAL_IN
C61M_XTAL_OUT
/x
12
C1311
GND
C1303
C1305
0.1UF/10V
R130822KOHM
C1312
21
21
0Ohm
/C61M0
1 2
C1310
U3D
A5
DAC_RED
B6
DAC_GREEN
A6
DAC_BLUE
B7
DAC_HSYNC
C7
DAC_VSYNC
D8
DAC_RSET
D9
DAC_VREF
C8
DAC_IDUMP
A9
12
+3.3V_DAC
H13
12
+2.5V_PLLGPU
C9
XTAL_IN
B9
XTAL_OUT
F12
NC1/DDC_CLK
E11
NC2/DDC_DATA
E17
12
NC3/HPDET
F17
NC4/EE_CLK
G17
NC5/EE_DATA
R9
+1.2V_PLLGPU
P9
+1.2V_PLLCORE
H16
+1.2V_PLLIFP
12
C51MV
IFPA_TXC_P
IFPA_TXC_N
IFPA_TXD0_P
IFPA_TXD1_P
IFPA_TXD2_P
IFPA_TXD3_P
IFPA_TXD0_N
IFPA_TXD1_N
IFPA_TXD2_N
IFPA_TXD3_N
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD4_P
IFPB_TXD5_P
IFPB_TXD6_P
IFPB_TXD7_P
IFPB_TXD4_N
IFPB_TXD5_N
IFPB_TXD6_N
IFPB_TXD7_N
IFPAB_VPROBE
IFPAB_RSET
+2.5V_PLLIFP
+2.5V_PLLCORE
PKG_TEST
TEST_MODE_EN
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
C14
B13
A15
D15
A14
F14
B15
C15
B14
E14
A10
B10
B11
E13
D13
B12
A11
F13
C13
C12
A16
F15
E16
H12
D17
C17
C18
B19
C19
B18
A19
R1305 1KOhm
C1308
4.7UF/6.3V
R1309 1KOhm
22KOHM
LVDS_CLKAP
LVDS_CLKAM
LVDS_YA0P
LVDS_YA1P
LVDS_YA2P
LVDS_YA0M
LVDS_YA1M
LVDS_YA2M
LVDS_CLKBP
LVDS_CLKBM
LVDS_YB0P
LVDS_YB1P
LVDS_YB2P
LVDS_YB0M
LVDS_YB1M
LVDS_YB2M
+2.5V_PLLIFP
+2.5V_PLLCORE
12
R1313
1 2
GND
C1306 0.1UF/10V
1 2
12
C1307
1UF/16V
/C61MP
C1309
0.1UF/10V
12
1 2
12
12
R1312
22KOHM
R1325
1 2
/C61M0
L1303
30Ohm/100Mhz
/C61MP
L1304
30Ohm/100Mhz
R1310
22KOHM
/x
+3VS
12
R1314
22KOHM
0Ohm
21
21
22KOHM
1 2
LVDS_CLKAP [41]
LVDS_CLKAM [41]
LVDS_YA0P [41]
LVDS_YA1P [41]
LVDS_YA2P [41]
LVDS_YA0M [41]
LVDS_YA1M [41]
LVDS_YA2M [41]
LVDS_CLKBP [41]
LVDS_CLKBM [41]
LVDS_YB0P [41]
LVDS_YB1P [41]
LVDS_YB2P [41]
LVDS_YB0M [41]
LVDS_YB1M [41]
LVDS_YB2M [41]
+2.5VS
+2.5VS
+3VS
R1311
1 2
TV_EN[19]
CRT_RED[40]
TV_C[40]
CRT_GREEN[40]
TV_Y[40]
C61M_RED
C61M_GREEN
JP4001
1 2
JP4002
1 2
Share C1435 and C1436
R4001
75Ohm
TV_EN
1 2
22KOHM
/C61M
CRT_RED
TV_C
_C61M_RED
CRT_GREEN
TV_Y
_C61M_GREEN
R4002
75Ohm
1 2
R1326
+5VS
1 2
R1330 10KOhm
1 2
U36
1
S
VCC
2
I0A
E#
3
I1A
I0D
4
YA
I1D
5
I0B
YD
6
I1B
I0C
7
YB
I1C
8 9
GND YC
IDTQS3257QG
/C61M
16
15
14
13
12
11
10
LOAD_VIDEO
LOAD_VGA
CRT_BLUE
TV_CVBS
_C61M_BLUE
R4003
75Ohm
C1315
1UF/16V
R1331 10KOhm
1 2
R1329 10KOhm
1 2
1 2
JP4003
1 2
+3VS
12
12
1 2
R1328
100KOHM
C1316
0.01UF/10V
CRT_BLUE [40]
TV_CVBS [40]
C61M_BLUE
LOAD_TEST [19]
A A
5
4
3
2
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
Custom
Date: Sheet
Engineer:
A6M
1
C51_VIDEO
Jefing_Li
of
13 73Thursday, March 09, 2006
Rev
1.0
5
4
3
2
1
C1444
12
12
1UF/16V
12
0.1UF/10V
+1.0VS
C1418
C1445
1UF/16V
12
+1.2VS
12
C1403
C1446
0.1UF/10V
12
1UF/16V
C1427
0.1UF/10V
1UF/16V
C1437
0.1UF/10V
12
0.1UF/10V
C1404
C1430
C1447
12
12
0.1UF/10V
12
12
12
C1405
1UF/16V
C1428
1UF/16V
C1438
0.1UF/10V
C1448
0.1UF/10V
12
C1431
12
12
1UF/16V
C1429
0.1UF/10V
12
12
C1449
0.1UF/10V
C1406
1UF/16V
12
12
C1432
21
L1403
47Ohm/100Mhz
+1.2V_C51_PLL
+1.2VS
+1.0VS
12
12
AB11
AA18
W16
E10
F10
F11
G11
H11
T15
U13
U11
U16
U15
K16
M16
R16
M21
T16
U17
C21
H17
D18
C10
B5
C6
D7
E8
E9
J11
J12
J13
J14
Y9
B4
C5
D6
E7
J20
U3E
+1.2V_CORE1
+1.2V_CORE2
+1.2V_CORE3
+1.2V_CORE4
+1.2V_CORE5
+1.2V_CORE6
+1.2V_CORE7
+1.2V_CORE8
+1.2V_CORE9
+1.2V_CORE10
+1.2V_CORE11
+1.2V_CORE12
+1.2V_CORE13
+1.2V_CORE14
+1.2V_HTMCP1
+1.2V_HTMCP2
+1.2V_HTMCP3
+1.2V_HTMCP4
+1.2V_HTMCP5
+1.2V_HTMCP6
+1.2V_HTMCP7
+1.2V_HTMCP8
+1.2V_HTMCP9
+1.2V_PED1
+1.2V_PED2
+1.2V_PED3
+1.2V_PED4
+1.2V_HT1
+1.2V_HT2
+1.2V_HT3
+1.2V_HT4
+1.2V_HT5
+1.2V_HT6
+1.2V_HT7
+1.2V_HT8
+1.2V_HT9
+3.3V_1
+3.3V_2
C51MV
+1.2V_PEA1
+1.2V_PEA2
+1.2V_PEA3
+1.2V_PEA4
+1.2V_PEA5
+1.2V_PEA6
+1.2V_PEA7
+1.2V_PEA8
+1.2V_PLL1
+1.2V_PLL2
+1.2V_PLL3
+1.2V_PLL4
+1.2V_PLL5
+1.2V_PLL6
+1.2V_PLL7
+1.2V_PLL8
+1.2V_PLL9
+1.2V_PLL10
+1.2V_PLL11
+1.2V_PLL12
+2.5V_CORE_1
+2.5V_CORE_2
+2.5V_IFPA
+2.5V_IFPB
A3
B3
C4
D5
E6
F7
F8
F9
A2
B2
C2
C3
D4
E5
F6
G7
G8
G9
H10
J10
C16
B16
G15
H15
0.1UF/10V
C1419
0.1UF/10V
C1407
0.1UF/10V
0.1UF/10V
/C61MP
12
12
0.1UF/10V
C1433
C1439
C1408
0.1UF/10V
C1420
12
12
12
0.1UF/10V
12
0.1UF/10V
+2.5VS
0.1UF/10V
+2.5V_IFPAB
C1440
1UF/16V
/C61MP
C1409
C1421
C1434
12
12
12
C1410
0.1UF/10V
0.1UF/10V
12
+1.2V_PEA_C51MV
12
C1411
1UF/16V
12
C1422
C1435
1UF/16V
1 2
12
C1412
1UF/16V
+1.2V_PLL_C51MV
12
C1423
0.1UF/10V
0.1UF/10V
12
C1436
22UF/6.3V
L1404
21
47Ohm/100Mhz
/C61MP
R1401
0Ohm
/C61M0
12
12
C1413
22UF/6.3V
C1424
12
C1414
22UF/6.3V
12
C1425
4.7UF/6.3V
+2.5VS
Share C1435 and C1436
with L1303
+1.8VS
12
L1401
42Ohm/100Mhz
C1426
21
12
12
47UF/6.3V
LVDS 1.8V
+1.0VS
12
C1401
1UF/16V
C1441
47UF/6.3V
C1415
12
22UF/6.3V
12
1UF/16V
C1442
0.1UF/10V
C1416
12
D D
+1.0VS +1.0VS
C C
+1.2V_HT
12
C1443
0.1UF/10V
C1402
22UF/6.3V
C1417
1UF/16V
12
0.1UF/10V
TMDS 3.3V
+3VS
12
C1450
V19
GND34
GND1
C1
T14
GND35
GND2
AA21
C20
GND36
GND3
AA13
R17
GND37
GND4
U14
AB14
GND38
GND5
H14
1UF/16V
U12
G13
Y16
GND39
GND40
GND6
GND7
C11
AB4
AA4
H21
GND41
GND8
J15
C22
GND42
GND9
E12
GND43
GND10
AB6
GND44
GND11
AB10
F22
Y18
L22
R22
V22
AA22
A23
AA23
AA24
L11
M11
N11
P11
M12
N12
P12
M13
N13
P13
M14
N14
P14
L12
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
E18
U18
E15
Y11
U19
N17
F16
J17
L13B1T17
D11
T12
J16
D19
H19
L21
M19
P19
T19
L14
3
K6M6P6T6W6W8H8K8V6F4V8
PE_GND12
PE_GND13
PE_GND14
PE_GND15
PE_GND16
PE_GND17
PE_GND18
PE_GND19
PE_GND20
PE_GND21
PE_GND1
PE_GND2
PE_GND3
PE_GND4
PE_GND5
PE_GND6
PE_GND7
PE_GND8
PE_GND9
PE_GND10
F3L9P8N9K4N4T4W4Y4U9H9
U3F
C51MV
PE_GND22
PE_GND11
final_1.00
Title :
C51_VCC_GND
ASUSTECH CO.,LTD.
Size Project Name
A3
2
Date: Sheet
A6T
Engineer:
Jefing_Li
Rev
1
14 73Monday, March 06, 2006
1.0
of
B B
A A
5
4
5
KBC will issue a
analog ( a voltage
level ) signal.
D D
YAGEO/RC0402FR-0710KL <G>
SW: FAN_DA1 must
be low during S3
FAN_DA1[38]
R1.1
1S_DEL[43]
C C
GND
4.7KOhm
1 2
R1505
1MOhm
r0402_h16
1 2
R1504
1
r0402_h16
C1506
0.1UF/25V
32
3
D
Q1502
1
2N7002
G
/x
S
2
GND
+5VS_FAN +5VS
1 2
GND
1 2
1 2
GND
R1501
10KOhm
R1506
15KOhm
1%
12
RN1501A
10KOhm
R1508
10KOhm
1 2
/x
GND GND
CPU FAN will be forced on:
1) Thermal Sensor
Over-temperture
2) PROCHOT asserted(CPU)
3) WATCHDOG asserted(KBC)
4
Using a OP AMP and
fine-tuning the level,
we can improve the fan
speed accuracy.
c0402
C1501 1000PF/50V
FAN_SPD
1 2
R1510
10KOhm
3
2
5
6
1 2
A+
A-
B+
B-
LM358MX
WATCHDOG[38]
+12V
U4
8
VCC
+
1
AO
-
+
BO
CPUFAN_SPD
7
4
-
GND
GND GND
OS_OC#
R1503 330Ohm
1 2
+3VS
56
RN1501C
10KOhm
32
3
D
Q1505
1
2N7002
1
G
12
GND
R1511
10KOhm
r0402_h16
GND
S
2
3
2
Fan Speed Control
12
+
CE1501
47UF/6.3V
GND
CPUFAN_SPD
+5VS_FAN
1 2
GND
D1502
1N4148W
1
1
+3VS
CPU FAN
34
RN1501B
10KOhm
R1502
GND
12
100KOHM
r0402 /x
C1505
1UF/10V
/x
12
FAN_SPD
+3VS
12
R1509
10KOhm
/X
r0402_h16
32
3
D
Q1503
2N7002
G
S
2
/x
GND
1 2
R1507
0Ohm
D1501
RB751V_40
1 2
+5VS
12
C1502
0.1UF/10V
c0402
GND
+3VS
78
34
5
GND GND
Q1501
SI2301BDS_T1_E3
2 3
S
2
RN1501D
10KOhm
2
Q1504B
UM6K1N
D
3
G
1
1
61
Q1504A
UM6K1N
FANSP1
12
C1503
100PF/50V
c0402
GND
CPUFAN_SPD_A [19]
1
When fan speed is
very slow, after RC
integrator the level
of FANSP1 will be
very low that may
make south bridge do
the wrong detection.
+5VS_FAN
12
C1504
0.1UF/10V
c0402
/x
GND
45
HOLD1
1
2
3
HOLD2
GND
GND
CON2
WTOB_CON_3P
12G170000039
B B
CPU THERM SENSOR
Standby Mode: 3uA(Max. 10uA)
Full Active: 0.5 mA(Max. 1mA)
12
C1508
0.1UF/10V
c0402
GND
/x
/x
GND
U6
8
SCLK
7
SDA
6
ALERT#
5
GND
MAX6657MSA
3/6
Fixed Slave Address: 98H
Close to Pin W7 & W8 of CPU
1
VCC
DXP
DXN
OVERT#
H_THERMDA
2
3
4
H_THERMDC
OS_OC#
1 2
1 2
4
12
C1510
2200PF/50V
c0402
R1515
R1522
3/6
0Ohm
/x
0Ohm
/x
CPU_THERMADA [6]
CPU_THERMADC [6]
CPU_THERMTRIP# [9,16]
CPU_PROCHOT# [9,19]
final_1.00
Title :
FAN/THERM SENSOR
1
Jefing_Li
15 73Thursday, March 09, 2006
of
Rev
1.0
ASUSTECH CO.,LTD.
Size Project Name
A3
3
2
Date: Sheet
A6M
Engineer:
I2C_CLK0_S[8,19]
I2C_DATA0_S[8,19]
+3VS_THM1
R1519 0Ohm
1 2
1 2
R1520 0Ohm
1 2
R1521 0Ohm
R1513
100Ohm
+3VS
+3VS
A A
PM_THERM#[19]
SMB_ALERT#[19]
CPU_PROCHOT#[9,19]
1 2
R1518
4.7KOhm
1 2
5
5
A
4
3
2
1
HT_MCP_TX_H[0..7][11]
HT_MCP_TX_H0
HT_MCP_TX_H1
HT_MCP_TX_H2
HT_MCP_TX_H3
D D
HT_MCP_TX_L[0..7][11]
HT_MCP_TX_CLK_H0[11]
HT_MCP_TX_CLK_L0[11]
HT_MCP_TX_CTL_H[11]
HT_MCP_TX_CTL_L[11]
C C
1.8V_PWRGD[64]
HT_MCP_REQ#[11]
HT_MCP_STOP#[11]
R1607 150Ohm
R1609 49.9Ohm
R1601
+1.2VS
R1602
1 2
HT_VLD[6,64]
CPU_VLD[17,61,70]
MEM_VLD[64]
HTVDD_EN[67]
CPUVDD_EN[61]
MEM_VLD
49.9Ohm
/X
1 2
49.9Ohm
/X
1 2
12
B B
+3VS
L1601
30Ohm/100Mhz
12
C1605
0.1UF/10V
21
C1602
10UF/10V
12
HT_MCP_TX_H4
HT_MCP_TX_H6
HT_MCP_TX_H7
HT_MCP_TX_L0
HT_MCP_TX_L1
HT_MCP_TX_L2
HT_MCP_TX_L3
HT_MCP_TX_L4
HT_MCP_TX_L5
HT_MCP_TX_L6
HT_MCP_TX_L7
HT_MCP_TX_CLK_H0
HT_MCP_TX_CLK_L0
HT_MCP_TX_CTL_H
HT_MCP_TX_CTL_L
HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_COMP_GND1
HT_MCP_COMP_GND2
HT_VLD
CPU_VLD
MEM_VLD
HTVDD_EN
CPUVDD_EN
+1.5VS
12
C1601
0.1UF/10V
+3.3V_PLL_CPU_HT
12
C1603
0.1UF/10V
C1604
0.01UF/10V
U7A
K1
L1
M1
N1
R1
T1
U1
V1
K2
L2
M2
N2
R2
T2
U2
V2
P1
P2
W1
W2
AD1
AA5
AB1
AB2
F22
N26
M24
F23
N25
M6
M5
MCP51
12
HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RX_CLK_P
HT_MCP_RX_CLK_N
HT_MCP_RXCTL_P
HT_MCP_RXCTL_N
HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_COMP_GND1
HT_MCP_COMP_GND2
HT_VLD
CPU_VLD
MEM_VLD
HTVDD_EN
CPUVDD_EN
+1.5V_PLL_CPU_HT
+3.3V_PLL_CPU_HT
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
HT_MCP_TX_CLK_P
HT_MCP_TX_CLK_N
HT_MCP_TXCTL_P
HT_MCP_TXCTL_N
CLKOUT_200MHZ_N
CLKOUT_200MHZ_P
CLKOUT_25MHZ
HT_MCP_PWRGD
HT_MCP_RST#
THERMTRIP#/GPIO_58
CLK200_TERM_GND
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
AA1
Y1
AA3
W5
U5
T5
R5
P5
AA2
Y2
AA4
W6
U6
T6
R6
P6
V5
V6
N5
N6
AC2
AC1
Y5
AD2
AE1
J6
K6
H22
H21
H23
D26
F25
_HT_MCP_PWRGD
HT_MCP_RST#
CPU_THERMTRIP#
HT_MCP_RX_H0
HT_MCP_RX_H1
HT_MCP_RX_H2
HT_MCP_RX_H3
HT_MCP_RX_H4
HT_MCP_RX_H5HT_MCP_TX_H5
HT_MCP_RX_H6
HT_MCP_RX_H7
HT_MCP_RX_L0
HT_MCP_RX_L1
HT_MCP_RX_L2
HT_MCP_RX_L3
HT_MCP_RX_L4
HT_MCP_RX_L5
HT_MCP_RX_L6
HT_MCP_RX_L7
HT_MCP_RX_CLK_H0
HT_MCP_RX_CLK_L0
HT_MCP_RX_CTL_H
HT_MCP_RX_CTL_L
MCP_OUT_200M_L
MCP_OUT_200M_H
R1610
562Ohm
1%
1 2
MCP_TCK
MCP_TDI
MCP_TDO
MCP_TMS
MCP_TRST#
R1614
10KOhm
10KOhm
1 2
1 2
R1615
HT_MCP_RX_H[0..7] [11]
HT_MCP_RX_L[0..7] [11]
HT_MCP_RX_CLK_H0 [11]
HT_MCP_RX_CLK_L0 [11]
HT_MCP_RX_CTL_H [11]
HT_MCP_RX_CTL_L [11]
MCP_OUT_200M_L [11]
MCP_OUT_200M_H [11]
R1608 22Ohm
R1611
10KOhm
1 2
1 2
R1612
10KOhm
/x
+3VS
1 2
MCP_OUT_25M [11]
HT_MCP_RST# [11]
CPU_THERMTRIP# [9,15]
R1613
10KOhm
1 2
+3VS
HT_MCP_REQ#
HT_MCP_STOP#
_HT_MCP_PWRGD
HT_MCP_RST#
R1603 1.5KOhm
1 2
R1604 1.5KOhm
1 2
R1605 1.5KOhm
1 2
R1606 1.5KOhm
1 2
OPEN DRAID
_HT_MCP_PWRGD [6]
R1617 0Ohm
1 2
CPUVDD_EN HT_MCP_PWRGD
R1618
1 2
HT_MCP_PWRGD [11]
0Ohm
/X
3/1
For HT X4
Rev
1.0
A
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
B
5
4
3
2
Date: Sheet
A6T
Engineer:
1
MCP51_HT
Jefing_Li
of
16 73Thursday, March 09, 2006
5
A
4
3
2
1
D D
C C
MINI_PCI_RST#[32]
B B
CARD_PCI_RST#[33]
PCI_IDE_RST#[31]
LPC_RST#[36,37,38]
PCI_AD[0..31][32,33]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
R1710 33Ohm
R1711 33Ohm
R1714 33Ohm
R1716 33Ohm
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_PAR
PCI_PERR#
PCI_SERR#
PCI_PME#
PM_CLKRUN#
_MINI_PCI_RST#
_CARD_PCI_RST#
_PCI_IDE_RST#
_LPC_RST#
PCI_C/BE#[0..3][32,33]
PCI_FRAME#[32,33]
PCI_IRDY#[32,33]
PCI_TRDY#[32,33]
PCI_STOP#[32,33]
PCI_DEVSEL#[32,33]
PCI_PAR[32,33]
PCI_PERR#[32,33]
PCI_SERR#[32,33]
PCI_PME#[32,33]
PM_CLKRUN#[32,33,38]
1 2
1 2
1 2
1 2
U7B
AF19
PCI_AD0
AB21
PCI_AD1
AC19
PCI_AD2
AA20
PCI_AD3
AA19
PCI_AD4
AF20
PCI_AD5
AE19
PCI_AD6
AE20
PCI_AD7
AB20
PCI_AD8
AB19
PCI_AD9
AA18
PCI_AD10
AB18
PCI_AD11
AE18
PCI_AD12
AF18
PCI_AD13
AC17
PCI_AD14
AA17
PCI_AD15
AB15
PCI_AD16
AF15
PCI_AD17
AE15
PCI_AD18
AF14
PCI_AD19
AE14
PCI_AD20
AA14
PCI_AD21
AB14
PCI_AD22
AC13
PCI_AD23
AB13
PCI_AD24
AE13
PCI_AD25
AA12
PCI_AD26
AF13
PCI_AD27
AB12
PCI_AD28
AF12
PCI_AD29
AE12
PCI_AD30
AF11
PCI_AD31
AD19
PCI_CBE0#
AB17
PCI_CBE1#
AA15
PCI_CBE2#
AA13
PCI_CBE3#
AC15
PCI_FRAME#
AD15
PCI_IRDY#
AB16
PCI_TRDY#
AE16
PCI_STOP#
AA16
PCI_DEVSEL#
AE17
PCI_PAR
AF16
PCI_PERR#/GPIO_43
AF17
PCI_SERR#
AD11
PCI_PME#/GPIO_30
AF25
PCI_CLKRUN#/GPIO_42
AE25
PCI_RESET0#
AD24
PCI_RESET1#
AE26
PCI_RESET2#
W22
PCI_RESET3#
L26
LPC_RESET#
MCP51
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#/GPIO_38
PCI_REQ4#/GPIO_40
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#/GPIO_39
PCI_GNT4#/GPIO_41
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
LPC_CS#/LPC_DRQ1#
LPC_SERIRQ
LPC_PWRDWN#/GPIO_54
LPC_CLK0
LPC_CLK1
AA22
AE22
AF21
AF22
AE23
AE21
AC21
AA21
AB24
AB22
AE11
AB11
AC11
AA11
AE24
AF24
AD23
AF23
AB23
AC23
K24
H26
H25
K22
G25
K21
K23
L22
H24
F26
G26
10PF/50V
/X
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_GNT#0
PCI_GNT#1
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
CLK_MINIPCI_
CLK_CB_
CLK_KBC_
PCI_CLKOUT
PCI_CLKIN
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
LPC_DRQ1#
INT_SERIRQ
LPC_PD#
12
C1705
PCI_REQ#0 [32]
PCI_REQ#1 [33]
PCI_GNT#0 [32]
PCI_GNT#1 [33]
PCI_INTX# [32,33]
PCI_INTY# [32,33]
PCI_INTZ# [33]
R1702 22Ohm
R1703 22Ohm
R1704 22Ohm
R1705 22Ohm
R1706 22Ohm
12
C1708
10PF/50V
/x
LPC_FRAME# [32,34,36,37,38]
LPC_DRQ#0 [36]
INT_SERIRQ [32,33,36,38]
LPC_PD# [36]
CLK_SIOPCI_
CLK_FWHPCI_
12
C1706
10PF/50V
/X
1 2
1 2
1 2
1 2
1 2
C1707
10PF/50V
/x
LPC_AD[0..3] [32,34,36,37,38]
R1713 22Ohm
1 2
R1715 22Ohm
1 2
12
C1701
10PF/50V
/x
+3VS
1 2
12
R1707
8.2KOhm
12
C1702
10PF/50V
/x
CLK_SIOPCI [34,36]
CLK_FWHPCI [37]
PCI_PME#
C1703
10PF/50V
/x
12
C1704
10PF/50V
/x
R1701
8.2KOhm
12
3v dual
+3VSUS
12
CLK_MINIPCI [32]
CLK_CB [33]
CLK_KBC [38]
3/1
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
PCI_SERR#
PCI_DEVSEL#
PCI_IRDY#
PCI_PERR#
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PM_CLKRUN#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
LPC_DRQ#0
PCI_REQ#4
PCI_REQ#3
RP1701A
RP1701B
RP1701C
RP1701D
RP1701E
RP1701F
RP1701G
RP1701H
RP1702A
RP1702B
RP1702C
RP1702D
RP1702E
RP1702F
RP1702G
RP1702H
R1708
R1709
1 5
2 5
3 5
4 5
6 5
7 5
8 5
9 5
1 5
2 5
3 5
4 5
6 5
7 5
8 5
9 5
12
8.2KOhm
12
8.2KOhm
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
8.2KOHM
+3VS
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
+3VSUS +3VSUS
23
2
MINI_PCI_RST#
R1718
0Ohm
/debug
FOR DEBUG
5
S
Q1701
1
1
12
SI2305DS
G
D
/debug
3
R1719
330Ohm
/debug
1 2
12
+
LED1701
RED
/debug
CPU_VLD[16,61,70]
R1720
0Ohm
/debug
12
4
R1717
330Ohm
/debug
1 2
12
+
LED1702
RED
/debug
32
3
D
Q1702
BSS138
1
1
/debug
G
S
2
3
2
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
A3
Date: Sheet
A6T
Engineer:
1
MCP51_PCI/LPC
Jefing_Li
17 73Thursday, March 09, 2006
of
Rev
1.0
A
5
A
4
3
2
1
IDE_PDD[0..15] [31]
IDE_PDA[0..2] [31]
IDE_PDCS1# [31]
IDE_PDCS3# [31]
IDE_PDDACK# [31]
IDE_PDIOW# [31]
IDE_PDINTR [31]
IDE_PDDREQ [31]
IDE_PDIOR# [31]
IDE_PIORDY [31]
UDMA_DET_P [31]
IDE_SDD[0..15] [31]
IDE_SDA[0..2] [31]
IDE_SDCS1# [31]
IDE_SDCS3# [31]
IDE_SDDACK# [31]
IDE_SDIOW# [31]
IDE_SDINTR [31]
IDE_SDDREQ [31]
IDE_SDIOR# [31]
IDE_SIORDY [31]
UDMA_DET_S [31]
R1810
12
121Ohm
R1811
121Ohm
1 2
length match within
100mil,5mil wide and
10mil away from
others
+3VS
0.01UF/10V
12
C1808
0.01UF/10V
/satap
U7C
B20
SATA_A0_TX_P
A20
SATA_A0_TX_N
A19
SATA_A0_RX_N
B19
SATA_A0_RX_P
B18
SATA_A1_TX_P
A18
SATA_A1_TX_N
A17
SATA_A1_RX_N
B17
SATA_A1_RX_P
B15
SATA_B0_TX_P
A15
SATA_B0_TX_N
A16
SATA_B0_RX_N
B16
SATA_B0_RX_P
B13
SATA_B1_TX_P
A13
SATA_B1_TX_N
A14
SATA_B1_RX_N
B14
SATA_B1_RX_P
C20
SATA_LED#/GPIO_57
D14
SATA_TSTCLK_P
E13
SATA_GND
F13
SATA_TEST
F14
SATA_TERMP
E14
SATA_TERMN
F18
+1.5V_PLL_SP_VDD
F19
+1.5V_PLL_SP_SS
D20
+3.3V_PLL_SP_SS
MCP51
IDE_DATA_P0
IDE_DATA_P1
IDE_DATA_P2
IDE_DATA_P3
IDE_DATA_P4
IDE_DATA_P5
IDE_DATA_P6
IDE_DATA_P7
IDE_DATA_P8
IDE_DATA_P9
IDE_DATA_P10
IDE_DATA_P11
IDE_DATA_P12
IDE_DATA_P13
IDE_DATA_P14
IDE_DATA_P15
IDE_ADDR_P0
IDE_ADDR_P1
IDE_ADDR_P2
IDE_CS1_P#
IDE_CS3_P#
IDE_DACK_P#
IDE_IOW_P#
IDE_INTR_P
IDE_DREQ_P
IDE_IOR_P#
IDE_RDY_P
CABLE_DET_P/GPIO_63
IDE_DATA_S0
IDE_DATA_S1
IDE_DATA_S2
IDE_DATA_S3
IDE_DATA_S4
IDE_DATA_S5
IDE_DATA_S6
IDE_DATA_S7
IDE_DATA_S8
IDE_DATA_S9
IDE_DATA_S10
IDE_DATA_S11
IDE_DATA_S12
IDE_DATA_S13
IDE_DATA_S14
IDE_DATA_S15
IDE_ADDR_S0
IDE_ADDR_S1
IDE_ADDR_S2
IDE_CS1_S#
IDE_CS3_S#
IDE_DACK_S#
IDE_IOW_S#
IDE_INTR_S
IDE_DREQ_S
IDE_IOR_S#
IDE_RDY_S
CABLE_DET_S/GPIO_64
IDE_COMP_3P3
IDE_COMP_GND
R1851
10KOhm
/sata
SATA_A0_TX_P
SATA_A0_TX_N
SATA_A0_RX_N
SATA_A0_RX_P
SATA_LED# [31]
SATA_A0_TX_P[31]
SATA_A0_TX_N[31]
/sata
SATA_A0_RX_N[31]
SATA_A0_RX_P[31]
R1850
10KOhm
/sata
UM6K1N
/sata
Q1810A
+5VS
1 2
61
2
+3VS
1 2
34
5
D D
Q1810B
UM6K1N
+3V_SATA_LED#
C C
+3V_SATA_LED#
T1801TPC26T N/A
T1802TPC26T N/A
T1803TPC26T N/A
+1.5VS
12
C1804
0.1UF/10V
/satap
B B
+3VS
12
C1809
0.1UF/10V
/satap
L1801
30Ohm/100Mhz
/satap
R1812
1 2
L1802
30Ohm/100Mhz
/satap
R1813
1 2
21
0Ohm
/sata0
0.1UF/10V
/satap
21
0Ohm
/sata0
1 2
C1805
R1809
2.49KOhm
12
C1801
10UF/10V
/satap
+1.5VS
12
12
C1806
10UF/10V
/satap
1
1
1
SATA_TERMP
SATA_TERMN
+1.5V_PLL_SP_VDD
12
12
C1802
C1803
0.1UF/10V
/satap
/satap
+3.3V_PLL_SP_SS
12
C1807
0.1UF/10V
/satap
IDE_PDD0
F8
IDE_PDD1
D8
IDE_PDD2
A9
IDE_PDD3
E9
IDE_PDD4
A10
IDE_PDD5
E10
IDE_PDD6
C10
IDE_PDD7
E11
IDE_PDD8
F11
IDE_PDD9
D10
IDE_PDD10
F10
IDE_PDD11
B10
IDE_PDD12
F9
IDE_PDD13
B9
IDE_PDD14
E8
IDE_PDD15
A8
IDE_PDA0
A6
IDE_PDA1
D6
IDE_PDA2
B6
IDE_PDCS1#
A5
IDE_PDCS3#
B5
IDE_PDDACK#
B7
IDE_PDIOW#
F7
IDE_PDINTR
E6
IDE_PDDREQ
B8
IDE_PDIOR#
E7
IDE_PIORDY
A7
UDMA_DET_P
C6
IDE_SDD0
E4
IDE_SDD1
D1
IDE_SDD2
D4
IDE_SDD3
C2
IDE_SDD4
B2
IDE_SDD5
C3
IDE_SDD6
A3
IDE_SDD7
A4
IDE_SDD8
B4
IDE_SDD9
B3
IDE_SDD10
A2
IDE_SDD11
B1
IDE_SDD12
C1
IDE_SDD13
D2
IDE_SDD14
E3
IDE_SDD15
E5
IDE_SDA0
G4
IDE_SDA1
G6
IDE_SDA2
G2
IDE_SDCS1#
G1
IDE_SDCS3#
G3
IDE_SDDACK#
F5
IDE_SDIOW#
E1
IDE_SDINTR
F6
IDE_SDDREQ
E2
IDE_SDIOR#
F2
IDE_SIORDY
F1
UDMA_DET_S
G5
B11
A11
width >10mil
IDE_COMP_3P3V
IDE_COMP_GND
A
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
A3
5
4
3
2
Date: Sheet
A6T
Engineer:
MCP51_IDE/SATA
1
Jefing_Li
18 73Thursday, March 09, 2006
of
Rev
1.0
A
12
AC_RESET#
12
+3VS
+VCC_RTC
12
12
R1944 10KOhm
R1946 0Ohm
1 2
R1949 10KOhm
R1990
4.7KOhm
1 2
1 2
12
GND
5
AC_BITCLK_CODEC[42]
AC_BITCLK_MDC[45]
PULL DOWN
NOT USE
802_LED_EN[32,39,48]
1 2
R1932
49.9KOhm
C1902
1UF/10V
12
12
R1991
4.7KOhm
1 2
/C61M
/C61M
R1992 0Ohm
/X
PM_V3P3_DEEP
PM_BATLOW#
R1905 22Ohm
1 2
R1904 22Ohm
1 2
AC_SOUT[42,45]
AC_SDIN0[42]
AC_SDIN1[45]
AC_RESET#[42,43,45]
AC_SYNC[42,45]
/C61M
RN1901A
1 2
33Ohm
RN1901B
3 4
33Ohm
/C61M
LOAD_TEST[13]
RN1902A
1 2
33Ohm
RN1902B
3 4
33Ohm
BACK_OFF#[41]
FWH_WP#[37]
1 2
R1993 0Ohm
TV_EN[13]
3/7
TPC26T
3/6
+3VS
30Ohm/100Mhz
12
PM_LID#
PWRLMT#[68]
T7119
TPC26T
1
BT_ON[39]
WLAN_ON#[32]
MINIWL_ON[39]
SIO_SMI#[36]
LID_SW_SB#[49]
RTC_RST# SIO_PME#
+1.5VS
12
C1904
0.1UF/10V
+3.3V_PLL_USB
L1901
21
12
C1905
C1908
0.1UF/10V
10UF/10V
AC_BITCLK
AC_SOUT
AC_SDIN0
AC_SDIN1
1 2
R1908 10KOhm
AC_RESET#
AC_SYNC
AC_SPDIF0
CRT_DDC_CLK_MCP
CRT_DDC_DATA_MCP
LOAD_TEST
NV_I2CC_SDA_MCP
NV_I2CC_SCL_MCP
KB_SCI#[38]
CB_SD#[33]
_802_LED_EN
T7118
1
T1902N/A
1
+1.5VS
12
C1901
0.1UF/10V
+3.3V_PLL_SP_SS
12
12
C1907
C1906
0.1UF/10V
TPC26T
T1901
AC_CLK
1
KB_SCI#
CB_SD#
BACK_OFF#
FWH_WP#
TV_EN
PWRLMT#
WLAN_ON#
SIO_SMI#
PM_LID#
PM_SLP_DEEP#
PM_V3P3_DEEP
PM_BATLOW#
0.01UF/10V
+3VSUS
R1901
10KOhm
AC_RESET STRAP
0 MII
1
RGMII
R1913
D D
10KOhm
/X
3/1
CRT_DDC_CLK[40]
CRT_DDC_DATA[40]
NV_I2CC_SDA[41]
NV_I2CC_SCL[41]
+3VS
12
R1923
10KOhm
/X
AC_SPDIF0
12
R1925
10KOhm
SPDIF STRAP(SIO CLK)
0 14.314MHz
1 24MHz
CPU_PROCHOT#[9,15]
C C
JRST1
SGL_JUMP
RTC CMOS CLEAR
B B
+3VSUS
4
U7D
R22
AC97_CLK
U26
AC_BITCLK/HDA_BCLK
T25
(AC/HAD)_SDATA_OUT0/GPIO_45
R26
(AC/HAD)_SDATA_IN0/GPIO_22
T24
(AC/HAD)_SDATA_IN1/GPIO_23
U21
(AC/HAD)_SDATA_IN2/GPIO_24
U25
AC_RESET#/HDA_RST#
R21
AC_SYNC/HDA_SYNC/GPIO_44
T26
SPDIF0/GPIO_46
AE10
DDC_CLK0
AF10
DDC_DATA0
AF9
HPLUG_DET0/GPIO_47
AB10
DDC_DATA1/GPIO_53
AE9
NC
AA10
DDC_CLK1/GPIO_52
J4
GPIO_1/SLV_RDY4PWRDWN
J3
GPIO_2/CPU_SLP
J5
GPIO_3/CPU_CLKRUN
AE2
GPIO_4/AGPSTP/SUS_STAT
K5
GPIO_5/SYS_SHUTDOWN
J2
GPIO_6/NFERR/SYS_PERR
J1
GPIO_7/FERR/SYS_SERR
AC9
GPIO_8/CR_VID0
AB9
GPIO_9/CR_VID1
AA9
GPIO_10/CR_VID2
P24
GPIO_11/CPU_VID0
P25
GPIO_12/CPU_VID1
P22
GPIO_13/CPU_VID2
P26
GPIO_14/CPU_VID3
R25
GPIO_15/CPU_VID4
P23
GPIO_16/CPU_VID5
B25
LID#/GPIO_17
B24
SLP_DEEP#
E22
V3P3_DEEP
G22
LLB#
A25
RTC_RST#
B22
+1.5V_PLL_LEG
A22
+3.3V_PLL_LEG
Y21
+1.5V_PLL_USB
AD26
+3.3V_PLL_USB
MCP51
+RTCBAT
T1903
TPC26T
1
RTC Battery
P/N=07G016102032
+3VA
12
BAT1
BATT_HOLDER
GND
1 2
R1942 1KOhm
DELAY 18~25ms
D1901
2
1
1
T1904
TPC26T
USB_OC0#/GPIO_18
USB_OC1#/GPIO_19
USB_OC2#/GPIO_20
USB_OC3#/GPIO_21
USB_RBIAS_GND
A20GATE/GPIO_55
INTRUDER#
EXT_SMI#/GPIO_32
RI#/GPIO_33
PWRBTN#
SIO_PME#/GPIO_31
KBRDRSTIN#/GPIO_56
PE_WAKE#
SMB_CLK0/GPIO_25
SMB_DATA0/GPIO_26
SMB_CLK1/GPIO_27
SMB_DATA1/GPIO_28
SMB_ALERT#/GPIO_29
+3.3V_VBAT
BUF_SIO_CLK
SUS_CLK/GPIO_34
THERM#/GPIO_59
PWRGD_SB
FANRPM/GPIO_60
FANCTL0/GPIO_61
FANCTL1/GPIO_62
TEST_MODE_EN
+VCC_RTC
3
12
C1909
1UF/10V
GND
USB0_P
USB0_N
USB1_P
USB1_N
USB2_P
USB2_N
USB3_P
USB3_N
USB4_P
USB4_N
USB5_P
USB5_N
USB6_P
USB6_N
USB7_P
USB7_N
SPKR
RSTBTN#
SLP_S5#
SLP_S3#
PWRGD
AC26
AC25
AB26
AB25
AA26
AA25
Y26
Y25
W26
W25
V24
V23
V26
V25
T22
T23
Y24
Y23
U22
V22
AD25
J22
A24
M26
M25
E26
D23
M23
J21
AC3
H1
H2
M21
L25
M22
A23
J26
N21
K25
F21
C26
F24
B26
N22
L21
J25
K26
D25
1 2
15KOhm
1 2
15KOhm
1 2
15KOhm
1 2
15KOhm
1 2
15KOhm
1 2
15KOhm
1 2
15KOhm
1 2
15KOhm
22KOHM
USB_OC_01#
USB_OC_23#
USB_OC2#
USB_OC3#
USB_RBIAS_GND
A20GATE
INTRUDER#
EXT_SMI#
RI#
SB_SPKR
PWRBTN#
KBRST#
PE_WAKE#
I2C_CLK0
I2C_DATA0
I2C_CLK1
I2C_DATA1
SMB_ALERT#
CLK_SIO14_
SUS_CLK
PM_THERM#
RSTBTN#
_SUSB#
T1950 TPC26TN/A
T1951 TPC26TN/A
3
R1902
R1906
R1909
R1911
R1914
R1916
R1919
R1921
R1926
R1941
1
1
1 2
1 2
1 2
732Ohm
1%
A20GATE [38]
EXT_SMI# [38]
SB_SPKR [42]
SB_PWRBTN# [49]
SIO_PME# [36]
KBRST# [38]
1KOhm
R1903
1 2
15KOhm
R1907
1 2
15KOhm
R1910
1 2
15KOhm
R1912
1 2
15KOhm
R1915
1 2
15KOhm
R1917
1 2
15KOhm
R1920
1 2
15KOhm
R1922
1 2
15KOhm
+3VSUS
R1927
22KOHM
1 2
R1931
PM_THERM# [15]
RSTBTN# [21]
SUSC# [47,49,67]
SUSB# [33,41,67,70]
PWRGD_SB [49,50]
PWRGD [70]
CPUFAN_SPD_A [15]
+3VSUS
R1945
10KOhm
12
R1948 4.7KOhm
12
R1950
10KOhm
12
R1951
10KOhm
12
R1952
10KOhm
12
R1953
10KOhm
12
R1954
10KOhm
12
/X
USB_OC_01# [39]
USB_OC_23# [39]
+VCC_RTC
R1933
12
1MOhm
SIO_PME#
EXT_SMI#
PWRBTN#
RI#
SIO_SMI#
BACK_OFF#
FWH_WP#
12
C1910
10PF/50V/X
USB_PP0_B [39]
USB_PN0_B [39]
USB_PP1_B [39]
USB_PN1_B [39]
USB_PP2_B [39]
USB_PN2_B [39]
USB_PP3_B [39]
USB_PN3_B [39]
USB_PP4_B [41]
USB_PN4_B [41]
USB_PP5_B [33]
USB_PN5_B [33]
USB_PP6_B [39]
USB_PN6_B [39]
USB_PP7_B [39]
USB_PN7_B [39]
R1928
22KOHM
1 2
+3VSUS
R1936
10KOhm
1 2
12
C1903
0.1UF/10V
R1940 22Ohm
1 2
+3VS
22KOHM
R1929
22KOHM
1 2
R1937
2.7KOhm
1 2
+VCC_RTC
R1943 1KOhm
R1947
10KOhm
R1955 10KOhm
R1956 10KOhm
3/1
R1994
1 2
USB 4 PORTS
SPKR STRAP
0 =USER MODE BOOT
1 =SAFE MODE BOOT
+3VSUS
R1938
2.7KOhm
1 2
1 2
CLK_SIO14 [36]
KBRST#
12
KB_SCI#
12
SUS_CLK
12
TPC26T
802_LED_EN
12
_SUSB#
2
USB
CAMERA
CARD BUS
BLUE TOOTH
R1939
2.7KOhm
PE_WAKE# [46]
I2C_CLK1 [38]
I2C_DATA1 [38]
SMB_ALERT# [15]
SUS_CLK STRAP
T1905
0 =MCP51 NORMAL
1
1 =MCP51 SLAVE MODE
+3VSUS
1 2
1 2
R1924
1KOhm
/x
SB_SPKR
R1930
1KOhm
2.7KOhm
1 2
R1934
+3VSUS
1 2
R1935
2.7KOhm
+5VS
1
1
3 2
3
D
Q1901
2N7002
G
2
S
1
1
3 2
3
D
Q1902
2N7002
1
+3VS
R7111
R7112
2.7KOhm
2.7KOhm
/X
/X
1 2
1 2
3/2
G
2
S
I2C_CLK0_S [8,15]
I2C_DATA0_S [8,15]
3/7
A
final_1.00
Title :
MCP51_USB/AC97/SMB
ASUSTECH CO.,LTD.
Size Project Name
Custom
5
4
3
2
Date: Sheet
Engineer:
A6T
Jefing_Li
Rev
1.0
of
19 73Thursday, March 09, 2006
1
5
A
4
3
2
1
U7E
AE7
RGMII_TXD0/MII_TXD0
AF6
RGMII_TXD1/MII_TXD1
AB6
D D
C C
C2001
10PF/50V
/X
R2013 22Ohm
1 2
12
/x
+1.5VSUS
+3VSUS
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
C2005
0.1UF/10V
/x
12
C2008
0.1UF/10V
/x
R2001 10KOhm
R2002 10KOhm
R2003 10KOhm
R2004 10KOhm
R2005 10KOhm
R2006 10KOhm
R2007 10KOhm
R2008 10KOhm
R2009 4.7KOhm
12
R2015 10KOhm
R2010 10KOhm
R2011 10KOhm
R2012 10KOhm
FOR LAN PHY
RGMII_TXD2/MII_TXD2
AA6
RGMII_TXD3/MII_TXD3
AA7
RGMII_TXCLK/MII_TXCLK
AB7
RGMII_TXCTL/MII_TXEN
AF7
RGMII_RXD0/MII_RXD0
AF8
RGMII_RXD1/MII_RXD1
AD7
RGMII_RXD2/MII_RXD2
AB8
RGMII_RXD3/MII_RXD3
AC7
RGMII_RXCLK/MII_RXCLK
AE8
RGMII_RXCTL/MII_RXDV
AF4
RGMII_VREF/MII_VREF
AF5
RGMII_MDC/MII_MDC
AE6
RGMII_MDIO/MII_MDIO
AD3
MII_RXER/GPIO_36
AC4
MII_COL
AF2
MII_CRS
AE5
RGMII_PWRDWN/MII_PWRDWN/GPIO_37
AA8
RGMII_INTR/MII_INTR/GPIO_35
AC5
BUF_25MHZ
AE4
+1.2V_PLL_MAC_DUAL
AB5
+3.3V_PLL_MAC_DUAL
MCP51
LCD_BKL_ON/GPIO_51
LCD_BKL_CTL/GPIO_49
LCD_PANEL_PWR/GPIO_50
XTALIN_RTC
XTALOUT_RTC
NC1
NC2
NC3
NC4
XTALIN
XTALOUT
E19
D12
C25
E25
C24
E12
D24
E21
D22
C22
B23
B B
Active
High
LVDS_BACK_EN
T2010 TPC26TN/A
LVDS_VDD_EN
25M_XTALIN
25M_XTALOUT
RTC_XTALIN
RTC_XTALOUT
LVDS_BACK_EN [41]
1
LVDS_VDD_EN [41]
12
GND
C2002
22PF/50V
NPO
32.768Khz
3
2
X2001
12
25Mhz
GND
C2011
18PF/50V
1 4
18PF/50V
LVDS_VDD_EN
LVDS_BACK_EN
25M_XTALOUT25M_XTALIN
12
RTC Crystal
X2002
C2012
12
12
C2003
22PF/50V
NPO
R2621
10KOhm
1 2
GND
RTC_XTALIN
R2014
10MOhm
1 2
RTC_XTALOUT
1 2
GND
R2622
10KOhm
AF26
AF1
AD22
AD20
AD18
AD16
AD14
AD12
AD10
AD8
AD6
AD4
AC24
AB3
AA24
W24
U24
U14
U13
R24
R16
R15
R14
R13
R12
R11
N24
N17
D18
D16
C18
C16
T16
T15
T14
T13
T12
T11
P17
P16
P15
P14
P13
P12
P11
P10
F20
E18
E20
B21
A21
Y3
V3
T3
P3
U7G
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
SATA_GND1
SATA_GND2
SATA_GND3
SATA_GND4
SATA_GND5
SATA_GND6
SATA_GND7
SATA_GND8
SATA_GND9
MCP51
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
SATA_GND10
SATA_GND11
SATA_GND12
SATA_GND13
SATA_GND14
SATA_TSTCLK_N
SATA_GND15
SATA_GND16
N16
N15
N14
N13
N12
N11
N10
M16
M15
M14
M13
M12
M11
M3
L24
L16
L15
L14
L13
L12
L11
K14
K13
K3
J24
H3
G24
F3
E24
D3
C23
C11
C9
C7
C5
A26
A1
H5
H6
U4
R4
N4
L4
W4
L5
L6
C21
C19
C17
C15
C13
C14
B12
A12
Rev
1.0
A
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
B
5
4
3
2
Date: Sheet
A6T
Engineer:
MCP51_RGMI/XTAL
Jefing_Li
of
20 73Thursday, March 09, 2006
1
5
A
+1.2VS
12
C2101
22UF/6.3V
+1.2VS
D D
C C
0.1UF/10V
+1.2VS
+1.2VS
0.1UF/10V
0.1UF/10V
1UF/16V
C2107
C2124
+1.2VS
C2143
+1.5VSUS
C2151
12
12
12
12
C2102
4.7UF/6.3V
C2108
0.1UF/10V
C2118
4.7UF/6.3V
C2125
0.1UF/10V
C2144
0.1UF/10V
C2152
0.1UF/10V
12
12
12
12
12
12
C2103
1UF/16V
C2109
0.1UF/10V
C2119
1UF/16V
C2126
0.1UF/10V
C2145
0.1UF/10V
C2153
0.01UF/10V
12
12
12
12
12
12
C2104
1UF/16V
0.1UF/10V
C2120
1UF/16V
0.1UF/10V
1UF/16V
C2110
C2127
C2134
12
12
+1.2VS
12
12
12
0.1UF/10V
0.1UF/10V
C2111
C2117
12
12
4
+1.2VS
+1.5VSUS
+1.2VS
M17
M10
U17
U16
U15
U12
U11
U10
T17
T10
R17
R10
K17
K16
K15
K12
K11
K10
AE3
AF3
L17
L10
U3
R3
N3
L3
W3
U7F
+1.2V_1
+1.2V_2
+1.2V_3
+1.2V_4
+1.2V_5
+1.2V_6
+1.2V_7
+1.2V_8
+1.2V_9
+1.2V_10
+1.2V_11
+1.2V_12
+1.2V_13
+1.2V_14
+1.2V_15
+1.2V_16
+1.2V_17
+1.2V_18
+1.2V_19
+1.2V_20
+1.2V_HT_1
+1.2V_HT_2
+1.2V_HT_3
+1.2V_HT_4
+1.2V_HT_5
+1.2V_DUAL_1
+1.2V_DUAL_2
MCP51
+5V_1
+5V_2
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_HT
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_DUAL_1
+3.3V_DUAL_2
+3.3V_DUAL_3
+3.3V_DUAL_4
+3.3V_USB_DUAL_1
+3.3V_USB_DUAL_2
+1.5V_SP_A_1
+1.5V_SP_A_2
+1.5V_SP_D_1
+1.5V_SP_D_2
+1.5V_SP_A_3
+1.5V_SP_A_4
Y22
F12
AD21
AD17
AD13
AD9
AD5
C12
C8
C4
Y6
T21
P21
G21
W21
V21
F17
E17
F15
E15
E16
F16
3
0.1UF/10V
C2146
0.1UF/10V
12
C2105
0.1UF/10V
0.1UF/10V
12
C2112
12
+1.5V_SP_A_MCP
C2128
0.1UF/10V
/satap
C2135
C2106
0.1UF/10V
4.7UF/6.3V
0.1UF/10V
12
12
10UF/10V
/satap
12
12
C2113
+3V_HT_MCP
12
C2121
12
C2147
C2129
0.1UF/10V
/satap
C2137
R2111100Ohm
1 2
R2112100Ohm
1 2
C2114
0.1UF/10V
C2123
0.01UF/10V
C2148
0.1UF/10V
12
C2130
0.1UF/10V
/satap
12
C2138
0.1UF/10V
/satap
12
12
12
12
0.1UF/10V
/satap
12
0.1UF/10V
/satap
0.1UF/10V
0.1UF/10V
C2131
2/8
C2115
C2149
12
2
+5VS
12
0.1UF/10V
L2102
21
30Ohm/100Mhz
12
0.1UF/10V
L2101
21
47Ohm/100Mhz
/satap
R2104
1 2
C2116
C2150
0Ohm
/sata0
12
12
C2139
10UF/10V
1
+3VS
+3VS
+3VSUS
+1.5VS
12
1.5V
FOR SATA & MXM CONNECTOR
1.5V_SP_A @440MA
1.5V_SP_D @164MA
1.5V_PLL_SP_DVDD @20MA
1.5V_PLL_SP_AVDD @160MA
/RESET button
B B
SW2101
1
132
3
TACT_SWITCH_5P
/X
2
4
4
5
5
R2103 33Ohm
1 2
C2154
1UF/16V
/debug
+3VSUS
12
R2110
10KOhm
RSTBTN# [19]
12
1.5V_PLL_CPU_HT @71MA
1.5V_PLL_SP_SS @10MA
1.5V_PLL_LEG @4MA
1.5V_PLL_USB_CORE @16MA
A
final_1.00
Title :
ASUSTECH CO.,LTD.
Size Project Name
A3
5
4
3
2
Date: Sheet
A6T
Engineer:
1
MCP51_VCC
Jefing_Li
21 73Thursday, March 09, 2006
of
Rev
1.0
5
A
4
3
2
1
D D
C C
B B
final_1.00
Title :
ASUS-SER
Size Project Name
A3
5
4
3
2
Date: Sheet
<Doc>
Engineer:
1
<Title>
lanny_zhang
22 73Monday, March 06, 2006
of
Rev
1.0
A
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