ASUS A45VD Schematics

1 1

2 2

Compal Confidential

QCL40 MB Schematic Document

LA-8224P

3 3

v: 0.2

2011.09.28

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-8224P

0.2

1 59Thursday, October 27, 2011

0.2

Compal Confidential

ZZZ1

PCB-MB

PCB P/N for Load BOM

DA80000QT00

A A

NV N13M-GE1

PEG 16X

Gb1B-64 23x23mm

Page 20 ~ 28

LCD conn

B B

CRT Conn

HDMI

C C

Page 30

Page 35

LVDS, EDID, DISPOFF#, PWM

RGB, HV Sync, DDC

HDMI, DDC

PCI-e

port 4

ASM1042 USB3.0 Controller

page 36

USB3.0 conn x2

Page 37

LAN/CRT Board

10/100/1000 LAN

Realtek GbE

RTL8111F

Page 32

port 2port 1

Mini Card-1

WLAN Bluetooth

Page 40

QCL40

Mobile

Ivy Bridge Processor

rPGA 988B Socket

+VCC_CORE, +VCCP, +VCC_GFXCORE_AVG, +1.5V_CPU_VDDQ, +1.8VS, _VCCSA

FDI x8 (UMA)

100MHz

2.7GT/s

ANTHER-POINT

FCBGA 989 Balls

+1.05VS, +1.8VS, +3VS, +3V_PCH, +5V_PCH, +RTCVCC, +VCCAFDI_VRM

Intel PCH

HM77

Page 4 ~ 9

Page 12 ~ 19

LPC BUS

DMI x4

100M 5GB/s

DDR3 1333/1600MHz 1.5V

Dual Channel

USB2.0

USB3.0

Azalia

SATA

SPI

port 4

port 0,1

port 1,2

port 0

port 2

DDR3-SO-DIMM X 2

BANK 0, 1, 2, 3

USB conn x1

USB Board

port 8

port 10

Camera

Card Reader RTS5137

port 9

MiniCard-2

USB3.0 conn x2

Realtek ALC269

2.5" SATA HDD Connector

SATA ODD Connector

SPI ROM 4MB+2MB

Page 12

+1.5V, +0.75VS

Page 10, 11

Page 33

Page 30

Page 34

Page 40

Page 36

Page 33

Page 31

Memory Card Slot

SD/MMC

Audio Jack (HP)

Audio Jack (MIC)

Speaker Connector

Page 34

Page 33

D D

DC/DC Interface CKT.

Page 29,41

External board

LS-4221P USB/B

Page 33

Touch Pad CONN.

Page 38

Fan Control

Page 37

ENE KB9012QF

Reserve KB930F

+3VLP/+3VALW

SPI ROM

256KB

Page 39

page 39

Int. KBD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Page 38

Compal Secret Data

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-8224P

2 59Thursday, October 27, 2011

0.2

X76@:

ER39

N13P-GS N13P-GL N13M-GE1 N13M-GE1 x8

GS@ G

DIS@:

GE8@:

9012@:

1 1

930@:

XDP@:

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

PCH_SMBCLK PCH_SMBDATA PCH

PCH_SMLCLK PCH_SMLDATA

CLK

VRAMX16X8 V

ZZZ11

X76L11@ZZZ11

X76L11@ ZZZ3

2G HYN

ZZZ12

X76L12@ZZZ12

X76L12@

2G SAM

U10

GS@U10

GS@

N13P-GS

VGA componet N13M-GE1_GB1b

EC(ENE 9012 chip) EC(ENE 930 chip) Intel debug port

SOURCE

KB930

ZZZ

2G SAM

ZZZ2

2G HYN

ZZZ5

1G SAM

ZZZ6

1G HYN

L@ GE@ GE8@

U10

N13P-GL

MINI1 BATT SODIMM

X X

PCH

CLKOUT_PCIE0 CLKOUT_PCIE1 CLKOUT_PCIE2 CLKOUT_PCIE3 CLKOUT_PCIE4 CLKOUT_PCIE5

CLKOUT_PCIE7 None CLKOUT_PEG_B

X X

RAMX16X4 VRAMX8X8

X76L01@ZZZ

X76L01@

1G SAM

X X

ZZZ4

1G HYN

U10

N13M-GE1

IU3@:

USB30@:

AI@:

NAI@:

PCH

X76L02@ZZZ2

X76L02@

X76L05@ZZZ5

X76L05@

X76L06@ZZZ6

X76L06@

GL@U10

GL@

DESTINATIONDIFFERENTIAL

MINI CARD WLAN None USB3.0 controller None None NoneCLKOUT_PCIE6

None

X76L03@ZZZ3

X76L03@

X76L04@ZZZ4

X76L04@

GE@U10

GE@

USB3.0 by PCH

USB3.0 controller IC

AI Charger Non AI Charger

X X

ZZZ7

2G HYN

ZZZ8

2G ELP

ZZZ9

4G ELP

ZZZ10

4G HYN

U10

N13M-GE1 x8

DGPU

X76L07@ZZZ7

X76L07@

X76L08@ZZZ8

X76L08@

X76L09@ZZZ9

X76L09@

X76L10@ZZZ10

X76L10@

GE8@U10

GE8@

FLEX CLOCKS DESTINATION CLKOUTFLEX010/100/1G LAN CLKOUTFLEX1 CLKOUTFLEX2 CLKOUTFLEX3

Symbol Note :

N13M-GE1 x8N13M-GE1N13P-GLN13P-GS

CLKOUT PCI0 PCI1 PCI2 PCI3 PCI4

DESTINATION

PCH_LOOPBACK

EC None

LPC Debug Port

None

PCH

USB3 PORT

1 2 3 4

DESTINATION

Voltage Rails

Power Plane Description

VIN BATT+ B+ +3VLP +3VALW ON3.3V always on power rail +LAN_IO OFF +3VS_WLAN ON +3V_PCH ON +3VS +3VSG +LCDVDD +5VALW ON +5V_PCH +5VS +5VS_ODD +1.8VS +1.05VS ON +VCCP +1.05VSG +1.5V

+1.5V_CPU_VDDQ

+1.5VSG +1.5VS +0.75VS +VCCSA +VCC_CORE

+VCC_GFXCORE_AXG

+VGA_CORE

Adapter power supply (19V) Battery power supply (12.6V) AC or battery power rail for power circuit

3.3V power rail for 51ON power management

3.3V power rail for DDR SPI,PCH,HDD,Audio,Card Reader

3.3V power rail for LCD 5V always on power rail 5V power rail for PCH suspend well plane 5V power rail for HDD,AUDIO,FAN,Touch PAD 5V power rail for SATA ODD

1.8V power rail for CPU,PCH

1.05V power rail for PCH

1.05V power rail for CPU VCCIO,PCH

1.05V power rail for N13P

1.5V power rail for DDR3 system memory

1.5V power rail CPU VDDQ

1.5V power rail for N13P,VRAM

1.5V power rail for PCH,WLAN/BT combo

0.75V power rail for DDR VREF VCCSA for CPU system agent CORE Voltage for CPU

1.5V power rail for N13P,VRAM CORE Voltage for N13P Graphics ON OFF OFF

SATA SATA0 SATA1

SATA2 CLK_SD_48M None None

SATA3

SATA4

SATA5

S1 S3 S5

N/A N/A N/A

N/A N/A N/A N/A ON ON ON ON

ON ON

ON3.3V power rail for ethernet

OFF OFF ON

OFF OFF OFF

OFF OFF3.3V power rail for VGA

OFF OFF ON

ON OFF

OFF

ON ON

OFF OFF OFF OFF OFF OFF

OFF OFF

OFF OFF OFF

OFF

OFF OFF OFF

DESTINATION

HDD None ODD None None None

None

: means Digital Ground

Security Classification

: means Analog Ground

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTR ONICS, INC.

2011/07/12 2012/12/31

USB2.0+3.0 USB2.0+3.0

None None

Deep S3

N/A

N/AN/AN/A

N/A

AC/ON; DC/OFF

OFF

OFF3.3V power rail for WLAN/BT Combo

OFF OFF3.3V power rail for PCH suspend well plane

OFF OFF ON

AC/ON; DC/OFF

OFF

OFF OFFOFF

Compal Secret Data

Deciphered Date

PCH

PCI EXPRESS

Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane 6 Lane 7 Lane 8

USB2 PORT

0 1 2 3 4 5 6 7 8 9 10 11 12 13

DESTINATION 10/100/1G LAN MINI CARD WLAN None USB3.0 controller None None None None

DESTINATION USB2.0+3.0 USB2.0+3.0 None None J

MINI1 (WLAN)

Bluetooth None None None CAMERA U

SB2 Card Reader None None None

Compal Electronics, Inc.

Title

Notes List

Size Document Number Rev

LA-8224P

Date: Sheet of

3 59Thursday, October 27, 2011

0.2

JCPU1A

D D

DMI_CRX_PTX_N014 DMI_CRX_PTX_N114 DMI_CRX_PTX_N214 DMI_CRX_PTX_N314

DMI_CRX_PTX_P014 DMI_CRX_PTX_P114 DMI_CRX_PTX_P214 DMI_CRX_PTX_P314

DMI_CTX_PRX_N014 DMI_CTX_PRX_N114 DMI_CTX_PRX_N214 DMI_CTX_PRX_N314

DMI_CTX_PRX_P014 DMI_CTX_PRX_P114 DMI_CTX_PRX_P214 DMI_CTX_PRX_P314

FDI_CTX_PRX_N014 FDI_CTX_PRX_N114 FDI_CTX_PRX_N214 FDI_CTX_PRX_N314 FDI_CTX_PRX_N414 FDI_CTX_PRX_N514

C C

+1.05VS

24.9_0402_1%

eDP_COMPIO and ICOMPO signals should be shorted

B B

near balls and routed with typical impedance <25 mohms

FDI_CTX_PRX_N614 FDI_CTX_PRX_N714

FDI_CTX_PRX_P014 FDI_CTX_PRX_P114 FDI_CTX_PRX_P214 FDI_CTX_PRX_P314 FDI_CTX_PRX_P414 FDI_CTX_PRX_P514 FDI_CTX_PRX_P614 FDI_CTX_PRX_P714

FDI_FSYNC014 FDI_FSYNC114

FDI_INT14 FDI_LSYNC014

FDI_LSYNC114

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

EDP_COMP

JCPU1A

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

CONN@

DMI

Intel(R) FDI

eDP

+1.05VS

PEG_ICOMPI and RCOMPO signals should be shorted and routed

24.9_0402_1%

PEG_COMP

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

J22 J21 H22

PCIE_GTX_CRX_N15

K33

PCIE_GTX_CRX_N14

M35

PCIE_GTX_CRX_N13

L34

PCIE_GTX_CRX_N12

J35

PCIE_GTX_CRX_N11

J32

PCIE_GTX_CRX_N10

H34

PCIE_GTX_CRX_N9

H31

PCIE_GTX_CRX_N8

G33

PCIE_GTX_CRX_N7

G30

PCIE_GTX_CRX_N6

F35

PCIE_GTX_CRX_N5

E34

PCIE_GTX_CRX_N4

E32

PCIE_GTX_CRX_N3

D33

PCIE_GTX_CRX_N2

D31

PCIE_GTX_CRX_N1

B33

PCIE_GTX_CRX_N0

C32

PCIE_GTX_CRX_P15

J33

PCIE_GTX_CRX_P14

L35

PCIE_GTX_CRX_P13

K34

PCIE_GTX_CRX_P12

H35

PCIE_GTX_CRX_P11

H32

PCIE_GTX_CRX_P10

G34

PCIE_GTX_CRX_P9

G31

PCIE_GTX_CRX_P8

F33

PCIE_GTX_CRX_P7

F30

PCIE_GTX_CRX_P6

E35

PCIE_GTX_CRX_P5

E33

PCIE_GTX_CRX_P4

F32

PCIE_GTX_CRX_P3

D34

PCIE_GTX_CRX_P2

E31

PCIE_GTX_CRX_P1

C33

PCIE_GTX_CRX_P0

B32

PCIE_CTX_GRX_N15

M29

PCIE_CTX_GRX_N14

M32

PCIE_CTX_GRX_N13

M31

PCIE_CTX_GRX_N12

L32

PCIE_CTX_GRX_N11

L29

PCIE_CTX_GRX_N10

K31

PCIE_CTX_GRX_N9

K28

PCIE_CTX_GRX_N8

J30

PCIE_CTX_GRX_N7

J28

PCIE_CTX_GRX_N6

H29

PCIE_CTX_GRX_N5

G27

PCIE_CTX_GRX_N4

E29

PCIE_CTX_GRX_N3

F27

PCIE_CTX_GRX_N2

D28

PCIE_CTX_GRX_N1

F26

PCIE_CTX_GRX_N0

E25

PCIE_CTX_GRX_P15

M28

PCIE_CTX_GRX_P14

M33

PCIE_CTX_GRX_P13

M30

PCIE_CTX_GRX_P12

L31

PCIE_CTX_GRX_P11

L28

PCIE_CTX_GRX_P10

K30

PCIE_CTX_GRX_P9

K27

PCIE_CTX_GRX_P8

J29

PCIE_CTX_GRX_P7

J27

PCIE_CTX_GRX_P6

H28

PCIE_CTX_GRX_P5

G28

PCIE_CTX_GRX_P4

E28

PCIE_CTX_GRX_P3

F28

PCIE_CTX_GRX_P2

D27

PCIE_CTX_GRX_P1

E26

PCIE_CTX_GRX_P0

D25

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with - max length = 500 mils

- typical impedance = 14.5 mohms

C1 0.22U_0402_10V6KDIS@ C1 0.22U_0402_10V6KDIS@

1 2

C2 0.22U_0402_10V6KDIS@ C2 0.22U_0402_10V6KDIS@

1 2

C3 0.22U_0402_10V6KDIS@ C3 0.22U_0402_10V6KDIS@

1 2

C4 0.22U_0402_10V6KDIS@ C4 0.22U_0402_10V6KDIS@

1 2

C5 0.22U_0402_10V6KDIS@ C5 0.22U_0402_10V6KDIS@

1 2

C6 0.22U_0402_10V6KDIS@ C6 0.22U_0402_10V6KDIS@

1 2

C7 0.22U_0402_10V6KDIS@ C7 0.22U_0402_10V6KDIS@

1 2

C8 0.22U_0402_10V6KDIS@ C8 0.22U_0402_10V6KDIS@

1 2

C9 0.22U_0402_10V6KDIS@ C9 0.22U_0402_10V6KDIS@

1 2

C10 0.22U_0402_10V6KDIS@ C10 0.22U_0402_10V6KDIS@

1 2

C11 0.22U_0402_10V6KDIS@ C11 0.22U_0402_10V6KDIS@

1 2

C12 0.22U_0402_10V6KDIS@ C12 0.22U_0402_10V6KDIS@

1 2

C13 0.22U_0402_10V6KDIS@ C13 0.22U_0402_10V6KDIS@

1 2

C14 0.22U_0402_10V6KDIS@ C14 0.22U_0402_10V6KDIS@

1 2

C15 0.22U_0402_10V6KDIS@ C15 0.22U_0402_10V6KDIS@

1 2

C16 0.22U_0402_10V6KDIS@ C16 0.22U_0402_10V6KDIS@

1 2

C17 0.22U_0402_10V6KDIS@ C17 0.22U_0402_10V6KDIS@

1 2

C18 0.22U_0402_10V6KDIS@ C18 0.22U_0402_10V6KDIS@

1 2

C19 0.22U_0402_10V6KDIS@ C19 0.22U_0402_10V6KDIS@

1 2

C20 0.22U_0402_10V6KDIS@ C20 0.22U_0402_10V6KDIS@

1 2

C21 0.22U_0402_10V6KDIS@ C21 0.22U_0402_10V6KDIS@

1 2

C22 0.22U_0402_10V6KDIS@ C22 0.22U_0402_10V6KDIS@

1 2

C23 0.22U_0402_10V6KDIS@ C23 0.22U_0402_10V6KDIS@

1 2

C24 0.22U_0402_10V6KDIS@ C24 0.22U_0402_10V6KDIS@

1 2

C25 0.22U_0402_10V6KDIS@ C25 0.22U_0402_10V6KDIS@

1 2

C26 0.22U_0402_10V6KDIS@ C26 0.22U_0402_10V6KDIS@

1 2

C27 0.22U_0402_10V6KDIS@ C27 0.22U_0402_10V6KDIS@

1 2

C28 0.22U_0402_10V6KDIS@ C28 0.22U_0402_10V6KDIS@

1 2

C29 0.22U_0402_10V6KDIS@ C29 0.22U_0402_10V6KDIS@

1 2

C30 0.22U_0402_10V6KDIS@ C30 0.22U_0402_10V6KDIS@

1 2

C31 0.22U_0402_10V6KDIS@ C31 0.22U_0402_10V6KDIS@

1 2

C32 0.22U_0402_10V6KDIS@ C32 0.22U_0402_10V6KDIS@

1 2

C33 0.22U_0402_10V6KDIS@ C33 0.22U_0402_10V6KDIS@

1 2

C34 0.22U_0402_10V6KDIS@ C34 0.22U_0402_10V6KDIS@

1 2

C35 0.22U_0402_10V6KDIS@ C35 0.22U_0402_10V6KDIS@

1 2

C36 0.22U_0402_10V6KDIS@ C36 0.22U_0402_10V6KDIS@

1 2

C37 0.22U_0402_10V6KDIS@ C37 0.22U_0402_10V6KDIS@

1 2

C38 0.22U_0402_10V6KDIS@ C38 0.22U_0402_10V6KDIS@

1 2

C39 0.22U_0402_10V6KDIS@ C39 0.22U_0402_10V6KDIS@

1 2

C40 0.22U_0402_10V6KDIS@ C40 0.22U_0402_10V6KDIS@

1 2

C41 0.22U_0402_10V6KDIS@ C41 0.22U_0402_10V6KDIS@

1 2

C42 0.22U_0402_10V6KDIS@ C42 0.22U_0402_10V6KDIS@

1 2

C43 0.22U_0402_10V6KDIS@ C43 0.22U_0402_10V6KDIS@

1 2

C44 0.22U_0402_10V6KDIS@ C44 0.22U_0402_10V6KDIS@

1 2

C45 0.22U_0402_10V6KDIS@ C45 0.22U_0402_10V6KDIS@

1 2

C46 0.22U_0402_10V6KDIS@ C46 0.22U_0402_10V6KDIS@

1 2

C47 0.22U_0402_10V6KDIS@ C47 0.22U_0402_10V6KDIS@

1 2

C48 0.22U_0402_10V6KDIS@ C48 0.22U_0402_10V6KDIS@

1 2

C49 0.22U_0402_10V6KDIS@ C49 0.22U_0402_10V6KDIS@

1 2

C50 0.22U_0402_10V6KDIS@ C50 0.22U_0402_10V6KDIS@

1 2

C51 0.22U_0402_10V6KDIS@ C51 0.22U_0402_10V6KDIS@

1 2

C52 0.22U_0402_10V6KDIS@ C52 0.22U_0402_10V6KDIS@

1 2

C53 0.22U_0402_10V6KDIS@ C53 0.22U_0402_10V6KDIS@

1 2

C54 0.22U_0402_10V6KDIS@ C54 0.22U_0402_10V6KDIS@

1 2

C55 0.22U_0402_10V6KDIS@ C55 0.22U_0402_10V6KDIS@

1 2

C56 0.22U_0402_10V6KDIS@ C56 0.22U_0402_10V6KDIS@

1 2

C57 0.22U_0402_10V6KDIS@ C57 0.22U_0402_10V6KDIS@

1 2

C58 0.22U_0402_10V6KDIS@ C58 0.22U_0402_10V6KDIS@

1 2

C59 0.22U_0402_10V6KDIS@ C59 0.22U_0402_10V6KDIS@

1 2

C60 0.22U_0402_10V6KDIS@ C60 0.22U_0402_10V6KDIS@

1 2

C61 0.22U_0402_10V6KDIS@ C61 0.22U_0402_10V6KDIS@

1 2

C62 0.22U_0402_10V6KDIS@ C62 0.22U_0402_10V6KDIS@

1 2

C63 0.22U_0402_10V6KDIS@ C63 0.22U_0402_10V6KDIS@

1 2

C64 0.22U_0402_10V6KDIS@ C64 0.22U_0402_10V6KDIS@

1 2

PCIE_GTX_C_CRX_N15 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_N7 PCIE_GTX_C_CRX_N6 PCIE_GTX_C_CRX_N5 PCIE_GTX_C_CRX_N4 PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_N1 PCIE_GTX_C_CRX_N0

PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_P11 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_P0

PCIE_CTX_C_GRX_N15 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N8 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N0

PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P0

PCIE_CTX_C_GRX_N[0..15] 20

PCIE_CTX_C_GRX_P[0..15] 20

PCIE_GTX_C_CRX_N[0..15] 20

PCIE_GTX_C_CRX_P[0..15] 20

M34

G35 G32 G29 G26 G23 G20 G17 G11

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

VSS171

VSS172

VSS173

VSS174

VSS175

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186 VSS187

L33

VSS188

L30

VSS189

L27

VSS190

VSS191

VSS192

VSS193

VSS194

VSS195

VSS196

VSS197

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

VSS214

VSS215

VSS216

VSS217

VSS218

VSS219

VSS220

VSS221

VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

TYCO_2013620-2_IVY BRIDGE

CONN@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/6) DMI,FDI,PEG

LA-8224P

4 59Thursday, October 27, 2011

0.2

+3VS

ER17

10K_0402_5%

S_PWG D_PWG

1 2

1 2 1 2 1 2

+3VALW

+3V_PCH

R267

R576

1 2

+3VS

A2Y

SN74LVC1G07DCKR_SC70-5

+3VS

R241K_0402_5% R241K_0402_5%

R2510K_0402_5% R2510K_0402_5%

R34140_0402_1% R34140_0402_1% R3825.5_0402_1% R3825.5_0402_1% R39200_0402_1% R39200_0402_1%

0_0402_5%

1 2

0.1U_0402_16V4Z~D

C65

74AHC1G09GW TSSOP 5P

+1.05VS

0.1U_0402_16V4Z

C69

BUFO_CPU_RST# BUF_CPU_RST#

R15

R15 75_0402_5%

75_0402_5%

R17

1 2

43_0402_1%

+1.5V_CPU_VDDQ

VDDPWRGOOD

PU/PD for JTAG signals

XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TDO_R

XDP_TCK XDP_TRST#

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(2/6) PM,XDP,CLK

LA-8224P

1 2 1 2 1 2 1 2

1 2 1 2

R4 200_0402_1%

200_0402_1%

R20

R20 0_0402_5%

0_0402_5%

R2651_0402_5% R2651_0402_5% R2751_0402_5% R2751_0402_5% R2851_0402_5% @ R2851_0402_5% @ R2951_0402_5% R2951_0402_5%

R3251_0402_5% R3251_0402_5% R3351_0402_5% R3351_0402_5%

5 59Thursday, October 27, 2011

+1.05VS

0.2

JXDP1

XDP_PREQ# XDP_PRDY#

R51K_0402_5%

D D

C C

PBTN_OUT#14,40

CLK_CPU_ITP13

CLK_CPU_ITP#13

Processor Pullups

H_PROCHOT#

H_PECI40

H_PROCHOT#40,43

B B

H_THERMTRIP#16

H_PM_SYNC14

H_CPUPWRGD16

A A

1 2

H_SNB_IVB#16

PAD @

H_CPUPWRGD

VDDPWRGOOD

1 2

C72 100P_0402_50V8J

H_CPUPWRGD H_CPUPWRGD_XDP

CFG07 VGATE14,51

+1.05VS

R1662_0402_5% R1662_0402_5%

H_CATERR#

H_PECI

R23

H_PROCHOT#_R

1 2

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

ER20

R684

H_CPUPWRGD_R

1 2

0_0402_5%

0_0402_5% R36

R36

VDDPWRGOOD_R

1 2

130_0402_1%

BUF_CPU_RST#

VDDPWRGOOD_R

Reserve for EMI please close to JCPU1

1 2

H_CPUPWRGD_R

ER20

C421 100P_0402_50V8J

Reserve for EMI please close to JCPU1

R51K_0402_5%

XDP@

1 2 1 2 1 2 1 2

1 2

XDP@ R13

XDP@

1 2

1K_0402_5%

CFD_PWRBTN#_XDP

R60_0402_5% XDP@ R60_0402_5% XDP@

XDP_HOOK2

R71K_0402_5% XDP@ R71K_0402_5% XDP@

SYS_PWROK_XDP

R100_0402_5% XDP@ R100_0402_5% XDP@

CLK_CPU_ITP CLK_CPU_ITP# +VCCP_XDP

R120_0402_5% XDP@ R120_0402_5% XDP@

XDP_RST#_RPLT_RST#

R13

XDP_DBRESET# XDP_TDO

XDP_TRST# XDP_TDI XDP_TMS

XDP_TCK

1 2

C68 100P_0402_50V8J

Reserve for EMI please close to JCPU1

JCPU1B

C26

PROC_SELECT#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

SM_DRAMPWROK

AR33

RESET#

TYCO_2013620-2_IVY BRIDGE

CONN@

1 2

C426 100P_0402_50V8J

Reserve for EMI please close to JCPU1

JXDP1

+3VALW

ACES_87152-26051

CONN@

H_PECI

MISCTHERMALPWR MANAGEMENT

BUF_CPU_RST#

DPLL_REF_CLK#

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

R8 1K_0402_5%

1K_0402_5%

SYS_PWROK_XDP

BCLK

BCLK#

DPLL_REF_CLK

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TDI

XDP@

CLK_CPU_DMI_R

A28

CLK_CPU_DMI#_R

A27

CLK_CPU_DPLL_R

A16

CLK_CPU_DPLL#_R

A15

H_DRAMRST#

SM_RCOMP0

AK1

SM_RCOMP1

SM_RCOMP2

XDP_PRDY#

AP29

XDP_PREQ#

AP27

XDP_TCK

AR26

XDP_TMS

AR27

XDP_TRST#

AP30

XDP_TDI_R

AR28

XDP_TDO_R

AP26

XDP_DBRESET#_R1

AL35

XDP_BPM#0

AT28

XDP_BPM#1

AR29

XDP_BPM#2

AR30

XDP_BPM#3

AT30

XDP_BPM#4

AP32

XDP_BPM#5

AR31

XDP_BPM#6

AT31

XDP_BPM#7

AR32

+1.05VS

0.1U_0402_16V4Z~D

XDP@

C66

Place near JXDP1

R30 0_0402_5%XDP@R30 0_0402_5%XDP@

1 2

R31 0_0402_5%XDP@R31 0_0402_5%XDP@

1 2

R35 0_0402_5%XDP@R35 0_0402_5%XDP@

1 2

R37 0_0402_5%R37 0_0402_5%

1 2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

0.1U_0402_16V4Z~D

C67

SYSTEM_PWROK14

PM_DRAM_PWRGD14

+3V_PCH

R18 0_0402_5%R18 0_0402_5%

1 2

R19 0_0402_5%R19 0_0402_5%

1 2

H_DRAMRST# 6

1 2

C70 100P_0402_50V8J

CLK_CPU_DMI 13 CLK_CPU_DMI# 13

CLK_CPU_DPLL#_R CLK_CPU_DPLL_R

H_DRAMRST#

Reserve for EMI please close to JCPU1

XDP_TDI XDP_TDO

XDP_DBRESET#

T2 PAD@ T2 PAD@ T3 PAD@ T3 PAD@ T4 PAD@ T4 PAD@ T5 PAD@ T5 PAD@ T6 PAD@ T6 PAD@ T7 PAD@ T7 PAD@ T8 PAD@ T8 PAD@ T9 PAD@ T9 PAD@

C71 100P_0402_50V8J

Reserve for EMI please close to JCPU1

2011/07/12 2012/12/31

Issued Date

2011/07/12 2012/12/31

200_0402_1%

XDP_DBRESET#_R 12,14

XDP_DBRESET#_R1

1 2

Compal Secret Data

1 2

R21

1 2 1 2

R22

Deciphered Date

1 2

0_0402_5%@

1 2

R11 0_0402_5%R11 0_0402_5%

R14

PLT_RST#15,32,36,40,41

+1.05VS

1K_0402_1%

1K_0402_1% 1K_0402_1%

1K_0402_1%

XDP_DBRESET#_R1

H_CPUPWRGD_R

ER20

DDR3 Compensation Signals

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

JCPU1C

DDR_A_D[0..63]10

D D

C C

B B

DDR_A_BS010 DDR_A_BS110 DDR_A_BS210

DDR_A_CAS#10 DDR_A_RAS#10 DDR_A_WE#10

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

SA_DQ[0]

SA_DQ[1]

SA_DQ[2]

SA_DQ[3]

SA_DQ[4]

SA_DQ[5]

SA_DQ[6]

SA_DQ[7]

F10

SA_DQ[8]

SA_DQ[9]

G10

SA_DQ[10]

SA_DQ[11]

SA_DQ[12]

SA_DQ[13]

SA_DQ[14]

SA_DQ[15]

SA_DQ[16]

SA_DQ[17]

SA_DQ[18]

SA_DQ[19]

SA_DQ[20]

SA_DQ[21]

SA_DQ[22]

SA_DQ[23]

SA_DQ[24]

N10

SA_DQ[25]

SA_DQ[26]

SA_DQ[27]

M10

SA_DQ[28]

SA_DQ[29]

SA_DQ[30]

SA_DQ[31]

AG6

SA_DQ[32]

AG5

SA_DQ[33]

AK6

SA_DQ[34]

AK5

SA_DQ[35]

AH5

SA_DQ[36]

AH6

SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]

AK8

SA_DQ[41]

AJ9

SA_DQ[42]

AK9

SA_DQ[43]

AH8

SA_DQ[44]

AH9

SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]

AP11

SA_DQ[48]

AN11

SA_DQ[49]

AL12

SA_DQ[50]

AM12

SA_DQ[51]

AM11

SA_DQ[52]

AL11

SA_DQ[53]

AP12

SA_DQ[54]

AN12

SA_DQ[55]

AJ14

SA_DQ[56]

AH14

SA_DQ[57]

AL15

SA_DQ[58]

AK15

SA_DQ[59]

AL14

SA_DQ[60]

AK14

SA_DQ[61]

AJ15

SA_DQ[62]

AH15

SA_DQ[63]

AE10

SA_BS[0]

AF10

SA_BS[1]

SA_BS[2]

AE8

SA_CAS#

AD9

SA_RAS#

AF9

SA_WE#

TYCO_2013620-2_IVY BRIDGE

CONN@

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1] RSVD_TP[2] RSVD_TP[3]

RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]

SA_CS#[0]

SA_CS#[1] RSVD_TP[7] RSVD_TP[8]

SA_ODT[0]

SA_ODT[1] RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDRA_CLK0 10 DDRA_CLK0# 10 DDRA_CKE0 10

DDRA_CLK1 10 DDRA_CLK1# 10 DDRA_CKE1 10

DDRA_SCS0# 10 DDRA_SCS1# 10

DDRA_ODT0 10 DDRA_ODT1 10

DDR_A_DQS#[0..7] 10

DDR_A_DQS[0..7] 10

DDR_A_MA[0..15] 10

DDR_B_D[0..63]11

DDR_B_BS011 DDR_B_BS111 DDR_B_BS211

DDR_B_CAS#11 DDR_B_RAS#11 DDR_B_WE#11

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

JCPU1D

SB_DQ[0]

SB_DQ[1]

D10

SB_DQ[2]

SB_DQ[3]

SB_DQ[4]

SB_DQ[5]

SB_DQ[6]

SB_DQ[7]

SB_DQ[8]

SB_DQ[9]

SB_DQ[10]

SB_DQ[11]

SB_DQ[12]

SB_DQ[13]

SB_DQ[14]

SB_DQ[15]

SB_DQ[16]

SB_DQ[17]

K10

SB_DQ[18]

SB_DQ[19]

SB_DQ[20]

J10

SB_DQ[21]

SB_DQ[22]

SB_DQ[23]

SB_DQ[24]

SB_DQ[25]

SB_DQ[26]

SB_DQ[27]

SB_DQ[28]

SB_DQ[29]

SB_DQ[30]

SB_DQ[31]

AM5

SB_DQ[32]

AM6

SB_DQ[33]

AR3

SB_DQ[34]

AP3

SB_DQ[35]

AN3

SB_DQ[36]

AN2

SB_DQ[37]

AN1

SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]

AN9

SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]

AN8

SB_DQ[45]

AR6

SB_DQ[46]

AR5

SB_DQ[47]

AR9

SB_DQ[48]

AJ11

SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]

AH11

SB_DQ[52]

AR8

SB_DQ[53]

AJ12

SB_DQ[54]

AH12

SB_DQ[55]

AT11

SB_DQ[56]

AN14

SB_DQ[57]

AR14

SB_DQ[58]

AT14

SB_DQ[59]

AT12

SB_DQ[60]

AN15

SB_DQ[61]

AR15

SB_DQ[62]

AT15

SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

SB_BS[2]

AA10

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

TYCO_2013620-2_IVY BRIDGE

CONN@

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

RSVD_TP[11]

AA2

RSVD_TP[12]

RSVD_TP[13]

AA1

RSVD_TP[14]

AB1

RSVD_TP[15]

T10

RSVD_TP[16]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

RSVD_TP[17]

AE6

RSVD_TP[18]

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5

RSVD_TP[19]

AE5

RSVD_TP[20]

DDR_B_DQS#0

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDRB_CLK0 11 DDRB_CLK0# 11 DDRB_CKE0 11

DDRB_CLK1 11 DDRB_CLK1# 11 DDRB_CKE1 11

DDRB_SCS0# 11 DDRB_SCS1# 11

DDRB_ODT0 11 DDRB_ODT1 11

DDR_B_DQS#[0..7] 11

DDR_B_DQS[0..7] 11

DDR_B_MA[0..15] 11

+1.5V

R40

R40 1K_0402_5%

BSS138_SOT23

H_DRAMRST#5

A A

H_DRAMRST# DDR3_DRAMRST#_R

R42

4.99K_0402_1%

1 2 1 2

C73

0.047U_0402_16V4Z

1K_0402_5%

1 2

R41 1K_0402_5%R41 1K_0402_5%

R430_0402_5%

R430_0402_5% R440_0402_5% R440_0402_5%

DRAMRST_CNTRL_PCH 9,13,40 EC_DRAMRST_CNTRL_PCH 40

Instant ON

ER28

DDR3_DRAMRST# 10,11

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISIO N OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISIO N OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISIO N OF R&D DEPARTMENT EX CEPT AS AUTHORIZED BY CO MPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZED BY CO MPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZED BY CO MPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Size Document Number Rev Custom

Custom

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/6) DDRIII

LA-8224P

6 59Thursday, October 27, 2011

0.2

CFG Straps for Processor

D D

JCPU1E

RSVD28 RSVD29 RSVD30 RSVD31

RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD51 RSVD52

BCLK_ITP

BCLK_ITP#

AH27 AH26

L7 AG7 AE7 AK2

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AN35 AM35

AT2 AT1 AR1

KEY

CLK_RES_ITP 13 CLK_RES_ITP# 13

PEG Static Lane Reversal - CFG2 is for the 16x

Display Port Presence Strap

PCIE Port Bifurcation Straps

CFG[6:5]

CFG

RESERVED

VCC_DIE_SENSE VSS_DIE_SENSE

RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9

RSVD_NCTF10

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

CFG05

+VCC_GFXCORE_AXG

+VCC_CORE

R46

49.9_0402_1%

R48

49.9_0402_1%

C C

B B

Please place as close as JCPU1

VCC_AXG_VAL_SENSE

T38PAD @T38PAD @ T39PAD @T39PAD @ T40PAD @T40PAD @ T41PAD @T41PAD @ T42PAD @T42PAD @ T43PAD @T43PAD @ T10PAD @T10PAD @ T11PAD @T11PAD @

VCC_VAL_SENSE

CFG0 CFG2 CFG4

CFG5 CFG6

CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

CONN@

CFG2

R45

R45 1K_0402_1%

1K_0402_1%

1:(Default) Normal Operation; Lane #

CFG2

definition matches socket pin map definition 0:Lane Reversed

CFG4

R47

@R47

1K_0402_1%

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port 0 : Enabled; An external Display Port device is

connected to the Embedded Display Port

CFG6 CFG5

1K_0402_1%

R50

@R50

R49

1K_0402_1%

11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2

disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

VSS_AXG_VAL_SENSE

VSS_VAL_SENSE

R52

R51

49.9_0402_1%

A A

49.9_0402_1%

R52

49.9_0402_1%

Please place as close as JCPU1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISIO N OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISIO N OF R&D

AND TRADE SE CRET INFORMATION. THIS SHE ET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMP ETENT DIVISIO N OF R&D DEPARTMENT EX CEPT AS AUTHORIZED BY CO MPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZED BY CO MPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZED BY CO MPAL EL ECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATIO N IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PROCESSOR(4/6) RSVD,CFG

LA-8224P

7 59Thursday, October 27, 2011

0.2

D D

C C

B B

A A

JCPU1F

+VCC_CORE

97A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

TYCO_2013620-2_IVY BRIDGE

CONN@

POWER

PEG AND DDR

CORE SUPPLY

VSS_SENSE_VCCIO

SENSE LINES SVID

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

+1.05VS

8.5A

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

0.1U_0402_16V4Z

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

VR_SVID_DAT

AJ28

Place the PU resistors close to CPU

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

B10 A10

R58

R58 R59

R59

R55

VR_SVID_DAT

1 2 1 2

10_0402_1%

R62

R62 10_0402_1%

10_0402_1%

C74

1 2

43_0402_1%

130_0402_1%

R60

+1.05VS

H_CPU_SVIDCLK

Place the PU resistors close to CPU

R54

R54 75_0402_5%

75_0402_5%

R56

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

+1.05VS

0.1U_0402_16V4Z

VCCIO_SENSE 48

C75

1 2

R53 0_0402_5%R53 0_0402_5%

+VCC_CORE

R57

R57 100_0402_1%

100_0402_1%

R61

R61 100_0402_1%

100_0402_1%

VR_SVID_ALRT# 51

VCCSENSE 51 VSSSENSE 51

VR_SVID_CLK 51

VR_SVID_DAT 51

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS T HE PROPRIETA RY PROPERTY OF COMPAL ELEC TRONICS, INC. A ND CONT AINS CONFIDEN TIAL

THIS SHEET OF ENGINEERING D RAWING IS T HE PROPRIETA RY PROPERTY OF COMPAL ELEC TRONICS, INC. A ND CONT AINS CONFIDEN TIAL AND TRAD E SECRET INF ORMATION. TH IS SHEET MAY NOT BE TRANSFE RED FROM THE CUST ODY OF THE C OMPETENT D IVISION OF R&D

AND TRAD E SECRET INF ORMATION. TH IS SHEET MAY NOT BE TRANSFE RED FROM THE CUST ODY OF THE C OMPETENT D IVISION OF R&D

AND TRAD E SECRET INF ORMATION. TH IS SHEET MAY NOT BE TRANSFE RED FROM THE CUST ODY OF THE C OMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION IT CONTAI NS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEI THER THIS SHEET NOR THE INFORMATION IT CONTAI NS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR(5/6) PWR,BYPASS

Size Document Number Rev

Custom

LA-8224P

Date: Sheet of

8 59Thursday, October 27, 2011

0.2

+1.5V_CPU_VDDQ

ER19

+1.5V +1.5V_CPU_VDDQ

+5VALW+5VALW

R65

D D

R66

+VCC_GFXCORE_AXG

1U_0402_6.3V6K

C96

BSS138_SOT23

R79

1K_0402_1%

2 3

1 2

0_0402_5%

33A

1.5A

330U_D2_2VM_R6M

C97

R80

R80 1K_0402_1%

1K_0402_1%

AR24 AR23 AR21 AR20 AR18 AR17

AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17

AK24 AK23 AK21 AK20 AK18 AK17

AH24 AH23 AH21 AH20 AH18 AH17

AT24 AT23 AT21 AT20 AT18 AT17

AP24 AP23 AP21 AP20 AP18 AP17

AL24 AL23 AL21 AL20 AL18 AL17

AJ24 AJ23 AJ21 AJ20 AJ18 AJ17

B6 A6 A2

CPU1.5V_S3_GATE40

C C

B B

+1.8VS

A A

+V_DDR_REFB

DRAMRST_CNTRL_PCH

R242

1 2

0_0805_5%

+V_DDR_REFA

ER23

10U_0805_6.3VAM

C94

R77 0_0402_5%@R77 0_0402_5%@

1 2

R78 0_0402_5%@R78 0_0402_5%@

1 2

Q10

BSS138_SOT23

+1.8VS_VCCPLL

1U_0402_6.3V6K

C95

R65 100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3#

Q4A

2N7002KDWH_SOT363-6

POWER

VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54

VCCPLL1 VCCPLL2 VCCPLL3

POWER

GRAPHICS

1.8V RAIL

JCPU1G

TYCO_2013620-2_IVY BRIDGE

CONN@

DRAMRST_CNTRL_PCH 6,13,40

+V_DDR_REFA_R +V_DDR_REFB_R

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREFMISC

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

DDR3 -1.5V RAILS

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

SA RAIL

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

VCCIO_SEL

R63

36.5K_0402_1%

1 2 34

Q4B

2N7002KDWH_SOT363-6

RUN_ON_CPU1.5VS3# 42

AK35 AK34

+V_SM_VREF_CNT

AL1

+V_DDR_REFA_R

+V_DDR_REFB_R

+1.5V_CPU_VDDQ

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

VCCIO_SEL

A19

RUN_ON_CPU1.5VS3

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

Q7 AO4304L_SO8

AO4304L_SO8

8 7 6 5

C77

C77 2200P_0402_50V7K

2200P_0402_50V7K

1 2

+VCC_GFXCORE_AXG

R67

R67 100_0402_1%

100_0402_1%

R68

100_0402_1%

+1.5V_CPU_VDDQ

R70

R70 1K_0402_1%

1K_0402_1%

ER23

0.1U_0402_16V4Z

R72

C149

1K_0402_1%

RUN_ON_CPU1.5VS3

10U_0805_6.3VAM

C79

10U_0805_6.3VAM

C80

C81

10U_0805_6.3VAM

C87

C86

@ R74

R75

10K_0402_5% @

0_0402_5%

H_VCCSA_VID0 50 H_VCCSA_VID1 50

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

R64

C76

20K_0402_5%

10U_0805_10V4Z~D

Place near CPU

VCC_AXG_SENSE 51 VSS_AXG_SENSE 51

R690_0402_5% @R690_0402_5% @

PMV45EN_SOT23-3

10U_0805_6.3VAM

C84

C82

10U_0805_6.3VAM

C88

+VCCSA_SENSE 50

R74

+3VS

1 2

2011/07/12 2012/12/31

C83

10U_0603_6.3V6M

C89

2 3

330U_D2_2VM_R6M

C85

2 3

Compal Secret Data

+V_SM_VREF

330U_D2_2VM_R6M

C78

+VCCSA

Deciphered Date

+V_SM_VREF should have 10 mil trace width

+1.5V

R71

R71 1K_0402_1%

1K_0402_1%

R73

R73 1K_0402_1%@

1K_0402_1%@

JCPU1H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

TYCO_2013620-2_IVY BRIDGE

CONN@

Title

PROCESSOR(6/6) PWR,VSS

Size Document Number Rev

Custom

LA-8224P

Date: Sheet of

VSS

+1.5V_CPU_VDDQ +1.5V

C90 0.1U_0402_10V7KC90 0.1U_0402_10V7K

C91 0.1U_0402_10V7KC91 0.1U_0402_10V7K

C92 0.1U_0402_10V7KC92 0.1U_0402_10V7K

C93 0.1U_0402_10V7KC93 0.1U_0402_10V7K

Compal Electronics, Inc.

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

9 59Thursday, October 27, 2011

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

0.2

+1.5V

R81

1K_0402_1%

+V_DDR_REFA

R82

D D

C C

B B

A A

R82

1K_0402_1%

DDRA_CKE06

DDR_A_BS26

DDRA_CLK06 DDRA_CLK0#6

DDR_A_BS06 DDR_A_WE#6

DDR_A_CAS#6

DDRA_SCS1#6

+3VS

ER15

0.1U_0402_10V6K

0.1U_0402_10V6K C98

C98

2.2U_0402_6.3V6M

C99

0.1U_0402_10V6K

ER15

0.1U_0402_10V6K

2.2U_0402_6.3V6M

C118

3.56A

+1.5V +1.5V

DDR3 SO-DIMM A

DDR_A_D0 DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDRA_CLK0

DDRA_CLK0# DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDRA_ODT0 DDR_A_MA13

DDRA_SCS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

C119

R85

10K_0402_5%

R85

10K_0402_5%

R86

10K_0402_5%

R86

10K_0402_5%

JDIMM1

VREF_DQ1VSS1

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

TYCO 2-1932323-1

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5 VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

DM6

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7 VSS50

DQ62

DQ63 VSS52

EVENT#

SDA

VTT2

DQ4 DQ5

DQ6 DQ7

A15 A14

A11

CK1

BA1

S0#

SCL

DDR_A_D[0..63]6 DDR_A_DQS[0..7]6 DDR_A_DQS#[0..7]6

DDRA_CKE1 6

+VREF_CA

0.1U_0402_10V6K

DDR_A_MA[0..15]6

+1.5V

R83

R83 1K_0402_1%

1K_0402_1%

ER15

C108

2.2U_0402_6.3V6M

C109

R84

R84 1K_0402_1%

1K_0402_1%

Compal Secret Data

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

DDR_A_D4

DDR_A_D5

6 8

DDR_A_DQS#0

DDR_A_DQS0

12 14

DDR_A_D6

DDR_A_D7

18 20

DDR_A_D12

DDR_A_D13

24 26 28

DDR3_DRAMRST#

30 32

DDR_A_D14

DDR_A_D15

36 38

DDR_A_D20

DDR_A_D21

42 44 46 48

DDR_A_D22

DDR_A_D23

52 54

DDR_A_D28

DDR_A_D29

58 60

DDR_A_DQS#3

DDR_A_DQS3

64 66

DDR_A_D30

DDR_A_D31

70 72

DDRA_CKE1

74 76

DDR_A_MA15

DDR_A_MA14

80 82

DDR_A_MA11

DDR_A_MA7

DDR_A_MA6

A6 A4

A2 A0

DDR_A_MA4

92 94

DDR_A_MA2

DDR_A_MA0

98 100

DDRA_CLK1

102

DDRA_CLK1#

104 106

DDR_A_BS1

108

DDR_A_RAS#

110 112

DDRA_SCS0#

114 116 118

DDRA_ODT1

120 122 124 126 128

DDR_A_D36

130

DDR_A_D37

132 134 136 138

DDR_A_D38

140

DDR_A_D39

142 144

DDR_A_D44

146

DDR_A_D45

148 150

DDR_A_DQS#5

152

DDR_A_DQS5

154 156

DDR_A_D46

158

DDR_A_D47

160 162

DDR_A_D52

164

DDR_A_D53

166 168 170 172

DDR_A_D54

174

DDR_A_D55

176 178

DDR_A_D60

180

DDR_A_D61

182 184

DDR_A_DQS#7

186

DDR_A_DQS7

188 190

DDR_A_D62

192

DDR_A_D63

194 196 198

PCH_SMBDATA

200

PCH_SMBCLK

202 204

206

+0.75VS





DDR3_DRAMRST# 6,11

DDRA_CLK1 6 DDRA_CLK1# 6

DDR_A_BS1 6 DDR_A_RAS# 6

DDRA_SCS0# 6 DDRA_ODT0 6

DDRA_ODT1 6

PCH_SMBDATA 11,13,41 PCH_SMBCLK 11,13,41

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Layout Note:

+1.5V

330U_B2_2.5VM_R15M

C100

Place near JDDRL

10U_0603_6.3V6M

C102

C101

Title

Size Document Number Rev

Custom

Date: Sheet of

10U_0603_6.3V6M

C103

Layout Note: Place these 4 Caps near Command and Control signals of JDDRL

+1.5V

1U_0402_6.3V6K

C110

Layout Note: Place near JDDRL.203,204

+0.75VS

C114

1U_0402_6.3V6K

C114

1U_0402_6.3V6K

Compal Electronics, Inc.

LA-8224P

10U_0603_6.3V6M

C105

C104

1U_0402_6.3V6K

C111

C112

C116

1U_0402_6.3V6K

C116

1U_0402_6.3V6K

C115

1U_0402_6.3V6K

C115

1U_0402_6.3V6K

DDRIII-DDRL

10U_0603_6.3V6M

C106

C107

1U_0402_6.3V6K

C113

C117

1U_0402_6.3V6K

C117

1U_0402_6.3V6K

0.2

10 59Thursday, October 27, 2011

0.2

+1.5V

R87

1K_0402_1%

ER15

2.2U_0402_6.3V6M

1K_0402_1%

0.1U_0402_10V6K

C120

DDRB_CKE06

DDR_B_BS26

DDRB_CLK06 DDRB_CLK0#6

DDR_B_BS06 DDR_B_WE#6

DDR_B_CAS#6

DDRB_SCS1#6

+3VS

R88

C121

1K_0402_1%

ER15

2.2U_0402_6.3V6M

C141

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDRB_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDRB_CLK0

DDRB_CLK0# DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDRB_ODT0 DDR_B_MA13

DDRB_SCS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

R91

1 2

10K_0402_5%

0.1U_0402_10V6K

0.1U_0402_10V6K C142

C142

R92 10K_0402_5%R92 10K_0402_5%

+V_DDR_REFB

D D

C C

B B

A A

+1.5V +1.5V

3.56A

JDIMM2

VREF_DQ1VSS1

VSS2

DQ0

DQ1

VSS4

DM0

VSS5

DQ2

DQ3

VSS7

DQ8

DQ9

VSS9

DQS#1 DQS129RESET# VSS1131VSS12

DQ10

DQ11 VSS1337VSS14

DQ16

DQ17 VSS1543VSS16

DQS#2

DQS2

VSS18

DQ18

DQ19

VSS20

DQ24

DQ25 VSS2261DQS#3

DM3 VSS2365VSS24

DQ26

DQ27 VSS2571VSS26

CKE0

VDD1

NC1

BA2

VDD3

A12/BC#

VDD5

VDD7

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

1 2

203

VTT1

205

TYCO_2-2013287-1

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3 DQ30

DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30 VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42 VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

DQ4 DQ5

DQ6 DQ7

DM1

DM2

CK1

CK1#

BA1

NC2

DM4

DM6

SDA SCL

VTT2

DDR_B_D4

DDR_B_D5

6 8

DDR_B_DQS#0

DDR_B_DQS0

12 14

DDR_B_D6

DDR_B_D7

18 20

DDR_B_D12

DDR_B_D13

24 26 28

DDR3_DRAMRST#

30 32

DDR_B_D14

DDR_B_D15

36 38

DDR_B_D20

DDR_B_D21

42 44 46 48

DDR_B_D22

DDR_B_D23

52 54

DDR_B_D28

DDR_B_D29

58 60

DDR_B_DQS#3

DDR_B_DQS3

64 66

DDR_B_D30

DDR_B_D31

70 72

DDRB_CKE1

74 76

DDR_B_MA15

A15 A14

A11

A7 A6

A4 A2

S0#

DDR_B_MA14

80 82

DDR_B_MA11

DDR_B_MA7

86 88

DDR_B_MA6

DDR_B_MA4

92 94

DDR_B_MA2

DDR_B_MA0

98 100

DDRB_CLK1

102

DDRB_CLK1#

104 106

DDR_B_BS1

108

DDR_B_RAS#

110 112

DDRB_SCS0#

114 116 118

DDRB_ODT1

120 122 124

+VREF_CB

126 128

DDR_B_D36

130

DDR_B_D37

132 134 136 138

DDR_B_D38

140

DDR_B_D39

142 144

DDR_B_D44

146

DDR_B_D45

148 150

DDR_B_DQS#5

152

DDR_B_DQS5

154 156

DDR_B_D46

158

DDR_B_D47

160 162

DDR_B_D52

164

DDR_B_D53

166 168 170 172

DDR_B_D54

174

DDR_B_D55

176 178

DDR_B_D60

180

DDR_B_D61

182 184

DDR_B_DQS#7

186

DDR_B_DQS7

188 190

DDR_B_D62

192

DDR_B_D63

194 196 198

PCH_SMBDATA

200

PCH_SMBCLK

202 204

206





DDR3_DRAMRST# 6,10

DDRB_CKE1 6

DDRB_CLK1 6 DDRB_CLK1# 6

DDR_B_BS1 6 DDR_B_RAS# 6

DDRB_SCS0# 6 DDRB_ODT0 6

DDRB_ODT1 6

0.1U_0402_10V6K

0.1U_0402_10V6K C139

C139

PCH_SMBDATA 10,13,41 PCH_SMBCLK 10,13,41

+0.75VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_DQS#[0..7]6 DDR_B_D[0..63]6 DDR_B_DQS[0..7]6 DDR_B_MA[0..15]6

Layout Note: Place these 4 Caps near Command and Control signals of JDDRH

+1.5V

1U_0402_6.3V6K

C131

+1.5V

R89

1K_0402_1%

ER15

2.2U_0402_6.3V6M

1K_0402_1%

C140

R90

2011/07/12 2012/12/31

Layout Note: Place near JDDRH

+1.5V

330U_B2_2.5VM_R15M

10U_0603_6.3V6M

C122

C132

Compal Secret Data

Deciphered Date

1U_0402_6.3V6K

C134

C133

C132

C122

C123

C124

10U_0603_6.3V6M

C126

C125

Layout Note: Place near JDDRH.203 and 204

+0.75VS

1U_0603_10V4Z

10U_0603_6.3V6M

C127

1U_0603_10V4Z

C135

C136

Title

Size Document Number Rev

Date: Sheet of

10U_0603_6.3V6M

C128

1U_0603_10V4Z

C137

C138

Compal Electronics, Inc.

LA-8224P

10U_0603_6.3V6M

C129

10U_0603_6.3V6M

C130

DDRIII-DDRH

0.2

11 59Thursday, October 27, 2011

0.2

PCH_RTCX1

C145

C145 18P_0402_50V8J

18P_0402_50V8J

PCH_RTCX2

+RTCVCC

R94 1M_0402_5%R94 1M_0402_5%

1 2

SM_INTRUDER#

1 2

R93 10M_0402_5%R93 10M_0402_5%

1 2

32.768KHZ_12.5PF_9H03200019

C144

C144 18P_0402_50V8J

18P_0402_50V8J

D D

ER16

far away hot spot

HDA_SDO40

HDA for AUDIO

HDA_BITCLK_AUDIO33

@ C148

C C

HDA_RST_AUDIO#33

HDA_SDOUT_AUDIO33

+3V_PCH +3V_PCH+3V_PCH

R111

R116

R124

C152

C155

200_0402_5%

100_0402_1%

51_0402_5%

R127 33_0402_5%R127 33_0402_5%

R139

1 2

33_0402_5% @

R142

1 2

0_0402_5% @

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

100_0402_1%

XDP_DBRESET#_R5,14

B B

HDA_SYNC_AUDIO33 FLASH_EN 40

22P_0402_50V8J

Reserve for EMI please close to U4

A A

10P_0402_50V8J

Reserve for EMI please close to U5

+RTCVCC

R99 20K_0402_5%R99 20K_0402_5% R100 20K_0402_5%R100 20K_0402_5%

HDA_SDOUT

1 2

R101 0_0402_5%~DR101 0_0402_5%~D

1 2

R102 33_0402_5%R102 33_0402_5%

C148 10P_0402_50V8J

10P_0402_50V8J

Reserve for EMI please close to R102

1 2

R108 33_0402_5%R108 33_0402_5%

1 2

R109 33_0402_5%R109 33_0402_5%

R112

R117

XDP_DBRESET#_R

1 2

PCH_JTAG_TCK

R129

1M_0402_5%

PCH_SPI_CLK_RRR

PCH_SPI_CLK_R

R113

200_0402_5%

R118

100_0402_1%

1U_0603_10V4Z

1 2 1 2

1U_0603_10V4Z

HDA_BIT_CLK

HDA_RST# HDA_SDOUT

T49

C146

C147

PAD@

+5VS

BSS138_SOT23

BSS138_SOT23 Q11

Q11

+3V_SPI

EC_SPI_WP40

CMOS

CLRP1

SHORT PADS

CLRP2

SHORT PADS

ME CMOS

HDA_SDIN033

ER35

PAD @

PAD @ PAD @

PAD @

HDA_SYNC

R132

1 2

R134

1 2

PCH_SPI_WP PCH_WP

PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

HDA_BIT_CLK HDA_SYNC HDA_SPKR HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_SPI_WP

PCH_JTAG_TCK

T45

PCH_JTAG_TMS

T46

PCH_JTAG_TDI

T47

PCH_JTAG_TDO

T48

PCH_SPI_WP#

3.3K_0402_5%

PCH_SPI_HOLD#

3.3K_0402_5%

1 2

R137 0_0402_5%

1 2

R135 0_0402_5%R135 0_0402_5%

ER41

PCH_SPI_CLK_RR PCH_SPI_CS#_RR

PCH_SPI_SI_RR PCH_SPI_SO_RR

SPI ROM ( 4MByte )

SSM3K7002FU_SC70-3

CLRP1 & CLRP2 place near DIMM

A20 C20 D20 G22

K22 C17

N34

L34

T10

K34

E34 G34 C34

A34

A36

C36 N32

J3 H7 K5 H1

Y14

V4 U3

U3A

RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER# INTVRMEN

HDA_BCLK HDA_SYNC SPKR HDA_RST#

HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3

HDA_SDO

HDA_DOCK_EN# / GPIO33 HDA_DOCK_RST# / GPIO13

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO

SPI_CLK SPI_CS0# SPI_CS1#

SPI_MOSI SPI_MISO

PANTHER-POINT_FCBGA989

+3V_SPI

0.1U_0402_16V4Z

C150

PCH_SPI_WP# PCH_SPI_HOLD#

PCH_SPI_CS#_R PCH_SPI_CLK_R PCH_SPI_SI_R

PCH_SPI_WP#

Q63

ER35

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

RTCIHDA

SATA

JTAG

SPI

SATA0GP / GPIO21 SATA1GP / GPIO19

VCC

VSS

HOLD

W25Q32BVSSIG_SO8

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

PCH_SPI_SO_R

C38 A38 B37 C37

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME# LPC_LDRQ0#

LPC_LDRQ1# SERIRQ

SATA_COMP

SATA3_COMP

RBIAS_SATA3

PCH_SATALED# PCH_GPIO21 BBS_BIT0_R

LPC_AD0 40,41 LPC_AD1 40,41 LPC_AD2 40,41 LPC_AD3 40,41

LPC_FRAME# 40,41

T12 PAD~D

T13 PAD~D

SERIRQ 40

SATA_PRX_DTX_N0 31 SATA_PRX_DTX_P0 31 SATA_PTX_DRX_N0 31 SATA_PTX_DRX_P0 31

SATA_PRX_DTX_N2 31 SATA_PRX_DTX_P2 31 SATA_PTX_DRX_N2 31 SATA_PTX_DRX_P2 31

+3VS

Issued Date

+1.05VS_VCC_SATA

+1.05VS_SATA3

PCH_SATALED# 39

R131

1 2

0_0402_5%

EMI

+3VALW KSI439,40 KSI539,40 KSI639,40 KSI739,40

1 2

R114 37.4_0402_1%R114 37.4_0402_1%

1 2

R115 49.9_0402_1%R115 49.9_0402_1%

1 2

R120 750_0402_1%R120 750_0402_1%

PCH_SPI_CLK_RR

Security Classification

THIS SHEET OF ENGINEERING D RAWING IS T HE PROPRIETA RY PROPERTY OF COMPAL ELEC TRONICS, INC. A ND CONT AINS CONFIDEN TIAL

THIS SHEET OF ENGINEERING D RAWING IS T HE PROPRIETA RY PROPERTY OF COMPAL ELEC TRONICS, INC. A ND CONT AINS CONFIDEN TIAL AND TRAD E SECRET INF ORMATION. TH IS SHEET MAY NOT BE TRANSFE RED FROM THE CUST ODY OF THE C OMPETENT D IVISION OF R&D

AND TRAD E SECRET INF ORMATION. TH IS SHEET MAY NOT BE TRANSFE RED FROM THE CUST ODY OF THE C OMPETENT D IVISION OF R&D

AND TRAD E SECRET INF ORMATION. TH IS SHEET MAY NOT BE TRANSFE RED FROM THE CUST ODY OF THE C OMPETENT D IVISION OF R&D DEPARTMEN T EXCEPT AS A UTHORIZED BY COMPAL ELECT RONICS, INC. N EITHER THIS SH EET NOR T HE INFORMAT ION IT CONTAINS

DEPARTMEN T EXCEPT AS A UTHORIZED BY COMPAL ELECT RONICS, INC. N EITHER THIS SH EET NOR T HE INFORMAT ION IT CONTAINS

DEPARTMEN T EXCEPT AS A UTHORIZED BY COMPAL ELECT RONICS, INC. N EITHER THIS SH EET NOR T HE INFORMAT ION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COM PAL ELECTRONICS, INC.

HDD1

PCH_INTVRMEN

R106 330K_0402_5%R106 330K_0402_5%

ODD

INTVRMEN

H󶁪Integrated VRM enable

L󶁪Integrated VRM disable

+3V_PCH

PCH_SPI_CS#_RR PCH_SPI_CLK_RRR PCH_SPI_SI_RR PCH_SPI_SO_RR

KSI4 KSI5 KSI6 KSI7

2011/07/12 2012/12/31

VDD

PI3V512QE_QSOP24

Compal Secret Data

SEL

GND

Deciphered Date

FLASH_EN

PCH_SPI_CS#_R PCH_SPI_CLK

PCH_SPI_SI_R PCH_SPI_SO_R

R123

10K_0402_5%

FLASH_EN

+3V_SPI

1 2

0_0402_5%

R133

EMI

SERIRQ

+RTCVCC

R103 10K_0402_5%R103 10K_0402_5%

PCH_GPIO21

R104 10K_0402_5%R104 10K_0402_5%

PCH_SATALED#

R105 10K_0402_5%R105 10K_0402_5%

BBS_BIT0_R

R107 10K_0402_5%R107 10K_0402_5%

HDA_SPKR

R110 1K_0402_5%@R110 1K_0402_5%@

HDA_SYNC

This signal has a weak internal pull-down On Die PLL VR is supplied by

1.5V when smapled high

1.8V when sampled low Needs to be pulled High for Chief River platfrom

HDA_SYNC

R128 1K_0402_5%R128 1K_0402_5%

PCH_SPI_CLK_R

12 12 12 12

LOW=Default HIGH=No Reboot

RTC Battery

MAX. 8000mil

+RTCVCC

W=20mils

C154

0.1U_0402_16V4Z

Title

PCH (1/8) SATA,HDA,SPI, LPC

Size Document Number Rev

Custom

LA-8224P

Date: Sheet of

DAN202UT106_SC70-3

Compal Electronics, Inc.

+3V_PCH

+RTCBATT

W=20mils

+3VS

R136

R136 1K_0402_5%

1K_0402_5%

+CHGRTC

12 59Thursday, October 27, 2011

0.2

SMBALERT# SMBCLK

U3B

D D

10/100/1G LAN --->

MiniWLAN (Mini Card 1)--->

USB3.0 controller --->

C C

10/100/1G LAN --->

MiniWLAN (Mini Card 1)--->

USB3.0 controller --->

B B

R180

33_0402_5%

R1831M_0402_5% R1831M_0402_5%

GND

25MHZ_10PF_7V25000014

CLK_PCI_LPBACK

Reserve for EMI please close to U3

ER16

C163

C163 12P_0402_50V8J

12P_0402_50V8J

GND

A A

1 2

22P_0402_50V8J

C164

C164 12P_0402_50V8J

12P_0402_50V8J

PCIE_PRX_GLANTX_N132 PCIE_PRX_GLANTX_P132 PCIE_PTX_GLANRX_N132 PCIE_PTX_GLANRX_P132

PCIE_PRX_WLANTX_N241 PCIE_PRX_WLANTX_P241 PCIE_PTX_WLANRX_N241 PCIE_PTX_WLANRX_P241

PCIE_PRX_USB3TX_N436 PCIE_PRX_USB3TX_P436 PCIE_PTX_USB3RX_N436 PCIE_PTX_USB3RX_P436

C162

XTAL25_IN

XTAL25_OUT

CLK_CPU_ITP#5 CLK_CPU_ITP5

CLK_RES_ITP#7 CLK_RES_ITP7

CLK_PCH_14M

CLK_PCIE_LAN#32 CLK_PCIE_LAN32

LANCLK_REQ#32

CLK_PCIE_WLAN#41 CLK_PCIE_WLAN41

WLANCLK_REQ#41

CLK_PCIE_USB30#36 CLK_PCIE_USB3036

CLKREQ_USB30#36

CLK_CPU_ITP# CLK_CPU_ITP

R189

33_0402_5%

C158 0.1U_0402_10V7KC158 0.1U_0402_10V7K

1 2

C159 0.1U_0402_10V7KC159 0.1U_0402_10V7K

1 2

C160 0.1U_0402_10V7KC160 0.1U_0402_10V7K

1 2

C161 0.1U_0402_10V7KC161 0.1U_0402_10V7K

1 2

C1043 0.1U_0402_10V7K

1 2

C1044 0.1U_0402_10V7K

1 2

R167 0_0402_5%R167 0_0402_5% R168 0_0402_5%R168 0_0402_5%

+3V_PCH

R169 10K_0402_5%R169 10K_0402_5%

R170 0_0402_5%R170 0_0402_5% R171 0_0402_5%R171 0_0402_5% R172 10K_0402_5%R172 10K_0402_5%

+3VS

R175 10K_0402_5%R175 10K_0402_5%

+3VS

R1054 0_0402_5%USB30@R1054 0_0402_5%USB30@ R1055 0_0402_5%USB30@R1055 0_0402_5%USB30@

R176 10K_0402_5%R176 10K_0402_5%

R177 10K_0402_5%R177 10K_0402_5%

R178 10K_0402_5%R178 10K_0402_5%

R179 10K_0402_5%R179 10K_0402_5%

R182 10K_0402_5%R182 10K_0402_5%

R184 10K_0402_5%R184 10K_0402_5%

R185 0_0402_5%XDP@R185 0_0402_5%XDP@ R186 0_0402_5%

R186 0_0402_5%

R187 0_0402_5%@R187 0_0402_5%@ R188 0_0402_5%@R188 0_0402_5%@

C165

1 2

22P_0402_50V8J

USB30@

XDP@

1 2 1 2

1 2

12 12 12

12 12

PCIE_PRX_GLANTX_N1 PCIE_PRX_GLANTX_P1 PCIE_PTX_GLANRX_N1_C PCIE_PTX_GLANRX_P1_C

PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2_C PCIE_PTX_WLANRX_P2_C

PCIE_PRX_USB3TX_N4 PCIE_PRX_USB3TX_P4 PCIE_PTX_USB3RX_N4_C PCIE_PTX_USB3RX_P4_C

PCIE_LAN# PCIE_LAN

LANCLK_REQ#

PCIE_WLAN# PCIE_WLAN

WLANCLK_REQ#

PCIE_USB30# PCIE_USB30

PEG_B_CLKREQ#

PCIE_CLKREQ6#

GPIO46

CLK_BCLK_ITP# CLK_BCLK_ITP

CLK_BCLK_ITP

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

SMBALERT#

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKIN_DMI_N CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

Issued Date

E12

SMBCLK

H14

SMBDATA

DRAMRST_CNTRL_PCH

A12

SML0CLK

SML0DATA

G12

PCH_HOT#

C13

PCH_SMLCLK

E14

PCH_SMLDATA

M16

T11

P10

PEG_CLKREQ#_R

M10

CLK_PCIE_VGA#

AB37

CLK_PCIE_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12 AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

CLK_SD_48M_R

K43 F47 H47 K49

MEMORY

DRAMRST_CNTRL_PCH 6,9,40

ER03

T14 PAD@ T14 PAD@

T15 PAD@ T15 PAD@

T16 PAD@ T16 PAD@

PEG_CLKREQ#_R 20

CLK_PCIE_VGA# 20 CLK_PCIE_VGA 20

CLK_CPU_DMI# 5 CLK_CPU_DMI 5

CLK_PCI_LPBACK 15

1 2

R181 90.9_0402_1%R181 90.9_0402_1%

CLK_SD_48M

R277 0_0402_5%R277 0_0402_5%

Compal Secret Data

2011/07/12 2012/12/31

Compal Secret Data

+1.05VS_VCCDIFFCLKN

T17 PAD@ T17 PAD@ T18 PAD@ T18 PAD@ T19 PAD@ T19 PAD@

Deciphered Date

VGA

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

CLKIN_PCILOOPBACK

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SMBCLK

SMBDATA

CLK_SD_48M 34

ER03

6 1

2N7002DW-T/R7_SOT363-6

Q2A

2N7002DW-T/R7_SOT363-6

PCH_SMLCLK

PCH_SMLDATA

SMBDATA SML0CLK SML0DATA PCH_SMLCLK PCH_SMLDATA

PCH_HOT#

DRAMRST_CNTRL_PCH

ER17

CLKIN_DMI2# CLKIN_DMI2 CLKIN_DMI# CLKIN_DMI CLKIN_DOT96# CLKIN_DOT96 CLKIN_SATA# CLKIN_SATA CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen else, please pl ace close to P CH

+3VS+3VS

R173

2.2K_0402_5%

Q2B

1 2

ER03

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

LA-8224P

R149 10K_0402_5%R149 10K_0402_5%

1 2

R150 2.2K_0402_5%R150 2.2K_0402_5%

1 2

R151 2.2K_0402_5%R151 2.2K_0402_5%

1 2

R152 2.2K_0402_5%R152 2.2K_0402_5%

1 2

R153 2.2K_0402_5%R153 2.2K_0402_5%

1 2

R154 2.2K_0402_5%R154 2.2K_0402_5%

1 2

R155 2.2K_0402_5%R155 2.2K_0402_5%

1 2

R156 10K_0402_5%R156 10K_0402_5%

1 2

R157 1K_0402_1%R157 1K_0402_1%

1 2

R750 100K_0402_5%

R158 10K_0402_5%R158 10K_0402_5%

1 2

R159 10K_0402_5%R159 10K_0402_5%

1 2

R160 10K_0402_5%R160 10K_0402_5%

1 2

R161 10K_0402_5%R161 10K_0402_5%

1 2

R162 10K_0402_5%R162 10K_0402_5%

1 2

R163 10K_0402_5%R163 10K_0402_5%

1 2

R164 10K_0402_5%R164 10K_0402_5%

1 2

R165 10K_0402_5%R165 10K_0402_5%

1 2

R166 10K_0402_5%R166 10K_0402_5%

1 2

R174

2.2K_0402_5%

1 2

PCH_SMBCLK 10,11,41

PCH_SMBDATA 10,11,41

PCH_SMLCLK 20,40

PCH_SMLDATA 20,40

13 59Thursday, October 27, 2011

+3V_PCH

0.2

U3C

DMI_CTX_PRX_N04 DMI_CTX_PRX_N14 DMI_CTX_PRX_N24 DMI_CTX_PRX_N34

DMI_CTX_PRX_P04 DMI_CTX_PRX_P14

XDP_DBRESET#_R5,12

SYSTEM_PWROK

PBTN_OUT#5,40

ACIN40,44

1 2

C166 100P_0402_50V8J

DMI_CTX_PRX_P24 DMI_CTX_PRX_P34

DMI_CRX_PTX_N04 DMI_CRX_PTX_N14 DMI_CRX_PTX_N24 DMI_CRX_PTX_N34

DMI_CRX_PTX_P04 DMI_CRX_PTX_P14 DMI_CRX_PTX_P24 DMI_CRX_PTX_P34

+1.05VS_VCC_EXP

R192 49.9_0402_1%R192 49.9_0402_1% R193 750_0402_1%R193 750_0402_1%

4mil width and place within 500mil of the PCH

R802

1 2

R196 0_0402_5%R196 0_0402_5%

1 2

R197 0_0402_5%R197 0_0402_5%

PM_DRAM_PWRGD

R200

1 2

R801

1 2

RB751V-40_SOD323-2

1 2

R751 0_0402_5%R751 0_0402_5%

XDP_DBRESET#_R

D D

SUSACK#40

C C

Reserve

ER26

PCH_PWROK40

PM_DRAM_PWRGD5

PCH_RSMRST#40

SUSWARN#40

AC_PRESENT40

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

1 2

@R802

0_0402_5%

@R801

0_0402_5%

R203 0_0402_5%R203 0_0402_5%

ER21

SUSACK#_R

XDP_DBRESET#_R

SYSTEM_PWROK_I

PM_PWROK_R

1 2

R198 0_0402_5%R198 0_0402_5%

PCH_RSMRST#_R

0_0402_5%

SUSWARN#_R

1 2

@D2

AC_PRESENT_R

DMI_IRCOMP RBIAS_CPY

PBTN_OUT#_R

PCH_GPIO72

RI#

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

DMI

FDI

DMI

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

System Power Management

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

PCH_DPWROK_R

E22

WAKE#

N14

D10

G10

G16

AP14

K14

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWODVREN

1 2

PM_CLKRUN#

0_0402_5% @

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

H_PM_SYNC

PCH_GPIO29

R800 0_0402_5%@R800 0_0402_5%@

R195

1 2

R199

1 2

R194 0_0402_5%R194 0_0402_5%

1 2

0_0402_5%

R529

T22 PADT22 PAD

0_0402_5%

T23 PADT23 PAD

T24 PADT24 PAD

T25 PADT25 PAD

FDI_CTX_PRX_N0 4 FDI_CTX_PRX_N1 4 FDI_CTX_PRX_N2 4 FDI_CTX_PRX_N3 4 FDI_CTX_PRX_N4 4 FDI_CTX_PRX_N5 4 FDI_CTX_PRX_N6 4 FDI_CTX_PRX_N7 4

FDI_CTX_PRX_P0 4 FDI_CTX_PRX_P1 4 FDI_CTX_PRX_P2 4 FDI_CTX_PRX_P3 4 FDI_CTX_PRX_P4 4 FDI_CTX_PRX_P5 4 FDI_CTX_PRX_P6 4 FDI_CTX_PRX_P7 4

FDI_INT 4 FDI_FSYNC0 4 FDI_FSYNC1 4 FDI_LSYNC0 4 FDI_LSYNC1 4

PCIE_WAKE# 32,36,41

PM_CLKRUNEC# 40

SUSCLK_R 40

PM_SLP_S5# 40

PM_SLP_S4# 40

PM_SLP_S3# 40

H_PM_SYNC 5

ER26ER26

PCH_DPWROK PCH_RSMRST#_R

PCH_DPWROK 40

PCH_CRT_HSYNC30 PCH_CRT_VSYNC30

PCH_ENBKL40

PCH_ENVDD30

PCH_INV_PWM30

PCH_LCD_CLK30 PCH_LCD_DATA30

PCH_TXCLK-30 PCH_TXCLK+30

PCH_TXOUT0-30 PCH_TXOUT1-30 PCH_TXOUT2-30

PCH_TXOUT0+30 PCH_TXOUT1+30 PCH_TXOUT2+30

PCH_CRT_BLU30 PCH_CRT_GRN30 PCH_CRT_RED30

PCH_CRT_DDC_CLK30 PCH_CRT_DDC_DAT30

PCH_ENBKL

R190

1 2

100K_0402_5%

CTRL_CLK CTRL_DATA

LVDS_IBG

T20

T20 PAD

PAD

1 2 1 2

1K_0402_0.5%

PCH_TXCLKPCH_TXCLK+

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+

PCH_CRT_BLU PCH_CRT_GRN PCH_CRT_RED

PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT

HSYNC_PCH VSYNC_PCH

CRT_IREF

R204

R191 2.37K_0402_1%R191 2.37K_0402_1%

R201 33_0402_5%R201 33_0402_5%

R202 33_0402_5%R202 33_0402_5%

U3D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N

DDPB_0P

DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

HDMICLK_NB

P38

HDMIDAT_NB

M39

AT49 AT47

TMDS_B_HPD

AT40

TMDS_B_DATA2#

AV42

TMDS_B_DATA2

AV40

TMDS_B_DATA1#

AV45

TMDS_B_DATA1

AV46

TMDS_B_DATA0#

AU48

TMDS_B_DATA0

AU47

TMDS_B_CLK#

AV47

TMDS_B_CLK

AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

HDMICLK_NB 35 HDMIDAT_NB 35

TMDS_B_HPD 35 TMDS_B_DATA2# 35

TMDS_B_DATA2 35 TMDS_B_DATA1# 35 TMDS_B_DATA1 35 TMDS_B_DATA0# 35 TMDS_B_DATA0 35 TMDS_B_CLK# 35 TMDS_B_CLK 35

B B

A A

Reserve for EMI please close to U3

VGATE5,51

PM_PWROK_R SYSTEM_PWROK_I

1 2

R210 0_0402_5%R210 0_0402_5%

R226 100K_0402_5%@R226 100K_0402_5%@ R227 100K_0402_5%@R227 100K_0402_5%@

ER23

+3VS

PCH_GPIO29

PCH_GPIO72 RI# WAKE# AC_PRESENT_R SUSWARN#

PCH_DPWROK PCH_RSMRST#

12 12

SYSTEM_PWROK

NC7SZ08P5X_NL_SC70-5

R230 10K_0402_5%R230 10K_0402_5%

1 2

R217 10K_0402_5%R217 10K_0402_5%

1 2

R219 10K_0402_5%R219 10K_0402_5%

1 2

R221 10K_0402_5%R221 10K_0402_5%

1 2

R222 200K_0402_5%R222 200K_0402_5%

1 2

R223 10K_0402_5%R223 10K_0402_5%

1 2

R803 100K_0402_5%@R803 100K_0402_5%@ R225 10K_0402_5%R225 10K_0402_5%

1 2

Intel CRB EMRLDLKE2 Rev1.0

ER26

SYSTEM_PWROK 5

+3V_PCH

DSWODVREN DSWODVREN

R213 330K_0402_5%R213 330K_0402_5% R214 330K_0402_5%@R214 330K_0402_5%@

DSWODVREN - On Die DSW VR Enable

H󶁪Enable

L󶁪Disable

+3VS

@ R224

PM_CLKRUN#

12 12

R130

R130 10K_0402_5%

10K_0402_5%

1 2

R224

8.2K_0402_5%

+RTCVCC

+3VS

1 2

R206 2.2K_0402_5%R206 2.2K_0402_5%

1 2

R207 2.2K_0402_5%R207 2.2K_0402_5%

1 2

R208 2.2K_0402_5%R208 2.2K_0402_5%

1 2

R209 2.2K_0402_5%R209 2.2K_0402_5%

1 2

R215 150_0402_1%~DR215 150_0402_1%~D

1 2

R216 150_0402_1%~DR216 150_0402_1%~D

1 2

R218 150_0402_1%~DR218 150_0402_1%~D

1 2

R220 100K_0402_5%~D@R220 100K_0402_5%~D@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCH_CRT_DDC_CLK PCH_CRT_DDC_DAT

CTRL_CLK CTRL_DATA

PCH_CRT_BLU PCH_CRT_GRN PCH_CRT_RED PCH_ENVDD

Compal Secret Data

2011/07/12 2012/12/31

Compal Secret Data

ER01

Del R205

Deciphered Date

+3VS

R211 2.2K_0402_5%R211 2.2K_0402_5%

1 2

R212 2.2K_0402_5%R212 2.2K_0402_5%

1 2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-8224P

PCH_LCD_CLK PCH_LCD_DATAPCH_PWROK

14 59Thursday, October 27, 2011

0.2

D D

USB3_RX1_N37 USB3_RX2_N37

USB3_RX1_P37 USB3_RX2_P37

USB3_TX1_N37 USB3_TX2_N37

USB3_TX1_P37

PCH_WAN_RADIO_OFF#41

CLK_PCI_LPBACK CLK_PCI_LPC CLK_LPC_DEBUG1

USB3_TX2_P37

DGPU_PWR_EN20,29,54

ODD_DA#31

T26PAD @T26PAD @

R232 22_0402_5%R232 22_0402_5% R233 22_0402_5%R233 22_0402_5%

1 2

R234 22_0402_5%R234 22_0402_5%

1 2

R7848.2K_0402_5% R7848.2K_0402_5%

1 2

R7858.2K_0402_5% R7858.2K_0402_5%

1 2

R7868.2K_0402_5% R7868.2K_0402_5%

1 2

R7878.2K_0402_5% R7878.2K_0402_5%

1 2

R7888.2K_0402_5% R7888.2K_0402_5%

1 2

R7898.2K_0402_5% R7898.2K_0402_5%

1 2

R7908.2K_0402_5% R7908.2K_0402_5%

1 2

R7918.2K_0402_5% R7918.2K_0402_5%

1 2

R7928.2K_0402_5% R7928.2K_0402_5%

1 2

R7938.2K_0402_5% R7938.2K_0402_5%

1 2

ER23

R244 10K_0402_5%R244 10K_0402_5%

1 2

R288 10K_0402_5%

1 2

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST#

PCH_GPIO52

DGPU_PWR_EN

PCH_WAN_RADIO_OFF#

PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5

PCH_PLTRST#

+3VS

CLK_PCI0 CLK_PCI1 CLK_PCI3

C C

C167

1 2

0.1U_0402_16V4Z~D

ODD_DA#

Reserve for EMI please close to U3

B B

CLK_PCI_LPBACK13

CLK_PCI_LPC40

CLK_LPC_DEBUG141

ER14

PCH_GPIO4 PCI_PIRQB# PCI_PIRQD# PCI_PIRQC#

PCH_WAN_RADIO_OFF#

PCI_PIRQA# ODD_DA# PCH_GPIO5

PCH_GPIO52

A A

PCH_GPIO2

DGPU_HOLD_RST#

DGPU_PWR_EN

U3E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

RSVD

PCI

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22 RSVD23

RSVD24 RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P

USB

USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

+3VS

R238

10K_0402_5%

PLT_RST#5,32,36,40,41

AV5 AV10

AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

1 2

R243

R243 100K_0402_5%

100K_0402_5%

NV_ALE

USB20_N0 USB20_P0 USB20_N1 USB20_P1

USB20_N4 USB20_P4

HM76 not Support USB Port6,7

USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10

USBRBIAS

USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

R235 0_0402_5%

Within 500 mils

R231 22.6_0402_1%R231 22.6_0402_1%

1 2

+3VS

OUT

USB20_N0 37 USB20_P0 37 USB20_N1 37 USB20_P1 37

USB20_N4 41 USB20_P4 41

USB20_N8 30 USB20_P8 30 USB20_N9 33 USB20_P9 33 USB20_N10 34 USB20_P10 34

1 2

C168

1 2

IN1

VCC

IN2

GND

MC74VHC1G08DFT2G_SC70-5

Panther Point USB Port Mapping

USB 2.0 Port Number

USB 2.0 Port Number USB 3.0 Port Number

USB 2.0 Port NumberUSB 2.0 Port Number

USB 3.0 Port Number

USB 3.0 Port NumberUSB 3.0 Port Number

0000 1111

1111

2222

3333

2222

3333

4444

USB2/3 port 1 USB2/3 port 2

Mini Card(WLAN)

Bluetooth

Camera USB2 Conn. R Card Reader

USB_OC0# 37

USB_OC4# 37

0.1U_0402_16V4Z~D

PCH_PLTRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

(For USB Port0, 1)

(For USB Port9)

2011/07/12 2012/12/31

USB_OC0# USB_OC2# USB_OC7# USB_OC5#

USB_OC6# USB_OC4# USB_OC3# USB_OC1#

DGPU_RST#20

Compal Secret Data

ER14

Deciphered Date

GPIO19 => BBS_BIT0 GPIO51 => BBS_BIT1

Boot BIOS Strap

BBS_BIT1BBS_BIT0

0 0 1

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

1 2 1 2 1 2 1 2

DIS@

R240

100_0402_5%

R241

100K_0402_5%

DIS@

R228 1K_0402_5%@R228 1K_0402_5%@

0 1 0 11

R77610K_0402_5% R77610K_0402_5% R77710K_0402_5% R77710K_0402_5% R77810K_0402_5% R77810K_0402_5% R77910K_0402_5% R77910K_0402_5%

R78010K_0402_5% R78010K_0402_5% R78110K_0402_5% R78110K_0402_5% R78210K_0402_5% R78210K_0402_5% R78310K_0402_5% R78310K_0402_5%

1 2

Boot BIOS Location

LPC Reserved(NAND) Reserved SPI

+3V_PCH

1 2

R236 0_0402_5%

+3VS

C169

NC7SZ08P5X_NL_SC70-5DIS@U9NC7SZ08P5X_NL_SC70-5DIS@

+1.8VS

Over Current Pin Default Usage

OC Pin

OC Pin PCH Mapping

PCH Mapping

OC PinOC Pin

PCH MappingPCH Mapping

Port 0 & 1

Port 0 & 1Port 0 & 1

0000

Port 2 & 3

Port 2 & 3Port 2 & 3

1111

Port 4 & 5

Port 4 & 5Port 4 & 5

2222

Port 6 & 7

Port 6 & 7Port 6 & 7

3333

Port 8 & 9

Port 8 & 9Port 8 & 9

4444

Port 10 & 11

Port 10 & 11Port 10 & 11

5555

Port 12 & 13

Port 12 & 13Port 12 & 13

6666

DIS@C169

DIS@

1 2

0.1U_0402_16V4Z~D

PCH_PLTRST#

DGPU_HOLD_RST#

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

LA-8224P

0.2

15 59Thursday, October 27, 2011

0.2

+3VS

CRT_DET ODD_DETECT# PCH_GPIO16 PCH_BT_ON

D D

C C

B B

KB_RST# PCH_GPIO48 PCH_GPIO22 ODD_EN# DGPU_PWROK

+3VS

R264

+3VALW

R266 10K_0402_5%@ R266 10K_0402_5%@

PCH_GPIO28

HDD2_DETECT#

PCH_LID_SW_IN# EC_SMI#

1 2

1 2 1 2

R80710K_0402_5% R80710K_0402_5%

R25710K_0402_5% R25710K_0402_5% R25910K_0402_5%@R25910K_0402_5%

R26010K_0402_5% R26010K_0402_5%

R26110K_0402_5% R26110K_0402_5% R26210K_0402_5% R26210K_0402_5%

R26310K_0402_5% R26310K_0402_5%

100K_0402_5%

ER26

R80510K_0402_5%@R80510K_0402_5%

R268

R269

R270

R270 R271

R271

PCH_GPIO27

1 2

R245

1 2

R246

1 2

R247

1 2

R248

1 2

R249

1 2

R250

1 2

R252

1 2

R253

1 2

R255

ER25

10K_0402_5%

1K_0402_5%

1K_0402_5% 10K_0402_5%

10K_0402_5%

10K_0402_5%@

10K_0402_5%@ 200K_0402_5%

200K_0402_5% 10K_0402_5%

10K_0402_5% 10K_0402_5%

10K_0402_5%

PCH_GPIO69

PCH_GPIO1 PCH_GPIO37 PCH_GPIO38 PCH_GPIO39 PCH_GPIO49 USB30_SMI#

PCH_GPIO37

DS_WAKE#

+3V_PCH

GPIO28

On-Die PLL Voltage Regulator This signal has a weak internal pull up

H󶁪On-Die voltage regulator enable

L󶁪On-Die PLL Voltage Regulator disable

ER26

CABC_SAVING30

1 2

R272 1K_0402_5%@ R272 1K_0402_5%@

USB30_SMI#36

EC_LID_OUT#40

DS_WAKE#40

PCH_GPIO28

DS_WAKE#

EC_SCI#40 EC_SMI#40

DGPU_PWROK40

PCH_BT_ON41

ODD_DETECT#31

R265 0_0402_5%

USB30_SMI#

1 2

R804 0_0402_5%

CRT_DET PCH_GPIO1

EC_SCI# EC_SMI#

PCH_LID_SW_IN#EC_LID_OUT#

R4980_0402_5% R4980_0402_5%

PCH_GPIO16

DGPU_PWROK PCH_GPIO22

PCH_GPIO27 PCH_GPIO28 PCH_BT_ON

ODD_DETECT# PCH_GPIO37 PCH_GPIO38 PCH_GPIO39 PCH_GPIO48 PCH_GPIO49 HDD2_DETECT#

U3F

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

LAN_PHY_PWR_CTRL / GPIO12

GPIO15

SATA4GP / GPIO16

D40

TACH0 / GPIO17

SCLOCK / GPIO22

GPIO24

E16

GPIO27

GPIO28

STP_PCI# / GPIO34

GPIO35

SATA2GP / GPIO36

SATA3GP / GPIO37

SLOAD / GPIO38

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

SATA5GP / GPIO49 / TEMP_ALERT#

GPIO57

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989

GPIO

NCTF

TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

ODD_EN# PCH_GPIO69 GPIO70 GPIO71

H_THERMTRIP#_C

DF_TVS

T30 PAD@T30 PAD@

ER25

T28 PAD@T28 PAD@ T29 PAD@T29 PAD@

GATEA20

KB_RST# 40 H_CPUPWRGD 5

1 2

ODD_EN# 31

+3VS

R251

R251 10K_0402_5%

10K_0402_5%

1 2

GATEA20 40

H_THERMTRIP#

R258390_0402_5% R258390_0402_5%

1 2

C170 100P_0402_50V8J

Reserve for EMI please close to U3

H_CPUPWRGD

H_THERMTRIP# 5

DMI Termination Voltage

Set to Vcc when HIGH

DF_TVS

Set to Vss when LOW

R254

2.2K_0402_5%

DF_TVS

2.2K_0402_5%

R2561K_0402_5% R2561K_0402_5%

CLOSE TO THE BRANCHING POINT

+1.8VS

H_SNB_IVB# 5

+3VS

R273

High: CRT Plugged

A A

CRT_DET

CRT_DET#30

R273 10K_0402_5%

10K_0402_5%

1 2 13

Q12

2N7002_SOT23-3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

LA-8224P

16 59Thursday, October 27, 2011

0.2

+1.05VS

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

+1.05VS

+1.05VS_VCC_EXP

C187

C186

1U_0402_6.3V6K

+1.05VS

+VCCP_VCCDMI

C176

C177

1U_0402_6.3V6K

C188

1U_0402_6.3V6K

+1.5VS

C174

+3VS

C174

+1.05VS_VCC_EXP

C185

C190

0.1U_0402_10V7K

10U_0805_6.3V6M

D D

R274

0_0805_5%

C C

B B

0_0805_5%

10U_0805_6.3V6M

+1.05VS

R275

R275 0_0805_5%

0_0805_5%

C184

10U_0805_6.3V6M

U3G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER-POINT_FCBGA989

1300mA

POWER

3709mA

CRTLVDS

VCC CORE

40mA

75mA

DMI

VCCIO

2mA

DFT / SPI HVCMOS

FDI

1mA

VCCADAC

VSSADAC

1mA

VCCALVDS VSSALVDS

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

10mA

VCCSPI

+VCCADAC

U48

U47

AK36 AK37

AM37 AM38 AP36 AP37

V33

V34

AT16

+VCCP_VCCDMI

AT20

+1.05VS_VCC_DMI_CCI

AB36

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

C171

+VCCTX_LVDS

C178

0.01U_0402_16V7K

C182

0.1U_0402_10V7K

C191

C193

C193 1U_0402_6.3V6K

1U_0402_6.3V6K

0.01U_0402_16V7K

+1.5VS

0.1U_0402_10V7K

C172

Near AP43

C189

C189 1U_0402_6.3V6K

1U_0402_6.3V6K

+1.8VS

0.1U_0402_10V7K

+VCCP_VCCDMI

BLM18PG181SN1_0603

C173

C173 10U_0805_6.3V6M

10U_0805_6.3V6M

C180

22U_0805_6.3V6M

R387

1 2

0_0805_5%

22U_0805_6.3V6M

+1.05VS

ER23

C179

0.01U_0402_16V7K

+3VS

R278 0_0603_5%

R279 0_0603_5%R279 0_0603_5%

+3V_PCH

+3VS

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

R276

1 2

0_0805_5%

C183

1U_0402_6.3V6K

+1.8VS

+1.05VS

PCH Power Rail Table Refer to CPU EDS R1.5

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

1.05

S0 Iccmax Current (A)

0.001

0.228

0.001

0.075

1.3

0.042

1.05VccIO 3.709

1.05VccASW 0.903

3.3VccSPI 0.01

3.3VccDSW 0.001

1.8 0.002VccDFTERM

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.065

0.01

VccVRM 1.8 / 1.5 0.167

1.05VccCLKDMI

0.075

VccSSC 1.05 0.095

ccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.04

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/07/12 2012/12/31

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCH (6/8) PWR

LA-8224P

0.2

17 59Thursday, October 27, 2011

+1.05VS

+3V_PCH

1 2

R281 0_0603_5%R281 0_0603_5%

ER10

+1.05VS

+3VALW

+3VS

+1.05VS

1 2

R290 0_0603_5%

ER23

R289

1 2

0_0805_5%

+1.05VM_VCCSUS

C218

C218 1U_0402_6.3V6K

1U_0402_6.3V6K

R287 0_0603_5%R287 0_0603_5%

+1.05VS

10UH_LBR2012T100M_20%~D

1 2

10UH_LBR2012T100M_20%~D

+1.05VS

C222

C222 1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K

D D

C C

+1.05VS

R285 0_0603_5%

B B

+1.05VS

A A

+1.05VS

C194

0.1U_0402_10V7K

+1.05VS

22U_0805_6.3V6M

+3VS_VCC_CLKF33

C213

C212

1U_0402_6.3V6K

10U_0805_10V4Z

+1.05VS_VCCDIFFCLKN

C220

C220 1U_0402_6.3V6K

1U_0402_6.3V6K

C225

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

C232

C234

220U_B2_2.5VM_R35M

+1.05VS_VCCDIFFCLKN

1U_0402_6.3V6K

0.1U_0402_10V7K

C203

C223

0.1U_0402_10V7K

C233

R280 0_0603_5%

C196

@C196

C206

1U_0402_6.3V6K~D

C217

0.1U_0402_10V7K

C227

C226

0.1U_0402_10V7K

C235

1U_0402_6.3V6K

220U_B2_2.5VM_R35M

C204

C204 22U_0805_6.3V6M

22U_0805_6.3V6M

C207

1U_0402_6.3V6K~D

+VCCRTCEXT

18mil 18mil

C224

C224 1U_0402_6.3V6K

1U_0402_6.3V6K

+RTCVCC

+VCCACLK

+VCCPDSW

+PCH_VCCDSW

+3VS_VCC_CLKF33

+VCCSUS1

C200

C200 1U_0402_6.3V6K

1U_0402_6.3V6K

C208

1U_0402_6.3V6K~D

+1.5VS

+1.05VS_VCCA_A_DPL +1.05VS_VCCA_B_DPL

+VCCSST

+1.05VM_VCCSUS

C229

C228

0.1U_0402_10V7K

POWER

U3J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

0.1U_0402_10V7K

VCCRTC

PANTHER-POINT_FCBGA989

C230

1U_0402_6.3V6K

POWER

N26

VCCIO[29]

P26

1mA

PCI/GPIO/LPCMISC

SATA USB

10mA

HDA

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

1mA

VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5]

VCC3_3[1] VCC3_3[8] VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12] VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2] VCCIO[3] VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

P28 T27 T29

T23 T24 V23 V24 P24

T26

M26

AN23 AN24

P34

N20 N22 P20 P22

AA16 W16 T34

AJ2

AF13

AH13 AH14

AF14 AK1

AF11

AC16 AC17 AD17

T21

V21

T19

P32

2011/07/12 2012/12/31

3mA

119mA

903mA

Clock and Miscellaneous

75mA 75mA

55mA

95mA

1mA

CPURTC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C195

C195 1U_0402_6.3V6K

1U_0402_6.3V6K

C198

+PCH_V5REF_SUS

+VCCA_USBSUS

+PCH_V5REF_RUN

C209

C209 1U_0402_6.3V

1U_0402_6.3V

+1.05VS_VCC_SATA

+VCCSUSHDA

C231

0.1U_0402_10V7K

Compal Secret Data

0.1U_0402_10V7K

C215

0.1U_0402_10V7K

+1.5VS

+1.05VS_VCC_SATA

C199

0.1U_0402_10V7K

+3VS

+1.05VS_SATA3

R292

150_0402_1%

Deciphered Date

0.1U_0402_10V7K

+1.05VS

+3V_PCH +3V_PCH

+3V_PCH

C205

+3V_PCH

+3VS

C211

0.1U_0402_10V7K

C214

0.1U_0402_10V7K

+1.05VS_SATA3

R286

0_0805_5%

C221

1U_0402_6.3V6K

1 2

R291 0_0402_5%R291 0_0402_5%

+1.05VS

+3VS

C216

C216 1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05VS

R284

0_0805_5%

+VCCA_USBSUS

+1.05VS

+3V_PCH

+3V_PCH+5V_PCH

1 2

D3 RB751V40_SC76-2

RB751V40_SC76-2

1 2

+PCH_V5REF_SUS

C202

0.1U_0603_25V7K

+3VS+5VS

D4 RB751V40_SC76-2

RB751V40_SC76-2

1 2

+PCH_V5REF_RUN

C210

C210 1U_0603_10V6K

1U_0603_10V6K

18 59Thursday, October 27, 2011

R282

10_0402_5%

If it support 3.3V audio signals POP:RH12 (0ohm)

If it support 1.5V audio signals POP:RH12 (180 ohm)/RH13 (150 ohm)

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

10_0402_5%

C201

@ C201

1U_0402_6.3V6K

R283

10_0402_5%

Compal Electronics, Inc.

PCH (7/8) PWR

LA-8224P

0.2

+ 42 hidden pages

ASUS A45VD Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual