© ASML 2016
Confidential
Page 1 of 118
Modified date:
Status:
Info type:
2016-12-22
UCC
GID
Document name:
D000118344-10-GID-001
Program/Machine type:
Project/Group:
All
e-prs
Title:
GID PCBA Technology Design rules
Summary:
Confidential
This document describes the PCBA design rules for the development of PCBA’s within the ASML PCBA
design process. The PCBA design rules, which are mentioned in this document, are standard design
rules and are intended to cover approximately 90% of the PCBA’s within the ASML machines. The other
10% of the PCBA’s will be designed with deviations of those PCBA design rules.
This document is applicable for ASML employees responsible for a new, or to be modified PCBA, and
Subcontractors (co-developers) who design a new or modified PCBA for ASML as defined in the
Statement of Work (Sow) for that development.
This GID is a so-called "living document" and shall be updated in an unscheduled time frame. Please
check TCE for the latest version. In case of an update, all people and/or roles mentioned on the
reviewers list of this document, will be involved in the review process.
For change control
Reviewers
For info
Paul van der Heijde GL EDEV-EDS
Dimitri Filaktakis CL PCB Technology
Jeroen Frank Dekkers CL PCBA Design
Hans Maranus CL EME
Frank van Dijk CL EL
Eugene Brinkhof PCB Expert
Jan Bex PCB Expert
John Damen PCB Expert
Rob van Vliet EDEV Quality
Jan Gabriels EDEV SCE
Nico Gotink EDEV SCE
Willem Sloof EDEV SCE
Jeroen Looijen MDEV
George Fortier CL PCB Wilton
Leon Bongers EDEV-SE
Marc Gruijters EDEV-SE
Marco Reinierkens EDEV-SE
Jos Van Grotel PCB-Layouter
Jan Vanuytven PCB-Layouter
Cor Coolen PCB-Layouter
Wim de Keyser PCB-Layouter
David Womack CL PCBA SD
Wilbur van den Boogaard Neways NT
Antwan Langeveld Neways NAA
Ruud van Beek GL EDEV-SCE
Steven Vis CE
Maintainer : Botterweck, Marc (mbotterw)
Keywords:
PCB PCBA Design rules DFx
Pages incl. cover : 118
Word processor : MS Word 2010
© ASML 2016. All rights reserved.
Reproduction in whole or in part is prohibited without the prior written consent of ASML.
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 2 of 118
1
Name author
Part(s) of this document
Eugene Brinkhof
Chapter 6: Flex-Rigid design rules, Chapter 3.1.3: Clearances and tolerances
Marc Botterweck
Chapter 2.4: Cost influences for pcba’s, Chapter 4.1: Standard stackup for Rigid pcb’s,
Chapter 6.4.1: Standard stackup (Flex / Flex-rigid)
Dimitri Filaktakis
Chapter 1
2
ID
Description
IP/ECR, CR/PR
Action holder
1
Par. 3.1.1 is only based on dimensions received by Neways. This should cover
all our suppliers. Questionnaire is send to our suppliers, but waiting for response
JGAC
2
Par 7.5.2. Pin in Paste needs more information from suppliers
MBOT
3
Par. 3.8.2. Scoring not allowed, maybe for a select kind of boards it’s allowed, Is
Grade 4 clean needed for all boards
JGAC
3
Maintainer
Modified date
Status
Revision
IP/ECR,
CR/PR
Comment
MMAE
2012-11-29
Draft
00
Creation
MMAE
2012-12-21
For Review
01
Review chapter H2, H3, H4
MMAE
2013-02-04
For Review
02
Processed TDL chapter H1, H2, H3, H4
MMAE
2013-03-15
For Review
03
Added chapters H5 & H7
Review Chapters H1-5 & H7 by PCB Team
MMAE
2013-04-24
Draft
04
Processed TDL for H1-5 & 7.
Added chapters H6, 8, 10 & 11
MMAE
2013-04-26
For Review
05
Some minor changes
Review Chapters H1-8, 10 & 11
MMAE
2013-05-31
UCC
06
Processed TDL for H1-8, 10 & 11
MMAE
2013-06-14
For Review
07
Added chapter 9. Added a quick reference list to
chapter 1.
MMAE
2013-07-04
UCC
08
Processed TDL for H9.
Added H3.1.3.3 Copper positioning tolerance
Updated H5.3 with new values
MBOT
2016-07-21
For Review
09
Update: Add 1.2.2 Dispensation, update 3.8 with
more info about panelization, add 3.9 Edge
plating, add 5.11 Heavy copper, update 5.3 High
Current, change clearance boardoutline to
min.500um,
MBOT
2016-12-22
UCC
10
Processed TDL
4
CONTRIBUTING AUTHORS
DOCUMENT CHANGE & HISTORY RECORD
OPEN ISSUES
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 3 of 118
1
2
Ref.
Title, author
Document name
Status
[1.1]
GID PCBA process Memory Jogger <JEDE>
D000104924
UCC
[1.2]
GID PCB Process Memory Jogger <DIFI>
D000064411
UCC
[1.3]
3
Ref.
Title, author
Document name
Status
[2.1]
Template Board Technology Specification, <MBOT>
D000094837
UCC
[2.2]
GID Template PLI (P)PCA, <DIFI>
D000015952
UCC
[2.3]
GID PCB stack / build-up, <MBOT>
D000023606
UCC
[2.4]
GID WoW Mentor Expedition Templates Creation EE7.9.x, <EHAR>
D000151580
UCC
[2.5]
PCB Stackup templates Library, <MBOT>
Link to html page
[2.6]
GID constructing symbols, cells and parts
D000225737
UCC
[2.7]
Manufacturing specification for printed circuit boards, <EUBR>
D000124477
UCC
4
Ref.
Title, author
Document name
Status
[3.1]
VSD Mechanical Tolerances PCB, <EUBR>
D000092534
UCC
[3.2]
IPC-2152, IPC
IPC-2152
UCC*
[3.3]
IPC-6012D, IPC
IPC-6012D
UCC*
[3.4]
IPC-6013C, IPC
IPC-6013C
UCC*
[3.5]
IPC-A-600J, IPC
IPC-A-600J
UCC*
[3.6]
PIR Influence of copper balancing on pcb's on cross-talk and
capacitive loading, <GPOO>
42589
UCC
[3.7]
GID ESC Flex-PCB HV vacuum interconnect, <EUBR>
D000023134
UCC
[3.8]
GID Electrical safety of PCBAs and racks, <HLAN>
D000086055
UCC
[3.9]
PIR WorkStream5 Connector watertight, locking & guiding,<LBON>
D000114540
UCC
[3.10]
PIR Tolerances PCA, <EUBR>
D000111623
UCC
[3.11]
GID EMC Design Guidelines for PCAs, <MCOE>
D000021403
UCC
[3.12]
VSD PCBA Technology design rules (drawings)
D000203057
UCC
[3.13]
PIR Heavy Copper PCBs
D000352454
UCC
[3.14]
PIR PCB Thermal reliefs
D000241013
UCC
[3.15]
PRD Non-Compliance Process
D000261000
UCC
[3.16]
GID Hatched Planes Topology Study
D000276542
UCC
[3.17]
PSA Cover investigation for design rules
D000469404
UCC
[3.18]
XLS Simulation tracks in air and vacuum
D000479306
UCC
[3.19]
PSA Investigation IPC2152 Current vs Trace
D000479307
UCC
[3.20]
GID Devil's Vacuum Handbook
D000024294
UCC
[3.21]
GID IE-SEO SCRS Electrical, <WSLO>
D000033886
UCC
5
6
7
Ref.
Title
Author
Modified date
D000104924
GID PCBA Process Memory Jogger
Dekkers, Frank
03-Mar-2016
8
9
Controlling documents 10
Subsidiary documents 20
Reference documents 30
APPLICABLE DOCUMENTS
* The documents with their status and/or other information can be found in the ISAS tool
TCE Controlling documents (auto generated, do not change) 40
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 4 of 118
1
Ref.
Title
Author
Modified date
42589
PIR Influence of copper balancing on
pcb's on cross-talk and capactive
loading
Poorter, Gerben
13-Feb-2009
D000021403
GID EMC Design Guidelines for PCAs
xx Coenen, Mart INACTIVE
16-Feb-2011
D000023134
GID ESC Flex-PCB HV vacuum
interconnect
Brinkhof, Eugene
10-Mar-2015
D000023606
GID PCB stack / build-up
Botterweck, Marc
16-Sep-2013
D000033886
GID IE-SEO SCRS Electrical
Mensvoort, Tiny van
13-Dec-2016
D000086055
GID Electrical safety of PCBAs and
racks
Langeler, Herman
31-Aug-2015
D000092534
VSD Mechanical Tolerances PCB
Brinkhof, Eugene
25-Nov-2016
D000103851
PIR Failure mechanisms of PCBs in
water
Patrascu, Mihai
06-Jun-2012
D000111623
PIR Tolerances PCA
Brinkhof, Eugene
05-Feb-2013
D000114540
PIR WorkStream5 Connector
watertight, locking & guiding
Bongers, Leon
29-Nov-2012
D000115483
PIR Mounting principles PCA & Cables
in dynamical environment
Housen, Dries
22-Feb-2013
D000124477
EPS Manufacturing Specification PCB
Brinkhof, Eugene
17-Sep-2015
D000137742
XLS traceability matrix design rules
flex pca production and installation
Bex, Jan
28-Feb-2013
D000151580
GID WoW Mentor Expedition
Templates EE7.9.x
Botterweck, Marc
06-Oct-2016
D000158170
TDL Design Rules PCB Technology
Filaktakis, Dimitri
22-Dec-2016
D000188728-00
TDL GID PCBA Technology Design
rules H1,5-8,10-11
xx Maenhout, Michel INACTIVE
31-May-2013
D000199510
TDL GID PCBA Technology Design
rules H9
xx Maenhout, Michel INACTIVE
04-Jul-2013
D000203057
VSD PCBA Technology design rules
(drawings)
Botterweck, Marc
19-Dec-2016
2
Abbreviation
Description
AOI
Automated Optical Inspection
AR
Annular Ring
AXI
Automatic X-ray Inspection
BGA
Ball Grid Array component
BST
Boundary Scan Testing
BTS
Board Technology Specification
CAF
Conductive Anode Filament
CDR
Critical Design Review
CES
Constraint Editing System
CL
Competence Leader
CU
Copper
DRC
Design Rule Check
ECAD
Electronic Computer Aided Design
EDS
Electronic Design Services
TCE Reference documents (auto generated, do not change) 50
ABBREVIATIONS
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 5 of 118
Abbreviation
Description
ENEPIG
Electroless Nickel Electroless Palladium Immersion Gold
ENIG
Electroless Nickel Immersion Gold
EMC
Electro Magnetic Compatibility
EMI
Electro Magnetic Interference
EMN
Electro Mechanical Neutral
FP
Flying Probe
FPT
Flying Probe Testing
GL
Group Leader
GND
Ground
HASL
Hot Air Solder Leveling
HV
High Voltage
IAg or ImAg
Immersion Silver
IDF
Intermediate Data Format
ICT
In Circuit Test
IEC
International Electrotechnical Commission
IPC
Industry association for Printed Circuit board and electronics manufacturing service companies
ISn or ImSn
Immersion Tin
i.s.o.
Instead of
LL
Lessons Learned
L&T
Layout & Technology
NPTH
Non Plated Through Hole
NX
Unigraphics
ODB
Open Data Base
OSP
Organic Solderability Preservative
PCA
Printed Circuit Assembly (=PCB with components), also called PCBA
PCB
Printed Circuit Board (=PCB without components)
PCBA
Printed Circuit Board Assembly (=PCB with components), also called PCA
PER
Proto Evaluation Report
PI
Power Integrity
PiP
Pin In Paste
PIR
Preliminary Investigation Report
PLI
PCB Layout Input
PSA
Pressure Sensitive Adhesive
PTH
Plated Through Hole
PROM
Programmable Read-Only Memory (= memory component)
RefDes
Reference Designator
SI
Signal Integrity
SMD
Surface Mount Device
SO
Small Outline package
SOT
Small Outline Transistor package
SOW
Statement Of Work
TAR
Test Analysis (acceptance) Report
TAS
TPD Acceptance by Supplier
TCE
TeamCenter
THT
Through Hole Technology
TPD
Technical Product Documentation
TPS
Test Performance (Plan) Specification
UDL
User Defined Layer
VuV
Valor Universal Viewer
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 6 of 118
Abbreviation
Description
Other abbreviations can be found in myASML or ASML/WIKI
1
Definition
Description
Active PCBA
PCB’s containing connectors, passive & active components
Assembly
outline
Graphical figure, representing the body of the component
Base copper
The thin copper foil portion of a copper-clad laminate for PCB’s. It can be present on one or both sides of the
laminate.
BTS
Board Technology Specification. This document contains all necessary data to setup the technology in the
PCB Layout. This document is created before the PCB Layout starts. This document is also the Sheet 110
which is part of the PCB TPD output
Board outline
A closed polygon that defines the boundary or extents of the PCB
Bondply
Basic PCB material for flexible PCB’s, formed by a combination of a polyimide film (Kapton) and an adhesive
layer on both sides
CAF
Conductive anodic filament (CAF) occurs in substrates and PCB’s when a Cu conductive filament forms in the
laminate dielectric material between two adjacent conductors or plated through vias under an electrical bias.
Capped via
Via which is completely covered at the surface with copper, including the via hole.
CES
Constraints Editing System. CES is an integrated spreadsheet-based constraint editing interface for both the
schematic capture and physical PCB layout design tools in the Mentor Graphics software flow
Cleanliness
Grade
Established level of cleanliness in a given volume, or on a given surface. (specified in the TPD of the PCB)
Contour
An opening in the PCB formed by a laser or mechanical milling process. Contours can have non-circular
shapes.
Cover layer
Cover layer is a composite of polyimide film (Kapton), coated on one side with a proprietary acrylic adhesive.
Cover layer can be used to encapsulate etched details in flexible and rigid-flex multi-layer constructions for
environmental protection and electrical insulation.
DFX
Design for Excellence (X = Manufacturability, Testability, Cost-Effectiveness)
dl-edev-edspcb-library
Contact distribution list for ASML mail. Mails send to this address are send to the maintainer of the PCB library.
Dyne
Unit, used for measuring surface tension. For example, the surface tension of distilled water is 72 dyne/cm at
25 °C; in SI units: 72 mN/m
EMN file
IDF board file. Used for data exchange between 3D mechanical construction and 2D PCB layout
EPAK
Software for NX which transfers PCBA data between NX (3 dimensional world) and ECAD (2 dimensional
world)
Extrude height
The height of a 3 dimensional shape in a 3D mechanical construction program like UniGraphics
Fiducial
Registration marker on the PCB, used for alignment aid during the assembly processes.
Finish
A protective and solderable coating applied to uncovered copper features on a PCB.
Finished
copper
The final copper after completion of the production of the PCB. Including copper plating and finishing.
Globtop
Drop of special formulated resin deposited over a micro-chip, part or protrusion.
Hand
soldering
Hand soldering is the process of selectively soldering electronic components to a printed circuit board to form
an electronic assembly. This process is performed with hand tools, typically with a soldering iron, soldering
gun, or a torch. Often the term “manual soldering” is used for the same process.
HASL
Hot-air solder leveling. The PCB is dipped into a bath of molten solder such that all exposed copper surfaces
are covered by solder. Excessive solder is removed by scraping the PCB with hot air knives.
Hole (PCB)
A circular opening in the PCB formed by a laser or mechanical process.
Hybrid
PCBA which uses special material as a carrier (e.g. ceramic carrier).
Impedance
controlled
stackup
A stackup that has it’s material properties and thicknesses carefully chosen to be able to layout traces as
transmission lines with a specific impedance value. These traces are bound to a specific trace width and
clearance.
Jitter
Jitter is the movement in time of the crossing or data transition from signal to signal with respect to the clock
DEFINITIONS
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 7 of 118
Definition
Description
that is part of the data path. Jitter is at its lowest when the two signals cross in the “straight” parts of the rising
and falling edges.
Keep-out
Forbidden area for defined features (like traces, vias, components, …) Also called “Void” or “Obstruct”
Laminate
Homogeneous basic PCB material formed by a combination of copper foil, prepreg and copper foil
Mandrel
A spindle or an axle around which material may be shaped
Net-class
User defined category of nets. All nets within a net-class have one or more properties in common.
NX
Software for creation of 3D mechanical constructions from Unigraphics Solutions (UGS)
Obstruct
Forbidden area for defined features (like traces, copper, vias, components, …) Also called “Keep-out” or
“Void”
Pad
Designed surface of conductive and solderable material on a PCB
Padstack
Combination of pads on different layers and a hole. The padstack can also contain the soldermask opening,
plane clearance and plane connection shape.
Passive &
active
components
Passive components: Resistor, inductor and/or capacitor
Active components: components which rely on a source of energy; like a transistor, op-amp & programmable
Device
Passive PCBA
PCB’s containing only passive components and connectors
PCB Stackup
The layered combination of different PCB materials with detailed specifications of all involved materials
Pitch
Minimum distance between the center of component leads or the soldering balls of a BGA
Plane
Designed surface area with conductive material on a PCB, used for transportation of power source signals or
large currents. Also for ground and shielding (grid/full plane)
Polar tooling
SI9000 v12.05
The Polar Instruments Si9000 Transmission Line Field Solver incorporates fast and accurate frequencydependent PCB transmission line modelling. The Si9000 provides for both lossless and frequency-dependent
modelling and extracts full transmission line parameters for a wide range of PCB transmission lines. The
Si9000 uses advanced field solving methods to calculate PCB trace impedance for most single-ended and
differential circuit designs. Based on Boundary Element analysis, the Field Solver is able to provide rapid
modelling for a wide range of microstrip, stripline and coplanar structures.
Potted Hole
Also called a counter-bore hole. This is a cylindrical flat-bottomed hole that enlarges another coaxial hole. A
potted hole is typically used when a fastener, such as a socket head cap screw, is required to sit flush with or
below the level of a PCB surface.
Prepreg
Basic PCB material build from woven glass, coated with resin, intended to form a carrier and an isolator for
and between 2 copper foils
Press-fit
mounting
A press-fit connector is mounted to the board, through the pressing in of the contact pins into a PCB through
hole. The cross section of the pin is greater than the diameter of the PCB hole. This difference in pin cross
section and hole diameter results in a deformation of the PCB hole and/or the cross section of the pin during
the insertion process. As a result: a gas-tight connection is formed without soldering or using thermal
processes.
Ref-des
Reference Designator = Unique identification of a component on the PCBA. (Like: R10, C100, RA11, U1A, …)
Reflow
soldering
Reflow soldering is a process in which a solder paste (sticky mixture of powdered solder and flux) is used to
temporarily attach one or several electrical components to their contact pads, after which the entire assembly
is subjected to controlled heat, which melts the solder, permanently connecting the joint. Heating may be
accomplished by passing the assembly through a reflow oven or under an infrared lamp or by soldering
individual joints with a hot air pencil
Soldering
dwell time
Soldering dwell time is the time that the component lead is in contact with bath of solder
Scoring
A process which leaves a V-groove or V-cut in the PCB material on both sides of the PCB. Used for creating
breakoff lines on which the depanelization of the individual PCBA’s from a panel can be done with a V-cutting
blade.
Selective wave
soldering
Selective wave soldering is the process of selectively soldering electronic components to a printed circuit
board to form an electronic assembly. This process is automatic and uses a selective wave soldering machine.
SELV
A SELV circuit is a secondary circuit, with a working voltage between any two conductors in the circuit or one
circuit conductor and PE less than 42.4V peak to peak 42.4V peak or less than 60V DC. More info can be
found in ref[3.8].
Sheet 110
Within ASML this is defined as physical data. In the context of PCBA’s this is used as the Board Specification
layer. This sheet is part of PCB TPD output
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 8 of 118
Definition
Description
Sheet 130
Circuit diagram or schematic drawing
Signal integrity
Signal Integrity is the process of understanding and controlling the collective effects of “real world” behaviors
on an ideal digital signal, to maintain reliable, error-free circuits and systems.
Soldermask
Solder mask or solder resist is a thin lacquer-like layer of polymer that is applied to the surface of a PCB for
protection against oxidation and to prevent solder bridges from forming between closely spaced solder pads.
Contact pads, or soldering pads are left free of soldermask
Silkscreen
Line art and text added to the surface of a PCB. This text is most often colored in white.
Skew
The difference in propagation delay between two or more signal paths
Solder Resist
= Soldermask
Stackup
Ordered combination of PCB material layers, which together form a PCB
Stiffener
The Stiffener is a non-patterned, read no copper, FR4, polyimide or metal part that functions as a local
strengthening placed onto the flexible PCB.
Through Hole
(TH)
A hole in the PCB that protrudes the whole PCB, a through hole can be plated or non-plated.
Trace
Designed surface line with conductive material on a PCB, used for transportation of an electrical signal
Tombstoning
The raising of one end, or standing up, of a leadless component from the solder pad. This phenomenon is the
result of an imbalance of the wetting forces during reflow soldering.
Utilization rate
A factor, showing the efficiency of the panelization of individual PCB’s in a production panel.
µvia
Microvias are vias that have a finished hole diameter < 0.15mm, and are formed either through laser or
mechanical drilling, wet/dry etching, photo imaging or conductive ink formation, followed by a plating operation.
Via
A vertical plated connection between all or several layers to establish an electric contact. The via is not
intended as a through hole for component leads or other features.
Via plugging
The via hole is closed on one side of the PCB with additional solder mask
Void
Forbidden area for defined features (like traces, vias, components, …) Also called “Keep-out” or “Obstruct”
Wave
soldering
Wave soldering is a large-scale soldering process by which electronic components are soldered to a printed
circuit board to form an electronic assembly. This process uses a wave soldering machine where the complete
board is transported over a bath with liquid soldering material
Wire bonding
Wire bonding is a method of making interconnections between an integrated circuit die and an integrated
circuit’s package or a printed circuit board by using aluminum, copper or gold wires.
1
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 9 of 118
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TABLE OF CONTENTS
1 INTRODUCTION................................................................................................................................................. 16
1.1 MAINTAINING THIS DOCUMENT ................................................................................................................................17
1.2 TECHNOLOGY FLOW ..................................................................................................................................................17
1.2.1 STANDARD TECHNOLOGY FLOW .......................................................................................................................18
1.2.2 DISPENSATION .....................................................................................................................................................18
1.2.3 SPECIAL TECHNOLOGY REQUEST .....................................................................................................................19
1.3 INTERPRETATION .......................................................................................................................................................19
1.4 ROLES ..........................................................................................................................................................................19
1.5 QUICK REFERENCE ....................................................................................................................................................20
2 PCBA .................................................................................................................................................................. 21
2.1 PCBA TYPES ................................................................................................................................................................21
2.1.1 ASML PCBA TYPES ...............................................................................................................................................21
2.1.2 ASSEMBLY METHODS ..........................................................................................................................................21
2.1.3 ASSEMBLY COMBINATIONS ................................................................................................................................22
2.2 PCB TYPES ................................ ................................ ..................................................................................................23
2.3 PCB TECHNOLOGY CLASSES ...................................................................................................................................23
2.3.1 PCB TECHNOLOGY CLASS DEFINITION ............................................................................................................. 23
2.3.2 PCB TECHNOLOGY CLASS DRIVERS .................................................................................................................24
2.3.3 PCB TECHNOLOGY CLASS VERSUS BGA PITCH ..............................................................................................24
2.4 COST INFLUENCES FOR PCBA’S ..............................................................................................................................24
2.4.1 PCB COST DRIVERS .............................................................................................................................................25
2.4.2 PCBA COST DRIVERS...........................................................................................................................................27
3 MECHANICS ...................................................................................................................................................... 29
3.1 BOARD .........................................................................................................................................................................29
3.1.1 BOARD DIMENSIONS (X,Y) ...................................................................................................................................29
3.1.2 BOARD THICKNESS ..............................................................................................................................................30
3.1.3 CLEARANCES AND TOLERANCES ......................................................................................................................31
3.1.3.1 THICKNESS TOLERANCES ON PCB SURFACE ............................................................................................32
3.1.3.2 COPPER THICKNESS ON INNER LAYERS ....................................................................................................33
3.1.3.3 COPPER POSITIONING TOLERANCES .........................................................................................................33
3.1.4 MAXIMUM ALLOWED BOW & TWIST ...................................................................................................................33
3.1.5 PIN PROTRUSION THROUGH-HOLE COMPONENTS .........................................................................................34
3.2 HOLES ..........................................................................................................................................................................34
3.2.1 NON-PLATED HOLES ............................................................................................................................................34
3.2.1.1 NON-PLATED MOUNTING HOLES..................................................................................................................35
3.2.2 PLATED HOLES ..................................................................................................................................................... 35
3.2.2.1 PLATED MOUNTING HOLES ...........................................................................................................................36
3.2.2.2 MINIMUM ANNULAR RING ..............................................................................................................................37
3.2.3 VIAS ........................................................................................................................................................................38
3.2.3.1 VIA TYPES AND COMBINATIONS...................................................................................................................38
3.2.3.2 STANDARD VIAS .............................................................................................................................................38
3.2.3.3 HOLE WALL PLATING THICKNESS ................................ ................................................................................39
3.2.3.4 VIA ASPECT RATIO .........................................................................................................................................39
3.2.4 POTTED HOLES ....................................................................................................................................................40
3.2.4.1 NON-PLATED POTTED HOLES ......................................................................................................................40
3.2.4.2 NON-PLATED POTTED HOLE CLOSE TO BOARD OUTLINE ........................................................................41
3.2.4.3 PLATED POTTED HOLES ................................................................................................................................41
3.2.5 BOARD OUTLINE, CONTOURS AND SLOTS .......................................................................................................41
3.2.6 REFERENCE HOLES .............................................................................................................................................42
3.3 OBSTRUCTS ................................................................................................................................................................43
3.3.1 HEIGHT OBSTRUCTS............................................................................................................................................44
3.4 COPPER AREAS ..........................................................................................................................................................44
3.5 CONDUCTIVE CONTACTS ..........................................................................................................................................45
3.6 PCB AREAS COVERED BY POLYIMIDE COVER LAYER ..........................................................................................45
3.7 GLUE AREAS ...............................................................................................................................................................46
3.8 PANELIZATION ............................................................................................................................................................47
3.8.1 BREAKAWAY TABS AND MILLING .......................................................................................................................47
3.8.2 SCORING ...............................................................................................................................................................48
3.9 EDGE PLATING ............................................................................................................................................................48
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
Page 10 of 118
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4 PCB STACKUP FOR RIGID PCB’S .................................................................................................................. 49
4.1 STANDARD STACKUP ................................................................................................................................................49
4.2 NON-STANDARD STACKUP .......................................................................................................................................49
4.3 PCB FINISH ................................ ..................................................................................................................................50
5 PCBA LAYOUT DESIGN RULES / GUIDELINES ............................................................................................. 51
5.1 COPPER WIDTH AND CLEARANCE RULES ..............................................................................................................51
5.2 SOLDERMASK .............................................................................................................................................................51
5.3 COVER LAYER .............................................................................................................................................................52
5.4 HIGH CURRENT ...........................................................................................................................................................53
5.4.1 TRACES ..................................................................................................................................................................53
5.4.1.1 TRACE WIDTH VS. CURRENT CALCULATION ..............................................................................................53
5.4.2 VIAS ........................................................................................................................................................................54
5.4.3 VOLTAGE DROP ....................................................................................................................................................54
5.4.4 THERMAL RELIEFS AND WIDE COPPER TRACES .............................................................................................55
5.5 HIGH SPEED DESIGN .................................................................................................................................................56
5.5.1 IMPEDANCE ...........................................................................................................................................................56
5.5.1.1 SINGLE ENDED IMPEDANCE .........................................................................................................................57
5.5.1.2 DIFFERENTIAL IMPEDANCE ..........................................................................................................................58
5.5.1.3 LENGTH MATCHING WITHIN A DIFFERENTIAL PAIR ...................................................................................59
5.5.1.4 LENGTH ROUTING ..........................................................................................................................................59
5.5.2 REFERENCE PLANES ...........................................................................................................................................60
5.5.3 RETURN PATH .......................................................................................................................................................61
5.5.4 TERMINATION .......................................................................................................................................................62
5.5.5 STUB-LENGTH RESTRICTION ..............................................................................................................................63
5.5.6 ROUTING TOPOLOGY...........................................................................................................................................63
5.5.7 ANALOG / DIGITAL / OTHER .................................................................................................................................64
5.6 EMC / EMI .....................................................................................................................................................................65
5.6.1 CROSSTALK ..........................................................................................................................................................67
5.7 THERMAL PADS UNDERNEATH DEVICES ................................................................................................................68
5.8 ROUTING DO’S AND DON’TS .....................................................................................................................................69
5.9 COPPER BALANCING .................................................................................................................................................70
5.10 TEXT .............................................................................................................................................................................70
5.11 HEAVY COPPER ..........................................................................................................................................................71
6 FLEX / FLEX-RIGID ........................................................................................................................................... 72
6.1 DEFINITIONS ...............................................................................................................................................................72
6.1.1 LEGEND .................................................................................................................................................................72
6.1.2 FLEX APPLICATION DEFINITION ........................................................................................................................73
6.2 MECHANICS .................................................................................................................................................................73
6.2.1 BOARD DIMENSIONS ............................................................................................................................................73
6.2.2 ROBUSTNESS .......................................................................................................................................................74
6.2.2.1 TEAR PROTECTION ........................................................................................................................................74
6.2.2.2 STRAIN RELIEF................................................................................................................................................74
6.2.2.3 FLEX AND FLEX-RIGID GEOMETRIC ARCHITECTURE ................................................................................75
6.2.3 NON-PLATED HOLES IN FLEXIBLE AREA ...........................................................................................................77
6.2.4 CONTOURS IN FLEXIBLE AREA ...........................................................................................................................77
6.2.5 BENDING RADIUS .................................................................................................................................................77
6.3 LAYOUT ........................................................................................................................................................................79
6.3.1 SIGNAL ROUTING .................................................................................................................................................79
6.3.2 CONTROLLED IMPEDANCE ROUTING ................................................................................................................79
6.3.3 HATCHED AND FULL PLANE REFERENCE .........................................................................................................80
6.4 STACKUP .....................................................................................................................................................................82
6.4.1 STANDARD STACK-UP .........................................................................................................................................82
6.4.2 NON-STANDARD STACKUP .................................................................................................................................82
6.4.3 FLEXIBLE LAYER COUNT .....................................................................................................................................82
6.4.4 BOOKBINDER CONSTRUCTION ..........................................................................................................................83
6.4.5 STANDARD VERSUS MULTI LEVEL FLEX-RIGID CONSTRUCTION ..................................................................83
6.5 STIFFENERS ................................................................................................................................................................84
6.5.1 STIFFENERS USED FOR PCB THICKNESS OR STRENGTH INCREASE ..........................................................85
6.6 FIDUCIALS ...................................................................................................................................................................85
7 COMPONENT PLACEMENT DESIGN RULES AND GUIDELINES ................................................................. 86
7.1 KEEP-OUT AREA .........................................................................................................................................................86
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
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7.2 REFERENCE HOLES ...................................................................................................................................................86
7.3 FIDUCIALS ...................................................................................................................................................................86
7.3.1 BOARD OR GLOBAL FIDUCIALS ................................................................................................ .......................... 87
7.3.2 COMPONENT OR LOCAL FIDUCIALS ..................................................................................................................88
7.4 PLACEMENT RULES / GUIDELINES ...........................................................................................................................88
7.4.1 COMPONENT PLACEMENT OUTLINE..................................................................................................................88
7.4.2 BGA REPAIR AREA ...............................................................................................................................................88
7.4.3 HIGH AND LARGE COMPONENTS .......................................................................................................................89
7.4.4 PRESS-FIT .............................................................................................................................................................90
7.4.5 HEAT MANAGEMENT ............................................................................................................................................90
7.4.6 DECOUPLING ........................................................................................................................................................91
7.4.6.1 DECOUPLING OF IC’S .....................................................................................................................................91
7.4.6.2 DECOUPLING OF BGA’S .................................................................................................................................92
7.4.7 DOT NUMBER RESISTORS ..................................................................................................................................92
7.4.8 POLARIZED COMPONENTS .................................................................................................................................93
7.4.9 PART SPREADING ................................................................................................................................................93
7.5 SOLDERING .................................................................................................................................................................94
7.5.1 SELECTIVE WAVE SOLDERING ...........................................................................................................................94
7.5.2 PIN IN PASTE .........................................................................................................................................................94
7.5.2.1 PASTE MASK ...................................................................................................................................................94
7.6 WIRE BONDING ...........................................................................................................................................................95
7.6.1 DESIGN RULES .....................................................................................................................................................95
7.6.2 BONDING PAD SIZE ..............................................................................................................................................95
7.6.3 PRECAUTIONS IN THE PCB-TPD .........................................................................................................................96
8 HAZARDOUS AND HIGH VOLTAGES ............................................................................................................. 97
9 NON-STANDARD ENVIRONMENT ................................................................................................................... 98
9.1 MOISTURE ...................................................................................................................................................................98
9.1.1 COATING ................................................................................................................................................................ 98
9.1.2 GLOBTOP ...............................................................................................................................................................98
9.1.3 COVER LAYER .....................................................................................................................................................100
9.1.4 SEALING RINGS ..................................................................................................................................................100
9.2 VACUUM DESIGN RULES .........................................................................................................................................102
9.2.1 TRACE WIDTHS IN VACUUM ..............................................................................................................................102
9.2.2 STACKUP RULES ................................................................................................................................................102
9.2.3 OUTER LAYERS ..................................................................................................................................................102
9.2.3.1 DESIGN RULES FOR ACTIVE PCBA’S .........................................................................................................103
9.2.3.2 DESIGN RULES FOR PASSIVE PCBA’S .......................................................................................................104
9.2.4 SEALING RINGS IN VACUUM .............................................................................................................................104
9.2.5 CLEANING ............................................................................................................................................................104
9.2.6 STRAIN RELIEF FOR VACUUM ..........................................................................................................................105
9.2.7 HAZARDOUS VOLTAGE FLEX PCB’S ................................................................................................................105
9.2.8 TPD-PCB FOR VACUUM .....................................................................................................................................105
9.2.8.1 TPD-PCB FOR PCBA’S ..................................................................................................................................105
10 PCBA MANUFACTURING TEST TECHNOLOGIES ....................................................................................... 106
10.1 IN CIRCUIT TEST (ICT) ..............................................................................................................................................106
10.2 FLYING PROBE TEST (FPT) .....................................................................................................................................107
10.3 BOUNDARY SCAN TEST(BST) .................................................................................................................................108
10.4 CONNECTIVITY TEST ...............................................................................................................................................108
11 TPD PCB .......................................................................................................................................................... 109
11.1 PREPARATION FOR TPD ..........................................................................................................................................109
11.1.1 TEXT MARKINGS .................................................................................................................................................109
11.1.2 LOGOS ON THE BOARD .....................................................................................................................................110
11.1.2.1 PCB LOGOS ...................................................................................................................................................110
11.1.2.2 PCA SUPPLIER TRACEABILITY LOGO ........................................................................................................111
11.1.3 DIMENSION DRAWING ........................................................................................................................................111
11.1.4 DRILL DRAWING ..................................................................................................................................................113
11.1.5 EDGE PLATING ....................................................................................................................................................114
11.2 BOARD TECHNOLOGY SPECIFICATION (BTS) .......................................................................................................115
11.3 ADDITIONAL DOCUMENTS .......................................................................................................................................115
11.4 FINAL PCB-TPD DATASET ........................................................................................................................................116
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
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APPENDIX A PCB TECHNOLOGY CLASSES DETAIL .................................................................................... 117
APPENDIX B PCBA TYPE DEFINITION ............................................................................................................ 118
Figure 1-1 Maintenance design rule document ..................................................................................................... 17
Figure 1-2 Dispensation process ........................................................................................................................... 18
Figure 2-1 PCB types ............................................................................................................................................. 23
Figure 2-2 PCB technology class versus BGA pitch .............................................................................................. 24
Figure 2-3 PCB cost standard factor ...................................................................................................................... 25
Figure 3-1 PCBA maximum dimensions ................................................................................................................ 29
Figure 3-2 PCBA without break-off edges ............................................................................................................. 30
Figure 3-3 PCBA with break-off edges .................................................................................................................. 30
Figure 3-4 Mechanical tolerances on a PCB ......................................................................................................... 31
Figure 3-5 surface thickness tolerances for covered and non-covered copper ..................................................... 32
Figure 3-6 Copper positioning tolerances .............................................................................................................. 33
Figure 3-7 Bow ....................................................................................................................................................... 33
Figure 3-8 Twist ..................................................................................................................................................... 33
Figure 3-9 Bow & twist ........................................................................................................................................... 33
Figure 3-10 Pin protrusion ................................................................................................................................ 34
Figure 3-11 Non-plated hole and Mounting hole .............................................................................................. 34
Figure 3-12 Plated hole and mounting hole ...................................................................................................... 36
Figure 3-13 Annular ring ................................................................................................................................... 37
Figure 3-14 Via types ........................................................................................................................................ 38
Figure 3-15 Via construction ............................................................................................................................. 39
Figure 3-16 Total via length .............................................................................................................................. 39
Figure 3-17 Potted holes 3D view..................................................................................................................... 40
Figure 3-18 Potted holes cross-section view .................................................................................................... 40
Figure 3-19 non-plated potted hole................................................................................................................... 40
Figure 3-20 Potted hole close to edge .............................................................................................................. 41
Figure 3-21 Potted hole intersects edge ........................................................................................................... 41
Figure 3-22 Board outline, contours and slots .................................................................................................. 41
Figure 3-23 Reference hole construction. ........................................................................................................ 42
Figure 3-24 Obstruct types ............................................................................................................................... 43
Figure 3-25 Obstructs with electrical clearance ................................................................................................ 43
Figure 3-26 Height obstructs ............................................................................................................................ 44
Figure 3-27 Copper areas in 3D-model ............................................................................................................ 44
Figure 3-28 Panelization example .................................................................................................................... 47
Figure 5-1 Soldermask clearance rules ................................................................................................................. 51
Figure 5-2 Cover layer design rules ....................................................................................................................... 52
Figure 5-3 Hole thermal relief ................................................................................................................................ 55
Figure 5-4 SMD thermal relief ................................................................................................................................ 56
Figure 5-5 Single ended impedance ...................................................................................................................... 57
Figure 5-6 Single ended impedance structures ..................................................................................................... 57
Figure 5-7 Differential impedance .......................................................................................................................... 58
Figure 5-8 Differential impedance structures ......................................................................................................... 58
Figure 5-9 Length routing ....................................................................................................................................... 60
Figure 5-10 Stubs ............................................................................................................................................. 63
Figure 5-11 Star topology ................................................................................................................................. 63
Figure 5-12 Daisy-chain topology ..................................................................................................................... 63
Figure 5-13 Functional blocks power planes .................................................................................................... 64
Figure 5-14 Functional blocks one GND plane ................................................................................................. 64
Figure 5-15 Functional blocks split GND plane ................................................................................................ 64
Figure 5-16 Thermal pad layout options ........................................................................................................... 68
Figure 5-17 Copper balancing dimensions and build-up .................................................................................. 70
Figure 5-18 Text dimensions ..................................................................................................................................... 70
LIST OF FIGURES
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
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Figure 5-19 Silkscreen clearance .............................................................................................................................. 71
Figure 6-1 Legend .................................................................................................................................................. 72
Figure 6-2 Flex definition ....................................................................................................................................... 73
Figure 6-3 Rounded corners flex and flex-rigids .................................................................................................... 74
Figure 6-4 Strain relief ........................................................................................................................................... 74
Figure 6-5 Flex and flex-rigid geometric constraints / requirements ...................................................................... 75
Figure 6-6 Flex and flex-rigid copper pattern requirements ................................................................................... 75
Figure 6-7 Flex-rigid cross-hatch plane requirements at transition area ............................................................... 76
Figure 6-8 Non-plated contour in flexible area ....................................................................................................... 77
Figure 6-9 Screenshot Bending Radius Calculator. ............................................................................................... 78
Figure 6-10 Preferred hatch pattern calculation ............................................................................................... 80
Figure 6-11 Maximum flexible layer count constructions ................................................................................ 82
Figure 6-12 Prohibited bookbinder construction ............................................................................................... 83
Figure 6-13 Standard level rigid surface areas ................................................................................................. 83
Figure 6-14 Split level rigid surface areas ........................................................................................................ 83
Figure 6-15 Examples of stiffeners applied to the flexible PCB. ...................................................................... 84
Figure 6-16 Example of stiffeners applied to the rigid PCB. ............................................................................. 85
Figure 6-17 Additional (component) fiducial placement ................................................................................... 85
Figure 7-1 Fiducial ................................................................................................................................................. 86
Figure 7-2 Placement outline ................................................................................................................................. 88
Figure 7-3 Repair area ........................................................................................................................................... 89
Figure 7-4 High / Low components ........................................................................................................................ 89
Figure 7-5 Dot nr. Resistors in schematic .............................................................................................................. 92
Figure 7-6 Dot nr. resistors on PCB ....................................................................................................................... 92
Figure 7-7 Orientation of polarized components .................................................................................................... 93
Figure 7-8 Optimize part spread ............................................................................................................................ 93
Figure 7-9 Bonding pad size .................................................................................................................................. 95
Figure 9-1 Globtop design rules ............................................................................................................................. 99
Figure 9-2 Globtop examples ................................................................................................................................. 99
Figure 9-3 Connector alignment pins covered with cover layer ........................................................................... 100
Figure 9-4 Sealing ring principle .......................................................................................................................... 100
Figure 9-5 Sealing ring PCB layout ...................................................................................................................... 100
Figure 9-6 Sealing ring ......................................................................................................................................... 101
Figure 9-7 Plugged Via ....................................................................................................................................... 101
Figure 9-8 Filled Via ............................................................................................................................................ 101
Figure 9-9 Filled and Capped Via ....................................................................................................................... 101
Figure 9-10 Vacuum & ≥ 160V ....................................................................................................................... 102
Figure 9-11 Vacuum design rules for active PCBA’s...................................................................................... 103
Figure 9-12 Vacuum design rules for passive PCBA’s ................................................................................... 104
Figure 9-13 Cleaning for vacuum ................................................................................................................... 104
Figure 9-14 “No solderresist allowed” mark on both standard soldermask layers ......................................... 105
Figure 10-1 Typical boundary scan circuit ...................................................................................................... 108
Figure 11-1 Text markings .............................................................................................................................. 109
Figure 11-2 PCB Logos .................................................................................................................................. 110
Figure 11-3 PCA Supplier Traceability logo ................................................................................................... 111
Figure 11-4 Dimension drawing ...................................................................................................................... 112
Figure 11-5 Drill run examples ........................................................................................................................ 113
Figure 11-6 Drill table example ....................................................................................................................... 113
Figure 11-7 Dimensioning edge plating .......................................................................................................... 114
Figure 11-8 Drill drawing Edge plating ........................................................................................................... 114
Figure 11-9 Copper pattern edge plating ........................................................................................................ 115
Figure 11-10 Soldermask/Cover layer edge plating ........................................................................................ 115
Table 1.1 Roles definition ..................................................................................................................................... 19
Table 2.1 ASML PCBA type definitions ................................................................................................................ 21
LIST OF TABLES
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
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Table 2.2 Components and assembly technologies ............................................................................................. 21
Table 2.3 PCBA Assembly combinations ............................................................................................................. 22
Table 2.4 PCB technology classes overview ....................................................................................................... 23
Table 2.5 BGA vs. PCB technology class ............................................................................................................ 24
Table 2.6 PCB related cost drivers ....................................................................................................................... 27
Table 2.7 PCB flex material cost drivers .............................................................................................................. 27
Table 2.8 PCBA process cost drivers ................................................................................................................... 28
Table 2.9 PCBA component and material cost drivers......................................................................................... 28
Table 3.1 Break-off edge dimensions ................................................................................................................... 30
Table 3.2 Board thickness .................................................................................................................................... 30
Table 3.3 Total copper thickness on external layers ............................................................................................ 32
Table 3.4 Finished soldermask and polyimide cover layer thickness .................................................................. 32
Table 3.5 Finishing thickness ............................................................................................................................... 32
Table 3.6 Minimum copper foil thickness on inner layers after processing .......................................................... 33
Table 3.7 Copper positioning tolerances .............................................................................................................. 33
Table 3.8 Maximum Bow & Twist ......................................................................................................................... 34
Table 3.9 Pin protrusion design rules ................................................................................................................... 34
Table 3.10 Non-plated holes .................................................................................................................................. 34
Table 3.11 Non-plated mounting holes................................................................................................................... 35
Table 3.12 Plated holes .......................................................................................................................................... 36
Table 3.13 Standard plated mounting holes ........................................................................................................... 37
Table 3.14 Minimum annular ring plated holes ...................................................................................................... 37
Table 3.15 Via types ............................................................................................................................................... 38
Table 3.16 Standard vias ........................................................................................................................................ 38
Table 3.17 Copper plating ...................................................................................................................................... 39
Table 3.18 Standard non-plated potted holes ........................................................................................................ 40
Table 3.19 Design rules for non-plated potted holes .............................................................................................. 40
Table 3.20 Reference holes placement .................................................................................................................. 42
Table 3.21 obstruct types ....................................................................................................................................... 43
Table 3.22 Obstruct calculation parameters for dimensions .................................................................................. 43
Table 3.23 Design rules for copper areas .............................................................................................................. 45
Table 3.24 Cover layer materials ............................................................................................................................ 46
Table 4.1 Standard stackups for rigid PCB’s ........................................................................................................ 49
Table 4.2 PCB Surface Finish .............................................................................................................................. 50
Table 5.1 Soldermask clearance rules ................................................................................................................. 51
Table 5.2 Soldermask tolerance ........................................................................................................................... 51
Table 5.3 Cover layer design rules ....................................................................................................................... 52
Table 5.4 Cover layer positioning tolerance ......................................................................................................... 52
Table 5.5 Accepted temperature rise above ambient........................................................................................... 53
Table 5.6 Minimum final copper thickness for trace width calculations ................................................................ 53
Table 5.7 Trace width calculator fields ................................................................................................................. 53
Table 5.8 Via current capacity calculator fields .................................................................................................... 54
Table 5.9 Through hole thermal relief design rules .............................................................................................. 55
Table 5.10 Maximum current for 10°C temperature rise for thermal relief ...................................................... 55
Table 5.11 Maximum current for 30°C temperature rise for thermal relief ...................................................... 55
Table 5.12 Thermal relief design rules ................................................................................................................... 56
Table 5.13 Single ended impedance design rules ................................................................................................. 57
Table 5.14 Differential impedance design rules ..................................................................................................... 59
Table 5.15 Reference plane design rules ............................................................................................................... 60
Table 5.16 Return path design rules ...................................................................................................................... 61
Table 5.17 termination examples ........................................................................................................................... 62
Table 5.18 Termination design rules ...................................................................................................................... 62
Table 5.19 Stub design rules .................................................................................................................................. 63
Table 5.20 Topology design rules .......................................................................................................................... 64
Table 5.21 Functional block design rules (analog/digital/…) .................................................................................. 65
Table 5.22 EMC design rules ................................................................................................................................. 67
Table 5.23 Crosstalk design rules .......................................................................................................................... 68
Table 5.24 Thermal pad layout options .................................................................................................................. 69
Table 5.25 Routing do’s and don’ts ........................................................................................................................ 70
Table 5.26 Copper balancing ................................................................................................................................. 70
GID PCBA Technology Design rules
Maintainer :
Document name :
Modified date :
Status :
Botterweck, Marc (mbotterw)
D000118344-10-GID-001
2016-12-22
UCC
© ASML 2016
Confidential
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Table 5.27 Copper text dimensions ........................................................................................................................ 70
Table 5.28 Silkscreen clearance rule ..................................................................................................................... 71
Table 5.29 Heavy Copper, Trace, Clearance & Via requirements ......................................................................... 71
Table 5.30 Available heavy copper thicknesses ............................................................................................. 71
Table 6.1 Maximum flex and flex-rigid board (design) dimensions ...................................................................... 73
Table 6.2 Flex and flex-rigid geometric and copper pattern constraints / requirements ...................................... 76
Table 6.3 Non-plated holes in flexible area .......................................................................................................... 77
Table 6.4 Signal routing ........................................................................................................................................ 79
Table 6.5 Controlled Impedance routing .............................................................................................................. 79
Table 6.6 Hatched reference plane application .................................................................................................... 81
Table 6.7 Flex-rigid stackups ................................................................................................................................ 82
Table 6.8 Stiffener tolerances ............................................................................................................................... 84
Table 7.1 Fiducial dimensions when soldermask is used .................................................................................... 86
Table 7.2 Fiducial dimensions when cover layer is used .................................................................................... 86
Table 7.3 Board or global fiducials placement ..................................................................................................... 87
Table 7.4 Component or local fiducials placement ............................................................................................... 88
Table 7.5 Press-fit placement design rules .......................................................................................................... 90
Table 7.6 Heat management guidelines ............................................................................................................... 91
Table 7.7 Decoupling of IC’s ................................................................................................................................ 91
Table 7.8 Decoupling of BGA’s ............................................................................................................................ 92
Table 7.9 Dot number resistor design rules ......................................................................................................... 93
Table 7.10 Selective wave soldering design rules ................................................................................................. 94
Table 7.11 Wire bonding design rules .................................................................................................................... 95
Table 7.12 Bonding pad size ........................................................................................................................... 95
Table 7.13 Wire bonding PCB-TPD precautions .................................................................................................... 96
Table 9.1 Moisture resist design rules .................................................................................................................. 98
Table 9.2 Coating rules ........................................................................................................................................ 98
Table 9.3 Globtop design rules ............................................................................................................................. 99
Table 9.4 Sealing ring design rules .................................................................................................................... 100
Table 9.5 Sealing ring clearances ...................................................................................................................... 101
Table 9.6 PCB Outgassing numbers .................................................................................................................. 102
Table 9.7 Vacuum design rules for active PCBA’s ............................................................................................. 103
Table 9.8 Vacuum design rules for passive PCBA’s .......................................................................................... 104
Table 10.1 Test-points for ICT .............................................................................................................................. 106
Table 10.2 Design rules for ICT ............................................................................................................................ 107
Table 10.3 Test-point for FP ................................................................................................................................. 107
Table 10.4 Design rules for FPT ........................................................................................................................... 107
Table 10.5 design guidelines for boundary scan signals...................................................................................... 108
Table 11.1 Text markings on the PCB.................................................................................................................. 109
Table 11.2 Layer identification text outside the PCB .................................................................................... 110
Table 11.3 Design rules for logos ......................................................................................................................... 111
Table 11.4 Dimension drawing design rules ........................................................................................................ 112
Table 11.5 PCB-TPD dataset contents ................................................................................................................ 116
Table 11.6 ODB++ contents ................................................................................................................................. 116
GID PCBA Technology Design rules
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1 INTRODUCTION
This document describes the PCBA design rules for the development of PCBA’s within the ASML PCBA
design process. The PCBA design rules, which are mentioned in this document, are standard design
rules and are intended to cover approximately 90% of the PCBA’s within the ASML machines. The other
10% of the PCBA’s will be designed with deviations of those PCBA design rules. Deviating from those
design rules is described in chapter 1.2.
This document is applicable for ASML employees responsible for a new, or to be modified PCBA, and
Subcontractors (co-developers) who design a new or modified PCBA for ASML as defined in the
Statement of Work (SoW) for that development.
In case of a redesign / modification of existing PCBA’s, it is not required to adjust the PCBA to the latest
revision of this document. In these cases only the mandatory design changes are applicable, necessary
for DFx and/or functionality.
In more detail this document describes design rules and/or guidelines for:
PCB Technology (Rigid, Flex and Flex-rigid)
PCB Mechanical
PCBA Assembly
Hazardous and high voltage
Non-standard environment
PCBA manufacturing test
TPD PCB
This document will not describe design rules and/or guidelines for:
Functional design
WoW & Processes (Processes are described in controlling documents [1.1] and [1.2])
Firmware
Geometry of standard boards (back panels, rear panels etc.)
Mechanical parts on PCBA’s (ejector handles, front panels etc.)
TPD PCBA
Possible users within the projects are:
PCBA Owners / PCBA Designers
EM Engineers
SI/PI/DFx/Thermal analysts
Supply chain engineers
DFx Engineers Supplier
PCB Layout Engineers
PCB Technology Experts
EL Designers
EM Engineers
Cost Engineers
M-Constructor
The following paragraphs describe the process regarding the maintenance of the design rules document
and the dispensation process when standard design rules are not sufficient for a project.
GID PCBA Technology Design rules
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PCB Technology
design rules
(D000118344)
Projects
(PIR/TPS/TAR)
This document
Information
Roadmap PCB
Layout &
Technology
SCRS for Electrical
and electronic
products
Design rules
Supplier
Maintenance
Design rule document
Dispensation
Process
TAS & PER
(feedback &
learning)
Normative
(EIC, IPC,etc)
Lessons Learned
PCBA Process
Memory Jogger
(D000104924)
Controlling
1.1 MAINTAINING THIS DOCUMENT
This GID is under change control by the CL PCB L&T and the GL EDEV-EDS. Input for this document is
derived from:
Projects of various platforms (NXT, NXE, etc.)
Roadmap projects, initiated by the PCBL&T Team (new technology)
SCRS Electrical- and Electronic-products
Design rules suppliers
Repeating authorized dispensations
TAS & PER (feedback & learning)
Normative (IPC, IEC, etc.)
Lessons Learned (LL)
This GID is a so-called "living document" and shall be updated in an unscheduled time frame. Please
check TCE for the latest version. In case of an update, all people and/or roles mentioned on the
reviewers list of this document, will be involved in the review process.
1.2 TECHNOLOGY FLOW
The Technology Flow is the process flow that describes how the Projects within ASML need to use this
document. The process can be divided in two major directions:
1. Use of standard technology (Applicable for approximately 90% of all projects)
2. Use of new/special technology that is not standard technology (Applicable for approximately 10%
of all projects)
Figure 1-2 gives an overview of the Technology Flow.
Figure 1-1 Maintenance design rule document
GID PCBA Technology Design rules
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Kick-off
1
A4 Spec
PIR
PCBA Process
9
Standard
Technology
Possible?
no
yes
TPS/TAR
GID/white paper
Standard
technology
possible?
yes
no
Add technology to standard
design rules
Post-Layout Review (PoLR)
10
Project specific solution
(solution at 12-nc level)
LEGEND:
Review step
Main Process
10% of all
projects
90% of all
projects
TPD
Dispensation
Applicable?
PLI
Document dispensation
on design rule in PLI
ASML Standard Proven solutions
D000118344
yes
no
1.2.1 STANDARD TECHNOLOGY FLOW
When standard technology is possible to solve technical challenges, all design rules from this document
need to be applied. No exceptions are allowed.
1.2.2 DISPENSATION
When a PCBA design (project) needs to deviate from the PCBA design rules, as described in this GID, a
dispensation is possible. The deviation can be discussed with the PCBT Expert that is assigned to the
applicable project (see ROMEO) or with CL PCB Layout & Technology. After the discussion, the PCB
Expert shall give an advice on how to handle the deviation with a Dispensation note. All dispensations
within the applicable design shall be documented in the PLI. A list of all dispensation notes can be found
on: http://collaboration.asml.com/knowledge/de-pcb-layout-technology/Pages/Design-Rules.aspx
Positive advice: Proposal can be implemented
Negative advice: Start Non-Compliance Process, described in ref[3.15]
The responsibility for every deviation lies within the projects. The Dispensation process can start at any
time within the PCBA Process of a PCBA design. All Dispensation notes will be documented in TCE.
Figure 1-2 Dispensation process
GID PCBA Technology Design rules
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Role
Description
PCBL Engineer
PCB Layout Engineer
PCBA Designer
Electronic Hardware designer
PCBA Owner
Responsible for the execution of every PCBA project step
EM Engineer
Electrical-Mechanical Engineer
EL-Designer
Electrical Layout Designer
M-Constructor
Mechanical constructor
PCBT Expert
PCBA Technology Expert
CL PCB L&T
Competence Leader PCB Layout & Technology
26
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1.2.3 SPECIAL TECHNOLOGY REQUEST
When standard design rules are not sufficient to solve a technical issue, new technology can provide a
solution. For this, an investigation is necessary. A Technology investigation needs to be started with
possible deliverables like A4-Spec, PIR, TPS/TAR and Design Rules. The deliverables depend on the
project.
The Technology request shall be discussed with the CL PCB Layout & Technology or PCBT Expert that
is assigned to the applicable project.
1.3 INTERPRETATION
“Shall”, the emphatic form of the verb, is used throughout this document whenever a requirement is
intended to express a provision that is binding. The words “should” and “may” are used whenever it is
necessary to express non-mandatory provisions.
“Prohibited”, is used throughout this document whenever something is forbidden and a dispensation will
not be granted.
When in this document is referred to the term “base material” it has to be read as laminate, prepregs,
bondplies, cover layers and adhesives, to be used primarily for rigid or multilayer printed circuit boards
and flex or flex-rigid boards for electrical and electronic circuits.
1.4 ROLES
The following roles are used in this document:
Table 1.1 Roles definition
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Subject
(Click on subject words to
jump to the right chapter, use
[Alt + left arrow] to return to
this table)
PLI chapter
Roles
PCBL Engineer
PCBA Designer
PCBA Owner
EM-Engineer
EL-Designer
M-Constructor
Technology flow (Standard Dispensation - Special)
12
X X X X X
X
PCBA Type & PCB Type
1.2
X X X X X
X
Environment: Moisture &
Vacuum
1.2
X X X
X
Assembly methods &
combinations
1.2
X
PCB Technology class ( Trace
width and clearances)
X
X
PCB & PCBA cost drivers
X X X
Board dimensions &
thickness
2.1
X
X
Board clearances and
tolerances
X X X
Surface thickness and
tolerances
X
Bow & Twist
X
Pin-protrusion
6.3
X
Holes: Plated, Non-plated,
Potted holes and reference
holes
2.5
X
X X X X
Vias, standard vias
X
X
Plating thickness inside
plated holes and vias
X
Aspect ratio
X
Contours and slots
2.5
X
Obstructs and height
obstructs
2.3
X
X
Areas: Copper, polyimide
cover layer, Glue
2.4
X
X
Panelization & breakaway
tabs
2.5
X
X
Standard stackups for Rigid
PCB's
1.3
X X X X X
Standard stackups for Flex
and Flex-Rigid PCB's
1.3
3
X X X X X
PCB finish
1.2
X
X
Soldermask
1.3
X
X
Cover layer (Polyimide)
1.3
2.4
X X
High current through traces &
vias, Voltage drop
4
X
X
Thermal reliefs and wide
copper traces
X
X
High speed design:
Impedances, length routing
7.1
X
X
Return Path, Reference
planes, EMC/EMI, Crosstalk
X
X
Subject
(Click on subject words to
jump to the right chapter, use
[Alt + left arrow] to return to
this table)
PLI chapter
Roles
PCBL Engineer
PCBA Designer
PCBA Owner
EM-Engineer
EL-Designer
M-Constructor
Thermal pads
X X
Routing do’s & dont’s
X
Copper balancing
X
Text (silkscreen and copper)
1.3
X
Flex types (Static - Flex to
install - Dynamic)
3
X X X X X
X
F&FR board dimensions
2.1
X
X
F&FR robust: Tear protection,
Strain relief, geometry
3
X X
F&FR copper & signal routing
X
X
F&FR holes and contours
2.5
X
F&FR Bending radius
X X X
F&FR impedance routing
X
X
F&FR Hatched planes
X
X
Stiffeners
3
X
X
Fiducials on F&FR
X
Fiducials
X
Comp. placement outline
X X X
BGA repair area
X
X
Press-fit component keepout
X X X
Heat management
9
X
X
Decoupling: IC, BGA
X
X
Dot number resistors
6.2
X
X
Selective wave soldering
X
X
Wire bonding
6.6
X
X
Hazardous and high voltages
8
X
X
Globtop
6.7
X X X
Alignment pins and cover
layer
X X X
Sealing rings
X X X
Active PCBA's in vacuum
X
X
Passive PCBA's in vacuum
X
X
TPD-PCB for vacuum
X
PCBA test (ICT, FPT, BST)
10
X X X
X
TPD-PCB (text markings,
logo's, dimensions, drill)
X
X
TPD-PCB (Final dataset)
X X X
X
Volume claim
3
X X X
X
2
1.5 QUICK REFERENCE
Table 1.2 Quick reference list
GID PCBA Technology Design rules
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Category
PCBA type
Passive
PCBA
Backplane
Connection board
Terminal plate
Flex/rigid connection
Flex/rigid connection complex
Rear panel (passive)
Active
PCBA
Rear panel (active)
Hybrid
PCA standard
PCA standard + mechanics
Complex PPCA < 2000 components
Complex PPCA < 2000 components + mechanics
Complex PPCA > 2000 components
Complex PPCA > 2000 components + mechanics
8
9
10
11
12
13
Picture
Wave
soldering
Selective Wave
soldering
Reflow
soldering
Press-fit
mounting
Hand
soldering
Wire
Bonding
Through
hole
(THT)
Yes
(1)
Yes
No
(4)
No
No
(3)
No
Surface
Mount
(SMD)
Yes
(2)
No
Yes
No
No
(3)
No
Fine
Pitch
SMD
No
No
Yes
No
No
No
Ball Grid
Array
(BGA)
No
No
Yes
No
No
No
Press-fit
No
No
No
Yes
No
No
Wire
Bonding
No
No
No
No
No
Yes
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2 PCBA
To understand this document, some background information is necessary. This chapter describes the
various PCBA types and PCB types.
2.1 PCBA TYPES
For the PCBA types the assembly methods will be described, together with all applicable combinations.
2.1.1 ASML PCBA TYPES
The following PCBA type definitions are applicable within ASML:
Table 2.1 ASML PCBA type definitions
For more information about the PCBA types and definitions, see: Appendix B .
2.1.2 ASSEMBLY METHODS
Different component types need different assembly technologies. This table illustrates the component
types and the assembly methods that should be applied by the manufacturer.
Table 2.2 Components and assembly technologies
(1) Only allowed if the side to be wave soldered is designed for the wave soldering process
(2) Not allowed for active components, connectors and passive components ≤ 0402 imperial package size
(3) Not Recommended. It is up to the assembly company to decide whether hand soldering shall be used. The
assembly company must be convinced that hand soldering is possible without a footprint change.
(4) Only if through hole components are suitable for PiP process
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3
Preference
Assembly combination
Assembly method
1st side
2nd side
(1)
Reflow
soldering
Press-fit
mounting
(2)
Wave
soldering
(1)
Reflow
soldering
Press-fit
mounting
(2)
Wave
soldering
Lower Preference ----------------------------------------------------------- Higher Preference
1
X
2
X X
3
X
4
X X
5
X X
6
X X
7
X X X
8
X X X
9
X
10
X
X
11
X X
12
X X
13
X X X
14
X X X X
15
X X X
X
4
5
6
7
8
9
10
11
12
13
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2.1.3 ASSEMBLY COMBINATIONS
A combination of different assembly methods is possible. In the table below a preference order for
assembly method combinations is defined. Lower number > easier to manufacture > less costs.
Table 2.3 PCBA Assembly combinations
(1) PiP can be used, If Through hole components are suitable for the reflow process
(2) Wave = Wave and selective wave
Remarks :
1st side can be top or bottom side of the PCB and 2nd side is the other side of the PCB
Hand soldering of THT components is not recommended
Components shall be selected from the preferred components list. When this results in extra assembly
production steps, the consequence of extra cost should be considered.
Selective wave soldering, applied for through hole components, requires a better process control, is time
consuming and implies quality risks. Therefore this process has a lower preference.
Wire bonding is not included. If wire bonding is required, see chapter 7.6.
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2
Rigid Board
Flex board
Flex-rigid board
3
4
5
6
7
8
9
10
11
12
Preferred ----------------------- Non-Preferred | Advanced
(Units = µm) Class
1 2 3 4 5
Min. Trace width / Spacing
200 / 200
150 / 150
125 / 125
100 / 100
75 / 75
Min. finished through hole via diameter
500
300
200
200
150
Min. via pad diameter Outer/Inner layer
1000/1000
700 / 700
500 / 600
500 / 500
450 / 475
Min. Clearance contours & NPTH
500
500
500
500
500
Min. Clearance to board outline
500
500
500
500
500
Max. PCB thickness
(1)
4400
2800
2400
2000
1600
Max. Base copper thickness Outer /
Inner layer
35 / 70
35 / 70
18 / 35
0 / 18
0 / 18
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2.2 PCB TYPES
ASML uses three standard PCB types:
Figure 2-1 PCB types
2.3 PCB TECHNOLOGY CLASSES
The PCB shall be designed such to end up in the lowest possible PCB technology class to avoid
unnecessary risks, lower yield and higher cost.
An optimal PCB technology class is selected by a PCBT expert, based on factors like component
technology, complexity, component density, high current requirements and impedance requirements.
This PCB technology class is used as input for creating the BTS.
2.3.1 PCB TECHNOLOGY CLASS DEFINITION
PCB technology classes are defined, based upon the physical dimensions of traces and clearances on
the PCB. The next table gives a short overview of the PCB technology classes used within ASML.
Table 2.4 PCB technology classes overview
1. Max. PCB Thickness is a relation to the min. finished through hole via diameter, see also chapter 3.2.3.4
Remarks:
The PCB technology class shall be determined by the PCBT expert.
Class 5 is an advanced PCB technology class, which can only be used at areas where it is
absolutely necessary and at special request with the PCBT expert.
Only class 3,4 and 5 can make use of blind micro vias and buried vias. See Table 3.15 and Table
3.16 for via types and the standard vias that shall be used.
If a buried via is used, the layers from where the via hole starts and ends, shall have a maximum
base copper thickness as specified for outer layers.
Class 4 and 5 shall not be used for outer layers. For this reason the value for “max. base copper
thickness on outer layers” is set to “0”.
Appendix A shows each PCB technology class explained in more detail.
GID PCBA Technology Design rules
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1
The choice for a specific pcb technology class is driven by:
Controlled impedance requirements
Component type (BGA, Fine pitch, …)
Available area
2
3
4
5
6
7
8
BGA Pitch (mm)
1 1 0.8
0.8
(2)
0.5
(2)
PCB technology Class
3 4 5
(1)
5
(1)
5
(1)
Via Inner Pad size P (µm)
600
500
475
350 (µVia) / 475 (buried)
250 (µVia)
Via Finished Hole size H (µm)
200
200
150
125 (µVia) / 150 (buried)
100 (µVia)
Trace width W / Spacing S (µm)
125 / 125
100 / 100
100 / 100
100 / 100
75 / 75
#Traces / Channel
1 2 1 1 1
9
10
11
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2.3.2 PCB TECHNOLOGY CLASS DRIVERS
2.3.3 PCB TECHNOLOGY CLASS VERSUS BGA PITCH
When a BGA is applied, the pitch of the BGA balls will restrict the size and clearance of traces and the
via used to interconnect the BGA. The pitch will determine the PCB technology class to use for routing
this BGA.
Figure 2-2 PCB technology class versus BGA pitch
Table 2.5 BGA vs. PCB technology class
(1) The local BGA fan-out requires a via, trace and clearances technology as defined in technology class 5. Other
areas shall be routed compliant to a lower technology class.
(2) Blind µvia and/or buried vias shall only be used when absolutely necessary and require a dispensation.
2.4 COST INFLUENCES FOR PCBA’S
This chapter provides the common cost drivers compared to standard processes as an indication of
several suppliers. The cost factors are subjected to fluctuations according the market situation. The
numbers mentioned are intended to give relative comparison between different values of the same
parameter (ex. 2 layers vs. 4 layers), but the numbers mentioned have no absolute value to compare
different parameters (ex. layer count vs. board thickness). Therefore they have no absolute relevance
and the numbers can't be used to make a simple cost calculation. A PCBA-estimator tool can be found
on the DE MA&I TC Cost Engineering experts sharepoint site:
http://collaboration.asml.com/knowledge/cost-engineering/esti/SitePages/Home.aspx
Note: cost estimations to be created and evaluated for Volume situation / quantity
GID PCBA Technology Design rules
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2
3
4
• Total 4 layer rigid board
(Signal-Plane-Plane-Signal)
• Standard FR4 material
• all layers 35µm copper final
thickness
• copper foil – core – copper foil
construction
• Board Thickness 1.6 mm
• Trace/Gap outer layers 125µm
• Trace/Gap inner layers 125µm
• Solder mask on top and bottom
• Only Through hole via ≥ 300µm
• PCB Surface Finish ENIG
• Batch size = 5
• Standard 20 delivery days
Figure 2-3 PCB cost standard factor
5
6
7
Option
Cost factor (≈)
Remarks
Layer
count
2
0,75
Layer count, based on standard production process of a PCB
4
1.00
6
1,25
8
1,50
10
1,75
12
1,95
14
2,20
16
2,45
18
2,70
20
2,90
Board
thickness
1.6
1.00
Board thickness (mm).
2.0
1.05
2.4
1,15
3.2
1,25
4.4
1,35
Board type
Rigid
1.00
Note!!!! It’s very difficult to define a general cost factor, because
the cost of a flex is influenced by several parameters and
production processes.
Flex PCB
2,00
Flex-rigid PCB
3,50
PCB
Surface
finish
LF-HASL
0,90
PCB surface finish.
ImSn
0.95
ENIG
1.00
ImAg
0.95
Solder
mask
No solder mask
0,96
Solder mask. Standard on Top -and Bottom side.
Solder mask
1.00
Cover
layer
No cover layer
1.00
Polyimide cover layer instead of Solder mask (material and
handling)
Cover layer
1.10
2.4.1 PCB COST DRIVERS
The table below shows the cost drivers or factors of a PCB.
The factor 1 is the standard factor; the most common factor for the standard production process of a
PCB. The standard factors are:
E.g. If a 4 layer board is standard and you need 6 layers, this will increase the cost with ± 25%.
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Option
Cost factor (≈)
Remarks
No silkscreen
1 side
2 sides
1.00
A single sided silkscreen is included in the standard price.
1.00 1.02
150
200
300
500
1.15
Minimal via finished hole size (µm). Standard > 300µm
1.10
1.00
1.00
Not filled
Filled
1
1.10
Vias filled with an epoxy material and covered with copper
Via types
and
combinatio
ns
A – Through hole via
1.00
B – Buried via (1 type)
1.25
B – Buried via (2 different types)
1.35
C – Blind via
Not used within ASML
D – Blind µvia (1 side 125µm)
1.20
D – Blind µvia (2 sides 125µm)
1.30
D – Blind µvia (1 side 100µm)
1.30
D – Blind µvia (2 sides 100µm)
1.40
E – Buried µvia (1 type)
1.25
E – Buried µvia (2 different types)
1.35
F – Stacked blind and buried µvia
1.35
G – Non-stacked blind µvia &
buried via & blind µvia
1.40
H – Stacked blind µvia & buried via
& blind µvia
1.45
I – Blind µvia in pad
1.25
J – Through hole via, filled and
capped
1.15
Trace /
Spacing
(internal &
external)
75
1.40
Inner and outer layer trace / gap (clearance) distance (µm).
100
1.20
125
1.00
150
1.00
200
1.00
Cu
thickness
(internal)
17.5
1.00
Inner layer CU-foil thickness (µm).
35
1.00
70
1.10
105
1.25
Cu
thickness
(external)
17.5
1.00
Outer layer CU-foil thickness (µm).
35
1.00
70
1.10
105
1.25
Delivery
time Rigid
boards
5
1.75
Delivery days rigid boards
10
1.50
15
1.30
20
1.00
Delivery
time
Flex/Flexrigid
boards
5
n.a.
Delivery days Flex-rigid, The manufacturer is not able to deliver
a flex or flex-rigid board shorter than 15 working days, because
of complex production process
10
n.a.
15
1.40
20
1.24
25
1.00
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Option
Cost factor (≈)
Remarks
PCB batch
size
1
4.00
Batch size of a PCB (indication if multi PCB’s are possible in
one panel size)
2
2.00
5
1.00
10
0.60
20
0.40
1
2
3
4
Type
Cost factor (≈)
Remarks
Cores
AP-9111R 1 25um Kapton + 2 x 35um copper
AP-9121R
1
50um Kapton + 2 x 35um copper
AP-9131R
1.75
75um Kapton + 2 x 35um copper
AP-9141R
2.5
100um Kapton + 2 x 35um copper
AP-8515R
1.2
25um Kapton + 2 x 18um copper
AP-8525R
1.2
50um Kapton + 2 x 18um copper
AP-8535R
2.4
75um Kapton + 2 x 18um copper
AP-8545R
2.4
100um Kapton + 2 x 18um copper
AP-9212R
1.2
25um Kapton + 2 x 70um copper
AP-9222R
1.2
50um Kapton + 2 x 70um copper
AP-9232R
1.75
75um Kapton + 2 x 70um copper
AP-9242R
2.5
100um Kapton + 2 x 70um copper
Adhesive
FR-0100
0.8
25um adhesive
FR-0200 1 50um adhesive
Bondply
FR-0111
1
25um Kapton + 2 x 25um adhesive
FR-0121
1.85
50um Kapton + 2 x 25um adhesive
FR-0212
2.8
25um Kapton + 2 x 50um adhesive
Cover layer
FR-0110 1 25um adhesive + 25um Kapton
FR-0120
1.4
25um adhesive + 50um Kapton
FR-7001
2.45
13um adhesive + 13um Kapton
FR-0210
1.4
50um adhesive + 25um Kapton
FR-0220
1.95
50um adhesive + 50um Kapton
5
6
7
8
Process
Factor
Remark
SMD process
Assembly sides
Single sided or double sided
# components
Qty of high speed placement components (0402, 0603,
SOT, SO, …)
Qty of high accuracy components (BGA, Fine Pitch, …)
Qty manual smd placement
Manual assembly +
soldering
# Components not in SMD process
Components which need manual placement
Soldering process:
- Reflow
- Wave
- Hand soldering
For SMD and Fine-pitch SMD components
For through-hole components and non-active SMD
Not preferred solder process (increase costs)
Table 2.6 PCB related cost drivers
The table below shows the cost factors of the most common used flex materials as opposed to the
standard materials, which are expressed in bold text.
Table 2.7 PCB flex material cost drivers
(Lines marked as bold text are the standard materials)
2.4.2 PCBA COST DRIVERS
The following assembly processes are factors which estimate the cost of the product.
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Process
Factor
Remark
Components after mass
soldering
Press-fit connectors
Labels
Mechanical parts
PROM’s (off line programming)
Wire bonding
Depanelization
# of cuts
Depanelization method:
- Scoring
- Breakaway tabs
How many cuts need to be made to detach the PCB
from the panel
Cutting knife (only straight lines)
Every tab has to be cut off or routed
Test costs
Different testing methods
Troubleshooting time
Parallelism
Handling time
Repair time
On board programming required?
AOI, FPT, BST, ICT, Functional test, …
Which is depending on the ease of diagnostics
Related to volume
Other processes
Mechanical assemblies
Cleaning
Potting
coating
According to the ASML Cleaning Class
Delivery time
Faster delivery = higher cost
Batch size
More PCBA’s = lower cost / PCBA
Also depends on #PCBA’s in one assembly panel
1
2
3
Factor
Remark
Combination of assembly
methods
This is illustrated in the PCBA assembly combinations Table 2.3. A lower priority number
equals lower assembly cost.
Component cost
The price of the components
BGA pitch
BGA pitch influences the PCB technology and cost. See also Table 2.5
BGA Pitch (mm)
1 1 0.8
0.8
0.5
#Traces / Channel
1 2 1 1 1
Via Finished Hole size (µm)
200
200
150
125 (µVia) /
150 (buried)
100 (µVia)
Cost factor
1.00
1.10
1.10
1.50
1.50
Coating
material and time to process
Glob top
Material and time to process
Stiffeners
Material, preparation and time to assemble
Extra features
All extra features, special requirements and mechanical items are cost factors for a PCBA
4
5
6
7
8
9
Table 2.8 PCBA process cost drivers
The following component choices and materials are factors which influence the PCBA cost:
Table 2.9 PCBA component and material cost drivers
To create a designer cost estimate (DE or DCE) on cost, use "PCBA Estimator tool" available on the DE
MA&I TC Cost Engineering experts sharepoint site:
http://collaboration.asml.com/knowledge/cost-engineering/esti/SitePages/Home.aspx
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3 MECHANICS
This chapter describes the mechanical constraints for the PCB types. The exceptions for flex and flexrigid PCB’s are mentioned in Chapter 6.1 of this document.
3.1 BOARD
3.1.1 BOARD DIMENSIONS (X,Y)
The standard maximum PCBA dimensions are 480 X 400 mm. When larger dimensions are required,
refer to the next drawing. This drawing illustrates the maximum bare board dimensions (green dotted
line), together with the maximum dimensions for each possible PCBA manufacturing process. The
maximum bare board dimensions are based on a production panel size of 18”x 24”, 1”of each size needs
the PCB Manufacturer for his PCB process. For board thicknesses see chapter 3.1.2
Figure 3-1 PCBA maximum dimensions
The above dimensions are applicable if the next conditions are met:
Board fiducials placed according the design rules, see chapter 7.3 fiducials
Reference holes placed according the design rules, see chapter 3.2.6 reference holes
Free component area of 5mm available on 2 opposite and parallel sides of the PCB, according
the design rules, see chapter 7.1 keep-out area
Straight edges at the sides with the 5mm free component area.
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2
3
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5
6
Figure 3-2 PCBA without break-off edges
Figure 3-3 PCBA with break-off edges
7
8
9
10
Situation
Solution
No free component area of 5mm available
on 2 opposite and parallel sides
Add 3mm break-off edge, and ensure 5mm component
free area on at least 2 opposite and parallel sides
Irregular shaped edge on one or two
sides with the 5mm free component area
Add 3mm break-off edge on each irregular shaped edge
Reference holes cannot be placed
Add 3mm break-off edge
Board fiducials cannot be placed
None. Fiducials shall be located on the functional PCBA
11
12
13
14
15
16
17
Rule
Value(s)
Thickness range (mm)
1.6 – 4.4
Preferred board thicknesses (mm)
1.6 – 2.0 – 2.4 – 3.2 – 4.4
18
19
20
In case one or more of the above conditions cannot be met, an additional space is required to place
break-off edges and a milling gap of 2mm. This space decreases the maximum allowed PCBA
dimensions as displayed in Figure 3-1.
The final designed PCB is displayed in the next picture. The left drawing illustrates the situation where all
above conditions are met. The right drawing illustrates the situation where these conditions are not met.
The dimensions for these break-off edges can be found using the next Table 3.1 and Figure 3-3. See
also chapter 3.8 panelization
Table 3.1 Break-off edge dimensions
The orientation of the PCB shall be with the longest side of the PCB parallel to the X-direction.
The origin shall be located at the lower left corner and on the top surface of the PCB.
3.1.2 BOARD THICKNESS
Table 3.2 Board thickness
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2
3
This picture is a snapshot of the drawing in TCE at the time this document went UCC.
Check TCE for the most recent version of this drawing. TCE link:
ref [3.1]<D000092534.
Or click the figure on the left to activate the hyperlink which points to TCE.
3.1.3 CLEARANCES AND TOLERANCES
Figure 3-4 Mechanical tolerances on a PCB
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1
2
3
4
5
6
7
8
Base Copper
(µm)
Standard plating (20µm)
(1)
Flex & Flex Rigid
> 6 layers
Boards with press-fit
components
Cu (µm)
± Tol. (µm)
Cu (µm)
± Tol. (µm)
Cu (µm)
± Tol. (µm)
18
54
22
62
25
62
25
35
68
23
79
26
79
26
70
108
32
112
28
112
28
9
10
11
12
13
14
15
Cover layer type
Thickness (µm)
± Tolerance (µm)
Soldermask
20
10
Cover layer Dupont FR0210
50
25
Cover layer Dupont FR0220
75
25
Cover layer Dupont FR0310
62.5
37.5
16
17
18
Finish type
Thickness
(µm)
± Tolerance
(µm)
ENIG (Preferred finish)
5.5
1.5
ENEPIG
5.5
1.5
HASL (Pb-Free)
10
5
IAg / ImAg
(1)
0.4
0.2
ISn / ImSn
(1)
1.5
0.5
OSP
(2)
N/A
N/A
19
20
21
22
23
24
3.1.3.1 THICKNESS TOLERANCES ON PCB SURFACE
The surface thickness of the PCB is determined by the materials that are used and the manufacturer’s
process tolerances. Below the surface thickness tolerances are given for the different processes in
production.
Figure 3-5 surface thickness tolerances for covered and non-covered copper
Dimension A = Total copper thickness on external layers:
Table 3.3 Total copper thickness on external layers
(1) Standard plating of 20µm applies when the PCB is a:
Rigid board without press-fit components
Flex or Flex-Rigid board without press-fit components and total number of layers ≤ 6
Dimension B = Finished thickness of soldermask or polyimide cover layer:
Table 3.4 Finished soldermask and polyimide cover layer thickness
Dimension C = Finishing thickness:
Table 3.5 Finishing thickness
(1) Due to the low values, no rounding is used. Rounding would end in a zero value.
(2) The N/A, non-applicable, is given, due to the fact that this finish is used as a protection of the bare copper and
disappears during the soldering process.
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2
3
4
Base Copper (µm)
Minimum Cu thickness (µm)
18
12
35
25
70
56
5
6
7
8
9
10
11
12
Positioning tolerance
Value
A: Outer layer to Inner layer
± 250 µm
B: Inner layer to Inner layer (on a core)
± 50 µm
C: Inner layer to Inner layer (core to core)
± 100 µm
Table 3.7 Copper positioning tolerances
Figure 3-6 Copper positioning tolerances
13
14
Figure 3-7 Bow
Figure 3-8 Twist
15
16
17
18
19
3.1.3.2 COPPER THICKNESS ON INNER LAYERS
The copper foils on the inner layers are not plated like the external layers. Due to thickness tolerances
on the copper foils itself and to processing, the final copper thickness on the inner layers can vary.
Table 3.6 Minimum copper foil thickness on inner layers after processing
3.1.3.3 COPPER POSITIONING TOLERANCES
The PCB is stacked-up with several base materials (cores) that are glued together with prepregs. Most
of these separate semi-finished base materials are patterned before adding to the stack. Each patterning
step (exposure) has its tolerance. This results in positioning differences between the different copper
layers. When for example 2 traces are routed exactly above each other on 2 adjacent layers, the result
after production might not be that exact, because of these tolerances. The tolerances involved are
displayed in the next picture and table.
3.1.4 MAXIMUM ALLOWED BOW & TWIST
What :
Measure and calculation method:
This measurement must be done in both planar directions of the PCB. The maximum measured
value of both directions counts.
Figure 3-9 Bow & twist
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Maximum allowed bow & twist for :
Value
Boards before assembly (PCB)
0.75 %
Boards using SMD component types (PCBA)
0.75 %
Boards using all other component types (PCBA)
1.50 %
2
3
4
5
6
7
Rule
Value
Remark
Minimum Pin Protrusion
≥ 0.4mm
= Minimum Pin length – Maximum PCB thickness
Maximum Pin Protrusion
(1)
≤ 2.5mm
= Maximum Pin Length – Minimum PCB thickness
8
9
10
11
12
13
14
15
16
17
Start size diameter(mm)
End size diameter(mm)
Step (mm)
Tolerance
Padstack name example
0.50 - 0.55 - …………… - 5.95 - 6.00
0.05
±0.05
MHN STD D0.50 Tol 0.05
18
Acceptance criteria for bow & twist:
Table 3.8 Maximum Bow & Twist
3.1.5 PIN PROTRUSION THROUGH-HOLE COMPONENTS
The pin protrusion of through-hole components shall be checked to ensure the Solderability of the pin.
Figure 3-10 Pin protrusion
Design rules:
Table 3.9 Pin protrusion design rules
(1) Maximum Pin Protrusion for rack boards ≤ 1.5mm
3.2 HOLES
3.2.1 NON-PLATED HOLES
Non-plated holes are used for two different applications:
Non-plated holes: holes for dowel pins, crossing cables and wires or accessing other features
Non-plated mounting holes: holes for mounting hardware like bolts, nuts, washer rings, etc…
Figure 3-11 Non-plated hole and Mounting hole
Non-plated holes are available according the following table:
Table 3.10 Non-plated holes
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Msize
Fit type
Finished hole size
diameter (mm)
Hole tolerance
(mm)
Obstruct area diameter
(3D-model & EMN)(mm)
Padstack name
M1.6
Minimum
1.90
± 0.05
5.4
MHN STD D1.90 Tol 0.05
Typical
2.00
± 0.05
5.5
MHN STD D2.00 Tol 0.05
Loose
2.20
± 0.05
5.7
MHN STD D2.20 Tol 0.05
M2
Minimum
2.30
± 0.05
6.5
MHN STD D2.30 Tol 0.05
Tight
2.40
± 0.05
6.6
MHN STD D2.40 Tol 0.05
Typical
2.50
± 0.05
6.7
MHN STD D2.50 Tol 0.05
Loose
2.60
± 0.05
6.8
MHN STD D2.60 Tol 0.05
M2.5
Minimum
2.80
± 0.05
7.5
MHN STD D2.80 Tol 0.05
Tight
2.90
± 0.05
7.6
MHN STD D2.90 Tol 0.05
Typical
3.00
± 0.05
7.7
MHN STD D3.00 Tol 0.05
Loose
3.10
± 0.05
7.8
MHN STD D3.10 Tol 0.05
M3
Minimum
3.30
± 0.05
8.5
MHN STD D3.30 Tol 0.05
Tight
3.40
± 0.05
8.6
MHN STD D3.40 Tol 0.05
Typical
3.50
± 0.05
8.7
MHN STD D3.50 Tol 0.05
Loose
3.60
± 0.05
8.8
MHN STD D3.60 Tol 0.05
M4
Minimum
4.40
± 0.05
10.9
MHN STD D4.40 Tol 0.05
Typical
4.60
± 0.05
11.1
MHN STD D4.60 Tol 0.05
M5
Minimum
5.40
± 0.05
12.0
MHN STD D5.40 Tol 0.05
Typical
5.60
± 0.05
12.2
MHN STD D5.60 Tol 0.05
M6
Tight
6.40
± 0.10
14.2
MHN STD D6.40 Tol 0.10
Loose
6.60
± 0.10
14.4
MHN STD D6.60 Tol 0.10
M8
Tight
8.40
± 0.10
18.3
MHN STD D8.40 Tol 0.10
Loose
8.60
± 0.10
18.5
MHN STD D8.60 Tol 0.10
M10
Tight
10.40
± 0.10
22.5
MHN STD D10.40 Tol 0.10
Loose
10.60
± 0.10
22.7
MHN STD D10.60 Tol 0.10
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Remark:
Holes larger then 6mm diameter are not drilled, but milled.
The padstack name syntax is described in Subsidiary documents 2.6. The obstruct area on all layers is
defined by the “Min. Clearance contours & NPTH” rule defined in the PCB technology class, see chapter
2.3.1 pcb technology class definition.
3.2.1.1 NON-PLATED MOUNTING HOLES
The next table lists the commonly used metric size screws with the corresponding non-plated hole size
and a general obstruct area around the center of the hole for traces and vias.
Table 3.11 Non-plated mounting holes
Remarks:
A selection can be made by the EM Engineer between minimum, tight and loose fit, depending on the
tolerances of the PCBA and counterpart(s).
The obstruct area is a forbidden area for traces, vias and components on both outer layer of the PCB. This
area shall be defined by the EM Engineer. The inner layer obstruct is defined by the “Min. Clearance contours
& NPTH” rule defined in chapter 2.3.1 pcb technology class definition.
Obstruct area is based on the fixation of a common bolt, spacer, or washer ring, all possible tolerances and an
extra electrical clearance. If the standard obstruct area is not sufficient, a larger obstruct area shall be created
including all tolerances and electrical clearance (0.2mm), around the mechanical feature.
If a non-plated mounting hole is required, which is not available in the above list, a new library part request
shall be issued to the distribution list mail address: dl-edev-eds-pcb-library.
3.2.2 PLATED HOLES
Plated holes are used for two different applications:
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Figure 3-12 Plated hole and mounting hole
8
9
Finished hole size
diameter(mm)
Hole tolerance (mm)
Cu pad size diameter (mm)
Part Number / FuncID
0.90
± 0.10
1.40
PARTPTH0D900AA
10
11
12
13
14
15
16
17
18
19
20
Msize
Fit type
Finished hole size
diameter(mm)
Hole tolerance
(mm)
Cu pad size
diameter(mm)
Part Number /
FuncID
M1.6
Minimum
1.90
± 0.10
4.90
PARTMTH1M600AD
Typical
2.00
± 0.10
5.00
PARTMTH1M600AC
Loose
2.20
± 0.10
5.20
PARTMTH1M600AB
M2
Minimum
2.30
± 0.10
6.00
PARTMTH2M000AD
Tight
2.40
± 0.10
6.10
PARTMTH2M000AC
Typical
2.50
± 0.10
6.20
PARTMTH2M000AE
Loose
2.60
± 0.10
6.30
PARTMTH2M000AB
M2.5
Minimum
2.80
± 0.10
7.00
PARTMTH2M500AD
Tight
2.90
± 0.10
7.10
PARTMTH2M500AC
Typical
3.00
± 0.10
7.20
PARTMTH2M500AE
Loose
3.10
± 0.10
7.30
PARTMTH2M500AB
M3
Minimum
3.30
± 0.10
8.00
PARTMTH3M000AD
Tight
3.40
± 0.10
8.10
PARTMTH3M000AC
Typical
3.50
± 0.10
8.20
PARTMTH3M000AE
Loose
3.60
± 0.10
8.30
PARTMTH3M000AB
Plated holes = Holes for dowel pins or accessing other features. The minimal copper ring around
these holes guarantees the proper plating of the hole edges.
Plated mounting holes = Holes for mounting hardware like bolts, nuts, washer rings, etc… . The
large copper ring around these holes guarantees a proper contact surface for the fixation of the
bolt and mechanical counterparts and ensures a good electrical connectivity between mechanics
and PCBA.
Plated holes are available according the following table:
Table 3.12 Plated holes
Remark:
Holes above 6mm diameter are not drilled, but milled.
The Cu pad size on all layers is defined by the “Minimum annular ring” rule defined in chapter 3.2.2.2
minimum Annular ring.
If a plated hole is required, which is not available in the above list, a new library part request shall be
issued to the distribution list mail address: dl-edev-eds-pcb-library.
All plated holes need to be available on sheet 130 regardless if connected to a potential or unconnected.
3.2.2.1 PLATED MOUNTING HOLES
The next table lists all metric size bolts with the plated hole size, the copper pad size on the outer layers
of the PCB and the part number of the part used for the schematic design.
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Msize
Fit type
Finished hole size
diameter(mm)
Hole tolerance
(mm)
Cu pad size
diameter(mm)
Part Number /
FuncID
M4
Minimum
4.40
± 0.10
10.40
PARTMTH4M000AC
Typical
4.60
± 0.10
10.60
PARTMTH4M000AB
M5
Minimum
5.40
± 0.10
11.50
PARTMTH5M000AC
Typical
5.60
± 0.10
11.70
PARTMTH5M000AB
M6
Tight
6.40
± 0.10
13.70
PARTMTH6M000AC
Loose
6.60
± 0.10
13.90
PARTMTH6M000AB
M8
Tight
8.40
± 0.10
17.80
PARTMTH8M000AC
Loose
8.60
± 0.10
18.00
PARTMTH8M000AB
M10
Tight
10.40
± 0.10
22.00
PARTMTH10M00AC
Loose
10.60
± 0.10
22.20
PARTMTH10M00AB
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7
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19
20
Finished hole size
(mm)
Minimum Annular ring
(mm)
≤ 1.5
0.25
> 1.5 ≤ 2.5
0.30
> 2.5 ≤ 3.5
0.40
> 3.5
0.50
Table 3.14 Minimum annular ring plated holes
Figure 3-13 Annular ring
21
22
Table 3.13 Standard plated mounting holes
Remarks:
A selection can be made by the EM Engineer between minimum, tight and loose fit, depending on the
tolerances of the PCBA and counterpart(s).
The copper pad size is based on the fixation of a common bolt, spacer, or washer ring.
If the standard Cu pad size is not sufficient, a larger area needs to be created around the mechanical feature
by the EM Engineer, including all tolerances.
If a plated hole is required, which is not available in the above list, a new library part request shall be issued to
the distribution list mail address: dl-edev-eds-pcb-library.
All plated holes need to be available on sheet 130 regardless if connected to a potential or not.
All Part Numbers given in Table 3.13 are having 2 alternate padstacks:
o One with a minimum annular ring copper pad on only inner layers and the given copper pad in Table
3.13 on the outer layers.
o One with a minimum annular ring copper pad on all layers, to use if the given copper pad exceeds the
board outline or is too close to the an object (Not correct designed). The layouter has to create
manually a bigger copper area/pad and free soldermask area/pad which fits to the pad in Table
3.13.
3.2.2.2 MINIMUM ANNULAR RING
Plated holes shall have a minimum copper ring around the finished hole edge, according the next table:
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2
3
Via type(s)
Dispensation
required ?
Figure 3-14 Via types
A
Through hole via
No
B
Buried via
Yes
C
Blind via (not used within
ASML)
NA
D
Blind µvia
Yes
E
Buried µvia
Yes
F
Stacked blind and buried
µvia
Yes
G
Non-stacked blind µvia &
buried via & blind µvia
Yes
H
Stacked blind µvia & buried
via & blind µvia
Yes
I
Blind µvia in pad
Yes
J
Through hole via, filled &
capped
Yes
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5
6
7
8
9
10
11
12
Padstack name
Suitable for
PCB
technology
Class(es)
Suitable for
via type
(chapter
3.2.3.1)
Finished
hole size
(µm)
Cu Pads
Outer / Inner
layers (µm)
Soldermask
opening
(µm)
Max. aspect
ratio
MVIA D100 250 M0
3, 4, 5
D, E, F, G, H & I
100
250 / 250
0
0.8
MVIA D125 350 M0
3, 4, 5
D, E, F, G, H & I
125
350 / 350
0
0.8
VIA D150 TB450 I475 M300
5
A, B, C, G, H, J
150
450 / 475
300
8
VIA D200 TB500 I600 M350
(1)
3, 4, 5
A, B, C, G, H, J
200
500 / 600
350
8
VIA D200 500 M350
3, 4, 5
A, B, C, G, H, J
200
500 / 500
350
8
VIA D300 700 M450
2, 3, 4, 5
A, B, C, G, H, J
300
700 / 700
450
8
VIA D300 TB700 I800 M450
(1)
2, 3, 4, 5
A, B, C, G, H, J
300
700 / 800
450
8
VIA D300 800 M450
(1)
2, 3, 4, 5
A, B, C, G, H, J
300
800 / 800
450
8
VIA D500 1000 M650
1, 2, 3, 4, 5
A, B, C, G, H, J
500
1000 / 1000
650
8
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3.2.3 VIAS
3.2.3.1 VIA TYPES AND COMBINATIONS
The next picture and table show the different via types and combinations that can exist on a PCB.
Table 3.15 Via types
Remarks:
More than one via type can be used on a PCB, but not all combinations are possible. This depends on the
layer buildup, the used materials and the manufacturing sequence of the PCB build. Contact a PCBT
expert to determine the via combinations to use.
If a buried via or µvia is used, the layers from where the via hole starts and ends, shall have a maximum
base copper thickness as specified for outer layers in Table 2.4 PCB technology classes overview.
3.2.3.2 STANDARD VIAS
Standard vias are available according the next table:
Table 3.16 Standard vias
1. For Flex-Rigid designs
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2
3
4
IPC Class2
Copper plating
(average thickness)
Rigid PCB
(µm)
Flex 2 layers
(µm)
Flex & Flex rigid
≤ 6 layers
(µm)
Flex & Flex rigid
> 6 layers
(µm)
Through hole
20
12
25
35
Press-fit
(1)
25 - 50
NA
25 - 50
25 – 50
Blind via
20
NA
20
20
Blind µvia
12
NA
20
20
Buried vias
20
NA
20
20
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8
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𝑨𝒔𝒑𝒆𝒄𝒕 𝒓𝒂𝒕𝒊𝒐 (𝑨𝑹)=
𝐓𝐨𝐭𝐚𝐥 𝐛𝐨𝐚𝐫𝐝 𝐭𝐡𝐢𝐜𝐤𝐧𝐞𝐬𝐬
𝑭𝒊𝒏𝒊𝒔𝒉𝒆𝒅 𝒉𝒐𝒍𝒆 𝒔𝒊𝒛𝒆+𝟎.𝟏𝒎𝒎
≤ 8
𝑨𝒔𝒑𝒆𝒄𝒕 𝒓𝒂𝒕𝒊𝒐 (𝑨𝑹)=
𝐓𝐨𝐭𝐚𝐥 𝐛𝐮𝐫𝐢𝐞𝐝 𝐯𝐢𝐚 𝐥𝐞𝐧𝐠𝐭𝐡
𝑭𝒊𝒏𝒊𝒔𝒉𝒆𝒅 𝒉𝒐𝒍𝒆 𝒔𝒊𝒛𝒆+𝟎.𝟏𝒎𝒎
≤ 8
𝑨𝒔𝒑𝒆𝒄𝒕 𝒓𝒂𝒕𝒊𝒐 (𝑨𝑹)=
𝐓𝐨𝐭𝐚𝐥 𝐛𝐥𝐢𝐧𝐝 𝐯𝐢𝐚 𝐥𝐞𝐧𝐠𝐭𝐡
𝑳𝒂𝒔𝒆𝒓 𝒅𝒓𝒊𝒍𝒍𝒆𝒅 𝒉𝒐𝒍𝒆 𝒔𝒊𝒛𝒆
≤ 0.8
Figure 3-15 Via construction
3.2.3.3 HOLE WALL PLATING THICKNESS
The minimum average copper plating thickness inside hole walls is restricted by IPC:
Table 3.17 Copper plating
Remarks:
The values in this table are derived from IPC-6012D (ref[3.3]) and IPC-6013C (ref[3.4]).
(1) These values are absolute values (not average)
3.2.3.4 VIA ASPECT RATIO
The aspect ratio is the ratio between the total via length and the drilled hole size.
Aspect ratio for through hole vias:
The via length equals the total board thickness.
Aspect ratio for buried vias: AR ≤ 8
The total buried via length shall include all dielectric thicknesses, including the base copper
thickness of all copper layers where the via is drilled through.
Aspect ratio for blind vias (µvias): AR ≤ 0.8
The total blind via length shall include all the dielectric thicknesses, including the base copper
thickness of all copper layers where the via is drilled through.
Figure 3-16 Total via length
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Figure 3-17 Potted holes 3D view
Figure 3-18 Potted holes cross-section view
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3
4
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6
7
Drawing cell name
(3)
D3 (mm)
D4 (mm)
D1
D5
D6
(1)
D7
(2)
Nom.
Tol. ±
Nom.
Tol. ±
(mm)
(mm)
(mm)
(mm)
MHN_POT_D3.00_P6.00_TM6.40_BM7.60
6
0.1 3 0.05
6.4
3.4
6.65
7
MHN_POT_D3.40_P6.00_TM6.40_BM7.60
6
0.1
3.4
0.05
6.4
3.8
6.65
7
MHN_POT_D3.70_P6.50_TM6.90_BM8.30
6.5
0.1
3.7
0.05
6.9
4.1
7.15
7.5
MHN_POT_D10.00_P16.00_TM16.40_BM20.10
16
0.1
10
0.1
16.4
10.4
16.65
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Item
Description
Tolerance /
Dimension
Figure 3-19 non-plated potted hole
H1
Board thickness
±10%
H2
Controlled depth
± 0.125 mm
H3
Remaining PCB material
≥1mm ± 10%
D1
Soldermask opening
D3 + 400µm
Cover layer opening
D3 + 1000µm
D3
Final hole diameter < 6mm
± 50µm
D3
Final hole diameter ≥ 6mm
± 100µm
D4
Final hole diameter <6mm
± 50µm
D4
Final hole diameter ≥6mm
± 100µm
D5
Soldermask opening
D4 + 400µm
Cover layer opening
D4 + 1000µm
D6
(1)
Obstruct on outer layers (Soldermask)
D1 + 250µm
Obstruct on outer layers (Cover layer)
D1 + 500µm
D7
Obstruct on inner layers
(2)
D3 + 1000µm
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3.2.4 POTTED HOLES
All potted holes shall be non-plated !
Not recommended in PCB Designs. Designer to consult PCBT expert (check on
manufacturability, yield, cost impact)
3.2.4.1 NON-PLATED POTTED HOLES
The next picture and table show the non-plated potted holes used within ASML, together with all the
dimensions and design rules.
Table 3.18 Standard non-plated potted holes
Table 3.19 Design rules for non-plated potted holes
Remarks:
(1) Valid for components, vias and copper on the outer layers
(2) Valid for vias and copper on the inner layers
(3) Drawing cell name is the footprint name as defined in the ECAD PCB layout library
Non-plated potted holes are not available as a part for schematic, since they have no electrical connectivity. If non-plated potted holes
are needed, the details need to be supplied in the PLI document.
The tolerances and dimensions are based on round potted holes.
Only H2 can vary and shall be explicitly stated in the PCB TPD. For a correct PCB TPD, a special “drawing cell” representing the
cross/section of the potted hole is available in the ECAD PCB layout library to specify the H2 value.
If a potted hole is required, which is not available in the above list, a new library part request shall be issued to the distribution list mail
address: dl-edev-eds-pcb-library.
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Figure 3-20 Potted hole close to edge
Figure 3-21 Potted hole intersects edge
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3.2.4.2 NON-PLATED POTTED HOLE CLOSE TO BOARD OUTLINE
In case potted holes are placed close to the board outline and the circular potted hole contour intersects
or is too close to the board outline, depth contours shall be created as shown in the next 2 pictures.
The depth contour shape shall be constructed by the EM Engineer, added to the EMN file and described
in the PLI document.
The PCB TPD shall contain detailed dimensions and a cross-section of the depth contour and potted
hole. For a correct PCB TPD, a special “drawing cell” representing the cross/section of the potted hole
with depth contour is available in the ECAD PCB layout library, see Figure 11-4, detail A:A for an
example.
3.2.4.3 PLATED POTTED HOLES Plated potted holes are prohibited
3.2.5 BOARD OUTLINE, CONTOURS AND SLOTS
The board outline is formed by the circumference of the PCB, this outline shall be non-plated.
Contours are cut-outs (not being round holes) within the PCB and can be non-plated or plated.
A slot or slot-hole is a contour in one direction where the radii equals the width/2.
The next picture illustrates all applicable design rules:
Figure 3-22 Board outline, contours and slots
The board outline, contours and slot-holes shall be available in the EMN file and described in the PLI.
The board outline, contours and slot-holes shall be documented in the TPD-PCB data.
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Placement
dimensions
Center reference hole, 4.2mm from
each PCB edge
Preferred
Two reference holes.
(diagonal formation)
PCB dimension
≥ 300 mm
Multiple reference holes.
(triangle formation)
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3.2.6 REFERENCE HOLES
Reference holes are used for production alignment during PCBA manufacturing.
Figure 3-23 Reference hole construction.
Placement obstructs on top side and bottom side are keep-out areas for components.
Placement design rules:
Table 3.20 Reference holes placement
Remarks:
Reference holes do not need to be drawn in the 3D model by the EM Engineer. These holes are placed
by the PCBL engineer during the development of the PCB layout.
The EM Engineer should provide sufficient room for these reference holes on the PCBA.
When there is absolutely no sufficient room for reference holes, they can be omitted. The PCBA
manufacturer can be instructed by the PCBL engineer to place the holes in the break off edges around the
PCB. This situation should be avoided, because it makes repair and testing difficult.
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Not allowed features
Allowed features
Routing obstruct
Traces and copper
Vias, Components
Via obstruct
Vias
Traces, copper and Components
Placement obstruct
Components
Traces, copper and vias
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Parameter
Description
Maximum dimensions
Dimensions of the hardware touching the PCBA
Maximum misalignment
Misalignment between the hardware and the PCBA
Maximum tolerances
Tolerances on the PCBA material and mechanical hardware
Extra electrical clearance = 0.2mm
Around the calculated area to prevent short circuits or
damaging the PCBA copper as shown in the next figure.
If high voltage or hazardous voltage applies, more clearance
shall be required, according chapter 8 hazardous and high
voltages.
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20
21
22
3.3 OBSTRUCTS
Mechanical items, part of the PCBA or from the surroundings, require additional areas or voids on the
PCB to prevent unintended contact to non-conductive or conductive parts. to conductive features,
components and hardware. These areas or voids are called obstructs.
All obstructs shall be described textual and graphical in the PLI document.
All obstructs shall be defined by the EM Engineer and exported to the EMN file for the 3D-2D interface.
The next table and picture shows all type of obstructs and what they result to in layout :
Table 3.21 obstruct types
Figure 3-24 Obstruct types
The dimensions of obstructs shall be defined by the EM Engineer, using the next parameters:
Table 3.22 Obstruct calculation parameters for dimensions
Figure 3-25 Obstructs with electrical clearance
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3.3.1 HEIGHT OBSTRUCTS
Height obstructs are keep-out areas for components which are higher than a fixed value. It is not a keepout for copper, traces or vias.
Height obstructs restrict the placement of components on the top side or bottom side of the PCB.
Height obstructs do not restrict the pin protrusion of through hole and press-fit components. The pin
protrusions in relation to the height constraints shall be checked within the mechanical 3D model by the
EM Engineer.
All obstructs shall be described textual and graphical in the PLI document.
All obstructs shall be defined by the EM Engineer and exported to the EMN file for the 3D-2D interface.
The same calculation parameters as for obstructs shall be used to calculate the dimensions and height
value of height obstructs, found in table 3.22 .
Figure 3-26 Height obstructs
3.4 COPPER AREAS
A specific area on the PCB can be filled with copper for several purposes:
To create an electrical conductive path to or from mechanical hardware
To guarantee a flat surface for sealing in a moisture environment
To enhance the cooling of thermal radiating components
All copper areas shall be described textual and graphical in the PLI document.
All copper areas shall be defined by the EM Engineer and exported to the EMN file for the 3D-2D
interface.
Figure 3-27 Copper areas in 3D-model
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Rule
Description
Remark
No unconnected copper
Copper shall have a defined electric
potential.
If the potential is guaranteed
through a mechanical path,
the physical connection on the
PCBA can be omitted.
Via obstruct
When a flat surface is required for sealing
purpose, a via obstruct shall be applied.
Respect PCB
technology class rules
Minimum clearances and widths shall be
respected according the used PCB
technology class (chapter 2.3.1)
Soldermask clearance
Respect the soldermask clearance rules
(chapter 5.2)
Cover layer clearance
Respect the cover layer clearance rules
(chapter 5.3)
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When defining copper areas, the following items shall be considered and described in the PLI:
Potential or signal connected to the copper (floating or unconnected copper is forbidden)
Should this area be free of soldermask and/or cover layer ?
Should this area be an obstruct for vias ? If so, an additional via obstruct shall be defined.
Should this area allow connected vias with the same potential ?
Should this area be an obstruct for components ? If so an additional placement obstruct shall be
defined.
Design rules for copper areas:
Table 3.23 Design rules for copper areas
3.5 CONDUCTIVE CONTACTS
All conductive patterns shall be covered by soldermask or a polyimide cover layer. An exception to this
rule is required for conductive features which are intended to be reachable, like:
Solder connections
Fiducials
Testpads
Screw connections
Mounting connections
Seal areas
3.6 PCB AREAS COVERED BY POLYIMIDE COVER LAYER
The complete rigid PCB, one or both sides, or specific areas on the rigid PCB can be covered by a
polyimide cover layer for:
extra electrical insulation
copper pattern protection from water and/or chemicals, see chapter 9.1.3.
All cover layer areas shall be described textual and graphical in the PLI document.
When the complete PCB needs to be covered on both sides, a textual indication in the PLI document is
sufficient.
In case specified areas or parts of the PCB are intended to be covered, the outline of those areas shall
be defined by the EM Engineer and exported to the EMN file for the 3D-2D interface.
Clearances of the cover layer material to other features and positioning tolerance are described in
chapter 5.3.
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Preferred Cover
layer materials
Max. Base copper
thickness (µm)
Adhesive
thickness (µm)
Kapton thickness
(µm)
FR0110*
18
25
25
FR0210
18
50
25
FR0220
18
50
50
FR0310
35
75
25
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34
When a cover layer is used at a specific area, this area shall be cleared from soldermask. A solid
soldermask figure needs to be drawn on that place.
The cover layer is not acceptable as an electrical insulator between the conductive patterns of the PCBA
and mechanical conductive hardware.
Only DuPont™ Pyralux® FR cover layer material is applied by ASML.
Preferred Pyralux FR material:
3.7 GLUE AREAS
A specific area on the PCB can be indicated as an area where glue will be applied.
Glue is intended for:
Glue areas shall be described textual and graphical in the PLI document.
Glue areas shall be drawn by the EM Engineer and exported to the EMN file for the 3D-2D interface.
Glue requires a smooth surface for fixation. Precautions can be taken to ensure a smooth underground
for the glue area:
!! In case vias are required underneath the glue area, these vias shall be filled.
All the required precautions shall be described in the PLI document.
Table 3.24 Cover layer materials
*Can only be used if the plated copper doesn’t exceed the 25µm.
Fixation of the PCBA to the mechanical surroundings
Fixation of a mechanical part
No sudden geometric changes of the underground (traces and vias).
Provide a copper area, connected to an electrical potential
Provide a route obstruct and a via obstruct (valid for traces, vias and planes)
No holes
Provide a placement obstruct (valid for electrical components)
No silkscreen
Apply a soldermask or cover layer
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3.8 PANELIZATION
Panelization will preferably be defined by the co-maker to optimize their assembly process.
Panelization is not only on Multi-board panel but also on Single-board panels which need a break-off
edge, see Figure 3-3.
Take panelization into account in PCBA design, the PCB form factor, dimensions, and materials will
influence the possibilities for panelization at the supplier. For PCBA dimensions see chapter 3.1.1:
Panelization results in cost reduction
Panelization to optimize utilization rate
Figure 3-28 Panelization example
3.8.1 BREAKAWAY TABS AND MILLING
The position and construction of the tabs is defined by the assembly company. The assembly company
will optimize the utilization rate of the production panel, because it increases risk on:
Unless breakaway tab positions are explicitly indicated in the PCB TPD. The assembly company is free
to add and locate the breakaway tabs. With taken into account design by balancing risks to damage
components. The designer must take into account the requirements for the co-maker to create an
optimal production panel balancing impact on PCBA manufacturability, material, and yield and
manufacturing costs to choose the separation method unless otherwise stated in the PCB TPD.
The remaining material at the breakaway positions, after separation from the production panel, shall fit
within the PCB dimensions as specified on the PCB TPD. Separation from the production shall be done
by a milling process.
In case areas are restricted for breakaway tabs, these areas shall be indicated in the PCB TPD.
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3.8.2 SCORING
Scoring is not allowed for the de-panelization of PCB’s or PCBA’s due to:
Loose particles
Injuries caused by sharp edges
Damage during install
Stress on components
3.9 EDGE PLATING
For certain circumstances it can be necessary to have a conductive area at the edge of a Printed Circuit
Board. Mainly the conductive edge of the PCB will be applied to define a contact area with its
mechanical surrounding.
This “edge plating” process is not a standard production process, to apply an edge plated area to the
board a Deviation Note process has to be executed. See chapter 1.2.2
A Way of Working has been added to chapter 11 of the TPD PCB (see example chapter 11.1.5 Edge
Plating) that describes the actions to be executed and additional information to be added to the PCB
TPD for correct interpretation of the required feature.
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Layers
Stackup
nr.
Non-impedance controlled
stackup
Stackup
nr.
Impedance controlled stackup
2
rgd00010
2 Layers 35μm copper
4
rgd00020
4 Layers 35µm copper
rgd00030
4 Layers 35µm copper, impedance
6
rgd00040
rgd00060
6 Layers 35µm copper
6 Layers inner 18µm, outer
35µm copper
rgd00050
rgd00070
6 Layers 35µm copper, impedance
6 Layers inner 18µm, outer 35µm copper,
impedance
8
rgd00080
rgd00100
8 Layers 35µm copper
8 Layers inner 18µm, outer
35µm copper
rgd00090
rgd00110
rgd00270
8 Layers 35µm copper, impedance
8 Layers inner 18µm, outer 35µm copper,
impedance
8 Layers 35µm copper, impedance,
Hazardous Voltage
10
rgd00120
rgd00150
10 Layers 35µm copper
10 Layers inner 18µm, outer
35µm copper
rgd00130
rgd00160
rgd00170
10 Layers 35µm copper, impedance
10 Layers inner 18µm, outer 35µm copper,
impedance Version a
10 Layers inner 18µm, outer 35µm copper,
impedance Version b
12
rgd00180
12 Layers inner 18µm, outer
35µm copper
rgd00190
rgd00190a
rgd00200
rgd00200a
12 Layers inner 18µm, outer 35µm copper,
impedance, blind & buried via Version a
12 Layers inner 18µm, outer 35µm copper,
impedance, only THT via Version a
12 Layers inner 18µm, outer 35µm copper,
impedance, blind & buried via Version b
12 Layers inner 18µm, outer 35µm copper,
impedance, only THT via Version b
14
rgd00260
14 Layers 35µm copper, impedance
(Backpanel)
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10
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12
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4 PCB STACKUP FOR RIGID PCB’S
4.1 STANDARD STACKUP
The next table shows a list of standard rigid stackups that are available. The details of these stackups
can be found in the “PCB Stackup templates Library”, see Subsidiary documents 2.5.
Stackups for flex and flex-rigid PCB’s can be found in chapter 6.4.
Table 4.1 Standard stackups for rigid PCB’s
4.2 NON-STANDARD STACKUP
A non-standard stackup needs to be discussed and investigated within the PCB Technology
Team. This process is called the “Dispensation process” as described in chapter 1.2 of this
document.
Heavy Copper, consult a PCB Expert to determine a suitable stack-up, dispensation required
High Voltage, consult a PCB Expert to determine a suitable stack-up, dispensation required
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Picture
HASL (Pb-Free)
ENIG
ENEPIG
ISn / ImSn
IAg / ImAg
Through hole
(THT)
Preferred
Yes
Yes
Yes
Yes
Surface Mount
(SMD)
Yes
Preferred
Yes
Yes
Yes
Fine Pitch
SMD
No
Preferred
Yes
Yes
Yes
Ball Grid Array
(BGA)
No
Preferred
Yes
Yes
Yes
Press-fit
Yes
Yes
Yes
Preferred
Yes
Wire Bonding
No
Yes
(1)
Yes
(1)
No
No
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4.3 PCB FINISH
An appropriate finish is selected by the PCBT expert in consultation with the supplier, based upon
reliability, cost, process and shelf life.
PCB solderable finish shall be stated in the PCB TPD.
The next table lists the most common finishes for each component type.
Only one finish is used for the whole PCBA, thus the selected finish needs to be suitable for all
component types used on the PCBA.
Table 4.2 PCB Surface Finish
(1) ENIG finish is only suitable for aluminum wire bonding. In case of gold wire bonding the finish shall be ENEPIG
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Clearance rule
Value (µm)
A: Soldermask to copper
= 50
B: Soldermask to hole edge
= 200
C: Overlapping width on covered copper
≥ 75
D: Soldermask width
≥ 75
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17
18
Tolerance
Value (µm)
Positioning tolerance of soldermask
± 25
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23
24
25
5 PCBA LAYOUT DESIGN RULES / GUIDELINES
5.1 COPPER WIDTH AND CLEARANCE RULES
PCB technology classes are defined, based upon the physical dimensions of traces and clearances on
the PCB. For an overview, see chapter 2.3.1 of this document. A detailed overview of the PCB
technology classes can be found in Appendix A .
5.2 SOLDERMASK
All contact pads, soldering pads, holes, contours and uncovered copper shall be free of soldermask
according the next clearance rules. All other copper, like copper planes and traces shall be covered with
soldermask.
Figure 5-1 Soldermask clearance rules
Table 5.1 Soldermask clearance rules
Table 5.2 Soldermask tolerance
Remarks:
Its mandatory to check
Application to fine pitch components (no soldermask to avoid paste/stenciling problems and or manufacturing
problems
Reason for understanding (slivers)
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Clearance rule
Value (µm)
Remark
A: Remaining cover layer width near board edge
≥ 500
B: SMD assembly outline to cover
≥ 500
C: SMD pads to cover
≥ 2000
D: Minimum overlap for covered features
≥ 500
E: Cover layer opening for fiducials
= 4000
= 3000
For fiducials with 1500µm copper spot
For fiducials with 1000µm copper spot
F: Cover layer opening non-plated holes
≥ 500
G: copper (Non SMD pads) to cover
≥ 500
H: Cover layer – soldermask overlap
≥ 550
Soldermask overlaps cover layer
I: Remaining cover layer dam
≥ 250
If < 250µm, remove cover in narrow
areas.
J: Overlapping width on covered copper
≥ 500
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10
Tolerance
Value (µm)
Positioning tolerance of cover layer
± 500
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5.3 COVER LAYER
Cover layer can function as a replacement for soldermask, the following clearance rules shall be taken
into account. See ref [3.17] for investigation results. If cover layer is used as replacement for
soldermask, no soldermask is needed on that place; a solid soldermask figure needs to be drawn on that
place.
Figure 5-2 Cover layer design rules
Table 5.3 Cover layer design rules
Table 5.4 Cover layer positioning tolerance
Remarks:
Avoid small narrow peaces (width < 250µm)
Its mandatory to check
Application to fine pitch components (no soldermask to avoid paste/stenciling problems and or manufacturing
problems
Reason for understanding (slivers)
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Environment
Accepted temperature rise above ambient
Cooled racks
30 ºC
Non cooled box
10 ºC
Vacuum
10 ºC
Custom
Custom value as defined in the PLI document
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9
10
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Base copper
(µm)
External layer
Standard plating (µm)
External layer
Board with Press-fit (µm)
Internal layer
(1)
(µm)
18
32
37
12
35
45
53
25
70
76
84
56
15
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17
18
19
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25
26
Field name
Required value
Unit
Current
The current for which a trace width needs to be calculated
A
Thickness
The final copper thickness as defined in Table 5.6
µm
Temperature Rise
As stated in the PLI and described in Table 5.5
ºC
Ambient Temperature
= 25 ºC (Has no influence on the calculations)
ºC
Trace length
Trace length (Optional, only required if a calculation for resistance,
voltage drop or power loss is needed)
mm
27
28
29
30
5.4 HIGH CURRENT
5.4.1 TRACES
The minimum width and thickness of traces on the PCB shall be determined primarily based on:
the maximum permissible conductor temperature rise above ambient
the current carrying capacity required
The conductor’s permissible temperature rise shall be stated in the PLI document.
Table 5.5 Accepted temperature rise above ambient
The current carrying capacity of a copper trace on a PCB is influenced by:
The final copper thickness
The final copper trace width
To calculate the safe trace width, the minimum final copper thickness shall be used:
Table 5.6 Minimum final copper thickness for trace width calculations
(1) Only for internal layers which are not start or stop layers for blind µvias or buried vias. The final minimum
copper thickness of these layers shall be 35µm.
5.4.1.1 TRACE WIDTH VS. CURRENT CALCULATION
A trace width calculator is available on the “PCB Layout & Technology Competence homepage”:
http://collaboration.asml.com/knowledge/de-pcb-layout-technology/Pages/PCB-Toolkit.aspx
For exact calculations and calculations for combinations of high current tracks, ask a PCBT expert for
support.
This calculator is based on IPC-2152 ref[3.2] and shall be used to calculate the trace widths for high
currents.
These are the fields required for a correct calculation:
Table 5.7 Trace width calculator fields
As a result, the trace width on external and internal layers is calculated, together with the resistance,
voltage drop and power loss. See also ref[3.18] and ref[3.19] for more information.
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Field name
Required value
Unit
Finished Hole
Diameter
The finished hole diameter of the via
µm
Plating Thickness
The final plating thickness in the via as defined in Table 3.17
µm
Temperature Rise
As defined in the PLI and described in Table 5.5
ºC
Via length
The total length of the via from start layer to stop layer. For through
hole vias, this equals the total PCB thickness + 10%.
(Only required if the user is interested in voltage drop, resistance or
power loss calculation results)
µm
Applied Current
Current which will be used (Optional, only required if a calculation for
resistance, voltage drop or power loss is needed)
A
Plating Resistivity
= 1.9E-6 (Fixed value for plated copper)
Ω-m
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5.4.2 VIAS
A via calculator is available on the “PCB Layout & Technology Competence homepage”:
http://collaboration.asml.com/knowledge/de-pcb-layout-technology/Pages/PCB-Toolkit.aspx.
This calculator is based on IPC-2152 ref[3.2] and shall be used to calculate the current capacity of a via.
These are the fields required for a correct calculation:
Table 5.8 Via current capacity calculator fields
As a result, the current capacity of the via is calculated, together with the resistance, voltage drop and
power loss.
5.4.3 VOLTAGE DROP
Voltage drop requirements shall be described in the PLI document.
The previous 2 calculators for trace width and vias are useful for calculating the voltage drop.
Voltage drop can be calculated if the next values are known:
Current through the trace
Length of the trace (This can be the total net length, or a defined point-to-point length)
Cross-section dimensions of the trace (Width and copper thickness)
Temperature rise and ambient temperature
Often voltage drop is a multi-board and/or cable requirement, where the PCBA only takes a small part of
the voltage drop budget.
The E-layout engineer is responsible for gathering the voltage drop information from all the layouts and
periphery and to keep track of the physical changes through the design process and succeeding
changes or revisions.
On request, the PCBL engineer can supply the necessary trace length data.
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Rule
Value
S (Thermal clearance) ≥
200µm
∑ 𝑾
(Sum of connected tie
widths and trace widths)
≤ 2mm in case of 70 µm base copper
≤ 4mm in case of 35 µm base copper
≤ 8mm in case of 18 µm base copper
Number of thermal ties
≥ 2 per pin per layer
t
Copper thickness
Table 5.9 Through hole thermal relief design rules
Figure 5-3 Hole thermal relief
16
17
18
19
20
Thermal relief: w = 200 µm, s = 200 µm
Base
copper (µm)
Spokes/Layer
Layers with
thermal reliefs
Current/spoke (A)
Current
Through
hole (A)
T
rise
(°C)
18
4 2 2.00
8.00
10
35
4 2 2.63
10.52
10
70
2 2 6.30
12.60
10
21
Thermal relief: w = 200 µm, s = 200 µm
Base
copper (µm)
Spokes/Layer
Layers with
thermal reliefs
Current/spoke (A)
Current
Through
hole (A)
T
rise
(°C)
18
4 2 3.39
13.54
30
35
4 2 4.52
18.06
30
70
2 2 11.90
23.80
30
22
5.4.4 THERMAL RELIEFS AND WIDE COPPER TRACES
Thermal reliefs shall be used on plated through holes and SMD pads that need to be soldered and which
are connected to a large amount of copper, like planes or large copper areas. The thermal relief is
required to reduce soldering dwell time by providing thermal resistance during the soldering process.
Thermal reliefs are not needed on vias, mounting holes and press-fit pins. These can be connected
without using a thermal relief (full copper connection).
To guarantee a good soldering joint and ensure possible repairing actions, some design rules are
needed when using thermal reliefs and wide copper traces. These design rules are different for plated
through holes and SMD pads.
Plated though holes
As an example a plated hole with 4 connected layers is used. One of these layers uses a wide trace
instead of a thermal relief.
Table 5.10 and Table 5.11 below give the maximum current for a 10°C and a 30°C temperature rise for
2 different base copper thicknesses. For the 18 & 35um copper thickness 4 spokes are used, for the
70um 2 spokes are used. This information can be found in ref [3.14]
Table 5.10 Maximum current for 10°C temperature rise for thermal relief
Table 5.11 Maximum current for 30°C temperature rise for thermal relief
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Rule
Value
S (Thermal clearance) ≥
200µm
∑ 𝑾
(Sum of connected tie
widths and trace widths)
≤ 30% x Circumference of pad
( ≤ 30% x (2X + 2Y) )
Number of thermal ties
≥ 2 per smd pad
Figure 5-4 SMD thermal
relief
Table 5.12 Thermal relief design rules
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23
24
25
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31
32
𝑪𝒓𝒊𝒕𝒊𝒄𝒂𝒍 𝒍𝒆𝒏𝒈𝒕𝒉 (𝒎𝒎) = 𝐓𝐫𝐢𝐬𝐞(𝐧𝐬) 𝐱 𝟑𝟎
𝑽𝒑𝒄𝒃 = 𝟏𝟓𝟎𝒎𝒎/𝐧𝐬 Delay = 7 ps/mm
SMD pads
See ref [3.14] for more information about thermal relief vs. current.
5.5 HIGH SPEED DESIGN
Special high speed design rules are needed for all critical signals on a PCB.
The PLI document shall contain a list of all the critical signals in the schematic.
A signal with its physical length larger than its electrical "critical length" shall be considered as a
transmission line. A transmission line shall be routed as a controlled impedance line (Single ended or
Differential) taking termination strategies into account.
Critical length is found using the following formula:
The propagation speed and propagation delay using FR4 PCB material with Ɛr=4.3:
5.5.1 IMPEDANCE
The PLI document shall contain a list of all the controlled impedance signals.
The board technology specification document (BTS) shall contain a list of all the calculated impedances,
together with the intended route layer and the physical dimensions to use, like the width and clearances
(in case of differential pairs). Impedances are calculated with Polar tooling SI9000 v12.05.
For standard stackups, these BTS documents are stored in the “PCB Layout technology database”, see
ref. [2.5] for more detailed information.
Two types of impedance exist:
Single ended impedance
Differential impedance
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Figure 5-5 Single ended impedance
A single conductor connects the source of one
device (A) to the load of another device (B). The
reference (ground) plane provides the signal return
path.
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7
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10
Rule
Don’t
Do
Description
Fixed trace
width, avoid
necking
The BTS shall specify the trace width per layer,
non-defined layers shall not be used for
routing. Necking the trace width can cause
reflections. If inevitable, keep the length of the
discontinuity < 20% of the signals risetime.
Avoid usage of
vias
Avoid layer changes as much as possible.
3W-Clearance
(planar)
The clearance to adjacent traces should be ≥ 3
x trace width.
Z-Clearance
(Z-direction)
Avoid crossing traces between the impedance
trace and the reference plane. If unable to
avoid, minimize the coupling area by routing
the traces perpendicular to each other
Good reference
plane
The reference plane(s) have no discontinuities
underneath the impedance traces and shall
comply to the design rules stated in chapter
5.5.2
Preserve the
return path for
layer changes
Always know where the return path will be, and
try to have an optimal return path for each
impedance signal. Return path rules are stated
in chapter 5.5.3
Correct
termination
Termination component(s) are placed correctly
and impedance matching is done before and
after the termination. Termination rules are
stated in chapter 0
11
5.5.1.1 SINGLE ENDED IMPEDANCE
What
Structures
Design rules
Figure 5-6 Single ended impedance structures
Table 5.13 Single ended impedance design rules
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Figure 5-7 Differential impedance
The lines are driven as a pair with one line
transmitting a signal waveform of the opposite
polarity to the other. Fields generated in the two
lines will tend to cancel each other, so EMI and
RFI will be lower than with the single impedance
line and problems with external noise are reduced.
3
4
5
6
7
Rule
Don’t
Do
Description
Fixed trace
width / spacing
Use the trace width and spacing as defined in
the BTS, non-defined layers shall not be used
for routing. Necking the trace width or adapting
the spacing shall be avoided. If inevitable, keep
the length of the discontinuity < 20% of the
signals risetime.
Avoid usage of
vias
Avoid layer changes as much as possible.
Equal length
Keep both traces in a differential pair equal in
length as much as possible. This to avoid EMI
problems caused by uncontrolled ground
currents in the planes. See chapter 5.5.1.3 for
allowed length differences.
Equal length is
more important
than pairing
It is allowed to obtain equal length between two
signals of a differential pair by interrupting the
pairing over a short distance. But only when no
other solution is possible. Obtain equal length
as close as possible to the source (driver),
before the traces are paired.
3S-Clearance
(planar)
The clearance to adjacent traces should be ≥ 3
* Spacing
Meander
spacing ≥ 3 x
diff-pair
spacing
The edge to edge spacing within routing
meanders should be ≥ 3 x the spacing within a
diff-pair
5.5.1.2 DIFFERENTIAL IMPEDANCE
What
Structures
Figure 5-8 Differential impedance structures
Design rules
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Rule
Don’t
Do
Description
Z-Clearance
(Z-direction)
Avoid crossing traces between the impedance
trace and the reference plane. If unable to
avoid, minimize the coupling area by routing the
traces perpendicular to each other
Good reference
plane
The reference plane(s) have no discontinuities
underneath the impedance traces and shall
comply to the design rules stated in chapter
5.5.2
Preserve the
return path for
layer changes
Always know where the return path will be, and
try to have an optimal return path for each
differential pair signal. Return path rules are
stated in chapter 5.5.3
Broadside
coupled is Not
Preferred
Edge coupled differential impedance routing
shall be used. Broadside coupled is not
preferred, can lead to impedance mismatches
because of copper positioning tolerances as
stated in chapter 3.1.3.3 Due to practical
situations misalignment between layers causes
offsets between the tracks of a broadside
coupled pair
Correct
termination
Termination component(s) are placed correctly
and impedance matching is done before and
after the termination. Termination rules are
stated in chapter 0
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7
8
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14
15
16
17
18
19
20
21
22
𝑳𝒆𝒏𝒈𝒕𝒉 𝒅𝒊𝒇𝒇𝒆𝒓𝒆𝒏𝒄𝒆 (𝒎𝒎) = 𝑻𝒓𝒊𝒔𝒆(ɳ𝒔) 𝐱 15
Table 5.14 Differential impedance design rules
5.5.1.3 LENGTH MATCHING WITHIN A DIFFERENTIAL PAIR
Equal length between both signals in a differential pair is important for two reasons:
EMC: preventing uncontrolled GND currents from flowing in the reference plane
Skew: keeping skew to a minimum
Critical diff pair signals should be analysed and adjusted if necessary. When matching the intra pair
length of the high-speed signals, add serpentine routing to match the lengths as close to the mismatched
end which has the poorest termination.
The allowed difference in length to lower the skew for differential pairs is based on 10% of the rise or fall
time (which is the fastest).
These values can be used by the PCBL engineer to prevent EMI and skew problems in the PCBA.
Timing problems are not covered, if timing could cause a problem, this has to be investigated by the
PCBA engineer and the resulting constraints shall be described in the PLI document.
5.5.1.4 LENGTH ROUTING
Length routing is used when timing of the signals or a signal bus is important and trace length
differences could lead to wrong triggering of signal levels.
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Rule
Don’t
Do
Description
Each signal
layer needs a
reference plane
Each signal layer needs an adjacent reference plane,
to prevent crosstalk and EMI problems.
Continuous
without splits
Avoid openings or via areas which create large gaps
in the plane.
No traces
allowed
Do not use reference planes for routing signal traces.
Completely
overlay all
signals
Make sure reference planes overlay completely all
signals on an adjacent layer
Use Ground
planes as
preferred
reference plane1
It is preferred to have all signal traces referred to
ground planes, not to supply planes. It is preferred to
have supply planes embedded between ground
planes.
Use the correct
reference plane
The reference plane shall belong to the circuitry and
its traces to prevent crosstalk.
Use connecting
vias
If more than 1 plane layer is used with the same
reference signal. Connect the planes together with
several vias, spread over the complete plane area.
14
15
The PCBA designer is responsible to supply the correct and complete values in the PLI document. This
document shall contain all the relevant trace length requirements, needed to achieve good timing.
Length routing can also be required between signals that are related to each other. An example can be
found in the constraints necessary to route the signals for DDR2 or DDR3 memory devices.
Figure 5-9 Length routing
5.5.2 REFERENCE PLANES
Reference planes for signals and especially for controlled impedance signals shall comply with the next
design rules:
Table 5.15 Reference plane design rules
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Pref.
Picture
Situation
Solution
1
On only one layer adjacent to
a reference plane.
No solution needed, return path
is ensured.
2
On two layers that are
adjacent to the same
reference plane.
No solution needed, return path
is ensured.
3
On two layers adjacent to two
separate reference planes of
the same type (ground or
power).
Connect the reference planes
together with vias wherever the
signal changes layers.
4
On two layers adjacent to two
separate reference planes of
different types (ground and
power).
Connect the reference planes
together with capacitors
wherever the signal changes
layers.
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25
(1) If it is inevitable to use the voltage plane as a reference instead of the ground plane, extra
precautions are needed to ensure a good return path and to prevent EMI, more information can be found
in the next chapter 5.5.3.
5.5.3 RETURN PATH
The PCBL engineer has to make sure that the return current can flow directly underneath the signal
trace on an adjacent layer, which creates the smallest loop area and prevents EMI problems.
An adequate return path is important for dynamic signals. Static signals are less important and create
less EMI problems because they do not change voltage levels often.
Static signals can be:
Identification signals
Led signals
Fixed level IO signals (IO connected to power with a series resistor)
Other signals with non-alternating, or slow alternating voltage levels
The return path should be located on a power plane, called the reference plane. Reference plane design
rules can be found in the previous chapter 5.5.2.
To preserve the return path of critical signals running from one board to another board, the used
reference planes on both boards shall be the same.
The next picture and table illustrate various situations in order of preference when routing these signals
and what needs to be done to keep the return path close to the signal when layer changes (vias) are
needed.
Table 5.16 Return path design rules
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Single ended
impedance
signals
Differential
impedance
signals
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Rule
Don’t
Do
Description
Series
termination
close to the
driver
Series termination shall be placed as close as
possible to the driver of the signal.
Parallel
termination after
the device to be
terminated
Parallel termination components shall be placed after
the device that needs termination. Exception for BGA
devices, termination on fan-out vias is acceptable.
Short distance
from device to
termination
Keep the trace lengths from device pins to
termination components as short as possible.
Maintain trace
width and
spacings
Maintain the trace width and spacing’s from device to
termination, as specified in the BTS.
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19
5.5.4 TERMINATION
What
Engineering the impedance at one or both ends of a transmission line to minimize reflections is
called terminating the line. Typically one or more resistors are added at strategic locations.
Terminations in schematic
The schematic design shall contain all required termination components. Preferable the termination
components are positioned in the schematic near the device where the termination needs to be
closest.
Termination types
Series termination = termination component(s) placed in-line with the signal
Parallel termination = termination component(s) placed between the signal and another signal or
reference voltage
Examples of termination
Table 5.17 termination examples
Design rules
Table 5.18 Termination design rules
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Stubs in layout traces are un-terminated branches on a
routed net. These stubs can be the branch to a
receiver device which is not internally terminated, or a
dead end of a trace that is unintentionally left over.
Stubs can lead to signal integrity problems caused by
unwanted reflections and signal loss.
In this example S1 should be shorter and S4 needs to
be removed.
Figure 5-10 Stubs
3
4
Rule
Description
Keep length of S1, S2 and S3
≤ 15mm*T
rise
(ns)
If stub length is smaller than 20% of rise time, reflections and
impedance mismatch are most probably negligible. But
simulation is advised to guarantee the signal integrity.
No dead-end stubs allowed
(S4)
Dead-end stubs are to be removed (also called “hangers”)
Place test-points in line with
the trace
Test-points shall not create stubs on critical signals. Place testpoints in-line with the trace, to avoid a stub.
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Figure 5-11 Star topology
Figure 5-12 Daisy-chain topology
5.5.5 STUB-LENGTH RESTRICTION
What
Design rules
Table 5.19 Stub design rules
T
for a critical signal can be found in the PLI document.
rise
5.5.6 ROUTING TOPOLOGY
What
Routing topology is only important for critical signals which have multiple loads.
When only one load is used, this is a point-to-point connection, but when multiple loads are used, the
structure or topology of the net can be more complex. The different loads can be connected using
several topology structures.
Examples of net topologies
There are many topologies available to create a signal path with multiple loads and achieve a
descent signal quality. The two most used topologies are illustrated here, other topologies our out of
the scope of this document.
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Topology
Rules
Description
Star
Length S2 = S3
Achieve equal length between the branches
Consider termination at
all loads
Termination could be needed at all the loads. The
termination design rules from chapter 0 apply.
Consider mixed
impedance
Reflections could be muted by using mixed impedances: S1
= 50Ω & S2 = S3 = 100Ω. Simulation is advised.
Daisychain
Consider termination
after the last load
Termination could be needed after the last load. The
termination design rules from chapter 0 apply.
Consider timing
Signals arrive at different points in time. Consider the timing
constraints of the devices.
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Figure 5-13 Functional blocks power planes
Figure 5-14 Functional blocks one GND plane
Figure 5-15 Functional blocks split GND plane
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Design rules
5.5.7 ANALOG / DIGITAL / OTHER
Proper placement by dividing the layout in functional blocks for (high-speed) digital circuitry, (sensitive)
analog circuitry, and power electronics is crucial to prevent SI and EMC problems.
Table 5.20 Topology design rules
It is preferred to use a continuous ground plane without splits. Functional blocks need to be placed and
routed in separate areas, then traces and return-paths of a digital part cannot influence any trace of the
analog part.
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Rules
Description
Preserve the gap
on all layers
The gap between the functional blocks needs to be
maintained through all layers (planes and signal layers)
and shall be as large as possible.
In case of one solid ground plane, this plane is the only
plane that can traverse the gap.
Connect split
ground planes only
at one point
More than one common ground connection can create
ground loops, and this increases radiation. Do not allow
one ground plane passing another ground plane to get
connected to the common ground.
The return currents
of functional
blocks should not
cross
e.g., an analog system or transmitter path must not be
in the path of the other subsystem (digital system or
receiver path). The return current should flow directly to
the common ground point.
Power planes
should only
reference their own
ground plane
They should not overlap with another ground plane.
This leads to capacitive coupling between the power
plane and a not-referenced ground plane. Noise can
couple into the other system.
Highest speed
close to connector
Locate the functional block with the highest speed
(frequency) closest to the connectors.
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Design rules:
Table 5.21 Functional block design rules (analog/digital/…)
5.6 EMC / EMI
Scope
EMI and EMC characteristics are determined by the choice of components, schematic design and
PCB layout. A must-read document has been created that covers these three aspects: GID EMC
Design Guidelines for PCBA’s, see ref[3.11]. In this chapter only do’s and don’ts for PCB layout will
be handled.
Design rules
The general guideline for reaching EMC is:
Think in closed current loops, not in voltages. Don't think in terms of ground as being waste bin that
absorbs all disturbances. Ground (or Gnd) is a reference return path through which the current
travels back to its source which is mostly not drawn in the circuit schematics.
A PCBL Engineer is spending a lot of effort in constructing the copper traces on a PCB. When the
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Rule
Don’t
Do
Description
Respect the
reference plane
design rules
See chapter 5.5.2
Respect the
return path
design rules
See chapter 5.5.3
Respect the
analog/digital/ot
her separation
design rules
See chapter 5.5.7
Respect the stub
design rules
See chapter 0
Correct
placement of
decoupling
capacitors
See chapter 7.4.6
No floating
copper planes
Avoid floating planes, as these tend to couple to
traces, and resonate at high frequencies (for one
frequency a perfect antenna). When connecting these
to ground, they help to shield instead.
Avoid sharp
corners
Avoid sharp corners. These give impedance
mismatch, which at high frequencies can radiate.
The same applies when changing routing layer(s)
Use a multi-layer
board with
planes
Use a four-layer (or more) PCB. For PCB’s containing
frequencies > 1MHz, ground planes should be used.
Use short surge
damping loops
for relay coils
Keep with relay coils snubbers/reverse diodes as
close as possible to the coil. Fly-back currents should
remain local. Keep signal and return together (paired)
and loop between diode and coil as small as possible.
Use 3Wclearance rule
for Sensitive
traces
Do not run sensitive traces in parallel with highcurrent, fast-switching signals. Use the 3W clearance
rule.
Keep op-amp
circuits short
keep input traces and feedback circuits as short as
possible
Connectors at
one side of
PCBA
It is preferred to design PCBA’s with its connectors at
one side only. Doing so, prevents common-mode
currents: Icm, flowing across the board through the
circuitry causing interference.
routing is done, only 50% of the PCB is routed. The return paths should be treated with as much
effort as the traces to achieve a 100% routed layout.
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Rule
Don’t
Do
Description
Keep radiating
areas as small
as possible
Keep radiating areas (loops, shielded areas, oscillator
circuits) as small as possible, and keep
radiating components together (example oscillators).
I/O Filtering and
I/O drivers near
connector
All I/O lines must be filtered on the PCBA near the I/O
connectors
Filtering at edge
of the functional
blocks
Always place filter components at the edge of the
functional blocks to be separated, with no traces
passing this border unfiltered.
Filter area =
keep-out area
Threat filter area’s as voids for other signals.
Use shielding
Shield sensitive traces. Connect the shield at least at
both ends to ground.
Avoid trace
loops
Avoid loops in traces, as these are in fact coils.
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Rule
Don’t
Do
Description
Avoid long
parallel traces
Avoid long parallel traces in the same layer, but also
in different layers
Route traces
perpendicular on
adjacent layers
Route signals on adjacent layers perpendicular to
each other
Table 5.22 EMC design rules
5.6.1 CROSSTALK
What
Crosstalk is the interaction between signals on two different electrical nets. The one creating
crosstalk is called an aggressor, and the one receiving it is called a victim. Often, a net is both an
aggressor and a victim.
Drivers for crosstalk
There are three factors that influence the crosstalk from an aggressor to a victim signal :
o The degree of coupling that exists between the aggressor and victim traces (determined by
parallel length, trace width and spacing)
o The rise time of the signals rising or falling edge
o The effectiveness of any trace terminations that might exist
Design rules
Knowing the drivers for crosstalk, we can formulate some basic design rules to avoid as much as
possible crosstalk problems. Remember though, there are no easy rule of thumbs or formulas to
predict the amount of crosstalk. Simulation is needed to exclude any crosstalk problems.
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Rule
Don’t
Do
Description
High-Frequency
= Use 3W
clearance rule
Use the 3W clearance rule for high frequency signals
(short T
rise
or T
fall
) like clocks.
Shield sensitive
traces
Sensitive traces need to be embedded by shielding
traces and layers. Connect the shield at least at both
ends to ground.
Use the correct
reference plane
Be sure that the reference plane, used as reference
or as signal return path, belongs with the circuitry to
which the traces refer. A non-related ground or
power plane will enhance the crosstalk between
traces independent on their separation.
No traces over
plane splits or
discontinuities
Do not route traces over splits or discontinuities in
reference planes. This creates crosstalk in the return
paths of the signals.
Use terminations
Use proper terminations if needed, see chapter 0
Simulate
Crosstalk simulation is advised to exclude any
crosstalk problems
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Option
Description
Remark
1
Preferred
Resin filled and
capped through hole
vias inside thermal
pad
Requires special PCB production process
BTS shall specify filled and capped vias
Table 5.23 Crosstalk design rules
5.7 THERMAL PADS UNDERNEATH DEVICES
The PCB layout of devices with thermal pads, requires special attention to facilitate the soldering
process and possible repair actions. Three solutions are possible:
Figure 5-16 Thermal pad layout options
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Option
Description
Remark
2
Non-preferred
Standard through
hole vias outside
thermal pad
Bad thermal performance
Lowest cost and standard assembly and repair process
Not suitable for packages with pads on 4 sides of the
device (quad packages)
Add soldermask outside the thermal pad
3
Avoid
Blind copper filled
µvias inside thermal
pad
Expensive, requires special PCB production process and
one additional drill process (buried vias)
Not allowed if microvias are not yet used in the layout
Preferred if microvias are already used in the layout
BTS shall specify filled and capped vias
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Rule
Don’t
Do
Description
Miter all trace
corners
Miter all 90 degree trace corners with 45 degrees
Prevent
tombstoning,
1:2 rule
Make sure that the copper width connected to one
side of a 2-pins device is equal to the other side. The
deviation ratio shall not exceed 1:2. This is required
for devices ≤ 1206 imperial package size.
Vias centered
between BGA
pads
Place vias centered between the four surrounding
BGA pads
Preserve planes
between BGA
pads
Make sure all planes can protrude between the vias
used for the fan-out of a BGA device
Prevent acid
traps
Prevent angles ≤ 90º between copper features
Ensure pad exit routing starts bending after a
distance D ≥ minimum trace width
Prevent slivers
Ensure spacing between copper features
S ≥ minimum trace spacing
Trace width ≤
SMD pad width
The trace width used for exiting a SMD pad
W ≤ pad width on that side of the SMD pad
Table 5.24 Thermal pad layout options
5.8 ROUTING DO’S AND DON’TS
Good PCB layout practice requires some do’s and don’ts for layout. A lot of do’s and don’ts are already
discussed in previous chapters 5.5 and 5.6. In this chapter the standard routing do’s and don’ts are
handled. These are only guidelines and no hard rules. Every situation can require some tweaking of
these guidelines, using common sequense.
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Rule
Don’t
Do
Description
Prevent offset
traces on SMD
pads
Prevent traces from exiting SMD pads offset and
protruding the SMD pad edge
Prevent shortcircuit like
traces between
IC smd pads
These tracks look like an erroneous short-circuit and
should be avoided to prevent confusion during the
visual inspection of the PCBA.
Prevent traces
from protruding
beyond the pad
boundary
These tracks enlarge the soldering pad and can lead
to undesired soldering bridges between solder pads.
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Figure 5-17 Copper balancing dimensions and build-up
Rule
Value
X: Offset
1700 µm
C: Clearance
≥ 1000 µm
D: Distance
2400 µm
W: Width
1000 µm
Shape
Circle
% Fill ratio
13%
Table 5.26 Copper balancing
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Figure 5-18 Text dimensions
Rule
Copper text
Silkscreen text
Font
VeriBest Gerber 0
VeriBest Gerber 0
H: Height
≥ 10 x W
≥ 1.25mm
W: Line width
≥ Minimum trace width
(1)
= H / 10
S: Spacing
≥ Minimum spacing
(1)
≥ H / 10
Table 5.27 Copper text dimensions
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Table 5.25 Routing do’s and don’ts
5.9 COPPER BALANCING
Copper balancing shall be used on all layers which are not completely filled with copper planes.
Copper balancing shall be applied in a staggered pattern between adjacent layers. See ref[3.6] for
influence of copper balancing on PCB’s on cross-talk and capacitive loading.
When High- or Hazardous voltages are used, the clearance “C” shall comply to additional clearance
rules as stated in chapter 8.
5.10 TEXT
For identification or information purpose, text can be added to the PCB as silkscreen or copper.
Dimensions:
All text dimensions are bound to some rules:
(1) Minimum trace width and spacing is according the selected PCB technology class as defined in
chapter 2.3.1.
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Figure 5-19 Silkscreen
clearance
Rule
Value
C: Spacing silkscreen to soldermask or
cover layer edge
≥ 300 µm
Silkscreen shall be visible after assembly of
the components.
Silkscreen is not allowed on uncovered
copper.
Table 5.28 Silkscreen clearance rule
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Copper Thickness Outer / Inner Layer
(Units = µm)
@70
@105
@140
@210
@400
Min. Trace width / Spacing
200 / 200
250 / 250
300 / 300
500 / 500
900 / 900
Min. finished through hole via
500
500
500
1000
1000
Min. via pad Outer / Inner layer
1000/1000
1000/1000
1000/1000
2400/2400
2400/2400
Min. Clearance contours & NPTH
750
750
1000
1000
1000
Clearance to board outline
Min. / Standard
500/750
500/750
500/1000
500/1000
500/1000
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Available Heavy Copper Thickness
Copper thickness (Oz)
Copper thickness (µm)
6
210
8
280
10
350
12
420
14
490
20
Clearances:
Copper text shall respect the clearance rules as specified in the PCB technology class, chapter 2.3.1.
Silkscreen text shall respect the clearance rules as in the next picture and table :
5.11 HEAVY COPPER
Some additional design rules are required, ref[3.13]:
Table 5.29 Heavy Copper, Trace, Clearance & Via requirements
Max base copper thickness 400µm.
Prefer less thick copper layers (400µm) instead of multiple thinner copper foils (200µm).
Always consult a PCB Expert for guidance regarding design, production and stackup definition.
Dispensation required
For High Voltage applications see chapter 8
Max heavy copper layers of 12Oz = 4
Max. PCB thickness 6mm
Available Heavy Copper thicknesses
Table 5.30 Available heavy copper thicknesses
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Flexible part:
the part of the stackup that is constructed with flexible
PCB (polyimide) material only.
Rigid part:
the part of the stackup that is constructed with rigid and
flexible PCB material.
Transition area:
part of the stackup where the flex-rigid area transfers
into the flexible part
Bendable area:
the area of the flexible part that is intended to bend in
the application.
= Bendable area
= Flexible part
= Rigid part
= Transition area
= copper pattern
Bendable area
Bendable area
Flexible part
Rigid part
Transition area
UnfoldedTop View
Side View as in application
Transition area
6 FLEX / FLEX-RIGID
6.1 DEFINITIONS
6.1.1 LEGEND
Throughout this chapter the following colors will be used to indicate specific parts or features of the flex
and flex-rigid construction:
Figure 6-1 Legend
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10
Item
All assembly
processes available
Limited Assembly
processes available
Press-fit
No assembly
process
Flex only
480 x 400 mm
600 x 500 mm
Prohibited
560 x 864 mm
(1)
Flex-Rigid
480 x 400 mm
600 x 500 mm
560 x 864 mm
(1)
560 x 864 mm
(1)
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6.1.2 FLEX APPLICATION DEFINITION
Static flex
Flex to install
Dynamic flex
Figure 6-2 Flex definition
6.2 MECHANICS
6.2.1 BOARD DIMENSIONS
Table 6.1 Maximum flex and flex-rigid board (design) dimensions
Remark:
(1) Maximum board design dimensions due to available flex material size.
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Rigid
Flex
H
L
6.2.2 ROBUSTNESS
6.2.2.1 TEAR PROTECTION
To increase the robustness and mechanical lifetime of the flexible area, rounded corners shall be applied
to the flex. It’s preferred to provide the rigid part with rounded corners as well, due to handling in the
cleanroom.
Figure 6-3 Rounded corners flex and flex-rigids
6.2.2.2 STRAIN RELIEF
To prevent the flex from tearing at the transition area a so-called strain relief shall be added at the flexrigid transition areas. The need for this strain relief is indicated in the PCB TPD by the “Manufacturing
Specification”. The strain relief will be added by the PCB manufacturer according the “Manufacturing
Specification” (subsidiary documents 2.7) with the following requirements:
Figure 6-4 Strain relief
L = 2H ± H
Strain relief shall not encroach the rigid surface
Use specified material(s)
The following materials are allowed to use. It is not allowed to use different materials from the list below without
written authorization of ASML.
Eccobond® 45 Clear / Catalyst 15 LV Clear (mix ratio 100 / 100)
3M™ - Scotchweld™ 2216 B/A Grey (mix ratio is described in the data sheet)
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6.2.2.3 FLEX AND FLEX-RIGID GEOMETRIC ARCHITECTURE
The transition areas are vulnerable areas during the flex-rigid production and during the lifetime of the
flex-rigid PCB. The following design rules shall be applied during the mechanical design phase and
during the PCB layout design phase.
Figure 6-5 Flex and flex-rigid geometric constraints / requirements
Figure 6-6 Flex and flex-rigid copper pattern requirements
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Transition area
No holes allowed (vias, component- or mountingholes)
No geometric copper changes (flexible layers)
No copper direction changes (flexible layers)
Preferred Perpendicular crossing of copper pattern
If planes are cross-hatched on Flex parts, make the planes at the transition area as full copper
plane.
Rigid part
Can be considered as a rigid PCB
Route border can be used as placement area for components
Flexible part
No vias
No plated holes
No non-plated mounting holes (exceptions see table 6.3)
No components
No silkscreen (Prohibited)
No uncovered conductive pattern
No Logos: UL, Vendor and RoHs
Copper pattern shall follow outline geometry
Copper pattern preferred to be equally divided over flex area
Copper pattern shall cross the bendable area perpendicular
Prevent geometric changes of the copper pattern
Prevent dimensional changes of the copper pattern
Outer contour shall follow a tangent shape
Flex contour shall enter the rigid part perpendicular
Bendable area minimum 1.5 mm from transition area
3
4
5
6
7
Figure 6-7 Flex-rigid cross-hatch plane requirements at transition area
Table 6.2 Flex and flex-rigid geometric and copper pattern constraints / requirements
The bendable areas as indicated in Figure 6-5 are the areas of the flex that are intended for flex cycles
and/or direction changes (bend radii) of the flex. The other flex area is intended for low flex cycles or flex
to install only.
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Item
Acceptable
Acceptable
Prohibited
Prohibited
Non plated hole
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6.2.3 NON-PLATED HOLES IN FLEXIBLE AREA
Non-plated holes for mounting purposes in the flexible area are prohibited. In case a non-plated hole in
the flexible area, for mounting purposes, is inevitable a stiffener should be applied such that local
wrecking of the flex is avoided. See also chapter 6.5 Stiffeners.
Non-plated holes for alignment, guiding or tooling purposes in the flexible area should be avoided.
Non-plated holes for alignment, guiding or tooling purposes in the bend area are prohibited. In case a
non-plated hole in the flexible area is inevitable the hole size should be defined such that no stress will
be induced by a mechanical part or wrecking of the flex occurs.
Table 6.3 Non-plated holes in flexible area
6.2.4 CONTOURS IN FLEXIBLE AREA
Plated contours are prohibited in the flexible area.
Non-plated contours are allowed and should be considered as a flex-outline contour (tolerances). The
minimum inner radius of the contour is 0.5 mm. The contour shall follow the outline geometry of the
flexible area.
Figure 6-8 Non-plated contour in flexible area
6.2.5 BENDING RADIUS
By bending the flexible area of a flex or flex-rigid a certain amount of stress will be induced on the copper
and flexible layers. The amount of induced stress depends on the layer stackup, amount of copper and
the bend radius and copper pattern distribution. The induced stress strongly influences the lifetime and
amount of flex cycles of the flex or flex-rigid construction.
To determine the amount of stress induced and the amount of expected flex cycles to fatigue, the
Bending Radius Calculator shall be used. The bending radius calculator is available on the EDS PCB
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Technology Competence internet site: Bending Radius Calculator.
The bend radius the flex will experience, is not by definition the bend radius as defined in the mechanical
CAD software. Take mechanical strokes of the relative motion into account, which may not be modelled
in CAD. When the bend radius is defined without a mandrel the minimum bend radius will be defined by
its natural bend shape. This bend radius, formed by its natural shape, is the one to calculate with. The
Bending Radius Calculator will list 19 (definable) bendradii with its induced stress and predicted bend
cycle to fatigue. For a dynamic flex calculation contact a PCBT expert.
Figure 6-9 Screenshot Bending Radius Calculator.
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Item
Preferred
Acceptable
Non preferred
Prohibited
Direction
changes
Geometric
changes
Pattern
distribution
Pattern
distribution
Current carrying
pattern
Cross sectional
routing
(flexibility)
4 and 6 layer
example
*
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Item
Preferred
Acceptable
Non preferred
Prohibited
2 layer
construction
(1)
3 layer
construction
4 layer
construction
(1)
(2)
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6.3 LAYOUT
6.3.1 SIGNAL ROUTING
Table 6.4 Signal routing
* Offset in practical examples
6.3.2 CONTROLLED IMPEDANCE ROUTING
Table 6.5 Controlled Impedance routing
Remark:
(1) The preferred routing construction, applied as an interconnect structure in a chain, needs extra
precautions at the beginning and end of the interconnect chain. Please contact the EMC team for details.
(2) Offset in practical examples, which influences the impedance
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6.3.3 HATCHED AND FULL PLANE REFERENCE
From Signal Integrity point of view it is desirable to have a continuous (geometric equal) return path
underneath or on top of the signal path. Regarding a plane construction a full plane as reference is
preferred; from dynamic point of view it is advisable to hatch the reference plane (when the reference
plane is not positioned at the neutral axis of the flex construction). Depending on the signal bitrate a
hatched reference plane is acceptable without noticeable performance loss.
The hatched plane pattern needs to be calculated and depends on the differential pair dimensions. The
hatch pattern shall be generated with a 45 degrees angle.
Figure 6-10 Preferred hatch pattern calculation
The hatch trace width shall be equal to the signal trace width.
The hatch pitch must be defined such that the gap of the hatch is larger than or equal to the
minimum clearance as specified in the PCB technology class.
The (X and Y) position of the differential pair in respect to the (hatched) reference plane determines the
bitrate, the construction is suitable for.
The differential pairs need to be conscientious routed in respect of the hatch pattern. Such that an even
amount and surface area of “crossings” are applicable at the two signals within a pair and pair to pair. In
case of an inevitable layout direction change, the differential pairs need to be routed with 45° such that
the parallel line of the hatched copper is located in the center between the signals of the differential pair.
For more information about the use of hatch planes, see the topology study in ref[3.16]
The impedance can be calculated with the Polar tooling SI9000 v12.05.
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Example values:
S = 125 µm
W = 175 µm
Hatch pitch = 424.26 µm
Differential pair routing
Suitable bitrate f
max
Preferred
~3.0 Gb/s (T
rise
≈100ps)
Acceptable
~1.8 Gb/s (T
rise
≈166ps)
Acceptable
~1.5 Gb/s (T
rise
≈200ps)
1
2
Table 6.6 Hatched reference plane application
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Flex
Layers
Stackup
Nr.
Non-impedance controlled
stackup
Stackup
Nr.
Impedance controlled stackup
1
flr00010
flr00020
1 flex layer, 2 rigid layer 18µm Cu
1 flex layer, 2 rigid layer 35µm Cu
2
flr00030
flr00040
2 flex layer, 2 rigid layer 18µm Cu
2 flex layer, 2 rigid layer 35µm Cu
3
flr00070
flr00080
3 flex layer, 2 rigid layer 18µm Cu
3 flex layer, 2 rigid layer 35µm Cu
flr00050
flr00060
3 flex layer, 2 rigid layer 18µm Cu
hatched plane
3 flex layer, 2 rigid layer 18µm Cu
full plane
4
flr00110
flr00120
4 flex layer, 2 rigid layer 18µm Cu
4 flex layer, 2 rigid layer 35µm Cu
flr00090
flr00100
4 flex layer, 2 rigid layer 18µm Cu
full plane
4 flex layer, 2 rigid layer 18µm Cu
hatched plane
5
flr00140
flr00150
5 flex layer, 2 rigid layer 18µm Cu
5 flex layer, 2 rigid layer 35µm Cu
flr00130
5 flex layer, 2 rigid layer 18µm Cu
full/cross hatch plane
6
flr00160
6 flex layer, 2 rigid layer 18µm Cu
8
flr00170
2 x 4 flex layer, 2 rigid layer
18/35µm Cu
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6.4 STACKUP
6.4.1 STANDARD STACK-UP
The next table shows a list of standard flex- rigid stackups that are available. These standard stackups
are based on the numbers of flex layers. Total Number of layers can change. This list and the details of
those stackups can be found in the “PCB Stackup templates Library”, see subsidiary documents 2.5
Table 6.7 Flex-rigid stackups
6.4.2 NON-STANDARD STACKUP
A non-standard stackup needs to be discussed and investigated within the PCB Technology Team. This
process is called the “Dispensation process” as described in chapter 1.2 of this document.
6.4.3 FLEXIBLE LAYER COUNT
With the standard flex-rigid stackups the flexible layer count is maximized by 6 flex layers bonded
together. The maximum allowed flexible layers within a flex-rigid is 8 layers.
The 8 flexible layer stackup is split in two sets of 4 flex layers. Those two sets are not bonded together
and should be considered as a four layer flex stack.
When more than 8 flexible layers are needed contact a PCBT expert for a non-standard flex-rigid
stackup and design- and material requirements suitable for the application.
A flexible layer count larger than 6 is not suitable for a 90 degrees bend direction and shall be applied in
an S-curve construction only.
Figure 6-11 Maximum flexible layer count constructions
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6.4.4 BOOKBINDER CONSTRUCTION
A bookbinder construction with different lengths of bonded flexible areas to be suited in a 90 degree
bend construction is prohibited.
6.4.5 STANDARD VERSUS MULTI LEVEL FLEX-RIGID CONSTRUCTION
The flexible layers in a flex-rigid construction will be evenly distributed in the stackup. A split level rigid
surface area can be designed in case of volume requirements. Depending on the surface level of the
rigid part, the rigid parts can be assembled with components or only used for mounting purposes.
Contact the PCBT expert for detailed information. The areas of the split leveled rigid surfaces should be
indicated as no glued/bonded areas in the PCB TPD.
Figure 6-12 Prohibited bookbinder construction
Figure 6-13 Standard level rigid surface areas
Figure 6-14 Split level rigid surface areas
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Flex with polyimide and FR4 stiffener
Flex with FR4 stiffener
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Placement
level
FR4
stiffener
Polyimide
stiffener
Metal
(1)
stiffener
Adhesion type
Placement
tolerance
Outline tol. i.r.o.
flex outline
PCBA
ok
ok
ok
Pressure
Sensitive
Adhesive
± 0.20 mm (with
alignment pins)
± 0.40 mm
Double-sided
adhesive tape
± 0.50 mm (without
alignment pins)
± 0.70 mm (without
alignment pins)
PCB
ok
ok
specials
Thermoset
(PCB pressprocess)
N/A
Equal to board
outline
Pressure
Sensitive
Adhesive
N/A
Equal to board
outline
Double-sided
adhesive tape
± 0.20 mm (with
alignment pins)
± 0.40 mm
Thickness
tolerance
of stiffener
Part of total
stack-up +/-
10%
Part of total
stack-up +/-
10%
± 0.05
Available
thickness
(mm)
0.25 - 0.50 -
0.80 - 1.00 -
1.20 - 1.60 -
2.00 - 2.40 -
3.20
0.025 mm
0.050 mm
0.075 mm
0.125 mm
N/A
6.5 STIFFENERS
A Stiffener is a non-patterned, read no copper, FR4, polyimide, plastic or metal part that functions as a
local strengthening placed onto the flexible PCB. The stiffener is used for applications that require
support in areas where connectors or other components are applied on the flex or as support for
mounting areas or handling. The stiffener is an inexpensive option for rigidizing the flexible PCB
compared to a flex-rigid construction and is in fact a cost reduction related item.
Every design where a stiffener is used shall be discussed with the PCBA and/or PCB manufacturer to
define the best approach for assembly method, adhesion material, costs and the tolerances that can be
reached. Depending on the outcome of this discussion, the stiffener(s) will be placed at PCB or PCA
level. Different tolerances apply, depending on which (production) level the stiffener will be applied.
Table 6.8 Stiffener tolerances
Remark: (1) The metal stiffener is hardly processed by the PCB manufacturer. This is a non-standard
The tolerances from this table shall be used to determine the actual hole diameter in the stiffener while
the hole sizes depends on the assembly method. When the stiffener will be placed at PCB production
level, the stiffener areas shall be indicated in the PCB TPD. The stiffener and its holes shall be drawn
and dimensioned in the PCB TPD.
Figure 6-15 Examples of stiffeners applied to the flexible PCB.
process and the materials are not standard available. When a metal stiffener is required, it is
recommended to consider this as a component to be applied on PCBA level.
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Flex-rigid with FR4 and metal stiffener
6.5.1 STIFFENERS USED FOR PCB THICKNESS OR STRENGTH INCREASE
When a stiffener is used to increase locally the thickness of the (rigid) PCB, the stiffener shall be applied
by the PCA manufacturer and shall be considered as a component and part of the PCA assembly. The
stiffener shall be placed after the applied component solder process(es).
6.6 FIDUCIALS
Additional to the global fiducials as described in the rigid PCB section, 2 extra (component) fiducials
have to be placed on each rigid part of the flex-rigid at the sides where components are placed. The
fiducials have to be placed diagonal. Also 1 fiducial has to been placed on each rigid part on the noncomponent side. See chapter 7.3 for more information about fiducials.
Figure 6-16 Example of stiffeners applied to the rigid PCB.
Figure 6-17 Additional (component) fiducial placement
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Figure 7-1 Fiducial
Soldermask (standard in library)
Item
Size 1 (µm)
(Preferred)
Size 2 (µm)
A: copper spot
1500
1000
B: soldermask opening
3000
2000
C: Placement, trace and via obstruct
3200
2200
Table 7.1 Fiducial dimensions when soldermask is used
Cover (not standard in library)
Item
Size 1 (µm)
(Preferred)
Size 2 (µm)
A: copper spot
1500
1000
B: Cover layer opening
4000
3000
C: Placement, trace and via obstruct
5000
4000
Table 7.2 Fiducial dimensions when cover layer is used
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7 COMPONENT PLACEMENT DESIGN RULES AND GUIDELINES
This chapter is valid for all kind of products (Rigid, flex and flex-rigid boards)
7.1 KEEP-OUT AREA
As specified in chapter 3.1.1, Figure 3-2, a free component area of 5mm on two opposite parallel sides
of the PCBA shall be provided to facilitate the assembly processes.
If this is not possible, the PCBA manufacturer will add break-off edges, as specified in chapter 3.1.1,
Figure 3-3.
When press-fit components are used, additional keep-out areas are needed, see chapter7.4.4.
7.2 REFERENCE HOLES
Reference holes and positioning rules are discussed in chapter 3.2.6.
7.3 FIDUCIALS
Fiducials shall be placed by the PCBL engineer.
Two types of fiducials are in use within ASML:
Board or global fiducials
Component or local fiducials
For each type two sizes are available. The available sizes are:
General fiducial requirement:
Always use one size for all board/global and component/local fiducials on a PCB.
Place always fiducials on top and bottom, also if there are non-components on one side. This is
because of:
Separating the board from the production panel is done by vision guided milling,. This
process needs fiducial marks at both sides, to guarantee freedom of choice with regard to
the orientation of the panel.
When globtop coating, a vision system uses fiducials at the opposite side.
Flying probe test.
Additional local fiducials may be used by the placement machine vision system to increase
placement accuracy where necessary, e.g. for BGA's and for accurate placement of fine pitch
devices (≤0.65 mm) and small chip components.
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Placement
dimensions
Center of fiducial, minimum 5.75mm
from each PCB edge
Number of
fiducials on
each side ?
Three fiducials (Preferred)
Two fiducials diagonal placed over
the longest side (At least)
Cover all SMD
The rectangular area formed by the
fiducials should cover all SMD
components
Fiducials under
components
Placement of fiducials under
components is possible, but should be
avoided. This fiducials can only be
used for placement.
Copper under
fiducial
Try to add full – or no copper on the
first inner layer under the fiducial. Do
not add several traces on the first inner
layer under the fiducial, because this
influences the contrast between the
fiducial itself and its immediate
surroundings.
24
Add a minimum of two local fiducials to cover approximately 100mm x 100mm areas on the PCB.
Local fiducials for individual components are not required.
The component fiducial appearance is similar to that of board fiducials.
Component fiducials shall be placed diagonal over the component area, in close proximity to the
component.
Fiducials can be shared between components.
For stencil prints, component side.
3D inspection component side.
AOI/AXI.
Selective wave soldering, top and bottom side.
Automatic supply of chemicals during production processes.
Fiducials can be placed outside the board, in case of space limitations and in consultation with the
supplier.
Cover layer openings for fiducials are no problem regarding moisture.
Fiducials will get a finish as well (eg. ENIG,…)
7.3.1 BOARD OR GLOBAL FIDUCIALS
Fiducials used for the main positioning of the components and process calibration.
Board or global fiducials are required on both sides of the PCBA, for alignment purposes during the
assembly process.
Board or global fiducial names available for PCB layout:
Size 1: Fiducial Global 1.50 M3.00
Size 2: Fiducial Global 1.00 M2.00
Placement design rules:
Table 7.3 Board or global fiducials placement
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Placement
Diagonal over the component, in close distance to the
component
Number of
fiducials
Two fiducials.
Fiducials can be shared
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Remark:
7.3.2 COMPONENT OR LOCAL FIDUCIALS
Component or local fiducials shall be provided when BGA’s are used.
Component or local fiducial names available for PCB layout:
Placement design rules:
When there is absolutely not sufficient room for fiducials, they can be omitted. The PCBA manufacturer
can be instructed by the PCBL engineer to place the fiducials in the break off edges around the PCB.
This situation should be avoided, because it makes repair and testing difficult.
Size 1: Fiducial Local 1.50 M3.00
Size 2: Fiducial Local 1.00 M2.00
Table 7.4 Component or local fiducials placement
7.4 PLACEMENT RULES / GUIDELINES
7.4.1 COMPONENT PLACEMENT OUTLINE
The component placement outline is an additional obstruct area around the component body and leads,
available in the PCB library for each component. This obstruct area provides sufficient room for the
component and assembly process tolerances and is dimensioned as displayed in the next picture.
Figure 7-2 Placement outline
7.4.2 BGA REPAIR AREA
BGA components need a larger free component area then the standard component placement outline as
discussed in chapter 7.4.1. This larger free component area is included in the placement outline in the
component.
This larger area is required for accommodating the possible repair actions after assembly.
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Figure 7-3 Repair area
Remarks:
Fiducials and testpoints for In-circuit-test or flying-probe-test (chapter 10) are allowed in this repair area.
No components shall be placed in this area. When small SMD components, like resistors and capacitors
are required within this area, this shall be discussed with the PCBT expert.
7.4.3 HIGH AND LARGE COMPONENTS
Do not place high and large SMD components close to each other. This to prevent reflow soldering
problems, caused by bad heat spread underneath these components.
Always asked the PCB technology Expert about what design ruled should be applied, since these are
defined by various items as there are:
What is the material of the component (metal or plastic).
The connected quantity of copper.
Where are the leads (under or along the component).
H ≥ 5mm, X ≥ 2mm.
Figure 7-4 High / Low components
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Design rule
Description
Picture
Edge clearance ≥ 7mm
(1)
The PCB edges perpendicular to the
component axis, need to be free of
components for 7mm
Component clearance ≥ 2mm
2mm area free of components is required
around the body of the press-fit
component
Opposite side clearance ≥
2mm, preferred 3mm
2mm (preferred 3mm) area free of
components is required on the opposite
side of the press-fit component, around
the side of the press-fit holes
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Guideline
Don’t
Do
Description
Distribute hot devices
on the board surface
Spread the heat by placing hot
devices far away from each
other.
If press-fit assembly technology is used => PCB thickness ≥ 1.6mm
7.4.4 PRESS-FIT
When press-fit connectors are used, additional keep-out areas are required for the special press-fit
tooling. Design rules for press-fit components:
Table 7.5 Press-fit placement design rules
(1) If this clearance is not achievable, the PCBA manufacturer will add break-off edges to ensure this 7mm
clearance.
7.4.5 HEAT MANAGEMENT
Components which need special attention regarding thermal aspects shall be listed and described in the
PLI document. If special precautions are needed, some guidelines are described in the next table:
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Guideline
Don’t
Do
Description
Place hot devices
parallel to the air flow
and ensure a good
airflow
If airflow is used, place the
devices parallel to the airflow.
This to prevent one hot device
warming up the other. Do not
place high components in
front of hot devices,
Place temperature
sensors near hot
devices and if airflow
is used, behind the
hot device
The senor needs to measure
the temperature at the hottest
place near the device.
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Don’t
Do
= GND, = Supply
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Table 7.6 Heat management guidelines
7.4.6 DECOUPLING
General design guideline:
Keep the impedance from decoupling capacitor to the IC supply terminal as small as possible.
This can be achieved by using wide and short traces.
Keep the closed loop area of the decoupling circuit as small as possible. This area is formed by
the supply line and the return line, and becomes short by placing the decoupling close to the
supply terminal and placing the vias to supply- and GND-plane close to each other.
Try to keep the decoupling circuit on the same side as the IC. For BGA’s however this is not
possible.
If a combination of capacitors is used, always place the smallest capacitance value closest to the
supply terminal.
7.4.6.1 DECOUPLING OF IC’S
Table 7.7 Decoupling of IC’s
Design guidelines:
Place vias as short as possible to the decoupling capacitor
Keep traces as short and as wide as possible
If a combination of capacitors with different values is used, always place the capacitors in order
of magnitude close to the supply pin, from lowest (=closest) to highest (=furthest) capacitance
value.
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Don’t
Do
= GND, = Supply
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Figure 7-5 Dot nr. Resistors in schematic
Figure 7-6 Dot nr. resistors on PCB
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7.4.6.2 DECOUPLING OF BGA’S
Table 7.8 Decoupling of BGA’s
Design guidelines:
Place the decoupling capacitor as close as possible to the BGA supply pin which need
decoupling. This results in the capacitor to be placed on the opposite side of the PCB
Keep traces as short and as wide as possible
If a combination of capacitors with different values is used, always place the capacitors in order
of magnitude close to the supply pin, from lowest (=closest) to highest (=furthest) capacitance
value.
7.4.7 DOT NUMBER RESISTORS
Dot number resistors are used for the electronic identification of the board.
These resisters shall be indicated in the PLI document
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Design rules
Description
Equal resistance values on the same PCB side
Place all resistors with the same resistance value
on the same side (Top or Bottom) of the PCB
Respect the dot order for the placement
Each resistor or combination of resistors,
represents a dot number. This numerical order
shall be respected (2, 3, …. 9) and placement of
the resistors shall be in this order.
Add identification text
Add identification text of the bits next to the
resistors. This can be silkscreen or copper text,
depending on the requirements in the PLI.
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Design rules for Dot number resistors:
Table 7.9 Dot number resistor design rules
7.4.8 POLARIZED COMPONENTS
Polarized components with the same orientation should be placed in the same direction. This facilitates
the inspection of the PCBA after production and minimizes possible errors.
Figure 7-7 Orientation of polarized components
7.4.9 PART SPREADING
To speed up the time it takes to assemble a board, it is important to pay attention to the part spread of
the PCBA.
If a certain part is used several times on one side of the board, the PCBL engineer should prevent using
the same part in a small quantity on the other side of the PCBA. Try to place equal parts on the same
side of the PCBA.
Figure 7-8 Optimize part spread
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Design rule
Picture
≥ 7mm rectangular area free of components, and pads
around the center of through hole pins
(1)
Spacing between pads of through hole pins ≥ 0.6mm
H: Component height at the selective wave side ≤ 15mm
Area free of components : Adjacent components that
exceed 11 mm height, there must be a free space that is
equal to that height
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7.5 SOLDERING
The different components with the soldering methods are discussed in Table 2.2 .
If selective wave soldering is required, additional design rules shall be used.
7.5.1 SELECTIVE WAVE SOLDERING
Table 7.10 Selective wave soldering design rules
(1) This area can be smaller in some special situations. To know the limits for a specific application,
contact a PCBT expert.
7.5.2 PIN IN PASTE
Pin in Paste (PiP) is a solder process where a through-hole component (leaded component) is soldered
to the PCB by applying a traditional reflow process instead of an additional manual-, wave- or selective
wave process. (PiP is only applicable when there are a few or just one leaded component while all other
components requires a reflow solder process)
By applying the PiP solder technology, extra attention is required for the solder paste mask definition and
component placement around the PiP component. The amount of required solder paste (mm3) to fill the
component holes has to be available on the PCB board at the connector terminals prior to the reflow
solder process. The amount of solder paste is way larger than with reflow components, this means that
more space has to be reserved around the connector pads.
Recommendation: The designer should gather “full information” before starting PIP design and consult a
e PCBT Expert.
7.5.2.1 PASTE MASK
The amount of required solder paste can be calculated with the Pin in Paste calculation tool D000415044. The tool
calculates the opening of the paste film based on the paste stencil thickness, component terminal diameter and the
pad-size. The opening can be round, square, rectangle or any arbitrary shape, as long as the surface of the
opening is equivalent to the calculated value.
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2
Design rule
Remark
Vias and µvias are not allowed in the
bonding pad
Bonding pad shall be free of
soldermask and solder paste
This to allow bonding and prevent contaminated bonding
pads.
Bonding pad ≠ testable pad
Bonding pads shall not be used for ICT or FP test. This
means a testpad shall be added by the EL-layout engineer
to ensure possible electrical or performance tests.
No crossings between bonding wires
allowed
Placement area
The bonding equipment used by the supplier to create the
bonding’s, needs space to move and place the wire bond.
3
4
Pristine area:
The pristine area is the actual area to bond the wire
on. Be sure that the required bondable area or
required pad dimensions, which is given by the
wire bond supplier, is at least the pristine area.
Contact pad calculation:
Cu < 35µm*
A = Contact pad width = Pristine width x
B = Contact pad length = Pristine length x
Cu ≥ 35µm*
A = Contact pad width = Pristine width x
B = Contact pad length = Pristine length x
Figure 7-9 Bonding pad size
5
Description
A
Nominal width of the master drawing (=IPC-6012D (ref[3.3]) “Minimum Conductor Width”)
A’
80% of A conform IPC-6012D (ref[3.3]), but 100% conform ref[2.7], A’ = A
B
Nominal length of the master drawing (=IPC-6012D (ref[3.3]) “Minimum Conductor Length”)
B’
80% of B conform IPC-6012D (ref[3.3]), but 100% conform ref[2.7], B’ = B
C
Process tolerances 90% width of A’ @ Cu < 35µm
Process tolerances 80% width of A’ @ Cu ≥ 35µm
D
Process tolerances 90% length of B’ @ Cu < 35µm
Process tolerances 80% length of B’ @ Cu ≥ 35µm
E
80% of C, Pristine width conform IPC-A-600J (ref[3.5])
F
80% of D, Pristine length conform IPC-A-600J (ref[3.5])
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1 0
0.8 x 0.9
1 0
0.8 x 0.9
1 0
0.8 x 0.8
1 0
0.8 x 0.8
7.6 WIRE BONDING
7.6.1 DESIGN RULES
Table 7.11 Wire bonding design rules
7.6.2 BONDING PAD SIZE
Table 7.12 Bonding pad size
Note: * Cu thickness indicated is the base copper thickness.
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Precaution
Description
Remark on sheet 110
When bonding pads are applied in a design, this
must be stated on the board specification tab of
sheet 110 of the PCB-TPD
Wire bond location indication in the PCB-TPD
The location of the bonding pads on the PCBA,
shall be clearly indicated in the PCB-TPD
Board finish in relation to bonding wire
See chapter 4.3
The finish shall be stated in the PCB-TPD
2
3
7.6.3 PRECAUTIONS IN THE PCB-TPD
Table 7.13 Wire bonding PCB-TPD precautions
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8 HAZARDOUS AND HIGH VOLTAGES
Hazardous and high voltage design rules can be found in the next documents:
GID Electrical safety of PCBAs and racks (HLAN) – D000086055 ref[3.8]
GID High Voltage Flex PCB Interconnect in vacuum (EUBR) – D000023134 ref[3.7]
Heavy Copper, consult a PCB Expert to determine a suitable stack-up, dispensation required,
some additional design rules required, see chapter 5.11, ref [3.28]
Printed circuit boards (rigid, flex and flex-rigid) are typically assigned to pollution degree 2 and
material groups IIIa and IIIb (CTI between 100-400V) see D000086055 ref[3.8]
In case the Printed circuit board is designed for material group I(CTI ≥ 600V) or II (CTI 400V –
600V) all materials at the outer layers of the stackup (PCB material, soldermask, silkscreen etc.)
have to be specified with corresponding CTI class, dispensation required.
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2
All electrical functional signals (traces, copper areas and via’s) shall be protected from
contact with water. Protection shall be provided by:
Design rule
Description
Use mechanical waterproof seals or housings (e.g.
around connectors)
See chapter 9.1.4
No soldermask
Unless it is located within the sealing ring used
around connectors, or in other areas where no
water can enter.
Use polyimide cover layer
Use cover layer type DuPont™ as specified in
chapter 3.6 on the whole PCBA
All conductive features shall be covered by
polyimide cover layer, unless they are intended for
soldering or electrical contact. Fiducials shall be
cleared from polyimide cover layer.
Copper tracks, planes and vias shall be completely
covered by a polyimide cover layer.
Features which need soldering (solder pads), or
features which require electrical contact (Mounting
holes, shield contacts) and fiducials shall be left
uncovered according the design rules in chapter
5.3.
Use globtop for through-hole and press-fit
connectors
Avoid the usage of press-fit and through hole
components. If inevitable, globtop shall be used.
See chapter 9.1.2
No potted holes
Potted holes are prohibited.
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6
Design rule
Description
Component height top and bottom
< 30mm
Vias
Vias shall be covered
Tolerance on position
3mm
Coating thickness
30mm – 130µm
Maximum PCB size L x B
600mm x 500mm
Material
COATING ACRYLIC 1B31LOC-1/4 GL
4022.488.07291
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9 NON-STANDARD ENVIRONMENT
9.1 MOISTURE
Table 9.1 Moisture resist design rules
9.1.1 COATING
Table 9.2 Coating rules
9.1.2 GLOBTOP
Globtop for moisture resist shall be used for two applications:
To make the pins of a through hole or pressfit component on the backside of the PCBA more
water tight
To close the gap between the component body and the PCBA surface
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Figure 9-1 Globtop design rules
Figure 9-2 Globtop examples
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Design rule
Description
Use only for SELV circuitry
Use only for voltages below 42.4V peak-to-peak or 60V DC
Ensure that the PCBA can withstand
the curing process
During the curing process of the glob top the PCBA will be
heated
A = 2.5mm ± 1mm
Obstruct area around the component’s maximum body size on
component side for:
No components
No contours or holes
No copper pads (soldering or mounting)
No board outline (edge)
B = 3.5mm ± 1mm
Obstruct area around the edge of the component pads on
opposite site for:
No components
No contours or holes
No copper pads (soldering or mounting)
No board outline (edge)
C ≤ 3mm
The height of the globtop shall not exceed 3mm
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Allowed material = Stycast 50400-1 (4022.489.00103)
Design rules for usage of globtop as moisture resist sealing:
Table 9.3 Globtop design rules
Globtop will be applied by the PCBA manufacturer
The PCA-TPD shall contain an indication of the globtop locations.
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See chapter 3.6 for cover layer usage and restrictions
See chapter 5.3 for cover layer design rules
Usage of components or connectors where alignment
holes are needed, is strongly not recommended. A
dispensation is required when these type of components
are used in a moisture environment.
Special precautions are needed for the alignment holes of
SMD connectors. These holes are non-plated holes and
shall be covered with cover layer on the opposite PCB side
of which the connector is mounted on.
Figure 9-3 Connector alignment pins
covered with cover layer
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Figure 9-4 Sealing ring principle
Figure 9-5 Sealing ring PCB layout
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Design rule
Description
No vias
No vias in the copper area of the sealing ring
No soldermask
No soldermask allowed on the sealing ring
No cover layer
No polyimide or any kind of cover layer or coating allowed on the sealing
ring
No silkscreen
No silkscreen allowed on the sealing ring
No copper outline change
The copper outline shall be as defined in the EMN file without any
changes
Uniform copper layout on
inner layers
The layout underneath the sealing ring on the inner layers shall be as
uniform as possible. How this can be achieved is depending on the
situation. For extra guidance on this, contact a PCBT expert.
Pristine area
Shall be free of surface nodules, contaminations, pinholes, voids, all kind
of scratches (eg. Sleek, rub, crush), pits, dents, bulges, blisters, digs,
bubbles and swellings. Roughness: Ra = 0.8 (see ref[3.20])
13
9.1.3 COVER LAYER
The BTS shall contain a remark about these covered holes, to prevent the supplier from clearing these
holes from cover layer: “Non-plated holes, covered by a cover layer = Yes”.
9.1.4 SEALING RINGS
The sealing ring or copper shape shall be defined by the EM Engineer. See ref[3.9] for information about
the sealing ring. The exact dimensions and form shall be available for the PCBL Engineer through the
EMN file.
The PCBL Engineer is responsible for adding this copper ring to the TPD-PCB according the next design
rules:
Table 9.4 Sealing ring design rules
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