• Up-to 3 chips can be cascaded locally for horizontal
expansion
• All ports can be separately isolated or partitioned in
response to fault condition
• Separate jabber and partition state machines for
each port
• Per-port LED display for Jabber, Partition, Activity
and global collision, utilization (%) for
10/100Mbps presentation
• Power on LED diagnosis. All the LED display will
follow the “ON-OFF-ON-OFF-Normal” operation
procedure during/after power on reset
• 50MHz Operation, 3.3volt and 128-pin PQFP
Product description
The AX88873 10/100Mbps Dual Speed repeater Controller is a counterpart of AX88872 without built in 4-ports
switch. It is design for low cost dual speed dumb HUB application.
The AX88873 directly supports up-to eight 10/100Mbps automatic links RMII interfaces. Maximum up-to 96
repeater ports can be constructed by stacking 1 AX88872 and 2 AX88873 chips horizontally and then cascading 4
horizontal boards vertically.
With using 128-pin low cost package, accompany with AX88872 to build up low cost dual speed repeater application.
Not only perform the repeater function but gain additional 2 switch ports. The 2 dual speed switch ports are connected
to external MII or RMII interfaces PHY for various applications. For example, one port is use for down link and the
other is used for up link to extend the network topology. The other case is one port for up link and the other port for
server.
The AX88873 is designed base on IEEE 802.3u clause 27 “ Repeater for 100Mb/s base-band networks” It is fully
compatible with IEEE 802.3u standard. Please refer Ax872-11.doc to get more information about AX88872.
System Block Diagram
Buffer
AX88873 #1
Repeater Controller
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
AX88873 #0
Repeater Controller
AX88872 #0
Swipeater Controller
ASIX ELECTRONICS CORPORATIONDoc. No. AX873-11.DOC Date : APR/26/1999
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500FAX: 886-3-579-9558 http://www.asix.com.tw
1.1 GENERAL DESCRIPTION...................................................................................................................................... 4
2.1 RMII INTERFACE FOR REPEATER PORTS............................................................................................................... 6
2.1.1 Repeater Port 0 .......................................................................................................................................... 6
2.1.2 Repeater Port 1 .......................................................................................................................................... 6
2.1.3 Repeater Port 2 .......................................................................................................................................... 7
2.1.4 Repeater Port 3 .......................................................................................................................................... 7
2.1.5 Repeater Port 4 .......................................................................................................................................... 7
2.1.6 Repeater Port 5 .......................................................................................................................................... 7
2.1.7 Repeater Port 6 .......................................................................................................................................... 8
2.1.8 Repeater Port 7 .......................................................................................................................................... 8
2.2 EXPANSION BUS INTERFACE FOR 100 MBPS......................................................................................................... 8
2.3 EXPANSION BUS INTERFACE FOR 10 MBPS........................................................................................................... 9
2.4 LED DISPLAY.................................................................................................................................................. 10
3.1 REPEATER STATE MACHINE.............................................................................................................................. 12
3.3 JABBER STATE MACHINE.................................................................................................................................. 12
3.4 PARTITION STATE MACHINE............................................................................................................................. 12
3.5 LED DISPLAY INTERFACE................................................................................................................................ 13
5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 15
5.1 ABSOLUTE MAXIMUM RATINGS........................................................................................................................ 15
5.2 GENERAL OPERATION CONDITIONS................................................................................................................... 15
5.3 DC CHARACTERISTICS..................................................................................................................................... 15
5.4 AC SPECIFICATIONS......................................................................................................................................... 16
5.4.2 MII Interface Timing TX & RX................................................................................................................. 17
5.4.3 LED DISPLAY ......................................................................................................................................... 18
5.4.4 LED Display after Reset........................................................................................................................... 18
FIG - 3 APPLICATION FOR LED DISPLAY..................................................................................................................... 13
3
ASIX ELECTRONICS CORPORATION
CONFIDENTIAL
AX88873P 10/100Mb Repeater Controller PRELIMINARY
1.0 AX88873 Overview
1.1 General Description
The AX88873 is a simple dual speed repeater that provides two expansion buses for 10M and 100M
segments respectively. Accompany with AX88872 (build-in a 4-port switch) can construct high port
count (16 ports or 24 ports) application and gain 2 additional switch ports. Additional two switch
ports are also useful for up-link or connection of server.
The pin count of chip is reduced to 128 when design uses RMII I/F instead of MII. It is not only
simplify the design but also user can choose low cost RMII Quad PHY.
All pin names with the “/” suffix are asserted low.
I=Input
O=Output
I/O=Input /Output
2.1 RMII interface for repeater ports
2.1.1 Repeater Port 0
Signal NameTypePin No.Description
SPEED0I103
CRS_DV0I104
RXD0[1:0]I106,105
TXEN0O108
TXD0[1:0]O110,109
Speed Select : SPEED0 is not standard RMII signal. This signal is
sourced from PHY to inform repeater whether 10M or 100M speed is
auto-negociated. Active for 10Mbps speed is selected depending on
power on configuration.
Carrier Sense/Receive Data Valid : CRS_DV is asserted
asynchronously on detection of carrier. CRS_DV is asserted by the PHY
when receive medium is non-idle. Loss of carrier shall result in the
desertion of CRS_DV synchronous to the cycle of REF_CLK, which
presents the first DI-bit of a nibble on to RXD0[1:0].
Receive Data : RXD0[1:0] is synchronous to REF_CLK
RXD0[1:0] shall be “00” to indicate idle when CRS_DV is disserted.
Value other than “00” are reserved for out-of-band signaling shall be
ignored by MAC Upon assertion of CRS_DV, PHY shall ensure that
RXD[1:0] = “00” until proper receive decoding takes place
Transmit Enable : TXEN0 is synchronous to REF_CLK.
TXEN0 indicates that MAC is presenting DI-bits on TXD[1:0] for
transmission. TXEN0 shall be negated prior to the 1st REF_CLK rising
edge following the final DI-bit of a frame
Transmit Data : TXD0[1:0] shall transition synchronously to
REF_CLK. TXD0[1:0] shall be “00” to indicate idle when TX_EN is
disserted. Value other than “00” are reserved for out-of-band signaling
shall be ignored by PHY. When TX_EN is asserted, TXD[1:0] are
accepted for transmission by PHY