ASIX AX88615P Datasheet

5-Port 10/100BASE Ethernet Switch Controller

1 Quad RMII/MII PHY

RMII/MII PHY for Down-link or Server

5 Port 10/100Mb SOHO Switch

Features

• Support 5 10/100 Mbps Ethernet ports with

RMII/MII interface

ü Provides packet switching functions between 5

10/100 Mbps, auto-negotiated ports

ü Ideal for SOHO switches and its application

• Build in 5-ports 10/100Mbps Switch engine with

following features

ü Low cost SSRAM interface to reduce system cost ü One or two 64K*32bit SSRAM to buffer packets ü 4/8 K MAC address look up Table is supported ü Address mapping of look up table can be linear or

use hash algorithm

ü Auto learning and filtering ü Aging the look up table is supported optionally ü Aging time can be 1min to 640 mins 7 steps

AX88615P

Document No.: AX615-13 / V1.3 / Aug. 11 ’99

ü Three forwarding modes are supported : Store-

and-Forward, Fragment-Free and Auto Forward which is based on network quality

ü Flow-control is supported optionally ü 802.3x flow control is supported when running in

full-duplex mode

ü Back-pressure base flow control is supported

when running in half-duplex mode

ü Ext. Buffer Memory auto testing ü Routing and Learning at wire speed (148800

packets/sec at 100Mbps)

• LED display buffer utilization (%) for whole system

and external SSRAM test.

• Power on LED diagnosis. All the LED display will

follow the “ON-OFF-ON-OFF-Normal” operation procedure during/after power on reset

• 60MHz Operation, 3.3volt, 208-pin PQFP

Product description

The AX88615 is a 5-ports 10/100 Mbps Ethernet switch with MII PHY or RMII PHY. It is design for low cost dumb Switch application, e.g. SOHO Ethernet Switch, with low cost 64K*32 SSRAM buffer memory.

Key Applications

ü SOHO Ethernet Switch ü IP Router

System Block Diagram

AX88615

Switch Controller

1 or 2 64K*32 SSRAM

This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify the product specification without notice. No

Always contact ASIX for possible updates before starting a design.

liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.

ASIX ELECTRONICS CORPORATION First Released Date : APR/02/1999

2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw

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CONTENTS

1.0 AX88615 OVERVIEW....................................................................................................................................... 4

1.1 GENERAL DESCRIPTION...................................................................................................................................... 4

1.2 AX88615 BLOCK DIAGRAM:.............................................................................................................................. 4

1.3 PIN CONNECTION DIAGRAM ............................................................................................................................... 5

2.0 PIN DESCRIPTION........................................................................................................................................... 6

2.1 MII/RMII INTERFACE FOR SWITCH PORTS............................................................................................................ 6

2.1.1 Switch Port 0.............................................................................................................................................. 6

2.1.2 Switch Port 1.............................................................................................................................................. 7

2.1.3 Switch Port 2.............................................................................................................................................. 7

2.1.4 Switch Port 3.............................................................................................................................................. 8

2.1.5 Switch Port 4.............................................................................................................................................. 8

2.2 LED DISPLAY.................................................................................................................................................... 9

2.3 BUFFER MEMORY PINS GROUP ............................................................................................................................. 9

2.4 MISCELLANEOUS.............................................................................................................................................. 10

2.5 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 11

3.0 FUNCTIONAL DESCRIPTION..................................................................................................................... 13

3.1 BASIC OPERATION............................................................................................................................................ 13

3.2 PACKET FILTERING AND FORWARDING PROCESS................................................................................................ 13

3.3 MAC ADDRESS LEARNING AND AGING PROCESS .............................................................................................. 13

3.4 FLOW CONTROL PROCESS ................................................................................................................................ 13

4.0 INTERNAL REGISTERS................................................................................................................................ 15

5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 16

5.1 ABSOLUTE MAXIMUM RATINGS........................................................................................................................ 16

5.2 GENERAL OPERATION CONDITIONS................................................................................................................... 16

5.3 DC CHARACTERISTICS..................................................................................................................................... 16

5.4 AC SPECIFICATIONS......................................................................................................................................... 17

5.4.1 LCLK....................................................................................................................................................... 17

5.4.2 Reset Timing............................................................................................................................................ 17

5.4.3 RMII Interface Timing Tx & Rx ................................................................................................................ 18

5.4.4 MII Interface Timing Tx & Rx.................................................................................................................. 19

5.4.5 SSRAM Read Cycle Timing...................................................................................................................... 20

5.4.6 SSRAM Write CycleTiming....................................................................................................................... 21

5.4.7 LED DISPLAY ......................................................................................................................................... 22

5.4.8 LED Display After Reset.......................................................................................................................... 22

6.0 PACKAGE INFORMATION........................................................................................................................... 23

APPENDIX A: SYSTEM APPLICATIONS.......................................................................................................... 24

A.1 AX88615 AS 5-PORT STANDALONE SOHO SWITCH........................................................................................... 24

A.2 AX88615 FOR IP ROUTER APPLICATION........................................................................................................... 24

A.3 AX88615 AS BACKEND OF DUAL SPEED REPEATERS........................................................................................... 25

APPENDIX B: DESIGN NOTE............................................................................................................................. 26

B.1 USING STATION MANAGEMENT (STA) CONNECTION ........................................................................................ 26

B.2 USING MII I/F CONNECTS TO MAC.................................................................................................................. 26

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FIGURES

FIG - 1 AX88615 BLOCK DIAGRAM ............................................................................................................................. 4

FIG - 2 PIN CONNECTION DIAGRAM.............................................................................................................................. 5

FIG - 3 APPLICATION FOR LED DISPLAY..................................................................................................................... 14

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1.0 AX88615 Overview

P0 10/100 MAC

P1 10/100 MAC

P2 10/100 MAC

P3 10/100 MAC

P4 10/100 MAC

PHY

64K*32 SSRAM

1.1 General Description

The AX88615 is a 5-ports 10/100 Mbps Ethernet switch with MII PHY or RMII PHY. A low cost Fast Ethernet switch can be implemented by using the AX88615 and low cost 64Kx32 SSRAM .

Data received from the MAC interface is stored in the external memory. All ports support multiple MAC addresses. The switch provides a look-up table for 8K MAC addresses with two 64Kx32 SSRAMs. The AX88615 provides three frame forwarding mode: store-and-forward mode, safe cut-through (fragment free) mode and dynamic-select-mode (auto). The dynamic-select-mode means the switch selects optimizes mode for forwarding packages automatically according to Network quality.

During transmission, the data is obtained from the buffer memory and routed to the destination port. For half-duplex operation, the MAC control will back off and retransmit in accordance to the IEEE802.3 CSMA/CD if collision occurs.

The AX88615 provides two flow control methods. For half-duplex operation, an optional jamming based flow control is available to avoid loss of data. This is also well known as back pressure. In the full-duplex mode, AX88615 utilizes IEEE802.3X as the flow control mechanism.

1.2 AX88615 Block Diagram:

MII / RMII

LED Interface

Fig - 1 AX88615 Block Diagram

High Speed

Switch Fabric

Routing /Learning

Controller

Buffer Manager

Buffer Memory

Interface

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1.3 Pin Connection Diagram

VDD

BMA11

BMA10

VSS

VDD

BMA5

BMA1

BMA4

BMA3

BMA2

BMD24

BMD28

BMD27

BMD31

BMD26

BMD25

BMD29

BMD30

SRXD4[3]

SDUPLEX4

SRXD4[1]

STXD4[1]

SCOL4

STXD4[0]

SRXD4[0]

STXCLK4

SRXDV4

SCRS4

SRXD4[2]

STXEN4

SRXCLK4

SRXD3[3]

SDUPLEX3

SRXD3[1]

STXD3[1]

SCOL3

STXD3[0]

SRXD3[0]

STXCLK3

SRXDV3

SCRS3

STXD3[2]

SRXD3[2]

STXEN3

SRXCLK3

STXD3[3]

SDUPLEX1

SDUPLEX0

BMA0

SPEED3

SPEED4

VSS

BMA7

DB_OUT[6]

DB_OUT[5]

DB_OUT[4]

VDD

145

146

147

144

143

101112131415161718

VSS /BMWE

/BMOE SPEED2 SCRS2 SRXD2[0] SRXD2[1] VDD STXEN2 BMA8 STXD2[0] STXD2[1] SRXCLK2 BMA9 BMD15

BMD14 BMD13 VSS BMD12 BMD11 BMD10 BMD9 BMD8 BMD7 SRXDV2 SRXD2[2] SRXD2[3] SDUPLEX2 VSS STXD2[2] STXD2[3] BMD6 BMD5 BMD4 BMD3 BMD2 BMD1 BMD0 VDD STXCLK2 BMA16 BMA15 BMA14 BMA13 BMA12 SCOL2 NC NC NC NC NC VSS

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

NCNCNCNCNC

153

152

154

155

156

56472

151

150

DB_OUT[7]

VSS

148

149

BMA6

BMD16

141

142

BMD20

BMD18

VSS

139

BMD19

138

137

BMD21

135

136

BMD22

BMD23

DB_SEL[7]

133

134

132

DB_SEL[6]

DB_SEL[5]

131

130

BMD17

140

AX88615

2324222021

DB_OUT[3]

NCNCNC

DB_SEL[4]

VSS

124

125

126

127

128

129

293028

3233343536373839404142

DB_OUT[2]

DB_OUT[1]

DB_OUT[0]

VDD

DB_SEL[3]

121

122

120

119

123

SRXD0[3]

VSS

DB_SEL[2]

DB_SEL[1]

DB_SEL[0]

114

117

115

116

118

4347464445

SRXD0[0]

SRXD0[1]

SRXD0[2]

VSS

110

111

112

113

NCNCNC

106

107

108

109

4849505152

105

104 103 102 101 100

99 98 97

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

SRXCLK0 NC NC VSS NC NC SRXDV0 SCOL_SP0 SCRS0 NC

STXCLK0 VDD STXD0[3] STXD0[2] STXD0[1] STXD0[0] STXEN0 LED_CK LED<1>

LED<0> VSS SRXD1[3] SRXD1[2] SRXD1[1] SRXD1[0] SRXCLK1 SRXDV1 SCOL_SP1 SCRS1 NC NC BMCLK

VSS LCLK VDD REF_CLK VSS

STXCLK1 STXD1[3] STXD1[2] STXD1[1] STXD1[0] STXEN1 /RST /TEST MDIO MDC STXD4[3] STXD4[2]

Fig - 2 Pin Connection Diagram

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2.0 Pin Description

The following terms describe the AX88615 pinout:

All pin names with the “/” suffix are asserted low.

I = Input O = Output I/O = Input /Output

2.1 MII/RMII interface for switch ports

2.1.1 Switch Port 0 Signal Name Type Pin No. Description

STXEN0 O 87

STXD0[3:0] O 91,90,89,88

STXCLK0 I 93

SDUPLEX0 I 94

SCOL_SP0 I 97

SCRS0

or SCRS_DV0

SRXDV0 I 98

SRXCLK0 I 104

SRXD0[3:0] I 114,113,

I 96

111,110

Transmit Enable : Active HIGH. This output indicates that the packet is being transmitted .If MII mode, TXEN0 is synchronous to STXCLK0. If RMII mode, TXEN0 is synchronous to REF_CLK. Transmit Data : STXD0[3:0] is synchronous to the rising edge of STXCLK0 in MII mode. For each STXCLK period in which STXEN is asserted, TXD[3:0] are accepted for transmission by the PHY. If RMII mode, STXD0[1:0] is synchronous to REF_CLK. TXD0[1:0] shall be “00” to indicate idle when TX_EN is disserted. Value that is not “00” is reserved for out-of-band signaling and shall be ignored by PHY. When TX_EN is asserted, TXD[1:0] are accepted for transmission by PHY Transmit Clock : Provides the timing reference for the STXEN0, STXD0 signals in MII mode. STXCLK0 frequency is one fourth of the data rate (25 MHz for 100Mbps, 2.5 MHz for 10Mbps). Duplex Select : DUPLEX0 is not standard MII/RMII signal. This input is connected to PHY directly to obtain the current data rate of Port0. Collision Detect: Active HIGH. Indicates a collision has been detected on wire in MII mode. This input is not synchronous to any clock and ignored in full-duplex mode If RMII mode, the signal is a speed indicator. Active for 10Mbps speed is selected depending on power on configuration. Carrier Sense : Active HIGH. Indicates that either the transmit or receive medium is non-idle in MII mode. SCRS0 is not synchronous to any clock. When RMII mode, the input is CRS_DV (Carrier Sense/Receive Data Valid ) that is asserted asynchronously on detection of carrier by the PHY when receive medium is non-idle. Loss of carrier shall result in the desertion of CRS_DV synchronous to the cycle of REF_CLK, which presents the first DI-bit of a nibble on to RXD0[1:0]. Receive Data Valid : Active HIGH. Indicates that valid data is present on the SRXD0 lines. Synchronous to SRXCLK0. Receive Clock : Provides the timing reference for the SRXDV0, SRXD0 signals in MII mode. STXCLK0 frequency is one fourth of the data rate (25 MHz for 100Mbps, 2.5 MHz for 10Mbps). Receive Data : Synchronously to the rising edge of RXCLK in MII mode. If RMII mode, SRXD0[1:0] is synchronous to REF_CLK. SRXD0[1:0] shall be “00” to indicate idle when CRS_DV is disserted. Value that is not “00” is reserved for out-of-band signaling shall be ignored by MAC Upon assertion of CRS_DV, PHY shall ensure that RXD[1:0] = “00” until proper receive decoding takes place

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2.1.2 Switch Port 1 Signal Name Type Pin No. Description

STXEN1 O 60

STXD1[3:0] O 64,63,62,61

STXCLK1 I 65

SDUPLEX1 I 66

SCOL_SP1 I 76

SCRS1 or SCRS_DV1 SRXDV1 I 77

SRXCLK1 I 78

SRXD1[3:0] I 82,81,80,79

I 75

Transmit Enable : Please references section 2.1.1 SWITCH PORT0 description. Transmit Data : Please references section 2.1.1 SWITCH PORT0 description. Transmit Clock : Please references section 2.1.1 SWITCH PORT0 description. Duplex Select : Please references section 2.1.1 SWITCH PORT0 description. Collision Detect: Please references section 2.1.1 SWITCH PORT0 description. Carrier Sense : Please references section 2.1.1 SWITCH PORT0 description.

Receive Data Valid : Please references section 2.1.1 SWITCH PORT0 description. Receive Clock : Please references section 2.1.1 SWITCH PORT0 description. Receive Data : Please references section 2.1.1 SWITCH PORT0 description.

2.1.3 Switch Port 2 Signal Name Type Pin No. Description

STXEN2 O 165

STXD2[3:0] O 187,186,

168,167

STXCLK2 I 196

SDUPLEX2 I 184

SCOL2 I 202

SCRS2 or SCRS_DV2 SRXDV2 I 181

SRXCLK2 I 169

SRXD2[3:0] I 183,182,

SPEED2 I 160

I 161

163,162

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2.1.4 Switch Port 3 Signal Name Type Pin No. Description

STXEN3 O 5

STXD3[3:0] O 15,14,7,6

STXCLK3 I 33

SDUPLEX3 I 13

SCOL3 I 34

SCRS3 or SCRS_DV3 SRXDV3 I 10

SRXCLK3 I 9

SRXD3[3:0] I 12,11,4,3

SPEED3 I 1

I 2

Speed Indicator : Identify data rate of Port 3

2.1.5 Switch Port 4 Signal Name Type Pin No. Description

STXEN4 O 45

STXD4[3:0] O 55,54,47,46

STXCLK4 I 36

SDUPLEX4 I 53

SCOL4 I 37

SCRS4 or SCRS_DV4 SRXDV4 I 50

SRXCLK4 I 49

SRXD4[3:0] I 52,51,44,43

SPEED4 I 41

I 42

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ASIX AX88615P Datasheet

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