ASIX AX88141 Datasheet

AX88141

ASIX

Fast Ethernet MAC Controller

ASIX AX88141

100BASE-TX/FX PCI Bus

Fast Ethernet MAC Controller

with Power management

Data Sheet (4/11/’ 98)

Always contact ASIX for possible updates

before starting a design.

DOCUMENT NO. : AX141-01.DOC

This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.

ASIX ELECTRONICS CORPORATION

2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: [phone] FAX: [phone] http:/www.asix.com.tw

AX88141 PRELIMINARY

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CONTENTS

1.0 INTRODUCTION..........................................................................................................................................6

1.1 GENERAL DESCRIPTION: ................................................................................................................................ 6

1.2 FEATURES .....................................................................................................................................................7

1.3 BLOCK DIAGRAM:..........................................................................................................................................8

1.4 AX88141 PIN CONNECTION DIAGRAM...........................................................................................................9

2.0 SIGNAL DESCRIPTION............................................................................................................................. 10

2.1 SIGNAL DESCRIPTIONS.................................................................................................................................10

2.2 PCI INTERFACE GROUP.................................................................................................................................10

2.3 BOOT ROM , SERIAL ROM , GENERAL-PURPOSE SIGNALS GROUP..................................................................11

2.4 MII INTERFACE SIGNALS GROUP ................................................................................................................... 12

2.5 POWER PINS GROUP......................................................................................................................................13

3.0 CONFIGURATION OPERATION .............................................................................................................14

3.1 CONFIGURATION SPACE MAPPING ................................................................................................................ 14

3.2 CONFIGURATION SPACE ...............................................................................................................................15

3.2.1 Configuration ID Register (CSID)....................................................................................................... 15

3.2.2 Command and Status Configuration Register (CSCS)...........................................................................15

3.2.3 Configuration Revision Register (CSRV) ............................................................................................. 15

3.2.4 Configuration Latency Timer Register (CSLT) .................................................................................... 15

3.2.5 Configuration Base I/O Address Register (CBIO) ...............................................................................16

3.2.6 Configuration Base Memory Address Register (CBMA) ...................................................................... 16

3.2.7 Expansion ROM Base Address Register (CBER)................................................................................. 16

3.2.8 Configuration Interrupt Register (CSIT)..............................................................................................16

3.2.9 Special Use Register (SUD) ................................................................................................................ 16

3.2.10 Subsystem ID and Subsystem Vendor Register (SSID) .......................................................................16

3.2.11 New Capabilities Pointer (CNCP)..................................................................................................... 17

3.2.12 Power Management register block (Offset 44H to 49H)......................................................................17

4.0 REGISTERS OPERATION ......................................................................................................................... 18

4.1 REGISTERS MAPPING ...................................................................................................................................18

4.2 HOST REGS ................................................................................................................................................19

4.2.1 Bus Mode Register (REG0).................................................................................................................. 19

4.2.2 Magic Packet Password Low (REG0B)................................................................................................ 19

4.2.3 Transmit Poll Demand (REG1) ........................................................................................................... 19

4.2.4 Magic Packet Password High (REG1B) .............................................................................................. 19

4.2.5 Receive Poll Demand (REG2)............................................................................................................. 20

4.2.6 Receive List Base Address (REG3) ...................................................................................................... 20

4.2.7 Transmit List Base Address (REG4)....................................................................................................20

4.2.8 Status Register (REG5).......................................................................................................................21

4.2.9 Operation Mode Register (REG6)....................................................................................................... 22

4.2.10 Interrupt Enable Register (REG7).....................................................................................................24

4.2.11 Missed Frame and Overflow Counter (REG8)..................................................................................24

4.2.12 Serial ROM and MII Management Register (REG9).......................................................................... 25

4.2.13 General -Purpose Timer (REG11)..................................................................................................... 25

4.2.14 General -Purpose Port Register (REG12)..........................................................................................26

4.2.15 Filtering Index (REG13) ................................................................................................................... 26

4.2.16 Filtering data (REG14)..................................................................................................................... 26

5.0 HOST COMMUNICATION ........................................................................................................................ 28

5.1 DESCRIPTOR LISTS AND DATA BUFFERS........................................................................................................28

5.2 RECEIVE DESCRIPTORS ................................................................................................................................29

5.2.1 Receive Descriptor 0 (RDES0).............................................................................................................29

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5.2.2 Receive Descriptor 1 (RDES1).............................................................................................................30

5.2.3 Receive Descriptor 2 (RDES2).............................................................................................................30

5.2.4 Receive Descriptor 3 (RDES3).............................................................................................................30

5.3 TRANSMIT DESCRIPTORS.............................................................................................................................. 31

5.3.1 Transmit Descriptor 0 (TDES0)............................................................................................................31

5.3.2 Transmit Descriptor 1 (TDES1)............................................................................................................32

5.3.3 Transmit Descriptor 2 (TDES2)............................................................................................................32

5.3.4 Transmit Descriptor 3 (TDES3)............................................................................................................32

6.0 ELECTRICAL SPECIFICATION AND TIMINGS .................................................................................. 33

6.1 ABSOLUTE MAXIMUM RATINGS.................................................................................................................... 33

6.2 GENERAL OPERATION CONDITIONS .............................................................................................................. 33

6.3 DC CHARACTERISTICS................................................................................................................................. 33

6.4 A.C. TIMING CHARACTERISTICS...................................................................................................................34

6.4.1 PCI CLOCK.........................................................................................................................................34

6.4.2 PCI Timings......................................................................................................................................... 34

6.4.3 Reset Timing........................................................................................................................................34

6.4.4 MII Timing...........................................................................................................................................35

6.4.5 Boot ROM Read Cycles ....................................................................................................................... 36

7.0 PACKAGE INFORMATION......................................................................................................................37

APPENDIX A H/W NOTE .......................................................................................................................38

A.1 BOOT ROM READ CYCLE ............................................................................................................................ 38

A.2 POWER SUPPLY...........................................................................................................................................39

A.3 BOUNDARY SCAN TEST PINS ....................................................................................................................... 39

APPENDIX B FUNCTION APPLICATION...........................................................................................40

B.1 APPLICATION FOR PCI INTERFACE............................................................................................................... 40

B.2 APPLICATION FOR BOOT ROM INTERFACE................................................................................................... 41

B.3 APPLICATION FOR SERIAL ROM INTERFACE.................................................................................................41

B.4 APPLICATIONS ............................................................................................................................................ 42

B.4.1 Application for NS DP83843...............................................................................................................42

B.4.2 Application for LUCENT M-LU6612/M-3X51 ..................................................................................... 42

B.4.3 Application for TI XTNETE2101 ......................................................................................................... 43

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FIGURES

FIG - 1 AX88141 BLOCK DIAGRAM .....................................................................................................8

FIG - 2 AX88141 PIN CONNECTION DIAGRAM ......................................................................................9

FIG - 3 DESCRIPTOR STRUCTURE EXAMPLE ...........................................................................................28

FIG - 4 RECEIVE DESCRIPTOR FORMAT .................................................................................................29

FIG - 5 TRANSMIT DESCRIPTOR FORMAT ...............................................................................................31

FIG - 6 APPLICATION FOR LXT970 .....................................................................................................42

FIG - 7 APPLICATION FOR MTD972 +MTD971 ...............................................................................43

FIG - 8 APPLICATION FOR DM9101 .....................................................................................................43

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TABLES

TAB - 1 PCI INTERFACE GROUP..............................................................................................................................11

TAB - 2 BOOT ROM , SERIAL ROM , GENERAL-PURPOSE SIGNALS GROUP...............................................................12

TAB - 3 MII INTERFACE SIGNALS GROUP.................................................................................................................12

TAB - 4 POWER PINS GROUP...................................................................................................................................13

TAB - 5 CONFIGURATION SPACE MAPPING..............................................................................................................14

TAB - 6 CSID CONFIGURATION ID REGISTER DESCRIPTION....................................................................................15

TAB - 7 CSCS COMMAND AND STATUS CONFIGURATION REGISTER ........................................................................15

TAB - 8 CSRV CONFIGURATION REVISION REGISTER DESCRIPTION.........................................................................15

TAB - 9 CSLT CONFIGURATION ID REGISTER DESCRIPTION ...................................................................................15

TAB - 10 CBIO CONFIGURATION BASE I/O ADDRESS REGISTER DESCRIPTION.........................................................16

TAB - 11 CBMA CONFIGURATION BASE MEMORY ADDRESS REGISTER DESCRIPTION..............................................16

TAB - 12 CBER EXPANSION ROM BASE ADDRESS REGISTER DESCRIPTION ............................................................16

TAB - 13 CSIT CONFIGURATION INTERRUPT REGISTER DESCRIPTION......................................................................16

TAB - 14 CSIT CONFIGURATION INTERRUPT REGISTER DESCRIPTION......................................................................16

TAB - 15 SSID CONFIGURATION ID REGISTER DESCRIPTION ..................................................................................17

TAB - 16 CNCP CONFIGURATION ID REGISTER DESCRIPTION.................................................................................17

TAB - 17 CSID CONFIGURATION ID REGISTER DESCRIPTION..................................................................................17

TAB - 18 COMMAND AND STATUS REGISTER MAPPING............................................................................................18

TAB - 19 REG0 BUS MODE REGISTER DESCRIPTION...............................................................................................19

TAB - 20 REG1 TRANSMIT POLL DEMAND REGISTER DESCRIPTION ........................................................................19

TAB - 21 REG1 TRANSMIT POLL DEMAND REGISTER DESCRIPTION ........................................................................19

TAB - 22 REG1 TRANSMIT POLL DEMAND REGISTER DESCRIPTION ........................................................................19

TAB - 23 REG2 RECEIVE POLL DEMAND REGISTER DESCRIPTION ...........................................................................19

TAB - 24 REG3 RECEIVE LIST BASE ADDRESS REGISTER DESCRIPTION...................................................................20

TAB - 25 REG4 TRANSMIT LIST BASE ADDRESS REGISTER DESCRIPTION ................................................................20

TAB - 26 REG5 STATUS REGISTER DESCRIPTION....................................................................................................22

TAB - 27 REG6 OPERATION MODE REGISTER DESCRIPTION ...................................................................................23

TAB - 28 PORT AND DATA RATE SELECTION...........................................................................................................23

TAB - 29 REG7 INTERRUPT ENABLE REGISTER DESCRIPTION .................................................................................24

TAB - 30 REG8 MISSED FRAME AND OVERFLOW COUNTER DESCRIPTION ...............................................................24

TAB - 31 REG9 SERIAL ROM, AND MII MANAGEMENT REGISTER DESCRIPTION....................................................25

TAB - 32 REG11 GENERAL -PURPOSE TIMER REGISTER DESCRIPTION.....................................................................26

TAB - 33 REG12 GENERAL -PURPOSE PORT REGISTER DESCRIPTION.......................................................................26

TAB - 34 REG13 FILTERING INDEX REGISTER DESCRIPTION...................................................................................26

TAB - 35 REG14 FILTERING DATA REGISTER DESCRIPTION....................................................................................26

TAB - 36 DESCRIPTION OF FILTERING BUFFER ........................................................................................................26

TAB - 37 LAYOUT OF FILTERING BUFFER................................................................................................................27

TAB - 38 RECEIVE DESCRIPTOR 0...........................................................................................................................30

TAB - 39 RECEIVE DESCRIPTOR 1...........................................................................................................................30

TAB - 40 RECEIVE DESCRIPTOR 2...........................................................................................................................30

TAB - 41 RECEIVE DESCRIPTOR 3...........................................................................................................................30

TAB - 42 TRANSMIT DESCRIPTOR 0........................................................................................................................32

TAB - 43 TRANSMIT DESCRIPTOR 1........................................................................................................................32

TAB - 44 TRANSMIT DESCRIPTOR 2........................................................................................................................32

TAB - 45 TRANSMIT DESCRIPTOR 3........................................................................................................................32

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1.0 Introduction

1.1 General Description:

l The AX88141 Fast Ethernet Controller is a high performance and highly integrated PCI Bus Ethernet

Controller chip.

l The AX88141 is cost effective, high performance solution for PCI add-in adapters, PC motherboards, or

bridge/hub applications.

l It implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3u LAN standard.
l The AX88141 contains a high speed 32 bit PCI Bus master interface to host CPU. Two large

independent transmit and receive FIFO allow the AX88141 to buffer the Ethernet packet efficiently.

l The AX88141 support 10Mbps/100Mbps media-independent interface (MII) to simplify the design.

l The AX88141 is compliant with the Network Device Class Power Management and the Communication

Device Class Power Management requirements under the OnNow Architecture for PC 97 and PC 98.

l The AX88141 is compliant with the Advanced Configuration and Power Interface (ACPI) Specification

and the PCI Bus Power Management Interface Specification.

l The AX88141 provide both PHY level or MAC level power management function.
l The AX88141 provide magic packet algorithm with password to support ACPI function.

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1.2 Features

l Single chip PCI bus Fast Ethernet Controller.
l Direct interface to PCI bus.
l Support both 10Mbps and 100Mbps data rate.
l Full or Half duplex operation supported for both10Mbps and 100Mbps operation.
l Provides a MII port for both 10/100Mbps operation.
l Support 20MHz to 33MHz no wait state PCI Bus Interface.
l Two large Independent FIFO for transmit and receive. no additional On board buffer memory required.
l Interface to serial ROM for Ethernet ID address and jumper-less board design.
l 64KB boot ROM support.
l Support automatic loading of subvendor ID.
l On chip general purpose, programmable register and I/O pins.
l Unlimited PCI burst.
l External and internal loop-back capability.
l Support early interrupts on transmit.
l Powerful on chip buffer management DMA. And PCI Bus master operation reduce CPU utilization.
l Support network device OnNow requirements for PC 97 and PC 98.
l Compliant with the ACPI specification and the PCI Bus Power Management Interface Specification.
l Support Magic Packet technology.
l Big and little endian byte ordering supported.
l IEEE 802.3u 100BASE-T, TX, and T4 Compatible.
l 128 pin PQFP package.
l 5V CMOS process.

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1.3 Block Diagram:

SERIAL BOOT ROM
ROM Interface

Serial

ROM I/F

PCI MII
BUS

General purpose I/O pins

PCI

BUS

Interface

Receive FIFO

Buffer

Management

DMA Engine

Transmit FIFO

General Purpose REG

BOOT

ROM I/F

MAC

Controller

10/100 MII

Interface

Fig - 1 AX88141 Block Diagram

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DEVSEL#

AD_20

C_BE#3

AD_26

INT#

AD_19

AD_25

VDD

VDD

VSS

PME#

VSS

AD_29

REQ#

AD_21

AD_16

GNT#

VSS

IDSEL

AD_23

VSS

PCI_CLK

AD_28

VSS

AD_17

VDD

AD_27

AD_30

VDD

AD_18

RST#

VSS

AD_22

AD_24

AD_31

C_BE#2

VSS

PTEST

VSS

1.4 AX88141 Pin Connection Diagram

The AX88141 is housed in the 128-pin plastic quad flat pack. Fig - 2 shows the AX88141 pin
connection diagram.

AD_0

BR_A12

BR_A11

BR_A10

BR_A13

BR_A9

BR_A8

BR_A7

BR_A6

BR_A5

BR_A4

BR_A3

BR_A2

BR_A1

BR_D7

BR_A0

VSS

BR_D6

BR_D5

BR_D4

BR_D3

BR_D2

BR_D1

SR_DI

VDD

SR_CS

VDD

SR_CK

BR_CE#

VSS

AD_1

AD_2

SR_DO/BR_D0

VSS

AD_3

VDD

AD_4

VSS

BR_A14
BR_A15
GEP_0
GEP_1
MDIO

MDC
RXER
VDD

RXDV

VSS

COL

CRS

RXCLK

RXD_0

RXD_1

RXD_2

RXD_3

VDD

TXCLK

VSS

TXEN

TXD_0

TXD_1

VDD

TXD_2

TXD_3

103
104
105

106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

102

1

101

2

100

3

78

75

77

84

829181

93

94

95

96

989799

90

86

87

8892858983

79

80

76

74

AX88141

8

7

4

6

5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

73

30

72

31

71

32

70

33

69

34

68

35

67

36

66

37

65

38

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46

45
44
43
42
41
40
39

AD_5
AD_6
AD_7
C_BE#0
VSS
AD_8
AD_9
AD_10
VDD
AD_11
AD_12
VSS
AD_13
AD_14
AD_15

VSS
C_BE#1

PAR
SERR#

PERR#
VDD
STOP#

TRDY#
IRDY#
FRAME#

Fig - 2 AX88141 Pin connection diagram

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2.0 Signal Description

2.1 Signal Descriptions

The following terms describe the AX88141 pin-out:

l Address phase

Address and appropriate bus commands are driven during this cycle.

l Data phase

Data and the appropriate byte enable codes are driven during this cycle.

l #

All pin names with the # suffix are asserted low.

The following abbreviations are used in Tab - 1 PCI interface group Tab - 2 Boot ROM , Serial ROM , General-

purpose signals group ,Tab - 3 MII interface signals group ,Tab - 4 Power pins group..

I Input
O Output
I/O Input /Output
O/D Open Drain

2.2 PCI interface group

SIGNAL TYPE PIN

NUMBER

CBE#<3>
CBE#<2>
CBE#<1>
CBE#<0>
DEVSEL# I/O 42 Device select Is asserted by the target of the current bus access. When the AX88141 is the master of the

FRAME# I/O 39 The FRAME# Signal is driven by the AX88141 To indicate the beginning and duration of an access.

GNT# I 7 BUS GRANT Indicates to the AX88141 That access to the bus is granted.
IDSEL I 22 Initialization devise select asserts To indicate that the host is issuing a configuration cycle to the

INT# O/D 1 Interrupt request asserts When one of the appropriate bits of reg5 sets and causes an interrupt, provided

IRDY# I/O 40

PAR I/O 47 Parity is an even parity bit for the AD<31:0> AD and CBE#<3:0>.

I/O 21,

38,
48,

61

BUS COMMAND and BYTE ENABLE Are multiplexed on the same PCI pins. During the address
phase of the transaction, CBE#<3:0> Provide the BUS COMMAND. During the data phase,
CBE#<3:0> Provide the BYTE ENABLE. The BYTE ENABLE determines which byte lines carry
valid data., CBE#<0> Applies to byte 0, and CBE#<3> Applies to byte 3.

current bus access, the target assert DEVSEL# confirming the access. It is driven by AX88141 When
AX88141 is selected as a slave.

FRAME# Asserts to indicate the beginning of a bus transaction. While FRAME# is asserted, data
transfers continue. When FRAME# deasserts the next data phase is the final data phase transaction.

AX88141.

that the corresponding mask bit in reg7 is not asserted. interrupt request deasserts by writing a 1 into the
appropriate reg5 bit.
This pin must be pulled up by an external resistor.
Initiator ready Indicates the bus master ability to complete the current data phase of the transaction.
A data phase is completed on any rising edge of the clock When both IRDY# and target ready TRDY#
are asserted. Wait cycles are inserted until both IRDY# and TRDY# are asserted together.
When the AX88141 is the bus master, IRDY# is asserted during write operations to indicate that valid
data is present on the AD<31:0>. During read operations, the AX88141 asserts IRDY# to indicate that
it is ready to accept data.

During address and data phases, parity is calculated on all the AD<31:0> AND CBE#<3:0>lines
whether or not any of these lines carry meaningful information.

DESCRIPTION

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AD<31>
AD<30>
AD<29>
AD<28>
AD<27>
AD<26>
AD<25>
AD<24>
AD<23>
AD<22>
AD<21>
AD<20>
AD<19>
AD<18>
AD<17>
AD<16>
AD<15>
AD<14>
AD<13>
AD<12>
AD<11>
AD<10>
AD<9>
AD<8>
AD<7>
AD<6>
AD<5>
AD<4>
AD<3>
AD<2>
AD<1>
AD<0>
PCI_CLK I 5 The clock provides the timing for the AX88141 related PCI bus transactions. All the bus signals are

PERR# I/O 45 Parity error asserts when a data parity error is detected. When the AX88141 is the bus master it monitor

REQ# O 8 Bus request is asserted by the AX88141 to indicate to the bus arbiter that it wants to use the bus.
RST# I 2 Resets the AX88141 to its initial state. This signal must be asserted for at least 10 active PCI clock

SERR# I/O 46 System Error is used by AX88141 to report address parity Error. This pin must be pulled up by an

STOP# I/O 43 Stop indicator indicates that the current target is requesting the bus master to stop the current transaction.

TRDY# I/O 41 Target ready indicates the target ability to complete the current data phase of the transaction.

PME# O 9

I/O 10,

11,
13,
14,
16,
17,
19,
20,
24,
25,
26,
27,
29,
30,
33,
34,
50,
51,
52,
54,
55,
57,
58,
59,
62,
63,
64,
66,
67,
69,
70,

72

Address and data bits are multiplexed on the same pins. During the address phase, the AD<31:0>
contain a physical address (32 bits). During, data phases, AD<31:0> contain 32 bits of data.
The AX88141 supports both read and write bursts (in master operation only). Little and big endian byte
ordering can be used.

sampled on the rising edge of PCI_CLK. The clock frequency range is between 20MHZ and 33MHZ.

PERR# to see if the target report a data parity error., when the AX88141 is the bus target and a parity
error is detected, the AX88141 asserts PERR#. This pin must be pulled up by an external resistor.

cycles. When is the reset state, all PCI output pins are put into tri-state and all PCI o/d signals are
floated.

external resistor.

The AX88141 responds to the assertion of STOP# when it is the bus master, and stop the current
transaction.

A data phase is completed on any clock when both TRDY# and IRDY# are asserted. Wait cycles are
inserted until both IRDY# and TRDY# are asserted together. When the AX88141 is the bus master,
target ready is asserted by the bus slave on the read operation, indicating that valid data is present on the
ad lines. During a write cycle, it indicates that the target is prepared to accept data.

2.3 Boot ROM , Serial ROM , General-purpose signals group

SIGNAL TYPE PIN

NUMBER

Tab - 1 PCI interface group

DESCRIPTION

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BR_A<15>
BR_A<14>
BR_A<13>
BR_A<12>
BR_A<11>
BR_A<10>
BR_A<9>
BR_A<8>
BR_A<7>
BR_A<6>
BR_A<5>
BR_A<4>
BR_A<3>
BR_A<2>
BR_A<1>
BR_A<0>
BR_D<7>
BR_D<6>
BR_D<5>
BR_D<4>
BR_D<3>
BR_D<2>
BR_D<1>
BR_D<0>/
SR_DO
BR_CE# O 78 Boot ROM chip enable.
SR_CK O 76 Serial ROM clock signal.
SR_CS O 77 Serial ROM chip-select signal.
SR_DI O 79 Serial ROM data-in signal.
GENP<1>
GENP<0>

O 104,

103,
102,
101,
100,

99,
98,
97,
96,
95,
94,
93,
92,
91,
90,

89

I 88,

86,
85,
84,
83,
82,
81,

73

I/O 106,

105

Boot ROM address lines bit 15 to bit 0.

Boot ROM data lines bit 7 to bit 0.

Serial ROM data-out signal.

General-purpose pins can be used by software as either status pins or control pins. These pins can be
configured by software to perform either input or output functions.

Tab - 2 Boot ROM , Serial ROM , General-purpose signals group

2.4 MII interface signals group

SIGNAL TYPE PIN

NUMBER
FOR 160 PIN

COL I 113 Collision detected is asserted when detected by an external physical layer protocol(PHY)

CRS I 114 Carrier sense is asserted by the PHY when the media is active.
RXDV I 111 Data valid is asserted by an external PHY when receive data is present on the RXD lines

RXER I 109 Receive error asserts when a data decoding error is detected by an external PHY device.

MDC O 108 MII management data clock is sourced by the AX88141 to the PHY devices as a timing

MDIO I/O 107 MII management data input/output transfers control information and status between the

RXCLK I 115 Supports either the 25-MHZ or 2.5-MHZ receive clock. This clock is recovered by the

RXD<3>
RXD<2>
RXD<1>
RXD<0>
TXCLK I 121 Supports the 25-MHZ or 2.5-MHZ transmit clock supplied by the external physical layer

TXD<3>
TXD<2>
TXD<1>
TXD<0>
TXEN O 123 Transmit enable signals that the transmit is active to an external PHY device.

I 119,

118,
117,

116

O 128,

127,
125,

124

device.

and is deasserted at the end of the packet. This signal should be synchronized with the
RXCLK signal.

This signal is synchronized to RXCLK and can be asserted for a minimum of one receive
clock. When asserted during a packet reception, it sets the cyclic redundancy check(CRC)
error bit in the receive descriptor (RDESO).

reference for the transfer of information on the MII_MDIO signal.

PHY and the AX88141.

PHY.
Four parallel receive data lines When MII mode is selected. This data is driven by an
external PHY that attached the media and should be synchronized with the RXCLK signal.

medium dependent (PMD) device. This clock should always be active.
Four parallel transmit data lines. This data is synchronized to the assertion of the TXCLK
signal and is latched by the external PHY on the rising edge of the TXCLK signal.

DESCRIPTION

Tab - 3 MII interface signals group

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2.5 Power pins group

SIGNAL TYPE PIN

NUMBER

VDD P 3,18,28,31,44,56,

68,75,80,110,120,
126

VSS P 4,6,12,15,23,32,

35,37,49,53,60,
65,71,74,87,112,
122

DESCRIPTION

5-V supply input voltage.

Ground pins.

Tab - 4 Power pins group

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