ASAHI KASEI AK4380 User Manual
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ASAHI KASEI [AK4380]
AK4380
100dB 24Bit 96kHz 2ch DAC
GENERAL DESCRIPTION
The AK4380 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator the AK4380 delivers a wide dynamic range while preserving linearity for
improved THD+N performance. The AK4380 integrates a combination of SCF and CTF filters, removing
the need for high cost external filters and increasing performance for systems with excessive clock jitter.
The 24 Bit word length and 96kHz sampling rate make this part ideal for a wide range of applications
including DVD and AC-3 systems. The AK4380 is offered in a space saving 16pin TSSOP package.
FEATURES
o Sampling Rates Ranging from 8kHz to 96kHz
o 128x Oversampling (Normal speed mode)
o 64x Oversampling (Double speed mode)
o 24Bit 8x FIR Digital Filter
o 2nd order Analog LPF
o On chip Buffer with Single End Output
o Digital de-emphasis for 32k, 44.1k and 48kHz sampling
o Soft mute
o I/F format: 24bit MSB justified, 24/20/16bit LSB justified, I
o Master clock: 256fs, 384fs, 512fs or 768fs (Normal speed mode)
128fs, 192fs, 256fs or 384fs (Double speed mode)
o THD+N: -88dB
o Dynamic Range: 100dB
o High Tolerance to Clock Jitter
o Power supply: 4.5 to 5.5V
o Space Saving 16 Pin TSSOP (6.4mm x 5.0mm) Package
2
S
P/S
SMUTE/CSN
DFS/CCLK
DIF0/CDTI
LRCK
BICK
SDTI
MS0018-E-01 2000/8
µP
Interface
Audio
Data
Interface
PDN
De-emphasis
Control
8X
Interpolator
8X
Interpolator
- 1 -
MCLK
Clock
Divider
∆Σ
Modulator
∆Σ
Modulator
LPF
LPF
VREF
VDD
VSS
VCOM
DZF
AOUTL
AOUTR
ASAHI KASEI [AK4380]
n Ordering Guide
AK4380VT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4380 Evaluation Board for AK4380
n Pin Layout
MCLK
BICK
SDTI
LRCK
PDN
SMUTE/CSN
DFS/CCLK
DIF0/CDTI
1
2
3
4
5
6
7
8
Top
View
PIN/FUNCTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 PDN I Power-Down Mode Pin
When at “L”, the AK4380 is in the power-down mode and is held in reset.
The AK4380 should always be reset upon power-up.
SMUTE I Soft Mute Pin in parallel mode
6
“H”: Enable, “L”: Disable
CSN I Chip Select Pin in serial mode
DFS I Double Speed Sampling Mode Pin in parallel mode
7
“L”: Normal Speed, “H”: Double Speed
CCLK I Control Data Input Pin in serial mode
DIF0 I Audio Data Interface Format Pin in parallel mode8
CDTI I Control Data Input Pin in serial mode
9P/S I
Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
10 AOUTR O Rch Analog Output Pin
11 AOUTL O Lch Analog Output Pin
12 VCOM O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with
a 10µF electrolytic cap.
13 VSS - Ground Pin
14 VDD - Power Supply Pin
15 VREF I Voltage Reference Input Pin
16 DZF O Data Zero Input Detect Pin
When SDTI of both channels follow a total 8192 LRCK cycles with “0” input
data, this spin goes to “H”.
Note: All input pins except pull-up pin should not be left floating.
16
15
14
13
12
11
10
DZF
VREF
VDD
VSS
VCOM
AOUTL
AOUTR
9
P/S
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ASAHI KASEI [AK4380]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter Symbol min max Units
Power Supply VDD -0.3 6.0 V
Input Current (any pins except for supplies) IIN Input Voltage VIND -0.3 VDD+0.3 V
Ambient Operating Temperature Ta -40 85
Storage Temperature Tstg -65 150
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
±10
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply VDD 4.5 5.0 5.5 V
Voltage Reference (Note 2) VREF 3.0 - VDD V
Note: 2. Analog output voltage scales with the voltage of VREF.
AOUT (typ@0dB) = 3.4Vpp×VREF/5.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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ASAHI KASEI [AK4380]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD = 5.0V; fs = 44.1kHz at DFS = “0”; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data;
Measurement frequency = 20Hz ∼ 20kHz at fs = 44.1kHz, 20Hz ∼ 40kHz at fs = 96kHz; R
≥10kΩ; unless otherwise
L
specified)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 3)
THD+N (0dB Output) fs = 44.1kHz
fs = 96kHz
Dynamic Range (-60dB Output, A-weight) fs = 44.1kHz
fs = 96kHz
S/N (A-weight) fs = 44.1kHz
fs = 96kHz
92
-
92
-
-88
-86
100
93
100
93
-82
dB
-
dB
dB
dB
dB
dB
Interchannel Isolation (1kHz) 90 100 dB
Interchannel Gain Mismatch 0.2 0.5 dB
DC Accuracy
Gain Drift 100 -
ppm/°C
Output Voltage (Note 4) 3.15 3.40 3.65 Vpp
Load Resistance 10
kΩ
Output Current 200 µA
Power Supplies
Power Supply Current (VDD)
Normal Operation (PDN = “H”)
Power-Down Mode (PDN = “L”) (Note 5)
14
10
22
100
mA
µA
Power Supply Rejection (Note 6) 40 dB
Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
4. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF,
AOUT (typ@0dB) = 3.4Vpp×VREF/5.
5. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.
6. PSR is applied to VDD with 1kHz, 100mV. VREF pin is held +5V.
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ASAHI KASEI [AK4380]
FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM0 = “1”, DEM1 = “0”)
Parameter Symbol min typ max Units
Digital filter
Passband ±0.05dB (Note 7)
-6.0dB
Stopband (Note 7) SB 24.25 kHz
Passband Ripple PR
Stopband Attenuation SA 54 dB
Group Delay (Note 8) GD - 19.1 - 1/fs
Digital Filter + LPF
Frequency Response 0 ∼ 20.0kHz
40.0kHz
Notes: 7. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
8. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both
channels to input register to the output of analog signal.
PB 0
FR -
- 22.05
± 0.2
-
± 0.3
20.0
-
± 0.02
-
-
kHz
kHz
dB
dB
dB
DIGITAL CHARACTERISTICS
(Ta = 25°C; VDD = 4.5 ∼ 5.5V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout = -80µA)
Low-Level Output Voltage (Iout = 80µA)
Input Leakage Current (Note 9) Iin - -
VIH
VIL
VOH
VOL
2.2
-
VDD-0.4
-
-
-
--
-
0.8
0.4
± 10
V
V
V
V
µA
Note: 9. P/S pin has internal pull-up device, normally 100kΩ.
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ASAHI KASEI [AK4380]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD = 4.5 ∼ 5.5V; CL = 20pF)
Parameter Symbol min typ max Units
Master Clock Frequency
Duty Cycle
LRCK Frequency
Duty Cycle
Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 10)
LRCK Edge to BICK “↑” (Note 10)
SDTI Hold Time
SDTI Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width (Note 11)
fCLK
dCLK
fs
Duty
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tPD 150 ns
2.048
40
8
45
1/128fs
1/64fs
70
70
40
40
40
40
200
80
80
40
40
150
50
50
11.2896 36.864
60
44.1 96
55
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 10. BICK rising edge must not occur at the same time as LRCK edge.
11. The AK4380 can be reset by PDN= “L” upon power up.
If MCLK frequency or DFS changes, the AK4380 should be reset by PDN pin or RSTN bit.
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ASAHI KASEI [AK4380]
n Timing Diagram
1/fCLK
MCLK
LRCK
BICK
tCLKH
tBCKH
1/fs
tBCK
Clock Timing
tCLKL
tBCKL
VIH
VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
VIH
VIL
VIH
VIL
LRCK
BICK
SDTI
tBLR
tLRB
tSDS
tSDH
Serial Interface Timing
VIH
VIL
VIH
VIL
VIH
VIL
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