arTech PEX1394B3 Service Manual

XIO2213B

XIO2213B PCI Express™ TO 1394b OHCI WITH 3-PORT PHY

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SCPS210F

October 2008–Revised May 2013

XIO2213B

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

Contents

1 Introduction ...................................................................................................................... 12

1.1 XIO2213B Features ....................................................................................................... 12

2 Overview .......................................................................................................................... 13

2.1 Related Documents ....................................................................................................... 14

2.2 Documents Conventions ................................................................................................. 15

2.3 Ordering Information ...................................................................................................... 15

2.4 Terminal Assignments .................................................................................................... 16

2.5 Terminal Descriptions ..................................................................................................... 24

3 Feature/Protocol Descriptions ............................................................................................. 31

3.1 Power-Up/Power-Down Sequencing .................................................................................... 31

3.1.1 Power-Up Sequence ........................................................................................... 32

3.1.2 Power-Down Sequence ........................................................................................ 33

3.2 XIO2213B Reset Features ............................................................................................... 34

3.3 PCI Express (PCIe) Interface ............................................................................................ 35

3.3.1 External Reference Clock ..................................................................................... 35

3.3.2 Beacon and Wake .............................................................................................. 35

3.3.3 Initial Flow Control Credits .................................................................................... 35

3.3.4 PCIe Message Transactions .................................................................................. 36

3.4 PCI Interrupt Conversion to PCIe Messages .......................................................................... 37

3.5 Two-Wire Serial-Bus Interface ........................................................................................... 38

3.5.1 Serial-Bus Interface Implementation ......................................................................... 38

3.5.2 Serial-Bus Interface Protocol .................................................................................. 39

3.5.3 Serial-Bus EEPROM Application ............................................................................. 41

3.5.4 Accessing Serial-Bus Devices Through Softwaree ........................................................ 43

3.6 Advanced Error Reporting Registers ................................................................................... 43

3.7 Data Error Forwarding Capability ....................................................................................... 43

3.8 General-Purpose I/O (GPIO) Interface ................................................................................. 44

3.9 Set Slot Power Limit Functionality ...................................................................................... 44

3.10 PCIe and PCI Bus Power Management ................................................................................ 44

3.11 1394b OHCI Controller Functionality ................................................................................... 46

3.11.1 1394b OHCI Power Management ............................................................................ 46

3.11.2 1394b OHCI and V

3.11.3 1394b OHCI and Reset Options .............................................................................. 46

3.11.4 1394b OHCI PCI Bus Master ................................................................................. 46

3.11.5 1394b OHCI Subsystem Identification ....................................................................... 47

3.11.6 1394b OHCI PME Support .................................................................................... 47

4 Classic PCI Configuration Space ......................................................................................... 48

4.1 Vendor ID Register ........................................................................................................ 49

4.2 Device ID Register ........................................................................................................ 49

4.3 Command Register ........................................................................................................ 49

4.4 Status Register ............................................................................................................ 51

4.5 Class Code and Revision ID Register .................................................................................. 52

4.6 Cache Line Size Register ................................................................................................ 52

4.7 Primary Latency Timer Register ......................................................................................... 52

4.8 Header Type Register .................................................................................................... 53

4.9 BIST Register .............................................................................................................. 53

4.10 Device Control Base Address Register ................................................................................. 53

4.11 Scratchpad RAM Base Address ......................................................................................... 54

4.12 Primary Bus Number Register ........................................................................................... 54

4.13 Secondary Bus Number Register ....................................................................................... 54

4.14 Subordinate Bus Number Register ...................................................................................... 55

........................................................................................ 46

AUX

XIO2213B

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4.15 Secondary Latency Timer Register ..................................................................................... 55

4.16 I/O Base Register ......................................................................................................... 55

4.17 I/O Limit Register .......................................................................................................... 56

4.18 Secondary Status Register ............................................................................................... 57

4.19 Memory Base Register ................................................................................................... 58

4.20 Memory Limit Register .................................................................................................... 58

4.21 Prefetchable Memory Base Register ................................................................................... 59

4.22 Prefetchable Memory Limit Register .................................................................................... 59

4.23 Prefetchable Base Upper 32 Bits Register ............................................................................. 60

4.24 Prefetchable Limit Upper 32 Bits Register ............................................................................. 60

4.25 I/O Base Upper 16 Bits Register ........................................................................................ 61

4.26 I/O Limit Upper 16 Bits Register ......................................................................................... 61

4.27 Capabilities Pointer Register ............................................................................................. 62

4.28 Interrupt Line Register .................................................................................................... 62

4.29 Interrupt Pin Register ..................................................................................................... 62

4.30 Bridge Control Register ................................................................................................... 63

4.31 PM Capability ID Register ................................................................................................ 65

4.32 Next Item Pointer Register ............................................................................................... 65

4.33 Power Management Capabilities Register ............................................................................. 66

4.34 Power Management Control/Status Register .......................................................................... 67

4.35 Power Management Bridge Support Extension Register ............................................................ 68

4.36 Power Management Data Register ..................................................................................... 68

4.37 MSI Capability ID Register ............................................................................................... 68

4.38 Next Item Pointer Register ............................................................................................... 69

4.39 MSI Message Control Register .......................................................................................... 69

4.40 MSI Message Lower Address Register ................................................................................. 70

4.41 MSI Message Upper Address Register ................................................................................. 70

4.42 MSI Message Data Register ............................................................................................. 71

4.43 SSID/SSVID Capability ID Register ..................................................................................... 71

4.44 Next Item Pointer Register ............................................................................................... 71

4.45 Subsystem Vendor ID Register .......................................................................................... 72

4.46 Subsystem ID Register ................................................................................................... 72

4.47 PCI Express Capability ID Register ..................................................................................... 72

4.48 Next Item Pointer Register ............................................................................................... 72

4.49 PCI Express Capabilities Register ...................................................................................... 73

4.50 Device Capabilities Register ............................................................................................. 74

4.51 Device Control Register .................................................................................................. 75

4.52 Device Status Register ................................................................................................... 76

4.53 Link Capabilities Register ................................................................................................ 77

4.54 Link Control Register ...................................................................................................... 78

4.55 Link Status Register ....................................................................................................... 79

4.56 Serial-Bus Data Register ................................................................................................. 79

4.57 Serial-Bus Word Address Register ...................................................................................... 79

4.58 Serial-Bus Slave Address Register ..................................................................................... 80

4.59 Serial-Bus Control and Status Register ................................................................................ 81

4.60 GPIO Control Register .................................................................................................... 82

4.61 GPIO Data Register ....................................................................................................... 83

4.62 Control and Diagnostic Register 0 ...................................................................................... 84

4.63 Control and Diagnostic Register 1 ...................................................................................... 86

4.64 PHY Control and Diagnostic Register 2 ................................................................................ 87

4.65 Subsystem Access Register ............................................................................................. 88

4.66 General Control Register ................................................................................................. 88

4.67 TI Proprietary Register .................................................................................................... 91

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

4.68 TI Proprietary Register .................................................................................................... 91

4.69 TI Proprietary Register .................................................................................................... 91

4.70 Arbiter Control Register ................................................................................................... 92

4.71 Arbiter Request Mask Register .......................................................................................... 93

4.72 Arbiter Time-Out Status Register ........................................................................................ 94

4.73 TI Proprietary Register .................................................................................................... 95

4.74 TI Proprietary Register .................................................................................................... 95

4.75 TI Proprietary Register .................................................................................................... 95

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5 PCIe Extended Configuration Space .................................................................................... 96

5.1 Advanced Error Reporting Capability ID Register ..................................................................... 96

5.2 Next Capability Offset/Capability Version Register ................................................................... 97

5.3 Uncorrectable Error Status Register .................................................................................... 97

5.4 Uncorrectable Error Mask Register ..................................................................................... 98

5.5 Uncorrectable Error Severity Register .................................................................................. 99

5.6 Correctable Error Status Register ..................................................................................... 101

5.7 Correctable Error Mask Register ....................................................................................... 102

5.8 Advanced Error Capabilities and Control Register .................................................................. 103

5.9 Header Log Register .................................................................................................... 103

5.10 Secondary Uncorrectable Error Status Register ..................................................................... 104

5.11 Secondary Uncorrectable Error Mask Register ...................................................................... 105

5.12 Secondary Uncorrectable Error Severity .............................................................................. 106

5.13 Secondary Error Capabilities and Control Register ................................................................. 107

5.14 Secondary Header Log Register ....................................................................................... 108

6 Memory-Mapped TI Proprietary Register Space ................................................................... 109

6.1 Device Control Map ID Register ....................................................................................... 109

6.2 Revision ID Register ..................................................................................................... 110

6.3 GPIO Control Register .................................................................................................. 110

6.4 GPIO Data Register ..................................................................................................... 111

6.5 Serial-Bus Data Register ................................................................................................ 112

6.6 Serial-Bus Word Address Register .................................................................................... 112

6.7 Serial-Bus Slave Address Register .................................................................................... 112

6.8 Serial-Bus Control and Status Register ............................................................................... 113

7 1394 OHCI PCI Configuration Space ................................................................................... 114

7.1 Vendor ID Register ...................................................................................................... 115

7.2 Device ID Register ....................................................................................................... 115

7.3 Command Register ...................................................................................................... 116

7.4 Status Register ........................................................................................................... 117

7.5 Class Code and Revision ID Registers ............................................................................... 118

7.6 Cache Line Size and Latency Timer Registers ...................................................................... 118

7.7 Header Type and BIST Registers ..................................................................................... 119

7.8 OHCI Base Address Register .......................................................................................... 119

7.9 TI Extension Base Address Register .................................................................................. 120

7.10 CIS Base Address Register ............................................................................................ 120

7.11 CIS Pointer Register ..................................................................................................... 121

7.12 Subsystem Vendor ID and Subsystem ID Registers ................................................................ 121

7.13 Power Management Capabilities Pointer Register .................................................................. 122

7.14 Interrupt Line and Interrupt Pin Registers ............................................................................ 122

7.15 Minimum Grant and Minimum Latency Registers ................................................................... 123

7.16 OHCI Control Register .................................................................................................. 123

7.17 Capability ID and Next Item Pointer Registers ....................................................................... 124

7.18 Power Management Capabilities Register ............................................................................ 124

7.19 Power Management Control and Status Register ................................................................... 125

7.20 Power Management Extension Registers ............................................................................ 125

XIO2213B

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7.21 PCI Miscellaneous Configuration Register ........................................................................... 125

7.22 Link Enhancement Control Register ................................................................................... 128

7.23 Subsystem Access Register ............................................................................................ 130

SCPS210F –OCTOBER 2008–REVISED MAY 2013

8 1394 OHCI Memory-Mapped Register Space ....................................................................... 131

8.1 OHCI Version Register .................................................................................................. 134

8.2 GUID ROM Register ..................................................................................................... 135

8.3 Asynchronous Transmit Retries Register ............................................................................. 136

8.4 CSR Data Register ...................................................................................................... 136

8.5 CSR Compare Register ................................................................................................. 137

8.6 CSR Control Register ................................................................................................... 137

8.7 Configuration ROM Header Register .................................................................................. 138

8.8 Bus Identification Register .............................................................................................. 138

8.9 Bus Options Register .................................................................................................... 139

8.10 GUID High Register ..................................................................................................... 140

8.11 GUID Low Register ...................................................................................................... 140

8.12 Configuration ROM Mapping Register ................................................................................ 141

8.13 Posted Write Address Low Register ................................................................................... 141

8.14 Posted Write Address High Register .................................................................................. 142

8.15 Vendor ID Register ...................................................................................................... 142

8.16 Host Controller Control Register ....................................................................................... 142

8.17 Self-ID Buffer Pointer Register ......................................................................................... 145

8.18 Self-ID Count Register .................................................................................................. 145

8.19 Isochronous Receive Channel Mask High Register ................................................................. 146

8.20 Isochronous Receive Channel Mask Low Register ................................................................. 148

8.21 Interrupt Event Register ................................................................................................. 148

8.22 Interrupt Mask Register ................................................................................................. 150

8.23 Isochronous Transmit Interrupt Event Register ...................................................................... 152

8.24 Isochronous Transmit Interrupt Mask Register ...................................................................... 153

8.25 Isochronous Receive Interrupt Event Register ....................................................................... 153

8.26 Isochronous Receive Interrupt Mask Register ....................................................................... 154

8.27 Initial Bandwidth Available Register ................................................................................... 154

8.28 Initial Channels Available High Register .............................................................................. 155

8.29 Initial Channels Available Low Register .............................................................................. 155

8.30 Fairness Control Register ............................................................................................... 156

8.31 Link Control Register .................................................................................................... 157

8.32 Node Identification Register ............................................................................................ 158

8.33 PHY Control Register ................................................................................................... 159

8.34 Isochronous Cycle Timer Register ..................................................................................... 160

8.35 Asynchronous Request Filter High Register ......................................................................... 160

8.36 Asynchronous Request Filter Low Register .......................................................................... 163

8.37 Physical Request Filter High Register ................................................................................ 163

8.38 Physical Request Filter Low Register ................................................................................. 166

8.39 Physical Upper Bound Register (Optional Register) ................................................................ 166

8.40 Asynchronous Context Control Register .............................................................................. 167

8.41 Asynchronous Context Command Pointer Register ................................................................. 168

8.42 Isochronous Transmit Context Control Register ..................................................................... 169

8.43 Isochronous Transmit Context Command Pointer Register ........................................................ 170

8.44 Isochronous Receive Context Control Register ...................................................................... 170

8.45 Isochronous Receive Context Command Pointer Register ......................................................... 172

8.46 Isochronous Receive Context Match Register ....................................................................... 172

9 1394 OHCI Memory-Mapped TI Extension Register Space ..................................................... 174

9.1 Digital Video (DV) and MPEG2 Timestamp Enhancements ....................................................... 174

9.2 Isochronous Receive Digital Video Enhancements ................................................................. 175

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

9.3 Isochronous Receive Digital Video Enhancement Registers ...................................................... 175

9.4 Link Enhancement Control Registers ................................................................................. 176

9.5 Timestamp Offset Registers ............................................................................................ 178

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10 Physical Layer (PHY) Section ............................................................................................ 179

10.1 PHY Section Register Configuration .................................................................................. 180

10.2 PHY Section Application Information .................................................................................. 187

10.2.1 Power Class Programming .................................................................................. 187

10.2.2 Power-Up Reset ............................................................................................... 188

10.2.3 Crystal Oscillator Selection .................................................................................. 188

10.2.4 Bus Reset ...................................................................................................... 189

11 Electrical Characteristics .................................................................................................. 190

11.1 Absolute Maximum Ratings ............................................................................................ 190

11.2 Recommended Operating Conditions ................................................................................. 190

11.3 PCIe Differential Transmitter Output Ranges ........................................................................ 191

11.4 PCIe Differential Receiver Input Ranges ............................................................................. 193

11.5 PCIe Differential Reference Clock Input Ranges .................................................................... 194

11.6 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O) .............................. 194

11.7 Electrical Characteristics Over Recommended Operating Conditions (PHY Port Driver) ...................... 195

11.8 Switching Characteristics for PHY Port Driver ....................................................................... 195

11.9 Electrical Characteristics Over Recommended Operating Conditions PHY Port Receiver .................... 196

11.10 Jitter/Skew Characteristics for 1394a PHY Port Receiver ......................................................... 196

11.11 Operating, Timing, and Switching Characteristics of XI ........................................................... 196

11.12 Electrical Characteristics Over Recommended Operating Conditions

(1394a Miscellaneous I/O) .............................................................................................. 196

12 Glossary ......................................................................................................................... 196

XIO2213B

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

List of Figures

3-1 XIO2213B Block Diagram....................................................................................................... 31

3-2 Power-Up Sequence............................................................................................................. 32

3-3 Power-Down Sequence ......................................................................................................... 33

3-4 PCIe Assert_INTA Message.................................................................................................... 37

3-5 PCIe Deassert_INTX Message................................................................................................. 37

3-6 Serial EEPROM Application .................................................................................................... 38

3-7 Serial-Bus Start/Stop Conditions and Bit Transfers.......................................................................... 39

3-8 Serial-Bus Protocol Acknowledge.............................................................................................. 39

3-9 Serial-Bus Protocol Byte Write ................................................................................................. 40

3-10 Serial-Bus Protocol Byte Read................................................................................................. 40

3-11 Serial-Bus Protocol Multibyte Read............................................................................................ 41

11-1 Test Load Diagram ............................................................................................................. 195

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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List of Tables

2-1 7 × 7 Terminals Sorted By Ball Number....................................................................................... 16

2-2 7 × 7 Terminals Sorted Alphanumerically..................................................................................... 18

2-3 12 × 12 Terminals Sorted By Ball Number.................................................................................... 20

2-4 12 × 12 Terminals Sorted Alphanumerically.................................................................................. 22

2-5 Power-Supply Terminals ........................................................................................................ 25

2-6 Ground Terminals ................................................................................................................ 26

2-7 PCIe Terminals ................................................................................................................... 26

2-8 Clock Terminals .................................................................................................................. 26

2-9 1394 Terminals ................................................................................................................... 27

2-10 Reserved Terminals.............................................................................................................. 29

2-11 Miscellaneous Terminals........................................................................................................ 29

3-1 XIO2213B Reset Options ....................................................................................................... 34

3-2 Initial Flow Control Credit Advertisements.................................................................................... 35

3-3 Messages Supported by Bridge................................................................................................ 36

3-4 EEPROM Register Loading Map............................................................................................... 41

3-5 Registers Used To Program Serial-Bus Devices............................................................................. 43

3-6 Clocking In Low Power States.................................................................................................. 44

3-7 1394b OHCI Configuration Register Map..................................................................................... 46

3-8 1394 OHCI Memory Command Options ...................................................................................... 47

4-1 Classic PCI Configuration Register Map...................................................................................... 48

4-2 Command Register Description ............................................................................................... 50

4-3 Status Register Description .................................................................................................... 51

4-4 Class Code and Revision ID Register Description .......................................................................... 52

4-5 Device Control Base Address Register Description ........................................................................ 53

4-6 Device Control Base Address Register Description ........................................................................ 54

4-7 I/O Base Register Description ................................................................................................. 55

4-8 I/O Limit Register Description .................................................................................................. 56

4-9 Secondary Status Register Description ...................................................................................... 57

4-10 Memory Base Register Description ........................................................................................... 58

4-11 Memory Limit Register Description ............................................................................................ 58

4-12 Prefetchable Memory Base Register Description ........................................................................... 59

4-13 Prefetchable Memory Limit Register Description ............................................................................ 59

4-14 Prefetchable Base Upper 32 Bits Register Description .................................................................... 60

4-15 Prefetchable Limit Upper 32 Bits Register Description ..................................................................... 60

4-16 I/O Base Upper 16 Bits Register Description ................................................................................ 61

4-17 I/O Limit Upper 16 Bits Register Description ................................................................................ 61

4-18 Bridge Control Register Description ........................................................................................... 63

4-19 Power Management Capabilities Register Description ..................................................................... 66

4-20 Power Management Control/Status Register Description .................................................................. 67

4-21 PM Bridge Support Extension Register Description ........................................................................ 68

4-22 MSI Message Control Register Description .................................................................................. 69

4-23 MSI Message Lower Address Register Description ........................................................................ 70

4-24 MSI Message Data Register Description ..................................................................................... 71

4-25 PCI Express Capabilities Register Description .............................................................................. 73

4-26 Device Capabilities Register Description ..................................................................................... 74

4-27 Device Control Register Description .......................................................................................... 75

4-28 Device Status Register Description ........................................................................................... 76

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

4-29 Link Capabilities Register Description ........................................................................................ 77

4-30 Link Control Register Description ............................................................................................. 78

4-31 Link Status Register Description .............................................................................................. 79

4-32 Serial-Bus Slave Address Register Descriptions ............................................................................ 80

4-33 Serial-Bus Control and Status Register Description ........................................................................ 81

4-34 GPIO Control Register Description ............................................................................................ 82

4-35 GPIO Data Register Description ............................................................................................... 83

4-36 Control and Diagnostic Register 0 Description .............................................................................. 84

4-37 Control and Diagnostic Register 1 Description .............................................................................. 86

4-38 Control and Diagnostic Register 2 Description .............................................................................. 87

4-39 Subsystem Access Register Description ..................................................................................... 88

4-40 General Control Register Description ......................................................................................... 89

4-41 Arbiter Control Register Description .......................................................................................... 92

4-42 Arbiter Request Mask Register Description .................................................................................. 93

4-43 Arbiter Time-Out Status Register Description ............................................................................... 94

5-1 PCIe Extended Configuration Register Map.................................................................................. 96

5-2 Uncorrectable Error Status Register Description ............................................................................ 97

5-3 Uncorrectable Error Mask Register Description ............................................................................. 98

5-4 Uncorrectable Error Severity Register Description .......................................................................... 99

5-5 Correctable Error Status Register Description ............................................................................. 101

5-6 Correctable Error Mask Register Description .............................................................................. 102

5-7 Advanced Error Capabilities and Control Register Description .......................................................... 103

5-8 Secondary Uncorrectable Error Status Register Description ............................................................. 104

5-9 Secondary Uncorrectable Error Mask Register Description .............................................................. 105

5-10 Secondary Uncorrectable Error Severity Register Description .......................................................... 106

5-11 Secondary Error Capabilities and Control Register Description ......................................................... 107

5-12 Secondary Header Log Register Description .............................................................................. 108

6-1 Device Control Memory Window Register Map............................................................................. 109

6-2 GPIO Control Register Description .......................................................................................... 110

6-3 GPIO Data Register Description ............................................................................................. 111

6-4 Serial-Bus Slave Address Register Descriptions .......................................................................... 112

6-5 Serial-Bus Control and Status Register Description ....................................................................... 113

7-1 1394 OHCI Configuration Register Map..................................................................................... 114

7-2 Command Register Description .............................................................................................. 116

7-3 Status Register Description ................................................................................................... 117

7-4 Class Code and Revision ID Registers Description ....................................................................... 118

7-5 Latency Timer and Class Cache Line Size Registers Description ...................................................... 118

7-6 Header Type and BIST Registers Description ............................................................................. 119

7-7 OHCI Base Address Register Description .................................................................................. 119

7-8 TI Base Address Register Description ...................................................................................... 120

7-9 Subsystem Vendor ID and Subsystem ID Registers Description ........................................................ 121

7-10 Interrupt Line and Interrupt Pin Registers Description .................................................................... 122

7-11 Minimum Grant and Minimum Latency Registers Description ........................................................... 123

7-12 OHCI Control Register Description .......................................................................................... 123

7-13 Capability ID and Next Item Pointer Registers Description ............................................................... 124

7-14 Power Management Capabilities Register Description ................................................................... 124

7-15 Power Management Control and Status Register Description ........................................................... 125

7-16 Power Management Extension Registers Description .................................................................... 125

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

7-17 PCI Miscellaneous Configuration Register ................................................................................. 127

7-18 Link Enhancement Control Register Description .......................................................................... 129

7-19 Subsystem Access Register Description ................................................................................... 130

8-1 OHCI Register Map............................................................................................................. 131

8-2 OHCI Version Register Description .......................................................................................... 134

8-3 GUID ROM Register Description ............................................................................................ 135

8-4 Asynchronous Transmit Retries Register Description ..................................................................... 136

8-5 CSR Control Register Description ........................................................................................... 137

8-6 Configuration ROM Header Register Description .......................................................................... 138

8-7 Bus Options Register Description ............................................................................................ 139

8-8 Configuration ROM Mapping Register Description ........................................................................ 141

8-9 Posted Write Address Low Register Description .......................................................................... 141

8-10 Posted Write Address High Register Description .......................................................................... 142

8-11 Host Controller Control Register Description ............................................................................... 144

8-12 Self-ID Count Register Description .......................................................................................... 145

8-13 Isochronous Receive Channel Mask High Register Description ......................................................... 146

8-14 Isochronous Receive Channel Mask Low Register Description ......................................................... 148

8-15 Interrupt Event Register Description ......................................................................................... 149

8-16 Interrupt Mask Register Description ......................................................................................... 150

8-17 Isochronous Transmit Interrupt Event Register Description .............................................................. 152

8-18 Isochronous Receive Interrupt Event Register Description ............................................................... 153

8-19 Initial Bandwidth Available Register Description ........................................................................... 154

8-20 Initial Channels Available High Register Description ...................................................................... 155

8-21 Initial Channels Available Low Register Description ...................................................................... 155

8-22 Fairness Control Registre Description ...................................................................................... 156

8-23 Link Control Register Description ............................................................................................ 157

8-24 Node Identification Register Description .................................................................................... 158

8-25 PHY Control Register Description ........................................................................................... 159

8-26 Isochronous Cycle Timer Register Description ............................................................................ 160

8-27 Asynchronous Request Filter High Register Description ................................................................. 161

8-28 Asynchronous Request Filter Low Register Description .................................................................. 163

8-29 Physical Request Filter High Register Description ........................................................................ 164

8-30 Physical Request Filter Low Register Description ......................................................................... 166

8-31 Asynchronous Context Control Register Description ...................................................................... 167

8-32 Asynchronous Context Command Pointer Register Description ......................................................... 168

8-33 Isochronous Transmit Context Control Register Description ............................................................. 169

8-34 Isochronous Receive Context Control Register Description ............................................................. 171

8-35 Isochronous Receive Context Match Register Description ............................................................... 172

9-1 TI Extension Register Map .................................................................................................... 174

9-2 Isochronous Receive Digital Video Enhancement Registers Description .............................................. 175

9-3 Link Enhancement Control Registers Description ......................................................................... 176

9-4 Timestamp Offset Registers Description .................................................................................... 178

10-1 Base Register Description .................................................................................................... 181

10-2 Base Register Field Description .............................................................................................. 181

10-3 Page 0 (Port Status) Register Description .................................................................................. 183

10-4 Page 0 (Port Status) Register Field Description ........................................................................... 184

10-5 Page 1 (Vendor ID) Register Configuration ................................................................................ 185

10-6 Page 1 (Vendor ID) Register Field Descriptions ........................................................................... 186

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

10-7 Page 7 (Vendor Dependent) Register Configuration ...................................................................... 187

10-8 Page 7 (Vendor Dependent) Register Field Descriptions ................................................................ 187

10-9 Power Class Register Description ........................................................................................... 187

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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XIO2213B

PCI Express™ TO 1394b OHCI WITH 3-PORT PHY

Check for Samples: XIO2213B

1 Introduction

1.1 XIO2213B Features

123

• Full ×1 PCI Express™ (PCIe) Throughput

• Fully Compliant With PCI Express Base Specification, Revision 1.1

• Utilizes 100-MHz Differential PCI Express Common Reference Clock or 125-MHz SingleEnded Reference Clock • EEPROM Configuration Support to Load Global

• Fully Supports Provisions of IEEE Std P1394b2002 • Support for D1, D2, D3

• Fully Compliant With Provisions of IEEE Std • Active-State Link Power Management Saves 1394-1995 for a High-Performance Serial Bus Power When Packet Activity on the PCI and IEEE Std 1394a-2000 Express Link Is Idle, Using Both L0s and L1

• Fully Compliant With 1394 Open Host Controller Interface (OHCI) Specification, • Eight 3.3-V Multifunction General-Purpose I/O Revision 1.1 and Revision 1.2 Draft (GPIO) Terminals

• Three IEEE Std 1394b Fully Compliant Cable

Ports at 100M Bit/s, 200M Bit/s, 400M Bit/s, and 800M Bit/s

• Cable Ports Monitor Line Conditions for Active Connection to Remote Node

• Cable Power Presence Monitoring

Unique ID for 1394 Fabric

hot

States

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2OHCI-Lynx is a trademark of Texas Instruments. 3PCI Express is a trademark of PCI-SIG.

XIO2213B

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2 Overview

The Texas Instruments XIO2213B is a single-function PCI Express™ (PCIe) to PCI local bus translation bridge, where the PCI bus interface is internally connected to a 1394b open host controller/link-layer controller with a 3-port 1394b physical layer (PHY). When the XIO2213B is properly configured, this solution provides full PCIe and 1394b functionality and performance.

The TI XIO2213B is a PCIe to PCI translation bridge, where the PCI bus interface is internally connected to a 1394b open host controller/link-layer controller with a 3-port 1394b PHY. The PCIe to PCI translation bridge is fully compatible with the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The 1394b OHCI controller function is fully compatible with IEEE Std 1394b and the latest 1394 Open Host Controller Interface (OHCI) Specification.

The XIO2213B simultaneously supports up to four posted write transactions, four nonposted transactions, and four completion transactions pending in each direction at any time. Each posted write data queue and completion data queue can store up to 8K bytes of data. The nonposted data queues can store up to 128 bytes of data.

The PCIe interface supports a ×1 link operating at full 250 Mbit/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting capability including ECRC as defined in the PCI Express Base Specification, Revision 1.1. Supplemental firmware or software is required to fully utilize both of these features.

Robust pipeline architecture is implemented to minimize system latency. If parity errors are detected, packet poisoning is supported for both upstream and downstream operations.

SCPS210F –OCTOBER 2008–REVISED MAY 2013

PCIe power management (PM) features include active-state link PM, PME mechanisms, and all conventional PCI D states. If the active-state link PM is enabled, the link automatically saves power when idle using the L0s and L1 states. PM active-state NAK, PM PME, and PME-to-ACK messages are supported. The bridge is compliant with the latest PCI Bus Power Management Specification and provides several low-power modes, which enable the host power system to further reduce power consumption

Eight general-purpose inputs and outputs (GPIOs), configured through accesses to the PCIe configuration space, allow for further system control and customization.

Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The device provides physical write posting and a highly tuned physical data path for SBP-2 performance. The device is capable of transferring data between the PCIe bus and the 1394 bus at 100M bit/s, 200M bit/s, 400M bit/s, and 800M bit/s. The device provides three 1394 ports that have separate cable bias (TPBIAS).

As required by the 1394 Open Host Controller Interface (OHCI) Specification, internal control registers are memory mapped and nonprefetchable. This configuration header is accessed through configuration cycles specified by PCIe, and it provides plug-and-play (PnP) compatibility.

The PHY provides the digital and analog transceiver functions needed to implement a 3-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. An optional external 2-wire serial EEPROM interface is provided to load the global unique ID for the 1394 fabric.

The XIO2213B requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbit/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.

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To ensure that the XIO2213B conforms to IEEE Std 1394b-2002, the BMODE terminal must be asserted. The BMODE terminal does not select the cable-interface mode of operation. BMODE selects the internal PHY-section/LLC-section interface mode of operation and affects the arbitration modes on the cable. BMODE must be pulled high during normal operation.

Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They can be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the XIO2213B, this bit can only be set by a write to the PHY register set. If a node is to be a contender for IRM or BM, the node software must set this bit in the PHY register set.

2.1 Related Documents

• PCI Express™ to PCI/PCI-X Bridge Specification, Revision 1.0

• PCI Express™ Base Specification, Revision 1.1

• PCI Express™ Card Electromechanical Specification, Revision 1.1

• PCI Local Bus Specification, Revision 2.3 and Revision 3.0

• PCI-to-PCI Bridge Architecture Specification, Revision 1.1

• PCI Bus Power-Management Interface Specification, Revision 1.1 and Revision 1.2

• 1394 Open Host Controller Interface (OHCI) Specification, Release 1.2

• High-Performance Serial Bus, IEEE Std 1394-1995

• High-Performance Serial Bus, Amendment 1, IEEE Std 1394a-2000

• High-Performance Serial Bus, Amendment 2, IEEE Std 1394b-2002

• Express Card Standard, Release 1.0 and Release 1.1

• PCI Express™ Jitter and BER white paper

• PCI Mobile Design Guide, Revision 1.1

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2.2 Documents Conventions

Throughout this data manual, several conventions are used to convey information. These conventions are:

• To identify a binary number or field, a lower-case b follows the numbers. For example, 000b is a 3-bit binary field.

• To identify a hexadecimal number or field, a lower-case h follows the numbers. For example, 8AFh is a 12-bit hexadecimal field.

• All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format.

• If the signal or terminal name has a bar above the name (for example, GRST), this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b.

• Differential signal names end with P, N, +, or – designators. The P or + designators signify the positive signal associated with the differential pair. The N or – designators signify the negative signal associated with the differential pair.

• RSVD indicates that the referenced item is reserved.

• In Sections 4 through 6, the configuration space for the bridge is defined. For each register bit, the software access method is identified in an access column. The legend for this access column includes the following entries:

– R: Read access by software – U: Updates by the bridge internal hardware – W: Write access by software – C: Clear an asserted bit with a write back of 1b by software. Write of zero to the field has no effect. – S: The field may be set by a write of one. Write of zero to the field has no effect. – NA: Not accessible or not applicable

• The XIO2213B consists of a PCIe to PCI translation bridge, where the secondary PCI bus is internally connected to a 1394b OHCI with a 3-port PHY. When describing functionality that is specific to the PCIe to PCI translation bridge, the term bridge is used to reduce text. The term 1394b OHCI is used to reduce text when describing the 1394b OHCI with 3-port PHY function.

• LLC refers to the 1394 link layer controller.

SCPS210F –OCTOBER 2008–REVISED MAY 2013

2.3 Ordering Information

PACKAGE VOLTAGE ORDERABLE PART NUMBER

167-terminal (Lead-Free) PBGA – ZAY 3.3-V and 1.5-V power terminals

168-terminal (Lead-Free) BGA – ZAJ 3.3-V and 1.5-V power terminals XIO2213BZAJ

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2.4 Terminal Assignments

The XIO2213B is packaged in a 168-ball BGA (ZAJ) and a 167-ball PBGA (ZAY). For the ZAJ package

Table 2-1 lists the terminals sorted by ball number. Table 2-2 lists the terminals in alphanumerical order.

For the ZAY packageTable 2-3 lists the terminals sorted by ball number. Table 2-4 lists the terminals in alphanumerical order.

Table 2-1. 7 × 7 Terminals Sorted By Ball Number

BALL NO. TERMINAL NAME

A01 VDDA_33 A02 CNA A03 TESTM A04 RXN A05 RXP A06 PHY_RESET A07 TXN A08 TXP A09 PC1 A10 REF1_PCIE A11 REF0_PCIE A12 TPBIAS2 A13 TPA2+ B01 REFCLK+ B03 PD B04 VDDA_15 B05 VDDA_15 B06 BMODE B07 VREG_PD B08 PC2 B09 VDD_33_COMB B10 VDD_33_COM_IO B11 VDD_15_COMB B12 PERST B13 TPA2– C01 REFCLK– C02 LINKON_L C03 LPS_L C04 VDDA_15 C05 VDDA_15 C06 VSSA_PCIE C07 VDD_15 C08 VDDA_33 C09 VDD_33_AUX C10 RSVD C11 PC0 C12 GRST C13 TPB2+ D01 LREQ_L D02 LKON/DS2_P D03 LPS_P D04 VSSA D05 VSSA_PCIE D06 VSSA_PCIE

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Table 2-1. 7 × 7 Terminals Sorted By Ball

Number (continued)

BALL NO. TERMINAL NAME

D07 VSSA D08 DVDD_CORE D09 DVDD_CORE D10 VDD_33 D11 RSVD D12 RSVD D13 TPB2– E01 LREQ_P E02 PINT_L E03 PINT_P E04 DVDD_3.3 E05 GND E06 VSSA_PCIE E07 VSS E08 VSS E09 VSSA E10 AVDD_3.3 E11 RSVD E12 TPBIAS1 E13 TPA1+ F01 CTL0 F02 PCLK_P F03 PCLK_L F04 GND F05 GND F06 GND F07 GND F08 GND F09 GND F10 AVDD_3.3 F11 RSVD F12 RSVD F13 TPA1– G01 CTL1 G02 LCLK_P G03 LCLK_L G04 GND G05 GND G06 GND G07 GND G08 GND G09 GND G10 GND G11 REFCLK_SEL G12 SCL

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Table 2-1. 7 × 7 Terminals Sorted By Ball Table 2-1. 7 × 7 Terminals Sorted By Ball

Number (continued) Number (continued)

BALL NO. TERMINAL NAME BALL NO. TERMINAL NAME

G13 TPB1+ L01 D6 H01 D0 L02 GPIO2 H02 D1 L03 VDD_33 H03 VDD_15 L04 GPIO3 H04 GND L05 GPIO7 H05 GND L06 VDD_15 H06 GND L07 GND H07 GND L08 VDD_33 H08 GND L09 CYCLEOUT H09 VDD_15 L10 RSVD H10 AVDD_3.3 L11 RSVD H11 SDA L12 RSVD H12 CLKREQ L13 TPB0+ H13 TPB1– M01 D7 J01 D3 M02 GPIO0 J02 D2 M03 GPIO4 J03 VDD_15 M04 AVDD_3.3 J05 GND M05 XO J06 GND M06 GPIO6 J07 GND M07 DS1 J08 GND M08 OHCI_PME J09 VDD_15 M09 RSVD J10 AVDD_3.3 M10 SE J11 RSVD M11 RSVD J12 TPBIAS0 M12 RSVD J13 TPA0+ M13 TPB0– K01 D5 N01 GPIO1 K02 D4 N02 R1 K03 VDD_33 N03 R0 K04 GPIO5 N04 PLLGND K05 DVDD_3.3 N05 XI K06 DVDD_3.3 N06 PLLVDD_CORE K07 GND N07 PLLVDD_3.3 K08 VDD_33 N08 DS0 K09 DVDD_CORE N09 CPS K10 RSVD N10 SM K11 RSVD N11 RSVD K12 RSVD N12 RSVD K13 TPA0–

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Table 2-2. 7 × 7 Terminals Sorted

Alphanumerically

BALL NO. TERMINAL NAME

E10 AVDD_3.3 F10 AVDD_3.3 H10 AVDD_3.3 J10 AVDD_3.3 M04 AVDD_3.3 B06 BMODE H12 CLKREQ A02 CNA N09 CPS F01 CTL0 G01 CTL1 L09 CYCLEOUT H01 D0 H02 D1 J02 D2 J01 D3 K02 D4 K01 D5 L01 D6 M01 D7 N08 DS0 M07 DS1 E04 DVDD_3.3 K05 DVDD_3.3 K06 DVDD_3.3 D08 DVDD_CORE D09 DVDD_CORE K09 DVDD_CORE E05 GND F04 GND F05 GND F06 GND F07 GND F08 GND F09 GND G04 GND G05 GND G06 GND G07 GND G08 GND G09 GND G10 GND H04 GND H05 GND H06 GND H07 GND H08 GND J04 GND J05 GND J06 GND

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Table 2-2. 7 × 7 Terminals Sorted

Alphanumerically (continued)

BALL NO. TERMINAL NAME

J07 GND

J08 GND K07 GND L07 GND M02 GPIO0 N01 GPIO1 L02 GPIO2 L04 GPIO3 M03 GPIO4 K04 GPIO5 M06 GPIO6 L05 GPIO7 C12 GRST G03 LCLK_L G02 LCLK_P C02 LINKON_L D02 LKON/DS2_P C03 LPS_L D03 LPS_P D01 LREQ_L E01 LREQ_P M08 OHCI_PME C11 PC0 A09 PC1 B08 PC2 F03 PCLK_L F02 PCLK_P B03 PD B12 PERST E02 PINT_L E03 PINT_P N04 PLLGND N07 PLLVDD_3.3 N06 PLLVDD_CORE N03 R0 N02 R1 A11 REF0_PCIE A10 REF1_PCIE C01 REFCLK– G11 REFCLK_SEL B01 REFCLK+ A06 PHY_RESET C10 RSVD D11 RSVD D12 RSVD E11 RSVD F11 RSVD F12 RSVD

J11 RSVD K10 RSVD

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Table 2-2. 7 × 7 Terminals Sorted Table 2-2. 7 × 7 Terminals Sorted

Alphanumerically (continued) Alphanumerically (continued)

BALL NO. TERMINAL NAME BALL NO. TERMINAL NAME

K11 RSVD A07 TXN K12 RSVD A08 TXP L10 RSVD C07 VDD_15 L11 RSVD H03 VDD_15 L12 RSVD H09 VDD_15 M09 RSVD J03 VDD_15 M11 RSVD J09 VDD_15 M12 RSVD L06 VDD_15 N11 RSVD B11 VDD_15_COMB N12 RSVD C09 VDD_33_AUX N13 RSVD D10 VDD_33 A04 RXN K03 VDD_33 A05 RXP K08 VDD_33 G12 SCL L03 VDD_33 H11 SDA L08 VDD_33 M10 SE B10 VDD_33_COM_IO N10 SM B09 VDD_33_COMB A03 TESTM B04 VDDA_15 B07 VREG_PD B05 VDDA_15 K13 TPA0– C04 VDDA_15 J13 TPA0+ C05 VDDA_15 F13 TPA1– A01 VDDA_33 E13 TPA1+ C08 VDDA_33 B13 TPA2– E07 VSS A13 TPA2+ E08 VSS M13 TPB0– D04 VSSA L13 TPB0+ D07 VSSA H13 TPB1– E09 VSSA G13 TPB1+ C06 VSSA_PCIE D13 TPB2– D05 VSSA_PCIE C13 TPB2+ D06 VSSA_PCIE J12 TPBIAS0 E06 VSSA_PCIE E12 TPBIAS1 N05 XI A12 TPBIAS2 M05 XO

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Table 2-3. 12 × 12 Terminals Sorted By Ball

Number

BALL NO. TERMINAL NAME

A01 REFCLK+ A02 CNA A03 RXN A04 RXP A05 BMODE A06 VREG_PD A07 VSS A08 TXN A09 TXP A10 VDDA_33 A11 PC2 A12 REF1_PCIE A13 REF0_PCIE A14 VSS B01 REFCLK– B02 TESTM B03 PD B04 PHY_RESET B05 VDDA_15 B06 VSSA B07 VDDA_15 B08 VDD_15 B09 VDDA_15 B10 VDDA_15 B11 VDD_33_COMB B12 VDD_33_AUX B13 PERST B14 TPA2+ C01 LPS_L C02 LPS_P C03 VDDA_33 C04 VSSA_PCIE C05 VSSA_PCIE C06 VSSA_PCIE C07 VSSA_PCIE C08 DVDD_3.3 C09 DVDD_CORE C10 VSSA C11 VDD_33_COM_IO C12 VDD_15_COMB C13 GRST C14 TPA2– D01 LKON/DS2_P D02 PINT_L D03 PINT_P D12 RSVD D13 RSVD D14 TPB2+ E01 LINKON_L E02 LREQ_P

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Table 2-3. 12 × 12 Terminals Sorted By Ball

Number (continued)

BALL NO. TERMINAL NAME

E03 VDD_33 E06 GND E07 GND E08 PC1 E09 PC0 E10 AVDD_3.3 E12 RSVD E13 TPBIAS2 E14 TPB2– F01 PCLK_P F02 LREQ_L F03 DVDD_CORE F05 VSSA F06 GND F07 GND F08 GND F09 GND F10 AVDD_3.3 F12 RSVD F13 RSVD F14 TPA1+ G01 PCLK_L G02 LCLK_L G03 VDD_15 G05 GND G06 GND G07 GND G08 GND G09 GND G10 VDD_33 G12 RSVD G13 TPBIAS1 G14 TPA1– H01 CTL0 H02 LCLK_P H03 VDD_15 H05 GND H06 GND H07 GND H08 GND H09 GND H10 VDD_33 H12 SDA H13 REFCLK_SEL H14 TPB1+

J01 CTL1

J02 D0

J03 DVDD_3.3

J05 GND

J06 GND

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Table 2-3. 12 × 12 Terminals Sorted By Ball Table 2-3. 12 × 12 Terminals Sorted By Ball

Number (continued) Number (continued)

BALL NO. TERMINAL NAME BALL NO. TERMINAL NAME

J07 GND M10 AVDD_3.3 J08 GND M11 RSVD J09 AVDD_3.3 M12 RSVD J10 VDD_33 M13 RSVD J12 CLKREQ M14 TPB0+ J13 SCL N01 R0 J14 TPB1– N02 GPIO1 K01 D2 N03 GPIO3 K02 D1 N04 GPIO4 K03 DVDD_3.3 N05 PLLGND K05 GND N06 GPIO7 K06 GND N07 PLLVDD_3.3 K07 GND N08 CYCLEOUT K08 GND N09 DS0 K09 AVDD_3.3 N10 RSVD K10 VDD_15 N11 RSVD K12 RSVD N12 RSVD K13 TPBIAS0 N13 RSVD K14 TPA0+ N14 TPB0– L01 D3 P01 GPIO0 L02 D4 P02 GPIO2 L03 D5 P03 RSVD L12 RSVD P04 XI L13 RSVD P05 GPIO5 L14 TPA0– P06 GPIO6 M01 R1 P07 VDD_15 M02 D6 P08 OHCI_PME M03 D7 P09 DS1 M04 AVDD_3.3 P10 RSVD M05 VDD_33 P11 RSVD M06 VDD_15 P12 CPS M07 PLLVDD_CORE P13 SE M08 RSVD P14 SM M09 DVDD_CORE

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Table 2-4. 12 × 12 Terminals Sorted

Alphanumerically

TERMINAL NAME BALL NO.

AVDD_3.3 E10 AVDD_3.3 F10 AVDD_3.3 J09 AVDD_3.3 K09 AVDD_3.3 M10 AVDD_3.3 M04 BMODE A05 CLKREQ J12 CNA A02 CPS P12 CTL0 H01 CTL1 J01 CYCLEOUT N08 D0 J02 D1 K02 D2 K01 D3 L01 D4 L02 D5 L03 D6 M02 D7 M03 DS0 N09 DS1 P09 DVDD_3.3 C08 DVDD_3.3 J03 DVDD_3.3 K03 DVDD_CORE C09 DVDD_CORE F03 DVDD_CORE M09 GND E06 GND E07 GND F06 GND F07 GND F08 GND F09 GND G05 GND G06 GND G07 GND G08 GND G09 GND H05 GND H06 GND H07 GND H08 GND H09 GND J05

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Table 2-4. 12 × 12 Terminals Sorted

Alphanumerically (continued)

TERMINAL NAME BALL NO.

GND J06 GND J07 GND J08 GND K05 GND K06 GND K07 GND K08 GPIO0 P01 GPIO1 N02 GPIO2 P02 GPIO3 N03 GPIO3 N04 GPIO5 P05 GPIO6 P06 GPIO7 N06 GRST C13 LCLK_L G02 LCLK_P H02 LINKON_L E01 LKON/DS2_P D01 LPS_L C01 LPS_P C02 LREQ_L F02 LREQ_P E02 OHCI_PME P08 PC0 E09 PC1 E08 PC2 A11 PCLK_L G01 PCLK_P F01 PD B03 PERST B13 PINT_L D02 PINT_P D03 PLLGND N05 PLLVDD_3.3 N07 PLLVDD_CORE M07 R0 N01 R1 M01 REF0_PCIE A13 REF1_PCIE A12 REFCLK- B01 REFCLK_SEL H13 REFCLK+ A01 PHY_RESET B04 RSVD G12

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Table 2-4. 12 × 12 Terminals Sorted Table 2-4. 12 × 12 Terminals Sorted

Alphanumerically (continued) Alphanumerically (continued)

TERMINAL NAME BALL NO. TERMINAL NAME BALL NO.

RSVD F13 TPBIAS0 K13 RSVD F12 TPBIAS1 G13 RSVD E12 TPBIAS2 E13 RSVD D12 TXN A08 RSVD D13 TXP A09 RSVD M08 VDD_15 G03 RSVD N10 VDD_15 H03 RSVD P10 VDD_15 K10 RSVD P11 VDD_15 M06 RSVD N11 VDD_15 B08 RSVD M11 VDD_15_COMB C12 RSVD N12 VDD_33 E03 RSVD N13 VDD_33 G10 RSVD M12 VDD_33 H10 RSVD M13 VDD_33 J10 RSVD L13 VDD_33 M05 RSVD K12 VDD_33_AUX B12 RSVD L12 VDD_33_COM_IO C11 RXN A03 VDD_33_COMB B11 RXP A04 VDDA_15 B10 SCL J13 VDDA_15 B09 SDA H12 VDDA_15 B07 SE P13 VDDA_15 B05 SM P14 VDDA_33 C03 TESTM B02 VDDA_33 A10 VREG_PD A06 VDD_15 P07 TPA0– L14 VSS A14 TPA0+ K14 VSS A07 TPA1– G14 VSSA F05 TPA1+ F14 VSSA C10 TPA2– C14 VSSA B06 TPA2+ B14 VSSA_PCIE C04 TPB0– N14 VSSA_PCIE C05 TPB0+ M14 VSSA_PCIE C06 TPB1– J14 VSSA_PCIE C07 TPB1+ H14 XI P04 TPB2– E14 RSVD P03 TPB2+ D14

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2.5 Terminal Descriptions

The following tables give a description of the terminals. These terminals are grouped in tables by functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.

The following list describes the different input/output cell types that appear in the terminal description tables:

• HS DIFF IN = High-speed differential input

• HS DIFF OUT = High-speed differential output

• LV CMOS = 3.3-V low-voltage CMOS input or output with 3.3-V clamp rail

• BIAS = Input/output terminals that generate a bias voltage to determine a driver's operating current

• Feedthrough = Terminals that connect directly to macros within the part and not through an input or output cell

• PWR = Power terminal

• GND = Ground terminal

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Table 2-5. Power-Supply Terminals

BALL NO.

SIGNAL DESCRIPTION

ZAY ZAJ

PACKAGE PACKAGE

DD_15

G03 H03 C07 H03 PWR Bypass 1.5-V digital core power for the link K10 M06 H09 J03 capacitors B08 P07 J09 L06

DDA_15

DD_33

B10 B09 B04 B05 PWR Filter 1.5-V analog power for the link B07 B05 C04 C05

E03 M05 D10 K03 PWR Bypass 3.3-V digital I/O power for the link

J10 H10 K08 L03 capacitors

G10 L08

DD_33_AUX

DDA_33

B12 C09 This terminal is connected to VSS through a pulldown resistor,

C03 A10 A01 C08 PWR Filter 3.3-V analog power for the link. This supply terminal is

DVDD_CORE C09 F03 D08 D09 PWR Bypass Digital 1.95-V circuit power for the PHY. A combination of high-

M09 K09 capacitors frequency decoupling capacitors near each terminal is

PLLVDD_CORE M07 N06 PWR Bypass PLL 1.95-V circuit power for the PHY. A combination of high-

DVDD_33 C08 J03 E04 K05 PWR Bypass 3.3-V digital I/O power for the PHY

K03 K06 capacitors

AVDD_33 M04 E10 E10 F10 PWR Filter 3.3-V analog power for the PHY

F10 J09 H10 J10

K09 M10 M04

PLLVDD_33 N07 N07 PWR Bypass PLL 3.3-V circuit power for the PHY. This supply terminal is

DD_15_COMB

DD_33_COMB

DD_33_COMBIO

C12 B11 PWR Bypass Internal 1.5-V main power output for external bypass capacitor

B11 B09 PWR Bypass Internal 3.3-V main power output for external bypass capacitor

C11 B10 PWR Bypass Internal 3.3-V IO power output for external bypass capacitor

I/O EXTERNAL

TYPE PARTS

capacitors frequency decoupling capacitors near each terminal is

capacitors separated from the other power terminals internal to the device

capacitors filtering

since the XIO2213B does not support auxiliary power.

separated from the other power terminals internal to the device to provide noise isolation.

suggested, such as paralleled 0.1 μF and 0.001 μF. An additional 1-μF capacitor is required for voltage regulation. These supply terminals are separated from the other power terminals internal to the device to provide noise isolation.

suggested, such as paralleled 0.1 μF and 0.001 μF. An additional 1-μF capacitor is required for voltage regulation, and the PLLVDD_CORE terminals must be separate from the DVDD_CORE terminals. These supply terminals are separated from the other power terminals internal to the device to provide noise isolation.

to provide noise isolation. The PLLVDD_33 and V should be connected together with a low-dc-impedance

DDA_33

pins

connection on the circuit board.

Caution: Do not use this terminal to supply external power to other devices.

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Table 2-6. Ground Terminals

BALL NO.

SIGNAL DESCRIPTION

SSA

SSA_PCIE

PLLGND N05 N04 GND PLL circuit ground. This terminal must be tied to the low-

GND E06 E07 F06 F07 F08 E05 F04 F05 F06 F07 GND Ground. These terminals must be tied together to the low-

F09 G05 G06 G07 G08 F08 F09 G04 G05 G06 impedance circuit-board ground plane. G09 H05 H06 H07 H08 G07 G08 G09 G10 H04

ZAY ZAJ

PACKAGE PACKAGE

A07 A14 E07 E08 GND Digital ground for link

B06 C10 F05 D04 D07 E09 GND Analog ground for link

C04 C05 C06 C07 C06 D05 D06 E06 GND Analog ground for PCIe function

H09 J05 J06 J07 J08 H05 H06 H07 H08 J04

K05 K06 K07 K08 J05 J06 J07 J08 K07

L07

I/O

TYPE

impedance circuit-board ground plane.

Table 2-7. PCIe Terminals

BALL NO.

SIGNAL DESCRIPTION

PERST B13 B12 I PCI Express reset. PERST identifies when the system power is stable

REF0_PCIE A13 A11 I/O External External reference resistor + and terminals for setting TX driver current. REF1_PCIE A12 A10 resistor An external resistor is connected between terminals REF0_PCIE and

RXP A04 A05 DI High-speed receive pair. RXP and RXN comprise the differential RXN A03 A04 receive pair for the single PCIe lane supported.

TXP A09 A08 DO Series High-speed transmit pair. TXP and TXN comprise the differential TXN A08 A07 capacitors transmit pair for the single PCIe lane supported.

ZAY ZAJ

PACKAGE PACKAGE

I/O EXTERNAL

TYPE PARTS

and generates an internal power-on reset. Note: The PERST input buffer has hysteresis.

REF1_PCIE.

Table 2-8. Clock Terminals

BALL NO.

SIGNAL DESCRIPTION

REFCLK_SEL H13 G11 I Pullup or Reference clock select. This terminal selects the reference clock input.

REFCLK+ A01 B01 DI Reference clock positive. REFCLK+ and REFCLK– comprise the

REFCLK– B01 C01 DI Capacitor to Reference clock negative. REFCLK+ and REFCLK– comprise the

CLKREQ J12 H12 O Clock request. This terminal is used to support the clock request

XI P04 N05 I Oscillator input. This terminal connects to a 98.304-MHz low-jitter

ZAY ZAJ

PACKAGE PACKAGE

I/O EXTERNAL

TYPE PARTS

pulldown

resistor

VSSfor differential input pair for the 100-MHz system reference clock. For a

single- single-ended, 125-MHz system reference clock, attach a capacitor from ended REFCLK– to VSS.

mode

0 = 100-MHz differential common reference clock used 1 = 125-MHz single-ended reference clock used

differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, use the REFCLK+ input.

protocol.

external oscillator. XI is a 1.8-V CMOS input. Oscillator jitter must be 5ps RMS or better. If only 3.3-V oscillators can be acquired, great care must be taken to not introduce significant jitter by the means used to level shift from 3.3 V to 1.8 V. If a resistor divider is used, a high-current oscillator and low-value resistors must be used to minimize RC time constants.

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Table 2-9. 1394 Terminals

BALL NO.

SIGNAL DESCRIPTION

CNA A02 A02 I/O Cable not active. This terminal is asserted high when there are no ports receiving

CPS P12 N09 I Cable power status. This terminal is normally connected to cable power through a

DS0 N09 N08 I Data-strobe-only mode for port 0. IEEE Std 1394a-2000-only port-0-enable

DS1 P09 M07 I Data-strobe-only mode for port 1. IEEE Std 1394a-2000-only port-1-enable

PC0 E09 C11 I Power-class programming. On hardware reset, these inputs set the default value of PC1 E08 A09 the power class indicated during self-ID. Programming is done by tying the terminals PC2 A11 B08 high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ

R0 N01 N03 I/O Current-setting resistor. These terminals are connected to an external resistance to R1 M01 N02 set the internal operating currents and cable driver output currents. A resistance of

TPA0P K14 J13 I/O Port 0 twisted-pair cable A differential. Board trace lengths from each pair of positive TPA0N L14 K13 and negative differential signal pins must be matched and as short as possible to the TPB0P M14 L13 external load resistors and to the cable connector. For an unused port, TPA+ and TPB0N N14 M13 TPA– can be left open.

TPA1P F14 E13 I/O Port 1 twisted-pair cable A differential. Board trace lengths from each pair of positive TPA1N G14 F13 and negative differential signal pins must be matched and as short as possible to the TPB1P H14 G13 external load resistors and to the cable connector. For an unused port, TPA+ and TPB1N J14 H13 TPA– can be left open.

TPA2P B14 A13 I/O Port 2 twisted-pair cable A differential. Board trace lengths from each pair of positive TPA2N C14 B13 and negative differential signal pins must be matched and as short as possible to the TPB2P D14 C13 external load resistors and to the cable connector. For an unused port, TPA+ and TPB2N E14 D13 TPA– can be left open.

TPBIAS0 K13 J12 O Twisted-pair bias. These terminals provide the 1.86-V nominal bias voltage needed TPBIAS1 G13 E12 for proper operation of the twisted-pair cable drivers and receivers, and for signaling TPBIAS2 E13 A12 to the remote nodes that there is an active cable connection in IEEE Std 1394a-2000

PCLK_L G01 F03 I PHY-section clock. This terminal must be connected to the PCLK_P output of the

PCLK_P F01 F02 O PHY-section clock. This terminal must be connected to the PCLK_L input of the LLC

LCLK_L G02 G03 O LLC-section clock. This terminal must be connected to the LCLK_P input terminal of

LCLK_P H02 G02 I LLC-section clock. This terminal must be connected to the LCLK_L output terminal of

LPS_L C01 C03 O LLC-section power status. This terminal must be connected to the LPS_P input

LPS_P C02 D03 I Link power status. This terminal must be connected to the LPS_L ouput terminal of

PINT_L D02 E02 I PHY-section interrupt. The PHY section uses this signal to transfer status and

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I/O

TYPE

incoming bias voltage. If it is not used, this terminal should be left unconnected.

400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power. If CPS is not used to detect cable power, this terminal must be connected to V

programming terminal. On hardware reset, this terminal allows the user to select whether port 0 acts like an IEEE Std 1394b-2002 bilingual port (terminal at logic 0) or as an IEEE Std 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-kΩ or smaller resistor (to enable IEEE Std 1394b-2002 bilingual mode) or high through a 10-kΩ or smaller resistor (to enable IEEE Std 1394a-2000-only mode).

programming terminal. On hardware reset, this terminal allows the user to select whether port 1 acts like an IEEE Std 1394b-2002 bilingual port (terminal at logic 0) or as an IEEE Std 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-kΩ or smaller resistor (to enable IEEE Std 1394b-2002 bilingual mode) or high through a 10-kΩ or smaller resistor (to enable IEEE Std 1394a-2000-only mode).

or smaller resistor. Bus holders are built into these terminals.

6.34 kΩ ± 1% is required to meet the IEEE Std 1394-1995 output voltage limits.

mode. Each of these terminals, except for an unused port, must be decoupled with a 1-μF capacitor to ground. For the unused port, this terminal can be left unconnected.

PHY section.

section.

the PHY section.

the LLC section.

terminal of the PHY section.

the LLC section.

interrupt information serially to the LLC section. This terminal must be connected to the PINT_P output of the PHY section.

SSA

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Table 2-9. 1394 Terminals (continued)

BALL NO.

SIGNAL DESCRIPTION

PINT_P D03 E03 O PHY-section interrupt. PINT_P is a serial input to the LLC section from the PHY

LKON/DS2_P D01 D02 I/O Link-on notification. If port is to operate in DS mode or is unused then it is necessary

LINKON_L E01 C02 I/O Link-on notification. LINKON_L is an input to the LLC section from the PHY section

LREQ_L F02 D01 O LLC-section request. The LLC section uses this output to initiate a service request to

LREQ_P E02 E01 I LLC-section request. LREQ_P is a serial input from the LLC section to the PHY

PHY_RESET B04 A06 I Reset for the 1394 PHY logic CTL1 J01 G01 I/O Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the

CTL0 H01 F01 phase of operation of the PHY link interface. Upon a reset of the interface, this bus is

D0 J02 H01 I/O Data. D[7:0] comprise a bidirectional data bus that is used to carry 1394 packet data, D1 K02 H02 packet speed, and grant type information between the PHY and the link. Upon a D2 K01 J02 reset of the interface, this bus is driven by the PHY. When driven by the PHY, D3 L01 J01 information on D[7:0] is synchronous to PCLK. When driven by the link, information D4 L02 K02 on D[7:0] is synchronous to LCLK. If not implemented, these terminals should be left D5 L03 K01 unconnected. D6 M02 L01 D7 M03 M01

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section that is used to transfer status, register, interrupt, and other information to the link. Information encoded on PINT_P is synchronous to PCLK_P. This terminal must be connected to the PINT_L input of the LLC section.

to pull the terminal high through a 470-Ω or smaller resistor. This terminal must also be connected to the LINKON_L input terminal of the LLC section via a 1-kΩ series resistor. A bus holder is built into this terminal. If the port is to operate in bilingual mode then the terminal should be tied low via a 1-kΩ resistor and directly connected to the link's LINKON_L pin with no series termination. After hardware reset, this terminal is the link-on output, which notifies the LLC section or other power-up logic to power up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (eight PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance. The link-on output is activated if the LLC section is inactive (the LPS input inactive or the LCtrl bit cleared) and when any of the following occurs: a) The XIO2213B receives a link-on PHY packet addressed to this node. b) The PEI (port-event interrupt) register bit is 1. c) Any of the configuration-timeout interrupt (CTOI), cable-power-status interrupt (CPSI), or state-time-out interrupt (STOI) register bits are 1, and the resuming-port interrupt enable (RPIE) register bit also is 1. d) The PHY is power cycled and the power class is 0 through 4.

Once activated, the link-on output is active until the LLC section becomes active (both the LPS_L input active and the LCtrl bit set). The PHY section also deasserts the link-on output when a bus reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). In the case of power cycling, the LKON signal must stop after 167 ms if the previous conditions have not been met. Note: If an interrupt condition exists that otherwise causes the link-on output to be activated if the LLC section were inactive, the link-on output is activated when the LLC section subsequently becomes inactive.

that is used to provide notification that a link-on packet has been received or an event, such as a port connection, has occurred. This I/O only has meaning when LPS is disabled. This includes the D0 (uninitialized), D2, and D3 power states. If LINKON_L becomes active in the D0 (uninitialized), D2, or D3 power state, the XIO2213B device sets bit 15 (PME_STS) in the power-management control and status register in the PCI configuration space at offset 48h. This terminal must be connected to the LKON output terminal of the PHY section.

the PHY section.This terminal must be connected to the LREQ_P input of the PHY section.

section used to request packet transmissions, read and write PHY section registers, and to indicate the occurrence of certain link events that are relevant to the PHY section. Information encoded on LREQ_P is synchronous to LCLK_P.This terminal must be connected to the LREQ_L output of the LLC section.

driven by the PHY. When driven by the PHY, information on CTL[1:0] is synchronous to PCLK. When driven by the link, information on CTL[1:0] is synchronous to LCLK. If not implemented, these terminals should be left unconnected.

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Table 2-10. Reserved Terminals

BALL NO.

SIGNAL I/O TYPE DESCRIPTION

RSVD E12 F12 F13 K12 L12 L13 D11 E11 F12 J11 K10 K11 I/O Reserved, do not connect to external signals.

M11 M12 M13 N10 N11 N12 K12 L10 L11 L12 M05 M11

RSVD D12 D13 G12 M08 C10 D12 F11 M09 I Must be connected to VSS.

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N13 P03 P10 P11 M12 N11 N12 N13

Table 2-11. Miscellaneous Terminals

BALL NO.

SIGNAL DESCRIPTION

GPIO0 P01 M02 I/O General-purpose I/O 0. This terminal functions as a GPIO controlled by bit 0

GPIO1 N02 N01 I/O General-purpose I/O 1. This terminal functions as a GPIO controlled by bit 1

GPIO2 P02 L02 I/O General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2

GPIO3 N03 L04 I/O General-purpose I/O 3. This terminal functions as a GPIO controlled by bit 3

GPIO4 N04 M03 I/O General-purpose I/O 4. This terminal functions as a GPIO controlled by bit 4

GPIO5 P05 K04 I/O General-purpose I/O 5. This terminal functions as a GPIO controlled by bit 5

GPIO6 P06 M06 I/O General-purpose I/O 6. This terminal functions as a GPIO controlled by bit 6

GPIO7 N06 L05 I/O General-purpose I/O 7. This terminal functions as a GPIO controlled by bit 7

OHCI_PME P08 M08 O OHCI power-management event. This is an optional signal that can be used by a

CYCLEOUT N08 L09 O Cycle out. This terminal provides an 8-kHz cycle timer synchronization signal. If not

PD B03 B03 I Power down. A high on this terminal turns off all internal circuitry, except the cable-

GRST C13 C12 I Global power reset. This reset brings all of the XIO2213B internal link registers to

SCL J13 G12 I/O Serial-bus clock. This signal is used as a serial bus clock when a pullup is detected

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(GPIO0_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO1_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO2_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO3_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO4_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO5_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO6_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO7_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

device to request a change in the device or system power state. This signal must be enabled by software.

implemented, this terminal should be left unconnected.

active monitor circuits that control the CNA output. Asserting PD high also activates an internal pulldown to force a reset of the internal control logic. If PD is not used, this terminal must be connected to VSS.

their default states. This should be a one-time power-on reset. This terminal has hysteresis and an integrated pullup resistor.

on SDA or when the SBDETECT bit is set in the serial bus control and status register.

Note: This terminal has an internal active pullup resistor.

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Table 2-11. Miscellaneous Terminals (continued)

BALL NO.

SIGNAL DESCRIPTION

SDA H12 H11 I/O Serial-bus data. This signal is used as serial bus data when a pullup is detected on

BMODE A05 B06 I Beta mode. This terminal determines the PHY-section/LLC-section interface

TESTM B02 A03 I Test control. This input is used in the manufacturing test of the XIO2213B. For

VREG_PD A06 B07 I Voltage regulator power-down input. When asserted logic high, this pin will power-

SE P13 M10 I Test control. This input is used in the manufacturing test of the XIO2213B. For

SM P14 N10 I Test control. This input is used in the manufacturing test of the XIO2213B. For

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SDA or when the SBDETECT bit is set in the serial bus control and status register. Note: In serial-bus mode, an external pullup resistor is required to prevent the SDA

signal from floating.

connection protocol. When logic high (asserted), the PHY-section/LLC-section interface complies with the IEEE Std 1394b-2002 Revision 1.33 beta interface. When logic low (deasserted), the PHY-section/LLC-section interface complies with legacy IEEE Std 1394a-2000. This terminal must be pulled high with a 1-kΩ resistor during normal operation.

normal use, this terminal must be pulled high through a 1-kΩ resistor to VDD.

down the internal 3.3- to 1.95V regulator. For single 3.3V supply operation, this pin should be tied to GND. When using the internal regulator, the XIO2213B can support a maximum of 2-Beta and 1-DS connection simultaneously. If 3-Beta ports are required to be simultaneously supported, it is recommended to use an external

1.95V regulator.

normal use, this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND.

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Transmitter

PCIExpress

Receiver

PCIBusInterface

Configurationand

MemoryRegister

GPIO

Serial

EEPROM

Reset

Controller

Clock

Generator

Power

Mgmt

1394bOHCIwith3-PortPHY

1394CablePort 1394CablePort 1394CablePort

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3 Feature/Protocol Descriptions

This chapter provides a high-level overview of all significant device features. Figure 3-1 shows a simplified block diagram of the basic architecture of the PCIe to PCI bridge with 1394b OHCI and 3-port PHY. The top of the diagram is the PCIe interface, and the 1394b OHCI with 3-port PHY is located at the bottom of the diagram.

SCPS210F –OCTOBER 2008–REVISED MAY 2013

Figure 3-1. XIO2213B Block Diagram

3.1 Power-Up/Power-Down Sequencing

The bridge contains both 1.5-V and 3.3-V power terminals. The following power-up and power-down sequences describe how power is applied to these terminals.

In addition, the bridge has three resets: PERST, GRST, and an internal power-on reset. These resets are described in Section 3.2. The following power-up and power-down sequences describe how PERST is applied to the bridge.

The application of the PCIe reference clock (REFCLK) is important to the power-up/-down sequence and is included in the following power-up and power-down descriptions.

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100ms

100 ms

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3.1.1 Power-Up Sequence

1. Assert PERST to the device.

2. Apply 1.5-V and 3.3-V voltages.

3. Apply a stable PCIe reference clock.

4. To meet PCIe specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied:

– Wait a minimum of 100 s after applying a stable PCIe reference clock. The 100-s limit satisfies the

requirement for stable device clocks by the deassertion of PERST.

– Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for

stable power by the deassertion of PERST.

See the power-up sequencing diagram in Figure 3-2.

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Figure 3-2. Power-Up Sequence

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3.1.2 Power-Down Sequence

1. Assert PERST to the device.

2. Remove the reference clock.

3. Remove 3.3-V and 1.5-V voltages.

See the power-down sequencing diagram in Figure 3-3. If the VDD_33_AUX terminal is to remain powered after a system shutdown, the bridge power-down sequence is the same as shown in Figure 3-3.

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Figure 3-3. Power-Down Sequence

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3.2 XIO2213B Reset Features

There are five XIO2213B reset options that include internally-generated power-on reset, resets generated by asserting input terminals, and software-initiated resets that are controlled by sending a PCIe hot reset or setting a configuration register bit. Table 3-1 identifies these reset sources and describes how the XIO2213B responds to each reset.

Table 3-1. XIO2213B Reset Options

RESET

OPTION

XIO2213B During a power-on cycle, the XIO2213B asserts an internal When the internal power-on reset is asserted, all control

internally- reset and monitors the V

generated this terminal reaches 90% of the nominal input voltage management state machines are initialized to their default

power-on reset specification, power is considered stable. After stable power, state.

the XIO2213B monitors the PCIe reference clock (REFCLK) In addition, the XIO2213B asserts the internal PCI bus and waits 10 s after active clocks are detected. Then, reset. internal power-on reset is deasserted.

PCIe reset input This XIO2213B input terminal is used by an upstream PCIe When PERST is asserted low, all control register bits that

(PERST, B12) device to generate a PCIe reset and to signal a system are not sticky are reset. Within the configuration register

power good condition. maps, the sticky bits are indicated by the symbol. Also, all When PERST is asserted low, the XIO2213B generates an

internal PCIe reset as defined in the PCI Express Specification.

When PERST transitions from low to high, a system power In addition, the XIO2213B asserts the internal PCI bus good condition is assumed by the XIO2213B. reset.

Note: The system must assert PERST before power is When the rising edge of PERST occurs, the XIO2213B removed, before REFCLK is removed or before REFCLK samples the state of all static control inputs and latches becomes unstable. the information internally. If an external serial EEPROM is

PCIe training The XIO2213B responds to a training control hot reset In the DL_DOWN state, all remaining configuration register

control hot reset received on the PCIe interface. After a training control hot bits and state machines are reset. All remaining bits

reset, the PCIe interface enters the DL_DOWN state. exclude sticky bits and EEPROM loadable bits. All

PCI bus reset System software has the ability to assert and deassert the When bit 6 (SRST) in the XIO2213B control register at

PCI bus reset on the secondary PCI bus interface. offset 3Eh (see Section 4.30) is asserted, the XIO2213B

XIO2213B FEATURE RESET RESPONSE

DD_15_COMB

(B11) terminal. When registers, state machines, sticky register bits, and power

state machines that are not associated with sticky functionality are reset.

detected, a download cycle is initiated. Also, the process to configure and initialize the PCIe link is started. The XIO2213B starts link training within 80 ms after PERST is deasserted.

remaining state machines exclude sticky functionality and EEPROM functionality.

Within the configuration register maps, the sticky bits are reset by a global reset (GRST) or the internally-generated power-on reset and EEPROM loadable bits are rest by a PCIe reset (PERST), GRST, or internally generated poweron reset.

In addition, the XIO2213B asserts the internal PCI bus reset.

asserts the internal PCI bus reset. A 0b in the SRST bit deasserts the PCI bus reset.

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3.3 PCI Express (PCIe) Interface

3.3.1 External Reference Clock

The XIO2213B requires either a differential, 100-MHz common clock reference or a single-ended, 125MHz clock reference. The selected clock reference must meet all PCI Express Electrical Specification requirements for frequency tolerance, spread-spectrum clocking, and signal electrical characteristics.

If the REFCLK_SEL input is connected to VSS, a differential, 100-MHz common clock reference is expected by the XIO2213B. If the REFCLK_SEL terminal is connected to V clock reference is expected by the XIO2213B.

When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is connected to the REFCLK+ terminal. The REFCLK terminal is connected to one side of an external capacitor with the other side of the capacitor connected to VSS.

When using a single-ended reference clock, care must be taken to ensure interoperability from a system jitter standpoint. The PCI Express Base Specification does not ensure interoperability when using a differential reference clock commonly used in PC applications along with a single-ended clock in a noncommon clock architecture. System jitter budgets will have to be verified to ensure interoperability (see the PCI Express Jitter and BER white paper from PCI-SIG).

3.3.2 Beacon and Wake

Since the 1394b OHCI function in the XIO2213B does not support PME from D3cold, it is not necessary for the PCIe to PCI bridge portion of the design to support beacon generation or WAKE signaling. As a result, the XIO2213B does not implement VAUX power support.

SCPS210F –OCTOBER 2008–REVISED MAY 2013

, a single-ended 125-MHz

DD_33

3.3.3 Initial Flow Control Credits

The bridge flow control credits are initialized using the rules defined in the PCI Express Base Specification. Table 3-2 identifies the initial flow control credit advertisement for the bridge.

Table 3-2. Initial Flow Control Credit Advertisements

CREDIT TYPE INITIAL ADVERTISEMENT

Posted request headers (PH) 8

Posted request data (PD) 128 Nonposted header (NPH) 4

Nonposted data (NPD) 4

Completion header (CPLH) 0 (infinite)

Completion data (CPLD) 0 (infinite)

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3.3.4 PCIe Message Transactions

PCIe messages are both initiated and received by the bridge. Table 3-3 outlines message support within the bridge.

Table 3-3. Messages Supported by Bridge

MESSAGE SUPPORTED BRIDGE ACTION

Assert_INTx Yes Transmitted upstream Deassert_INTx Yes Transmitted upstream PM_Active_State_Nak Yes Received and processed PM_PME Yes Transmitted upstream PME_Turn_Off Yes Received and processed PME_TO_Ack Yes Transmitted upstream ERR_COR Yes Transmitted upstream ERR_NONFATAL Yes Transmitted upstream ERR_FATAL Yes Transmitted upstream Set_Slot_Power_Limit Yes Received and processed Unlock No Discarded Hot plug messages No Discarded Advanced switching messages No Discarded Vendor defined type 0 No Unsupported request Vendor defined type 1 No Discarded

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All supported message transactions are processed per the PCI Express Base Specification.

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+1 +2

4567

2 1

Type

Fmt

Reserved

ReservedID

Reserved

Tag

Length

Code

Attr

Byte0>

Byte4>

Byte8>

Byte12>

+1 +2

4567

2 1

Type

Fmt

Reserved

ReservedID

Reserved

Tag

Length

Code

Attr

Byte0>

Byte4>

Byte8>

Byte12>

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3.4 PCI Interrupt Conversion to PCIe Messages

The bridge converts interrupts from the PCI bus sideband interrupt signals to PCIe interrupt messages. Since the 1394a OHCI only generates INTA interrupts, only PCIe INTA messages are generated by the bridge.

PCIe Assert_INTA messages are generated when the 1394a OHCI signals an INTA interrupt. The requester ID portion of the Assert_INTA message uses the value stored in the primary bus number register (see Section 4.12) as the bus number, 0 as the device number, and 0 as the function number. The tag field for each Assert_INTA message is 00h.

PCIe Deassert_INTA messages are generated when the 1394a OHCI deasserts the INTA interrupt. The requester ID portion of the Deassert_INTA message uses the value stored in the primary bus number register as the bus number, 0 as the device number, and 0 as the function number. The Tag field for each Deassert_INTA message is 00h.

Figure 3-4 and Figure 3-5 show the format for both the assert and deassert INTA messages.

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Figure 3-4. PCIe Assert_INTA Message

Figure 3-5. PCIe Deassert_INTX Message

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SDA

VDD_33

A1A2SCL

SDA

XIO2213B

Serial EEPROM

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3.5 Two-Wire Serial-Bus Interface

The bridge provides a two-wire serial-bus interface to load subsystem identification information and specific register defaults from an external EEPROM. The serial-bus interface signals are SCL and SDA.

3.5.1 Serial-Bus Interface Implementation

To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising edge of PERST or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup resistor. If one is detected, bit 3 (SBDETECT) in the serial-bus control and status register (see

Section 4.59) is set. Software may disable the serial-bus interface at any time by writing a 0b to the

SBDETECT bit. If no external EEPROM is required, the serial-bus interface is permanently disabled by attaching a pulldown resistor to the SDA signal.

The bridge implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA). The SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both are open-drain signals and require pullup resistors. The bridge is a bus master device and drives SCL at approximately 60 kHz during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. Figure 3-6 shows an example application implementing the two-wire serial bus.

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Figure 3-6. Serial EEPROM Application

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8 9

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SDA Output ByReceiver

SDA

SCL

Start

Condition

Stop

Condition

Changeof

Data Allowed

DataLineStable,

DataValid

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3.5.2 Serial-Bus Interface Protocol

All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state (see Figure 3-7). The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high transition of SDA while SCL is in the high state (see Figure 3-7). Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control signals, that is, a start or stop condition.

Figure 3-7. Serial-Bus Start/Stop Conditions and Bit Transfers

SCPS210F –OCTOBER 2008–REVISED MAY 2013

Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that are transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the data transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3-8 shows the acknowledge protocol.

Figure 3-8. Serial-Bus Protocol Acknowledge

The bridge performs three basic serial-bus operations: single-byte reads, single-byte writes, and multibyte reads. The single-byte operations occur under software control. The multibyte read operations are performed by the serial EEPROM initialization circuitry immediately after a PCIe reset (see Section 3.5.3, Serial-Bus EEPROM Application, for details on how the bridge automatically loads the subsystem identification and other register defaults from the serial-bus EEPROM.

Figure 3-9 shows a single-byte write. The bridge issues a start condition and sends the 7-bit slave device

address, and the R/W command bit is equal to 0b. A 0b in the R/W command bit indicates that the data transfer is a write. The slave device acknowledges if it recognizes the slave address. If no acknowledgment is received by the bridge, bit 1 (SB_ERR) is set in the serial-bus control and status register (PCI offset B3h, see Section 4.59). Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment is expected. Then the bridge delivers the data-byte most significant bit (MSB) first and expects a final acknowledgment before issuing the stop condition.

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1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0

A A

Slave Address

Word Address

R/W

DataByte1 DataByte2 DataByte3

M=Master Acknowledgement

S/P =Start/StopCondition

A =Slave Acknowledgement

DataByte0

1 1

0 0 0 0 0

Restart

R/W

Slave Address

Start

b0 0

Slave Address

Word Address

R/W

b2 b1

Slave Address

S/P =Start/StopCondition

M=Master Acknowledgement

M P

DataByte

Start

Restart

R/W

A =Slave Acknowledgement

Stop

b2 b1

b0 0

b2 b1

A A

Slave Address

Word Address

R/W

S/P =Start/StopCondition

A =Slave Acknowledgement

b2 b1

A P

DataByte

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Figure 3-9. Serial-Bus Protocol Byte Write

Figure 3-10 shows a single-byte read. The bridge issues a start condition and sends the 7-bit slave device

address, and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the slave address. Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment is expected. Then, the bridge issues a restart condition followed by the 7-bit slave address, and the R/W command bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the slave device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the bridge responds with no acknowledge (logic high) indicating the last data byte. Finally, the bridge issues a stop condition.

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Figure 3-10. Serial-Bus Protocol Byte Read

Figure 3-11 shows the serial interface protocol during a multibyte serial EEPROM download. The serial-

bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes are transferred. The number of transferred data bytes is controlled by the bridge master. After each data byte, the bridge master issues acknowledge (logic low) if more data bytes are requested. The transfer ends after a bridge master no acknowledge (logic high) followed by a stop condition.

Figure 3-11. Serial-Bus Protocol Multibyte Read

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Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the three previous serial-bus protocol figures show the PROT_SEL bit default (logic low). When this control bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol. This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM devices.

3.5.3 Serial-Bus EEPROM Application

The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3-4.

Table 3-4. EEPROM Register Loading Map

SERIAL EEPROM WORD ADDRESS

00h PCIe to PCI bridge function indicator (00h) 01h Number of bytes to download (1Eh)s 02h PCI 84h, subsystem vendor ID, byte 0 03h PCI 85h, subsystem vendor ID, byte 1 04h PCI 86h, subsystem ID, byte 0s 05h PCI 87h, subsystem ID, byte 1s 06h PCI D4h, general control, byte 0 07h PCI D5h, general control, byte 1 08h PCI D6h, general control, byte 2 09h PCI D7h, general control, byte 3 0Ah TI Proprietary register load 00h (PCI D8h) 0Bh TI Proprietary register load 00h (PCI D9h) 0Ch Reserved — no bits loaded 00h (PCI DAh) 0Dh PCI DCh, arbiter control 0Eh PCI DDh, arbiter request mask 0Fh PCI C0h, TL control and diagnostic register, byte 0 10h PCI C0h, TL control and diagnostic register, byte 1 11h PCI C0h, TL control and diagnostic register, byte 2 12h PCI C0h, TL control and diagnostic register, byte 3 13h PCI C4h, DLL control and diagnostic register, byte 0 14h PCI C5h, DLL control and diagnostic register, byte 1 15h PCI C6h, DLL control and diagnostic register, byte 2 16h PCI C7h, DLL control and diagnostic register, byte 3 17h PCI C8h, PHY control and diagnostic register, byte 0 18h PCI C9h, PHY control and diagnostic register, byte 1 19h PCI CAh, PHY control and diagnostic register, byte 2 1Ah PCI CBh, PHY control and diagnostic register, byte 3 1Bh Reserved — no bits loaded 00h (PCI CEh) 1Ch Reserved — no bits loaded 00h (PCI CFh) 1Dh TI proprietary register load 00h (PCI E0h) 1Eh TI proprietary register load 00h (PCI E2h) 1Fh TI proprietary register load 00h (PCI E3h) 20h 1394 OHCI function indicator (01h) 21h Number of bytes (18h) 22h PCI 3Fh, maximum latency, bits 7-4 PCI 3Eh, minimum grant, bits 3-0 23h PCI 2Ch, subsystem vendor ID, byte 0 24h PCI 2Dh, subsystem vendor ID, byte 1 25h PCI 2Eh, subsystem ID, byte 0

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BYTE DESCRIPTION

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Table 3-4. EEPROM Register Loading Map (continued)

SERIAL EEPROM WORD ADDRESS

26h PCI 2Fh, subsystem ID, byte 1

27h

28h Mini-ROM address, this byte indicates the MINI ROM offset into the EEPROM

29h OHCI 24h, GUIDHi, byte 0 2Ah OHCI 25h, GUIDHi, byte 1 2Bh OHCI 26h, GUIDHi, byte 2 2Ch OHCI 27h, GUIDHi, byte 3 2Dh OHCI 28h, GUIDLo, byte 0 2Eh OHCI 29h, GUIDLo, byte 1 2Fh OHCI 2Ah, GUIDLo, byte 2 30h OHCI 2Bh, GUIDLo, byte 3 31h Reserved — no bits loaded 32h PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4 33h PCI F0h, PCI miscellaneous, byte 0, bits 7, 4, 2, 1, 0 34h PCI F1h, PCI miscellaneous, byte 1, bits 1, 0 35h Reserved — no bits loaded 36h Reserved — no bits loaded 37h Reserved — no bits loaded 38h Reserved — no bits loaded 39h Reserved multifunction select register 3Ah End-of-list indicator (80h)

Link_Enh enab_unfair HC Control RSVD Link_Enh Link_Enh enab_accel RSVD

[7] [6] [5:3] [2] [1] [0]

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BYTE DESCRIPTION

Program Phy

Enable

00h = No MINI ROM

01h to FFh = MINI ROM offset

This format must be explicitly followed for the bridge to correctly load initialization values from a serial EEPROM. All byte locations must be considered when programming the EEPROM.

The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is internally hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the EEPROM are tied to VSSto achieve this address. The serial EEPROM in the sample application circuit (Figure 3-6) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to VSS.

During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may be monitored to verify a successful download.

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3.5.4 Accessing Serial-Bus Devices Through Softwaree

The bridge provides a programming mechanism to control serial-bus devices through system software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h.

Table 3-5 lists the registers that program a serial-bus device through software.

Table 3-5. Registers Used To Program Serial-Bus Devices

PCI OFFSET REGISTER NAME DESCRIPTION

B0h Serial-bus data Contains the data byte to send on write commands or the received data byte on read

B1h Serial-bus word address The content of this register is sent as the word address on byte writes or reads. This register is

B2h Serial-bus slave address Write transactions to this register initiate a serial-bus transaction. The slave device address and

B3h Serial-bus control and Serial interface enable, busy, and error status are communicated through this register. In

(see Section 4.56) commands.

(see Section 4.57) not used in the quick command protocol. Bit 7 (PROT_SEL) in the serial-bus control and status

(see Section 4.58) the R/W command selector are programmed through this register.

status (see Section 4.59) addition, the protocol-select bit (PROT_SEL) and serial-bus test bit (SBTEST) are programmed

through this register.

To access the serial EEPROM through the software interface, the following steps are performed:

1. The control and status byte is read to verify the EEPROM interface is enabled (SBDETECT asserted) and not busy (REQBUSY and ROMBUSY deasserted).

2. The serial-bus word address is loaded. If the access is a write, the data byte is also loaded.

3. The serial-bus slave address and R/W command selector byte is written.

4. REQBUSY is monitored until this bit is deasserted.

5. SB_ERR is checked to verify that the serial-bus operation completed without error. If the operation is a read, the serial-bus data byte is now valid.

3.6 Advanced Error Reporting Registers

In the extended PCIe configuration space, the bridge supports the advanced error reporting capabilities structure. For the PCIe interface, both correctable and uncorrectable error statuses are provided. For the PCI bus interface, secondary uncorrectable error status is provided. All uncorrectable status bits have corresponding mask and severity control bits. For correctable status bits, only mask bits are provided.

Both the primary and secondary interfaces include first error pointer and header log registers. When the first error is detected, the corresponding bit position within the uncorrectable status register is loaded into the first error pointer register. Likewise, the header information associated with the first failing transaction is loaded into the header log. To reset this first error control logic, the corresponding status bit in the uncorrectable status register is cleared by a writeback of 1b.

For systems that require high data reliability, ECRC is fully supported on the PCIe interface. The primaryside advanced error capabilities and control register has both ECRC generation and checking enable control bits. When the checking bit is asserted, all received TLPs are checked for a valid ECRC field. If the generation bit is asserted, all transmitted TLPs contain a valid ECRC field.

3.7 Data Error Forwarding Capability

The bridge supports the transfer of data errors in both directions. If a downstream PCIe transaction with a data payload is received that targets the internal PCI bus and the

EP bit is set indicating poisoned data, the bridge must ensure that this information is transferred to the PCI bus. To do this, the bridge forces a parity error on each PCI bus data phase by inverting the parity bit calculated for each double word of data.

If the bridge is the target of a PCI transaction that is forwarded to the PCIe interface and a data parity error is detected, this information is passed to the PCIe interface. To do this, the bridge sets the EP bit in the upstream PCIe header.

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3.8 General-Purpose I/O (GPIO) Interface

Up to eight GPIO terminals are provided for system customization. These GPIO terminals are 3.3-V tolerant.

The exact number of GPIO terminals varies based on implementing the clock-run, power-override, and serial EEPROM interface features. These features share four of the eight GPIO terminals. When any of the three shared functions are enabled, the associated GPIO terminal is disabled.

All eight GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding bit in the GPIO control register at offset B4h. A GPIO data register at offset B6h exists to either read the logic state of each GPIO input or to set the logic state of each GPIO output. The power-up default state for the GPIO control register is input mode.

3.9 Set Slot Power Limit Functionality

The PCI Express Specification provides a method for devices to limit internal functionality and save power based on the value programmed into the captured slot power limit scale (CSPLS) and capture slot power limit value (CSPLV) fields of the PCIe device capabilities register at offset 94h (see Section 4.50, Device Capabilities Register, for details). The bridge writes these fields when a set slot power limit message is received on the PCIe interface.

After the deassertion of PERST, the XIO2213B compares the information within the CSPLS and CSPLV fields of the device capabilities register to the minimum power scale (MIN_POWER_SCALE) and minimum power value (MIN_POWER_VALUE) fields in the general control register at offset D4h (see Section 4.66, General Control Register, for details). If the CSPLS and CSPLV fields are less than the MIN_POWER_SCALE and MIN_POWER_VALUE fields, respectively, the bridge takes the appropriate action that is defined below.

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The power usage action is programmable within the bridge. The general control register includes a 3-bit POWER_OVRD field. This field is programmable to the following two options:

• Ignore slot power limit fields.

• Respond with unsupported request to all transactions except type 0/1 configuration transactions, and set slot power limit messages.

3.10 PCIe and PCI Bus Power Management

The bridge supports both software-directed power management and active-state power management through standard PCI configuration space. Software-directed registers are located in the power management capabilities structure located at offset 50h. Active-state power management control registers are located in the PCIe capabilities structure located at offset 90h.

During software-directed power-management state changes, the bridge initiates link state transitions to L1 or L2/L3 after a configuration write transaction places the device in a low-power state. The powermanagement state machine is also responsible for gating internal clocks based on the power state.

Table 3-6 identifies the relationship between the D-states and bridge clock operation.

Table 3-6. Clocking In Low Power States

CLOCK SOURCE D0/L0 D1/L1 D2/L1 D3/L2/L3

PCIe reference clock input (REFCLK) On On On On/Off Internal PCI bus clock to bridge function On Off Off Off Internal PCI bus clock to 1394b OHCI function On On On On/Off

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The link power management (LPM) state machine manages active-state power by monitoring the PCIe transaction activity. If no transactions are pending and the transmitter has been idle for at least the minimum time required by the PCI Express Specification, the LPM state machine transitions the link to either the L0s or L1 state. By reading the bridges L0s and L1 exit latency in the link capabilities register, the system software may make an informed decision relating to system performance versus power savings. The ASLPMC field in the link control register provides an L0s-only option, L1-only option, or both L0s and L1 options.

Finally, the bridge generates the PM_Active_State_Nak Message if a PM_Active_State_Request_L1 DLLP is received on the PCIe interface and the link cannot be transitioned to L1.

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3.11 1394b OHCI Controller Functionality

3.11.1 1394b OHCI Power Management

The 1394b OHCI controller complies with the PCI Bus Power Management Interface Specification. The controller supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management definition in the 1394 Open Host Controller Interface Specification, Appendix A4.

Table 3-7 identifies the supported power-management registers within the 1394 OHCI configuration

Table 3-7. 1394b OHCI Configuration Register Map

Power management capabilities Next item pointer Capability ID 44h

PM data Power management control/status register bridge support extensions Power management control/status (CSR) 48h

3.11.2 1394b OHCI and V

The 1394b OHCI function within the XIO2213B is powered by V power-management state, V

This implies that the 1394b OHCI function does not implement sticky bits must be initialized after a D3 power-management state. An external serial EEPROM interface is available to initialize critical configuration register bits. The EEPROM download is triggered by the deassertion of the PERST input. Otherwise, the BIOS must initialize the 1394b OHCI function.

AUX

DD_MAIN

is not supplied to the 1394b OHCI function.

AUX

only. Therefore, during the D3

cold

3.11.3 1394b OHCI and Reset Options

The 1394b OHCI function is completely reset by the internal power-on reset feature, GRST input, or PERST input. This includes all EEPROM loadable bits, power-management functions, and all remaining configuration register bits and logic.

A PCIe training control hot reset or the PCI bus configuration register reset bit (SRST) excludes the EEPROM loadable bits, power-management functions, and 1394 PHY. All remaining configuration registers and logic are reset.

If the OHCI controller is in the power-management D2 or D3 state, or if the OHCI configuration register reset bit (SoftReset) is set, the OHCI controller DMA logic and link logic is reset.

Finally, if the OHCI configuration register PHY reset bit (ISBR) is set, the 1394 PHY logic is reset.

3.11.4 1394b OHCI PCI Bus Master

As a bus master, the 1394 OHCI function supports the memory commands specified in Table 3-8. The commands include memory read, memory read line, memory read multiple, memory write, and memory write and invalidate.

The read command usage for read transactions of greater than two data phases are determined by the selection in bits 9:8 (MR_ENHANCE field) of the PCI miscellaneous configuration register at offset F0h (see Section 7.21). For read transactions of one or two data phases, a memory read command is used.

The write command usage is determined by the MWI_ENB bit 4 of the command configuration register at offset 04h (see Section 4.3). If bit 4 is asserted and a memory write starts on a cache boundary with a length greater than one cache line, memory write and invalidate commands are used. Otherwise, memory write commands are used.

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Table 3-8. 1394 OHCI Memory Command Options

PCI OHCI MASTER FUNCTION

Memory read 0110 DMA read from memory Memory write 0111 DMA write to memory

Memory read multiple 1100 DMA read from memory

Memory read line 1110 DMA read from memory

Memory write and invalidate 1111 DMA write to memory

3.11.5 1394b OHCI Subsystem Identification

The subsystem identification register at offset 2Ch is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the 1394a OHCI PCI configuration space (see Section 7.23).

Write access to the subsystem access register updates the subsystem identification registers identically to OHCI-Lynx™ integrated circuits. The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. The subsystem ID value written to this register may also be read back from this register.

3.11.6 1394b OHCI PME Support

Since the 1394b OHCI controller is not connected to VAUX, PME generation is disabled for D3cold powermanagement states.

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COMMAND

C/BE3C/BE0

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4 Classic PCI Configuration Space

The programming model of the XIO2213B PCIe to PCI bridge is compliant to the classic PCI-to-PCI bridge programming model. The PCI configuration map uses the type 1 PCI bridge header.

Sticky bits are reset by a global reset (GRST) or the internally-generated power-on reset. EEPROM loadable bits are reset by a PCIe reset (PERST), GRST, or the internally-generated power-on reset. The remaining register bits are reset by a PCIe hot reset, PERST, GRST, or the internally-generated power-on reset.

Table 4-1. Classic PCI Configuration Register Map

Device ID Vendor ID 000h

Status Command 004h

Class code Revision ID 008h

BIST Header type Primary latency timer Cache line size 00Ch

Device contol base address 010h

Scratchpad RAM base address 014h

Secondary latency timer Subordinate bus number Secondary bus number Primary bus number 018h

Secondary status I/O limit I/O base 01Ch

Memory limit Memory base 020h

Prefetchable memory limit Prefetchable memory base 024h

Prefetchable base upper 32 bits 028h

Prefetchable limit upper 32 bits 02Ch

I/O limit upper 16 bits I/O base upper 16 bits 030h

Reserved Capabilities pointer 034h

Reserved 038h

Bridge control Interrupt pin Interrupt line 03Ch

Reserved 040h-04Ch

Power management capabilities Next item pointer PM apability ID 050h

Power management data Power management control/status 054h

MSI message control Next item pointer MSI capability ID 060h

Subsystem ID

PCI Express capabilities register Next item pointer PCI Express capability ID 090h

Serial-bus control and

status

(1)

Power management bridge

support extention

Reserved 058h-05Ch

MSI message lower address 064h

MSI message upper address 068h

Reserved MSI message data 06Ch

Reserved 070h-07Ch

Reserved Next item pointer SSID/SSVID capability ID 080h

(1)

Reserved 088h-08Ch

Device capabilities 094h

Device status Device control 098h

Link capabilities 09Ch

Link status Link control 0A0h

Reserved 0A4h-0ACh

Serial-bus slave address

GPIO data

(1)

Serial-bus word address

Subsystem vendor ID

(1)

GPIO control

(1)

Serial-bus data

(1)

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084h

0B0h 0B4h

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Table 4-1. Classic PCI Configuration Register Map (continued)

Reserved TI proprietary Reserved Arbiter time-out status Arbiter request mask

TI proprietary

Reserved TI proprietary 0E4h

4.1 Vendor ID Register

This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to TI.,

PCI register offset: 00h Register type: Read-only Default value: 104Ch

Reserved 0B8h-0BCh Control and diagnostic register 0 Control and diagnostic register 1 Control and diagnostic register 2

Reserved 0CCh

Subsystem access

General control

(1)

Reserved 0E8h-0FCh

SCPS210F –OCTOBER 2008–REVISED MAY 2013

(1) (1) (1)

(1)

TI proprietary

Reserved TI proprietary

(1)

TI proprietary

Arbiter control

0C0h 0C4h 0C8h

0D0h 0D4h

(1)

0D8h 0DCh 0E0h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

4.2 Device ID Register

This 16-bit read-only register contains the value 823Eh, which is the device ID assigned by TI for the bridge.,

PCI register offset: 02h Register type: Read only Default value: 823Eh

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1

4.3 Command Register

The command register controls how the bridge behaves on the PCIe interface. See Table 4-2 for a complete description of the register contents.

PCI register offset: 04h Register type: Read only, Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 4-2. Command Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:11 RSVD R Reserved. Returns 00000b when read.

10 INT_DISABLE R INTx disable. This bit enables device specific interrupts. Since the bridge does not

generate any internal interrupts, this bit is read-only 0b.

9 FBB_ENB R Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;

therefore, this bit returns 0b when read.

8 SERR_ENB RW SERR enable. When this bit is set, the bridge can signal fatal and nonfatal errors on the

PCIe interface on behalf of SERR assertions detected on the PCI bus.

0 = Disable the reporting of nonfatal errors and fatal errors (default) 1 = Enable the reporting of nonfatal errors and fatal errors

7 STEP_ENB R Address/data stepping control. The bridge does not support address/data stepping, and

this bit is hardwired to 0b.

6 PERR_ENB RW Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Section 4.4)

in response to a received poisoned TLP from PCIe. A received poisoned TLP is forwarded with bad parity to conventional PCI, regardless of the setting of this bit.

0 = Disables the setting of the master data parity error bit (default) 1 = Enables the setting of the master data parity error bit

5 VGA_ENB R VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore,

this bit returns 0b when read.

4 MWI_ENB RW Memory write and invalidate enable. When this bit is set, the bridge translates PCIe

memory write requests into memory write and invalidate transactions on the PCI interface.

0 = Disable the promotion to memory write and invalidate (default) 1 = Enable the promotion to memory write and invalidate

3 SPECIAL R Special cycle enable. The bridge does not respond to special cycle transactions; therefore,

this bit returns 0b when read.

2 MASTER_ENB RW Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on

the PCIe interface.

0 = PCIe interface cannot initiate transactions. The bridge must disable the response

to memory and I/O transactions on the PCI interface (default).

1 = PCIe interface can initiate transactions. The bridge can forward memory and I/O

transactions from PCI secondary interface to the PCIe interface.

1 MEMORY_ENB RW Memory space enable. Setting this bit enables the bridge to respond to memory

transactions on the PCIe interface.

0 = PCIe receiver cannot process downstream memory transactions and must

respond with an unsupported request (default)

1 = PCIe receiver can process downstream memory transactions. The bridge can

forward memory transactions to the PCI interface.

0 IO_ENB RW I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the

PCIe interface.

0 = PCIe receiver cannot process downstream I/O transactions and must respond

with an unsupported request (default)

1 = PCIe receiver can process downstream I/O transactions. The bridge can forward

I/O transactions to the PCI interface.

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4.4 Status Register

The status register provides information about the PCIe interface to the system. See Table 4-3 for a complete description of the register contents.

PCI register offset: 06h Register type: Read only, Read/Clear Default value: 0010h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Table 4-3. Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15 PAR_ERR RCU Detected parity error. This bit is set when the PCIe interface receives a poisoned TLP. This

14 SYS_ERR RCU Signaled system error. This bit is set when the bridge sends an ERR_FATAL or

13 MABORT RCU Received master abort. This bit is set when the PCIe interface of the bridge receives a

12 TABORT_REC RCUT Received target abort. This bit is set when the PCIe interface of the bridge receives a

11 TABORT_SIG RCUT Signaled target abort. This bit is set when the PCIe interface completes a request with

10:9 PCI_SPEED R DEVSEL timing. These bits are read-only 00b, because they do not apply to PCIe.

8 DATAPAR RCU Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset

7 FBB_CAP R Fast back-to-back capable. This bit does not have a meaningful context for a PCIe device

6 RSVD R Reserved. Returns 0b when read. 5 66MHZ R 66-MHz capable. This bit does not have a meaningful context for a PCIe device and is

4 CAPLIST R Capabilities list. This bit returns 1b when read, indicating that the bridge supports additional

3 INT_STATUS R Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only 0b

2:0 RSVD R Reserved. Returns 000b when read.

bit is set regardless of the state of bit 6 (PERR_ENB) in the command register (offset 04h, see Section 4.3).

0 = No parity error detected 1 = Parity error detected

ERR_NONFATAL message and bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set.

0 = No error signaled 1 = ERR_FATAL or ERR_NONFATAL signaled

completion-with-unsupported-request status.

0 = Unsupported request not received on the PCIe interface 1 = Unsupported request received on the PCIe interface

completion-with-completer-abort status.

0 = Completer abort not received on the PCIe interface 1 = Completer abort received on the PCIe interface

completer abort status.

0 = Completer abort not signaled on the PCIe interface 1 = Completer abort signaled on the PCIe interface

04h, see Section 4.3) is set and the bridge receives a completion with data marked as poisoned on the PCIe interface or poisons a write request received on the PCIe interface.

0 = No uncorrectable data error detected on the primary interface 1 = Uncorrectable data error detected on the primary interface

and is hardwired to 0b.

hardwired to 0b.

PCI capabilities.

since the bridge does not generate any interrupts internally.

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4.5 Class Code and Revision ID Register

This read-only register categorizes the base class, subclass, and programming interface of the bridge. The base class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a PCI to PCI bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in the lower byte (00h). See Table 4-4 for a complete description of the register contents.

PCI register offset: 08h Register type: Read only Default value: 0604 0001h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Table 4-4. Class Code and Revision ID Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:24 BASECLASS R Base class. This field returns 06h when read, which classifies the function as a bridge device. 23:16 SUBCLASS R Subclass. This field returns 04h when read, which classifies the function as a PCI to PCI bridge.

15:8 PGMIF R Programming interface. This field returns 00h when read.

7:0 CHIPREV R Silicon revision. This field returns the silicon revision of the function.

4.6 Cache Line Size Register

If the EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is 0, Cheetah- Express shall use side-band signals from the 1394b OHCI core to determine how much data to fetch when handling delayed read transactions. In this case, the cache line size register will have no effect on the design and will essentially be a read/write scratchpad register. If the EN_CACHE_LINE_CHECK bit is 1, the cache line size register is used by the bridge to determine how much data to prefetch when handling delayed read transactions. In this case, the value in this register must be programmed to a power of 2, and any value greater than 32 DWORDs will be treated as 32 DWORDs.

PCI register offset: 0Ch Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.7 Primary Latency Timer Register

This read-only register has no meaningful context for a PCIe device and returns 00h when read.

PCI register offset: 0Dh Register type: Read only Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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4.8 Header Type Register

This read-only register indicates that this function has a type 1 PCI header. Bit 7 of this register is 0b, indicating that the bridge is a single-function device.

PCI register offset: 0Eh Register type: Read only Default value: 01h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 1

4.9 BIST Register

Since the bridge does not support a built-in self test (BIST), this read-only register returns the value of 00h when read.

PCI register offset: 0Fh Register type: Read only Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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4.10 Device Control Base Address Register

This read/write register programs the memory base address that accesses the device control registers. See Table 4-5 for a complete description of the register contents.

PCI register offset: 10h Register type: Read only, Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-5. Device Control Base Address Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:12 ADDRESS R or RW Memory address. The memory address field for XIO2213B uses 20 read/write bits indicating

11:4 RSVD R Reserved. These bits are read only and return 00h when read.

3 PRE_FETCH R Prefetchable. This bit is read-only 0b indicating that this memory window is not prefetchable.

2:1 MEM_TYPE R Memory type. This field is read-only 00b indicating that this window can be located anywhere

0 MEM_IND R Memory space indicator. This field returns 0b indicating that memory space is used.

that 4096 bytes of memory space are required. While less than this is actually used, typical systems will allocate this space on a 4K boundary. If the BAR0_EN bit (bit 5 at C8h) is 0, these bits are read only and return zeros when read. If the BAR0_EN bit is 1, these bits are read/write.

in the 32-bit address space.

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4.11 Scratchpad RAM Base Address

This register is used to program the memory address used to access the embedded scratchpad RAM.

PCI register offset: 14h Register type: Read only, Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-6. Device Control Base Address Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:12 ADDRESS R or RW Memory address. The memory address field for XIO2213B uses 20 read/write bits indicating

11:4 RSVD R Reserved. These bits are read only and return 00h when read.

3 PRE_FETCH R Prefetchable. This bit is read-only 0b indicating that this memory window is not prefetchable.

2:1 MEM_TYPE R Memory type. This field is read-only 00b indicating that this window can be located anywhere

0 MEM_IND R Memory space indicator. This field returns 0b indicating that memory space is used.

that 4096 bytes of memory space are required. If the BAR1_EN bit (bit 6 at C8h) is 0, these bits are read only and return zeros when read. If the BAR1_EN bit is 1, these bits are read/write.

in the 32-bit address space.

4.12 Primary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCIe interface is connected to.

PCI register offset: 18h Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.13 Secondary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected to. The bridge uses this register to determine how to respond to a type 1 configuration transaction.

PCI register offset: 19h Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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4.14 Subordinate Bus Number Register

This read/write register specifies the bus number of the highest-number PCI bus segment that is downstream of the bridge. Since the PCI bus is internal and only connects to the 1394a OHCI, this register must always be equal to the secondary bus number register (offset 19h, see Section 4.13). The bridge uses this register to determine how to respond to a type 1 configuration transaction.

PCI register offset: 1Ah Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.15 Secondary Latency Timer Register

This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles.

PCI register offset: 1Bh Register type: Read/Write Default value: 00h

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BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.16 I/O Base Register

This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream. See Table 4-7 for a complete description of the register contents.

PCI register offset: 1Ch Register type: Read only, Read/Write Default value: 01h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 1

Table 4-7. I/O Base Register Description

BIT FIELD NAME ACCESS DESCRIPTION

7:4 IOBASE

3:0 IOTYPE R I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.

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4.17 I/O Limit Register

This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream. See Table 4-8 for a complete description of the register contents.

PCI register offset: 1Dh Register type: Read only, Read/Write Default value: 01h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 1

Table 4-8. I/O Limit Register Description

BIT FIELD NAME ACCESS DESCRIPTION

7:4 IOLIMIT RW I/O limit. Defines the top address of the I/O address range that determines when to forward I/O

transactions from one interface to the other. These bits correspond to address bits [15:12] in the I/O address. The lower 12 bits are assumed to be FFFh. The 16 bits corresponding to address bits [31:16] of the I/O address are defined in the I/O limit upper 16 bits register (offset 32h, see

Section 4.26).

3:0 IOTYPE R I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.

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4.18 Secondary Status Register

The secondary status register provides information about the PCI bus interface. See Table 4-9 for a complete description of the register contents.

PCI register offset: 1Eh Register type: Read only, Read/Clear Default value: 02X0h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 1 0 x 0 0 0 0 0 0 0

Table 4-9. Secondary Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15 PAR_ERR RCU Detected parity error. This bit reports the detection of an uncorrectable address, attribute, or data

14 SYS_ERR RCU Received system error. This bit is set when the bridge detects an SERR assertion.

13 MABORT RCU Received master abort. This bit is set when the PCI interface of the bridge reports the detection of a

12 TABORT_REC RCU Received target abort. This bit is set when the PCI interface of the bridge receives a target abort.

11 TABORT_SIG RCU Signaled target abort. This bit reports the signaling of a target abort termination by the bridge when it

10:9 PCI_SPEED R DEVSEL timing. These bits are 01b indicating that this is a medium-speed decoding device.

8 DATAPAR RCU Master data parity error. This bit is set if the bridge is the bus master of the transaction on the PCI

7 FBB_CAP R Fast back-to-back capable. This bit returns a 1b when read indicating that the secondary PCI

6 RSVD R Reserved. Returns 0b when read. 5 66MHZ R 66-MHz capable. The bridge operates at a PCI bus CLK frequency of 66 MHz; therefore, this bit

4:0 RSVD R Reserved. Returns 00000b when read.

error by the bridge on its internal PCI bus secondary interface. This bit must be set when any of the following three conditions are true:

The bridge detects an uncorrectable address or attribute error as a potential target. The bridge detects an uncorrectable data error when it is the target of a write transaction. The bridge detects an uncorrectable data error when it is the master of a read transaction

(immediate read data).

The bit is set irrespective of the state of bit 0 (PERR_EN) in the bridge control register at offset 3Eh (see Section 4.30).

0 = Uncorrectable address, attribute, or data error not detected on secondary interface 1 = Uncorrectable address, attribute, or data error detected on secondary interface

0 = No error asserted on the PCI interface 1 = SERR asserted on the PCI interface

master abort termination by the bridge when it is the master of a transaction on its secondary interface.

0 = Master abort not received on the PCI interface 1 = Master abort received on the PCI interface

0 = Target abort not received on the PCI interface 1 = Target abort received on the PCI interface

responds as the target of a transaction on its secondary interface.

0 = Target abort not signaled on the PCI interface 1 = Target abort signaled on the PCI interface

bus, bit 0 (PERR_EN) in the bridge control register (offset 3Eh see Section 4.30) is set, and the bridge either asserts PERR on a read transaction or detects PERR asserted on a write transaction.

0 = No data parity error detected on the PCI interface 1 = Data parity error detected on the PCI interface

interface of bridge supports fast back-to-back transactions.

always returns a 1b.

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4.19 Memory Base Register

This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream. See Table 4-10 for a complete description of the register contents.

PCI register offset: 20h Register type: Read only, Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-10. Memory Base Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:4 MEMBASE RW Memory base. Defines the lowest address of the memory address range that determines when to

3:0 RSVD R Reserved. Returns 0h when read.

forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 00000h.

4.20 Memory Limit Register

This read/write register specifies the upper limit of the memory addresses that the bridge forwards downstream. See Table 4-11 for a complete description of the register contents.

PCI register offset: 22h Register type: Read only, Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-11. Memory Limit Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:4 MEMLIMIT RW Memory limit. Defines the highest address of the memory address range that determines when to

3:0 RSVD R Reserved. Returns 0h when read.

forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh.

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4.21 Prefetchable Memory Base Register

This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge forwards downstream. See Table 4-12 for a complete description of the register contents.

PCI register offset: 24h Register type: Read only, Read/Write Default value: 0001h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Table 4-12. Prefetchable Memory Base Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:4 PREBASE RW Prefetchable memory base. Defines the lowest address of the prefetchable memory address range

3:0 64BIT R 64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this

that determines when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 00000h. The prefetchable base upper 32 bits register (offset 28h, see Section 4.23) specifies the bit [63:32] of the 64-bit prefetchable memory address.

memory window.

4.22 Prefetchable Memory Limit Register

This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge forwards downstream. See Table 4-13 for a complete description of the register contents.

PCI register offset: 26h Register type: Read only, Read/Write Default value: 0001h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Table 4-13. Prefetchable Memory Limit Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:4 PRELIMIT RW Prefetchable memory limit. Defines the highest address of the prefetchable memory address range

3:0 64BIT R 64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this

that determines when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh. The prefetchable limit upper 32 bits register (offset 2Ch, see Section 4.24) specifies the bit [63:32] of the 64-bit prefetchable memory address.

memory window.

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4.23 Prefetchable Base Upper 32 Bits Register

This read/write register specifies the upper 32 bits of the prefetchable memory base register. See Table 4-

14 for a complete description of the register contents.

PCI register offset: 28h Register type: Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-14. Prefetchable Base Upper 32 Bits Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:0 PREBASE RW Prefetchable memory base upper 32 bits. Defines the upper 32 bits of the lowest address of the

prefetchable memory address range that determines when to forward memory transactions downstream.

4.24 Prefetchable Limit Upper 32 Bits Register

This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See Table 4-

15 for a complete description of the register contents.

PCI register offset: 2Ch Register type: Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-15. Prefetchable Limit Upper 32 Bits Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:0 PRELIMIT RW Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the

prefetchable memory address range that determines when to forward memory transactions downstream.

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4.25 I/O Base Upper 16 Bits Register

This read/write register specifies the upper 16 bits of the I/O base register. See Table 4-16 for a complete description of the register contents.

PCI register offset: 30h Register type: Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-16. I/O Base Upper 16 Bits Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:0 IOBASE RW I/O base upper 16 bits. Defines the upper 16 bits of the lowest address of the I/O address range

that determines when to forward I/O transactions downstream. These bits correspond to address bits [31:20] in the I/O address. The lower 20 bits are assumed to be 00000h.

4.26 I/O Limit Upper 16 Bits Register

This read/write register specifies the upper 16 bits of the I/O limit register. See Table 4-17 for a complete description of the register contents.

PCI register offset: 32h Register type: Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-17. I/O Limit Upper 16 Bits Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:0 IOLIMIT RW I/O limit upper 16 bits. Defines the upper 16 bits of the top address of the I/O address range that

determines when to forward I/O transactions downstream. These bits correspond to address bits [31:20] in the I/O address. The lower 20 bits are assumed to be FFFFFh.

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4.27 Capabilities Pointer Register

This read-only register provides a pointer into the PCI configuration header where the PCI power management block resides. Since the PCI power-management registers begin at 50h, this register is hardwired to 50h.

PCI register offset: 34h Register type: Read only Default value: 50h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 1 0 0 0 0

4.28 Interrupt Line Register

This read/write register is programmed by the system and indicates to the software which interrupt line the bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet been assigned to the function. Since the bridge does not generate interrupts internally, this register is a scratchpad register.

PCI register offset: 3Ch Register type: Read/Write Default value: FFh

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BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 1 1 1 1 1 1 1 1

4.29 Interrupt Pin Register

The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts. While the bridge does not generate internal interrupts, it does forward interrupts from the secondary interface to the primary interface.

PCI register offset: 3Dh Register type: Read only Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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4.30 Bridge Control Register

The bridge control register provides extensions to the command register that are specific to a bridge. See

Table 4-18 for a complete description of the register contents.

PCI register offset: 3Eh Register type: Read only, Read/Write, Read/Clear Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-18. Bridge Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:12 RSVD R Reserved. Returns 0h when read.

11 DTSERR RW Discard timer SERR enable. Applies only in conventional PCI mode. This bit enables the

10 DTSTATUS RCU Discard timer status. This bit indicates if a discard timer expires and a delayed transaction

9 SEC_DT RW selects the number of PCI clocks that the bridge waits for the 1394a OHCI master on

8 PRI_DEC R Primary discard timer. This bit has no meaning in PCIe and is hardwired to 0b. 7 FBB_EN RW Fast back-to-back enable. This bit allows software to enable fast back-to-back

6 SRST RW Secondary bus reset. This bit is set when software wishes to reset all devices

bridge to generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on the primary interface when the secondary discard timer expires and a delayed transaction is discarded from a queue in the bridge. The severity is selectable only if advanced error reporting is supported.

0 = Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a

result of the expiration of the secondary discard timer. Note that an error message

can still be sent if advanced error reporting is supported and bit 10

(DISCARD_TIMER_MASK) in the secondary uncorrectable error mask register

(offset 130h, see Section 5.11) is clear (default).

1 = Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the

secondary discard timer expires and a delayed transaction is discarded from a

queue in the bridges.

is discarded.

0 = No discard timer error 1 = Discard timer error

the secondary interface to repeat a delayed transaction request. The counter starts once the delayed completion (the completion of the delayed transaction on the primary interface) has reached the head of the downstream queue of the bridge (i.e., all ordering requirements have been satisfied and the bridge is ready to complete the delayed transaction with the initiating master on the secondary bus). If the master does not repeat the transaction before the counter expires, the bridge deletes the delayed transaction from its queue and sets the discard timer status bit.

0 = Secondary discard timer counts 215PCI clock cycles (default). 1 = Secondary discard timer counts 210PCI clock cycles.

transactions on the secondary PCI interface.

0 = Fast back-to-back transactions are disabled (default). 1 = Secondary interface fast back-to-back transactions are enabled.

downstream of the bridge. Setting this bit causes the PRST signal on the secondary interface to be asserted.

0 = Secondary interface is not in reset state (default). 1 = Secondary interface is in the reset state.

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Table 4-18. Bridge Control Register Description (continued)

BIT FIELD NAME ACCESS DESCRIPTION

5 MAM RW Master abort mode. This bit controls the behavior of the bridge when it receives a master

abort or an unsupported request.

0 = Do not report master aborts. Returns FFFF FFFFh on reads and discard data on

writes (default).

1 = Respond with an unsupported request on PCIe when a master abort is received on

PCI. Respond with target abort on PCI when an unsupported request completion

on PCIe is received. This bit also enables error signaling on master abort

conditions on posted writes.

4 VGA16 RW VGA 16-bit decode. This bit enables the bridge to provide full 16-bit decoding for VGA I/O

addresses. This bit only has meaning if the VGA enable bit is set.

0 = Ignore address bits [15:10] when decoding VGA I/O addresses (default) 1 = Decode address bits [15:10] when decoding VGA I/O addresses

3 VGA RW VGA enable. This bit modifies the response by the bridge to VGA compatible addresses.

If this bit is set, the bridge decodes and forwards the following accesses on the primary interface to the secondary interface (and, conversely, block the forwarding of these addresses from the secondary to primary interface):

Memory accesses in the range 000A 0000h to 000B FFFFh

I/O addresses in the first 64 KB of the I/O address space (address bits [31:16] are

0000h) and where address bits [9:0] are in the range of 3B0h to 3BBh or 3C0h to

3DFh (inclusive of ISA address aliases – address bits [15:10] may possess any

value and are not used in the decoding)

If this bit is set, forwarding of VGA addresses is independent of the value of bit 2 (ISA), the I/O address and memory address ranges defined by the I/O base and limit registers, the memory base and limit registers, and the prefetchable memory base and limit registers of the bridge. The forwarding of VGA addresses is qualified by bits 0 (IO_ENB) and 1 (MEMORY_ENB) in the command register (offset 04h, see Section 4.3).

0 = Do not forward VGA-compatible memory and I/O addresses from the primary to

secondary interface (addresses previously defined) unless they are enabled for

forwarding by the defined I/O and memory address ranges (default).

1 = Forward VGA-compatible memory and I/O addresses (addresses previously

defined) from the primary interface to the secondary interface (if the I/O enable and

memory enable bits are set) independent of the I/O and memory address ranges

and independent of the ISA enable bit.

2 ISA RW ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This

applies only to I/O addresses that are enabled by the I/O base and I/O limit registers and are in the first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the bridge blocks any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they address the last 768 bytes in each 1-KB block.

0 = Forward downstream all I/O addresses in the address range defined by the I/O

base and I/O limit registers (default)

1 = Forward upstream ISA I/O addresses in the address range defined by the I/O base

and I/O limit registers that are in the first 64 KB of PCI I/O address space (top 768

bytes of each 1-KB block)

1 SERR_EN RW SERR enable. This bit controls forwarding of system error events from the secondary

interface to the primary interface. The bridge forwards system error events when:

This bit is set.

Bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set.

SERR is asserted on the secondary interface.

0 = Disable the forwarding of system error events (default) 1 = Enable the forwarding of system error events

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Table 4-18. Bridge Control Register Description (continued)

BIT FIELD NAME ACCESS DESCRIPTION

0 PERR_EN RW Parity error response enable. Controls the bridge's response to data, uncorrectable

address, and attribute errors on the secondary interface. Also, the bridge always forwards data with poisoning, from conventional PCI to PCIe on an uncorrectable conventional PCI data error, regardless of the setting of this bit.

0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface

(default)

1 = Enable uncorrectable address, attribute, and data error detection and reporting on

the secondary interface

4.31 PM Capability ID Register

This read-only register identifies the linked list item as the register for PCI power management. The register returns 01h when read.

PCI register offset: 50h Register type: Read only Default value: 01h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 1

4.32 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 80h pointing to the subsystem ID capabilities registers.

PCI register offset: 51h Register type: Read only Default value: 60h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 1 0 0 0 0 0

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4.33 Power Management Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCI power management. See

Table 4-19 for a complete description of the register contents.

PCI register offset: 52h Register type: Read only Default value: 0603h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1

Table 4-19. Power Management Capabilities Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:11 PME_SUPPORT R PME support. This 5-bit field indicates the power states from which the bridge may assert

10 D2_SUPPORT R This bit returns a 1b when read, indicating that the function supports the D2 device power

9 D1_SUPPORT R This bit returns a 1b when read, indicating that the function supports the D1 device power

8:6 AUX_CURRENT R 3.3 V

5 DSI R Device specific initialization. This bit returns 0b when read, indicating that the bridge does

4 RSVD R Reserved. Returns 0b when read. 3 PME_CLK R PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.

2:0 PM_VERSION R Power-management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control

PME. Because the bridge never generates a PME except on a behalf of a secondary device, this field is read only and returns 00000b.

state.

auxiliary current requirements. This field returns 000b since the bridge does not

AUX

generate PME from D3

not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it.

register (offset D4h, see Section 4.66) is 0b, this field returns 010b indicating revision 1.1 compatibility. If PCI_PM_VERSION_CTRL is 1b, this field returns 011b indicating revision

1.2 compatibility.

cold

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4.34 Power Management Control/Status Register

This register determines and changes the current power state of the bridge. No internal reset is generated when transitioning from the D3 register contents.

PCI register offset: 54h Register type: Read only, Read/Write Default value: 0008h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Table 4-20. Power Management Control/Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15 PME_STAT R PME status. This bit is read only and returns 0b when read.

14:13 DATA_SCALE R Data scale. This 2-bit field returns 00b when read since the bridge does not use the data

12:9 DATA_SEL R Data select. This 4-bit field returns 0h when read since the bridge does not use the data

8 PME_EN RW PME enable. This bit has no function and acts as scratchpad space. The default value for

7:4 RSVD R Reserved. Returns 0h when read.

3 NO_SOFT_RESET R No soft reset. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register (offset

2 RSVD R Reserved. Returns 0b when read.

1:0 PWR_STATE RW Power state. This 2-bit field determines the current power state of the function and sets the

state to the D0 state. See Table 4-20 for a complete description of the

hot

this bit is 0b.

D4h, see Section 4.66) is 0b, this bit returns 0b for compatibility with version 1.1 of the PCI Power Management Specification. If PCI_PM_VERSION_CTRL is 1b, this bit returns 1b indicating that no internal reset is generated and the device retains its configuration context when transitioning from the D3

function into a new power state. This field is encoded as follows:

00 = D0 (default)

01 = D1

10 = D2

11 = D3

hot

state to the D0 state.

hot

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4.35 Power Management Bridge Support Extension Register

This read-only register indicates to host software what the state of the secondary bus will be when the bridge is placed in D3. See Table 4-21 for a complete description of the register contents.

PCI register offset: 56h Register type: Read only Default value: 40h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 0 0 0 0 0

Table 4-21. PM Bridge Support Extension Register Description

BIT FIELD NAME ACCESS DESCRIPTION

7 BPCC R Bus power/clock control enable. This bit indicates to the host software if the bus secondary

clocks are stopped when the bridge is placed in D3. The state of the BPCC bit is controlled by bit 11 (BPCC_E) in the general control register (offset D4h, see

Section 4.66).

0 = Secondary bus clocks are not stopped in D3. 1 = Secondary bus clocks are stopped in D3.

6 BSTATE R B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2.

5:0 RSVD R Reserved. Returns 00 0000b when read.

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4.36 Power Management Data Register

The read-only register is not applicable to the bridge and returns 00h when read.

PCI register offset: 57h Register type: Read only Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.37 MSI Capability ID Register

This read-only register identifies the linked list item as the register for message signaled interrupts capabilities. The register returns 05h when read.

PCI register offset: 60h Register type: Read only Default value: 05h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 1 0 1

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4.38 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 80h pointing to the subsystem ID capabilities registers.

PCI register offset: 61h Register type: Read only Default value: 80h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 1 0 0 0 0 0 0 0

4.39 MSI Message Control Register

This register controls the sending of MSI messages. See Table 4-22 for a complete description of the register contents.

PCI register offset: 62h Register type: Read only, Read/Write Default value: 0088h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0

Table 4-22. MSI Message Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:8 RSVD R Reserved. Returns 00h when read.

7 64CAP R 64-bit message capability. This bit is read-only 1b indicating that the bridge supports 64-bit

6:4 MM_EN RW Multiple message enable. This bit indicates the number of distinct messages that the

3:1 MM_CAP R Multiple message capabilities. This field indicates the number of distinct messages that the

0 MSI_EN RW MSI enable. This bit enables MSI interrupt signaling. MSI signaling must be enabled by

MSI message addressing.

bridge is allowed to generate.

000 = 1 message (default) 001 = 2 messages 010 = 4 messages 011 = 8 messages 100 = 16 messages 101 = Reserved 110 = Reserved 111 = Reserved

bridge is capable of generating. This field is read-only 100b, indicating that the bridge can signal 1 interrupt for each IRQ supported on the serial IRQ stream up to a maximum of 16 unique interrupts.

software for the bridge to signal that a serial IRQ has been detected.

0 = MSI signaling is prohibited (default). 1 = MSI signaling is enabled.

NOTE

Enabling MSI messaging in the XIO2213B has no effect.

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4.40 MSI Message Lower Address Register

This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is detected. See Table 4-23 for a complete description of the register contents.

PCI register offset: 64h Register type: Read only, Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-23. MSI Message Lower Address Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:2 ADDRESS RW System specified message address

1:0 RSVD R Reserved. Returns 00b when read.

NOTE

Enabling MSI messaging in the XIO2213B has no effect.

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4.41 MSI Message Upper Address Register

This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is detected. If this register contains 0000 0000h, 32-bit addressing is used; otherwise, 64-bit addressing is used.

PCI register offset: 68h Register type: Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NOTE

Enabling MSI messaging in the XIO2213B has no effect.

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4.42 MSI Message Data Register

This register contains the data that software programmed the bridge to send when it send a MSI message. See Table 4-24 for a complete description of the register contents.

PCI register offset: 6Ch Register type: Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-24. MSI Message Data Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:4 MSG RW System specific message. This field contains the portion of the message that the bridge

3:0 MSG_NUM RW Message number. This portion of the message field may be modified to contain the

forwards unmodified.

message number is multiple messages are enable. The number of bits that are modifiable depends on the number of messages enabled in the message control register.

1 message = No message data bits can be modified (default). 2 messages = Bit 0 can be modified. 4 messages = Bits 1:0 can be modified. 8 messages = Bits 2:0 can be modified. 16 messages = Bits 3:0 can be modified.

Enabling MSI messaging in the XIO2213B has no effect.

4.43 SSID/SSVID Capability ID Register

This read-only register identifies the linked list item as the register for subsystem ID and subsystem vendor ID capabilities. The register returns 0Dh when read.

PCI register offset: 80h Register type: Read only Default value: 0Dh

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 1 1 0 1

4.44 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 90h pointing to the PCI Express capabilities registers.

PCI register offset: 81h Register type: Read only Default value: 90h

NOTE

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 1 0 0 1 0 0 0 0

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4.45 Subsystem Vendor ID Register

This register, used for system and option card identification purposes, may be required for certain operating systems. This read-only register is initialized through the EEPROM and can be written through the subsystem alias register. This register shall only be reset by a fundamental reset (FRST).

PCI register offset: 84h Register type: Read only Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.46 Subsystem ID Register

PCI register offset: 86h Register type: Read only Default value: 0000h

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BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.47 PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for PCIe capabilities. The register returns 10h when read.

PCI register offset: 90h Register type: Read only Default value: 10h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 1 0 0 0 0

4.48 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This register reads 00h indicating no additional capabilities are supported.

PCI register offset: 91h Register type: Read only Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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4.49 PCI Express Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCIe. See Table 4-25 for a complete description of the register contents.

PCI register offset: 92h Register type: Read only Default value: 0071h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1

Table 4-25. PCI Express Capabilities Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:9 RSVD R Reserved. Returns 000 0000b when read.

8 SLOT R Slot implemented. This bit is not valid for the bridge and is read-only 0b.

7:4 DEV_TYPE R Device/port type. This read-only field returns 0111b indicating that the device is a PCIe to

3:0 VERSION R Capability version. This field returns 1h indicating revision 1 of the PCIe capability.

PCI bridge.

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4.50 Device Capabilities Register

This register indicates the device-specific capabilities of the bridge. See Table 4-26 for a complete description of the register contents.

PCI register offset: 94h Register type: Read only Default value: 0000 8002

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Table 4-26. Device Capabilities Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:28 RSVD R Reserved. Returns 0h when read. 27:26 CSPLS RU Captured slot power limit scale. The value in this field is programmed by the host by issuing a

25:18 CSPLV RU Captured slot power limit value. The value in this field is programmed by the host by issuing a

17:16 RSVD R Reserved. Return 000b when read.

15 RBER R Role-based error reporting. This bit is hardwired to 1 indicating that the XIO2213B supports

14 PIP R Power indicator present. This bit is hardwired to 0b indicating that a power indicator is not

13 AIP R Attention indicator present. This bit is hardwired to 0b indicating that an attention indicator is not

12 ABP R Attention button present. This bit is hardwired to 0b indicating that an attention button is not

11:9 EP_L1_LAT RU Endpoint L1 acceptable latency. This field indicates the maximum acceptable latency for a

8:6 EP_L0S_LAT RU Endpoint L0s acceptable latency. This field indicates the maximum acceptable latency for a

5 ETFS R Extended tag field supported. This field indicates the size of the tag field not supported.

4:3 PFS R Phantom functions supported. This field is read-only 00b indicating that function numbers are

2:0 MPSS R Maximum payload size supported. This field indicates the maximum payload size that the

Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 9:8 are written to this field. The value in this field specifies the scale used for the slot power limit.

00 = 1.0x 01 = 0.1x 10 = 0.01x 11 = 0.001x1

Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 7:0 are written to this field. The value in this field in combination with the slot power limit scale value (bits 27:26) specifies the upper limit of power supplied to the slot. The power limit is calculated by multiplying the value in this field by the value in the slot power limit scale field.

role-based error reporting.

implemented.

transition from L1 to L0 state. This field can be programmed by writing to the L1_LATENCY field (bits 15:13) in the general control register (offset D4h, see Section 4.66). The default value for this field is 000b, which indicates a range less than 1s. This field cannot be programmed to be less than the latency for the PHY to exit the L1 state.

transition from L0s to L0 state. This field can be programmed by writing to the L0s_LATENCY field (bits 18:16) in the general control register (offset D4h, see Section 4.66). The default value for this field is 000b, which indicates a range less than 1s. This field cannot be programmed to be less than the latency for the PHY to exit the L0s state.

not used for phantom functions.

device can support for TLPs. This field is encoded as 010b indicating the maximum payload size for a TLP is 512 bytes.

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4.51 Device Control Register

The device control register controls PCIe device-specific meters. See Table 4-27 for a complete description of the register contents.

PCI register offset: 98h Register type: Read only, Read/Write Default value: 2800h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0

Table 4-27. Device Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15 CFG_RTRY_ENB RW Configuration retry status enable. When this read/write bit is set to 1b, the bridge returns a

14:12 MRRS RW Maximum read request size. This field is programmed by host software to set the maximum

11 ENS RW Enable no snoop. Controls the setting of the no snoop flag within the TLP header for upstream

10* APPE RW Auxiliary power PM enable. This bit has no effect in the bridge.

9 PFE R Phantom function enable. Since the bridge does not support phantom functions, this bit is

8 ETFE R Extended tag field enable. Since the bridge does not support extended tags, this bit is read-

7:5 MPS RW Maximum payload size. This field is programmed by host software to set the maximum size of

4 ERO R Enable relaxed ordering. Since the bridge does not support relaxed ordering, this bit is read-

3 URRE RW Unsupported request reporting enable. If this bit is set, the bridge sends an ERR_NONFATAL

completion with completion retry status on PCIe if a configuration transaction forwarded to the secondary interface did not complete within the implementation specific time-out period. When this bit is set to 0b, the bridge does not generate completions with completion retry status on behalf of configuration transactions. The default value of this bit is 0b.

size of a read request that the bridge can generate. The bridge uses this field in conjunction with the cache line size register (offset 0Ch, see Section 7.6) to determine how much data to fetch on a read request. This field is encoded as:

000 = 128B 001 = 256B 010 = 512B (default) 011 = 1024B 100 = 2048B 101 = 4096B 110 = Reserved 111 = Reserved

memory transactions mapped to any traffic class mapped to a virtual channel (VC) other than VC0 through the upstream decode windows.

0 = No snoop field is 0b. 1 = No snoop field is 1b (default).

0 = AUX power is disabled (default). 1 = AUX power is enabled.

read-only 0b.

only 0b.

posted writes or read completions that the bridge can initiate. This field is encoded as:

000 = 128B (default) 001 = 256B 010 = 512B 011 = 1024B 100 = 2048B 101 = 4096B 110 = Reserved 111 = Reserved

only 0b.

message to the root complex when an unsupported request is received.

0 = Do not report unsupported requests to the root complex (default) 1 = Report unsupported requests to the root complex

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Table 4-27. Device Control Register Description (continued)

BIT FIELD NAME ACCESS DESCRIPTION

2 FERE RW Fatal error reporting enable. If this bit is set, the bridge is enabled to send ERR_FATAL

messages to the root complex when a system error event occurs.

0 = Do not report fatal errors to the root complex (default) 1 = Report fatal errors to the root complex

1 NFERE RW Nonfatal error reporting enable. If this bit is set, the bridge is enabled to send

ERR_NONFATAL messages to the root complex when a system error event occurs.

0 = Do not report nonfatal errors to the root complex (default) 1 = Report nonfatal errors to the root complex

0 CERE RW Correctable error reporting enable. If this bit is set, the bridge is enabled to send ERR_COR

messages to the root complex when a system error event occurs.

0 = Do not report correctable errors to the root complex (default) 1 = Report correctable errors to the root complex

4.52 Device Status Register

The device status register provides PCIe device specific information to the system. See Table 4-28 for a complete description of the register contents.

PCI register offset: 9Ah Register type: Read only Default value: 0000h

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BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-28. Device Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:6 RSVD R Reserved. Returns 00 0000 0000b when read.

5 PEND RU Transaction pending. This bit is set when the bridge has issued a nonposted transaction that has

4 APD RU AUX power detected. This bit indicates that AUX power is present.

3 URD RCU Unsupported request detected. This bit is set by the bridge when an unsupported request is

2 FED RCU Fatal error detected. This bit is set by the bridge when a fatal error is detected. 1 NFED RCU Nonfatal error detected. This bit is set by the bridge when a nonfatal error is detected. 0 CED RCU Correctable error detected. This bit is set by the bridge when a correctable error is detected.

not been completed.

0 = No AUX power detected 1 = AUX power detected

received.

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4.53 Link Capabilities Register

The link capabilities register indicates the link-specific capabilities of the bridge. See Table 4-29 for a complete description of the register contents.

PCI register offset: 9Ch Register type: Read only Default value: 0006 XC11h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 x x x 1 1 0 0 0 0 0 1 0 0 0 1

Table 4-29. Link Capabilities Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:24 PORT_NUM R Port number. This field indicates port number for the PCIe link. This field is read-only 00h

23:19 RSVD R Reserved. Return 00 0000b when read.

18 CLK_PM R Clock power management. This bit is hardwired to 1 to indicate that XIO2213B supports clock

17:15 L1_LATENCY R L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the L0

14:12 L0S_LATENCY R L0s exit latency. This field indicates the time that it takes to transition from the L0s state to the

11:10 ASLPMS R Active-state link PM support. This field indicates the level of active-state power management

9:4 MLW R Maximum link width. This field is encoded 00 0001b to indicate that the bridge only supports a

3:0 MLS R Maximum link speed. This field is encoded 1h to indicate that the bridge supports a maximum

indicating that the link is associated with port 0.

power management through CLKREQ protocol.

state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.54) equals 1b for a common clock and equals 0b for an asynchronous clock.

For a common reference clock, the value of this field is determined by bits 20:18 (L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see Section 4.63).

For an asynchronous reference clock, the value of this field is determined by bits 17:15 (L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see

Section 4.63).

L0 state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.54) equals 1b for a common clock and equals 0b for an asynchronous clock.

For a common reference clock, the value of 011b indicates that the L1 exit latency falls between 256 ns to less than 512 ns.

For an asynchronous reference clock, the value of 100b indicates that the L1 exit latency falls between 512 ns to less than 1 s.

that the bridge supports. The value 11b indicates support for both L0s and L1 through activestate power management.

1× PCIe link.

link speed of 2.5 Gb/s.

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4.54 Link Control Register

The link control register controls link-specific behavior. See Table 4-30 for a complete description of the register contents.

PCI register offset: A0h Register type: Read only, Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-30. Link Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:9 RSVD RW Reserved. Returns 00h when read.

8 CPM_EN RW Clock power management enable. This bit is used to enable XIO2213B to use CLKREQ

for clock power management

0 = Clock power management is disabled and XIO2213B shall hold the CLKREQ signal low. 1 = Clock power management is enabled and XIO2213B is permitted to use the CLKREQ signal to allow the REFCLK input to be stopped.

7 ES RW Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets

and an extra TS2 when exiting from L1 prior to entering to L0.

0 = Normal synch (default) 1 = Extended synch

6 CCC RW Common clock configuration. When this bit is set, it indicates that the bridge and the

device at the opposite end of the link are operating with a common clock source. A value of 0b indicates that the bridge and the device at the opposite end of the link are operating with se te reference clock sources. The bridge uses this common clock configuration information to report the correct L0s and L1 exit latencies.

0 = Reference clock is asynchronous (default).

1 = Reference clock is common. 5 RL R Retrain link. This bit has no function and is read-only 0b. 4 LD R Link disable. This bit has no function and is read-only 0b. 3 RCB RW Read completion boundary. This bit is an indication of the RCB of the root complex. The

state of this bit has no effect on the bridge, since the RCB of the bridge is fixed at 128 bytes.

0 = 64 bytes (default)

1 = 128 bytes 2 RSVD R Reserved. Returns 0b when read.

1:0 ASLPMC RW Active-state link PM control. This field enables and disables the active-state PM.

00 = Active-state PM disabled (default)

01 = L0s entry enabled

10 = L1 entry enabled

11 = L0s and L1 entry enabled

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4.55 Link Status Register

The link status register indicates the current state of the PCIe link. See Table 4-31 for a complete description of the register contents.

PCI register offset: A2h Register type: Read only Default value: X011h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 x 0 0 0 0 0 0 0 1 0 0 0 1

Table 4-31. Link Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:13 RSVD R Reserved. Returns 000b when read.

12 SCC R Slot clock configuration. This bit indicates that the bridge uses the same physical reference

11 LT R Link training. This bit has no function and is read-only 0b.

10 TE R Retrain link. This bit has no function and is read-only 0b. 9:4 NLW R Negotiated link width. This field is read-only 00 0001b indicating the lane width is 1×. 3:0 LS R Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.

clock that the platform provides on the connector. If the bridge uses an independent clock irrespective of the presence of a reference on the connector, this bit must be cleared.

0 = Independent 125-MHz reference clock is used. 1 = Common 100-MHz reference clock is used.

4.56 Serial-Bus Data Register

The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this register prior to writing the serial-bus slave address register (offset B2h, see Section 4.58) that initiates the bus cycle. When reading data from the serial bus, this register contains the data read after bit 5 (REQBUSY) of the serial-bus control and status register (offset B3h, see Section 4.59) is cleared. This register shall only be reset by FRST.

PCI register offset: B0h Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.57 Serial-Bus Word Address Register

The value written to the serial-bus word address register represents the word address of the byte being read from or written to the serial-bus device. The word address is loaded into this register prior to writing the serial-bus slave address register (offset B2h, see Section 4.58) that initiates the bus cycle. This register shall only be reset by FRST.

PCI register offset: B1h Register type: Read/Write Default value: 00h

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BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.58 Serial-Bus Slave Address Register

The serial-bus slave address register indicates the slave address of the device being targeted by the serial-bus cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register initiates the cycle on the serial interface. See Table 4-32 for a complete description of the register contents.

PCI register offset: B2h Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

Table 4-32. Serial-Bus Slave Address Register Descriptions

BIT FIELD NAME ACCESS DESCRIPTION

(1)

7:1

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

SLAVE_ADDR RW Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write

(1)

RW_CMD RW Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.

transaction. The default value for this field is 000 0000b.

0 = A single byte write is requested (default). 1 = A single byte read is requested.

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4.59 Serial-Bus Control and Status Register

The serial-bus control and status register controls the behavior of the serial-bus interface. This register also provides status information about the state of the serial bus. See Table 4-33 for a complete description of the register contents.

PCI register offset: B3h Register type: Read only, Read/Write, Read/Clear Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

Table 4-33. Serial-Bus Control and Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

(1)

PROT_SEL RW Protocol select. This bit selects the serial-bus address mode used.

0 = Slave address and word address are sent on the serial bus (default 1 = Only the slave address is sent on the serial bus.

6 RSVD R Reserved. Returns 0b when read.

(1)

REQBUSY RU Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle

(1)

ROMBUSY RU Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge

(1)

SBDETECT RWU Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge

(1)

SBTEST RW Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source

(1)

SB_ERR RCU Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus

(1)

ROM_ERR RCU Serial EEPROM load error. This bit is set when an error occurs while downloading registers

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

is in progress.

0 = No serial-bus cycle 1 = Serial-bus cycle in progress

is downloading register defaults from a serial EEPROM.

0 = No EEPROM activity 1 = EEPROM download in progress

is downloading register defaults from a serial EEPROM. Note: A serial EEPROM is only detected once following PERST.

0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL and

GPIO5//SDA terminals are configured as GPIO signals.

1 = EEPROM present, EEPROM load process takes place. GPIO4//SCL and

GPIO5//SDA terminals are configured as serial-bus signals.

for the serial interface clock.

0 = Serial-bus clock at normal operating frequency ~60 kHz (default) 1 = Serial-bus clock frequency increased for test purposes ~4 MHz

cycle.

0 = No error 1 = Serial-bus error

from serial EEPROM.

0 = No error 1 = EEPROM load error

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4.60 GPIO Control Register

This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). See Table 4-34 for a complete description of the register contents.

PCI register offset: B4h Register type: Read only, Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-34. GPIO Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:8 RSVD R Reserved. Return 00h when read.

(1)

GPIO7_DIR RW GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.

0 = Input (default) 1 = Output

(1)

GPIO6_DIR RW GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.

0 = Input (default) 1 = Output

(1)

GPIO5_DIR RW GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.

0 = Input (default) 1 = Output

(1)

GPIO4_DIR RW GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.

0 = Input (default) 1 = Output

(1)

GPIO3_DIR RW GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.

0 = Input (default) 1 = Output

(1)

GPIO2_DIR RW GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.

0 = Input (default) 1 = Output

(1)

GPIO1_DIR RW GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.

0 = Input (default) 1 = Output

(1)

GPIO0_DIR RW GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.

0 = Input (default) 1 = Output

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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4.61 GPIO Data Register

This register reads the state of the input-mode GPIO terminals and changes the state of the output-mode GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs. See Table 4-35 for a complete description of the register contents.

PCI register offset: B6h Register type: Read only, Read/Write Default value: 00XXh

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 x x x x x x x x

Table 4-35. GPIO Data Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:8 RSVD R Reserved

(1)

GPIO7_DATA RW GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of

(1)

GPIO6_DATA RW GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of

(1)

GPIO5_DATA RW GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of

(1)

GPIO4_DATA RW GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of

(1)

GPIO3_DATA RW GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of

(1)

GPIO2_DATA RW GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of

(1)

GPIO1_DATA RW GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of

(1)

GPIO0_DATA RW GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

GPIO7 when in output mode.

GPIO6 when in output mode.

GPIO5 when in output mode.

GPIO4 when in output mode.

GPIO3 when in output mode.

GPIO2 when in output mode.

GPIO1 when in output mode.

GPIO0 when in output mode.

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4.62 Control and Diagnostic Register 0

The contents of this register are used for monitoring status and controlling behavior of the bridge. See

Table 4-36 for a complete description of the register contents. It is recommended that all values within this

register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.

PCI register offset: C0h Register type: Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-36. Control and Diagnostic Register 0 Description

BIT FIELD NAME ACCESS DESCRIPTION

(1)

31:24 23:19

15:14

13:12 RSVD R Reserved. Returns 00b when read.

PRI_BUS_NUM R This field contains the captured primary bus number.

(1)

PRI_DEVICE_NUM R This field contains the captured primary device number.

18 ALT_ERROR_REP RW Alternate error reporting. This bit controls the method that the XIO2213B uses for error

(2)

DIS_BRIDGE_PME RW Disable bridge PME input

(2)

DIS_OHCI_PME RW Disable OHCI_PME

(1)

FIFO_SIZE RW FIFO size. This field contains the maximum size (in DW) of the FIFO.

11 ALLOW_CFG_ANY_FN RW Allow configuration access to any function. When this bit is set, the bridge shall respond

10 RETURN_PW_CREDITS RW Return PW packet credits. When this bit is set, the bridge shall return all the PW packet

9 RSVD R Reserved. Returns 0b when read. 8 RETURN_CPL_CREDITS RW Return completion credits. When this bit is set, the bridge shall return all completion

7 EN_CACHE_LINE_CHECK RW Enable cache line check

reporting.

0 = Advisory nonratal error reporting supported (default) 1 = Advisory nonfatal error reporting not supported

0 = PME input signal to the bridge is enabled and connected to the PME signal

from the 1394 OHCI function (default).

1 = PME input signal to the bridge is disabled.

0 = OHCI_PME pin is enabled and connected to the PME signal from the 1394

OHCI function (default).

1 = OHCI_PME pin is disabled.

to configuration accesses to any function number.

credits.

credits immediately.

0 = Bridge shall use side-band signals to determine the transaction size (default). 1 = Bridge shall use the cache line size register to determine the transaction size.

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(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted. (2) These bits are reset only by a global reset (GRST) or the internally generated power-on reset.

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Table 4-36. Control and Diagnostic Register 0 Description (continued)

BIT FIELD NAME ACCESS DESCRIPTION

(1)

PREFETCH_4X RW Prefetch 4× enable

0 = Bridge prefetches up to two cache lines, as defined in the cache line size

1 = Bridge prefetches up to four cache lines, as defined in the cache line size

Note: When this bit is set and the FORCE_MRM bit in the general control register is set, both upstream memory read multiple transactions and upstream memory transactions prefetch up to four cache lines. Note: When the READ_PREFETCH_DIS bit in the general control register is set, this bit has no effect and only one DWORD will be fetched on a burst read. This bit only affects the XIO2213B design when the EN_CACHE_LINE_CHECK bit is set.

(1)

5:4

UP_REQ_BUF_VALUE RW PCI upstream req-res buffer threshold value. The value in this field controls the buffer

space that must be available for the device to accept a PCI bus transaction. If the cache line size is not valid, the device will use eight DW for calculating the threshold value.

00 = 1 cache line + 4 DW (default) 01 = 1 cache line + 8 DW 10 = 1 cache line + 12 DW 11 = 2 cache lines + 4 DW

(1)

UP_REQ_BUF_CTRL RW PCI upstream req-res buffer threshold control. This bit enables the PCI upstream req-

res buffer threshold control mode of the bridge.

0 = PCI upstream req-res buffer threshold control mode disabled (default) 1 = PCI upstream req-res buffer threshold control mode enabled

(1)

CFG_ACCESS_MEM_ RW Configuration access to memory-mapped registers. When this bit is set, the bridge REG allows configuration access to memory-mapped configuration registers.

(1)

RSVD RW Reserved. Bit 1 defaults to 0b. If this register is programmed via EEPROM or another

mechanism, the value written into this field must be 0b.

0 RSVD R Reserved. Returns 0b when read.

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4.63 Control and Diagnostic Register 1

The contents of this register are used for monitoring status and controlling behavior of the bridge. See

Table 4-37 for a complete description of the register contents. It is recommended that all values within this

register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.

PCI register offset: C4h Register type: Read/Write Default value: 0012 0108h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0

Table 4-37. Control and Diagnostic Register 1 Description

BIT FIELD NAME ACCESS DESCRIPTION

32:21 RSVD R Reserved. Returns 000h when read.

(1)

20:18

17:15

14:11

9:6

5:2

1:0

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

L1_EXIT_LAT_ RW L1 exit latency for asynchronous clock. When bit 6 (CCC) of the link control register (offset ASYNC A0h, see Section 4.54) is set, the value in this field is mirrored in bits 17:15 (L1_LATENCY)

(1)

L1_EXIT_LAT_ RW L1 exit latency for common clock. When bit 6 (CCC) of the link control register (offset A0h, see COMMON Section 4.54) is clear, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the

(1)

RSVD RW Reserved. Bits 14:11 default to 0000b. If this register is programmed via EEPROM or another

(1)

SBUS_RESET_ RW Secondary bus reset bit mask. When this bit is set, the bridge masks the reset caused by bit 6 MASK (SRST) of the bridge control register (offset 3Eh, see Section 4.30). This bit defaults to 0b.

(1)

L1ASPM_TIMER RW L1ASPM entry timer. This field specifies the value (in 512-ns ticks) of the L1ASPM entry timer.

(1)

L0s_TIMER RW L0s entry timer. This field specifies the value (in 62.5-MHz clock ticks) of the L0s entry timer.

(1)

RSVD RW Reserved. Bits 1:0 default to 00b. If this register is programmed via EEPROM or another

field in the link capabilities register (offset 9Ch, see Section 4.53). This field defaults to 100b.

link capabilities register (offset 9Ch, see Section 4.53). This field defaults to 100b.

mechanism, the value written into this field must be 0000b.

This field defaults to 0100b.

This field defaults to 0010b.

mechanism, the value written into this field must be 00b.

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4.64 PHY Control and Diagnostic Register 2

The contents of this register are used for monitoring status and controlling behavior of the PHY macro for diagnostic purposes. See Table 4-38 for a complete description of the register contents. It is recommended that all values within this register be left at the default value. Improperly programming fields in this register may cause interoperability or other problems.

PCI register offset: C8h Register type: Read/Write Default value: 3214 2000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-38. Control and Diagnostic Register 2 Description

BIT FIELD NAME ACCESS DESCRIPTION

(1)

31:24

23:16

15:13 PHY_REV R PHY revision number

12:8

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

N_FTS_ ASYNC_ RW N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h, CLK see Section 4.54) is clear, the value in this field is the number of FTS that are sent on a

(1)

N_FTS_COMMON_ RW N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see CLK Section 4.54) is set, the value in this field is the number of FTS that are sent on a transition

(1)

LINK_NUM RW Link number

7 EN_L2_PWR_ RW Enable L2 power savings

SAVE

6 BAR1_EN RW BAR 1 enable

5 BAR0_EN RW BAR 0 enable

4 REQ_RECOVERY RW REQ_RECOVERY to LTSSM 3 REQ_RECONFIG RW REQ_RECONFIGURE to LTSSM 2 REQ_HOT_RESET RW REQ_HOT_RESET to LTSSM 1 REQ_DIS_ RW REQ_DISABLE_SCRAMBLER to LTSSM

SCRAMBLER

0 REQ_LOOPBACK RW REQ_LOOPBACK to LTSSM

transition from L0s to L0. This field shall default to 32h.

from L0s to L0. This field defaults to 14h.

0 = Power savings not enabled when in L2 1 = Power savings enabled when in L2

0 = BAR at offset 14h is disabled (default). 1 = BAR at offset 14h is enabled.

0 = BAR at offset 10h is disabled (default). 1 = BAR at offset 10h is enabled.

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4.65 Subsystem Access Register

The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 84h and 86h. See Table 4-39 for a complete description of the register contents.

PCI register offset: D0h Register type: Read/Write Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-39. Subsystem Access Register Description

BIT FIELD NAME ACCESS DESCRIPTION

(1)

31:16

15:0

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

SubsystemID RW Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI

(1)

SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID

offset 86h (see Section 4.46).

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4.66 General Control Register

This read/write register controls various functions of the bridge. See Table 4-40 for a complete description of the register contents.

PCI register offset: D4h Register type: Read only, Read/Write Default value: 8600 025Fh

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1

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Table 4-40. General Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

(1)

31:30

29:28

22:20

CFG_RETRY_ RW Configuration retry counter. Configures the amount of time that a configuration request must be CNTR retried on the secondary PCI bus before it may be completed with configuration retry status on

the PCIe side.

00 = 25 s 01 = 1 ms 10 = 25 ms (default) 11 = 50 ms

(1)

ASPM_CTRL_ RW Active-state power-management control default override. These bits are used to determine the DEF_OVRD power up default for bits 1:0 of the link control register in the PCIe capability structure.

00 = Power-on default indicates that the active-state power management is disabled (00b) 01 = (default). 10 = Power-on default indicates that the active-state power management is enabled for 11 = L0s (01b).

Power-on default indicates that the active-state power management is enabled for L1s (10b). Power-on default indicates that the active-state power management is enabled for L0s and L1s (11b).

(2)

LOW_POWER _ RW Low-power enable. When this bit is set, the half-ampitude, no preemphasis mode for the PCIe TX EN drivers is enabled. The default for this bit is 0b.

(1)

PCI_PM_ RW PCI power management version control. This bit controls the value reported in bits 2:0 VERSION_ CTRL (PM_VERSION) in the power management capabilities register (offset 52h, see Section 4.33). It

also controls the value of bit 3 (NO_SOFT_RESET) in the power management control/status register (offset 54h, see Section 4.34).

0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power

Management 1.1 compliance.

1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power

Management 1.2 compliance (default).

(1)

STRICT_ RW Strict priority enable. When this bit is 0, the default LOW_PRIORITY_COUNT will be 001. When PRIORITY_EN this bit is 1, the default LOW_PRIORITY_COUNT will be 000. This default value for this bit is 1.

When this bit is set and the LOW_PRIORITY_COUNT is 000, meaning that strict priority VC arbitration is used and the extended virtual channel always receives priority over VC0 at the PCIe port.

0 = Default LOW_PRIORITY_COUNT is 001b. 1 = Default LOW_PRIORITY_COUNT is 000b (default).

(1)

FORCE_MRM RW Force memory read multiple

0 = Memory read multiple transactions are disabled (default). 1 = All upstream memory read transactions initiated on the PCI bus are treated as though

they are memory read multiple transactions in which prefetching is supported for the transaction. This bit shall only affect the XIO2213B design when the EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is set.

(1)

CPM_EN_ RW Clock power-management enable default override. This bit is used to determine the power up DEF_OVRD default for bit 8 of the link control register in the PCIe capability structure.

0 = Power-on default indicates that clock power management is disabled (00b) (default). 1 = Power-on default indicates that clock power management is enabled for L0s and L1

(11b).

(1)

POWER_ OVRD RW Power override. This bit field determines how the bridge responds when the slot power limit is

less than the amount of power required by the bridge and the devices behind the bridge. This field shall be hardwired to 000b since XIO2213B does not support slot power limit functionality.

000 = Ignore slot power limit (default) 001 = Assert the PWR_OVRD terminal 010 = Disable secondary clocks selected by the clock mask register 011 = Disable secondary clocks selected by the clock mask register and assert the

PWR_OVRD terminal

100 = Respond with unsupported request to all transactions except for configuration

transactions (type 0 or type 1) and set slot power limit messages

101, 110, 111 = Reserved

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Table 4-40. General Control Register Description (continued)

BIT FIELD NAME ACCESS DESCRIPTION

(1)

18:16

15:13

9:8

7:0

(3) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted. (4) These bits are reset only by a global reset (GRST) or the internally generated power-on reset.

READ_ RW Read prefetch disable. This bit controls the prefetch functionality on PCI memory read PREFETCH_ DIS transactions.

0 = Prefetch to the next cache line boundary on a burst read (default) 1 = Fetch only a single DWORD on a burst read

Note: When this bit is set, the PREFETCH_4X bit in the TL control and diagnostic register shall have no effect on the design. This bit shall only affect the XIO2213B when the EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is set.

(1)

L0s_LATENCY RW L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the

L0s state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 94h, see

Section 4.50).

000 = Less than 64 ns (default) 001 = 64 ns up to less than 128 ns 010 = 128 ns up to less than 256 ns 011 = 256 ns up to less than 512 ns 100 = 512 ns up to less than 1 s 101 = 1 s up to less than 2 s 110 = 2 s to 4 s 111 = More than 4 s

(3)

L1_LATENCY RW L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the

L1 state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 94h, see

Section 4.50).

000 = Less than 1 s (default) 001 = 1 s up to less than 2 s 010 = 2 s up to less than 4 s 011 = 4 s up to less than 8 s 100 = 8 s up to less than 16 s 101 = 6 s up to less than 32 s 110 = 32 s to 64 s 111 = More than 64 s

(3)

VC_CAP_EN R VC capability structure enable. This bit enables the VC capability structure by changing the next

offset field of the advanced error reporting capability register at offset 102h. This bit is a read only 0b indicating that the VC capability structure is permanently disabled.

0 = VC capability structure disabled (offset field = 000h) 1 = VC capability structure enabled (offset field = 150h)

(3)

BPCC_E RW Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are

stopped when the XIO2213B is placed in the D3 state. It is assumed that if the secondary bus clocks are required to be active that a reference clock continues to be provided on the PCIe interface.

0 = Secondary bus clocks are not stopped in D3 (default). 1 = Secondary bus clocks are stopped on D3.

(4)

BEACON_ RW Beacon enable. This bit controls the mechanism for waking up the physical PCIe link when in L2. ENABLE

0 = WAKE mechanism is used exclusively. Beacon is not used (default). 1 = Beacon and WAKE mechanisms are used.

(3)

MIN_POWER_ RW Minimum power scale. This value is programmed to indicate the scale of bits 7:0 SCALE (MIN_POWER_VALUE).

00 = 1.0x 01 = 0.1x 10 = 0.01x (default) 11 = 0.001x

(3)

MIN_POWER_ RW Minimum power value. This value is programmed to indicate the minimum power requirements. VALUE This value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum

power requirements for the bridge. The default is 5Fh, indicating that XIO2213B requires 0.95 W of power. This field can be reprogrammed through an EEPROM or the system BIOS.

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4.67 TI Proprietary Register

This read/write TI proprietary register is located at offset D8h and controls TI proprietary functions. This register must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset: D8h Register type: Read only, Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.68 TI Proprietary Register

This read/write TI proprietary register is located at offset D9h and controls TI proprietary functions. This register must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset: D9h Register type: Read only, Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

SCPS210F –OCTOBER 2008–REVISED MAY 2013

4.69 TI Proprietary Register

This read-only TI proprietary register is located at offset DAh and controls TI proprietary functions. This register must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset: DAh Register type: Read only Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

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4.70 Arbiter Control Register

The arbiter control register controls the device's internal arbiter. The arbitration scheme used is a twotier rotational arbitration. The device is the only secondary bus master that defaults to the higherpriority arbitration tier. See Table 4-41 for a complete description of the register contents.

PCI register offset: DCh Register type: Read/Write Default value: 40h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 0 0 0 0 0

Table 4-41. Arbiter Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

(1)

PARK RW Bus parking mode. This bit determines where the internal arbiter parks the secondary bus.

(1)

BRIDGE_TIER_SEL RW Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration

(1)

5:1

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

RSVD RW Reserved. These bits are reserved and must not be changed from their default value of

(1)

TIER_SEL0 RW GNT0 tier select. This bit determines in which tier GNT0 is placed in the arbitration

When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is cleared, the arbiter parks the bus on the last device mastering the secondary bus.

0 = Park the secondary bus on the last secondary bus master (default) 1 = Park the secondary bus on the bridge

scheme.

0 = Lowest-priority tier 1 = Highest-priority tier (default)

00000b.

scheme.

0 = Lowest-priority tier (default) 1 = Highest-priority tier

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4.71 Arbiter Request Mask Register

The arbiter request mask register enables and disables support for requests from specific masters on the secondary bus. The arbiter request mask register also controls if a request input is automatically masked on an arbiter time-out. See Table 4-42 for a complete description of the register contents.

PCI register offset: DDh Register type: Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

Table 4-42. Arbiter Request Mask Register Description

BIT FIELD NAME ACCESS DESCRIPTION

(1)

ARB_TIMEOUT RW Arbiter time-out. This bit enables the arbiter time-out feature. The arbiter time-out is

(1)

AUTO_MASK RW Automatic request mask. This bit enables automatic request masking when an arbiter

(1)

5:1

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

RSVD RW Reserved. These bits are reserved and must not be changed from their default value of

(1)

REQ0_MASK RW Request 0 (REQ0) mask. Setting this bit forces the internal arbiter to ignore requests

defined as the number of PCI clocks after the PCI bus has gone idle for a device to assert FRAME before the arbiter assumes the device will not respond.

0 = Arbiter time disabled (default) 1 = Arbiter time-out set to 16 PCI clocks

time-out occurs. 0 = Automatic request masking disabled (default)

1 = Automatic request masking enabled

00000b.

signal on request input 0. 0 = Use 1394a OHCI request (default)

1 = Ignore 1394a OHCI request

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4.72 Arbiter Time-Out Status Register

The arbiter time-out status register contains the status of each request (request 50) time-out. The time-out status bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value. See Table 4-43 for a complete description of the register contents.

PCI register offset: DEh Register type: Read/Clear Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

Table 4-43. Arbiter Time-Out Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

7:6 RSVD R Reserved. Returns 00b when read.

5 REQ5_TO RCU Request 5 time-out status

0 = No time-out 1 = Time-out has occurred.

4 REQ4_TO RCU Request 4 time-out status

0 = No time-out 1 = Time-out has occurred.

3 REQ3_TO RCU Request 3 time-out status

0 = No time-out 1 = Time-out has occurred.

2 REQ2_TO RCU Request 2 time-out status

0 = No time-out 1 = Time-out has occurred.

1 REQ1_TO RCU Request 1time-out status

0 = No time-out 1 = Time-out has occurred.

0 REQ0_TO RCU Request 0 time-out status

0 = No time-out 1 = Time-out has occurred.

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4.73 TI Proprietary Register

This read/write TI proprietary register is located at offset E0h and controls TI proprietary functions. This register must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset: E0h Register type: Read only, Read/Write Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.74 TI Proprietary Register

This read/write TI proprietary register is located at offset E2h and controls TI proprietary functions. This register must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset: E2h Register type: Read/Write Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.75 TI Proprietary Register

This read/clear TI proprietary register is located at offset E4h and controls TI proprietary functions. This register must not be changed from the specified default state.

PCI register offset: E4h Register type: Read/Clear Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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5 PCIe Extended Configuration Space

The programming model of the PCIe extended configuration space is compliant to the PCI Express Base Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCIe extended configuration map uses the PCIe advanced error reporting capability and PCIe virtual channel (VC) capability headers.

Table 5-1. PCIe Extended Configuration Register Map

Next capability offset/capability version Advanced error reporting capabilities ID 100h

Uncorrectable error status register

Uncorrectable error mask

Uncorrectable error severity

Correctable error status

Correctable error mask

Advanced error capabilities and control

Header log Header log Header log Header log

Secondary uncorrectable error status

Secondary uncorrectable error mask

Secondary uncorrectable error severity

Secondary error capabilities and control

Secondary header log Secondary header log Secondary header log Secondary header log

Reserved 14Ch FFCh

(1) This register shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

(1) (1) (1) (1)

(1)

(1) (1) (1) (1) (1)

104h 108h

10Ch

110h 114h 118h

11Ch

120h 124h 128h

12Ch

130h 134h 138h

13Ch

140h 144h 148h

5.1 Advanced Error Reporting Capability ID Register

This read-only register identifies the linked list item as the register for PCIe advanced error reporting capabilities. The register returns 0001h when read.

PCIe extended register 100h offset:

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

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5.2 Next Capability Offset/Capability Version Register

This read-only register identifies the next location in the PCIe extended capabilities link list. The upper 12 bits in this register shall be 000h, indicating that the advanced error reporting capability is the last capability in the linked list. The least significant four bits identify the revision of the current capability block as 1h.

PCIe extended register 102h offset:

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

5.3 Uncorrectable Error Status Register

The uncorrectable error status register reports the status of individual errors as they occur on the primary PCIe interface. Software may only clear these bits by writing a 1b to the desired location. See Table 5-2 for a complete description of the register contents.

PCIe extended register 104h offset:

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 5-2. Uncorrectable Error Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:21 RSVD R Reserved. Returns 000 0000 0000b when read.

(1)

19 18 17

15 14

12 11:5 RSVD R Reserved. Returns 000 0000b when read.

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

UR_ERROR RCU Unsupported request error. This bit is asserted when an unsupported request is received.

(1)

ECRC_ERROR RCU Extended CRC error. This bit is asserted when an extended CRC error is detected.

(1)

MAL_TLP RCU Malformed TLP. This bit is asserted when a malformed TLP is detected.

(1)

RX_OVERFLOW RCU Receiver overflow. This bit is asserted when the flow control logic detects that the

(1)

UNXP_CPL RCU Unexpected completion. This bit is asserted when a completion packet is received that

(1)

CPL_ABORT RCU Completed abort. This bit is asserted when the bridge signals a completed abort.

(1)

CPL_TIMEOUT RCU Completion time-out. This bit is asserted when no completion has been received for an

(1)

FC_ERROR RCU Flow control error. This bit is asserted when a flow control protocol error is detected either

(1)

PSN_TLP RCU Poisoned TLP. This bit is asserted when a poisoned TLP is received.

(1)

DLL_ERROR RCU Data link protocol error. This bit is asserted if a data link layer protocol error is detected.

3:0 RSVD R Reserved. Returns 0h when read.

transmitting device has illegally exceeded the number of credits that were issued.

does not correspond to an issued request.

issued request before the time-out period.

during initialization or during normal operation.

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5.4 Uncorrectable Error Mask Register

The uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5-3 for a complete description of the register contents.

PCIe extended register offset: 108h Register type: Read only, Read/Write Default value: 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 5-3. Uncorrectable Error Mask Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:21 RSVD R Reserved. Returns 000 0000 0000b when read.

(1)

11:5 RSVD R Reserved. Returns 000 0000b when read.

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

UR_ERROR_MASK RW Unsupported request error mask

0 = Error condition is unmasked (default).. 1 = Error condition is masked.

(1)

ECRC_ERROR_MASK RW Extended CRC error mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

(1)

MAL_TLP_MASK RW Malformed TLP mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

(1)

RX_OVERFLOW_MASK RW Receiver overflow mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

(1)

UNXP_CPL_MASK RW Unexpected completion mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

(1)

CPL_ABORT_MASK RW Completer abort mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

(1)

CPL_TIMEOUT_MASK RW Completion time-out mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

(1)

FC_ERROR_MASK RW Flow control error mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

(1)

PSN_TLP_MASK RW Poisoned TLP mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

(1)

DLL_ERROR_MASK RW Data link protocol error mask

0 = Error condition is unmasked (default). 1 = Error condition is masked.

3:0 RSVD R Reserved. Returns 0h when read.

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5.5 Uncorrectable Error Severity Register

The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5-4 for a complete description of the register contents.

PCIe extended register offset: 10Ch Register type: Read only, Read/Write Default value: 0006 2011h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1

Table 5-4. Uncorrectable Error Severity Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:21 RSVD R Reserved. Returns 000 0000 0000b when read.

(1)

UR_ERROR_SEVRO RW Unsupported request error severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

(1)

ECRC_ERROR_SEVRR RW Extended CRC error severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

(1)

MAL_TLP_SEVR RW Malformed TLP severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

(1)

RX_OVERFLOW_SEVR RW Receiver overflow severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

(1)

UNXP_CPL_SEVRP RW Unexpected completion severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

(1)

CPL_ABORT_SEVR RW Completed abort severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

(1)

CPL_TIMEOUT_SEVR RW Completion time-out severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

(1)

FC_ERROR_SEVR RW Flow control error severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

(1)

PSN_TLP_SEVR RW Poisoned TLP severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

11:6 RSVD R Reserved. Returns 000 000b when read.

5 RSVD R Reserved. Returns 1h when read.

(1)

DLL_ERROR_SEVR RW Data link protocol error severity

0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL.

3:1 RSVD R Reserved. Returns 000b when read.

(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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Table 5-4. Uncorrectable Error Severity Register Description (continued)

BIT FIELD NAME ACCESS DESCRIPTION

0 RSVD R Reserved. Returns 1h when read.

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arTech PEX1394B3 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 XIO2213B Features

2 Overview

2.1 Related Documents

2.2 Documents Conventions

2.3 Ordering Information

2.4 Terminal Assignments

2.5 Terminal Descriptions

3 Feature/Protocol Descriptions

3.1 Power-Up/Power-Down Sequencing

3.1.1 Power-Up Sequence

3.1.2 Power-Down Sequence

3.2 XIO2213B Reset Features

3.3 PCI Express (PCIe) Interface

3.3.1 External Reference Clock

3.3.2 Beacon and Wake

3.3.3 Initial Flow Control Credits

3.3.4 PCIe Message Transactions

3.4 PCI Interrupt Conversion to PCIe Messages

3.5 Two-Wire Serial-Bus Interface

3.5.1 Serial-Bus Interface Implementation

3.5.2 Serial-Bus Interface Protocol

3.5.3 Serial-Bus EEPROM Application

3.5.4 Accessing Serial-Bus Devices Through Softwaree

3.6 Advanced Error Reporting Registers

3.7 Data Error Forwarding Capability

3.8 General-Purpose I/O (GPIO) Interface

3.9 Set Slot Power Limit Functionality

3.10 PCIe and PCI Bus Power Management

3.11 1394b OHCI Controller Functionality

3.11.1 1394b OHCI Power Management

3.11.3 1394b OHCI and Reset Options

3.11.4 1394b OHCI PCI Bus Master

3.11.5 1394b OHCI Subsystem Identification

3.11.6 1394b OHCI PME Support

4 Classic PCI Configuration Space

4.1 Vendor ID Register

4.2 Device ID Register

4.3 Command Register

4.4 Status Register

4.5 Class Code and Revision ID Register

4.6 Cache Line Size Register

4.7 Primary Latency Timer Register

4.8 Header Type Register

4.9 BIST Register

4.10 Device Control Base Address Register

4.11 Scratchpad RAM Base Address

4.12 Primary Bus Number Register

4.13 Secondary Bus Number Register

4.14 Subordinate Bus Number Register

4.15 Secondary Latency Timer Register

4.16 I/O Base Register

4.17 I/O Limit Register

4.18 Secondary Status Register

4.19 Memory Base Register

4.20 Memory Limit Register

4.21 Prefetchable Memory Base Register

4.22 Prefetchable Memory Limit Register

4.23 Prefetchable Base Upper 32 Bits Register

4.24 Prefetchable Limit Upper 32 Bits Register

4.25 I/O Base Upper 16 Bits Register

4.26 I/O Limit Upper 16 Bits Register

4.27 Capabilities Pointer Register

4.28 Interrupt Line Register

4.29 Interrupt Pin Register

4.30 Bridge Control Register

4.31 PM Capability ID Register

4.32 Next Item Pointer Register

4.33 Power Management Capabilities Register

4.34 Power Management Control/Status Register

4.35 Power Management Bridge Support Extension Register

4.36 Power Management Data Register

4.37 MSI Capability ID Register

4.38 Next Item Pointer Register

4.39 MSI Message Control Register

4.40 MSI Message Lower Address Register