arTech PEX1394B3 Service Manual

XIO2213B

XIO2213B PCI Express™ TO 1394b OHCI WITH 3-PORT PHY

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SCPS210F

October 2008–Revised May 2013

XIO2213B

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

Contents

1 Introduction ...................................................................................................................... 12

1.1 XIO2213B Features ....................................................................................................... 12

2 Overview .......................................................................................................................... 13

2.1 Related Documents ....................................................................................................... 14

2.2 Documents Conventions ................................................................................................. 15

2.3 Ordering Information ...................................................................................................... 15

2.4 Terminal Assignments .................................................................................................... 16

2.5 Terminal Descriptions ..................................................................................................... 24

3 Feature/Protocol Descriptions ............................................................................................. 31

3.1 Power-Up/Power-Down Sequencing .................................................................................... 31

3.1.1 Power-Up Sequence ........................................................................................... 32

3.1.2 Power-Down Sequence ........................................................................................ 33

3.2 XIO2213B Reset Features ............................................................................................... 34

3.3 PCI Express (PCIe) Interface ............................................................................................ 35

3.3.1 External Reference Clock ..................................................................................... 35

3.3.2 Beacon and Wake .............................................................................................. 35

3.3.3 Initial Flow Control Credits .................................................................................... 35

3.3.4 PCIe Message Transactions .................................................................................. 36

3.4 PCI Interrupt Conversion to PCIe Messages .......................................................................... 37

3.5 Two-Wire Serial-Bus Interface ........................................................................................... 38

3.5.1 Serial-Bus Interface Implementation ......................................................................... 38

3.5.2 Serial-Bus Interface Protocol .................................................................................. 39

3.5.3 Serial-Bus EEPROM Application ............................................................................. 41

3.5.4 Accessing Serial-Bus Devices Through Softwaree ........................................................ 43

3.6 Advanced Error Reporting Registers ................................................................................... 43

3.7 Data Error Forwarding Capability ....................................................................................... 43

3.8 General-Purpose I/O (GPIO) Interface ................................................................................. 44

3.9 Set Slot Power Limit Functionality ...................................................................................... 44

3.10 PCIe and PCI Bus Power Management ................................................................................ 44

3.11 1394b OHCI Controller Functionality ................................................................................... 46

3.11.1 1394b OHCI Power Management ............................................................................ 46

3.11.2 1394b OHCI and V

3.11.3 1394b OHCI and Reset Options .............................................................................. 46

3.11.4 1394b OHCI PCI Bus Master ................................................................................. 46

3.11.5 1394b OHCI Subsystem Identification ....................................................................... 47

3.11.6 1394b OHCI PME Support .................................................................................... 47

4 Classic PCI Configuration Space ......................................................................................... 48

4.1 Vendor ID Register ........................................................................................................ 49

4.2 Device ID Register ........................................................................................................ 49

4.3 Command Register ........................................................................................................ 49

4.4 Status Register ............................................................................................................ 51

4.5 Class Code and Revision ID Register .................................................................................. 52

4.6 Cache Line Size Register ................................................................................................ 52

4.7 Primary Latency Timer Register ......................................................................................... 52

4.8 Header Type Register .................................................................................................... 53

4.9 BIST Register .............................................................................................................. 53

4.10 Device Control Base Address Register ................................................................................. 53

4.11 Scratchpad RAM Base Address ......................................................................................... 54

4.12 Primary Bus Number Register ........................................................................................... 54

4.13 Secondary Bus Number Register ....................................................................................... 54

4.14 Subordinate Bus Number Register ...................................................................................... 55

........................................................................................ 46

AUX

XIO2213B

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4.15 Secondary Latency Timer Register ..................................................................................... 55

4.16 I/O Base Register ......................................................................................................... 55

4.17 I/O Limit Register .......................................................................................................... 56

4.18 Secondary Status Register ............................................................................................... 57

4.19 Memory Base Register ................................................................................................... 58

4.20 Memory Limit Register .................................................................................................... 58

4.21 Prefetchable Memory Base Register ................................................................................... 59

4.22 Prefetchable Memory Limit Register .................................................................................... 59

4.23 Prefetchable Base Upper 32 Bits Register ............................................................................. 60

4.24 Prefetchable Limit Upper 32 Bits Register ............................................................................. 60

4.25 I/O Base Upper 16 Bits Register ........................................................................................ 61

4.26 I/O Limit Upper 16 Bits Register ......................................................................................... 61

4.27 Capabilities Pointer Register ............................................................................................. 62

4.28 Interrupt Line Register .................................................................................................... 62

4.29 Interrupt Pin Register ..................................................................................................... 62

4.30 Bridge Control Register ................................................................................................... 63

4.31 PM Capability ID Register ................................................................................................ 65

4.32 Next Item Pointer Register ............................................................................................... 65

4.33 Power Management Capabilities Register ............................................................................. 66

4.34 Power Management Control/Status Register .......................................................................... 67

4.35 Power Management Bridge Support Extension Register ............................................................ 68

4.36 Power Management Data Register ..................................................................................... 68

4.37 MSI Capability ID Register ............................................................................................... 68

4.38 Next Item Pointer Register ............................................................................................... 69

4.39 MSI Message Control Register .......................................................................................... 69

4.40 MSI Message Lower Address Register ................................................................................. 70

4.41 MSI Message Upper Address Register ................................................................................. 70

4.42 MSI Message Data Register ............................................................................................. 71

4.43 SSID/SSVID Capability ID Register ..................................................................................... 71

4.44 Next Item Pointer Register ............................................................................................... 71

4.45 Subsystem Vendor ID Register .......................................................................................... 72

4.46 Subsystem ID Register ................................................................................................... 72

4.47 PCI Express Capability ID Register ..................................................................................... 72

4.48 Next Item Pointer Register ............................................................................................... 72

4.49 PCI Express Capabilities Register ...................................................................................... 73

4.50 Device Capabilities Register ............................................................................................. 74

4.51 Device Control Register .................................................................................................. 75

4.52 Device Status Register ................................................................................................... 76

4.53 Link Capabilities Register ................................................................................................ 77

4.54 Link Control Register ...................................................................................................... 78

4.55 Link Status Register ....................................................................................................... 79

4.56 Serial-Bus Data Register ................................................................................................. 79

4.57 Serial-Bus Word Address Register ...................................................................................... 79

4.58 Serial-Bus Slave Address Register ..................................................................................... 80

4.59 Serial-Bus Control and Status Register ................................................................................ 81

4.60 GPIO Control Register .................................................................................................... 82

4.61 GPIO Data Register ....................................................................................................... 83

4.62 Control and Diagnostic Register 0 ...................................................................................... 84

4.63 Control and Diagnostic Register 1 ...................................................................................... 86

4.64 PHY Control and Diagnostic Register 2 ................................................................................ 87

4.65 Subsystem Access Register ............................................................................................. 88

4.66 General Control Register ................................................................................................. 88

4.67 TI Proprietary Register .................................................................................................... 91

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

4.68 TI Proprietary Register .................................................................................................... 91

4.69 TI Proprietary Register .................................................................................................... 91

4.70 Arbiter Control Register ................................................................................................... 92

4.71 Arbiter Request Mask Register .......................................................................................... 93

4.72 Arbiter Time-Out Status Register ........................................................................................ 94

4.73 TI Proprietary Register .................................................................................................... 95

4.74 TI Proprietary Register .................................................................................................... 95

4.75 TI Proprietary Register .................................................................................................... 95

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5 PCIe Extended Configuration Space .................................................................................... 96

5.1 Advanced Error Reporting Capability ID Register ..................................................................... 96

5.2 Next Capability Offset/Capability Version Register ................................................................... 97

5.3 Uncorrectable Error Status Register .................................................................................... 97

5.4 Uncorrectable Error Mask Register ..................................................................................... 98

5.5 Uncorrectable Error Severity Register .................................................................................. 99

5.6 Correctable Error Status Register ..................................................................................... 101

5.7 Correctable Error Mask Register ....................................................................................... 102

5.8 Advanced Error Capabilities and Control Register .................................................................. 103

5.9 Header Log Register .................................................................................................... 103

5.10 Secondary Uncorrectable Error Status Register ..................................................................... 104

5.11 Secondary Uncorrectable Error Mask Register ...................................................................... 105

5.12 Secondary Uncorrectable Error Severity .............................................................................. 106

5.13 Secondary Error Capabilities and Control Register ................................................................. 107

5.14 Secondary Header Log Register ....................................................................................... 108

6 Memory-Mapped TI Proprietary Register Space ................................................................... 109

6.1 Device Control Map ID Register ....................................................................................... 109

6.2 Revision ID Register ..................................................................................................... 110

6.3 GPIO Control Register .................................................................................................. 110

6.4 GPIO Data Register ..................................................................................................... 111

6.5 Serial-Bus Data Register ................................................................................................ 112

6.6 Serial-Bus Word Address Register .................................................................................... 112

6.7 Serial-Bus Slave Address Register .................................................................................... 112

6.8 Serial-Bus Control and Status Register ............................................................................... 113

7 1394 OHCI PCI Configuration Space ................................................................................... 114

7.1 Vendor ID Register ...................................................................................................... 115

7.2 Device ID Register ....................................................................................................... 115

7.3 Command Register ...................................................................................................... 116

7.4 Status Register ........................................................................................................... 117

7.5 Class Code and Revision ID Registers ............................................................................... 118

7.6 Cache Line Size and Latency Timer Registers ...................................................................... 118

7.7 Header Type and BIST Registers ..................................................................................... 119

7.8 OHCI Base Address Register .......................................................................................... 119

7.9 TI Extension Base Address Register .................................................................................. 120

7.10 CIS Base Address Register ............................................................................................ 120

7.11 CIS Pointer Register ..................................................................................................... 121

7.12 Subsystem Vendor ID and Subsystem ID Registers ................................................................ 121

7.13 Power Management Capabilities Pointer Register .................................................................. 122

7.14 Interrupt Line and Interrupt Pin Registers ............................................................................ 122

7.15 Minimum Grant and Minimum Latency Registers ................................................................... 123

7.16 OHCI Control Register .................................................................................................. 123

7.17 Capability ID and Next Item Pointer Registers ....................................................................... 124

7.18 Power Management Capabilities Register ............................................................................ 124

7.19 Power Management Control and Status Register ................................................................... 125

7.20 Power Management Extension Registers ............................................................................ 125

XIO2213B

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7.21 PCI Miscellaneous Configuration Register ........................................................................... 125

7.22 Link Enhancement Control Register ................................................................................... 128

7.23 Subsystem Access Register ............................................................................................ 130

SCPS210F –OCTOBER 2008–REVISED MAY 2013

8 1394 OHCI Memory-Mapped Register Space ....................................................................... 131

8.1 OHCI Version Register .................................................................................................. 134

8.2 GUID ROM Register ..................................................................................................... 135

8.3 Asynchronous Transmit Retries Register ............................................................................. 136

8.4 CSR Data Register ...................................................................................................... 136

8.5 CSR Compare Register ................................................................................................. 137

8.6 CSR Control Register ................................................................................................... 137

8.7 Configuration ROM Header Register .................................................................................. 138

8.8 Bus Identification Register .............................................................................................. 138

8.9 Bus Options Register .................................................................................................... 139

8.10 GUID High Register ..................................................................................................... 140

8.11 GUID Low Register ...................................................................................................... 140

8.12 Configuration ROM Mapping Register ................................................................................ 141

8.13 Posted Write Address Low Register ................................................................................... 141

8.14 Posted Write Address High Register .................................................................................. 142

8.15 Vendor ID Register ...................................................................................................... 142

8.16 Host Controller Control Register ....................................................................................... 142

8.17 Self-ID Buffer Pointer Register ......................................................................................... 145

8.18 Self-ID Count Register .................................................................................................. 145

8.19 Isochronous Receive Channel Mask High Register ................................................................. 146

8.20 Isochronous Receive Channel Mask Low Register ................................................................. 148

8.21 Interrupt Event Register ................................................................................................. 148

8.22 Interrupt Mask Register ................................................................................................. 150

8.23 Isochronous Transmit Interrupt Event Register ...................................................................... 152

8.24 Isochronous Transmit Interrupt Mask Register ...................................................................... 153

8.25 Isochronous Receive Interrupt Event Register ....................................................................... 153

8.26 Isochronous Receive Interrupt Mask Register ....................................................................... 154

8.27 Initial Bandwidth Available Register ................................................................................... 154

8.28 Initial Channels Available High Register .............................................................................. 155

8.29 Initial Channels Available Low Register .............................................................................. 155

8.30 Fairness Control Register ............................................................................................... 156

8.31 Link Control Register .................................................................................................... 157

8.32 Node Identification Register ............................................................................................ 158

8.33 PHY Control Register ................................................................................................... 159

8.34 Isochronous Cycle Timer Register ..................................................................................... 160

8.35 Asynchronous Request Filter High Register ......................................................................... 160

8.36 Asynchronous Request Filter Low Register .......................................................................... 163

8.37 Physical Request Filter High Register ................................................................................ 163

8.38 Physical Request Filter Low Register ................................................................................. 166

8.39 Physical Upper Bound Register (Optional Register) ................................................................ 166

8.40 Asynchronous Context Control Register .............................................................................. 167

8.41 Asynchronous Context Command Pointer Register ................................................................. 168

8.42 Isochronous Transmit Context Control Register ..................................................................... 169

8.43 Isochronous Transmit Context Command Pointer Register ........................................................ 170

8.44 Isochronous Receive Context Control Register ...................................................................... 170

8.45 Isochronous Receive Context Command Pointer Register ......................................................... 172

8.46 Isochronous Receive Context Match Register ....................................................................... 172

9 1394 OHCI Memory-Mapped TI Extension Register Space ..................................................... 174

9.1 Digital Video (DV) and MPEG2 Timestamp Enhancements ....................................................... 174

9.2 Isochronous Receive Digital Video Enhancements ................................................................. 175

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

9.3 Isochronous Receive Digital Video Enhancement Registers ...................................................... 175

9.4 Link Enhancement Control Registers ................................................................................. 176

9.5 Timestamp Offset Registers ............................................................................................ 178

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10 Physical Layer (PHY) Section ............................................................................................ 179

10.1 PHY Section Register Configuration .................................................................................. 180

10.2 PHY Section Application Information .................................................................................. 187

10.2.1 Power Class Programming .................................................................................. 187

10.2.2 Power-Up Reset ............................................................................................... 188

10.2.3 Crystal Oscillator Selection .................................................................................. 188

10.2.4 Bus Reset ...................................................................................................... 189

11 Electrical Characteristics .................................................................................................. 190

11.1 Absolute Maximum Ratings ............................................................................................ 190

11.2 Recommended Operating Conditions ................................................................................. 190

11.3 PCIe Differential Transmitter Output Ranges ........................................................................ 191

11.4 PCIe Differential Receiver Input Ranges ............................................................................. 193

11.5 PCIe Differential Reference Clock Input Ranges .................................................................... 194

11.6 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O) .............................. 194

11.7 Electrical Characteristics Over Recommended Operating Conditions (PHY Port Driver) ...................... 195

11.8 Switching Characteristics for PHY Port Driver ....................................................................... 195

11.9 Electrical Characteristics Over Recommended Operating Conditions PHY Port Receiver .................... 196

11.10 Jitter/Skew Characteristics for 1394a PHY Port Receiver ......................................................... 196

11.11 Operating, Timing, and Switching Characteristics of XI ........................................................... 196

11.12 Electrical Characteristics Over Recommended Operating Conditions

(1394a Miscellaneous I/O) .............................................................................................. 196

12 Glossary ......................................................................................................................... 196

XIO2213B

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

List of Figures

3-1 XIO2213B Block Diagram....................................................................................................... 31

3-2 Power-Up Sequence............................................................................................................. 32

3-3 Power-Down Sequence ......................................................................................................... 33

3-4 PCIe Assert_INTA Message.................................................................................................... 37

3-5 PCIe Deassert_INTX Message................................................................................................. 37

3-6 Serial EEPROM Application .................................................................................................... 38

3-7 Serial-Bus Start/Stop Conditions and Bit Transfers.......................................................................... 39

3-8 Serial-Bus Protocol Acknowledge.............................................................................................. 39

3-9 Serial-Bus Protocol Byte Write ................................................................................................. 40

3-10 Serial-Bus Protocol Byte Read................................................................................................. 40

3-11 Serial-Bus Protocol Multibyte Read............................................................................................ 41

11-1 Test Load Diagram ............................................................................................................. 195

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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List of Tables

2-1 7 × 7 Terminals Sorted By Ball Number....................................................................................... 16

2-2 7 × 7 Terminals Sorted Alphanumerically..................................................................................... 18

2-3 12 × 12 Terminals Sorted By Ball Number.................................................................................... 20

2-4 12 × 12 Terminals Sorted Alphanumerically.................................................................................. 22

2-5 Power-Supply Terminals ........................................................................................................ 25

2-6 Ground Terminals ................................................................................................................ 26

2-7 PCIe Terminals ................................................................................................................... 26

2-8 Clock Terminals .................................................................................................................. 26

2-9 1394 Terminals ................................................................................................................... 27

2-10 Reserved Terminals.............................................................................................................. 29

2-11 Miscellaneous Terminals........................................................................................................ 29

3-1 XIO2213B Reset Options ....................................................................................................... 34

3-2 Initial Flow Control Credit Advertisements.................................................................................... 35

3-3 Messages Supported by Bridge................................................................................................ 36

3-4 EEPROM Register Loading Map............................................................................................... 41

3-5 Registers Used To Program Serial-Bus Devices............................................................................. 43

3-6 Clocking In Low Power States.................................................................................................. 44

3-7 1394b OHCI Configuration Register Map..................................................................................... 46

3-8 1394 OHCI Memory Command Options ...................................................................................... 47

4-1 Classic PCI Configuration Register Map...................................................................................... 48

4-2 Command Register Description ............................................................................................... 50

4-3 Status Register Description .................................................................................................... 51

4-4 Class Code and Revision ID Register Description .......................................................................... 52

4-5 Device Control Base Address Register Description ........................................................................ 53

4-6 Device Control Base Address Register Description ........................................................................ 54

4-7 I/O Base Register Description ................................................................................................. 55

4-8 I/O Limit Register Description .................................................................................................. 56

4-9 Secondary Status Register Description ...................................................................................... 57

4-10 Memory Base Register Description ........................................................................................... 58

4-11 Memory Limit Register Description ............................................................................................ 58

4-12 Prefetchable Memory Base Register Description ........................................................................... 59

4-13 Prefetchable Memory Limit Register Description ............................................................................ 59

4-14 Prefetchable Base Upper 32 Bits Register Description .................................................................... 60

4-15 Prefetchable Limit Upper 32 Bits Register Description ..................................................................... 60

4-16 I/O Base Upper 16 Bits Register Description ................................................................................ 61

4-17 I/O Limit Upper 16 Bits Register Description ................................................................................ 61

4-18 Bridge Control Register Description ........................................................................................... 63

4-19 Power Management Capabilities Register Description ..................................................................... 66

4-20 Power Management Control/Status Register Description .................................................................. 67

4-21 PM Bridge Support Extension Register Description ........................................................................ 68

4-22 MSI Message Control Register Description .................................................................................. 69

4-23 MSI Message Lower Address Register Description ........................................................................ 70

4-24 MSI Message Data Register Description ..................................................................................... 71

4-25 PCI Express Capabilities Register Description .............................................................................. 73

4-26 Device Capabilities Register Description ..................................................................................... 74

4-27 Device Control Register Description .......................................................................................... 75

4-28 Device Status Register Description ........................................................................................... 76

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

4-29 Link Capabilities Register Description ........................................................................................ 77

4-30 Link Control Register Description ............................................................................................. 78

4-31 Link Status Register Description .............................................................................................. 79

4-32 Serial-Bus Slave Address Register Descriptions ............................................................................ 80

4-33 Serial-Bus Control and Status Register Description ........................................................................ 81

4-34 GPIO Control Register Description ............................................................................................ 82

4-35 GPIO Data Register Description ............................................................................................... 83

4-36 Control and Diagnostic Register 0 Description .............................................................................. 84

4-37 Control and Diagnostic Register 1 Description .............................................................................. 86

4-38 Control and Diagnostic Register 2 Description .............................................................................. 87

4-39 Subsystem Access Register Description ..................................................................................... 88

4-40 General Control Register Description ......................................................................................... 89

4-41 Arbiter Control Register Description .......................................................................................... 92

4-42 Arbiter Request Mask Register Description .................................................................................. 93

4-43 Arbiter Time-Out Status Register Description ............................................................................... 94

5-1 PCIe Extended Configuration Register Map.................................................................................. 96

5-2 Uncorrectable Error Status Register Description ............................................................................ 97

5-3 Uncorrectable Error Mask Register Description ............................................................................. 98

5-4 Uncorrectable Error Severity Register Description .......................................................................... 99

5-5 Correctable Error Status Register Description ............................................................................. 101

5-6 Correctable Error Mask Register Description .............................................................................. 102

5-7 Advanced Error Capabilities and Control Register Description .......................................................... 103

5-8 Secondary Uncorrectable Error Status Register Description ............................................................. 104

5-9 Secondary Uncorrectable Error Mask Register Description .............................................................. 105

5-10 Secondary Uncorrectable Error Severity Register Description .......................................................... 106

5-11 Secondary Error Capabilities and Control Register Description ......................................................... 107

5-12 Secondary Header Log Register Description .............................................................................. 108

6-1 Device Control Memory Window Register Map............................................................................. 109

6-2 GPIO Control Register Description .......................................................................................... 110

6-3 GPIO Data Register Description ............................................................................................. 111

6-4 Serial-Bus Slave Address Register Descriptions .......................................................................... 112

6-5 Serial-Bus Control and Status Register Description ....................................................................... 113

7-1 1394 OHCI Configuration Register Map..................................................................................... 114

7-2 Command Register Description .............................................................................................. 116

7-3 Status Register Description ................................................................................................... 117

7-4 Class Code and Revision ID Registers Description ....................................................................... 118

7-5 Latency Timer and Class Cache Line Size Registers Description ...................................................... 118

7-6 Header Type and BIST Registers Description ............................................................................. 119

7-7 OHCI Base Address Register Description .................................................................................. 119

7-8 TI Base Address Register Description ...................................................................................... 120

7-9 Subsystem Vendor ID and Subsystem ID Registers Description ........................................................ 121

7-10 Interrupt Line and Interrupt Pin Registers Description .................................................................... 122

7-11 Minimum Grant and Minimum Latency Registers Description ........................................................... 123

7-12 OHCI Control Register Description .......................................................................................... 123

7-13 Capability ID and Next Item Pointer Registers Description ............................................................... 124

7-14 Power Management Capabilities Register Description ................................................................... 124

7-15 Power Management Control and Status Register Description ........................................................... 125

7-16 Power Management Extension Registers Description .................................................................... 125

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

7-17 PCI Miscellaneous Configuration Register ................................................................................. 127

7-18 Link Enhancement Control Register Description .......................................................................... 129

7-19 Subsystem Access Register Description ................................................................................... 130

8-1 OHCI Register Map............................................................................................................. 131

8-2 OHCI Version Register Description .......................................................................................... 134

8-3 GUID ROM Register Description ............................................................................................ 135

8-4 Asynchronous Transmit Retries Register Description ..................................................................... 136

8-5 CSR Control Register Description ........................................................................................... 137

8-6 Configuration ROM Header Register Description .......................................................................... 138

8-7 Bus Options Register Description ............................................................................................ 139

8-8 Configuration ROM Mapping Register Description ........................................................................ 141

8-9 Posted Write Address Low Register Description .......................................................................... 141

8-10 Posted Write Address High Register Description .......................................................................... 142

8-11 Host Controller Control Register Description ............................................................................... 144

8-12 Self-ID Count Register Description .......................................................................................... 145

8-13 Isochronous Receive Channel Mask High Register Description ......................................................... 146

8-14 Isochronous Receive Channel Mask Low Register Description ......................................................... 148

8-15 Interrupt Event Register Description ......................................................................................... 149

8-16 Interrupt Mask Register Description ......................................................................................... 150

8-17 Isochronous Transmit Interrupt Event Register Description .............................................................. 152

8-18 Isochronous Receive Interrupt Event Register Description ............................................................... 153

8-19 Initial Bandwidth Available Register Description ........................................................................... 154

8-20 Initial Channels Available High Register Description ...................................................................... 155

8-21 Initial Channels Available Low Register Description ...................................................................... 155

8-22 Fairness Control Registre Description ...................................................................................... 156

8-23 Link Control Register Description ............................................................................................ 157

8-24 Node Identification Register Description .................................................................................... 158

8-25 PHY Control Register Description ........................................................................................... 159

8-26 Isochronous Cycle Timer Register Description ............................................................................ 160

8-27 Asynchronous Request Filter High Register Description ................................................................. 161

8-28 Asynchronous Request Filter Low Register Description .................................................................. 163

8-29 Physical Request Filter High Register Description ........................................................................ 164

8-30 Physical Request Filter Low Register Description ......................................................................... 166

8-31 Asynchronous Context Control Register Description ...................................................................... 167

8-32 Asynchronous Context Command Pointer Register Description ......................................................... 168

8-33 Isochronous Transmit Context Control Register Description ............................................................. 169

8-34 Isochronous Receive Context Control Register Description ............................................................. 171

8-35 Isochronous Receive Context Match Register Description ............................................................... 172

9-1 TI Extension Register Map .................................................................................................... 174

9-2 Isochronous Receive Digital Video Enhancement Registers Description .............................................. 175

9-3 Link Enhancement Control Registers Description ......................................................................... 176

9-4 Timestamp Offset Registers Description .................................................................................... 178

10-1 Base Register Description .................................................................................................... 181

10-2 Base Register Field Description .............................................................................................. 181

10-3 Page 0 (Port Status) Register Description .................................................................................. 183

10-4 Page 0 (Port Status) Register Field Description ........................................................................... 184

10-5 Page 1 (Vendor ID) Register Configuration ................................................................................ 185

10-6 Page 1 (Vendor ID) Register Field Descriptions ........................................................................... 186

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

10-7 Page 7 (Vendor Dependent) Register Configuration ...................................................................... 187

10-8 Page 7 (Vendor Dependent) Register Field Descriptions ................................................................ 187

10-9 Power Class Register Description ........................................................................................... 187

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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XIO2213B

PCI Express™ TO 1394b OHCI WITH 3-PORT PHY

Check for Samples: XIO2213B

1 Introduction

1.1 XIO2213B Features

123

• Full ×1 PCI Express™ (PCIe) Throughput

• Fully Compliant With PCI Express Base Specification, Revision 1.1

• Utilizes 100-MHz Differential PCI Express Common Reference Clock or 125-MHz SingleEnded Reference Clock • EEPROM Configuration Support to Load Global

• Fully Supports Provisions of IEEE Std P1394b2002 • Support for D1, D2, D3

• Fully Compliant With Provisions of IEEE Std • Active-State Link Power Management Saves 1394-1995 for a High-Performance Serial Bus Power When Packet Activity on the PCI and IEEE Std 1394a-2000 Express Link Is Idle, Using Both L0s and L1

• Fully Compliant With 1394 Open Host Controller Interface (OHCI) Specification, • Eight 3.3-V Multifunction General-Purpose I/O Revision 1.1 and Revision 1.2 Draft (GPIO) Terminals

• Three IEEE Std 1394b Fully Compliant Cable

Ports at 100M Bit/s, 200M Bit/s, 400M Bit/s, and 800M Bit/s

• Cable Ports Monitor Line Conditions for Active Connection to Remote Node

• Cable Power Presence Monitoring

Unique ID for 1394 Fabric

hot

States

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2OHCI-Lynx is a trademark of Texas Instruments. 3PCI Express is a trademark of PCI-SIG.

XIO2213B

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2 Overview

The Texas Instruments XIO2213B is a single-function PCI Express™ (PCIe) to PCI local bus translation bridge, where the PCI bus interface is internally connected to a 1394b open host controller/link-layer controller with a 3-port 1394b physical layer (PHY). When the XIO2213B is properly configured, this solution provides full PCIe and 1394b functionality and performance.

The TI XIO2213B is a PCIe to PCI translation bridge, where the PCI bus interface is internally connected to a 1394b open host controller/link-layer controller with a 3-port 1394b PHY. The PCIe to PCI translation bridge is fully compatible with the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The 1394b OHCI controller function is fully compatible with IEEE Std 1394b and the latest 1394 Open Host Controller Interface (OHCI) Specification.

The XIO2213B simultaneously supports up to four posted write transactions, four nonposted transactions, and four completion transactions pending in each direction at any time. Each posted write data queue and completion data queue can store up to 8K bytes of data. The nonposted data queues can store up to 128 bytes of data.

The PCIe interface supports a ×1 link operating at full 250 Mbit/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting capability including ECRC as defined in the PCI Express Base Specification, Revision 1.1. Supplemental firmware or software is required to fully utilize both of these features.

Robust pipeline architecture is implemented to minimize system latency. If parity errors are detected, packet poisoning is supported for both upstream and downstream operations.

SCPS210F –OCTOBER 2008–REVISED MAY 2013

PCIe power management (PM) features include active-state link PM, PME mechanisms, and all conventional PCI D states. If the active-state link PM is enabled, the link automatically saves power when idle using the L0s and L1 states. PM active-state NAK, PM PME, and PME-to-ACK messages are supported. The bridge is compliant with the latest PCI Bus Power Management Specification and provides several low-power modes, which enable the host power system to further reduce power consumption

Eight general-purpose inputs and outputs (GPIOs), configured through accesses to the PCIe configuration space, allow for further system control and customization.

Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The device provides physical write posting and a highly tuned physical data path for SBP-2 performance. The device is capable of transferring data between the PCIe bus and the 1394 bus at 100M bit/s, 200M bit/s, 400M bit/s, and 800M bit/s. The device provides three 1394 ports that have separate cable bias (TPBIAS).

As required by the 1394 Open Host Controller Interface (OHCI) Specification, internal control registers are memory mapped and nonprefetchable. This configuration header is accessed through configuration cycles specified by PCIe, and it provides plug-and-play (PnP) compatibility.

The PHY provides the digital and analog transceiver functions needed to implement a 3-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. An optional external 2-wire serial EEPROM interface is provided to load the global unique ID for the 1394 fabric.

The XIO2213B requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbit/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.

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To ensure that the XIO2213B conforms to IEEE Std 1394b-2002, the BMODE terminal must be asserted. The BMODE terminal does not select the cable-interface mode of operation. BMODE selects the internal PHY-section/LLC-section interface mode of operation and affects the arbitration modes on the cable. BMODE must be pulled high during normal operation.

Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They can be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable). The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the XIO2213B, this bit can only be set by a write to the PHY register set. If a node is to be a contender for IRM or BM, the node software must set this bit in the PHY register set.

2.1 Related Documents

• PCI Express™ to PCI/PCI-X Bridge Specification, Revision 1.0

• PCI Express™ Base Specification, Revision 1.1

• PCI Express™ Card Electromechanical Specification, Revision 1.1

• PCI Local Bus Specification, Revision 2.3 and Revision 3.0

• PCI-to-PCI Bridge Architecture Specification, Revision 1.1

• PCI Bus Power-Management Interface Specification, Revision 1.1 and Revision 1.2

• 1394 Open Host Controller Interface (OHCI) Specification, Release 1.2

• High-Performance Serial Bus, IEEE Std 1394-1995

• High-Performance Serial Bus, Amendment 1, IEEE Std 1394a-2000

• High-Performance Serial Bus, Amendment 2, IEEE Std 1394b-2002

• Express Card Standard, Release 1.0 and Release 1.1

• PCI Express™ Jitter and BER white paper

• PCI Mobile Design Guide, Revision 1.1

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2.2 Documents Conventions

Throughout this data manual, several conventions are used to convey information. These conventions are:

• To identify a binary number or field, a lower-case b follows the numbers. For example, 000b is a 3-bit binary field.

• To identify a hexadecimal number or field, a lower-case h follows the numbers. For example, 8AFh is a 12-bit hexadecimal field.

• All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format.

• If the signal or terminal name has a bar above the name (for example, GRST), this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b.

• Differential signal names end with P, N, +, or – designators. The P or + designators signify the positive signal associated with the differential pair. The N or – designators signify the negative signal associated with the differential pair.

• RSVD indicates that the referenced item is reserved.

• In Sections 4 through 6, the configuration space for the bridge is defined. For each register bit, the software access method is identified in an access column. The legend for this access column includes the following entries:

– R: Read access by software – U: Updates by the bridge internal hardware – W: Write access by software – C: Clear an asserted bit with a write back of 1b by software. Write of zero to the field has no effect. – S: The field may be set by a write of one. Write of zero to the field has no effect. – NA: Not accessible or not applicable

• The XIO2213B consists of a PCIe to PCI translation bridge, where the secondary PCI bus is internally connected to a 1394b OHCI with a 3-port PHY. When describing functionality that is specific to the PCIe to PCI translation bridge, the term bridge is used to reduce text. The term 1394b OHCI is used to reduce text when describing the 1394b OHCI with 3-port PHY function.

• LLC refers to the 1394 link layer controller.

SCPS210F –OCTOBER 2008–REVISED MAY 2013

2.3 Ordering Information

PACKAGE VOLTAGE ORDERABLE PART NUMBER

167-terminal (Lead-Free) PBGA – ZAY 3.3-V and 1.5-V power terminals

168-terminal (Lead-Free) BGA – ZAJ 3.3-V and 1.5-V power terminals XIO2213BZAJ

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2.4 Terminal Assignments

The XIO2213B is packaged in a 168-ball BGA (ZAJ) and a 167-ball PBGA (ZAY). For the ZAJ package

Table 2-1 lists the terminals sorted by ball number. Table 2-2 lists the terminals in alphanumerical order.

For the ZAY packageTable 2-3 lists the terminals sorted by ball number. Table 2-4 lists the terminals in alphanumerical order.

Table 2-1. 7 × 7 Terminals Sorted By Ball Number

BALL NO. TERMINAL NAME

A01 VDDA_33 A02 CNA A03 TESTM A04 RXN A05 RXP A06 PHY_RESET A07 TXN A08 TXP A09 PC1 A10 REF1_PCIE A11 REF0_PCIE A12 TPBIAS2 A13 TPA2+ B01 REFCLK+ B03 PD B04 VDDA_15 B05 VDDA_15 B06 BMODE B07 VREG_PD B08 PC2 B09 VDD_33_COMB B10 VDD_33_COM_IO B11 VDD_15_COMB B12 PERST B13 TPA2– C01 REFCLK– C02 LINKON_L C03 LPS_L C04 VDDA_15 C05 VDDA_15 C06 VSSA_PCIE C07 VDD_15 C08 VDDA_33 C09 VDD_33_AUX C10 RSVD C11 PC0 C12 GRST C13 TPB2+ D01 LREQ_L D02 LKON/DS2_P D03 LPS_P D04 VSSA D05 VSSA_PCIE D06 VSSA_PCIE

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Table 2-1. 7 × 7 Terminals Sorted By Ball

Number (continued)

BALL NO. TERMINAL NAME

D07 VSSA D08 DVDD_CORE D09 DVDD_CORE D10 VDD_33 D11 RSVD D12 RSVD D13 TPB2– E01 LREQ_P E02 PINT_L E03 PINT_P E04 DVDD_3.3 E05 GND E06 VSSA_PCIE E07 VSS E08 VSS E09 VSSA E10 AVDD_3.3 E11 RSVD E12 TPBIAS1 E13 TPA1+ F01 CTL0 F02 PCLK_P F03 PCLK_L F04 GND F05 GND F06 GND F07 GND F08 GND F09 GND F10 AVDD_3.3 F11 RSVD F12 RSVD F13 TPA1– G01 CTL1 G02 LCLK_P G03 LCLK_L G04 GND G05 GND G06 GND G07 GND G08 GND G09 GND G10 GND G11 REFCLK_SEL G12 SCL

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Table 2-1. 7 × 7 Terminals Sorted By Ball Table 2-1. 7 × 7 Terminals Sorted By Ball

Number (continued) Number (continued)

BALL NO. TERMINAL NAME BALL NO. TERMINAL NAME

G13 TPB1+ L01 D6 H01 D0 L02 GPIO2 H02 D1 L03 VDD_33 H03 VDD_15 L04 GPIO3 H04 GND L05 GPIO7 H05 GND L06 VDD_15 H06 GND L07 GND H07 GND L08 VDD_33 H08 GND L09 CYCLEOUT H09 VDD_15 L10 RSVD H10 AVDD_3.3 L11 RSVD H11 SDA L12 RSVD H12 CLKREQ L13 TPB0+ H13 TPB1– M01 D7 J01 D3 M02 GPIO0 J02 D2 M03 GPIO4 J03 VDD_15 M04 AVDD_3.3 J05 GND M05 XO J06 GND M06 GPIO6 J07 GND M07 DS1 J08 GND M08 OHCI_PME J09 VDD_15 M09 RSVD J10 AVDD_3.3 M10 SE J11 RSVD M11 RSVD J12 TPBIAS0 M12 RSVD J13 TPA0+ M13 TPB0– K01 D5 N01 GPIO1 K02 D4 N02 R1 K03 VDD_33 N03 R0 K04 GPIO5 N04 PLLGND K05 DVDD_3.3 N05 XI K06 DVDD_3.3 N06 PLLVDD_CORE K07 GND N07 PLLVDD_3.3 K08 VDD_33 N08 DS0 K09 DVDD_CORE N09 CPS K10 RSVD N10 SM K11 RSVD N11 RSVD K12 RSVD N12 RSVD K13 TPA0–

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Table 2-2. 7 × 7 Terminals Sorted

Alphanumerically

BALL NO. TERMINAL NAME

E10 AVDD_3.3 F10 AVDD_3.3 H10 AVDD_3.3 J10 AVDD_3.3 M04 AVDD_3.3 B06 BMODE H12 CLKREQ A02 CNA N09 CPS F01 CTL0 G01 CTL1 L09 CYCLEOUT H01 D0 H02 D1 J02 D2 J01 D3 K02 D4 K01 D5 L01 D6 M01 D7 N08 DS0 M07 DS1 E04 DVDD_3.3 K05 DVDD_3.3 K06 DVDD_3.3 D08 DVDD_CORE D09 DVDD_CORE K09 DVDD_CORE E05 GND F04 GND F05 GND F06 GND F07 GND F08 GND F09 GND G04 GND G05 GND G06 GND G07 GND G08 GND G09 GND G10 GND H04 GND H05 GND H06 GND H07 GND H08 GND J04 GND J05 GND J06 GND

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Table 2-2. 7 × 7 Terminals Sorted

Alphanumerically (continued)

BALL NO. TERMINAL NAME

J07 GND

J08 GND K07 GND L07 GND M02 GPIO0 N01 GPIO1 L02 GPIO2 L04 GPIO3 M03 GPIO4 K04 GPIO5 M06 GPIO6 L05 GPIO7 C12 GRST G03 LCLK_L G02 LCLK_P C02 LINKON_L D02 LKON/DS2_P C03 LPS_L D03 LPS_P D01 LREQ_L E01 LREQ_P M08 OHCI_PME C11 PC0 A09 PC1 B08 PC2 F03 PCLK_L F02 PCLK_P B03 PD B12 PERST E02 PINT_L E03 PINT_P N04 PLLGND N07 PLLVDD_3.3 N06 PLLVDD_CORE N03 R0 N02 R1 A11 REF0_PCIE A10 REF1_PCIE C01 REFCLK– G11 REFCLK_SEL B01 REFCLK+ A06 PHY_RESET C10 RSVD D11 RSVD D12 RSVD E11 RSVD F11 RSVD F12 RSVD

J11 RSVD K10 RSVD

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Table 2-2. 7 × 7 Terminals Sorted Table 2-2. 7 × 7 Terminals Sorted

Alphanumerically (continued) Alphanumerically (continued)

BALL NO. TERMINAL NAME BALL NO. TERMINAL NAME

K11 RSVD A07 TXN K12 RSVD A08 TXP L10 RSVD C07 VDD_15 L11 RSVD H03 VDD_15 L12 RSVD H09 VDD_15 M09 RSVD J03 VDD_15 M11 RSVD J09 VDD_15 M12 RSVD L06 VDD_15 N11 RSVD B11 VDD_15_COMB N12 RSVD C09 VDD_33_AUX N13 RSVD D10 VDD_33 A04 RXN K03 VDD_33 A05 RXP K08 VDD_33 G12 SCL L03 VDD_33 H11 SDA L08 VDD_33 M10 SE B10 VDD_33_COM_IO N10 SM B09 VDD_33_COMB A03 TESTM B04 VDDA_15 B07 VREG_PD B05 VDDA_15 K13 TPA0– C04 VDDA_15 J13 TPA0+ C05 VDDA_15 F13 TPA1– A01 VDDA_33 E13 TPA1+ C08 VDDA_33 B13 TPA2– E07 VSS A13 TPA2+ E08 VSS M13 TPB0– D04 VSSA L13 TPB0+ D07 VSSA H13 TPB1– E09 VSSA G13 TPB1+ C06 VSSA_PCIE D13 TPB2– D05 VSSA_PCIE C13 TPB2+ D06 VSSA_PCIE J12 TPBIAS0 E06 VSSA_PCIE E12 TPBIAS1 N05 XI A12 TPBIAS2 M05 XO

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Table 2-3. 12 × 12 Terminals Sorted By Ball

Number

BALL NO. TERMINAL NAME

A01 REFCLK+ A02 CNA A03 RXN A04 RXP A05 BMODE A06 VREG_PD A07 VSS A08 TXN A09 TXP A10 VDDA_33 A11 PC2 A12 REF1_PCIE A13 REF0_PCIE A14 VSS B01 REFCLK– B02 TESTM B03 PD B04 PHY_RESET B05 VDDA_15 B06 VSSA B07 VDDA_15 B08 VDD_15 B09 VDDA_15 B10 VDDA_15 B11 VDD_33_COMB B12 VDD_33_AUX B13 PERST B14 TPA2+ C01 LPS_L C02 LPS_P C03 VDDA_33 C04 VSSA_PCIE C05 VSSA_PCIE C06 VSSA_PCIE C07 VSSA_PCIE C08 DVDD_3.3 C09 DVDD_CORE C10 VSSA C11 VDD_33_COM_IO C12 VDD_15_COMB C13 GRST C14 TPA2– D01 LKON/DS2_P D02 PINT_L D03 PINT_P D12 RSVD D13 RSVD D14 TPB2+ E01 LINKON_L E02 LREQ_P

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Table 2-3. 12 × 12 Terminals Sorted By Ball

Number (continued)

BALL NO. TERMINAL NAME

E03 VDD_33 E06 GND E07 GND E08 PC1 E09 PC0 E10 AVDD_3.3 E12 RSVD E13 TPBIAS2 E14 TPB2– F01 PCLK_P F02 LREQ_L F03 DVDD_CORE F05 VSSA F06 GND F07 GND F08 GND F09 GND F10 AVDD_3.3 F12 RSVD F13 RSVD F14 TPA1+ G01 PCLK_L G02 LCLK_L G03 VDD_15 G05 GND G06 GND G07 GND G08 GND G09 GND G10 VDD_33 G12 RSVD G13 TPBIAS1 G14 TPA1– H01 CTL0 H02 LCLK_P H03 VDD_15 H05 GND H06 GND H07 GND H08 GND H09 GND H10 VDD_33 H12 SDA H13 REFCLK_SEL H14 TPB1+

J01 CTL1

J02 D0

J03 DVDD_3.3

J05 GND

J06 GND

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Table 2-3. 12 × 12 Terminals Sorted By Ball Table 2-3. 12 × 12 Terminals Sorted By Ball

Number (continued) Number (continued)

BALL NO. TERMINAL NAME BALL NO. TERMINAL NAME

J07 GND M10 AVDD_3.3 J08 GND M11 RSVD J09 AVDD_3.3 M12 RSVD J10 VDD_33 M13 RSVD J12 CLKREQ M14 TPB0+ J13 SCL N01 R0 J14 TPB1– N02 GPIO1 K01 D2 N03 GPIO3 K02 D1 N04 GPIO4 K03 DVDD_3.3 N05 PLLGND K05 GND N06 GPIO7 K06 GND N07 PLLVDD_3.3 K07 GND N08 CYCLEOUT K08 GND N09 DS0 K09 AVDD_3.3 N10 RSVD K10 VDD_15 N11 RSVD K12 RSVD N12 RSVD K13 TPBIAS0 N13 RSVD K14 TPA0+ N14 TPB0– L01 D3 P01 GPIO0 L02 D4 P02 GPIO2 L03 D5 P03 RSVD L12 RSVD P04 XI L13 RSVD P05 GPIO5 L14 TPA0– P06 GPIO6 M01 R1 P07 VDD_15 M02 D6 P08 OHCI_PME M03 D7 P09 DS1 M04 AVDD_3.3 P10 RSVD M05 VDD_33 P11 RSVD M06 VDD_15 P12 CPS M07 PLLVDD_CORE P13 SE M08 RSVD P14 SM M09 DVDD_CORE

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Table 2-4. 12 × 12 Terminals Sorted

Alphanumerically

TERMINAL NAME BALL NO.

AVDD_3.3 E10 AVDD_3.3 F10 AVDD_3.3 J09 AVDD_3.3 K09 AVDD_3.3 M10 AVDD_3.3 M04 BMODE A05 CLKREQ J12 CNA A02 CPS P12 CTL0 H01 CTL1 J01 CYCLEOUT N08 D0 J02 D1 K02 D2 K01 D3 L01 D4 L02 D5 L03 D6 M02 D7 M03 DS0 N09 DS1 P09 DVDD_3.3 C08 DVDD_3.3 J03 DVDD_3.3 K03 DVDD_CORE C09 DVDD_CORE F03 DVDD_CORE M09 GND E06 GND E07 GND F06 GND F07 GND F08 GND F09 GND G05 GND G06 GND G07 GND G08 GND G09 GND H05 GND H06 GND H07 GND H08 GND H09 GND J05

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Table 2-4. 12 × 12 Terminals Sorted

Alphanumerically (continued)

TERMINAL NAME BALL NO.

GND J06 GND J07 GND J08 GND K05 GND K06 GND K07 GND K08 GPIO0 P01 GPIO1 N02 GPIO2 P02 GPIO3 N03 GPIO3 N04 GPIO5 P05 GPIO6 P06 GPIO7 N06 GRST C13 LCLK_L G02 LCLK_P H02 LINKON_L E01 LKON/DS2_P D01 LPS_L C01 LPS_P C02 LREQ_L F02 LREQ_P E02 OHCI_PME P08 PC0 E09 PC1 E08 PC2 A11 PCLK_L G01 PCLK_P F01 PD B03 PERST B13 PINT_L D02 PINT_P D03 PLLGND N05 PLLVDD_3.3 N07 PLLVDD_CORE M07 R0 N01 R1 M01 REF0_PCIE A13 REF1_PCIE A12 REFCLK- B01 REFCLK_SEL H13 REFCLK+ A01 PHY_RESET B04 RSVD G12

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Table 2-4. 12 × 12 Terminals Sorted Table 2-4. 12 × 12 Terminals Sorted

Alphanumerically (continued) Alphanumerically (continued)

TERMINAL NAME BALL NO. TERMINAL NAME BALL NO.

RSVD F13 TPBIAS0 K13 RSVD F12 TPBIAS1 G13 RSVD E12 TPBIAS2 E13 RSVD D12 TXN A08 RSVD D13 TXP A09 RSVD M08 VDD_15 G03 RSVD N10 VDD_15 H03 RSVD P10 VDD_15 K10 RSVD P11 VDD_15 M06 RSVD N11 VDD_15 B08 RSVD M11 VDD_15_COMB C12 RSVD N12 VDD_33 E03 RSVD N13 VDD_33 G10 RSVD M12 VDD_33 H10 RSVD M13 VDD_33 J10 RSVD L13 VDD_33 M05 RSVD K12 VDD_33_AUX B12 RSVD L12 VDD_33_COM_IO C11 RXN A03 VDD_33_COMB B11 RXP A04 VDDA_15 B10 SCL J13 VDDA_15 B09 SDA H12 VDDA_15 B07 SE P13 VDDA_15 B05 SM P14 VDDA_33 C03 TESTM B02 VDDA_33 A10 VREG_PD A06 VDD_15 P07 TPA0– L14 VSS A14 TPA0+ K14 VSS A07 TPA1– G14 VSSA F05 TPA1+ F14 VSSA C10 TPA2– C14 VSSA B06 TPA2+ B14 VSSA_PCIE C04 TPB0– N14 VSSA_PCIE C05 TPB0+ M14 VSSA_PCIE C06 TPB1– J14 VSSA_PCIE C07 TPB1+ H14 XI P04 TPB2– E14 RSVD P03 TPB2+ D14

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2.5 Terminal Descriptions

The following tables give a description of the terminals. These terminals are grouped in tables by functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.

The following list describes the different input/output cell types that appear in the terminal description tables:

• HS DIFF IN = High-speed differential input

• HS DIFF OUT = High-speed differential output

• LV CMOS = 3.3-V low-voltage CMOS input or output with 3.3-V clamp rail

• BIAS = Input/output terminals that generate a bias voltage to determine a driver's operating current

• Feedthrough = Terminals that connect directly to macros within the part and not through an input or output cell

• PWR = Power terminal

• GND = Ground terminal

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Table 2-5. Power-Supply Terminals

BALL NO.

SIGNAL DESCRIPTION

ZAY ZAJ

PACKAGE PACKAGE

DD_15

G03 H03 C07 H03 PWR Bypass 1.5-V digital core power for the link K10 M06 H09 J03 capacitors B08 P07 J09 L06

DDA_15

DD_33

B10 B09 B04 B05 PWR Filter 1.5-V analog power for the link B07 B05 C04 C05

E03 M05 D10 K03 PWR Bypass 3.3-V digital I/O power for the link

J10 H10 K08 L03 capacitors

G10 L08

DD_33_AUX

DDA_33

B12 C09 This terminal is connected to VSS through a pulldown resistor,

C03 A10 A01 C08 PWR Filter 3.3-V analog power for the link. This supply terminal is

DVDD_CORE C09 F03 D08 D09 PWR Bypass Digital 1.95-V circuit power for the PHY. A combination of high-

M09 K09 capacitors frequency decoupling capacitors near each terminal is

PLLVDD_CORE M07 N06 PWR Bypass PLL 1.95-V circuit power for the PHY. A combination of high-

DVDD_33 C08 J03 E04 K05 PWR Bypass 3.3-V digital I/O power for the PHY

K03 K06 capacitors

AVDD_33 M04 E10 E10 F10 PWR Filter 3.3-V analog power for the PHY

F10 J09 H10 J10

K09 M10 M04

PLLVDD_33 N07 N07 PWR Bypass PLL 3.3-V circuit power for the PHY. This supply terminal is

DD_15_COMB

DD_33_COMB

DD_33_COMBIO

C12 B11 PWR Bypass Internal 1.5-V main power output for external bypass capacitor

B11 B09 PWR Bypass Internal 3.3-V main power output for external bypass capacitor

C11 B10 PWR Bypass Internal 3.3-V IO power output for external bypass capacitor

I/O EXTERNAL

TYPE PARTS

capacitors frequency decoupling capacitors near each terminal is

capacitors separated from the other power terminals internal to the device

capacitors filtering

since the XIO2213B does not support auxiliary power.

separated from the other power terminals internal to the device to provide noise isolation.

suggested, such as paralleled 0.1 μF and 0.001 μF. An additional 1-μF capacitor is required for voltage regulation. These supply terminals are separated from the other power terminals internal to the device to provide noise isolation.

suggested, such as paralleled 0.1 μF and 0.001 μF. An additional 1-μF capacitor is required for voltage regulation, and the PLLVDD_CORE terminals must be separate from the DVDD_CORE terminals. These supply terminals are separated from the other power terminals internal to the device to provide noise isolation.

to provide noise isolation. The PLLVDD_33 and V should be connected together with a low-dc-impedance

DDA_33

pins

connection on the circuit board.

Caution: Do not use this terminal to supply external power to other devices.

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Table 2-6. Ground Terminals

BALL NO.

SIGNAL DESCRIPTION

SSA

SSA_PCIE

PLLGND N05 N04 GND PLL circuit ground. This terminal must be tied to the low-

GND E06 E07 F06 F07 F08 E05 F04 F05 F06 F07 GND Ground. These terminals must be tied together to the low-

F09 G05 G06 G07 G08 F08 F09 G04 G05 G06 impedance circuit-board ground plane. G09 H05 H06 H07 H08 G07 G08 G09 G10 H04

ZAY ZAJ

PACKAGE PACKAGE

A07 A14 E07 E08 GND Digital ground for link

B06 C10 F05 D04 D07 E09 GND Analog ground for link

C04 C05 C06 C07 C06 D05 D06 E06 GND Analog ground for PCIe function

H09 J05 J06 J07 J08 H05 H06 H07 H08 J04

K05 K06 K07 K08 J05 J06 J07 J08 K07

L07

I/O

TYPE

impedance circuit-board ground plane.

Table 2-7. PCIe Terminals

BALL NO.

SIGNAL DESCRIPTION

PERST B13 B12 I PCI Express reset. PERST identifies when the system power is stable

REF0_PCIE A13 A11 I/O External External reference resistor + and terminals for setting TX driver current. REF1_PCIE A12 A10 resistor An external resistor is connected between terminals REF0_PCIE and

RXP A04 A05 DI High-speed receive pair. RXP and RXN comprise the differential RXN A03 A04 receive pair for the single PCIe lane supported.

TXP A09 A08 DO Series High-speed transmit pair. TXP and TXN comprise the differential TXN A08 A07 capacitors transmit pair for the single PCIe lane supported.

ZAY ZAJ

PACKAGE PACKAGE

I/O EXTERNAL

TYPE PARTS

and generates an internal power-on reset. Note: The PERST input buffer has hysteresis.

REF1_PCIE.

Table 2-8. Clock Terminals

BALL NO.

SIGNAL DESCRIPTION

REFCLK_SEL H13 G11 I Pullup or Reference clock select. This terminal selects the reference clock input.

REFCLK+ A01 B01 DI Reference clock positive. REFCLK+ and REFCLK– comprise the

REFCLK– B01 C01 DI Capacitor to Reference clock negative. REFCLK+ and REFCLK– comprise the

CLKREQ J12 H12 O Clock request. This terminal is used to support the clock request

XI P04 N05 I Oscillator input. This terminal connects to a 98.304-MHz low-jitter

ZAY ZAJ

PACKAGE PACKAGE

I/O EXTERNAL

TYPE PARTS

pulldown

resistor

VSSfor differential input pair for the 100-MHz system reference clock. For a

single- single-ended, 125-MHz system reference clock, attach a capacitor from ended REFCLK– to VSS.

mode

0 = 100-MHz differential common reference clock used 1 = 125-MHz single-ended reference clock used

differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, use the REFCLK+ input.

protocol.

external oscillator. XI is a 1.8-V CMOS input. Oscillator jitter must be 5ps RMS or better. If only 3.3-V oscillators can be acquired, great care must be taken to not introduce significant jitter by the means used to level shift from 3.3 V to 1.8 V. If a resistor divider is used, a high-current oscillator and low-value resistors must be used to minimize RC time constants.

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Table 2-9. 1394 Terminals

BALL NO.

SIGNAL DESCRIPTION

CNA A02 A02 I/O Cable not active. This terminal is asserted high when there are no ports receiving

CPS P12 N09 I Cable power status. This terminal is normally connected to cable power through a

DS0 N09 N08 I Data-strobe-only mode for port 0. IEEE Std 1394a-2000-only port-0-enable

DS1 P09 M07 I Data-strobe-only mode for port 1. IEEE Std 1394a-2000-only port-1-enable

PC0 E09 C11 I Power-class programming. On hardware reset, these inputs set the default value of PC1 E08 A09 the power class indicated during self-ID. Programming is done by tying the terminals PC2 A11 B08 high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ

R0 N01 N03 I/O Current-setting resistor. These terminals are connected to an external resistance to R1 M01 N02 set the internal operating currents and cable driver output currents. A resistance of

TPA0P K14 J13 I/O Port 0 twisted-pair cable A differential. Board trace lengths from each pair of positive TPA0N L14 K13 and negative differential signal pins must be matched and as short as possible to the TPB0P M14 L13 external load resistors and to the cable connector. For an unused port, TPA+ and TPB0N N14 M13 TPA– can be left open.

TPA1P F14 E13 I/O Port 1 twisted-pair cable A differential. Board trace lengths from each pair of positive TPA1N G14 F13 and negative differential signal pins must be matched and as short as possible to the TPB1P H14 G13 external load resistors and to the cable connector. For an unused port, TPA+ and TPB1N J14 H13 TPA– can be left open.

TPA2P B14 A13 I/O Port 2 twisted-pair cable A differential. Board trace lengths from each pair of positive TPA2N C14 B13 and negative differential signal pins must be matched and as short as possible to the TPB2P D14 C13 external load resistors and to the cable connector. For an unused port, TPA+ and TPB2N E14 D13 TPA– can be left open.

TPBIAS0 K13 J12 O Twisted-pair bias. These terminals provide the 1.86-V nominal bias voltage needed TPBIAS1 G13 E12 for proper operation of the twisted-pair cable drivers and receivers, and for signaling TPBIAS2 E13 A12 to the remote nodes that there is an active cable connection in IEEE Std 1394a-2000

PCLK_L G01 F03 I PHY-section clock. This terminal must be connected to the PCLK_P output of the

PCLK_P F01 F02 O PHY-section clock. This terminal must be connected to the PCLK_L input of the LLC

LCLK_L G02 G03 O LLC-section clock. This terminal must be connected to the LCLK_P input terminal of

LCLK_P H02 G02 I LLC-section clock. This terminal must be connected to the LCLK_L output terminal of

LPS_L C01 C03 O LLC-section power status. This terminal must be connected to the LPS_P input

LPS_P C02 D03 I Link power status. This terminal must be connected to the LPS_L ouput terminal of

PINT_L D02 E02 I PHY-section interrupt. The PHY section uses this signal to transfer status and

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incoming bias voltage. If it is not used, this terminal should be left unconnected.

400-kΩ resistor. This circuit drives an internal comparator that detects the presence of cable power. If CPS is not used to detect cable power, this terminal must be connected to V

programming terminal. On hardware reset, this terminal allows the user to select whether port 0 acts like an IEEE Std 1394b-2002 bilingual port (terminal at logic 0) or as an IEEE Std 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-kΩ or smaller resistor (to enable IEEE Std 1394b-2002 bilingual mode) or high through a 10-kΩ or smaller resistor (to enable IEEE Std 1394a-2000-only mode).

programming terminal. On hardware reset, this terminal allows the user to select whether port 1 acts like an IEEE Std 1394b-2002 bilingual port (terminal at logic 0) or as an IEEE Std 1394a-2000-only port (terminal at logic 1). Programming is accomplished by tying the terminal low through a 1-kΩ or smaller resistor (to enable IEEE Std 1394b-2002 bilingual mode) or high through a 10-kΩ or smaller resistor (to enable IEEE Std 1394a-2000-only mode).

or smaller resistor. Bus holders are built into these terminals.

6.34 kΩ ± 1% is required to meet the IEEE Std 1394-1995 output voltage limits.

mode. Each of these terminals, except for an unused port, must be decoupled with a 1-μF capacitor to ground. For the unused port, this terminal can be left unconnected.

PHY section.

section.

the PHY section.

the LLC section.

terminal of the PHY section.

the LLC section.

interrupt information serially to the LLC section. This terminal must be connected to the PINT_P output of the PHY section.

SSA

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Table 2-9. 1394 Terminals (continued)

BALL NO.

SIGNAL DESCRIPTION

PINT_P D03 E03 O PHY-section interrupt. PINT_P is a serial input to the LLC section from the PHY

LKON/DS2_P D01 D02 I/O Link-on notification. If port is to operate in DS mode or is unused then it is necessary

LINKON_L E01 C02 I/O Link-on notification. LINKON_L is an input to the LLC section from the PHY section

LREQ_L F02 D01 O LLC-section request. The LLC section uses this output to initiate a service request to

LREQ_P E02 E01 I LLC-section request. LREQ_P is a serial input from the LLC section to the PHY

PHY_RESET B04 A06 I Reset for the 1394 PHY logic CTL1 J01 G01 I/O Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the

CTL0 H01 F01 phase of operation of the PHY link interface. Upon a reset of the interface, this bus is

D0 J02 H01 I/O Data. D[7:0] comprise a bidirectional data bus that is used to carry 1394 packet data, D1 K02 H02 packet speed, and grant type information between the PHY and the link. Upon a D2 K01 J02 reset of the interface, this bus is driven by the PHY. When driven by the PHY, D3 L01 J01 information on D[7:0] is synchronous to PCLK. When driven by the link, information D4 L02 K02 on D[7:0] is synchronous to LCLK. If not implemented, these terminals should be left D5 L03 K01 unconnected. D6 M02 L01 D7 M03 M01

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section that is used to transfer status, register, interrupt, and other information to the link. Information encoded on PINT_P is synchronous to PCLK_P. This terminal must be connected to the PINT_L input of the LLC section.

to pull the terminal high through a 470-Ω or smaller resistor. This terminal must also be connected to the LINKON_L input terminal of the LLC section via a 1-kΩ series resistor. A bus holder is built into this terminal. If the port is to operate in bilingual mode then the terminal should be tied low via a 1-kΩ resistor and directly connected to the link's LINKON_L pin with no series termination. After hardware reset, this terminal is the link-on output, which notifies the LLC section or other power-up logic to power up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (eight PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance. The link-on output is activated if the LLC section is inactive (the LPS input inactive or the LCtrl bit cleared) and when any of the following occurs: a) The XIO2213B receives a link-on PHY packet addressed to this node. b) The PEI (port-event interrupt) register bit is 1. c) Any of the configuration-timeout interrupt (CTOI), cable-power-status interrupt (CPSI), or state-time-out interrupt (STOI) register bits are 1, and the resuming-port interrupt enable (RPIE) register bit also is 1. d) The PHY is power cycled and the power class is 0 through 4.

Once activated, the link-on output is active until the LLC section becomes active (both the LPS_L input active and the LCtrl bit set). The PHY section also deasserts the link-on output when a bus reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). In the case of power cycling, the LKON signal must stop after 167 ms if the previous conditions have not been met. Note: If an interrupt condition exists that otherwise causes the link-on output to be activated if the LLC section were inactive, the link-on output is activated when the LLC section subsequently becomes inactive.

that is used to provide notification that a link-on packet has been received or an event, such as a port connection, has occurred. This I/O only has meaning when LPS is disabled. This includes the D0 (uninitialized), D2, and D3 power states. If LINKON_L becomes active in the D0 (uninitialized), D2, or D3 power state, the XIO2213B device sets bit 15 (PME_STS) in the power-management control and status register in the PCI configuration space at offset 48h. This terminal must be connected to the LKON output terminal of the PHY section.

the PHY section.This terminal must be connected to the LREQ_P input of the PHY section.

section used to request packet transmissions, read and write PHY section registers, and to indicate the occurrence of certain link events that are relevant to the PHY section. Information encoded on LREQ_P is synchronous to LCLK_P.This terminal must be connected to the LREQ_L output of the LLC section.

driven by the PHY. When driven by the PHY, information on CTL[1:0] is synchronous to PCLK. When driven by the link, information on CTL[1:0] is synchronous to LCLK. If not implemented, these terminals should be left unconnected.

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Table 2-10. Reserved Terminals

BALL NO.

SIGNAL I/O TYPE DESCRIPTION

RSVD E12 F12 F13 K12 L12 L13 D11 E11 F12 J11 K10 K11 I/O Reserved, do not connect to external signals.

M11 M12 M13 N10 N11 N12 K12 L10 L11 L12 M05 M11

RSVD D12 D13 G12 M08 C10 D12 F11 M09 I Must be connected to VSS.

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N13 P03 P10 P11 M12 N11 N12 N13

Table 2-11. Miscellaneous Terminals

BALL NO.

SIGNAL DESCRIPTION

GPIO0 P01 M02 I/O General-purpose I/O 0. This terminal functions as a GPIO controlled by bit 0

GPIO1 N02 N01 I/O General-purpose I/O 1. This terminal functions as a GPIO controlled by bit 1

GPIO2 P02 L02 I/O General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2

GPIO3 N03 L04 I/O General-purpose I/O 3. This terminal functions as a GPIO controlled by bit 3

GPIO4 N04 M03 I/O General-purpose I/O 4. This terminal functions as a GPIO controlled by bit 4

GPIO5 P05 K04 I/O General-purpose I/O 5. This terminal functions as a GPIO controlled by bit 5

GPIO6 P06 M06 I/O General-purpose I/O 6. This terminal functions as a GPIO controlled by bit 6

GPIO7 N06 L05 I/O General-purpose I/O 7. This terminal functions as a GPIO controlled by bit 7

OHCI_PME P08 M08 O OHCI power-management event. This is an optional signal that can be used by a

CYCLEOUT N08 L09 O Cycle out. This terminal provides an 8-kHz cycle timer synchronization signal. If not

PD B03 B03 I Power down. A high on this terminal turns off all internal circuitry, except the cable-

GRST C13 C12 I Global power reset. This reset brings all of the XIO2213B internal link registers to

SCL J13 G12 I/O Serial-bus clock. This signal is used as a serial bus clock when a pullup is detected

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(GPIO0_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO1_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO2_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO3_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO4_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO5_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO6_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

(GPIO7_DIR) in the GPIO control register (see Section 4.60). Note: This terminal has an internal active pullup resistor.

device to request a change in the device or system power state. This signal must be enabled by software.

implemented, this terminal should be left unconnected.

active monitor circuits that control the CNA output. Asserting PD high also activates an internal pulldown to force a reset of the internal control logic. If PD is not used, this terminal must be connected to VSS.

their default states. This should be a one-time power-on reset. This terminal has hysteresis and an integrated pullup resistor.

on SDA or when the SBDETECT bit is set in the serial bus control and status register.

Note: This terminal has an internal active pullup resistor.

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Table 2-11. Miscellaneous Terminals (continued)

BALL NO.

SIGNAL DESCRIPTION

SDA H12 H11 I/O Serial-bus data. This signal is used as serial bus data when a pullup is detected on

BMODE A05 B06 I Beta mode. This terminal determines the PHY-section/LLC-section interface

TESTM B02 A03 I Test control. This input is used in the manufacturing test of the XIO2213B. For

VREG_PD A06 B07 I Voltage regulator power-down input. When asserted logic high, this pin will power-

SE P13 M10 I Test control. This input is used in the manufacturing test of the XIO2213B. For

SM P14 N10 I Test control. This input is used in the manufacturing test of the XIO2213B. For

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SDA or when the SBDETECT bit is set in the serial bus control and status register. Note: In serial-bus mode, an external pullup resistor is required to prevent the SDA

signal from floating.

connection protocol. When logic high (asserted), the PHY-section/LLC-section interface complies with the IEEE Std 1394b-2002 Revision 1.33 beta interface. When logic low (deasserted), the PHY-section/LLC-section interface complies with legacy IEEE Std 1394a-2000. This terminal must be pulled high with a 1-kΩ resistor during normal operation.

normal use, this terminal must be pulled high through a 1-kΩ resistor to VDD.

down the internal 3.3- to 1.95V regulator. For single 3.3V supply operation, this pin should be tied to GND. When using the internal regulator, the XIO2213B can support a maximum of 2-Beta and 1-DS connection simultaneously. If 3-Beta ports are required to be simultaneously supported, it is recommended to use an external

1.95V regulator.

normal use, this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND.

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+ 171 hidden pages

arTech PEX1394B3 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 XIO2213B Features

2 Overview

2.1 Related Documents

2.2 Documents Conventions

2.3 Ordering Information

2.4 Terminal Assignments

2.5 Terminal Descriptions