apple -macbook-pro-a1425_051-9216 Datasheet

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D

C

B

7

6 5 4 3

2 1

REV ECN

DESCRIPTION OF REVISION

CK
APPD

DATE

<REV> <ECN>

<ECO_DESCRIPTION>

<ECODATE>

SCHEM,MLB,D1

8/8/12

Page

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(.csa)

1

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

6

BOM Configuration

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU GROUNDS

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIe/CLK/LPC/SPI

19

PCH DMI/FDI/PM/Graphics

20

PCH PCI/USB/TP/RSVD

21

PCH GPIO/MISC/NCTF

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

Chipset Support

27

USB HUB & MUX

28

CPU Memory S3 Support

29

DDR3 SDRAM Bank A (Rank 0)

31

DDR3 SDRAM Bank B (Rank 0)

33

DDR3 Termination

34

DDR3/FRAMEBUF VREF MARGINING

35

ALS/CAMERA CONNECTOR

36

Thunderbolt Host (1 of 2)

37

Thunderbolt Host (2 of 2)

38

Thunderbolt Power Support

44

RIO CONNECTORS

45

SSD/HDD Connectors

46

USB 3.0 CONNECTORS

49

50

SMC Support

51

LPC+SPI Debug Connector

52

SMBus Connections

53

Power Sensor: Load Side

54

Power Sensor: High Side

55

Thermal Sensors

Contents

Sync

MASTER

MASTER

K17_REF

MASTER

MASTER

MASTER

MASTER

MASTER

D1_MLB_TEST

J30_MLB

J30_MLB

J30_MLB

J30_MLB

J30_MLB

MASTER

MASTER

J13_MLB

J13_MLB

J13_MLB

J13_MLB

J13_MLB

J13_MLB

J13_MLB

J30_MLB

MASTER

J5_AMD

J5_MLB

J5_MLB

J5_MLB

MASTER

J5_MLB

MASTER

J5_MLB_KEPLER

J5_MLB_KEPLER

J5_MLB_KEPLER

MASTER

MASTER

J5_AMD

D1_SENSORS

D1_SENSORS

D1_SENSORS

MASTER

D1_SENSORS

D1_SENSORS

D1_SENSORS

Date

MASTER

02/15/2011

06/30/2009

MASTER

MASTER

MASTER

MASTER

MASTER

01/27/2012

07/14/2011

07/14/2011

07/14/2011

07/14/2011

07/14/2011

MASTER

MASTER

09/15/2011

09/15/2011

09/15/2011

09/15/2011

09/15/2011

09/15/2011

09/15/2011

07/14/2011

MASTER

08/17/2011

07/29/2011

07/14/2011

07/14/2011

MASTER

07/29/2011

MASTER

11/14/2011

11/14/2011

11/14/2011

MASTER

MASTER

08/24/2011

02/20/2012

02/20/2012

02/20/2012

MASTER

02/20/2012

02/20/2012

02/20/2012

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

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46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

(.csa)

56

Fan Connectors

57

KEYBOARD/TRACKPAD (1 OF 2)

58

KEYBOARD/TRACKPAD (2 OF 2)

59

DIGITAL ACCELEROMETER & GYRO

61

SPI ROM

62

AUDIO: CODEC/REGULATOR

63

AUDIO: HEADPHONE FILTER

66

AUDIO: SPEAKER AMP

67

AUDIO: JACK

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPUVCCIO (1.05V) Power Supply

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

90

eDP Display Connector

92

DDC Crossbar

94

Thunderbolt Connector A

96

Thunderbolt Connector B

97

LCD Backlight Driver (LP8545)

100

CPU Constraints

101

Memory Constraints

102

PCH Constraints 1

103

PCH Constraints 2

105

Thunderbolt Constraints

106

SMC Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

132

Power Sensors: Extended

Contents

J5_MLB

D2_MLB_KEPLER

D2_MLB_KEPLER

J5_MLB

J13_MLB

D1_AUDIO

D1_AUDIO

D1_AUDIO

D1_AUDIO

D1_AUDIO

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

D1_SENSORS

MASTER

J5_MLB_KEPLER

J5_MLB_KEPLER

J5_MLB_KEPLER

J5_MLB

J5_MLB

J5_MLB_KEPLER

J5_MLB

T29_CR

J5_MLB

J5_MLB

J5_MLB

D1_SENSORS

Sync

Date

07/29/2011

12/08/2011

12/08/2011

07/29/2011

01/20/2012

06/06/2012

06/06/2012

06/06/2012

06/06/2012

06/06/2012

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

07/11/2012

MASTER

11/14/2011

11/14/2011

09/21/2011

09/13/2011

09/13/2011

09/21/2011

07/29/2011

08/31/2011

07/29/2011

07/29/2011

07/29/2011

07/11/2012

D

C

B

A

Schematic / PCB #’s

PART NUMBER

820-3462

DRAWING

TITLE=MLB
ABBREV=ABBREV

LAST_MODIFIED=Thu Aug 9 12:34:09 2012

QTY

1 SCH

DESCRIPTION

SCHEM,MLB,D1

PCBF,MLB(NEW),D1

REFERENCE DES

PCB1

CRITICAL

CRITICAL051-9216

CRITICAL

BOM OPTION

SIZE

A

D

DRAWING TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

3

SCHEM,MLB,D1

Apple Inc.

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

1 OF 132

SHEET

1 OF 80

1245678

8 7 6 5 4 3

J2500

XDP CONN

U1000

PG 23

12

J3502

U3100-U3170

Mem

CAMERA

PG 31

PG 28

U6100

SPI

Boot ROM

PG 49

J4410

RIO CONN

Bluetooth

PG 35

1 2 3

U2700

USB
HUB

PG 25

U4900

I2C Ser

U5701

TP/KB

PSOC

PG 46 PG 46

From PCH

SMC

PG 38

J5700, J5713

U4900

U2760

EHCI
XHCI

J2550

Fan

ADCSMS

Prt

TRACKPAD/

KEYBOARD

SMC

PG 38

USB
MUX

PG 25

PCH XDP

J6900, J6950

DC/BATT

PG 55

U5550,U5570

TEMP SENSOR

PG 47

U5920,U5940

Motion Sensor/GYRO

U5340,U5350,U5360,U5370,U5400,U5410,Q5480
Q5490

J5650,J5660

FAN CONN AND CONTROL

PG 48

POWER SENSE

PG 42, 43

PG 45

J5100

SPI

Port80,serial

J4410

RIO CONN

USB 3

PG 35

J4600

EXTERNAL A

USB 3

PG37

LPC+SPI Conn

PG 40

D

POWER SUPPLY

PG 56-65

C

B

INTEL CPU

2.X GHz

IVY BRIDGE 2C-35W

PG 9-15

D

U2600

SYSTEM

CLOCK

PG 24

GPIO

PG 19

CLK

BUFFER

PG 16

FDI

PG 17

DMI

PG 17

DDR3-1333/1600MHZ

U2900-U2970

Mem

PG 27

RTC

PG 16

MISC

PG 19

SPI

U4510

SATA

REDRIVER

PG 36

C

U9420

J9400

DP/TBT

PORT

CONN

PG 68,69

PortA

PortB

MUX

PG 68

U9620

U3600

CIO

TBT Host

CIO

PG 32,33

PCIe x4

DP

J4500

SATA
CONN

HDD

PG 36

MUX

PG 69

J9000

eDP

CONN

PG 66

J4410

RIO CONN

B

HDMI

PG 35

1.05V/6GHZ.
0

SATA

PG 16

LVDS OUT

RGB OUT

DP OUT

DVI OUT

TMDS OUT

PG 17

eDP OUT

PG 17

PCI

PG 18

HDMI

PG 17

JTAG

PG 16

PEG

PG 16

INTEL

PANTHER POINT-MPCH

U1800

PG 16-21

PCI-E

(UP TO 8 LINES)

PG 16

2 1

PG 16

LPC

PG 16

PWR

CTRL

PG 17

13
12
1110

98

USB

PG 18

4
3 5

(UP TO 14 DEVICES)

1 2
0 76

4
32

PG 18

1

USB 3

SMBUS

PG 16

HDA

PG 16

CONN

PG 23

U6201

EXTMIC LINEIN HPOUT SPDIF MICIN LINEOUT

J4410

AUDIO
Codec

PG 50

RIO CONN

J6802
J6803

PG 54

U6610,U6620
U6630,U6640

SPEAKER

AMPs

PG 52

SYNC_MASTER=MASTER

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

2 OF 132

SHEET

2 OF 80

124578

SIZE

A

D

Airport/SD Card

PG 35

A

U6750

MIC BIAS

PG53

J6701

PG 53

AUDIO
CONNs

J5815
PG 47

6 3

8 7 6 5 4 3

12

D1 POWER SYSTEM ARCHITECTURE

PPDCIN_G3H

P5V1_VIN

D

J6900

AC

ADAPTER

IN

DCIN(16.5V)

F6905
6A FUSE

R7020

A

SMC_DCIN_ISENSE

SMC_RESET_L

ENABLE

LT3470A

U7090

(PAGE 56)

VIN

PBUS SUPPLY/

BATTERY CHARGER

PP5V1_CHGR_VDDP

U7000

ISL6259

R6920

VOUT

PPVBAT_G3H

R7050

SMC_BATT_ISENSE

(PAGE 56)

J6950

PPVBATT_G3H_CONN

3S2P

(9 TO 12.6V)

Q7055

CHGR_BGATE

PPVBAT_G3H_CHGR_R

PPDCIN_S5_P3V42G3H

F7040

A

www.qdzbwx.com

PPBUS_G3H

C

SMC

U4900

(PAGE 38)

Panther-POINT

(PCH)

(PAGE 16~21)

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

U1800

SLP_S3#(D4)

PVCCSA_EN

CPUVCCIOS0_EN

P1V8S0_EN

P1V5S0_EN

B

A

P60

SMC_S4_WAKESRC_EN

SLP_S5#(F6)

SLP_S4#(K10)

PG67

PG67

PG67

SMC_PM_G2_EN

PM_SLP_S5_L

PG67

RC

DELAY

PG 17

DDRREG_EN

RC

DELAY

P5VS3_EN

RC

DELAY

P3V3S3_EN

RC

DELAY

P1V2S3_EN

RC

DELAY

TPAD_VBUS_EN

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

R7978

PG65

PM_SLP_S3_R_L

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

TBT_S0_EN

P3V3S5_EN

74LVG1G32

U7970

(PAGE 65)

PG67

PG 17

PG 17

TBTAPWRSW_EN
TBTBPWRSW_EN
P3V3S4_EN

P5VS4_EN

PG59

PG64

PG64

PG46

F9700

LCD_BKLT_EN

&&

BKLT_PLT_RST_L

PPBUS_S0_LCDBKLT_PWR

Q4260

PP3V3_S0 && FWPORT_PWR_EN

T29_A_HV_EN

Q9706

EN

Q3880

R5430

A

VIN

LP8545SQX-EXTJ

U9701

(PAGE 70)

PPBUS_S5_HS_OTHER_ISNS

P5V3V3S4_EN

P3V3S5_EN

PPVOUT_S0_LCDBKLT

VOUT

F4260

VIN

LT3957

U3890

VOUT

(PAGE 34)

EN1

EN2

PPVP_FW

PP15V_TBT_REG

VIN

TPS51980

U7201

(PAGE 60)

5V

(L/H)

3.3V

(R/H)

PGOOD

P5V3V3_PGOOD

VREG5

VOUT1

VOUT2

Q5720

SLG5AP020

VCC

(PAGE 64)

U7801

6 3

D6905

PP5V_S5RS4_CUMUUS

P5VS4_EN

P1V5CPU_EN

ON

P1V5_CPU_EN

PPVIN_S3_P1V5S3RS0_FET

PP5V_S4

PP3V3_S5

SMC_PBUS_VSENSE

V

P1V5S3RS0FET_GATE

PP3V3_S5

Q7800

P3V3_S4_EN

Q7840

Q7810

Q7830

Q7850

P5VS3_EN

Q7820

P3V3_SUS_EN

PP3V3_S4_FET

P5VSUS_EN

P3V3S3_EN

PP3V3_S0_FET

P3V3_S0_EN

PP5VS3_FET

PP3V3_SUS_FET

PP5V_S0

CPUVCCIOS0_EN

CPUIMVP_VR_ON

DDRREG_EN

MEMVTT_EN

PP5V_S0

PVCCSA_EN

Q7801

PP1V5_S3RS0_FET

PP5V_SUS_FET

PP3V3_S3

PP3V3_S0_P1V8S0

P1V8_S0_EN

ENABLE

3.425V G3HOT

LT3470A

U6990

(PAGE 55)

1.05V

VCC

ISL95874

U7600

EN

(PAGE 62)

CPU VCORE

VIN

MAX15119GTM

U7400

VR_ON

(PAGE 60)

VIN

1.5V

S5

S3

0.75V

TPS51916

U7300

(PAGE 59)

VCC

ISL95875

U7100

EN

(PAGE 57)

Q7850

Q7860

P5V_S0_EN

PP5V_S4_1V05BTS0

TBT_EN_LC_ISOL

PP3V3_S0_P1V5S0

P1V5_S0_EN

IN

MAX15053EWL

EN

U7760

(PAGE 63)

PP3V3_SUS_P1V05SUSLDO

EN

VOUT

CPUVCCIOS0_PGOOD

PGOOD

VOUT

VOUT

IMON

IMONG
PGOOD
PGOODG

VLDOIN

VOUT1

VOUT2

PGOOD

VOUT

PGOOD

P5V_S3_EN

VIN

ISL8014A

EN

U7720

(PAGE 63)

ISL8009B

EN

U7770

(PAGE 63)

PP1V8_S0_REG

IN

TPS720105

U7740

(PAGE 63)

PP3V42_G3H

R7640

SMC_CPU_ISENSE

A

SMC_CPU_ISENSE

A

CPUIMVP_IMON

CPUIMVP_IMONG

CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD

PP1V5R1V35_S3

PP0V75_S0_DDRVTT

TP_DDRREG_PGOOD

PPVCCSA_S0_REG

PVCCSA_PGOOD

PP5V_S0_FET

PP1V05_S0_P1V05BTREG_R

VIN

PP1V5_S0_REG

PP1V05_SUS_LDO

PP1V05_S0

A

SMC_CPU_FSB_ISENSE

V

PP5V_S3_FET

PP5V_S0_VMON

PP1V5_S3RS0_VMON

PP1V05_S0_VMON

SMC_CPU_VSENSE

V

PPVCORE_S0_CPUPPVCORE_S0_CPU

SMC_CPU_VSENSE

PPVCORE_S0_AXG

SMC_GFX_VSENSE

CPUIMVP_AXG_PWM2

SMC PWRGD

SN0903048

(PAGE 39)

VDD

MAX17491

PWN

U7542

(PAGE 61)

P1V5S0_PGOOD

P1V8S0_PGOOD
P5VS4_PGOOD

PVCCSA_PGOOD

CPUVCCIOS0_PGOOD

PP3V3_S0

VMON_Q2

VMON_Q3

VMON_Q4

U5010

PP5V_S0_CPUIMVP

2

U7960

ISL88042IRTEZ

(PAGE 67)

SMC_RESET_L

A

ALL_SYS_PWRGD

8

V

PPVCORE_S0_AXG

ALL_SYS_PWRGD

SMC_ONOFF_L

R7962

Panther-POINT

(PCH)

U1800

PM_PCH_PWROK

U7950

(PAGE 16~21)

CPU

U1000

SM_DRAMPWROK

UNCOREPWRGOOD

(PAGE 9~13)

SMC

PWRGD(P38)

S5_PWRGD

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

RSMRST_IN(P38)

PWR_BUTTON(P90)

SLP_S5_L(P38)

SLP_S4_L(P38)

SLP_S3_L(P38)

(PAGE 38)

SYNC_MASTER=K17_REF

PAGE TITLE

U4900

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PWRBTN#

SYS_RERST#

RSMRST#

PLTRST#

PROCPWRGD

DRAMPWROK

RESET*

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

SYSRST(PA2)

P17(BTN_OUT)

RES*

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PLT_RERST_L

CPU_PWRGD

PM_MEM_PWRGD

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

SYNC_DATE=06/30/2009

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

3 OF 132

SHEET

3 OF 80

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=MASTER

PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

4 OF 132

SHEET

4 OF 80

124578

BOM Variants

BOM NUMBER

085-4094

607-9189

639-3288

639-3289

639-3290

639-3291

D

C

639-3694

639-3695

639-3696

639-3697

639-3773

639-3772

639-3770

639-3771

639-3849

639-3848

639-3873

639-3874

639-3875

639-3876

639-3881

639-3882

639-3884

639-3883

639-3877

639-3878

639-3885

639-3886

639-3879

639-3880

639-3846

639-3847

639-3887

639-3888

Module Parts

PART NUMBER

B

A

8 7 6 5 4 3

Bar Code Labels / EEE #’s

BOM NAME

DEV BOM,MLB,D1

CMN PTS,PCBA,MLB,D1

PCBA,2.5G,SS 6GB,MLB,D1

PCBA,2.9G,SS 6GB,MLB,D1

PCBA,2.5G,HYNIX 6GB,MLB,D1

PCBA,2.9G,HYNIX 6GB,MLB,D1

PCBA,2.5G,SS 8GB,MLB,D1

PCBA,2.9G,SS 8GB,MLB,D1

PCBA,2.9G,HYNIX 8GB,MLB,D1

PCBA,2.5G,HYNIX 8GB,MLB,D1

PCBA,2.5G,ELPIDA 6GB,MLB,D1

PCBA,2.9G,ELPIDA 6GB,MLB,D1

PCBA,2.5G,ELPIDA 8GB,MLB,D1

PCBA,2.9G,ELPIDA 8GB,MLB,D1

PCBA,2.5G,MICRON 6GB,MLB,D1

PCBA,2.9G,MICRON 6GB,MLB,D1

PCBA,2.6G,SS 6GB,MLB,D1

PCBA,2.8G,SS 6GB,MLB,D1

PCBA,2.6G,HYNIX 6GB,MLB,D1

PCBA,2.8G,HYNIX 6GB,MLB,D1

PCBA,2.6G,SS 8GB,MLB,D1

PCBA,2.8G,SS 8GB,MLB,D1

PCBA,2.8G,HYNIX 8GB,MLB,D1

PCBA,2.6G,HYNIX 8GB,MLB,D1

PCBA,2.6G,ELPIDA 6GB,MLB,D1

PCBA,2.8G,ELPIDA 6GB,MLB,D1

PCBA,2.6G,ELPIDA 8GB,MLB,D1

PCBA,2.8G,ELPIDA 8GB,MLB,D1

PCBA,2.6G,MICRON 6GB,MLB,D1

PCBA,2.8G,MICRON 6GB,MLB,D1

PCBA,2.5G,MICRON 8GB,MLB,D1

PCBA,2.9G,MICRON 8GB,MLB,D1

PCBA,2.6G,MICRON 8GB,MLB,D1

PCBA,2.8G,MICRON 8GB,MLB,D1

BOM OPTIONS

D1_DEVEL:PVB

D1_COMMON

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:DWP2,RAM_6G_SAMSUNG_35NM_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:DWNY,RAM_6G_SAMSUNG_35NM_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:DWP0,RAM_6G_HYNIX_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:DWNW,RAM_6G_HYNIX_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16P,RAM_4G_SAMSUNG_35NM_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F16M,RAM_4G_SAMSUNG_35NM_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F16N,RAM_4G_HYNIX_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16V,RAM_4G_HYNIX_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F26M,RAM_6G_ELPIDA_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F26J,RAM_6G_ELPIDA_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F26L,RAM_4G_ELPIDA_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F26H,RAM_4G_ELPIDA_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F2WT,RAM_6G_MICRON_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F2WR,RAM_6G_MICRON_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33H,RAM_6G_SAMSUNG_35NM_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33P,RAM_6G_SAMSUNG_35NM_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33L,RAM_6G_HYNIX_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F339,RAM_6G_HYNIX_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33G,RAM_4G_SAMSUNG_35NM_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33C,RAM_4G_SAMSUNG_35NM_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F337,RAM_4G_HYNIX_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33D,RAM_4G_HYNIX_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33Q,RAM_6G_ELPIDA_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F338,RAM_6G_ELPIDA_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33J,RAM_4G_ELPIDA_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33N,RAM_4G_ELPIDA_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33M,RAM_6G_MICRON_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F336,RAM_6G_MICRON_CH0_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F2WV,RAM_4G_MICRON_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F2WQ,RAM_4G_MICRON_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33K,RAM_4G_MICRON_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33F,RAM_4G_MICRON_1600_S

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

PART NUMBER

QTY

1

826-4393

826-4393

826-4393

826-4393

826-4393 CRITICAL

826-4393 CRITICAL

826-4393

826-4393

826-4393

826-4393

826-4393

826-4393 CRITICAL

826-4393

826-4393

826-4393 CRITICAL

826-4393

826-4393

826-4393

826-4393

826-4393

826-4393

826-4393 CRITICAL

826-4393

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

826-4393

826-4393

826-4393

826-4393 CRITICAL

1

1

1

1

1

826-4393 CRITICAL

826-4393

1

1

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

REFERENCE DES

[EEEE:DV7Q]

[EEEE:DWNY]

[EEEE:DWNW]

[EEEE:DWP0]

[EEEE:DWP2]

[EEEE:F16M]

[EEEE:F16N]

[EEEE:F16P]

[EEEE:F16V]

[EEEE:F26H]

[EEEE:F26J]

[EEEE:F26L]

[EEEE:F26M]

[EEEE:F2WQ]

[EEEE:F2WR]

[EEEE:F2WT]

[EEEE:F2WV]

[EEEE:F336]

[EEEE:F337]

[EEEE:F338]

[EEEE:F339]

[EEEE:F33C]

[EEEE:F33D]

[EEEE:F33F]

[EEEE:F33G]

[EEEE:F33H]

[EEEE:F33J]

[EEEE:F33K]

[EEEE:F33L]

[EEEE:F33M]

[EEEE:F33N]

[EEEE:F33P]

[EEEE:F33Q]

D1 BOM GROUPS

QTY

337S4181

337S4182

337S4292

337S4300

337S4302

337S4294

337S4264

337S4265

337S4180 CRITICAL

337S4283

338S1113

333S0623

333S0622

333S0628

333S0625

333S0629

333S0624

333S0623

333S0624

333S0622

333S0625

333S0628

333S0629

333S0660

333S0649 CRITICAL

1

1

1

1

1

1

1

1

1

1

1

1

1

1

16

16

16

16

16

16

16

8

8

8

8

8

8

16

8

8

DESCRIPTION

IVB,QBP0,ES2,K0,2.3,35W,2+2,1.0,3M,BGA

IVB,QBP0,ES2,K0,2.6,35W,2+2,1.05,4M,BGA

IVB,Q4CT,QS,L1,2.5,35W,2+2,1.1,3M,BGA

IVB,QC96,QS,L1,2.6,35W,2+2,1.2,3M,BGA

IVB,QC94,QS,L1,2.8,35W,2+2,1.2,3M,BGA

IVB,QC4M,QS,L1,2.9,35W,2+2,1.25,4M,BGA

IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA

IVB,S R0MY,PRQ,L1,2.6,35W,2+2,1.2,3M,BGA

IVB,S R0MU,PRQ,L1,2.8,35W,2+2,1.2,3M,BGA

IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA

IC,PCH,PPT-MB SFF,ES2,B0

IC,PCH,PPT-MB SFF,P-QS,C0

IC,PCH,PPT-MB SFF,PRQ,C1

IC,TBT,CR-4C,B1,PRQ,288FCBGA,12X12MM

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON

IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON

IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON

REFERENCE DES

U1000

U1000

U1000

U1000

U1000

U1000

U1000

U1000

U1000

U1000

U1800

U1800

U1800

U3600

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL337S4338

CRITICAL337S4339

CRITICAL

CRITICAL337S4235

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL333S0649

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL333S0660

BOM OPTION

CPU_IVB_2C_2.3G_ES2

CPU_IVB_2C_2.6G_ES2

CPU_IVB_2C_2.5G_QS

CPU_IVB_2C_2.6G_QS

CPU_IVB_2C_2.8G_QS

CPU_IVB_2C_2.9G_QS

CPU_IVB_2C_2.5G

CPU_IVB_2C_2.6G

CPU_IVB_2C_2.8G

CPU_IVB_2C_2.9G

PCH_ES2

PCH_C0

PCH_C1

TBTRTR:B1

2G_SAMSUNG_35NM_1600_S

2G_HYNIX_1600_S

2G_ELPIDA_1600_S

2G_MICRON_1600_S

4G_HYNIX_1600_S

4G_ELPIDA_1600_S

4G_SAMSUNG_35NM_1600_S

6G_SAMSUNG_35NM_CH0_1600_S

6G_SAMSUNG_35NM_CH0_1600_S

6G_HYNIX_CH0_1600_S

6G_HYNIX_CH0_1600_S

6G_ELPIDA_CH0_1600_S

6G_ELPIDA_CH0_1600_S

4G_MICRON_1600_S

6G_MICRON_CH0_1600_S

6G_MICRON_CH0_1600_S

BOM GROUP

D1_COMMON

D1_COMMON1

D1_COMMON2

D1_PVB

D1_PROGPARTS

D1_BLANK

D1_DEVEL:ENG

D1_DEVEL:PVB

IVB_PPT_XDP

DDR3 SPD STRAPPINGS

BOM GROUP

RAM_4G_HYNIX_1600_S

RAM_2G_ELPIDA_1600_S

RAM_4G_SAMSUNG_28NM_1600_S

RAM_2G_MICRON_1600_S

RAM_4G_ELPIDA_1600_S

RAM_4G_SAMSUNG_35NM_1600_S

RAM_6G_SAMSUNG_35NM_CH0_1600_S

RAM_4G_MICRON_1600_S

RAM_6G_MICRON_CH0_1600_S

RAM_6G_ELPIDA_CH0_1600_S

RAM_6G_SAMSUNG_28NM_CH0_1600_S

RAM_6G_HYNIX_CH0_1600_S

RAM_2G_SAMSUNG_1600_S

RAM_2G_HYNIX_1600_S

Module Parts

PART NUMBER

333S0642

333S0623

333S0642

QTY

16

8

8

CPUMEM:S0,SMC_DEBUG_YES,TBTBST:Y,TBTRTR:B1,TBTHV:P15V,HUB_2NONREM,USBHUB:2512B,AXG_PHASE2,TBTISNS:YES

EDP:YES,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,CAPS:INT,BTPWR:S4,SKIP_5V3V3:AUDIBLE,TPAD_5V_LDO:S5,SMS

DESCRIPTION

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

BOM OPTIONS

ALTERNATE,COMMON,D1_COMMON1,D1_COMMON2,D1_PROGPARTS,D1_PVB

LOADISNS:NO,LCDBKLT:PROD,KBDBKLT:PROD

SMC_PROG:PVB,TBTROM:PROG,BOOTROM_PROG:PVB,TPAD_PSOC:PROG

ALTERNATE,IVB_PPT_XDP,LOADISNS:YES,S0PGOOD_ISL,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC

ALTERNATE,IVB_PPT_XDP,VREFDQ:M1_M3,VREFCA:LDO

XDP,XDP_CONN,XDP_CPU:BPM,XDP_PCH

BOM OPTIONS

4G_HYNIX_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

2G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

4G_SAMSUNG_28NM_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

2G_MICRON_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
4G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

4G_SAMSUNG_35NM_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

6G_SAMSUNG_35NM_CH0_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

4G_MICRON_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
6G_MICRON_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
6G_ELPIDA_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

6G_SAMSUNG_28NM_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

6G_HYNIX_CH0_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

2G_SAMSUNG_35NM_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

2G_HYNIX_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

REFERENCE DES

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

4G_SAMSUNG_28NM_1600_S

6G_SAMSUNG_28NM_CH0_1600_S

6G_SAMSUNG_28NM_CH0_1600_S

6 3

CRITICAL

CRITICAL826-4393

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL826-4393

CRITICAL826-4393

CRITICAL

CRITICAL

CRITICAL

CRITICAL826-4393

CRITICAL

BOM OPTION

EEEE:DV7Q

EEEE:DWNY

EEEE:DWNW

EEEE:DWP0

EEEE:DWP2

EEEE:F16M

EEEE:F16N

EEEE:F16P

EEEE:F16V

EEEE:F26H

EEEE:F26J

EEEE:F26L

EEEE:F26M

EEEE:F2WQ

EEEE:F2WR

EEEE:F2WT

EEEE:F2WV

EEEE:F336

EEEE:F337

EEEE:F338

EEEE:F339

EEEE:F33C

EEEE:F33D

EEEE:F33F

EEEE:F33G

EEEE:F33H

EEEE:F33J

EEEE:F33K

EEEE:F33L

EEEE:F33M

EEEE:F33N

EEEE:F33P

EEEE:F33Q

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Alternate Parts

PART NUMBER

128S0303

376S0953 376S0958

128S0311 128S0329

353S3237

376S0977

138S0722 138S0691

197S0487

197S0478

197S0481

376S0972

376S1053

138S0681 138S0638

152S1703

371S0730

138S0725 138S0724

372S0186 372S0185

128S0363

376S0903

740S0144

152S1539

152S1645 152S0461

103S0305

376S1113 376S1110

ALTERNATE FOR
PART NUMBER

BOM OPTION

128S0264128S0364

128S0353

353S2192

376S0859

197S0485

197S0485197S0484

197S0486197S0479

197S0486

197S0480

376S0612

376S0604

376S0612376S1017

138S0677138S0624

152S1701

371S0490

138S0709138S0727

376S0820376S1080

128S0296

376S0796

740S0118

152S1598

155S0583155S0667

103S0266

112S0254112S0274

155S0367155S0588

SYNC_MASTER=MASTER

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

REF DES

COMMENTS:

ALL

Kemet alt to Sanyo

Panasonic alt to Sanyo

ALL

ALL

RENESAS ALT TO FAIRCHILD

ALL

NEC ALT TO SANYO

TI ALT TO INTERSIL

ALL

ALL

Diodes alt to Toshiba

ALL

Multi alt to Samsung

Epson alt to TXC

ALL

NDK alt to TXC

ALL

Epson alt to TXC

ALL

ALL

NDK alt to TXC

ALL

Epson alt to NDK

ROHM alt to Toshiba

ALL

ALL

Diodes alt to Fairchild

ALL

ROHM alt to Toshiba

ALL

Murata alt to Taiyo Yuden

ALL

Taiyo Yuden alt to Samsung

Sumida alt to Cyntec

ALL

ALL

Diodes alt to NXP

ALL

Samsung alt to Murata

ALL

Samsung alt to Murata

ALL

Diodes alt to ON Semi

ALL

NXP alt to Diodes

ALL

NEC alt to Sanyo

ALL

Fairchild alt to Siliconix

ALL

Littlefuse alt to Polytronic

ALL

Cyntec alt to Toko

Cyntec alt to Vishay

ALL

ALL MAG LAYERS ALT TO MURATA

Yageo alt to Cyntec

ALL

Yageo alt to Cyntec

ALL

ALL

Diodes to AOS

ALL

murata ALT TO MURATA

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

PAGE

SHEET

124578

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

SYNC_DATE=MASTER

<BRANCH>
5 OF 132

5 OF 80

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

D

C

PD Module Parts

PART NUMBER

QTY

1

1

1

825-7841 CONFIG_LABEL

946-4350

1

1

DESCRIPTION

STDOFF,BMU,TOPSIDE,D1,SM

STDOFF-1.9D2.93H-TH-0.85-1.2

STDOFF-1.80D1.53H-SM

LBL,PART CONFIG,BOARDS,D2

D1 MLB LOCTITE UV GLUE 190024/S 0.24G

REFERENCE DES

J6950_63860-1533

J6950_64860-1530 CRITICAL

J6950_65860-1529

EDGE_BOND

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

DEVELOPMENT/BASE BOMs

PART NUMBER

085-4094

B

607-9189

QTY

1

1

DESCRIPTION

D1 MLB DEVELOPMENT BOM

D1 MLB BASE BOM

SMC

341S3528

341S3404

341S3405

341S3406

1

1

1

1

IC,SMC12,PROTO1,D1

IC,SMC,DEVELOPMENT-PIB,D1

IC,SMC,DEVELOPMENT-FSB,D1

IC,SMC,DEVELOPMENT-PVB,D1

EFI ROM

341S3571

341S3603

341S3636

341S3650

341SXXXX

341S3667

1

1

1

1

1

1

IC,EF,ROM,PROTO1,D1

IC,EFI,ROM,PIB, D1

IC,EFI,ROM,PIB2, D1

IC,EFI,ROM,FSB, D1

IC,EFI,ROM,FSB2, D1

IC,EFI,ROM,PVB, D1

REFERENCE DES

DEVEL

BASE BASE_BOMCRITICAL

U4900

U4900

U4900

U4900

U6100

U6100

U6100

U6100

U6100

U6100

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

DEVEL_BOM

B

SMC_PROG:PROTO

SMC_PROG:PIB

SMC_PROG:FSB

SMC_PROG:PVB

BOOTROM_PROG:PROTO

BOOTROM_PROG:PIB

BOOTROM_PROG:PIB2

BOOTROM_PROG:FSB

BOOTROM_PROG:FSB2

BOOTROM_PROG:PVB

Programmables - All builds

335S0809

A

335S0803

341S3670

337S2983

341S3668

335S0865 CRITICAL

338S1098

998-3919 CRITICAL

1

1

1

1

1

1

1

1

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx

IC,TP PSOC,V224,PVB,D1

IC,TP PSOC,QFN,BLANK

IC,EEPROM,CR,V14.1,D1 PVB

IC,EEPROM,SERIAL,8KB,SOIC

IC,SMC12-A3,LX4FS1AH5BBCIGA3

SOCKET, SMC12

U6100

U6100

U5701

U5701

U3690

U3690

U4900

J4900

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

BOOTROM_BLANK

BOOTROM_BLANK

TPAD_PSOC:PROG

TPAD_PSOC:BLANK

TBTROM:PROG

TBTROM:BLANK

SMC_BLANK

SMC_SOCKET

6 3

SYNC_MASTER=MASTER

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

6 OF 132

SHEET

6 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

J5713 (KEY BOARD CONN)

PP3V3_S4

Functional Test Points

J5650 (LEFT FAN CONN)

FUNC_TEST

TRUE

TRUE
TRUE

PP5V_S0
FAN_LT_PWM

FAN_LT_TACH

J5660 (RIGHT FAN CONN)

TRUE

D

TRUE
TRUE

TRUE

I1503

TRUE

I1502

TRUE

I1504

J4400 (RIO CABLE CONN)

TRUE

I1531

TRUE

I1534

TRUE

I1533

TRUE

I1535

TRUE

I1538

FAN_RT_PWM
FAN_RT_TACH
GND

J3502 (ALS/CAMERA CONN)

SMBUS_SMC_2_S3_SDA
SMBUS_SMC_2_S3_SCL

PP5V_S3_ALSCAMERA_F

PP3V3_S4
PP3V3_S3
PP3V3_WLAN_F
PP5V_S4
PP1V5_S0

J4410 (RIO FLEX CONN)

I1512

I1511

I1513

I1515

I1514

I1517

I1516

I1518

I1519

I1520

C

I1522

I1521

I1523

I1524

I1525

I1526

I1527

I1529

I1528

I1536

I1540

I1541

I1544

I1630

I1493

B

I1818

I1817

HDMI_IG_DDC_CLK

TRUE

HDMI_IG_DDC_DATA

TRUE

HDMI_HPD_L

TRUE

PM_SLP_S3_L

TRUE

PM_SLP_S4_L

TRUE

AP_CLKREQ_Q_L

TRUE

ENET_RESET_L

TRUE

ENET_CLKREQ_L

TRUE

SD_PWR_EN

TRUE

SDCONN_STATE_CHANGE_SMC

TRUE

PCIE_WAKE_L

TRUE

AP_CLKREQ_Q_L

TRUE

AP_RESET_CONN_L

TRUE

WIFI_EVENT_L

TRUE

USB_EXTB_P

TRUE

USB_EXTB_N

TRUE

USB_BT_CONN_P

TRUE

USB_BT_CONN_N

TRUE

AP_RESET_CONN_L

TRUE

SMBUS_PCH_CLK

TRUE

SMBUS_PCH_DATA

TRUE

SMBUS_SMC_1_S0_SCL

TRUE

SMBUS_SMC_1_S0_SDA

TRUE

J5815 (KBD BACKLIGHT CONN)

PP_KBD_BOOST_VOUT

TRUE

KBDLED_CATHODE1

TRUE

KBDLED_CATHODE2

TRUE

SMC_KBDLED_PRESENT_L

TRUE

J6950 (MAIN BATT CONN)

PPVBAT_G3H_CONN

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

SYS_DETECT_L_R

TRUE

SYSDET1

TRUE

SYSDET_3_4

TRUE

USB_EXTB_OC_L

TRUE

J6801 (2 MIC CONN)

CON_DMIC_PWR

TRUE

I1974

I1975

I1976

A

I1584

I1586

I1585

CON_DMIC_SDA1

TRUE

CON_DMIC_CLK

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<19>

TRUE

J4600 (LEFT USB CONN)

PP5V_S3_LTUSB_A_F

TRUE

USB_LT1_N

TRUE

USB_LT1_P

TRUE

FUNC_TEST

TRUE

TRUE

GND

GND

6 TPs

7

7

TRUE

7 8

46

46

46

46

39 42 77

7

7

39 42 77

7

32

7 8

7 8

7

36 40 80

8

8

24 36

9

36

9

36

36 40

7

18 27 36 39 66

18 27 36 38 39 66

7

36

25

17 36

9

36

7

18 36

7

36

7

36

36 39 40

26 36 74

26 36 74

9

36 74

9

36 74

7

36

17 42 75

17 42 75

39 42 77

39 42 77

48

48

48

48

56 57

39 42

39 42

56

55

55

55

38

38 74

38 74

GND

3 TPs
per Fan

U1000 CHARZ TPS

PCIE_TBT_D2R_P<0>

9

33 75

I1919

PCIE_TBT_D2R_N<0>

9

33 75

I1920

I1922

I1921

I1980

I1979

I1924

I1923

I1926

I1925

I1927

I1928

PCIE_AP_D2R_P

7

17 36 75

I1929

PCIE_AP_D2R_N

7

17 36 75

I1930

PCIE_ENET_D2R_P

17 36 75

I1931

PCIE_ENET_D2R_N

17 36 75

I1932

I1984

I1983

18 72
10

DMI_S2N_P<0>
DMI_S2N_N<0>
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

U1800 CHARZ TPS

DMI_N2S_P<0>
DMI_N2S_N<0>
FDI_DATA_P<0>
FDI_DATA_N<0>
FDI_DATA_P<4>
FDI_DATA_N<4>

PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N

5 TPs

per Fan

U4900 CHARZ TPS

LPC_AD<0>

I1954

LPC_AD<1>

I1956

LPC_AD<2>

I1955

LPC_AD<3>

I1958

LPC_FRAME_L

I1957

LPC_CLK33M_SMC

I1959

25 40

I1972

I1631

I1633

I1632

I1634

I1636

I1635

I1637

I1639

I1640

I1638

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

51 55

AUD_DMIC_SDA1

J6701 (AUDIO JACK CONN)

AUD_CONN_SLEEVE

AUD_CONN_MIC_XW

AUD_CONN_SLEEVE_XW

AUD_CONN_HP_LEFT
AUD_CONN_TIPDET_INV
PP3V3_S0
AUD_SPDIF_OUT_JACK
AUD_CONN_HP_RIGHT
AUD_CONN_TYPEDET

AUD_CONN_MIC

J6802 (AUDIO LEFT SPEAKER CONN)

I1644

I1646

I1648

I1647

I1649

SPKRCONN_L_OUT_N

TRUE

SPKRCONN_L_ID

TRUE

SPKRCONN_SL_OUT_P

TRUE

SPKRCONN_SL_OUT_N

TRUE

SPKRCONN_L_OUT_P

TRUE

J6803 (AUDIO RIGHT SPEAKER CONN)

I1653

I1654

I1652

I1651

I1655

I1656

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_ID

TRUE

SPKRCONN_SR_OUT_P

TRUE

SPKRCONN_SR_OUT_N

TRUE

GND

TRUE

SPKRCONN_R_OUT_P

TRUE

J9000 (EDP CONN)

PP5VR3V3_SW_LCD

TRUE

PPVOUT_S0_LCDBKLT

TRUE

LED_RETURN_6

TRUE

I1658

I1659

I1660

I1661

I1662

I1663

I1664

I1669

I1668

LED_RETURN_5

TRUE

LED_RETURN_4

TRUE

LED_RETURN_3

TRUE

LED_RETURN_2

TRUE

LED_RETURN_1

TRUE

LCD_HPD_CONN

TRUE

DP_INT_AUX_P

TRUE

DP_INT_AUX_N

TRUE

J3401 & J3402 (AIRPORT/BT/CAMERA CONN)

PCIE_CLK100M_AP_CONN_P

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

AP_CLKREQ_Q_L

TRUE

PCIE_WAKE_L

TRUE

AP_RESET_CONN_L

TRUE

PP3V3_WLAN_F

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

USB_CAMERA_CONN_P

TRUE

USB_CAMERA_CONN_N

TRUE

P2MM

1

P2MM

1

P2MM

1

P2MM

1

P2MM

1

P2MM

1

1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1

P2MM

1

54

54

54

7 8

54

54

54

53 55 78

53 55 78

51 55

53 55 78

53 55 78

53 55 78

53 55 78

51 55

53 55 78

53 55 78

SM
PP

SM
PP

SM
PP

SM
PP

SM
PP

SM
PP

P2MM
P2MM
P2MM
P2MM
P2MM
P2MM
P2MM
P2MM
P2MM
P2MM
P2MM
P2MM

P2MM
P2MM
P2MM
P2MM
P2MM
P2MM

SM
PP

54

51 54

PP0700
PP0701
PP0702
PP0703
PP0721
PP0722

SM
PP

SM

PP0704

PP
SM

PP0705

PP
SM

PP0706

PP
SM

PP0707

PP
SM

PP0708

PP
SM

PP0709

PP
SM

PP0710

PP
SM

PP0711

PP
SM

PP0712

PP
SM

PP0713

PP
SM

PP0723

PP

PP0724

SM
PP

SM

PP0714

PP
SM

PP0715

PP
SM

PP0716

PP
SM

PP0717

PP
SM

PP0718

PP

PP0719

PP0720

78

67

67 71 80

7

67 71

7

67 71

7

67 71

7

67 71

7

67 71

67 71

67

67 79

67 79

7

36

7

18 36

7

36

7

36 40 80

7

32

7

39 42 77

7

39 42 77

32 74

32 74

2 TP needed

36 78

36 78

TRUE

PP3V42_G3H

TRUE

WS_KBD1

TRUE

WS_KBD2

TRUE

WS_KBD3

TRUE

WS_KBD4

TRUE

WS_KBD5

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

WS_KBD10

TRUE

WS_KBD11

TRUE

WS_KBD12

TRUE

WS_KBD13

TRUE

WS_KBD14

TRUE

WS_KBD15_CAP

TRUE

WS_KBD16_NUM

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD19

TRUE

WS_KBD20

TRUE

WS_KBD21

TRUE

WS_KBD22

TRUE

WS_KBD23

TRUE

WS_KBD_ONOFF_L

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_CONTROL_KBD

TRUE

J5700 (IPD FLEX CONN)

PP3V3_S4

TRUE

Z2_CS_L

TRUE

Z2_MOSI

TRUE

Z2_MISO

TRUE

Z2_SCLK

TRUE

Z2_HOST_INTN

TRUE

PP5V_S4_CUMULUS

TRUE

Z2_CLKIN

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

PSOC_SCLK

TRUE

PSOC_MOSI

TRUE

PSOC_MISO

TRUE

PICKB_L

TRUE

PSOC_F_CS_L

TRUE

Z2_KEY_ACT_L

TRUE

I1629

J6900 (DC POWER CONN)

TDM_ONEWIRE_MPM

TRUE

I1657

ADAPTER_SENSE

TRUE

PP18V5_DCIN_FUSE

TRUE

TRUE

J4500 (SSD/HDD FLEX CONN)

PP3V3_S0_SSD_FLT

TRUE

I1566

TRUE

SMC_OOB1_TX_L

I1567

SMC_OOB1_RX_L

TRUE

I1569

PP5V_S0_HDD_FLT

TRUE

I1571

TRUE

FUNC_TEST

BKLT_EN

TRUE

LCD_BKLT_PWM

TRUE

PM_CLKRUN_L

TRUE

PM_SYSRST_L

TRUE

SMC_ONOFF_L

TRUE

J5100 (LPC + SPI CONN)

PP3V42_G3H

TRUE

I1601

PP5V_S0

TRUE

I1603

LPC_CLK33M_LPCPLUS

TRUE

I1602

LPC_AD<0>

TRUE

I1604

LPC_AD<2>

TRUE

I1606

LPC_AD<1>

TRUE

I1605

LPC_AD<3>

TRUE

I1607

SPI_ALT_MOSI

TRUE

I1609

I1608

I1611

I1610

I1612

I1614

I1613

I1616

I1615

I1617

I1618

I1619

I1621

I1620

I1622

I1623

I1624

I1626

I1625

I1627

I1628

LPCPLUS_GPIO

TRUE

LPCPLUS_RESET_L

TRUE

SMC_TDO

TRUE

TP_SMC_TRST_L

TRUE

TP_SMC_MD1

TRUE

SMC_TX_L

TRUE

SPI_ALT_MISO

TRUE

LPC_FRAME_L

TRUE

SPIROM_USE_MLB

TRUE

PM_CLKRUN_L

TRUE

SPI_ALT_CLK

TRUE

SPI_ALT_CS_L

TRUE

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

SMC_ROMBOOT

TRUE

SMC_RX_L

TRUE

SMC_TMS

TRUE

GND

GND

71

9

71

7

18 39 41

18 25 39

39 40 47

7 8

7 8

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

47

7 8

47

47

47

47

47

47

47

7

39 42 77

7

39 42 77

47

47

47

47

47

47

56

56

37

37 39 40

37 39 40

37

7 8

7 8

25 41 75

7

17 39 41 75

7

17 39 41 75

7

17 39 41 75

7

17 39 41 75

41

20 41

25 41

39 40 41

41

41

39 40 41

41

7

17 39 41 75

20 41 50

7

18 39 41

41

41

17 39 41

18 25 39 41

39 40 41

39 40 41

39 40 41 57

40 41

39 40 41

39 40 41

I1828

I1829

I1830

I1831

I1834

I1835

I1836

I1837

I1838

I1839

I1840

I1841

I1846

I1847

I1848

I1849

I1850

I1851

I1853

I1854

POWER RAILS

FUNC_TEST

PM_SLP_S3_L

TRUE

PP0V75_S0_DDRVTT

TRUE

PP1V05_S0

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

LED_RETURN_4

TRUE

LED_RETURN_5

TRUE

LED_RETURN_6

TRUE

TRUE

DMI_S2N_P<3..1>
DMI_S2N_N<3..1>
DMI_N2S_P<3..1>
DMI_N2S_N<3..1>

I1806

I1808

I1809

I1811

I1812

I1814

I1815

TBT_A_R2D_C_P<1..0>
TBT_A_R2D_C_N<1..0>
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>

TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>
TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>

I1843

I1842

I1844

I1845

TBT_B_R2D_C_P<1..0>
TBT_B_R2D_C_N<1..0>
TBT_B_R2D_P<1..0>
TBT_B_R2D_N<1..0>
TBT_B_D2R_C_P<0>
TBT_B_D2R_C_N<0>
TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>

I1852

I1855

I1856

I1857

TRUE
TRUE

TRUE

TRUE

GND

PP3V3_S0

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

PP5V_S3

TRUE

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PPDCIN_G3H

TRUE

PPVCORE_S0_CPU

TRUE

PPVTTDDR_S3

TRUE

TBTBPWRSW_ISET_V3P3

TBTBPWRSW_ISET_S0_R
TBTBPWRSW_ISET_S3

TBTAPWRSW_ISET_V3P3
TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

TBTAPWRSW_ISET_S3_R

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>
TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

TBT_B_D2R_P<0>
TBT_B_D2R_N<0>
TBT_B_D2R_P<1>
TBT_B_D2R_N<1>

PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N

ICT Test Points

7

18 27 36 39 66

8

TP_TBT_MONDC0

33

TP_TBT_MONDC1

33

TRUE

TRUE
TRUE
TRUE

8

7 8

7 8

8

7 8

7 8

8

8

8

8

8

8

TRUE

TRUE
TRUE

TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE
TRUE

TRUE

TRUE

TRUE

TRUE

TRUE
TRUE

TRUE

78

TRUE
TRUE
TRUE

TRUE

TRUE

TRUE

TRUE

51

17

TP_TBT_PCIE_RESET0_L

33

TP_TBT_PCIE_RESET1_L

33

TP_TBT_PCIE_RESET2_L

33

TP_TBT_PCIE_RESET3_L

7

67 71

33

TP_TBT_XTAL25OUT

7

67 71

33

7

67 71

7

67 71

TP_DP_TBTSRC_ML_CP<3>

33

7

67 71

TP_DP_TBTSRC_ML_CN<3>

33

4 TPs

TP_DP_TBTSRC_ML_CP<2>

33

TP_DP_TBTSRC_ML_CN<2>

33

TP_DP_TBTSRC_ML_CP<1>

33

TP_DP_TBTSRC_ML_CN<1>

33

78

TP_DP_TBTSRC_ML_CP<0>

33

TP_DP_TBTSRC_ML_CN<0>

33

TP_DP_TBTSRC_AUXCH_CP

33

39 40

TP_DP_TBTSRC_AUXCH_CN

33

TP_SPI_CS1_L

17

TP_PCH_GPIO8

20

TP_PCH_STRP_BBS1

19

TP_PCH_STRP_ESI_L

19

TP_PCH_TP23

19

TP_PCI_CLK33M_OUT2

19

TP_PCIE_CLK100M_PEGAN

17

TP_PCIE_CLK100M_PEGAP

17

TP_PM_SLP_A_L

18

TP_PPVOUT_PCH_DCPSUSBYP

21

10 18 72

TP_SMC_MPM5_LED_PWR

39

10 18 72

TP_SMC_MPM5_LED_CHG

39

10 18 72

TP_SMS_INT2

49

10 18 72

70

70

70

69

69

69

69

33 69 76

33 69 76

69 76

69 76

69 76

69 76

69 76

69 76

33 69 76

33 69 76

33 69 76

33 69 76

33 70 76

33 70 76

70 76

70 76

70 76

70 76

70 76

70 76

33 70 76

TRUE

33 70 76

TRUE

33 70 76

TRUE

33 70 76

TRUE

7

17 36 75

7

17 36 75

36 75

24

36 75

24

24

24

24

24

24

24

24

TP_1V05_S0_PCH_VCCAPLLEXP

21

TP_AUD_CODEC_MICBIAS

51

TP_AUD_MIC_INRP

51

TP_AUD_MIC_INRN

51

AUD_SPDIF_IN

7

TP_BKL_FAULT

71

TP_LPC_DREQ0_L

7

PCIE_TBT_R2D_C_P<3..0>

I1820

PCIE_TBT_R2D_C_N<3..0>

I1822

PCIE_TBT_R2D_P<3..0>

I1821

PCIE_TBT_R2D_N<3..0>

I1823

PCIE_TBT_D2R_P<3..1>

I1827

PCIE_TBT_D2R_N<3..1>

I1826

PCIE_TBT_D2R_C_P<3..1>

I1824

PCIE_TBT_D2R_C_N<3..1>

I1825

MEM_A_DQ<0>

I1709

MEM_A_DQ<12..2>

I1710

MEM_A_DQ<19..14>

I1711

MEM_A_DQ<24..21>

I1712

MEM_A_DQ<32..26>

I1713

MEM_A_DQ<42..34>

I1714

MEM_A_DQ<54..44>

I1715

MEM_A_DQ<56>

I1716

MEM_A_DQ<63..58>

I1717

MEM_B_DQ<2..0>

I1719

MEM_B_DQ<13..4>

I1718

MEM_B_DQ<19..15>

I1720

MEM_B_DQ<25..21>

I1722

MEM_B_DQ<35..27>

I1721

MEM_B_DQ<40..37>

I1723

MEM_B_DQ<47..42>

I1724

MEM_B_DQ<57..49>

I1725

MEM_B_DQ<63..59>

I1726

NC_MEM_EVENT_L

I1731

I1879

I1878

I1881

I1880

TP_XDP_PCH_HOOK4

TP_XDP_PCH_HOOK5
TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>
TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>
TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>
TP_XDP_PCH_TRST_L

CPU NO_TESTs

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE

HDMI_IG_CLK_C_P
HDMI_IG_CLK_C_N
HDMI_IG_DATA_C_P<2..0>
HDMI_IG_DATA_C_N<2..0>

PCIE_CLK100M_ENET_P

TRUE

I1542

I1543

I1545

I1547

PCIE_CLK100M_ENET_N

TRUE

USB3_EXTB_TX_C_P

TRUE

USB3_EXTB_TX_C_N

TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_1V05_S0_PCH_VCCAPLLEXP

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

NC_SPI_CS1_L
NC_PCH_GPIO8
NC_PCH_STRP_BBS1
NC_PCH_STRP_ESI_L
NC_PCH_TP23

NC_PCI_CLK33M_OUT2
NC_PCIE_CLK100M_PEGAN
NC_PCIE_CLK100M_PEGAP
NC_PM_SLP_A_L

NC_PPVOUT_PCH_DCPSUSBYP
NC_SMC_MPM5_LED_PWR
NC_SMC_MPM5_LED_CHG

NC_SMS_INT2

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

40

TRUE
TRUE

TRUE

TRUE

NC_TBT_MONDC0

NC_TBT_MONDC1
NC_TBT_PCIE_RESET0_L
NC_TBT_PCIE_RESET1_L
NC_TBT_PCIE_RESET2_L
NC_TBT_PCIE_RESET3_L

NC_TBT_XTAL25OUT

NC_DP_TBTSRC_ML_CP<3>
NC_DP_TBTSRC_ML_CN<3>

NC_DP_TBTSRC_ML_CP<2>

NC_DP_TBTSRC_ML_CN<2>
NC_DP_TBTSRC_ML_CP<1>

NC_DP_TBTSRC_ML_CN<1>
NC_DP_TBTSRC_ML_CP<0>

NC_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN

9

33 75

TRUE

9

33 75

TRUE

33 75

TRUE

33 75

TRUE

9

33 75

TRUE

9

33 75

TRUE

33 75

TRUE

33 75

TRUE

9

36 78

9

36 78

9

36 78

9

36 78

7

17 36 75

7

17 36 75

36 79

36 79

NC_XDP_PCH_HOOK4
NC_XDP_PCH_HOOK5
NC_XDP_PCH_OBSFN_B<0>
NC_XDP_PCH_OBSFN_B<1>
NC_XDP_PCH_OBSFN_A<0>
NC_XDP_PCH_OBSFN_A<1>
NC_XDP_PCH_OBSFN_D<0>
NC_XDP_PCH_OBSFN_D<1>
NC_XDP_PCH_TRST_L

NC_AUD_CODEC_MICBIAS

NC_AUD_MIC_INRP
NC_AUD_MIC_INRN

AUD_SPDIF_IN

NC_BKL_FAULT

NC_LPC_DREQ0_L

NC_PCIE_CAMERA_D2RP

MAKE_BASE=TRUE

NC_PCIE_CAMERA_D2RN

MAKE_BASE=TRUE

NC_PCIE_CAMERA_R2D_CN

MAKE_BASE=TRUE TRUE

NC_PCIE_CAMERA_R2D_CP

MAKE_BASE=TRUE TRUE

NC_PCIE_CLK100M_CAMERAN

MAKE_BASE=TRUE

NC_PCIE_CLK100M_CAMERAP

MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4N

17

TP_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4P

17

TP_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBN

17

TP_PCIE_CLK100M_PEBP NC_PCIE_CLK100M_PEBP

17

TP_SATA_C_D2RN

17

TP_SATA_C_D2RP NC_SATA_C_D2RP

17

TP_SATA_C_R2D_CN

17

TP_SATA_C_R2D_CP NC_SATA_C_R2D_CP

17

TP_SATA_D_D2RN NC_SATA_D_D2RN

17

TP_SATA_D_D2RP NC_SATA_D_D2RP

17

TP_SATA_D_R2D_CN NC_SATA_D_R2D_CN

17

TP_SATA_D_R2D_CP

17

TP_SATA_E_D2RN NC_SATA_E_D2RN

17

TP_SATA_E_D2RP NC_SATA_E_D2RP

17

TP_SATA_E_R2D_CN NC_SATA_E_R2D_CN

17

TP_SATA_E_R2D_CP NC_SATA_E_R2D_CP

17

TP_SATA_F_D2RN NC_SATA_F_D2RN

17

TP_SATA_F_D2RP NC_SATA_F_D2RP

17

TP_SATA_F_R2D_CN NC_SATA_F_R2D_CN

17

TP_SATA_F_R2D_CP NC_SATA_F_R2D_CP

17

TP_CRT_IG_BLUE NC_CRT_IG_BLUE

18

TP_CRT_IG_GREEN NC_CRT_IG_GREEN

18

TP_CRT_IG_RED

18

TP_CRT_IG_DDC_CLK NC_CRT_IG_DDC_CLK

18

TP_CRT_IG_DDC_DATA

18

TP_CRT_IG_HSYNC

18

TP_CRT_IG_VSYNC

18

TP_HDA_SDIN1

17

TP_HDA_SDIN2 NC_HDA_SDIN2

17

TP_HDA_SDIN3

17

18

TP_SDVO_TVCLKINN

18

TP_SDVO_TVCLKINP

18

TP_SDVO_STALLN

18

TP_SDVO_STALLP

18

TP_SDVO_INTN
TP_SDVO_INTP

18

TP_PCI_PME_L

19

TP_PCI_CLK33M_OUT3

19

I1987

I1986

I1985

I1988

I1989

I1990

NC_LPC_DREQ0_L

7 7

MAKE_BASE=TRUE

NC_LPC_DREQ1_L

MAKE_BASE=TRUE TRUE

TP_CLINK_CLK

17

TP_CLINK_DATA

17

TP_CLINK_RESET_L

17

PAGE TITLE

7

51

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

S2 CAMERA PCIE SIGNALS

PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P

TRUE

PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P

TRUE

TRUE

NC NO_TESTs

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE
TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE

NC_ISNS_LCDBKLTN
NC_ISNS_LCDBKLTP
NC_ISNS_WLANN
NC_ISNS_WLANP

NC_ISNS_LCD_PANELN
NC_ISNS_LCD_PANELP

PCH ALIASES

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P

TP_LPC_DREQ0_L
TP_LPC_DREQ1_L

TRUE
TRUE
TRUE
TRUE

TRUE
TRUE

TRUE

NO_TEST

TRUE

I1671

TRUE

I1670

TRUE

I1672

TRUE

I1673

TRUE

I1675

TRUE

I1674

TRUE

I1676

TRUE

I1677

TRUE

I1679

TRUE

I1678

TRUE

I1680

TRUE

I1681

TRUE

I1683

TRUE

I1682

TRUE

I1684

TRUE

I1685

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE

TRUE

Functional / ICT Test

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

R

6 3

12

17

17

17

17

NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP

NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP

NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP

NC_SATA_C_D2RN

NC_SATA_C_R2D_CN

NC_SATA_D_R2D_CP

NC_CRT_IG_RED

NC_CRT_IG_DDC_DATA

NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC

NC_HDA_SDIN1

NC_HDA_SDIN3

NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP

NC_SDVO_STALLN
NC_SDVO_STALLP

NC_SDVO_INTN
NC_SDVO_INTP

NC_PCI_PME_L
NC_PCI_CLK33M_OUT3

NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L

80

80

80

80

67 80

67 80

SYNC_DATE=MASTERSYNC_MASTER=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

7 OF 132

SHEET

7 OF 80

124578

PCIE_ENET_R2D_C_P

I1885

PCIE_ENET_R2D_C_N

I1884

7

17 75

7

17 75

17

D

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

C

B

17

PCIE_AP_R2D_C_P

I1889

PCIE_AP_R2D_C_N

I1888

PCIE_AP_D2R_P

I1887

PCIE_AP_D2R_N

I1886

PCIE_AP_D2R_PI_P

I1892

PCIE_AP_D2R_PI_N

I1893

PCIE_AP_R2D_PI_P

I1895

PCIE_AP_R2D_PI_N

I1894

PCIE_CLK100M_PCH_P

I1896

PCIE_CLK100M_PCH_N

I1897

PCIE_CLK100M_TBT_P

I1902

PCIE_CLK100M_TBT_N

I1901

PCH_CLK100M_SATA_P

I1899

PCH_CLK33M_PCIIN

I1909

PCIE_CLK100M_SSD_P

I1910

PCIE_CLK100M_SSD_N

I1911

PEG_CLK100M_P

I1904

PEG_CLK100M_N

I1903

PCIE_CLK100M_ENET_P

I1906

PCIE_CLK100M_ENET_N

I1905

PCIE_CLK100M_AP_P

I1917

PCIE_CLK100M_AP_N

I1916

PCIE_CLK100M_FW_P

I1914

PCIE_CLK100M_FW_N

I1915

PCIE_CLK100M_EXCARD_P

I1913

PCIE_CLK100M_EXCARD_N

I1912

SATA_HDD_R2D_RDRIN_P

I1858

SATA_HDD_R2D_RDRIN_N

I1860

SATA_HDD_D2R_RDROUT_P

I1859

SATA_HDD_D2R_RDROUT_N

I1861

SATA_HDD_D2R_RDRIN_P

I1862

SATA_HDD_D2R_RDRIN_N

I1863

SATA_HDD_R2D_RDROUT_N

I1865

SATA_HDD_R2D_RDROUT_P

I1864

SATA_HDD_D2R_RC_P

I1866

SATA_HDD_D2R_RC_N

I1867

SATA_HDD_R2D_RC_N

I1868

SATA_HDD_R2D_RC_P

I1869

SATA_HDD_R2D_C_P

I1870

SATA_HDD_R2D_C_N

I1872

SATA_HDD_D2R_P

I1871

SATA_HDD_D2R_N

I1873

SATA_SSDRHDD_D2R_P

I1874

SATA_SSDRHDD_D2R_N

I1875

SATA_SSDRHDD_R2D_P

I1876

SATA_SSDRHDD_R2D_N

I1877

USB3_EXTA_RX_F_P

I1960

USB3_EXTA_RX_F_N

I1961

USB3_EXTA_RX_P

I1962

USB3_EXTA_RX_N

I1963

USB3_EXTA_TX_C_P

I1964

USB3_EXTA_TX_C_N

I1966

USB3_EXTA_TX_N

I1965

USB3_EXTA_RX_N

I1967

USB3_EXTB_RX_RC_P

I1968

USB3_EXTB_RX_RC_N

I1970

USB3_EXTB_RX_P

I1969

USB3_EXTB_RX_N

I1971

TRUE

TRUE

TRUE

TRUE

TRUE
TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE
TRUE

TRUE
TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE
TRUE

TRUE

TRUE

TRUE
TRUE
TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE
TRUE
TRUE

TRUE

TRUE

TRUE

TRUE

TRUE

TRUE
TRUE

TRUE

A

SIZE

D

8 7 6 5 4 3

=PPBUS_G3H

56 57

G3H Rails

=PPVIN_S5_HS_COMPUTING_ISNS

44

D

=PPVIN_S5_HS_OTHER_ISNS

44

=PP18V5_DCIN_CONN

56

=PP3V42_G3H_REG

56

=PP3V42_G3H_BMU
=PP3V42_G3H_AUDIO

54

=PP3V42_G3H_TDM
=PP3V42_S3_HALL

40

For PCH RTC Power

=PPVRTC_G3_OUT

C

25

=PP5V_S5_LDO

59

=PP5V_SUS_FET

65

=PP5V_S4_REG

59

=PP5V_S3_FET

65

5V Rails

B

=PP5V_S0_FET

65

=PP5V_S0_AUDIO

51

3.3V Rails

=PP3V3_S4_FET

65

=PP3V3_S4_TBT

A

33 34 35

=PP3V3_S4_RIO

36

=PP3V3_SUS_FET

65

=PP3V3_SUS_PCH

23

=PP3V3_SUS_ROM

50

=PP3V3_SUS_PCH_VCC_SPI

21 23

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE

=PPBUS_S0_LCDBKLT
=PPVIN_S5_HS_OTHER_ISNS_R
=PPVIN_S5_HS_COMPUTING_ISNS_R

=PPVIN_SW_TBTBST
=PPBUS_S0_VSENSE
=PPBUS_G3H_T25_R

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE

=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_CPUAXG
=PPVIN_S0_VCCSAS0

PPVIN_S5_HS_OTHER_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

=PPVIN_S5_P5VP3V3
PPDCIN_G3H

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

=PPDCIN_S5_CHGR

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_CHGR
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_5
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

=PPVRTC_G3_PCH

PP5V_S5

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MMMAKE_BASE=TRUE

=PP5V_S5_P1V5S3RS0FET
=PP5V_S5_P5VSUSFET

=PP5V_S5_TPAD

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP5V_SUS_PCH

PP5V_S4

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

=PP5V_S0_LCD

=PP5V_S3_LTUSB
=PP5V_S4_P5VS0FET

=PP5V_S4_P5VS3FET
=PP5V_S4_AUDIO
=PP5V_S4_RIO

=PP5V_S4_P1V05TBTS0

=PP5V_S4_TPAD

PP5V_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

=PP5V_S3_ISNS
=PP5V_S3_ALSCAMERA

=PP5V_S3_DDRREG

=PP5V_S3_DEBUG_ADC_AVDD
=PP5V_S3_DEBUG_ADC_DVDD

=PP5V_S3_DEBUG_ISNS
=PP5V_S3_MEMRESET

PP5V_S0

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PP5V_S0_AUDIO_XW
=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN_LT

=PP5V_S0_FAN_RT

=PP5V_S0_KBDLED

=PP5V_S0_LPCPLUS
=PP5V_S0_PCH
=PP5V_S0_HDD

=PP5V_S0_RMC
=PP5V_S0_VCCSAS0
=PP5V_S0_VMON

PP3V3_S4

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM

=PP3V3_S4_TPAD
=PP3V3_S4_SMC
=PP3V3_S4_BT

PP3V3_SUS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

=PP3V3_SUS_P1V05SUSLDO
=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_SUS_PCH_VCCSUS_USB
=PP3V3_SUS_CNTRL
=PP3V3_SUS_SMC

VOLTAGE=12.8V
MAKE_BASE=TRUE

VOLTAGE=18.5V
MAKE_BASE=TRUE

VOLTAGE=3.42V
MAKE_BASE=TRUE

VOLTAGE=3.42V
MAKE_BASE=TRUE

VOLTAGE=5V

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=5V

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V

7

71

44

7

57

17 18 21

7

25 36 40

36

21 23

17 18 19 20

21 23

66

40

35

44

61 62

60

63

62

58

59

7

41

39 40

57 66

56

7

65

65

47

67

38

65

65

55

36

64

47

7

32

60

27

7

9

71

61 62

63

46

46

48

41

58

66

64

66

42

38

47

40

25

23

23 25

37

7

44

47

=PP3V3_S5_REG

59

=PP3V3_S3_FET

65

=PP3V3_S0_FET

65

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM

=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
=PP3V3_S4_TBTAPWRSW
=PP3V3_S4_TBTBPWRSW
=PP3V3_S4_P3V3S4FET
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S5_P3V3SUSFET
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD
=PP3V3_S5_PCH_GPIO
=PP3V3_S5_PCH_VCCDSW
=PP3V3_S5_PWRCTL
=PP3V3_S5_SMCBATLOW
=PP3V3_S5_SYSCLK
=PP3V3_S5_VMON
=PP3V3_S5_XDP

=PP3V3_S5_P1V5S0

PP3V3_S3

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S3_ISNS
=PP3V3_S3_MEMRESET
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_RIO
=PP3V3_S3_SMBUS_SMC_2_S3
=PP3V3_S3_SMBUS_SMC_3

=PP3V3_S3_USBMUX
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_GYRO
=PP3V3_S3_SMS
=PP3V3_S3_SDBUF
=PP3V3_S3_CAMERA
=PP3V3_S3_P1V2S3
=PP3V3_S3_P1V8S3
=PP3V3_S3_BT

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 mm

=PP3V3_S0_AUDIO
=PP3V3_S0_AUDIO_DIG
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_P1V5S0

=PP3V3_S0_P1V8S0
=PP3V3_S0_BKLI2C
=PP3V3_S0_DDCMUX
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_HS_ISNS

=PP3V3_S0_IMVPISNS
=PP3V3_S0_ISNS

=PP3V3_S0_CPU_VCCIO_SEL
=PP3V3_S0_LCD

=PP3V3_S0_P3V3TBTFET
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_VCC3_3
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SATAMUX

=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_1_S0
=PP3V3_S0_SSD
=PP3V3_S0_SYSCLK
=PP3V3_S0_TBTI2C
=PP3V3_S0_TBTPWRCTL
=PP3V3_S0_HDMI
=PP3V3_S0_TPAD
=PP3V3_S0_VMON

=PP3V3_S0_XDP
=PP3V3_S0_DDR3THMSNS
=PP3V3_S0_SPKRTHMSNS

=PP3V3_S0_HS_COMPUTING_ISNS

=PP3V3_S0_HS_OTHER_ISNS

VOLTAGE=3.3V
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V
MAKE_BASE=TRUE

VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S0_PCH_STRAPS

7

78

65

65

69

70

65

27

65

18

66

20

21 23

66

40

25

66

24

7

43

27

19 25

36

42

42

26

26

26

31

36 66

49

49

25

36

7

78

51 55

51 54

71

45

64

64

68

46

46

45

43

43 80

13

67

35

17 23

17 18 19 20 25 35

23

23

21 23

9

66

25

25 66

42

42

42

37

25

35

36

48

66

24

44

44

20

=PP1V8_S0_REG

64

2A max supply

=PP1V8_S0_CPU_VCCPLL_R

13 15

=PPDDR_S3_REG

60

=PPVIN_S3_MEM_ISNS

43

=PP1V5_S3RS0_FET

65

=PP1V5_S0_REG

64

=PPVTT_S3_DDR_BUF

31 60

=PPVTT_S0_DDR_LDO

60

=PP1V05_SUS_LDO

64

63

=PPCPUVCCIO_S0_REG

=PPBUS_G3H_T25

=PPBUS_SW_BKL

80

1.8V/1.5V/1.2V/1.05V Rails

Backlight Rails

PP1V8_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V8_S0_AUDIO
=PP1V8_S0_CPU_VCCPLL
=PP1V8_S0_PCH_VCC_DFTERM
=PPVDDIO_S0_SBCLK

PP1V8_S0_CPU_VCCPLL_R

MIN_LINE_WIDTH=0.5 MM

PP1V5R1V35_S3

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.35V
MAKE_BASE=TRUE

=PPDDR_S3_MEMVREF
=PPVIN_S3_P1V5S3RS0_FET
=PPVIN_S0_DDRREG_LDO

=PPVIN_S3_MEM_ISNS_R

PP1V5R1V35_MEM

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.35V
MAKE_BASE=TRUE

=PP1V5R1V35_S3_MEM_A
=PP1V5R1V35_S3_MEM_B
=PP1V5_S3_MEMRESET

PP1V5_S3RS0_CPUDDR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S3RS0_VMON
=PP1V5R1V35_S3_CPU_VCCDDR

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_AUDIO
=PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP1V5_S0_RDRVR

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.675V
MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.675V
MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B

=PPVTT_S0_VTTCLAMP
PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_SUS_PCH_JTAG
PP1V05_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_CPU_VCCIO
=PPVCCIO_S0_XDP
=PPVCCIO_S0_CPUIMVP
=PPVCCIO_S0_SMC
=PP1V05_S0_VMON
=PP1V05_S0_RMC
=PP1V05_S0_PCH_VCCIO_PLLPCIE
=PP1V05_S0_PCH_VCCADPLL
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI

PPBUS_G3H_T25_PWR

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MMMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 MM

PPBUS_S0_LCDBKLT_PWR

VOLTAGE=1.8V
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE
VOLTAGE=12.8V

VOLTAGE=12.6V

21

15

20 21 23

25

31

65

60

43

28

29

27

78

66

11 13 16 27

7

51

21 23 25

36

7

7

30

30

27

24

7

10 11 13 15

24

61

40

66

23

21 23

18

17 23

8

21 23

21 23

8

17 21 23

17 23

21 23

21 23

21 23

71

=PP18V5_DCIN_ISOL

56

TBT Rails (off when no cable)

=PP15V_TBT_REG

35

=PP3V3_TBTLC_FET

35

=PP1V05_S0_P1V05TBTREG_R

64 80

=PP1V05_S0_P1V05TBTREG

35 80

=PP1V05_TBTCIO_FET

35

=PPVCORE_S0_CPU_REG

62

=PPVCORE_S0_AXG_REG

62

=PP1V5_S3_CPU_VCCDQ

13 16

=PP1V05_S0_CPU_VCCPQE

13 15

=PPVCCSA_S0_REG

58 80

SYNC_MASTER=MASTER

PAGE TITLE

I1709

Chipset "VCore" Rails

PPDCIN_G3H_ISOL

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

=PPDCIN_S5_CHGR_ISOL
=PPDCIN_S5_VSENSE

PPVIN_SW_TBTBST

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V

PP15V_TBT

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=15V
MAKE_BASE=TRUE

=PPHV_SW_TBTAPWRSW
=PPHV_SW_TBTBPWRSW

PP3V3_TBTLC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_TBT_PCH_GPIO
=PP3V3_TBTLC_RTR
=PPVDDIO_TBT_CLK

=PP3V3_TBT_PCH_GPIO

PP1V05_S0_P1V05TBTREG_R

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

PP1V05_S0_P1V05TBTREG

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_TBTLC_RTR
=PP1V05_TBTLC

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_TBTCIO_RTR

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

=PPVCORE_S0_CPU
PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PPVCORE_S0_CPU_VCCAXG
PP1V5_S3_CPU_VCCDQ

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PPVCCSA_S0_REG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PPVCCSA_S0_CPU

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

12

VOLTAGE=18.5V

MAKE_BASE=TRUE

VOLTAGE=1.05V

VOLTAGE=1.05V
MAKE_BASE=TRUE

MAKE_BASE=TRUE
VOLTAGE=1.25V

MAKE_BASE=TRUE
VOLTAGE=1.05V

MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.5V

VOLTAGE=1.05V
MAKE_BASE=TRUE

VOLTAGE=0.9V
MAKE_BASE=TRUE

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

8 OF 132

SHEET

8 OF 80

124578

57

44

D

C

35

69

70

8

17 20

33 34 35

25

8

17 20

B

34

35

34

7

10 13 15 43

10 13 16 43

13 16

A

SIZE

D

ZT0940

4P5R2P3-3P5B

4P5R2P3-3P5B

1

ZT0960

1

Bosses for limiting deflection

2.8OD1.2ID-2.25H-SM-D1

D

2.8OD1.2ID-2.25H-SM-D1

2.8OD1.2ID-2.25H-SM-D1

2.8OD1.2ID-2.25H-SM-D1

SH0910

SH0911

SH0912

SH0913

C

APN: 860-1490

FAN BOSSES (4X 860-1327)

SH0922

STDOFF-4.5OD1.8H-SM

1

B

D1 POGO PINS (870-2451)

POGO-2.3OD-5.5H-SM-LOW-FORCE

D1 ELIPTICAL SLOT HOLES

ZT0930

TH-NSP TH-NSP

1

SL-3.9X2.3-4.2x2.6

A

8 7 6 5 4 3

SM

SH0933

1

1K

5%
MF

2

eDP signals

SL-1.1X0.5-1.4x0.8

SL-1.1X0.5-1.4x0.8

SL-1.1X0.45-1.4x0.75

SL-1.1X0.45-1.4x0.75

STDOFF-4.5OD1.8H-SM

SM

1

SH0936

SM

1

NC_PCH_GPIO64_CLKOUTFLEX0
NC_PCH_GPIO65_CLKOUTFLEX1
NC_PCH_GPIO66_CLKOUTFLEX2
NC_PCH_GPIO67_CLKOUTFLEX3

Digital Ground

TP_EDP_AUX_P
TP_EDP_AUX_N
TP_EDP_TX_P<3..0>
TP_EDP_TX_N<3..0>

TH0900

TH-NSP

1

TH0903

1

TH0904

1

TH0905

1

APN:862-0118

TH-NSP

TH-NSP

APN:998-3975

TH-NSP

SH0925

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

GND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

10

10

SH0937

1

10

10

LCD_BKLT_PWM

7

71

MAKE_BASE=TRUE

LCD_BKLT_EN

71

MAKE_BASE=TRUE

LCD_PWR_EN

67

MAKE_BASE=TRUE

CR SFF DG v1p0 Table 3-56 mapping for HDMI

HDMI_IG_CLK_C_P

7

36 78

MAKE_BASE=TRUE

HDMI_IG_CLK_C_N

7

36 78

MAKE_BASE=TRUE

HDMI_IG_DATA_C_P<2..0>

7

36 78

MAKE_BASE=TRUE

HDMI_IG_DATA_C_N<2..0>

7

36 78

MAKE_BASE=TRUE

HDMI_IG_DDC_CLK

7

36

MAKE_BASE=TRUE

HDMI_IG_DDC_DATA

MAKE_BASE=TRUE

36

DP_TBTSNK0_AUXCH_C_P

33 79

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_N

33 79

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>

33 79

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_N<3..0>

33 79

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_CLK

68

MAKE_BASE=TRUE

DP_TBTSNK0_DDC_DATA

68

MAKE_BASE=TRUE

33

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_P

33 79

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_N

33 79

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_P<3..0>

33 79

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_N<3..0>

33 79

MAKE_BASE=TRUE

DP_TBTSNK1_DDC_CLK

68

MAKE_BASE=TRUE

DP_TBTSNK1_DDC_DATA

68

MAKE_BASE=TRUE

DP_TBTSNK1_HPD

33

MAKE_BASE=TRUE

SM

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

=PP5V_S0_AUDIO_XW

8

HDMI_HPD

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

TP_PCH_GPIO64_CLKOUTFLEX0
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO66_CLKOUTFLEX2
TP_PCH_GPIO67_CLKOUTFLEX3

LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR

TP_DP_IG_B_MLP<3>
TP_DP_IG_B_MLN<3>

TP_DP_IG_B_MLP<0..2>
TP_DP_IG_B_MLN<0..2>

DPA_IG_DDC_CLK
DPA_IG_DDC_DATA

DPA_IG_HPD

DPB_IG_AUX_CH_P
DPB_IG_AUX_CH_N

TP_DP_IG_C_MLP<3..0>
TP_DP_IG_C_MLN<3..0>

DPB_IG_DDC_CLK
DPB_IG_DDC_DATA

TP_DP_IG_D_AUXP
TP_DP_IG_D_AUXN

TP_DP_IG_D_MLP<3..0>
TP_DP_IG_D_MLN<3..0>

TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_HPD

XW0902

SM

1 2

XW0903

SM

1 2

18

18

18

18

18

18

18

18

18

DPB_IG_HPD

17

17

17

17

PP5V_S0_AUDIO_AMP_L

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

PP5V_S0_AUDIO_AMP_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

18

18

18

18

18

33 75

33 75

33 75

33 75

36

18

18

NC_PEG_CLK100MN

MAKE_BASE=TRUE

NC_PEG_CLK100MP

MAKE_BASE=TRUE

18

18

18

18

18

18

18

18

MEMVTT_EN

27

MAKE_BASE=TRUE

T29 Signals Through PEG

PCIE_TBT_D2R_P<3..0>

7

MAKE_BASE=TRUE

PCIE_TBT_D2R_N<3..0>

7

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

7

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

7

MAKE_BASE=TRUE

SD_PWR_EN_PCH

MAKE_BASE=TRUE

SD_PWR_EN

7

MAKE_BASE=TRUE

TP_FW_PWR_EN

MAKE_BASE=TRUE

NC_PEG_D2RP<15..12>

MAKE_BASE=TRUE

NC_PEG_D2RN<15..12>

MAKE_BASE=TRUE

NC_PEG_R2D_CP<15..12>

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..12>

MAKE_BASE=TRUE

NC_PEG_D2RP<7..0>

MAKE_BASE=TRUE

NC_PEG_D2RN<7..0>

MAKE_BASE=TRUE

NC_PEG_R2D_CP<7..0>

MAKE_BASE=TRUE

NC_PEG_R2D_CN<7..0>

MAKE_BASE=TRUE

NC_DPA_IG_AUX_CHP

MAKE_BASE=TRUE

NC_DPA_IG_AUX_CHN

MAKE_BASE=TRUE

NC_USB3_EXTC_TXP

MAKE_BASE=TRUE

NC_USB3_EXTC_TXN

MAKE_BASE=TRUE

NC_USB3_EXTC_RXP

MAKE_BASE=TRUE

NC_USB3_EXTC_RXN

MAKE_BASE=TRUE

NC_USB_EXTCP

MAKE_BASE=TRUE

NC_USB_EXTCN

MAKE_BASE=TRUE

NC_USB3_EXTD_TXP

MAKE_BASE=TRUE

NC_USB3_EXTD_TXN

MAKE_BASE=TRUE

NC_USB3_EXTD_RXP

MAKE_BASE=TRUE

NC_USB3_EXTD_RXN

MAKE_BASE=TRUE

NC_USB_EXTD_EHCIP

MAKE_BASE=TRUE

NC_USB_EXTD_EHCIN

MAKE_BASE=TRUE

NC_USB_4N

MAKE_BASE=TRUE

NC_USB_4P

MAKE_BASE=TRUE

NC_USB_SDN

MAKE_BASE=TRUE

NC_USB_SDP

MAKE_BASE=TRUE

NC_USB_WLANN

MAKE_BASE=TRUE

NC_USB_WLANP

MAKE_BASE=TRUE

NC_USB_BT_HSN

MAKE_BASE=TRUE

NC_USB_BT_HSP

MAKE_BASE=TRUE

NC_USB_12N

MAKE_BASE=TRUE

NC_USB_12P

MAKE_BASE=TRUE

NC_USB_13N

MAKE_BASE=TRUE

NC_USB_13P

MAKE_BASE=TRUE

53

53

Unused PEG signals

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

Unused GPU signals

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

UNUSED USB SIGNALS

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

USB_BT_P

7

36 74

MAKE_BASE=TRUE

USB_BT_N

7

36 74

MAKE_BASE=TRUE

USB_TPAD_P

47 74

MAKE_BASE=TRUE

USB_TPAD_N

47 74

MAKE_BASE=TRUE

USB_SMC_P

39 74

MAKE_BASE=TRUE

USB_SMC_N

39 74

MAKE_BASE=TRUE

PU_USBHUB_DN4_P

78

MAKE_BASE=TRUE

PU_USBHUB_DN4_N

78

MAKE_BASE=TRUE

CPU signals

=DDRVTT_EN

ENET_LOW_PWR_PCH
ENET_LOW_PWR
FW_PWR_EN

=PEG_D2R_P<15..12>
=PEG_D2R_N<15..12>

=PEG_D2R_P<7..0>
=PEG_D2R_N<7..0>
=PEG_R2D_C_P<7..0>
=PEG_R2D_C_N<7..0>

Frame Holes

APN:860-1557

1

1

1

1

SH0920

STDOFF-4.5OD2.15H-SM

1

SH0926

STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM

1

D1 BMU MODULE STANDOFFS

SH0928

STDOFF-4.5OD1.73H-SM

1

SH0963 is BMU standoff with flange. 860-1534

TH0900 for upper TBT can gnd slot

TH0903 for lower TBT can gnd slot

TH0904,5 for USB can gnd slot

SH0923

STDOFF-4.5OD1.8H-SM

1

POGO-2.3OD-5.5H-SM-LOW-FORCE

SH0934

SM SM

1

MLB_RAMCFG0

20

POGO-2.3OD-5.5H-SM-LOW-FORCE

ZT0920

1

SL-2.8X1.8-3.1x2.1

R0910

1/20W

201

1K

5%
MF

20

RAMCFG1:L

1

2

20

MLB_RAMCFG1

RAMCFG0:L

1

SH0950

SHLD-D1-USB

D1 THERMAL MODULE STANDOFF (860-1439)

STDOFF-4.5OD2.33H-SM

SH0932

SM

1

SH0935

1

20

MLB_RAMCFG2

1

R0911

1K

5%

1/20W

MF

201

2

DP_INT_AUX_C_P

67 79

MAKE_BASE=TRUE

DP_INT_AUX_C_N

67 79

MAKE_BASE=TRUE

DP_INT_ML_C_P<3..0>

67 79

MAKE_BASE=TRUE

DP_INT_ML_C_N<3..0>

67 79

MAKE_BASE=TRUE

SM

SH0921

STDOFF-4.5OD2.15H-SM

1

SH0927

1

SH0963

1

SH0924

STDOFF-4.5OD1.8H-SM

1

POGO-2.3OD-4.1H-SM-LOW-FORCE

POGO-2.3OD-5.5H-SM-LOW-FORCE

ZT0931

SL-3.9X2.3-4.2x2.6

MLB_RAMCFG3

RAMCFG2:L

R0912

1/20W

201

1K

5%
MF

RAMCFG3:L

R0913

1

2

1

SH0951

SHLD-D1-MLB-T29

TH-NSP

1

1/20W

201

6 3

=PEG_D2R_P<11..8>
=PEG_D2R_N<11..8>

=PEG_R2D_C_P<11..8>
=PEG_R2D_C_N<11..8>

20 24 25

25

25

=PEG_R2D_C_P<15..12>
=PEG_R2D_C_N<15..12>

DPA_IG_AUX_CH_P
DPA_IG_AUX_CH_N

PEG_CLK100M_N
PEG_CLK100M_P

USB3_EXTC_TX_P
USB3_EXTC_TX_N
USB3_EXTC_RX_P
USB3_EXTC_RX_N
USB_EXTC_P
USB_EXTC_N
USB3_EXTD_TX_P
USB3_EXTD_TX_N
USB3_EXTD_RX_P
USB3_EXTD_RX_N
USB_EXTD_EHCI_P
USB_EXTD_EHCI_N
TP_USB_4N
TP_USB_4P
TP_USB_SDN
TP_USB_SDP
TP_USB_WLANN
TP_USB_WLANP
TP_USB_BT_HSN
TP_USB_BT_HSP
TP_USB_12N
TP_USB_12P
TP_USB_13N
TP_USB_13P

USB SIGNALS

USBHUB_DN1_P
USBHUB_DN1_N
USBHUB_DN2_P
USBHUB_DN2_N
USBHUB_DN3_P
USBHUB_DN3_N
USBHUB_DN4_P
USBHUB_DN4_N

27 60

10

10

10

NC_PCIE_CLK100M_SSDN

MAKE_BASE=TRUE

NC_PCIE_CLK100M_SSDP

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWN

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWP

MAKE_BASE=TRUE

10

10

10

10

10

10

10

10

18

18

7

17 75

7

17 75

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

19

NC_CPU_THERMDN

MAKE_BASE=TRUE

NC_CPU_THERMDP

MAKE_BASE=TRUE

NC_LCD_FSS

MAKE_BASE=TRUE

NC_PCIE_FW_D2RN

MAKE_BASE=TRUE

NC_PCIE_FW_D2RP

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CN

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CP

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_CN

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_CP

MAKE_BASE=TRUE

NC_MEM_A_CLKP<1>

MAKE_BASE=TRUE

NC_MEM_A_CLKN<1>

MAKE_BASE=TRUE

NC_MEM_B_CLKP<1>

MAKE_BASE=TRUE

NC_MEM_B_CLKN<1>

MAKE_BASE=TRUE

=PP3V3_S0_PWRCTL

8

66

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

26

SYNC_MASTER=D1_MLB_TEST

26

PAGE TITLE

26

26

26

26

26

26

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TRUE

TRUE

TRUE

TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

Unused SATA ODD Signals

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

Unused Memory Signals

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

1

R0991

10K

5%

1/20W

MF

201

2

Signal Aliases

Apple Inc.

R

12

CPU_THERMD_N
CPU_THERMD_P

LCD_FSS

67

PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P

PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P

SATA_ODD_D2R_N
SATA_ODD_D2R_P

SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

Unused PGOOD signal

CPUIMVP_AXG_PGOOD

P1V5S3RS0_RAMP_DONE
DDRREG_PGOOD

SYNC_DATE=01/27/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

9 OF 132

SHEET

9 OF 80

124578

10 78

10 78 10

7

7

7

7

17

17

17

17

17

17

17

17

12

12

12

12

17 75

17 75

17 75

17 75

D

C

B

61

65

60

A

SIZE

D

8 7 6 5 4 3

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

12

OMIT_TABLE

CRITICAL

AA11
AC12

AA10

AG11

AE11

AE10

P10

P11

W11

AA6

AC9

W10

AA7

AA3
AC8

U11

AG8

AD2
AF3

AG4
AF4

AC3
AC4

AE7

AC1
AA4

AE6

M2
P6
P1

N3
P7
P3

K1
M8
N4
R2

K3
M7
P4
T3

U7

W1

W6
V4
Y2

U6

W3

W7
T4

DMI_RX_0*
DMI_RX_1*
DMI_RX_2*
DMI_RX_3*

DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3

DMI_TX_0*
DMI_TX_1*
DMI_TX_2*
DMI_TX_3*

DMI_TX_0
DMI_TX_1
DMI_TX_2
DMI_TX_3

FDI0_TX_0*
FDI0_TX_1*
FDI0_TX_2*
FDI0_TX_3*

FDI1_TX_0*
FDI1_TX_1*
FDI1_TX_2*
FDI1_TX_3*

FDI0_TX_0
FDI0_TX_1
FDI0_TX_2
FDI0_TX_3

FDI1_TX_0
FDI1_TX_1
FDI1_TX_2
FDI1_TX_3

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

EDP_ICOMPO
EDP_COMPIO

EDP_HPD

EDP_AUX*
EDP_AUX

EDP_TX_0*
EDP_TX_1*
EDP_TX_2*
EDP_TX_3*

EDP_TX_0
EDP_TX_1
EDP_TX_2
EDP_TX_3

U1000

IVY-BRIDGE

2C-35W

BGA

(1 OF 9)

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

PCI EXPRESS BASED INTERFACE SIGNALS

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

PEG_RX_0*
PEG_RX_1*
PEG_RX_2*
PEG_RX_3*
PEG_RX_4*
PEG_RX_5*
PEG_RX_6*
PEG_RX_7*
PEG_RX_8*

PEG_RX_9*
PEG_RX_10*
PEG_RX_11*
PEG_RX_12*
PEG_RX_13*
PEG_RX_14*
PEG_RX_15*

PEG_RX_10

PEG_RX_11

PEG_RX_12

PEG_RX_13

PEG_RX_14

PEG_RX_15

PEG_TX_0*

PEG_TX_1*

PEG_TX_2*

PEG_TX_3*

PEG_TX_4*

PEG_TX_5*

PEG_TX_6*

PEG_TX_7*

PEG_TX_8*

PEG_TX_9*
PEG_TX_10*
PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*

EMBEDDED DISPLAY PORT

DMI_S2N_N<0>

7

18 72

IN

DMI_S2N_N<1>

7

18 72

IN

DMI_S2N_N<2>

7

18 72

IN

DMI_S2N_N<3>

7

18 72

IN

DMI_S2N_P<0>

7

18 72

D

C

=PP1V05_S0_CPU_VCCIO

8

10 11

13 15

R1030

24.9

1 2

1%
1/16W
MF-LF

402

OMIT_TABLE

R1031

10K

1 2

1%
1/16W
MF-LF

402

PLACE_NEAR=U1000.AF3:12.7MM

PLACE_NEAR=U1000.AG11:12.7MM

B

IN

DMI_S2N_P<1>

7

18 72

IN

DMI_S2N_P<2>

7

18 72

IN

DMI_S2N_P<3>

7

18 72

IN

DMI_N2S_N<0>

7

18 72

OUT

DMI_N2S_N<1>

7

18 72

OUT

DMI_N2S_N<2>

7

18 72

OUT

DMI_N2S_N<3>

7

18 72

OUT

DMI_N2S_P<0>

7

18 72

OUT

DMI_N2S_P<1>

7

18 72

OUT

DMI_N2S_P<2>

7

18 72

OUT

DMI_N2S_P<3>

7

18 72

OUT

FDI_DATA_N<0>

7

18 72

OUT

FDI_DATA_N<1>

18 72

OUT

FDI_DATA_N<2>

18 72

OUT

FDI_DATA_N<3>

18 72

OUT

FDI_DATA_N<4>

7

18 72

OUT

FDI_DATA_N<5>

18 72

OUT

FDI_DATA_N<6>

18 72

OUT

FDI_DATA_N<7>

18 72

OUT

FDI_DATA_P<0>

7

18 72

OUT

FDI_DATA_P<1>

18 72

OUT

FDI_DATA_P<2>

18 72

OUT

FDI_DATA_P<3>

18 72

OUT

FDI_DATA_P<4>

7

18 72

OUT

FDI_DATA_P<5>

18 72

OUT

FDI_DATA_P<6>

18 72

OUT

FDI_DATA_P<7>

18 72

OUT

FDI_FSYNC<0>

18 72

IN

FDI_FSYNC<1>

18 72

IN

FDI_INT

18 72

IN

FDI_LSYNC<0>

18 72

IN

FDI_LSYNC<1>

18 72

IN

CPU_EDP_COMP

72

EDP_HPD_L
TP_EDP_AUX_N

9

TP_EDP_AUX_P

9

TP_EDP_TX_N<0>

9

TP_EDP_TX_N<1>

9

TP_EDP_TX_N<2>

9

TP_EDP_TX_N<3>

9

TP_EDP_TX_P<0>

9

TP_EDP_TX_P<1>

9

TP_EDP_TX_P<2>

9

TP_EDP_TX_P<3>

9

3

D

S

2

Q1031

DMN5L06TK

SOT523

SYM_VER_1

PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

LCD_HPD

67

IN

G

1

EDP:YES

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9

G3
G1
G4

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

CPU_PEG_COMP

72

PLACE_NEAR=U1000.G3:12.7MM

=PEG_D2R_N<0>
=PEG_D2R_N<1>
=PEG_D2R_N<2>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_N<5>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<10>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>

=PEG_D2R_P<0>
=PEG_D2R_P<1>
=PEG_D2R_P<2>
=PEG_D2R_P<3>
=PEG_D2R_P<4>
=PEG_D2R_P<5>
=PEG_D2R_P<6>
=PEG_D2R_P<7>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_P<11>
=PEG_D2R_P<12>
=PEG_D2R_P<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>

=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_N<2>
=PEG_R2D_C_N<3>
=PEG_R2D_C_N<4>
=PEG_R2D_C_N<5>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>
=PEG_R2D_C_N<8>
=PEG_R2D_C_N<9>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<11>
=PEG_R2D_C_N<12>
=PEG_R2D_C_N<13>
=PEG_R2D_C_N<14>
=PEG_R2D_C_N<15>

=PEG_R2D_C_P<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_P<15>

R1010

24.9

1 2

=PP1V05_S0_CPU_VCCIO

1%
1/16W
MF-LF

402

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

IN

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

8

10 11 13 15

PLACE_NEAR=U1000.H43:50.8MM
PLACE_SIDE=TOP

=PPVCORE_S0_CPU

NOSTUFF

R1064

NOSTUFF

R1065

NOTE: Intel validation sense lines per

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

=PPVCORE_S0_CPU_VCCAXG

NOSTUFF

1

1

49.9

49.9

R1070

49.9

1%
1/16W
MF-LF

1/16W
MF-LF

1%
1/16W
MF-LF

402

402

2

2

PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=TOP

Note. VOLTAGE=1.25V
Note. VOLTAGE=0V

Note. VOLTAGE=1.05V
Note. VOLTAGE=0V

NOSTUFF

1

1

R1071

49.9

1%

1%
1/16W
MF-LF

402

402

2

2

PLACE_NEAR=U1000.K45:50.8MM
PLACE_SIDE=TOP

PLACE_NEAR=U1000.K43:50.8MM
PLACE_SIDE=TOP

8

13 15 43

8
16 43

NOTE: Intel does not recommend to use
this alnalog sense due to accuracy concern.

CPU_CFG<0>

10 24 72

IN

CPU_CFG<1>

10 24 72

IN

CPU_CFG<2>

10 24 72

IN

CPU_CFG<3>

10 24 72

IN

CPU_CFG<4>

10 24 72

IN

CPU_CFG<5>

10 24 72

IN

CPU_CFG<6>

10 24 72

IN

CPU_CFG<7>

10 24 72

IN

CPU_CFG<8>

24 72

IN

CPU_CFG<9>

24 72

IN

CPU_CFG<10>

24 72

IN

CPU_CFG<11>

24 72

IN

CPU_CFG<12>

24 72

13

IN

CPU_CFG<13>

24 72

IN

CPU_CFG<14>

24 72

IN

CPU_CFG<15>

24 72

IN

CPU_CFG<16>

10 24 72

IN

CPU_CFG<17>

24 72

IN

CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N

TP_CPU_VCC_DIE_SENSE

CPU_THERMD_P

9

78

OUT

CPU_THERMD_N

9

78

OUT

B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53

H43
K43

H45
K45

F48

H48
K48

BA19

NC

AV19

NC

AT21

NC

BB21

NC

BB19

NC

AY21

NC

BA22

NC

AY22

NC

AU19

NC

AU21

NC

BD21

NC

BD22

NC

BD25

NC

BD26

NC

BG22

NC

BE22

NC

BG26

NC

BE26

NC

BF23

NC

BE24

NC

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17

VCC_VAL_SENSE
VSS_VAL_SENSE

VAXG_VAL_SENSE
VSSAXG_VAL_SENSE

VCC_DIE_SENSE

RSVD_6
RSVD_7

RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
RSVD_16
RSVD_17
RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_22
RSVD_23
RSVD_24
RSVD_25
RSVD_26
RSVD_27

OMIT_TABLE

CRITICAL

U1000

BGA

(5 OF 9)

RESERVED

IVY-BRIDGE

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

RSVD_30
RSVD_31
RSVD_32
RSVD_33

RSVD_34
RSVD_35

2C-35W

RSVD_36
RSVD_37
RSVD_38

RSVD_39
RSVD_40

RSVD_41
RSVD_42
RSVD_43
RSVD_44

RSVD_45

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61

DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

BE7
BG7

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

VOLTAGE=0.75V

PPCPU_MEM_VREFDQ_A
PPCPU_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

NC

VOLTAGE=0.75V

NC
NC
NC

NC
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC

NC

TP_CPU_DC_TEST_A4
CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_D1
TP_CPU_DC_TEST_A58
CPU_DC_TEST_C59_A59

CPU_DC_TEST_C61_A61

TP_CPU_DC_TEST_D61
TP_CPU_DC_TEST_BD61

CPU_DC_TEST_BE59_BE61

CPU_DC_TEST_BG59_BG61

TP_CPU_DC_TEST_BG58
TP_CPU_DC_TEST_BG4
CPU_DC_TEST_C4_BE3_BG3

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

31 72

OUT

31 72

OUT

D

C

B

CPU_CFG<16>

CPU_CFG<7>

10 24 72

CPU_CFG<6>

10 24 72

CPU_CFG<5>

10 24 72

CPU_CFG<4>

10 24 72

CPU_CFG<2>

10 24 72

NOSTUFF

EDP:YES

1

R1042

1/20W

A

1

R1044

1K

1K

5%

5%

1/20W

MF

MF

201

201

2

2

R1045

NOSTUFF

NOSTUFF

1

1

R1046

1K

5%

1/20W

1/20W

MF

201

201

2

1

R1047

1K

1K

5%

5%

1/20W

MF

MF

201

2

2

FOR IVYBRIDGE PROCESSOR

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

10 24 72

CPU_CFG<3>

10 24 72

CPU_CFG<1>

10 24 72

CPU_CFG<0>

10 24 72

R1040

NOSTUFF

1

1K

5%

1/20W

MF

201

2

NOSTUFF

These can be Placed close to J2500 and Only for debug access

R1041

NOSTUFF

1

1K

5%

1/20W

MF

201

2

R1043

NOSTUFF

1

1K

5%

1/20W

MF

201

2

R1049

1

1K

5%

1/20W

MF

201

2

116S0066

116S0090

Intel Doc 460452 ChiefRiver Platform design guild rev1.0 section 2.2.12 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating
even if internal Graphics is disabled since they are
shared with other interfaces.

NOTE: The EDP_HPD processor input is a low voltage active low signal.
Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
to low voltage signals for the processor

(refer to latest Processor EDS for DC specifications).

If HPD is disabled while eDP interface is still enabled,
connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.
This signal can be left as no-connect if entire eDP interface is disabled.

PART NUMBER

QTY

1

1

DESCRIPTION

RES,MTL FILM,1/16W,1K,0402,SMD,LF

RES,MTL FILM,1/16W,10K,0402,SMD,LF

REFERENCE DES

R1031

R1031

CRITICAL

BOM OPTION

EDP:YES

EDP:NO

6 3

SYNC_MASTER=J30_MLB

PAGE TITLE

CPU DMI/PEG/FDI/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

10 OF 132

SHEET

10 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PP1V05_S0_CPU_VCCIO

8

10 11 13 15

NOSTUFF

1

R1100

1

R1112

140

2

1K

5%
1/20W
MF

201

2

72

72

72

1

R1113

25.5

1%

1%
1/16W

1/16W

MF-LF

MF-LF
402

402

2

1

R1101

62

5%

1/20W

MF

201

2

C

R1103

56

CPU_PROCHOT_L

39 40 61 72

BI

=PP1V5R1V35_S3_CPU_VCCDDR

8

13 16 27

PM_MEM_PWRGD

18 27 72

IN

=PP1V05_S0_CPU_VCCIO

8

10 11 13 15

B

CPU_RESET_L

24 25

IN

R1120

1/16W
MF-LF

200

402

1

1%

2

R1126

1/16W
MF-LF

1

75

1%

402

2

5%

1/20W

MF

201

R1121

R1125

1/16W
MF-LF

43.2

1/20W

130

1%

MF
201

12

1%

402

CPU_PROCHOT_R_L

12

12

CPU_PROC_SEL_L

20 72

OUT

CPU_CATERR_L

39 72

OUT

CPU_PECI

20 40 72

BI

PM_THRMTRIP_L

20 40 72

OUT

PM_SYNC

18 72

IN

CPU_PWRGD

20 24 72

IN

PM_MEM_PWRGD_R
PLT_RESET_LS1V1_L

=MEM_RESET_L

27

OUT

NOSTUFF

1

R1104

51

5%
1/20W
MF
201

2

CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>

1

1

R1114

200

2

1%
1/16W
MF-LF
402

R1115

2

NOSTUFF

4.99K

1%
1/20W
MF
201

NOSTUFF

1

R1102

1K

5%

1/20W

MF

201

2

1

R1111

10K

5%
1/20W
MF
201

2

NC

BE45

AT30

BF44
BE43
BG43

C57

PROC_DETECT*

F49

PROC_SELECT*

C49

CATERR*

A48

PECI

C45

PROCHOT*

D45

THERMTRIP*

C48

PM_SYNC

B46

UNCOREPWRGOOD

SM_DRAMPWROK

D44

RESET*

SM_DRAMRST*

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

OMIT_TABLE

CRITICAL

U1000

IVY-BRIDGE

2C-35W

BGA

(2 OF 9)

THERMAL

PWR MGMT

DDR3 MISC

DPLL_REF_CLK

DPLL_REF_CLK*

BCLK_ITP

CLOCKS

BCLK_ITP*

(IPU)
(IPU)

(IPU)
(IPU)
(IPU)

(IPU)

(IPU)
(IPU)

JTAG & BPM

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

BCLK

BCLK*

PRDY*
PREQ*

TRST*

DBR*

BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*

TCK
TMS

TDI
TDO

J3
H2

AG3
AG1

N59
N58

N53
N55

L56
L55
J58

M60
L59

K58

G58
E55
E59
G55
G59
H60
J59
J61

DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

DPLL_REF_CLK_P
DPLL_REF_CLK_N

ITPCPU_CLK100M_P
ITPCPU_CLK100M_N

XDP_CPU_PRDY_L
XDP_CPU_PREQ_L

XDP_CPU_TCK
XDP_CPU_TMS
XDP_CPU_TRST_L

XDP_CPU_TDI
XDP_CPU_TDO

XDP_DBRESET_L

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

7

17 72

IN

7

17 72

IN

17 72

IN

17 72

IN

17 72

IN

17 72

IN

24 72

OUT

24 72

IN

24 72

IN

24 72

IN

24 72

IN

24 72

IN

24 72

OUT

24 25 72

OUT

24 72

BI

24 72

BI

24 72

BI

24 72

BI

24 72

BI

24 72

BI

24 72

BI

24 72

BI

D

C

B

A

6 3

SYNC_MASTER=J30_MLB

PAGE TITLE

CPU CLOCK/MISC/JTAG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

11 OF 132

SHEET

11 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

OMIT_TABLE

CRITICAL

U1000

BGA

(3 OF 9)

2C-35W

IVY-BRIDGE

MEMORY CHANNEL A

SA_CK_0

SA_CK_0*

SA_CKE_0

SA_CK_1

SA_CK_1*

SA_CKE_1

SA_CS_0*
SA_CS_1*

SA_ODT_0
SA_ODT_1

SA_DQS_0*
SA_DQS_1*
SA_DQS_2*
SA_DQS_3*
SA_DQS_4*
SA_DQS_5*
SA_DQS_6*
SA_DQS_7*

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15

AU36
AV36

AY26

AT40
AU40

BB26

BB40
BC41

AY40
BA41

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_A<14>
MEM_A_A<15>

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

9

OUT

9

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 73

BI

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

28 30 73

OUT

7

29 73

7

29 73

7

29 73

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

29 73

7

29 73

7

29 73

7

29 73

7

29 73

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

29 73

7

29 73

7

29 73

7

29 73

7

29 73

7

29 73

29 30 73

29 30 73

29 30 73

29 30 73

29 30 73

29 30 73

MEM_B_DQ<0>

BI

MEM_B_DQ<1>

BI

MEM_B_DQ<2>

BI

MEM_B_DQ<3>

BI

MEM_B_DQ<4>

BI

MEM_B_DQ<5>

BI

MEM_B_DQ<6>

BI

MEM_B_DQ<7>

BI

MEM_B_DQ<8>

BI

MEM_B_DQ<9>

BI

MEM_B_DQ<10>

BI

MEM_B_DQ<11>

BI

MEM_B_DQ<12>

BI

MEM_B_DQ<13>

BI

MEM_B_DQ<14>

BI

MEM_B_DQ<15>

BI

MEM_B_DQ<16>

BI

MEM_B_DQ<17>

BI

MEM_B_DQ<18>

BI

MEM_B_DQ<19>

BI

MEM_B_DQ<20>

BI

MEM_B_DQ<21>

BI

MEM_B_DQ<22>

BI

MEM_B_DQ<23>

BI

MEM_B_DQ<24>

BI

MEM_B_DQ<25>

BI

MEM_B_DQ<26>

BI

MEM_B_DQ<27>

BI

MEM_B_DQ<28>

BI

MEM_B_DQ<29>

BI

MEM_B_DQ<30>

BI

MEM_B_DQ<31>

BI

MEM_B_DQ<32>

BI

MEM_B_DQ<33>

BI

MEM_B_DQ<34>

BI

MEM_B_DQ<35>

BI

MEM_B_DQ<36>

BI

MEM_B_DQ<37>

BI

MEM_B_DQ<38>

BI

MEM_B_DQ<39>

BI

MEM_B_DQ<40>

BI

MEM_B_DQ<41>

BI

MEM_B_DQ<42>

BI

MEM_B_DQ<43>

BI

MEM_B_DQ<44>

BI

MEM_B_DQ<45>

BI

MEM_B_DQ<46>

BI

MEM_B_DQ<47>

BI

MEM_B_DQ<48>

BI

MEM_B_DQ<49>

BI

MEM_B_DQ<50>

BI

MEM_B_DQ<51>

BI

MEM_B_DQ<52>

BI

MEM_B_DQ<53>

BI

MEM_B_DQ<54>

BI

MEM_B_DQ<55>

BI

MEM_B_DQ<56>

BI

MEM_B_DQ<57>

BI

MEM_B_DQ<58>

BI

MEM_B_DQ<59>

BI

MEM_B_DQ<60>

BI

MEM_B_DQ<61>

BI

MEM_B_DQ<62>

BI

MEM_B_DQ<63>

BI

MEM_B_BA<0>

OUT

MEM_B_BA<1>

OUT

MEM_B_BA<2>

OUT

MEM_B_CAS_L

OUT

MEM_B_RAS_L

OUT

MEM_B_WE_L

OUT

AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9

BD9
BD13
BF12

BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60

BG39
BD42
AT22

AV43
BF40
BD45

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS*
SB_RAS*
SB_WE*

AP11

AJ10

AR11

AT13
AU13

BA13
BB11

AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

AG6
AJ6

AL6

AJ8
AL8
AL7

AP6
AU6
AV9
AR6
AP8

BC7
BB7

BA7
BA9
BB9

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS*
SA_RAS*
SA_WE*

MEM_A_DQ<0>

7

28 73

BI

MEM_A_DQ<1>

28 73

BI

MEM_A_DQ<2>

7

28 73

BI

MEM_A_DQ<3>

7

28 73

BI

MEM_A_DQ<4>

7

28 73

D

C

B

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

28 73

7

28 73

7

28 73

7

28 73

7

28 73

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

28 73

7

28 73

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

7

28 73

28 30 73

28 30 73

28 30 73

28 30 73

28 30 73

28 30 73

BI

MEM_A_DQ<5>

BI

MEM_A_DQ<6>

BI

MEM_A_DQ<7>

BI

MEM_A_DQ<8>

BI

MEM_A_DQ<9>

BI

MEM_A_DQ<10>

BI

MEM_A_DQ<11>

BI

MEM_A_DQ<12>

BI

MEM_A_DQ<13>

BI

MEM_A_DQ<14>

BI

MEM_A_DQ<15>

BI

MEM_A_DQ<16>

BI

MEM_A_DQ<17>

BI

MEM_A_DQ<18>

BI

MEM_A_DQ<19>

BI

MEM_A_DQ<20>

BI

MEM_A_DQ<21>

BI

MEM_A_DQ<22>

BI

MEM_A_DQ<23>

BI

MEM_A_DQ<24>

BI

MEM_A_DQ<25>

BI

MEM_A_DQ<26>

BI

MEM_A_DQ<27>

BI

MEM_A_DQ<28>

BI

MEM_A_DQ<29>

BI

MEM_A_DQ<30>

BI

MEM_A_DQ<31>

BI

MEM_A_DQ<32>

BI

MEM_A_DQ<33>

BI

MEM_A_DQ<34>

BI

MEM_A_DQ<35>

BI

MEM_A_DQ<36>

BI

MEM_A_DQ<37>

BI

MEM_A_DQ<38>

BI

MEM_A_DQ<39>

BI

MEM_A_DQ<40>

BI

MEM_A_DQ<41>

BI

MEM_A_DQ<42>

BI

MEM_A_DQ<43>

BI

MEM_A_DQ<44>

BI

MEM_A_DQ<45>

BI

MEM_A_DQ<46>

BI

MEM_A_DQ<47>

BI

MEM_A_DQ<48>

BI

MEM_A_DQ<49>

BI

MEM_A_DQ<50>

BI

MEM_A_DQ<51>

BI

MEM_A_DQ<52>

BI

MEM_A_DQ<53>

BI

MEM_A_DQ<54>

BI

MEM_A_DQ<55>

BI

MEM_A_DQ<56>

BI

MEM_A_DQ<57>

BI

MEM_A_DQ<58>

BI

MEM_A_DQ<59>

BI

MEM_A_DQ<60>

BI

MEM_A_DQ<61>

BI

MEM_A_DQ<62>

BI

MEM_A_DQ<63>

BI

MEM_A_BA<0>

OUT

MEM_A_BA<1>

OUT

MEM_A_BA<2>

OUT

MEM_A_CAS_L

OUT

MEM_A_RAS_L

OUT

MEM_A_WE_L

OUT

OMIT_TABLE

CRITICAL

2C-35W

SB_CK_0

SB_CK_0*

SB_CKE_0

SB_CK_1

SB_CK_1*

U1000

BGA

(4 OF 9)

SB_CKE_1

IVY-BRIDGE

SB_CS_0*
SB_CS_1*

SB_ODT_0
SB_ODT_1

SB_DQS_0*
SB_DQS_1*
SB_DQS_2*
SB_DQS_3*
SB_DQS_4*
SB_DQS_5*
SB_DQS_6*
SB_DQS_7*

SB_DQS_0

MEMORY CHANNEL B

SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15

BA34
AY34

AR22

BA36
BB36

BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CKE<1>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

9

OUT

9

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 73

BI

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

29 30 73

OUT

D

C

B

A

6 3

SYNC_MASTER=J30_MLB

PAGE TITLE

CPU DDR3 INTERFACES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

12 OF 132

SHEET

12 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

=PPVCORE_S0_CPU_VCCAXG

8

10 13 16 43

=PPVCORE_S0_CPU

8

10 13 15

43

A26

VCC_1

A29

D

C

B

A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76

A

OMIT_TABLE

CRITICAL

U1000

BGA

(6 OF 9)

2C-35W

IVY-BRIDGE

PEG AND DDR

CORE SUPLLY

SENSE SVID QUIET

VSS_SENSE_VCCIO

VCCIO_1
VCCIO_3
VCCIO_4
VCCIO_5
VCCIO_6
VCCIO_7
VCCIO_8

VCCIO_9
VCCIO_10
VCCIO_11
VCCIO_12
VCCIO_13
VCCIO_14
VCCIO_15
VCCIO_16
VCCIO_17
VCCIO_18
VCCIO_19
VCCIO_20
VCCIO_21
VCCIO_22
VCCIO_23
VCCIO_24
VCCIO_25
VCCIO_26
VCCIO_27
VCCIO_28
VCCIO_29

VCCIO_30
VCCIO_31
VCCIO_32
VCCIO_33
VCCIO_34
VCCIO_35
VCCIO_36
VCCIO_37
VCCIO_38
VCCIO_39
VCCIO_40
VCCIO_41
VCCIO_42
VCCIO_43
VCCIO_44
VCCIO_45
VCCIO_46
VCCIO_47
VCCIO_48
VCCIO_49

VCCIO_50
VCCIO_51

VCCIO_SEL

VCCPQE_1
VCCPQE_2

RAIL

VIDALERT*

VIDSCLK

VIDSOUT

VCC_SENSE
VSS_SENSE

LINES

VCCIO_SENSE

=PP1V05_S0_CPU_VCCIO

(NOT controlled by VCCIO_SEL)

AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

W16
W17

BC22

AM25
AN22

A44
B43
C44

F43
G43

AN16
AN17

Fixed at 1.05V

IVB supports 1.05V VCCIO.
VCCIO_SEL can be NC.

CPU_VCCIO_SEL

=PP1V05_S0_CPU_VCCPQE

CPU_VIDALERT_L_R
CPU_VIDSCLK_R
CPU_VIDSOUT_R

CPU_VCCSENSE_P
CPU_VCCSENSE_N

CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N

8

10 11 13 15

=PP3V3_S0_CPU_VCCIO_SEL

NOSTUFF

1

R1320

10K

5%

1/20W

MF

201

2

8

15

8

1

R1302

130

PLACE_NEAR=U1000.C44:2.54mm

1%
1/16W
MF-LF
402

2

201

201

201

PLACE_NEAR=U1000.F43:50.8mm

PLACE_NEAR=U1000.G43:50.8mm

R1310

1 2

1/20W

R1311

1 2

1/20W

0

R1312

1 2

1/20W

0

PLACE_SIDE=TOP

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V
Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACE_SIDE=TOP

=PP1V05_S0_CPU_VCCIO

PLACE_NEAR=R1310.2:2.54mm
1

R1300

75

1%
1/20W
MF
201

2

MF435%

MF5%

MF5%

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

PLACE_NEAR=U1000.A44:38mm

=PP1V05_S0_CPU_VCCIO

1

100

1/16W
MF-LF

100

1/16W
MF-LF

1

R1362

100

1%

402

2

1

1%

402

2

PLACE_NEAR=U1000.AN16:50.8mm

1%

PLACE_SIDE=TOP

1/16W
MF-LF
402

2

1

R1363

100

1%
1/16W
MF-LF
402

2

R1360

R1361

8

10 11 13 15

IN

OUT

BI

=PPVCORE_S0_CPU

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

61 72

OUT

61 72

OUT

63 72

OUT

63 72

OUT

PLACE_NEAR=U1000.AN17:50.8mm

PLACE_SIDE=TOP

61 72

61 72

61 72

10 13 16 43

PLACE_NEAR=U1000.F45:50.8mm

61 72

OUT

61 72

OUT

8

10 13 15 43

8

10 11 13 15

PLACE_NEAR=U1000.G45:50.8mm

=PPVCORE_S0_CPU_VCCAXG

8

R1370

PLACE_SIDE=TOP

CPU_AXG_SENSE_P
CPU_AXG_SENSE_N

PLACE_SIDE=TOP

100

1/16W
MF-LF

=PP1V8_S0_CPU_VCCPLL_R

8

15

R1371

100

1/16W
MF-LF

1

1%

402

2

1

1%

402

2

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

=PPVCCSA_S0_CPU

8

13 16

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46

N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

F45
G45

BB3
BC1
BC4

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20

VAXG_1
VAXG_2
VAXG_3
VAXG_4
VAXG_5
VAXG_6
VAXG_7
VAXG_8
VAXG_9
VAXG_10
VAXG_11
VAXG_12
VAXG_13
VAXG_14
VAXG_15
VAXG_16
VAXG_17
VAXG_18
VAXG_19
VAXG_20
VAXG_21
VAXG_22
VAXG_23
VAXG_24
VAXG_25
VAXG_26
VAXG_27
VAXG_28
VAXG_29
VAXG_30
VAXG_31
VAXG_32
VAXG_33
VAXG_34
VAXG_35
VAXG_36
VAXG_37
VAXG_38
VAXG_39
VAXG_40
VAXG_41
VAXG_42
VAXG_43
VAXG_44
VAXG_45
VAXG_46
VAXG_47
VAXG_48
VAXG_49
VAXG_50
VAXG_51
VAXG_52
VAXG_53
VAXG_54
VAXG_55
VAXG_56

VAXG_SENSE
VSSAXG_SENSE

VCCPLL_1
VCCPLL_2
VCCPLL_3

VCCSA_1
VCCSA_2
VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8
VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13
VCCSA_14
VCCSA_15
VCCSA_16

OMIT_TABLE

CRITICAL

U1000

BGA

(7 OF 9)

IVY-BRIDGE

GRPHICS

DDR3-1.5V RAILS

(IPU)

QUIET

SENSE

(IPU)

LINE

SENSE

1.8V

RAIL

SA RAIL

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4

2C-35W

VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26

VCCDQ_1
VCCDQ_2

RAIL

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

LINE

VCCSA_VID_0
VCCSA_VID_1

SM_VREF

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

AM28
AN26

BC43
BA43

U10

D48
D49

AY43

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

=PP1V5R1V35_S3_CPU_VCCDDR

=PP1V5R1V35_S3_CPU_VCCDDR

8

11 13 16 27

PLACE_NEAR=U1000.U10:50.8mm

PLACE_NEAR=U1000.BC43:50.8mm

PLACE_SIDE=TOP

=PP1V5_S3_CPU_VCCDQ

R1314

10K

5%
1/20W
MF

201

CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N

CPU_VCCSASENSE
CPU_VCCSA_VID<0>

CPU_VCCSA_VID<1>

CPU_SM_VREF

VOLTAGE=0.75V

PLACE_NEAR=U1000.BA43:50.8mm

1

1

R1313

10K

5%

1/20W

MF

201

2

2

=PP1V5R1V35_S3_CPU_VCCDDR

8

11 13 16 27

Note. VOLTAGE=1.05V
Note. VOLTAGE=0V

PLACE_SIDE=TOP

R1330

PLACE_NEAR=U1000.BJ44:2.54mm

PLACE_NEAR=U1000.BJ44:2.54mm

R1331

PLACE_NEAR=U1000.BJ44:2.54mm

SYNC_MASTER=J30_MLB

PAGE TITLE

CPU POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

13 16

58 72

OUT

13

1

1K

1%
1/16W
MF-LF

402

2

1

1K

1%
1/16W
MF-LF

402

2

6 3

8

11 13 16 27

=PPVCCSA_S0_CPU

R1382

100

1/16W
MF-LF

1

R1380

100

1%
1/16W
MF-LF

402

2

8

16

58 72

1

R1381

100

1%
1/16W
MF-LF

402

2

CPU_SM_VREF

1

C1330

0.1UF

10%
16V

2

X7R-CERM
0402

SYNC_DATE=07/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

PAGE

13 OF 132

SHEET

124578

1

1%

402

2

OUT

<BRANCH>

13 OF 80

58 72

13

SIZE

D

C

B

A

D

8 7 6 5 4 3

OMIT_TABLE

OMIT_TABLE

CRITICAL

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M11
M15
M58
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P9
P14
P16
P18
P21
P58
P59
R4
R17
R20
R46
T1
T47
T50
T51
T52
T53
T55
T56
U8
U13
V20
V61
W8
W13
W15
W18
W21
W46
Y4
Y47
Y58
Y59

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

BG13

VSS

BG17

VSS

BG21

VSS

BG24

VSS

BG28

VSS

D

C

B

BG37
BG41
BG45
BG49
BG53

C29
C35
C40

D10
D14
D18
D22
D26
D29
D35
D40
D43
D46
D50
D54
D58

E25
E29
E35
E40
F13
F15
F19
F29
F35
F40
F55

G48
G51
G61

H10
H14
H17
H21
H53
H58

J49
J55

K11
K21
K51
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D4

VSS

D6

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G6

VSS
VSS
VSS
VSS

H4

VSS
VSS
VSS
VSS
VSS
VSS
VSS

J1

VSS
VSS
VSS

K8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M4

VSS

M6

VSS

U1000

BGA

(9 OF 9)

VSS

2C-35W

IVY-BRIDGE

A

AA13
AA50
AA51
AA52
AA53
AA55
AA56
AB16
AB18
AB21
AB48
AB61

AC10
AC14
AC46

AD17
AD20
AD61

AE13

AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59

AG10
AG14
AG18
AG47
AG52
AG61

AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61

AM13
AM20
AM22
AM26
AM30

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
AA1
AA8

AC6

AD4

AE8

AF1

AG7

AH4

AJ7

AK1

AM4

A9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CRITICAL

U1000

BGA

(8 OF 9)

VSS

IVY-BRIDGE

2C-35W

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM34
AM38
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP7
AP10
AP51
AP55
AR7
AR13
AR17
AR21
AR41
AR48
AR61
AT4
AT14
AT19
AT36
AT45
AT52
AT58
AU1
AU7
AU11
AU28
AU32
AU51
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW7
AW13
AW43
AW61
AY4
AY9
AY14
AY19
AY30
AY36
AY41
AY45
AY49
AY55
AY58
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC5
BC13
BC57
BD8
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BE5
BG9

SYNC_MASTER=J30_MLB

PAGE TITLE

CPU GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

12

SYNC_DATE=07/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

14 OF 132

SHEET

14 OF 80

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

All INTEL recommendations from Intel doc #458544 Chief River Platform Power Design Guide v0p9

CPU VCORE DECOUPLING

Intel recommendation (Table 7-2): Option 2: 35x 2.2uF, 12x 22uF, 4x 470uF, or Option 3: 35x 2.2uF, 6x 22uF, 6x 330 uF

=PPVCORE_S0_CPU

8

10 13 43

D

CRITICAL

1

C1600

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1625

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1604

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1627

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1606

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1628

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1607

2.2UF 2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1631

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

2

CRITICAL

1

2

C1608

20%

6.3V
CERM
402-2

C1632

2.2UF

20%

6.3V
CERM
402-2

CRITICAL

1

C1609

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1635

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1610

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1637

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1612

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1638

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1613

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1639

2.2UF

20%

6.3V

2

CERM CERM
402-2

CRITICAL

1

C1615

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1640

2.2UF

20%

6.3V

2

402-2

CRITICAL

1

C1617

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1623

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL CRITICAL

1

C1641

2.2UF

20%

6.3V

2

CERM
402-2

1

C1642

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1624

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1643

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1644

2.2UF 2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

2

C1645

20%

6.3V
CERM
402-2

CRITICAL CRITICAL

1

C1647

2.2UF

20%

6.3V

2

CERM
402-2

1

C1648

2.2UF

20%

6.3V

2

CERM
402-2

12

D

CRITICAL

1

C1650

2.2UF

20%

6.3V

2

CERM
402-2

PLACEMENT_NOTE (C1655-C1666):

CRITICAL

1

C1646

20UF 20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C168F

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C16A0

20UF

20%
2V

2

X6T-CERM
0402

C

CRITICAL

1

C16A1

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL CRITICAL

NO STUFF

1

C16A2

20UF

20%
2V

2

X6T-CERM
0402

1

C16A3

20UF

20%

2V

2

X6T-CERM
0402

Place close to U1000 on top side.

CRITICAL

1

C1655

20UF

20%

2V

2

X6T-CERM
0402

PLACEMENT_NOTE (C1667-C1679):
Place close to U1000 on bottom side.

Place close to U1000 on bottom side.

Place close to U1000 on bottom side.

Place close to U1000 on bottom side.

Place close to U1000 on bottom side.

Place close to U1000 on bottom side.

CRITICAL

NO STUFF

1

C1675

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1651

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

NO STUFF

1

C1656

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL CRITICAL

NO STUFF NO STUFF

1

C1668

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1652

2.2UF

20%

6.3V

2

CERM
402-2

CRITICAL

1

C1657

20UF

20%
2V

2

X6T-CERM
0402

1

C1669

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1653

2.2UF

20%

6.3V

2

CERM
402-2

1

2

CRITICAL

1

C1658

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1670

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

C1654

2.2UF

20%

6.3V
CERM
402-2

CRITICAL

NO STUFF

1

C1659

20UF 20UF

20%
2V

2

X6T-CERM
0402

1

2

CRITICAL

1

C1671

20UF

20%
2V

2

X6T-CERM
0402

1

2

CRITICAL

NO STUFF

C1660

20%
2V
X6T-CERM
0402

CRITICAL

NO STUFF

C1672

20UF

20%
2V
X6T-CERM
0402

CRITICAL

1

C1661

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1673

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL2VCRITICAL

NO STUFF NO STUFF

1

C1662

20UF

20%

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1649

20UF

20%
2V

2

X6T-CERM
0402

1

C1663

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C164A

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1664

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1676

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1665

20UF 20UF

20%
2V

2

X6T-CERM
0402

1

2

CRITICAL

1

C1677

20UF

20%
2V

2

X6T-CERM
0402

1

2

CRITICAL

NO STUFF

C1666

20%
2V
X6T-CERM
0402

CRITICAL

C1678

20UF

20%
2V
X6T-CERM
0402

CRITICAL

1

C166A

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1679

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C166B

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C165C

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C166C

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C165D

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C166D

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C165E

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C166E

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF NO STUFF

1

C165F

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C166F

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C164E

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C165A

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C164B

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF NO STUFF

1

C165B

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C164C

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1667

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C164D

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1674

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C164F

20UF

20%
2V

2

X6T-CERM
0402

C

PLACEMENT_NOTE (C1640-C1645):

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

Place near inductors on bottom side.

1

C1680

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

C1681

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

C1682

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

C1683

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

1

C168D

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C168E

270UF

20%
2V

2

TANT
CASE-B2-SM

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation (Table 7-7): 26x 1uF, 10x 10uF, 2x 330uF

PLACEMENT_NOTE (C1684-C167F):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

=PP1V05_S0_CPU_VCCIO

8

10 11 13

B

Place on bottom side of U1000

1

C1684

1UF

10%
10V

2

X5R-CERM
0402

1

C1697

1UF

10%
10V

2

X5R-CERM
0402

1

C1685

2

1

C1698

2

1UF

10%
10V
X5R-CERM
0402

1UF

10%

10V
X5R-CERM
0402

1

C1686

2

1

C1699

2

1UF

10%
10V
X5R-CERM
0402

1UF

10%
10V
X5R-CERM
0402

1

2

1

C169A

2

C1687

1UF

10%
10V
X5R-CERM
0402

1UF

10%
10V
X5R-CERM
0402

1

2

1

2

C1688

1UF

10%
10V
X5R-CERM
0402

C169B

1UF

10%
10V
X5R-CERM
0402

1

C1689

1UF

2

1

C169C

1UF

2

10%
10V
X5R-CERM
0402

10%
10V
X5R-CERM
0402

1

2

1

C169D

1UF

10%
10V

2

X5R-CERM
0402

C1690

1UF

10%
10V
X5R-CERM
0402

1

2

1

C169E

1UF

2

C1691

1UF

10%
10V
X5R-CERM
0402

10%
10V
X5R-CERM
0402

1

C1692

1UF

10%
10V

2

X5R-CERM
0402

1

C169F

1UF

10%
10V

2

X5R-CERM
0402

1

2

1

2

C1693

1UF

10%
10V
X5R-CERM
0402

C161A

1UF

10%
10V
X5R-CERM
0402

1

2

1

2

C1694

1UF

10%
10V
X5R-CERM
0402

C161B

1UF

10%
10V
X5R-CERM
0402

1

2

1

2

C1695

1UF

10%
10V
X5R-CERM
0402

C161C

1UF

10%
10V
X5R-CERM
0402

1

2

1

2

C1696

1UF

10%
10V
X5R-CERM
0402

C161D

1UF

10%
10V
X5R-CERM
0402

=PP1V8_S0_CPU_VCCPLL

8

PLACEMENT_NOTE (C1672-C1681):

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

Place near U1000 on bottom side

1

C161E

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C161F

2

10UF

20%

6.3V
CERM-X5R
0402-1

1

C162A

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C162B

2

10UF

20%

6.3V
CERM-X5R
0402-1

1

C162C

2

10UF

20%

6.3V
CERM-X5R
0402-1

1

C162D

2

10UF

20%

6.3V
CERM-X5R
0402-1

1

C162E

2

10UF

20%

6.3V
CERM-X5R
0402-1

1

C167A

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

2

C167B

10UF

20%

6.3V
CERM-X5R
0402-1

1

C167C

10UF

2

20%

6.3V
CERM-X5R
0402-1

CPU VCCPLL DECOUPLING

Intel recommendation (table 7-5): 2x 1uF, 1x 330uF

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

PLACEMENT_NOTE (C1646-C1671):

R1600

0

1 2

5%
1/16W
MF-LF

402

1

C160X

1UF

10%
10V

2

X5R
402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

1

2

CPU VCCPLL Low pass filter

C160Y

1UF

10%
10V
X5R
402

=PP1V8_S0_CPU_VCCPLL_R

PLACE_NEAR=U1000.AK61:5mm

1

C160Z

270UF

20%
2V

2

TANT
CASE-B2-SM

8

13

PLACE_NEAR=U1000.AK61:5mm

1

C168C

270UF

20%
2V

2

TANT
CASE-B2-SM

B

1

C167D

270UF

20%
2V

2

TANT

A

CASE-B2-SM

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1601

0.010

1 2

1%

1/4W

MF

0603

1

C167E

270UF

20%
2V

2

TANT
CASE-B2-SM

=PP1V05_S0_CPU_VCCPQE

1

C167F

1UF

10%
10V

2

X5R
402

1

C168A

270UF

20%
2V

2

TANT
CASE-B2-SM

8

13

1

C168B

270UF

20%
2V

2

TANT
CASE-B2-SM

Note:The smallest 10mOhm available in the library are 0805s

6 3

SYNC_MASTER=MASTER

PAGE TITLE

CPU DECOUPLING-I

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

16 OF 132

SHEET

15 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

VAXG DECOUPLING

Intel recommendation (Table 7-4) for GT2 3.9mOhm LL: 11x 1uF, 6x 10uF, 6x 22uF, 2x 470uF

12

=PPVCORE_S0_CPU_VCCAXG

8

10 13 43

D

PLACEMENT_NOTE (C1700-C1710):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

Place on bottom side of U1000

CRITICAL

1

C1700

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1701

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1702

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1703

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1704

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1705

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1706

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1707

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1708

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1709

1UF

10%
10V

2

X5R-CERM
0402

CRITICAL

1

C1710

1UF

10%
10V

2

X5R-CERM
0402

D

PLACEMENT_NOTE (C1711-C1716):

CRITICAL

1

C1711

10UF

20%

6.3V

2

CERM-X5R
0402-1

CRITICAL

1

C1712

10UF

20%

6.3V

2

CERM-X5R
0402-1

CRITICAL

1

C1713

10UF

20%

6.3V

2

CERM-X5R
0402-1

CRITICAL

1

C1714

10UF

20%

6.3V

2

CERM-X5R
0402-1

CRITICAL

1

C1715

10UF

20%

6.3V

2

CERM-X5R
0402-1

CRITICAL

1

C1716

10UF

20%

6.3V

2

CERM-X5R
0402-1

PLACEMENT_NOTE (C1717-C1722):

CRITICAL

1

C1717

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1718

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1719

20UF

20%
2V

2

X6T-CERM

CRITICAL

1

C1720

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1721

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

1

C1722

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1725

20UF

20%
2V

2

X6T-CERM
04020402

CRITICAL

NO STUFF

1

C1726

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1727

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1728

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C1729

20UF

20%
2V

2

X6T-CERM
0402

CRITICAL

NO STUFF

1

C172A

20UF

20%
2V

2

X6T-CERM
0402

PLACEMENT_NOTE (C1723-C1724):

Place near inductors on bottom side.

Place near inductors on bottom side.

1

C1723

470UF-4MOHM

C

23

20%

2.0V
POLY-TANT
D2T-SM1

1

C1724

470UF-4MOHM

20%

2.0V

23

POLY-TANT
D2T-SM1

C

CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Table 7-11): 10x 1uF, 8x 10uF, 1x 330uF

=PP1V5R1V35_S3_CPU_VCCDDR

8

11 13 27

B

A

PLACEMENT_NOTE (C1738-C1747):

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U1000

Place on bottom side of U100.

1

C1738

1UF

10%
10V

2

X5R-CERM
0402

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

Place close to U1000 on bottom side

1

C1748

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1756

270UF

20%
2V

2

TANT
CASE-B2-SM

1

C1739

1UF

10%
10V

2

X5R-CERM
0402

1

C1749

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1770

270UF

20%
2V

2

TANT
CASE-B2-SM

1

2

1

2

C1740

1UF

10%
10V
X5R-CERM
0402

C1750

10UF

20%

6.3V
CERM-X5R
0402-1

1

2

1

C1751

10UF

20%

6.3V

2

CERM-X5R
0402-1

C1741

1UF

10%
10V
X5R-CERM
0402

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1702

0.010

1 2

1/4W

0603

1%

MF

=PP1V5_S3_CPU_VCCDQ

1

2

C1757

1UF

10%
10V
X5R
402

8

13

6 3

1

C1742

1UF

10%
10V

2

X5R-CERM
0402

1

C1752

10UF

20%

6.3V

2

CERM-X5R
0402-1 0402-1

1

C1743

1UF

10%
10V

2

X5R-CERM
0402

1

C1753

10UF 10UF

20%

6.3V

2

CERM-X5R

1

2

1

2

C1744

1UF

10%
10V
X5R-CERM
0402

C1754

10UF

20%

6.3V
CERM-X5R
0402-1

1

2

1

C1755

2

C1745

1UF

10%
10V
X5R-CERM
0402

20%

6.3V
CERM-X5R
0402-1

1

2

C1746

1UF

10%
10V
X5R-CERM
0402

1

C1747

1UF

10%
10V

2

X5R-CERM
0402

=PPVCCSA_S0_CPU

8

13

CPU VCCSA DECOUPLING

Intel recommendation (Table 7-9): 5x 1uf, 5x 10uf, 1x 330uf

PLACEMENT_NOTE (C1758-C1762):

Place on bottom side of U1000

Place on bottom side of U100.

Place on bottom side of U1000

Place on bottom side of U1000

1

2

1

2

1

C1768

270UF

20%
2V

2

TANT
CASE-B2-SM

C1758

1UF

10%
10V
X5R-CERM
0402

C1763

10UF

20%

6.3V
CERM-X5R
0402-1

1

C1759

1UF

10%
10V

2

X5R-CERM
0402

1

C1764

10UF

20%

6.3V

2

CERM-X5R
0402-1

1

C1769

270UF

20%
2V

2

TANT
CASE-B2-SM

1

2

1

C1765

10UF

2

C1760

1UF

10%
10V
X5R-CERM
0402

20%

6.3V
CERM-X5R
0402-1

1

C1761

1UF

10%
10V

2

X5R-CERM
0402

1

C1766

10UF

20%

6.3V

2

CERM-X5R
0402-1 0402-1

SYNC_MASTER=MASTER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

C1762

1UF

10%
10V

2

X5R-CERM
0402

1

C1767

10UF

20%

6.3V

2

CERM-X5R

CPU DECOUPLING-II

Apple Inc.

R

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

17 OF 132

SHEET

16 OF 80

124578

SIZE

B

A

D

8 7 6 5 4 3

SYSCLK_CLK32K_RTC

25 74

IN

RTC_RESET_L

17

PCH_SRTCRST_L

17

PCH_INTRUDER_L

D

VSel strap not functional (VCCVRM = 1.8V)

C

=PPVRTC_G3_PCH

B

A

17

PCH_INTVRMEN_L

17

HDA_BIT_CLK_R

17 75

HDA_SYNC_R

17 75

PCH_SPKR

17

HDA_RST_R_L

17 75

HDA_SDIN0

51 75

IN

TP_HDA_SDIN1

7

TP_HDA_SDIN2

7

TP_HDA_SDIN3

7

HDA_SDOUT_R

17 25 75

JTAG_ISP_TMS

17 20

OUT

ENET_MEDIA_SENSE_RDIV

17

IN

XDP_PCH_TCK

24

IN

XDP_PCH_TMS

24

IN

XDP_PCH_TDI

24

IN

XDP_PCH_TDO

24

OUT

SPI_CLK_R

41 75

OUT

SPI_CS0_R_L

41 75

OUT

TP_SPI_CS1_L

7

SPI_MOSI_R

41 75

OUT

SPI_MISO

41 75

IN

8

18 21

R1800

330K

=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_TBT_PCH_GPIO

R1876
R1877

R1878
R1834

R1833
R1842

R1869
R1844
R1845
R1847
R1814
R1815
R1843

R1846
R1848
R1853
R1854
R1855

R1879

OMIT_TABLE

U1800

A19
C19

NC

F19

A23

K22

C21

H35

H37

N1

F35

D36
B36
C35
A35

K37

K35
M35

M17

M15

U12

M12

AD12

AB8

AB6

W8

Y2

1

R1802

20K

1

R1801

1M

5%
1/20W
MF
201

2

1/20W

C1802

1.0UF

6.3V

0201-MUR

8

18 19 20

8

18 19 20 25 35

8

20

1/20W

1/20W
1/20W

1/20W
1/20W

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

1/20W
1/20W
1/20W
1/20W
1/20W

1/20W

20%
X5R

201

1

5%

1/20W

MF

201

2

NO STUFF

10K

1 2

4.7K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

2 1

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.

1

R1803

20K

5%

5%
1/20W

MF

MF
201

2

2

RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L

1

1

C1803

1.0UF

20%

6.3V

2

2

X5R
0201-MUR

MF 2015%

MF 2015%
MF 2015%

MF 2015%
MF 2015%

MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%

MF 2015%
MF 2015%
MF 2015%
MF 2015%
MF 2015%

MF 2015%

PCH-PPT-MB-SFF-ES1

RTCX1
RTCX2

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

(IPD-BOOT)

SPKR

(IPD-PLTRST#)

HDA_RST*

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDO

(IPD-BOOT)

HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13

JTAG_TCK

(IPD)

JTAG_TMS

(IPU)

JTAG_TDI

(IPU)

JTAG_TDO

SPI_CLK

SPI_CS0*

SPI_CS1*

SPI_MOSI

(IPD-BOOT)

SPI_MISO

(IPU)

JTAG_ISP_TMS
PCH_SPKR

PCH_SATALED_L
DP_AUXCH_ISOL

SATARDRVR_EN
FW_CLKREQ_L

AP_CLKREQ_L
EXCARD_CLKREQ_L
JTAG_DPMUXUC_TRST_L
ENET_CLKREQ_L
PEG_CLKREQ_L
TBT_CLKREQ_L
SSD_CLKREQ_L

PEGCLKRQA_L_GPIO47
PEGCLKRQB_L_GPIO56
SMBUS_PCH_ALERT_L
USB_EXTB_SEL_XHCI
USB_EXTD_SEL_XHCI

ENET_MEDIA_SENSE_RDIV

QP8D-MM915462

(1 OF 10)

(IPD)
(IPD)
(IPD)
(IPD)

17

17

17

17

BGA

RTCSPI

IHDA

JTAG

(IPU)

LPC

LDRQ1*/GPIO23

(IPU)

SATA

SATA0GP/GPIO21
SATA1GP/GPIO19

17

17

17

17

17

17 75

17 75

17 75

17 25 75

FWH4/LFRAME*

(IPU)

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

(IPU)

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO
SATAICOMPI

SATA3RCOMPO

SATA3COMPI
SATA3RBIAS

SATALED*

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME_R_L

HDA_BIT_CLK_R
HDA_SYNC_R
HDA_RST_R_L
HDA_SDOUT_R

17 20

17

17

24 25

24

17

17 36

17

17

7

17 36

17

17 35

17

17

17

17

17 26

17

17

A37
A39
C39
C37
K40

H40

LDRQ0*

F37

Y4

SERIRQ

AN3
AN1
AU3
AU1

AN6
AN8
AR3
AR1

AD4
AD2
AL3
AL1

AD8
AD6
AG3
AG1

AE3
AE1
AH8
AH6

AC3
AC1
AJ3
AJ1

AB10
AB12

AF10
AF12
AH4

W10

M2
R1

PLACE_NEAR=U1800.H35:1.27mm

PLACE_NEAR=U1800.H37:1.27mm

PLACE_NEAR=U1800.F35:1.27mm

PLACE_NEAR=U1800.K37:1.27mm

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_FRAME_R_L

TP_LPC_DREQ0_L
TBT_PWR_EN_PCH

17

17

17

17

17

7

25

OUT

LPC_SERIRQ

SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P

SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P

TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP

TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP

TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP

TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP

PCH_SATAICOMP

74

PCH_SATA3COMP

74

PCH_SATA3RBIAS

PCH_SATALED_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

33

R1860
R1861
R1862
R1863
R1864

R1810
R1811
R1812
R1813

1 2
1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

33

1 2

7

37 74

IN

7

37 74

IN

7

37 74

OUT

7

37 74

OUT

9

IN

9

IN

9

OUT

9

OUT

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

17

1/20W
1/20W33MF 2015%
1/20W
1/20W
1/20W

1/20W

1/20W

1/20W

1/20W

ITPCPU_CLK100M_N

11 72

ITPCPU_CLK100M_P

11 72

=PP3V3_S0_PCH

1

R1820

10K

5%
1/20W
MF
201

2

7

39 41

BI

=PP1V05_S0_PCH_VCCIO_SATA

PLACE_NEAR=U1800.AB10:2.54mm

1

R1830

37.4

1%
1/20W
MF
201

2

=PP1V05_S0_PCH

1

R1831

49.9

1%
1/20W
MF
201

2

PLACE_NEAR=U1800.AF12:2.54mm

PLACE_NEAR=U1800.AH4:2.54mm

1

R1832

750

1%
1/20W

24

OUT
OUT

MF 2015%

MF 2015%
MF 2015%
MF 2015%

MF 2015%

MF 2015%

MF 2015%

MF 2015%

MF
201

24

2

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
LPC_FRAME_L

HDA_BIT_CLK
HDA_SYNC
HDA_RST_L
HDA_SDOUT

NO STUFF

R1841

1 2

1/20W

201

8

23

8

23

8

23

7

39 41 75

BI

7

39 41 75

BI

7

39 41 75

BI

7

39 41 75

BI

7

39 41 75

OUT

51 75

OUT

51 75

OUT

51 75

OUT

51 75

OUT

75

75

75

75

NO STUFF

R1840

0

1 2

5%

1/20W

MF

0

5%
MF

201

PCIE_ENET_D2R_N

7

36 75

IN

PCIE_ENET_D2R_P

7

36 75

IN

PCIE_ENET_R2D_C_N

7

36 75

OUT

PCIE_ENET_R2D_C_P

7

36 75

OUT

PCIE_AP_D2R_N

7

36 75

IN

PCIE_AP_D2R_P

7

36 75

IN

PCIE_AP_R2D_C_N

7

36 75

OUT

PCIE_AP_R2D_C_P

7

36 75

OUT

PCIE_FW_D2R_N

9

IN

PCIE_FW_D2R_P

9

IN

PCIE_FW_R2D_C_N

9

OUT

PCIE_FW_R2D_C_P

9

OUT

PCIE_EXCARD_D2R_N

7

IN

PCIE_EXCARD_D2R_P

7

IN

PCIE_EXCARD_R2D_C_N

7

OUT

PCIE_EXCARD_R2D_C_P

7

OUT

PCIE_CLK100M_ENET_N

7

36 75

OUT

PCIE_CLK100M_ENET_P

7

36 75

OUT

SSD_CLKREQ_L

17

IN

PCIE_CLK100M_FW_N

7 9

75

PCIE_CLK100M_FW_P

75

7 9

FW_CLKREQ_L

17

PCIE_CLK100M_AP_N

7

36 75

OUT

PCIE_CLK100M_AP_P

7

36 75

OUT

AP_CLKREQ_L

17 36

IN

PCIE_CLK100M_EXCARD_N

7

75

OUT

PCIE_CLK100M_EXCARD_P

7

75

OUT

EXCARD_CLKREQ_L

17

IN

JTAG_DPMUXUC_TRST_L

17

OUT

PCIE_CLK100M_SSD_N

7 9

OUT

PCIE_CLK100M_SSD_P

7 9

OUT

ENET_CLKREQ_L

17 36

7

IN

PEG_CLK100M_N

7 9

OUT

PEG_CLK100M_P

7 9

OUT

PEG_CLKREQ_L

17

IN

PCIE_CLK100M_TBT_N

7

33 75

OUT

PCIE_CLK100M_TBT_P

7

33 75

OUT

TBT_CLKREQ_L

17 35

IN

ITPXDP_CLK100M_N

24 72

ITPXDP_CLK100M_P

24 72

NC_PCIE_5_D2RN

7

NC_PCIE_5_D2RP

7

NC_PCIE_5_R2D_CN

7

NC_PCIE_5_R2D_CP

7

NC_PCIE_6_D2RN

7

NC_PCIE_6_D2RP

7

NC_PCIE_6_R2D_CN

7

NC_PCIE_6_R2D_CP

7

NC_PCIE_7_D2RN

7

NC_PCIE_7_D2RP

7

NC_PCIE_7_R2D_CN

7

NC_PCIE_7_R2D_CP

7

NC_PCIE_8_D2RN

7

NC_PCIE_8_D2RP

7

NC_PCIE_8_R2D_CN

7

NC_PCIE_8_R2D_CP

7

TP_PCIE_CLK100M_PE4N

7

TP_PCIE_CLK100M_PE4P

7

TP_PCIE_CLK100M_PEBN

7

TP_PCIE_CLK100M_PEBP

7

PEGCLKRQB_L_GPIO56

17

25 74

IN

Unused clock terminations for FCIM Mode

10K

PCH_CLK96M_DOT_P

17 75

PCH_CLK96M_DOT_N

17 75

PCH_CLK100M_SATA_P

7

17 75

PCH_CLK100M_SATA_N

17 75

PCIE_CLK100M_PCH_P

7

17 75

PCIE_CLK100M_PCH_N

7

17 75

PCH_CLK14P3M_REFCLK

17 75

PCH_CLKIN_GNDP1

17

PCH_CLKIN_GNDN1

17

R1891
R1892

R1893
R1894

R1895
R1896

R1897
R1870

R1871

10K
10K

10K
10K

10K
10K

10K
10K

1 2
1 2

1 2
1 2

1 2
1 2

1 2

1 2
1 2

6 3

BJ33

PERN1

BL33

PERP1

BB30

PETN1

AY30

PETP1

BJ35

PERN2

BL35

PERP2

BB33

PETN2

AY33

PETP2

BH36

PERN3

BK36

PERP3

BF33

PETN3

BD33

PETP3

BJ37

PERN4

BL37

PERP4

BD35

PETN4

BF35

PETP4

BJ39

PERN5

BL39

PERP5

AY35

PETN5

BB35

PETP5

BH40

PERN6

BK40

PERP6

BD37

PETN6

BF37

PETP6

BJ41

PERN7

BL41

PERP7

AY37

PETN7

BB37

PETP7

BJ43

PERN8

BL43

PERP8

AY40

PETN8

BB40

PETP8

AD48

CLKOUT_PCIE0N

AD50

CLKOUT_PCIE0P

M4

PCIECLKRQ0*/GPIO73

AE49

CLKOUT_PCIE1N

AE51

CLKOUT_PCIE1P

U8

PCIECLKRQ1*/GPIO18

AD40

CLKOUT_PCIE2N

AD42

CLKOUT_PCIE2P

T4

PCIECLKRQ2*/GPIO20

AA49

CLKOUT_PCIE3N

AA51

CLKOUT_PCIE3P

B8

PCIECLKRQ3*/GPIO25

Y48

CLKOUT_PCIE4N

Y50

CLKOUT_PCIE4P

M19

PCIECLKRQ4*/GPIO26

AB40

CLKOUT_PCIE5N

AB42

CLKOUT_PCIE5P

K8

PCIECLKRQ5*/GPIO44

(IPU-RSMRST#)

AF40

CLKOUT_PEG_B_N

AF42

CLKOUT_PEG_B_P

C4

PEG_B_CLKRQ*/GPIO56

AB44

CLKOUT_PCIE6N

AB46

CLKOUT_PCIE6P

J3

PCIECLKRQ6*/GPIO45

W44

CLKOUT_PCIE7N

W46

CLKOUT_PCIE7P

H4

PCIECLKRQ7*/GPIO46

(IPU-RSMRST#)

AR12

CLKOUT_ITPXDP_N

AR10

CLKOUT_ITPXDP_P

SYSCLK_CLK25M_SB

PLACE_NEAR=U1800.W49:5.1mm

1/20W
1/20W

1/20W
1/20W

1/20W
1/20W

1/20W

1/20W
1/20W

OMIT_TABLE

U1800

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

(2 OF 10)

SMBUS

SML1ALERT*/PCHHOT*/GPIO74

C-LINK

PCI-E*

Controlled by PCIECLKRQ5#

CLOCKS

FLEX

CLOCKS

R1885

1 2

MF201

604

1/20W

1%

MF 2015%
MF 2015%

MF 2015%
MF 2015%

MF 2015%
MF 2015%

MF 2015%

MF 2015%
MF 2015%

SMBALERT*/GPIO11

SML0ALERT*/GPIO60

(IPU/IPD)
(IPU/IPD)

PEG_A_CLKRQ*/GPIO47

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

(IPD-PWROK)

CLKOUTFLEX1/GPIO65

(IPD-PWROK)

CLKOUTFLEX2/GPIO66

(IPD-PWROK)

CLKOUTFLEX3/GPIO67

(IPD-PWROK)

1

R1886

1K

1%
1/20W
MF
201

2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1
CL_DATA1
CL_RST1*

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

SYSCLK_CLK25M_SB_R

1.8V -> 1.1V

SYNC_MASTER=J13_MLB

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

H12
F17
F10

H22
K12
A9

C9
D12
C11

L3
J1
M8

R8
AF44
AF46

BB24
AY24

AN10
AN12

BD17
BF17

BB26
AY26

M24
K24

AK8
AK6

J49

E51

W49
W51

AC49

H50

D48

G49

J51

SMBUS_PCH_ALERT_L
SMBUS_PCH_CLK
SMBUS_PCH_DATA

USB_EXTB_SEL_XHCI
SML_PCH_0_CLK
SML_PCH_0_DATA

USB_EXTD_SEL_XHCI
SML_PCH_1_CLK
SML_PCH_1_DATA

TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47
TP_PCIE_CLK100M_PEGAN
TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P

DPLL_REF_CLK_N
DPLL_REF_CLK_P

PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P

PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1

PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P

PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P

PCH_CLK14P3M_REFCLK

PCH_CLK33M_PCIIN

DOES THIS NEED LENGTH MATCH???

SYSCLK_CLK25M_SB_R

NC

=PP1V05_S0_PCH_VCCDIFFCLK

8

21 23

PLACE_NEAR=U1800.AC49:2.54mm

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

17 74

PCH SATA/PCIe/CLK/LPC/SPI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:

12

17

7

42 75

OUT

7

42 75

BI

17 26

OUT

42 75

OUT

42 75

BI

17

OUT

42 75

OUT

42 75

BI

7

7

7

17

7

7

7

11 72

OUT

7

11 72

OUT

11 72

OUT

11 72

OUT

7

17 75

IN

7

17 75

IN

17

17

17 75

IN

17 75

IN

17 75

IN

7

17 75

IN

17 75

IN

7

25 75

IN

17 74

1

R1890

90.9

1%

1/20W

MF

201

2

9

9

9

9

SYNC_DATE=09/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

18 OF 132

SHEET

17 OF 80

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

C

B

R1905

10K

1/20W

=PP3V3_SUS_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_PCIE

PLACE_NEAR=U1800.BF19:12.7mm

1

1

R1900

49.9

1%

5%

1/20W
MF

MF

201

201

2

2

PLACE_NEAR=U1800.BK20:2.54mm

1

R1920

750

1%
1/20W
MF
201

2

7

10 72

IN

7

10 72

IN

7

10 72

IN

7

10 72

IN

7

10 72

IN

7

10 72

IN

7

10 72

IN

7

10 72

IN

7

10 72

OUT

7

10 72

OUT

7

10 72

OUT

7

10 72

OUT

7

10 72

OUT

7

10 72

OUT

7

10 72

OUT

7

10 72

OUT

18

7

25 39

IN

24 39 66

IN

25 66

IN

66

IN

11 27 72

OUT

66

IN

18

18 24 39

IN

39 40 66

IN

40

IN

8

17 18 19 20

8

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>
DMI_N2S_N<3>

DMI_N2S_P<0>
DMI_N2S_P<1>
DMI_N2S_P<2>
DMI_N2S_P<3>

DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>

DMI_S2N_P<0>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_S2N_P<3>

PCH_DMI_COMP

PCH_DMI2RBIAS

PCH_SUSACK_L

PM_SYSRST_L

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PM_PCH_APWROK

PM_MEM_PWRGD

PM_RSMRST_L

PCH_SUSWARN_L

PM_PWRBTN_L

SMC_ADAPTER_EN

PM_BATLOW_L

PCH_RI_L

BL21
BL23
BJ19
BL17

BJ21
BJ23
BL19
BJ17

BD22
BB22
BB19
BB17

BF22
AY22
AY19
AY17

BF19
BD19

BK20

F15

M10

M22

B12

B20

C13

K19

H19

H10

F12

PCH-PPT-MB-SFF-ES1

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

DMI_ZCOMP
DMI_IRCOMP

DMI2RBIAS

SUSACK*

L1

SYS_RESET*

SYS_PWROK

PWROK

G3

APWROK

DRAMPWROK

RSMRST*

SUSWARN*/SUSPWRDNACK/GPIO30

PWRBTN*

ACPRESENT/GPIO31

(IPD-DeepS4/S5)

BATLOW*/GPIO72

RI*

QP8D-MM915462

(IPU)

(IPU)

OMIT_TABLE

U1800

BGA

(3 OF 10)

FDI

DMI

CLKRUN*/GPIO32

MANAGEMENT

SYSTEM POWER

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

(IPU)

SLP_LAN*/GPIO29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0
FDI_FSYNC1

FDI_LSYNC0
FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE*

SLP_S4*
SLP_S3*

SLP_A*

SLP_SUS*

PMSYNCH

BL13
BJ15
BD12
BJ11
AY15
AY12
BJ9
BF10

BJ13
BL15
BF12
BL11
BB15
BB12
BL9
BD10

BB10

BH12
BK8

BK12
BH8

F22

A21

D8

T2

G6

D3

F6
K10
D4

C7

A15

BB8

A7

FDI_DATA_N<0>
FDI_DATA_N<1>
FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>
FDI_DATA_N<5>
FDI_DATA_N<6>
FDI_DATA_N<7>

FDI_DATA_P<0>
FDI_DATA_P<1>
FDI_DATA_P<2>
FDI_DATA_P<3>
FDI_DATA_P<4>
FDI_DATA_P<5>
FDI_DATA_P<6>
FDI_DATA_P<7>

FDI_INT

FDI_FSYNC<0>
FDI_FSYNC<1>

FDI_LSYNC<0>
FDI_LSYNC<1>

PCH_DSWVRMEN

PM_DSW_PWRGD

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

PM_SYNC

PCH_GPIO29

OUT

OUT
OUT

OUT
OUT

IN

BI

OUT

OUT

OUT
OUT
OUT

7

OUT

OUT

OUT

7

10 72

IN

10 72

IN

10 72

IN

10 72

IN

7

10 72

IN

10 72

IN

10 72

IN

10 72

IN

7

10 72

IN

10 72

IN

10 72

IN

10 72

IN

7

10 72

IN

10 72

IN

10 72

IN

10 72

IN

10 72

10 72

10 72

10 72

10 72

7

18 36

7

18 39 41

7

25 39 41

40

18 39 66

7

18 27 36 38 39 66

7

18 27 36 39 66

18 66

11 72

18

=PPVRTC_G3_PCH

1

R1915

390K

5%
1/20W
MF
201

2

39

IN

1

R1909

100K

5%
1/20W
MF
201

2

9

R1955

100K

1/20W

17 21

8

OMIT_TABLE

U1800

OUT

1

5%
MF

201

2

LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR

9

OUT

LVDS_IG_BKL_PWM

9

OUT

TP_CRT_IG_BLUE

7

TP_CRT_IG_GREEN

7

TP_CRT_IG_RED

7

TP_CRT_IG_DDC_CLK

7

TP_CRT_IG_DDC_DATA

7

TP_CRT_IG_HSYNC

7

TP_CRT_IG_VSYNC

7

PCH_DAC_IREF

PLACE_NEAR=U1800.R51:2.54mm

1

R1951

1K

5%
1/20W
MF
201

2

M44
M42

L49

L51

NC

K46

NC

R42

NC

M40

NC

AH42

NC

AH40

NC

AG51

NC

AG49

NC

AK44

NC

AK46

NC

AR46

NC

AN49

NC

AN44

NC

AK40

NC

AR44

NC

AN51

NC

AN46

NC

AK42

NC

AH46

NC

AH44

NC

AM50

NC

AL49

NC

AJ51

NC

AH50

NC

AM48

NC

AL51

NC

AJ49

NC

AH48

NC

M46
R46
U46

R49
N49

M50
N51

R51
T48

PCH-PPT-MB-SFF-ES1

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CLK
L_DDC_DATA

(IPD-PLTRST#)

L_CTRL_CLK
L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK*
LVDSA_CLK

LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK*
LVDSB_CLK

LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

BGA

QP8D-MM915462

(4 OF 10)

SDVO_TVCLKINN

(IPD)

SDVO_TVCLKINP

(IPD)

SDVO_STALLN

(IPD)

SDVO_STALLP

(IPD)

SDVO_INTN

(IPD)

SDVO_INTP

(IPD)

SDVO_CTRLCLK

SDVO_CTRLDATA

(IPD-PLTRST#)

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P

LVDS

DIGITAL DISPLAY INTERFACE

CRT

DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_CTRLCLK

DDPD_CTRLDATA

(IPD-PLTRST#)

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AU40
AU42

AR51
AR49

AT50
AT48

W42
R44

AW51
AW49
AY42

AY48
AY50
AY44
AY46
BB44
BB46
BA49
BA51

T50
U44

AU51
AU49
BE46

BC49
BC51
BD48
BD50
BF46
BF45
BE49
BE51

M48
U42

AU46
AU44
BK44

BG51
BG49
BF42
BD42
BJ47
BL47
BL45
BJ45

TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP

TP_SDVO_STALLN
TP_SDVO_STALLP

TP_SDVO_INTN
TP_SDVO_INTP

DPA_IG_DDC_CLK
DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N
DPA_IG_AUX_CH_P
DPA_IG_HPD

TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>
TP_DP_IG_B_MLN<1>
TP_DP_IG_B_MLP<1>
TP_DP_IG_B_MLN<2>
TP_DP_IG_B_MLP<2>
TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>

DPB_IG_DDC_CLK
DPB_IG_DDC_DATA

DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_HPD

TP_DP_IG_C_MLN<0>
TP_DP_IG_C_MLP<0>
TP_DP_IG_C_MLN<1>
TP_DP_IG_C_MLP<1>
TP_DP_IG_C_MLN<2>
TP_DP_IG_C_MLP<2>
TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>

TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0>
TP_DP_IG_D_MLP<0>
TP_DP_IG_D_MLN<1>
TP_DP_IG_D_MLP<1>
TP_DP_IG_D_MLN<2>
TP_DP_IG_D_MLP<2>
TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>

7

7

7

7

7

7

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

D

C

B

=PP3V3_SUS_PCH_GPIO

8

17 18 19 20

1

R1983

10K

5%

1/20W

MF

201

R1986

2

0

PCH_SUSWARN_L

18

=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH

R1985
R1991

A

R1982
R1925

R1924
R1921
R1922
R1923

1K

8.2K
10K

1K

100K
100K
100K
100K

1 2

1 2

1 2

1 2

2 1
2 1
2 1
2 1

8

17 18 19 20

8

17 19 20 25 35

8

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

PM_PWRBTN_L
PM_CLKRUN_L
PCH_GPIO29
PCIE_WAKE_L

PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_SLP_SUS_L

5%

1/20W

MF

201

12

PCH_SUSACK_L

18

18 24 39

7

18 39 41

18

7

18 36

7

18 27 36 39 66

7

18 27 36 38 39 66

18 39 66

18 66

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH DMI/FDI/PM/Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

19 OF 132

SHEET

18 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

OMIT_TABLE

RSVD

USBP0N
USBP0P

USBP1N
USBP1P

USBP2N
USBP2P

USBP3N
USBP3P

USBP4N
USBP4P

USBP5N
USBP5P

USBP6N
USBP6P

USBP7N
USBP7P

USBP8N
USBP8P

USBP9N
USBP9P

USBP10N
USBP10P

USBP11N
USBP11P

USBP12N
USBP12P

USBP13N
USBP13P

(IPD)

USBRBIAS

AU6

NC

AU8

NC

AW1

NC

AW3

NC

AY2

NC

AY4

NC

AY6

NC

AY8

NC

BA1

NC

BA3

NC

BB6

NC

BC1

NC

BC3

NC

BD2

NC

BD4

NC

BE1

NC

BE3

NC

BE6

NC

BF6

NC

BF7

NC

BG1

NC

BG3

NC

BH3

NC

BH4

NC

BJ4

NC

BJ5

NC

BJ7

NC

BK6

NC

BL5

NC

F24
H24

C25
A25

C27
A27

H28
F28

M26
K26

D28
B28

H26
F26

D32
B32

M28
K28

C29
A29

C31
A31

H33
F33

H30
F30

M33
K33

C33
A33

C17
A17
A13
D16
A11
B16
C23
H15

USB_EXTA_N
USB_EXTA_P

USB_EXTC_N
USB_EXTC_P

USB_EXTB_XHCI_N
USB_EXTB_XHCI_P

USB_EXTD_XHCI_N
USB_EXTD_XHCI_P

TP_USB_4N
TP_USB_4P

TP_USB_SDN
TP_USB_SDP

TP_USB_WLANN
TP_USB_WLANP

USB_HUB_UP_N
USB_HUB_UP_P

USB_CAMERA_N
USB_CAMERA_P

USB_EXTB_EHCI_N
USB_EXTB_EHCI_P

USB_EXTD_EHCI_N
USB_EXTD_EHCI_P

TP_USB_BT_HSN
TP_USB_BT_HSP

TP_USB_12N
TP_USB_12P

TP_USB_13N
TP_USB_13P

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

9

9

38 74

BI

38 74

BI

9

BI

9

BI

26 74

BI

26 74

BI

26 74

BI

26 74

BI

9

9

9

9

9

9

26 74

BI

26 74

BI

32 74

BI

32 74

BI

26 74

BI

26 74

BI

9

BI

9

BI

9

9

9

9

PCH_USB_RBIAS

74

Ext A (XHCI/EHCI)

Ext C (XHCI/EHCI)

Ext B (XHCI)

Ext D (XHCI) (Mobiles: Trackpad)

Unused

RSVD: SD

RSVD: WiFi

USB Hub (All LS/FS Devices)

Camera

Ext B (EHCI)

Ext D (EHCI)

RSVD: BT (HS)

Unused

Unused

PLACE_NEAR=U1800.A33:2.54mm

1

R2070

19 24

IN

19 24

IN

19 24

IN

19 24

IN

24

IN

24

IN

24

OUT

19 24

IN

22.6

1%
1/20W
MF
201

2

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH PCI/USB/TP/RSVD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

20 OF 132

SHEET

19 OF 80

124578

SIZE

D

C

B

A

D

BH24
BK24
BH20
BK16
BH16
AN42
AN40
AR40
AR42

AD10

AD44
AD46
BJ48

BH49

NC

BB42

NC

BJ25
BJ27
BJ31
BJ29

BL25
BL27
BL31
BL29

BF26
BB28
BF28
BF30

BD26
AY28
BD28
BD30

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9

D20

TP10

M30

TP11

E3

TP12

AM4

TP13

AT4

TP14

AT2

TP15
TP16

B24

TP17

D24

TP18
TP19
TP20
TP21

BL7

TP22

W40

TP23

K30

TP24

TP41
TP42

USB3RN1
USB3RN2
USB3RN3
USB3RN4

USB3RP1
USB3RP2
USB3RP3
USB3RP4

USB3TN1
USB3TN2
USB3TN3
USB3TN4

USB3TP1
USB3TP2
USB3TP3
USB3TP4

D49

PIRQA*

C48

PIRQB*

C47

PIRQC*

C45

PIRQD*

G46

REQ1*/GPIO50

K44

REQ2*/GPIO52

F46

REQ3*/GPIO54

F42

GNT1*/GPIO51

H42

GNT2*/GPIO53

D44

GNT3*/GPIO55

(IPU-PCIERST#)

A47

PIRQE*/GPIO2

C41

PIRQF*/GPIO3

F45

PIRQG*/GPIO4

F40

PIRQH*/GPIO5

H2

PME*

F7

PLTRSTB*

G51

CLKOUT_PCI0

E49

CLKOUT_PCI1

H48

CLKOUT_PCI2

J43

CLKOUT_PCI3

G45

CLKOUT_PCI4

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

D

7

TP_PCH_TP23

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

USB3_EXTA_RX_N

7

38 74

IN

USB3_EXTC_RX_N

9

IN

USB3_EXTB_RX_N

7

36 74

IN

USB3_EXTD_RX_N

9

IN

USB3_EXTA_RX_P

7

38 74

IN

USB3_EXTC_RX_P

9

C

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 35

R2010
R2011
R2012
R2013

B

R2054

=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO

R2016
R2017
R2018

R2030
R2014

R2031

A

R2033
R2069

R2060
R2061

R2062
R2068
R2067

10K
10K
10K

10K

10K
10K

10K

10K
10K

10K
10K

10K
10K

NO STUFF

NO STUFF

1 2
1 2
1 2

1 2

1 2
1 2

1 2

1 2

1 2
1 2

1 2
1 2

2 1

8

17 18 20

8

25

8

17 18 19 20 25 35

JTAG_GMUX_TMS

MF 2015%

1/20W
1/20W
1/20W

1/20W

Redundant to pull-up on audio page

1/20W
1/20W

Redundant to pull-up on audio page

1/20W

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1/20W

1/20W
1/20W

1/20W
1/20W
1/20W

BLC_I2C_MUX_SEL

MF 2015%

USE_HDD_OOB_L

MF 2015%

BLC_GPIO

MF 2015%

AUD_IP_PERIPHERAL_DET

MF 2015%

TBT_PWR_REQ_L

MF 2015%

AUD_I2C_INT_L

MF 2015%

MF 2015%

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

MF 2015%

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

MF 2015%

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

MF 2015%

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

MF 2015%

AP_PWR_EN

MF 2015%

10K
10K
10K
10K

10K

1 2
1 2
1 2
1 2

NO STUFF

2 1

19

19

19

19

19 55

19 33

19 54

24 36 66

19 24

19 24

19 24

19 24

19 24

1/20W
1/20W
1/20W
1/20W

1/20W

IN

USB3_EXTB_RX_P

7

36 74

IN

USB3_EXTD_RX_P

9

IN

USB3_EXTA_TX_N

7

38 74

OUT

USB3_EXTC_TX_N

9

OUT

USB3_EXTB_TX_N

36 74

OUT

USB3_EXTD_TX_N

9

OUT

USB3_EXTA_TX_P

38 74

OUT

USB3_EXTC_TX_P

9

OUT

USB3_EXTB_TX_P

36 74

OUT

USB3_EXTD_TX_P

9

OUT

MF 2015%
MF 2015%
MF 2015%
MF 2015%

MF 2015%

PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L

JTAG_GMUX_TMS

19

OUT

BLC_I2C_MUX_SEL

19

OUT

USE_HDD_OOB_L

19

OUT

TP_PCH_STRP_BBS1

7

TP_PCH_STRP_ESI_L

7

PCH_STRP_TOPBLK_SWP_L

BLC_GPIO

19

IN

AUD_IP_PERIPHERAL_DET

19 55

IN

TBT_PWR_REQ_L

19 33

IN

AUD_I2C_INT_L

19 54

IN

TP_PCI_PME_L

7

PLT_RESET_L

25 27

OUT

LPC_CLK33M_SMC_R

25 75

OUT

LPC_CLK33M_LPCPLUS_R

25

OUT

TP_PCI_CLK33M_OUT2

7

TP_PCI_CLK33M_OUT3

7

PCH_CLK33M_PCIOUT

25

OUT

U1800

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

(5 OF 10)

USB

PCI

(IPU)

(IPD)

USBRBIAS*

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43

OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14

6 3

8 7 6 5 4 3

BOM GROUP

RAMCFG_SLOT

BOM OPTIONS

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

12

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

D

Systems with chip-down memory should add pull-downs on another page and set straps per software.

R2574 is 1K series resistor between U2100 output and PCH input to reduce the current between the two drivers..

U1800

PCH-PPT-MB-SFF-ES1

XDP_FC1_TBT_CIO_PLUG_EVENT

24

IN

FW_PME_L

20

IN

DPMUX_UC_IRQ

20

IN

SMC_RUNTIME_SCI_L

20 39

IN

WOL_EN

20

OUT

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

24

IN

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

24

OUT

LPCPLUS_GPIO

7

20 41

BI

ODD_PWR_EN_L

20

OUT

SMC_WAKE_SCI_L

20 39

IN

0

35

OUT

TBT_SW_RESET_L

R2180

1 2

5%
MF

C

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

20

TBT_SW_RESET_R_L

1/20W

201

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

20 24

OUT

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

24

OUT

JTAG_ISP_TDO

20

IN

JTAG_ISP_TDI

20

OUT

FW_PWR_EN_PCH

20 25

OUT

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

24

OUT

SPIROM_USE_MLB

7

20 41 50

BI

TP_PCH_GPIO8

7

TBT_GO2SX_BIDIR

20 33

XDP_DC1_PCH_GPIO35_MXM_GOOD

24

OUT

W1

BMBUSY*/GPIO0

B40

GPIO1

C43

GPIO6

A45

GPIO7

H17

GPIO8

(IPU-RSMRST#)

C5

LAN_PHY_PWR_CTRL/GPIO12

K6

GPIO15

AA3
B44

K15
C15

W12

U10

AA1
K17

A48
A49
A51
BH1

BH51

BJ1

BJ3
BJ49
BJ51

BL1

BL3

BL4

(IPU)

SATA4GP/GPIO16
GPIO17

W3

SCLOCK/GPIO22
GPIO24
GPIO27

(IPU-DeepS4/S5)

G1

(IPU-RSMRST#)

GPIO28

R3

STP_PCI*/GPIO34
GPIO35

W6

SATA2GP/GPIO36

(IPD-PLTRST#)

M6

SATA3GP/GPIO37

(IPD-PLTRST#)

N3

SLOAD/GPIO38
SDATAOUT0/GPIO39

U1

SDATAOUT1/GPIO48
SATA5GP/GPIO49
GPIO57

A4
A5

VSS_NCTF

QP8D-MM915462

(6 OF 10)

B

JTAG Isolation due to glitch in and out of sleep

NOTE: TCK from PCH is Push-Pull CMOS
NOTE: TMS/TDI from PCH is Open Drain
NOTE: TDO from CR is Push-Pull CMOS

1

R2188

10K

5%
1/20W
MF
201

2

1

R2199

10K

5%
1/20W
MF
201

2

CRITICAL

Q2160

SSM6N15AFE

SOT563

D

6

CRITICAL

Q2160

SSM6N15AFE

SOT563

D

3

=PP3V3_S0_PCH_STRAPS

8

=PP3V3_S5_PCH_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO

R2185
R2196
R2190

R2197
R2184

R2150
R2155

A

R2194
R2192
R2193

R2191
R2111

R2195
R2112
R2198

R2116

10K
10K

100K

10K
10K

10K
10K

10K
10K

100K

10K
20K

100K

10K
10K

10K

NO STUFF

1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2
1 2

1 2

2 1
2 1
2 1
2 1

2 1

8

8

17 18 19

8

17 18 19 20 25 35

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

Must stuff R2197 when R2180 NO STUFFed.

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

MF 2015%

1/20W

FW_PME_L
SMC_RUNTIME_SCI_L
LPCPLUS_GPIO

TBT_SW_RESET_R_L
FW_PWR_EN_PCH

PCH_A20GATE
PCH_RCIN_L

WOL_EN
TBT_GO2SX_BIDIR
SPIROM_USE_MLB

SMC_WAKE_SCI_L
DPMUX_UC_IRQ

AUD_IPHS_SWITCH_EN_PCH
ODD_PWR_EN_L

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

ENET_LOW_PWR_PCH

20

20 39

7

20 41

20

20 25

20

20

20

20 33

7

20 41 50

20 39

20

24 25

20

9

24 25

20 24

20

JTAG_ISP_TMS

17

IN

=PP3V3_S0_PCH_STRAPS

8

20

JTAG_ISP_TDI

20

IN

6 3

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 25 35

OMIT_TABLE

BGA

GPIO

CPU/MISC

NCTF

2

S G

1

5

S G

4

K42

GPIO68

A43

GPIO69

D40

GPIO70

A41

GPIO71

U3

A20GATE

AU12

PECI

(IPD)

U6

RCIN*

DF_TVS

TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4

NC_1

AU10

BC9

R6

BC7

AK10
AH12
AK12
AH10

U40

BL48
BL49
BL51
C3
C49
C51
D1
D51
E1

PROCPWRGD

THRMTRIP*

INIT3_3V*

(IPU)

(IPD-PLTRST#?)

VSS_NCTF

=PP3V3_TBT_PCH_GPIO

1

R2163

10K

5%
1/20W
MF
201

2

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

1

R2161

10K

5%
1/20W
MF
201

2

JTAG_TBT_TDI

MLB_RAMCFG3

9

MLB_RAMCFG2

9

MLB_RAMCFG1

9

MLB_RAMCFG0

9

PCH_A20GATE

PCH_PECI

PCH_RCIN_L

PCH_PROCPWRGD

PM_THRMTRIP_L_R

40

PCH_INIT3V3_L

PCH_DF_TVS

NC

NO STUFF

8

OUT

8

OUT

R2130

1/20W

17 20

33

17 20

33

RAMCFG3:H

1

1K

5%
MF

201

2

1

R2172

10K

5%

1/20W

MF

201

2

20

R2170

20

R2140
R2156

This has internal pull up and should not pulled low.

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

=PP3V3_S0_PCH_STRAPS

8

20

JTAG_ISP_TDO

20

OUT

=PP3V3_S0_PCH_STRAPS

8

20

JTAG_ISP_TCK JTAG_TBT_TCK

IN

RAMCFG2:H

1

R2173

10K

5%
1/20W
MF
201

2

NO STUFF

43

1 2

0

1 2

390

1 2

8

17 18 19 20 25 35

TBT_PWR_EN goes high for JTAG Programming

TBT_CIO_PLUG_EVENT

33

IN

RAMCFG1:H

CPU_PECI

5%
MF 201

CPU_PWRGD

1/20W

5%
MF 201

PM_THRMTRIP_L

5%

1/20W

MF 201

=PP3V3_S0_PCH_GPIO

1

R2186

10K

5%
1/20W
MF
201

2

1

R2113

10K

5%
1/20W
MF
201

2

R2174

10K

1/20W

201

1/20W

C2113

X5R-CERM

1

R2160

10K

5%
1/20W
MF
201

2

CRITICAL

Q2162

SSM6N15AFE

SOT563

D

6

CRITICAL

Q2162

SSM6N15AFE

SOT563

D

3

1

5%
MF

2

0.1UF

0201

10%
16V

RAMCFG0:H

1

R2175

10K

5%
1/20W
MF
201

2

BI

11 24 72 24

OUTOUT

11 40 72

IN

1

2

2

1

NC

2

S G

1

5

S G

4

11 40 72

=PP1V8_S0_PCH_VCC_DFTERM

1

R2179

2.2K

5%
1/20W
MF
201

2

12
5%
MF

CPU_PROC_SEL_L

DF_TVS:DMI & FDI Term Voltage
Set to Vss when Low
Set to Vcc when High

TBT_CIO_PLUG_EVENT_ISOL

6

U2100

08

NC

3

5

R2178

1K

1/20W

201

CRITICAL

74LVC1G08

SOT891

4

=PP3V3_TBT_PCH_GPIO

1

R2162

10K

5%
1/20W
MF
201

2

JTAG_TBT_TDO

IN

=PP3V3_TBT_PCH_GPIO

1

R2164

10K

5%
1/20W
MF
201

2

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH GPIO/MISC/NCTF

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

D

8

21 23

11 72

24

OUT

C

B

8

17 20

33

8

17 20

33 24

OUT

SIZE

A

D

SYNC_DATE=09/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

21 OF 132

SHEET

20 OF 80

124578

8 7 6 5 4 3

12

D

PLACE_NEAR=U1800.R15:2.54mm

C2210

0.1UF

X5R-CERM

C

C2222

0.1UF

X5R-CERM

8

17 18

PLACE_NEAR=U1800.N16:2.54mm

B

VCCACLK pin left as NC per DG

PCH output, for decoupling only

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

10%
16V

2

0201

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

PLACE_NEAR=U1800.U17:2.54mm

10%
16V

2

0201

VCCAPLLDMI2 pin left as NC per DG

AL24 left as NC per DG

23

=PPVRTC_G3_PCH

1

C2231

1UF

20%

6.3V
2

X5R

0201

PLACE_NEAR=U1800.N16:2.54mm

PCH output, for decoupling only

=PP3V3_S5_PCH_VCCDSW

8

23

TP_PPVOUT_PCH_DCPSUSBYP

7

PPVOUT_G3_PCH_DCPRTC

PP1V05_S0_PCH_VCCADPLLA_F

23

PP1V05_S0_PCH_VCCADPLLB_F

23

=PP1V05_S0_PCH_VCCDIFFCLK

8

17 23

55mA Max, 5mA Idle

=PP1V05_S0_PCH_VCCSSC

8

23

PPVOUT_S0_PCH_DCPSST

PP1V05_S0_PCH_VCCCLKDMI_F

23

=PP1V05_S0_PCH_V_PROC_IO

8

23

=PP1V05_S0_PCH_VCCASW

8

1

C2232

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2233

0.1UF

10%
16V

2

X5R-CERM
0201

PLACE_NEAR=U1800.N16:2.54mm

D

OMIT_TABLE

V5REF

VCCIO

DCPSUS

VCCVRM

M37

=PP5V_SUS_PCH_V5REFSUS

U27

=PP3V3_SUS_PCH_VCCSUS_USB

U29

N36

=PP5V_S0_PCH_V5REF

AM2

NC

NC-ed per DG

V31

=PP3V3R1V5_S0_PCH_VCCSUSHDA

10 mA Max, 1mA Idle

AA13

=PP1V05_S0_PCH_VCCIO

AB15
AC13
AC15
AF15
AG13
AG15
AJ17
AK21
N18
R23
R25
U23
U25

AM27

=PP3V3_SUS_PCH_VCCSUS

N27
R27
R29
R33
R35
U33
U35

AR33

NC

AU31

NC

AU33

NC

V13

NC

AC39

=PP1V8R1V5_S0_PCH_VCCVRM

AE19
AF17
AW18
AW21

23

8

23

23

8

23 25

8

21 23

8

23

8

21

AC51

AW31

BF40
BD40

AC37
AE37
AE39

AC35

AP39

AM17

AB27
AB29
AB31
AC27
AC29
AC31
AE27
AE29
AE31

Y25

R12

R10

R15
U15

U17

N16

R19
U19
U21
V19
V21
V23
V25
Y21
Y23

Y27
Y29
Y31

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCCAPLLDMI2

DCPRTC

VCCADPLLA
VCCADPLLB

VCCDIFFCLKN

VCCSSC

DCPSST

VCCCLKDMI

V_PROC_IO

VCCRTC

VCCASW

NC

NC

U1800

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

(8 OF 10)

CLK/MISC

CPURTC

V5REF_SUS

USB

PCI/GPIO/LPC

VCCAPLL_SATA3

SATA

VCCSUSHDA

HDA

VCCSUS3_3

VCCPUSB

=PP1V05_S0_PCH_VCC_CORE

8

23

1.44 A Max, 474mA Idle

TP_1V05_S0_PCH_VCCAPLLEXP

7

=PP1V05_S0_PCH_VCCIO

8

21 23

AB21
AB23
AC21
AC23
AE21
AE23
AF21
AF23
AG21
AG23
AG25
AG27
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AK29
AK31
AK33
AM33
AM35

AP19

AM21
AP27
AR15
AR23
AR25
AR27
AR29
AT13
AU23
AU25
AU27
AU29
AU35
AW34

PCH-PPT-MB-SFF-ES1

VCCCORE

VCCAPLLEXP

VCCIO

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(7 OF 10)

CRTFDI

VCC CORE

LVDS

DMI

DFT/SPI

VCCIO

VCCADAC

VSSA_DAC

VCCALVDS

VSSALVDS

VCCTX_LVDS

VCCDMI

VCCADMI_VRM

VCCDFTERM

VCCSPI

VCCAFDIPLL
VCCAFDI_VRM

VCC3_3

U51

PP3V3_S0_PCH_VCCA_DAC_F

V50

AF33

pwrterm2gnd

AG33

pwrterm2gnd

AC33
AE33

AF37

pwrterm2gnd

AG37

pwrterm2gnd

AG39

pwrterm2gnd

AJ37

pwrterm2gnd

AM23

=PP1V05_S0_PCH_VCC_DMI

AU15
AW16
AU21

=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V8_S0_PCH_VCC_DFTERM

AJ13
AJ15
AK15
AL13

Y19

=PP3V3_SUS_PCH_VCC_SPI

AP13

NC

AP15

NC

AU19

=PP1V8R1V5_S0_PCH_VCCVRM

AB19

=PP3V3_S0_PCH_VCC3_3

AC19
AF6
BK28
R40
T39
U37
V37

PP3V3_S0_PCH_VCC3_3_CLK_F

V39

23

8

23

8

21

8

20 23

8

23

8

21

8

23

23

C

B

A

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=09/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

22 OF 132

SHEET

21 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

AA7
AA9

PCH-PPT-MB-SFF-ES1

AA11
AA39
AA41
AA43
AA45

D

C

B

A

AB2

AB4
AB17
AB25
AB33
AB35
AB37
AB48
AB50

AC7

AC9
AC11
AC17
AC25
AC41
AC43
AC45

AE7

AE9
AE11
AE13
AE15
AE17
AE25
AE35
AE41
AE43
AE45

AF2

AF4

AF8
AF19
AF25
AF27
AF29
AF31
AF35
AF48
AF50

AG7

AG9
AG11
AG17
AG19
AG29
AG31
AG35
AG41
AG43
AG45

AH2

AJ7

AJ9
AJ11
AJ19
AJ33
AJ35
AJ39
AJ41
AJ43
AJ45

AK2

AK4
AK17
AK19
AK23
AK25
AK27
AK35
AK37
AK48
AK50

AL7

AL9
AL11
AL39
AL41
AL43
AL45
AM15
AM19
AM25
AM29
AM31
AM37

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(9 OF 10)

AP2
AP4
AP7
AP9
AP11
AP17
AP21
AP23
AP25
AP29
AP31
AP33
AP35
AP37
AP41
AP43
AP45
AP48
AP50
AR6
AR8
AR17
AR19
AR21
AR31
AR35
AR37
AT7
AT9
AT11
AT39
AT41
AT43
AT45
AU17
AU37
AV2
AV4
AV48
AV50
AW7
AW9

VSSVSS

AW11
AW13
AW23
AW25
AW27
AW29
AW36
AW39
AW41
AW43
AW45
AY10
B6
B10
B14
B18
B22
B26
B30
B34
B38
B42
B46
BA7
BA9
BA11
BA13
BA16
BA18
BA21
BA23
BA25
BA27
BA29
BA31
BA34
BA36
BA39
BA41
BA43
BA45
BB2
BB4
BB48
BB50
BC11
BC13
BC16
BC18
BC21

BC23
BC25

PCH-PPT-MB-SFF-ES1

BC27
BC29
BC31
BC34
BC36
BC39
BC41
BC43
BC45
BD15
BD24

BE7

BE9
BE11
BE13
BE16
BE18
BE21
BE23
BE25
BE27
BE29
BE31
BE34
BE36
BE39
BE41
BE43
BE45

BF2

BF4
BF15
BF24
BF48
BF50

BH6
BH10
BH14
BH18
BH22
BH26
BH28
BH30
BH32
BH34
BH38
BH42
BH44
BH46
BH48
BK10
BK14
BK18
BK22
BK26
BK30
BK32
BK34
BK38
BK42
BK46

D6
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46

F2

F4
F48
F50

G7

G9
G11
G13
G16
G18
G21
G23
G25
G27
G29
G31
G34
G36

6 3

OMIT_TABLE

U1800

BGA

QP8D-MM915462

(10 OF 10)

G39
G41
G43
J7
J9
J11
J13
J16
J18
J21
J23
J25
J27
J29
J31
J34
J36
J39
J41
J45
K2
K4
K48
K50
L7
L9
L11
L13
L16
L18
L21
L23
L25
L27
L29
L31
L34
L36
L39
L41

VSSVSS

L43
L45
N7
N9
N11
N13
N21
N23
N25
N29
N31
N34
N39
N41
N43
N45
P2
P4
P48
P50
R17
R21
R31
R37
T7
T9
T11
T13
T41
T43
T45
U31
U49
V2
V4
V7
V9
V11
V15
V17
V27
V29
V33
V35
V41
V43
V45
V48
Y15
Y17
Y33
Y35
Y37

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH GROUNDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

23 OF 132

SHEET

22 OF 80

SIZE

D

C

B

A

D

124578

8 7 6 5 4 3

PCH VCCIO BYPASS

L2406

10UH-0.12A-0.36OHM

=PP1V05_S0_PCH

8

17

1 2

0603

PLACE_NEAR=U1800.AP39:2.54mm

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.05V
MAKE_BASE=TRUE

1

C2411

10UF

20%

6.3V

2

CERM-X5R
0402-2

21

PLACE_NEAR=U1800.R27:2.54mm

D

8

21

PLACE_NEAR=U1800.AM17:2.54mm
PLACE_NEAR=U1800.AM17:2.54mm
PLACE_NEAR=U1800.AM17:2.54mm

=PP3V3_S0_PCH_VCCADAC

8

R2450

0

1 2

5%

1/20W

MF

201

C2450

10UF

20%

6.3V

CERM-X5R

0402-2

PLACE_NEAR=U1800.U51:2.54mm
PLACE_NEAR=U1800.U51:2.54mm
PLACE_NEAR=U1800.U51:2.54mm

1

2

C2451

0.1UF

10%
16V

X5R-CERM

0201

PP3V3_S0_PCH_VCCA_DAC_F

C2455

0.01UF

X5R-CERM

0201

10%
16V

1

2

1

2

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

8

21 23

21

=PP1V05_S0_PCH_VCC_DMI

C

=PP3V3_S0_PCH

8

17

=PP5V_S0_PCH

8

25

1 mA

R2405

C2439

PLACE_NEAR=U1800.N36:2.54mm

=PP3V3_SUS_PCH

8

=PP5V_SUS_PCH

8

1 mA S0-S5

B

PLACE_NEAR=U1800.M37:2.54mm

=PP3V3_S0_PCH_VCC3_3

8

21 23

1

C2421

0.1UF

10%
16V

2

X5R-CERM

PLACE_NEAR=U1800.BK28:2.54mm

0201

100

1/20W

201

1UF

10%
10V
X5R
402

R2404

1/20W

C2438

0.1UF

20%
10V

CERM

402

5%
MF

201

12

1

2

12

10

5%
MF

1

2

21 23

PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)

1

5

D2400

NC

NC

BAT54DW-X-G

SOT-363

6

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_PCH_V5REF

PCH V5REF_SUS Filter & Follower

(PCH Reference for 5V Tolerance on USB)

4

2

NC

8

D2400

NC

BAT54DW-X-G

SOT-363

3

PP5V_SUS_PCH_V5REFSUS

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_SUS_PCH_V5REFSUS

=PP3V3_S0_PCH_VCC3_3

PLACE_NEAR=U1800.AF6:2.54mm

NEED PWR CONSTRAINT

NEED PWR CONSTRAINT

1

2

<1 MA

C2423

0.1UF

10%
16V
X5R-CERM
0201

21

=PP1V05_S0_PCH_VCCADPLL

8

21

=PP3V3_S0_PCH_VCC3_3

8

21 23

PLACE_NEAR=U1800.AW16:2.54mm

=PP3V3_S0_PCH_VCC3_3_CLK

8

PLACE_NEAR=U1800.AB19:2.54mm

PCH VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)

=PP3V3_SUS_PCH_VCCSUS

8

21 23

1

C2484

0.1UF

10%
16V

2

X5R-CERM
0201

=PP1V05_S0_PCH_V_PROC_IO

C2416

4.7UF

PCH VCCIO BYPASS

=PP1V05_S0_PCH_VCC_DMI

8

21 23

1

2

1

C2422

0.1UF

10%
16V

2

X5R-CERM
0201

C2418

1UF

20%

6.3V
X5R
0201

PLACE_NEAR=U1800.AM23:2.54mm

PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)

R2451

1 2

R2460

0

1 2

5%
1/16W
MF-LF

402

R2465

0

1 2

5%
1/16W
MF-LF

402

1

5%
1/16W
MF-LF

402

PP1V05_S0_PCH_VCCADPLLA_R

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLB_R

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2413

0.1UF

10%
16V

2

X5R-CERM
0201

PLACE_NEAR=U1800.N27:2.54mm

1

1

C2417

0.1UF

20%

6.3V
X5R
402

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

10%
16V

2

2

X5R-CERM
0201

1

C2419

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.BF40:2.54MM

PLACE_NEAR=U1800.V31:2.54mm

1

C2430

0.1UF

10%
16V

2

X5R-CERM
0201

PLACE_NEAR=U1800.Y19:2.54mm

=PP3V3_S5_PCH_VCCDSW

8

21

PLACE_NEAR=U1800.R12:2.54mm

L2451

10UH-0.12A-0.36OHM

1 2

0603

PLACE_NEAR=U1800.V37:2.54mm

L2460

10UH-0.12A-0.36OHM

1 2

0603

L2465

10UH-0.12A-0.36OHM

1 2

0603

PLACE_NEAR=U1800.BD40:2.54MM

=PP1V8_S0_PCH_VCC_DFTERM

8

20 21

PLACE_NEAR=U1800.AJ13:2.54mm

PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

=PP3V3R1V5_S0_PCH_VCCSUSHDA

8

21 25

=PP3V3_SUS_PCH_VCC_SPI

8

21

C2499

0.1UF

X5R-CERM

PP3V3_S0_PCH_VCC3_3_CLK_F

21

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2453

10UF

20%

6.3V

2

CERM-X5R

0402-1

PLACE_NEAR=U1800.V37:2.54mm

PCH VCCADPLLA Filter
(PCH DPLLA PWR)

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2403

100UF

20%

6.3V

2

CERM-X5R
1206-1

1

2

1

2

PCH VCCADPLLB Filter
(PCH DPLLB PWR)

C2462

100UF

20%

6.3V
CERM-X5R
1206-1

C2402

100UF

20%

6.3V
CERM-X5R
1206-1

PLACE_NEAR=U1800.BF40:2.54MM

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2440

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2441

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2442

1UF

20%

6.3V

2

X5R
0201

1

10%
16V

2

0201

1

C2454

1UF

10%
10V

2

X5R
402

1

C2465

100UF

20%

6.3V

2

CERM-X5R

PLACE_NEAR=U1800.BD40:2.54MM

1206-1

1

C2461

1UF

20%

6.3V

2

X5R
0201

=PP1V05_S0_PCH_VCCIO_SATA

8

17

PLACE_NEAR=U1800.AB15:2.54mm

=PP1V05_S0_PCH_VCCSSC

8

21

PLACE_NEAR=U1800.AC35:2.54mm

=PP1V05_S0_PCH_VCCDIFFCLK

8

17 21

PLACE_NEAR=U1800.AC37:2.54mm

=PP1V05_S0_PCH_VCCIO

8

21 23

21

68 mA

PLACE_NEAR=U1800.BF40:2.54MM

=PP1V05_S0_PCH_VCCASW

8

21

21

69 mA

1

C2466

1UF

20%

PLACE_NEAR=U1800.BD40:2.54MM

6.3V

2

X5R
0201

1

C2444

1UF

20%

6.3V

2

X5R
0201

21

1

2

1

C2452

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.AG13:2.54mm

=PP1V05_S0_PCH_VCC_CORE

8

1

C2481

1UF

20%

6.3V

2

X5R
0201

1

C2429

1UF

20%

6.3V
X5R
0201

1

2

C2414

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.AR25:2.54mm
PLACE_NEAR=U1800.AU25:2.54mm
PLACE_NEAR=U1800.AU29:2.54mm
PLACE_NEAR=U1800.AR29:2.54mm
PLACE_NEAR=U1800.AU27:2.54mm

1

C2426

1UF

20%

6.3V
2

X5R
0201

C2456

1UF

20%

6.3V
X5R
0201

(PCH USB 1.05V PWR)

8

21

1

C2475

1UF

20%

6.3V

2

PLACE_NEAR=U1800.R33:2.54mm

X5R
0201

1

C2434

1UF

20%

6.3V

2

X5R
0201

1

C2482

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.AB21:2.54mm
PLACE_NEAR=U1800.AB21:2.54mm
PLACE_NEAR=U1800.AB21:2.54mm
PLACE_NEAR=U1800.AB21:2.54mm

1

C2407

1UF

20%

6.3V

2

X5R
0201

1

C2496

1UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.AB27:2.54mm

=PP3V3_SUS_PCH_VCCSUS_USB

PLACE_NEAR=U1800.U27:2.54mm

=PP3V3_SUS_PCH_VCCSUS

8

21 23

=PP1V05_S0_PCH_VCCIO

8

21 23

PLACE_NEAR=U1800.AJ17:2.54mm

PCH VCCCORE BYPASS

(PCH 1.05V CORE PWR)

1

C2483

1UF

20%

6.3V

2

X5R
0201

1

C2463

1UF

20%

6.3V

2

X5R
0201

C2428

X5R-CERM1

22UF

6.3V
0603

C2460

CERM-X5R

20%

10UF

20%

6.3V

0402-2

C2401

CERM-X5R

1

C2420

2

X5R-CERM1

10UF

6.3V

0402-2

22UF

12

1

C2446

1UF

20%

6.3V

2

X5R
0201

D

1

C2476

1UF

20%

6.3V

2

X5R
0201

1

C2469

1UF

20%

6.3V

2

X5R
0201

C

1

2

1

20%

2

B

1

20%

6.3V
2

0603

A

=PP3V3_S0_PCH_VCC3_3

8

21 23

PLACE_NEAR=U1800.T39:2.54mm

1

C2424

0.1UF

10%
16V

2

X5R-CERM
0201

=PP3V3_S0_PCH_VCC3_3

8

21 23

PLACE_NEAR=U1800.AC19:2.54mm

1

C2486

0.1UF

10%
16V

2

X5R-CERM
0201

1

C2485

0.1UF

10%
16V

2

X5R-CERM
0201

PLACE_NEAR=U1800.R40:2.54mm

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

PCH DECOUPLING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

24 OF 132

SHEET

23 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

=PPVCCIO_S0_XDP

8

24

=PP3V3_S0_XDP

8

XDP_CPU_PREQ_L

11 72

BI

XDP_CPU_PRDY_L

11 72

D

(R2560-R2563)

XDP_CPU:BPM

XDP_CPU:BPM

XDP_CPU:BPM

XDP_CPU:BPM

0

XDP_BPM_L<4>

11 72

IN

XDP_BPM_L<5>

11 72

IN

XDP_BPM_L<6>

11 72

IN

XDP_BPM_L<7>

11 72

IN

CPU_CFG<12>

10 72

IN

CPU_CFG<13>

10 72

IN

CPU_CFG<14>

10 72

IN

CPU_CFG<15>

10 72

IN

CPU_PWRGD

11 20 72

IN

PM_PWRBTN_L

18 24 39

OUT

CPU_CFG<0>

10 24 72

OUT

PM_PCH_SYS_PWROK

18 39 66

OUT

R2560
R2561
R2562
R2563

R2564
R2565
R2566
R2567

PLACE_NEAR=U1000.C60:2.54mm

PLACE_NEAR=U4900.P17:2.54mm

PLACE_NEAR=U1000.B57:2.54mm

R2500
R2502

R2501
R2504

1 2

0

1 2

0

1 2

0

1 2

(R2564-R2567)

XDP_CPU:CFG

XDP_CPU:CFG

XDP_CPU:CFG

XDP_CPU:CFG

0

1 2

0

1 2

0

1 2

0

1 2

XDP

1K

1 2

XDP

0

1 2

XDP

1K

1 2

XDP

330

1 2

5% 201MF

1/20W

5% MF

1/20W

5% MF

5% 201MF

1/20W
1/20W

5% 201

1/20W

5% 201MF

1/20W

5% MF

1/20W

5% 201MF

5%

1/20W

1/20W

5% 201MF

1/20W

5% 201MF

201
201

MF

201

201MF

MF

1/20W

5% 201

1/20W

C

XDP SIGNALS

XDP_DA0_USB_EXTA_OC_L

24

OUT

XDP_DA1_USB_EXTB_OC_L

24

OUT

XDP_DA2_USB_EXTC_OC_L

24

OUT

XDP_DA3_USB_EXTD_OC_L

24

OUT

XDP_DB0_USB_EXTB_OC_EHCI_L

24

OUT

XDP_DB1_USB_EXTD_OC_EHCI_L

24

OUT

XDP_DB2_AP_PWR_EN

24

IN

XDP_DB3_SDCONN_STATE_CHANGE

24

OUT

XDP_FC0_MEM_VDD_SEL_1V5_L

24

OUT

XDP_FC1

24

OUT

XDP_DC0_ISOLATE_CPU_MEM_L

24

IN

XDP_DC1_MXM_GOOD

24

IN

XDP_DC2_DP_AUXCH_ISOL

24

IN

XDP_DC3_SATARDRVR_EN

24

IN

XDP_DD0_DP_GPU_TBT_SEL

24

IN

XDP_DD1_JTAG_ISP_TCK

24

IN

XDP_DD2_AUD_IPHS_SWITCH_EN

24

IN

XDP_DD3_ENET_LOW_PWR

24

IN

B

PCH/XDP Signal Isolation Notes:

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3
doc id 404081.
Initially, stuffing both 33 and 0 ohms and validate whether
it is functional in that state, else add BOM options.

- For isolated GPIOs:

- ’Output’ non-XDP signals require pulls.

- ’Output’ PCH/XDP signals require pulls.

R252x, R253x, R257x and R259x should be placed where signal path
needs to split between route from PCH to J2550
and path to non-XDP signal destination.

ALL_SYS_PWRGD

39 66

IN

18 24 39

OUT

PM_PWRBTN_L

PLACE_NEAR=J2550.39:2.54mm

PLACE_NEAR=U4900.P17:2.54mm

R2584

R2585

R2520
R2521
R2522
R2523

R2524
R2525
R2526
R2527
R2528

R2529
R2530

R2531
R2532
R2533
R2534
R2535

R2536
R2537

(R2520-R2537)

33
33
33
33

33
33
33
33
33

33
33

33
33
33
33
33

33
33

XDP

1K

1 2

XDP

0

1 2

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

XDP

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2

1 2

1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2

5% 201MF

5% 201MF

PCH SIGNALS

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

5% 201MF
5% 201MF
5% 201MF

5% 201MF

5% 201MF
5%
5% MF
5% 201MF
5% 201MF
5% 201MF

5% 201MF
5% 201MF

1/20W

1/20W

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

1/20W
1/20W

1/20W

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

1/20W
1/20W

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

A

1/20W

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

201MF

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

201

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

24 42

24 42

17 24

IN

XDP_BPM_L<0>

11 72

IN

XDP_BPM_L<1>

11 72

IN

XDP_BPM_L<2>

11 72

IN

XDP_BPM_L<3>

11 72

IN

CPU_CFG<10>

10 72

IN

CPU_CFG<11>

10 72

IN

XDP_OBSDATA_B<0>
XDP_OBSDATA_B<1>

XDP_OBSDATA_B<2>
XDP_OBSDATA_B<3>

72

XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L

XDP_CPU_CFG<0>
XDP_VR_READY

=SMBUS_XDP_SDA

24 42

BI

=SMBUS_XDP_SCL

24 42

IN

XDP_CPU_TCK

11 24 72

OUT

R2581

1 2

201 MF

1K

1/20W

5%

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_DC1_PCH_GPIO35_MXM_GOOD

TP_XDP_PCH_OBSFN_A<0>

7

TP_XDP_PCH_OBSFN_A<1>

7

XDP_DA0_USB_EXTA_OC_L

24

XDP_DA1_USB_EXTB_OC_L

24

XDP_DA2_USB_EXTC_OC_L

24

XDP_DA3_USB_EXTD_OC_L

24

TP_XDP_PCH_OBSFN_B<0>

7

TP_XDP_PCH_OBSFN_B<1>

7

XDP_DB0_USB_EXTB_OC_EHCI_L

24

XDP_DB1_USB_EXTD_OC_EHCI_L

24

XDP_DB2_AP_PWR_EN

24

XDP_DB3_SDCONN_STATE_CHANGE

24

XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3

=SMBUS_XDP_SDA

BI

=SMBUS_XDP_SCL

IN

XDP_PCH_TCK

OUT

NO STUFF

R2580

1 2

201 MF

1K

R2540

1/16W
MF-LF

402

5%

1

1K

5%

2

OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

19 24

IN

19 24

IN

19

IN

19

IN

19

IN

19

IN

19 24

19 24

IN

20 24

IN

20 24

IN

20 24

20

17 24

17 24

20

20 24

20 24

20 24

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0
OBSDATA_B1

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

HOOK1

HOOK2
HOOK3

TCK1
TCK0

C2500

0.1UF

X7R-CERM

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

HOOK1

HOOK2
HOOK3

TCK1
TCK0

C2580

0.1UF

X7R-CERM

CPU Micro2-XDP

CRITICAL
XDP_CONN

J2500

DF40RC-60DP-0.4V

M-ST-SM1

62

2
4
6

10

20

30

40

SDA
SCL

50

NC

XDP

10%
16V

0402

1

2

60

518S0847

PCH Micro2-XDP

CRITICAL
XDP_CONN

J2550

DF40RC-60DP-0.4V

M-ST-SM1

62

2
4
6

10

20

30

40

SDA
SCL

XDP

10%
16V

0402

1

2

50

NC

60

518S0847

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

61

1
3
5
78
9
1112
1314
1516
1718
19
2122
2324
2526
2728
29
3132
3334
3536
3738
39
4142
4344
4546
4748
49
5152
5354
5556
5758
59

6364

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C2501

0.1UF

10%
16V

2

X7R-CERM
0402

=PP3V3_S5_XDP

61

1
3
5
78
9
1112
1314
1516
1718
19
2122
2324
2526
2728
29
3132
3334
3536
3738
39
4142
4344
4546
4748
49
5152
5354
5556
5758
59

6364

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C2581

0.1UF

10%
16V

2

X7R-CERM
0402

CPU_CFG<16>
CPU_CFG<17>

CPU_CFG<0>
CPU_CFG<1>

CPU_CFG<2>
CPU_CFG<3>

CPU_CFG<8>
CPU_CFG<9>

CPU_CFG<4>
CPU_CFG<5>

CPU_CFG<6>
CPU_CFG<7>

XDP_CPU_CLK100M_P

72

XDP_CPU_CLK100M_N

72

XDP_CPURST_L
XDP_DBRESET_L

XDP_CPU_TDO
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TMS

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

OUT

IN
OUT
OUT
OUT

10 72

10 72

10 24 72

10 72

10 72

10 72

10 72

10 72

10 72

10 72

10 72

10 72

11 24 25 72

11 24 72

11 24 72

11 24 72

11 24 72

R2515
R2516

R2505

PCH SIGNALS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

19 24

OUT

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

19 24

OUT

XDP_DB2_PCH_GPIO10_AP_PWR_EN

19 24

IN

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

19 24

OUT

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

17 24

IN

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

20 24

OUT

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

17 24

IN

XDP_FC1_TBT_CIO_PLUG_EVENT

20 24

OUT

8

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

20 24 60

IN

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

20 24

OUT

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

20 24

OUT

XDP_FC0_MEM_VDD_SEL_1V5_L
XDP_FC1

XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD

XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN

TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>

XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR

TP_XDP_PCH_HOOK4
TP_XDP_PCH_HOOK5

XDPPCH_PLTRST_L
XDP_DBRESET_L

XDP_PCH_TDO
TP_XDP_PCH_TRST_L
XDP_PCH_TDI
XDP_PCH_TMS

24

24

24

24

24

24

7

7

24

24

24

24

7

7

7

OUT

OUT
OUT

IN

IN

25

11 24 25 72

17 24

17 24

17 24

0

0

1K

R2590
R2591
R2596
R2597

R2573
R2570

R2572
R2574

R2595

11 24 72

11 24 72

11 24 72

11 24 72

11 24 72

1 2

1 2

1 2

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

PLACE_NEAR=R1841.1:2.54mm

XDP

XDP

XDP

R2575
R2576
R2577

ITPXDP_CLK100M_P

1/20W

5% 201MF

PLACE_NEAR=R1840.1:2.54mm

ITPXDP_CLK100M_N

1/20W

5% 201MF

PLACE_NEAR=U1000.G3:2.54mm

CPU_RESET_L

1/20W

5% MF

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

1K

1 2

PPDDR:1V5

0

1 2

0
0

XDP_PCH_TDO

17 24

XDP_PCH_TDI

17 24

XDP_PCH_TMS

17 24

XDP_PCH_TCK

17 24

R2510

R2511

R2512
R2513

R2514

201

5% 201MF
5% 201MF
5% 201

5% MF

5% 201MF

5% 201MF

5%

1 2
1 2
1 2

1K series R on PCH Support Page

SYNC_MASTER=J30_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

5% 201MF
5% 201MF

R2550

R2551

R2552
R2556

51

51

51

51

51

17 72

IN

17 72

IN

11 25

IN

Non-XDP Signals

MF 2015%

1/20W
1/20W
1/20W

MF

1/20W

1/20W

1/20W

1/20W

1/20W

1/20W

201

MF 2015%

201MF

1/20W

MF02015%

AUD_IPHS_SWITCH_EN_PCH

1/20W
1/20W

51

51

51

51

CPU & PCH XDP

Apple Inc.

R

6 3

=PPVCCIO_S0_XDP

8

24

PLACE_NEAR=J2500.52:2.54mm

XDP

2 1

XDP

2 1

XDP

2 1

XDP

2 1

XDP

2 1

SDCONN_STATE_CHANGE

1/20W

5% 201MF

PLACE_NEAR=U1000.K61:2.54mm

1/20W

5% 201MF

PLACE_NEAR=U1000.H59:2.54mm

1/20W

5% 201MF

PLACE_NEAR=U1000.J58:2.54mm

1/20W

5% 201MF

PLACE_NEAR=U1000.H63:2.54mm

1/20W

5% 201MF

USB_EXTA_OC_L
USB_EXTB_OC_L

AP_PWR_EN

SATARDRVR_EN

ISOLATE_CPU_MEM_L

DP_AUXCH_ISOL

TBT_CIO_PLUG_EVENT_ISOL

MEM_VDD_SEL_1V5_L

JTAG_ISP_TCK

ENET_LOW_PWR_PCH

=PP1V05_SUS_PCH_JTAG

8

PLACE_NEAR=J2550.52:2.54mm

XDP

2 1

XDP

2 1

XDP

2 1

XDP

2 1

1/20W

5% 201MF

PLACE_NEAR=U1800.K5:2.54mm

1/20W

5% 201MF

PLACE_NEAR=U1800.H7:2.54mm

1/20W

5% 201MF

PLACE_NEAR=U1800.J3:2.54mm

1/20W

5% 201MF

SYNC_DATE=07/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

38

IN

7

36

IN

19 36 66

OUT

25

IN

17

OUT

27

OUT

17 25

OUT

IN

OUT

20 20 24

OUTOUT

20 25

OUT

9

20 25

OUT

<E4LABEL>

<BRANCH>

25 OF 132

24 OF 80

20

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

GPIO Glitch Prevention

=PP3V3_S3_PCH_GPIO

8

19 25

CRITICAL

ENET_LOW_PWR_PCH

20 24

IN

PM_PCH_PWROK

18 25 66

IN

FW_PWR_EN_PCH

20

D

IN

=PP3V3_S3_PCH_GPIO

8

19 25

1

A1

2

B1

5

A2

6

B2

U2650

8

VCC

SOT833

08

GND

4

74LVC2G08GT

1

C2650

0.1UF

20%
10V

2

CERM
402

7

3

ENET_LOW_PWR

FW_PWR_EN

Y1

Y2

9 9

OUT

9

OUT

11 24 72

IN

PCH Reset Button

=PP3V3_S0_SB_PM

8

66

1

R2695

10K

5%
1/16W
MF-LF
402

2

0

PM_SYSRST_L

OMIT

1

R2697

0

5%
1/16W
MF-LF
402

2

SILK_PART=SYS RESET

XDP_DBRESET_L

XDP

R2696

1 2

5%
1/16W
MF-LF

402

7

18 39

OUT

Platform Reset Connections

19 27

IN

PLT_RESET_L

MAKE_BASE=TRUE

Unbuffered

R2681

33

1 2

5%
1/16W
MF-LF

402

R2671

0

1 2

5%
1/16W
MF-LF

402

R2683

33

1 2

5%
1/16W
MF-LF

402

XDP

R2689

1K

1 2

5%
1/16W
MF-LF

402

LPC_RESET_L
LPCPLUS_RESET_L

MAKE_BASE=TRUE

SMC_LRESET_L

PCA9557D_RESET_L

XDPPCH_PLTRST_L

75

OUT

7

41

OUT

39

OUT

31

OUT

24

OUT

D

SDCONN_STATE_CHANGE ISOLATION

TBT_PWR_EN_PCH

17

IN

LPC_PWRDWN_L

7

18 39 41

IN

AUD_IPHS_SWITCH_EN_PCH

20 24

IN

PM_PCH_PWROK

18 25 66

IN

CRITICAL

1

A1

2

B1

5

A2

6

B2

U2652

8

VCC

SOT833

08

GND

4

74LVC2G08GT

C

33 MHz Clock Series Termination

LPC_CLK33M_SMC_R

19 75

IN

LPC_CLK33M_LPCPLUS_R

19

IN

PCH_CLK33M_PCIOUT

19

IN

PLACE_NEAR=U1800.G51:5.1MM

PLACE_NEAR=U1800.E49:5.1MM

PLACE_NEAR=U1800.G45:2.54MM:5.1MM

R2655

12

1 2

5%

1/20W

MF

201

R2656

1 2

R2659

1 2

Y1

Y2

22

5%

1/20W

MF

201

22

5%

1/20W

MF

201

1

2

7

3

C2652

0.1UF

20%
10V
CERM
402

TBT_PWR_EN

AUD_IPHS_SWITCH_EN

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIIN

=PP3V3_S3_SDBUF

SDCONN_STATE_CHANGE

24

OUT

33

OUT

54

OUT

CRITICAL

TC7SZ08AFEAPE

SOT665

5

Y

U2630

3

A

B

4

2

1

1

C2630

0.1UF

10%

6.3V

2

X5R
201

8

R2641

470K

1/20W

=PP3V3_S4_SMC

1

5%
MF

201

2

SDCONN_STATE_CHANGE_RIO

=PP3V3_S4_SMC

8

25 36 40

Q2640

SSM6N37FEAPE

SDCONN_STATE_CHANGE_SMC

7

40

OUT

7

39 75

OUT

7

41 75

OUT

7

17 75

OUT

SOT563

D

3

=PP3V3_S0_PCH_GPIO

8

17 18 19 20 35

DP_AUXCH_ISOL

17 24

IN

1

R2640

470K

5%

1/20W

MF

201

2

5

SDCONN_STATE_CHANGE_INV

S G

4

R2630

CRITICAL

Q2630

SOD-VESM-HF

SSM3K15FV

Q2640

SSM6N37FEAPE

SOT563

D

6

10K

1 2

5%

1/20W

MF

201

D

1

G S

2

S G

1

DP_AUXIO_EN INVERSION

DP_AUXIO_EN

3

2

C2639

0.1UF

X5R-CERM

0201

10%
16V

1

2

=PP3V3_S0_RSTBUF

8

25

36

IN

=PP3V3_S0_RSTBUF

8

25

69 70

OUT

8

25 36 40

C2680

0.1UF

CERM

C2690

0.1UF

CERM

20%
10V

402

20%
10V

402

Buffered

CRITICAL

5

MC74VHC1G08

1

2

1

2

U2680

3

SC70-HF

4

PLT_RST_BUF_L

MAKE_BASE=TRUE

1

R2680

100K

5%
1/16W
MF-LF
402

2

Buffered CPU reset

CRITICAL

5

U2690

74LVC1G07

SC70

2

1

2

4

PLT_RST_CPU_BUF_L

NC

3

1

NC

MAKE_BASE=TRUE

1

R2690

100K

5%
1/16W
MF-LF
402

2

R2686

0

1 2

5%
1/16W
MF-LF

402

R2688

0

1 2

5%
1/16W
MF-LF

402

R2693

1 2

1/16W
MF-LF

=ENET_RESET_L
ENET_RESET_L

MAKE_BASE=TRUE

=TBT_RESET_L

Series R on Pg38, R3803

AP_RESET_L

0

BKLT_PLT_RST_L

5%

402

CPU_RESET_L

VTT voltage divider on CPU page

36

OUT

7

35

OUT

36

OUT

71

OUT

11 24

OUT

C

System RTC Power Source & 32kHz / 25MHz Clock Generator

B

VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_B: Ethernet power rail for XTAL circuit.
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

GreenClk 25MHz Power

=PP3V3_S0_SYSCLK

8

=PPVBAT_G3_SYSCLK

8

Coin-Cell: VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)

=PP3V3_S5_SYSCLK

8

Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5
No bypass necessary

NO STUFF

R2607

0

Ethernet XTAL Power (Unused on J5)
SB XTAL Power
TBT XTAL Power

A

=PPVDDIO_S0_SBCLK

8

=PPVDDIO_TBT_CLK

8

CRITICAL

C2605

12PF

12

5%

50V

CERM

402

CRITICAL

C2606

12PF

1 2

5%

50V

CERM

402

1 2

NO STUFF

C2624

0.1UF

CERM

20%
10V

402

1

2

C2622

0.1UF

CERM

20%
10V

402

1

2

C2620

SYSCLK_CLK25M_X2

CRITICAL

13

NC

24

Y2605

3.2X2.5MM-SM

NC

25.000MHZ-20PPM-12PF-85C

NOTE: 30 PPM crystal required

5%
1/16W
MF-LF

402

0.1UF

20%
10V

CERM

402

1

2

R2605

0

1 2

5%
1/16W
MF-LF

402

GND_SYSCLK_25M_B

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

1

R2608

0

5%
1/16W
MF-LF
402

2

NO STUFF

1

R2606

2

SYSCLK_CLK25M_X1

C2602

SYSCLK_CLK25M_X2_R

1M

5%
1/16W
MF-LF
402

1UF

10%
10V
X5R

402-1

13

2

5

VBAT and +V3.3A are
internally ORed to

+3.42V

+V3.3A

11

6

14

3
4

VDD_25M

U2600

SLG3NB148A

CRITICAL

VDDIO_25M_A
VDDIO_25M_B
VDDIO_25M_C

X2
X1

71016

TQFN

VDD_RTC_OUT

THRM

GND

1

2

create VDD_RTC_OUT.
+V3.3A should be first

available ~3.3V power
to reduce VBAT draw.

12

32KHZ_A

9

25MHZ_A

8

25MHZ_B

15

25MHZ_C

1

PAD

17

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB
TP_SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_TBT
=PPVRTC_G3_OUT
For SB RTC Power

1

C2610

1UF

10%

6.3V

2

CERM
402

6 3

PCH ME Disable Strap

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

Q2620

SSM6N37FEAPE

SOT563

=PP3V3R1V5_S0_PCH_VCCSUSHDA

8

21 23

3

Q2620

SSM6N37FEAPE

SPI_DESCRIPTOR_OVERRIDE_L

39 40

17 74

OUT

17 74

OUT

33 74

8

OUT

IN

D

SOT563

5

SPI_DESCRIPTOR_OVERRIDE_LS5V

S G

SPI_DESCRIPTOR_OVERRIDE

4

6

D

2

SG

1

SYNC_MASTER=MASTER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

=PP5V_S0_PCH

8

23

1

R2620

100K

5%
1/20W
MF
201

2

1

R2621

1K

5%
1/20W
MF
201

2

HDA_SDOUT_R

IPD = 9-50k

Chipset Support

Apple Inc.

R

17 75

OUT

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

26 OF 132

SHEET

25 OF 80

SIZE

B

A

D

124578

8 7 6 5 4 3

12

D

HUB_NONREM1_1

C

HUB_NONREM1_0

B

=PP3V3_S3_USB_HUB

8

26

CRITICAL

C2709

HUB_NONREM0_1

1

1

402

402

5%

2

1

5%

2

R2703

10K

5%
1/16W
MF-LF
402

2

HUB_NONREM0_0

1

R2705

10K

5%
1/16W
MF-LF
402

2

R2702

10K

1/16W
MF-LF

R2704

10K

1/16W
MF-LF

J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION
J3X USE 197S0284 FOR Y2700 TO SAVE COST

BYPASS=U27000.5::5MM

C2700

4.7UF

20%

6.3V
X5R
603

BYPASS=U2700.15::2MM

BYPASS=U2700.23::5MM

C2704

4.7UF

20%

6.3V
X5R
603

CRITICAL

Y2700

SM-2

24.000MHZ-16PF

1 3

1

18PF

5%

50V

2

CERM

402

=PP3V3_S3_USB_RESET

8

2 4

NC

R2700

1M

1 2

5%
1/16W
MF-LF

402

CRITICAL

1

2

1

2

OMIT_TABLE

NC

1

R2712

10K

5%
1/16W
MF-LF
402

2

C2701

X7R-CERM

USB_HUB_RESET_L

1

0.1UF

10%
16V

2

0402

BYPASS=U2700.10::2MM

1

C2705

0.1UF

10%
16V

2

X7R-CERM

0402

BYPASS=U2700.36::2MM

BYPASS=U2650.29::2MM

CRITICAL

1

C2710

18PF

5%
50V

2

CERM
402

USB MUX FOR LS/FS INTERNAL DEVICES

BYPASS=U2700.5::2MM

C2706

R2701

1 2

1/16W
MF-LF

1

R2706

10K

5%
1/16W
MF-LF
402

2

26

1

C2702

0.1UF

10%
16V

2

X7R-CERM
0402

BYPASS=U2700.23::2MM

0.1UF

10%
16V

X7R-CERM

0402

100

5%

402

1

2

USB_HUB_NONREM0
USB_HUB_NONREM1
USB_HUB_CFG_SEL0
USB_HUB_CFG_SEL1

1

2

1

C2703

0.1UF

10%
16V

2

X7R-CERM
0402

C2708

0.1UF

10%
16V

X7R-CERM

0402

USB_HUB_RESET_L

26

USB_HUB_XTAL1
USB_HUB_XTAL2

R2707

10K

5%
1/16W
MF-LF
402

PART#

197S0485

1

2

11

TEST

26

RESET*

33

XTALIN/CLKIN

32

XTALOUT

28

SUSP_IND/LOCAL_PWR/NON_REM0

22

SDA/SMBDATA/NON_REM1

24

SCL/SMBCLK/CFG_SEL0

25

HS_IND/CFG_SEL1

DESCRIPTION

QTY

XTAL,24MHZ,60PPM,16PF,2.5X2X0.55MM,90C

1

510152329

VDD33

SYM VER 1

U2700

USB2513B

QFN

36

OMIT_TABLE

THRM_PAD

37

PPUSB_HUB2_VDD1V8

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8PLL

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

14

34

CRFILT

PLLFILT

USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1

USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2

USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3

PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*

REFERENCE DESIGNATOR(S)

OCS1*

IPU

OCS2*

IPU

OSC3*

IPU
IPU

RBIAS

VBUS_DET

USBDM_UP
USBDP_UP

Y2700

1

C2711

0.1UF

10%
16V

2

X7R-CERM
0402

1

USBHUB_DN1_NUSB_HUB_TEST

2

USBHUB_DN1_P

3

USBHUB_DN2_N

4

USBHUB_DN2_P

6

USBHUB_DN3_N

7

USBHUB_DN3_P

8

USBHUB_DN4_N

NC

9

USBHUB_DN4_P

NC

12

TP_USB_HUB_PRTPWR1

16

TP_USB_HUB_PRTPWR2

18

TP_USB_HUB_PRTPWR3

20

TP_USB_HUB_PRTPWR4

NC

13

TP_USB_HUB_OCS1

17

TP_USB_HUB_OCS2

19

TP_USB_HUB_OCS3

21

TP_USB_HUB_OCS4

NC

35

USB_HUB_RBIAS

27

USB_HUB_VBUS_DET

CKPLUS_WAIVE=ndifpr_badterm

30

USB_HUB_UP_N

31

USB_HUB_UP_P

PCH PORT 7 (EHCI1)

CRITICAL BOM OPTION

CRITICAL

1

C2712

1UF

10%
16V

2

X5R
402

9

BI

9

BI

9

26

9

26

9

BI

9

BI

9

BI

9

BI

19 74

BI

19 74

BI

BOM GROUP

HUB_ALLREM
HUB_1NONREM
HUB_2NONREM
HUB_3NONREM

NON_REM 1 : NON_REM 0 STRAP PIN CFG
0 : 0 ALL PORTS ARE REMOVABLE

0 : 1 PORT 1 IS NON REMOVABLE
1 : 0 PORT 1&2 ARE NON REMOVABLE

CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STRAPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

TABLE_5_HEAD

TABLE_5_ITEM

1 : 1 PORT 1&2&3 ARE NON REMOVABLE

HUB_NONREM1_0,HUB_NONREM0_0
HUB_NONREM1_0,HUB_NONREM0_1
HUB_NONREM1_1,HUB_NONREM0_0
HUB_NONREM1_1,HUB_NONREM0_1

PART#

338S0824
338S0923
338S0983

D1,D2 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B

1

C2714

1UF

10%
16V

2

X5R
402

BLUETOOTH FOR D1/D2 & J3X

TRACKPAD/KEYBOARD FOR D1/D2, IR FOR J3X

SMC DEBUG PORT FOR D1/D2, TPAD/KBD FOR J3X

NC FOR D1/D2, SMC DEBUG PORT FOR J3X

26

26

26

26

1

C2713

0.1UF

10%
16V

2

X7R-CERM
0402

=PP3V3_S3_USB_HUB

1

R2708

10K

5%
1/16W
MF-LF
402

2

CRITICAL

1

R2709

12K

1%
1/16W
MF
402

2

8

26

TO CONNECT TP/KB TO PCH XHCI
NOSTUFF R5701 & R5702, STUFF R2720 & R2721

USB_EXTD_XHCI_N

19 74

BI

J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B

USBHUB_DN3_N

9

26

USBHUB_DN3_P

9

26

USBHUB_DN4_N

9

26

USBHUB_DN4_P

9

26

USBHUB_DN2_N

9

26

USBHUB_DN2_P

9

26

TO PCH XHCI

USB_EXTD_XHCI_P

19 74

BI

BOM OPTIONS

BOM TABLE

DESCRIPTION

QTY

USB HUB 2514B

1

USB HUB 2513B

1

USB HUB 2512B

1

NOSTUFF

1

R2716

10K

5%
1/16W
MF-LF
402

2

NOSTUFF

R2721

27

1 2

5%
1/16W
MF-LF

402

NOSTUFF

1

R2717

10K

5%
1/16W
MF-LF
402

2

NOSTUFF

R2720

1 2

1/16W
MF-LF

REFERENCE DESIGNATOR(S)

1

R2718

10K

2

27

5%

402

U2700
U2700
U2700

NOSTUFF

5%
1/16W
MF-LF
402

NOSTUFF

1

R2719

10K

5%
1/16W
MF-LF
402

2

USB_TPAD_R_N

USB_TPAD_R_P

CRITICAL BOM OPTION

CRITICAL
CRITICAL
CRITICAL

USBHUB:2514B
USBHUB:2513B
USBHUB:2512B

=PP3V3_S3_USB_HUB

NOSTUFF

1

R2722

10K

5%
1/16W
MF-LF
402

2

1

R2723

10K

2

BI

NOSTUFF

5%
1/16W
MF-LF
402

47 78

TO TP/KB

47 78

BI

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

D

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

8

26

C

B

1

C2715

0.1UF

10%
16V

2

X7R-CERM

BYPASS=U2700.26::2MM

A

0402

PCH PORT 9 (EHCI2)

PCH PORT 1 (XHCI)

USB XHCI/EHCI2 PORT MUX FOR EXT B

=PP3V3_S3_USBMUX

8

1

19

BI

74
19 74

BI

19

BI

74
19 74

BI

C2760

0.1UF

USB_EXTB_EHCI_P
USB_EXTB_EHCI_N

USB_EXTB_XHCI_P
USB_EXTB_XHCI_N

20%
10V

CERM

402

2

5
4

7
6

8

9

VCC

M+
M-

U2760

PI3USB102ZLE

TQFN

D+

CRITICAL

D-

GND

3

1

Y+

2

Y-

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

10

SELOE*

USB_EXTB_P
USB_EXTB_N

USB_EXTB_SEL_XHCI

SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT

7

36 74

BI

7

36 74

BI

17

IN

TO CONNECTOR

PCH GPIO60

6 3

SYNC_MASTER=J5_AMD

PAGE TITLE

USB HUB & MUX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/17/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

27 OF 132

SHEET

26 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

PM_SLP_S4_L

7

18 27 36 38 39 66

IN

1

R2805

10K

5%
1/16W
MF-LF
402

2

3

3

D

S G

D

S G

1

2

CPUMEM:S0

C2816

0.1UF

10%
16V
X7R-CERM
0402

P1V5CPU_EN

6

D

SG

1

CRITICAL

CPUMEM:S0

Q2805

SSM6N37FEAPE

SOT563

5

PM_SLP_S3_L

1

R2810

10K

5%
1/16W
MF-LF
402

2

MEMVTT_EN

6

D

SG

1

CRITICAL

CPUMEM:S0

Q2810

SSM6N37FEAPE

SOT563

5

PLT_RESET_L

8

MEM_RESET_L

=PP3V3_S3_MEMRESET

8

27

NO STUFF

1

R2895

20K

5%
1/16W
MF-LF
402

C

2

CPUMEM:S0

R2890

0

12

ISOLATE_CPU_MEM_L

24 27

IN IN

=PP5V_S3_MEMRESET

8

27

CPUMEM:S0

R2815

100K

1/16W
MF-LF

402

1

5%

2

ISOLATE_CPU_MEM_L_R

5%

1/20W

MF

201

CRITICAL

CPUMEM:S0

NOSTUFF

C2817

0.047UF

B

11 27

IN

1

10%

6.3V

2

X5R
201

=MEM_RESET_L

Q2815

SSM6N37FEAPE

SOT563

6

MEMRESET_ISOL_LS5V_L

31

2

D

S G

CPU_MEM_RESET_L

MAKE_BASE=TRUE

1

CPUMEM:S0

R2801

CRITICAL

CPUMEM:S0

Q2800

SSM6N37FEAPE

SOT563

CPUMEM:S0

R2802

CRITICAL

CPUMEM:S0

Q2800

SSM6N37FEAPE

SOT563

CRITICAL

CPUMEM:S0

Q2815

SSM6N37FEAPE

5

S G

4

100K

5

100K

2

1/16W
MF-LF

1/16W
MF-LF

SOT563

402

402

1

5%

2

3

D

SG

4

1

5%

2

6

D

SG

1

D

3

CRITICAL

CPUMEM:S0

Q2805

SSM6N37FEAPE

P1V5CPU_EN_L

CRITICAL

CPUMEM:S0

Q2810

SSM6N37FEAPE

MEMVTT_EN_L

=PP1V5_S3_MEMRESET

1

R2816

1K

5%
1/16W
MF-LF
402

2

SOT563

2

4

SOT563

2

4

OUT

OUT

IN

27 65

7

18 27 36 39 66

9

27

18 27 36 39 66

18 27 36 38 39 66

19 25 27

OUT

8

27

CPUMEM:SLG

PLT_RESET_L

19 25 27

IN

ISOLATE_CPU_MEM_L

24 27

IN

PM_SLP_S3_L

7

IN

PM_SLP_S4_L

7

IN

=MEM_RESET_L

11 27

IN

27 28 29

CPUMEM:S3

R2817

0

1 2

5%
1/16W
MF-LF

402

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

S0

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1

to

2 0 0 1 1 1 1 0 1

A

3 0 0 0 1 X 1 0 0

S3

4 0 0 1 1 X 1 0 1
5 0 1 1 1 0 (*) 1 1 1

to

6 0 1 1 1 1 1 1 1
7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

6 3

=PP3V3_S3_MEMRESET

10%

6.3V
X5R
201

1

2

C2800

0.1UF

S0_READY

1

9

ISOL*

3

6

7

=PP1V5R1V35_S3_CPU_VCCDDR

8

11 13 16

CPUMEM:SLG

10

VDD

U2800

SLG4AP022

TQFN

VTT_EN

GND

VDDIO_EN

RST_OUT*

THRM

PAD

5

11

S0_EN

S3_EN

RST_IN*

1V35 S0 "PGOOD" for CPU

=PP3V3_S5_CPU_VCCDDR

8

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

1

R2822

10K

5%

R2820

27.4K

1/16W
MF-LF

R2821

33.2K

1/16W
MF-LF

1

1%

402

2

1

1%

402

2

P1V35_S0_DIV

C2820

0.047UF

10%
10V

X5R-CERM

0402

1/16W
MF-LF
402

2

PM_MEM_PWRGD_L

3

CRITICAL

Q2820

5

DMB53D0UV

SOT-563

1

2

4

CRITICAL

2

MEMVTT Clamp

2

MEMVTT_EN

4

P1V5CPU_EN

8

MEM_RESET_L

Ensures CKE signals are held low in S3

9

27

OUT

27 65

OUT

27 28 29

OUT

=PP5V_S3_MEMRESET

8

27

SSM6N37FEAPE

=DDRVTT_EN

9

60

IN

R2851

CRITICAL

Q2850

SOT563

5

100K

1/16W
MF-LF

1

5%

402

2

D

SG

SSM6N37FEAPE

VTTCLAMP_EN

3

4

=PPVTT_S0_VTTCLAMP

8

CRITICAL

Q2850

SOT563

NO STUFF

C2851

0.047UF

10%
10V

CERM

402

2

1

2

G

6
D

S
1

VTTCLAMP_L

6

D

SG

1

PM_MEM_PWRGD

Q2820

DMB53D0UV

SOT-563

1

R2850

10

5%
1/10W
MF-LF

603

2

SYNC_MASTER=J5_MLB

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

12

11 18 72

OUT

75mA max load @ 0.75V
60mW max power

SYNC_DATE=07/29/2011

CPU Memory S3 Support

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

<SCH_NUM>

<E4LABEL>

<BRANCH>

28 OF 132

27 OF 80

SIZE

D

C

B

A

D

D

C

MEM_A_A<0>

12 28
30 73

MEM_A_A<1>

12 28
30 73

MEM_A_A<2>

12 28
30 73

MEM_A_A<3>

12 28
30 73

MEM_A_A<4>

12 28
30 73

MEM_A_A<5>

12 28
30 73

MEM_A_A<6>

12 28
30 73

MEM_A_A<7>

12 28
30 73

MEM_A_A<8>

12 28
30 73

MEM_A_A<9>

12 28
30 73

MEM_A_A<10>

12 28
30 73

MEM_A_A<11>

12 28
30 73

MEM_A_A<12>

12 28
30 73

MEM_A_A<13>

12 28
30 73

MEM_A_A<14>

12 28
30 73

MEM_A_A<15>

12 28
30 73

MEM_A_BA<0>

12 28
30 73

MEM_A_BA<1>

12 28
30 73

MEM_A_BA<2>

12 28
30 73

MEM_A_RAS_L

12 28
30 73

MEM_A_CAS_L

12 28
30 73

MEM_A_WE_L

12 28
30 73

MEM_A_ODT<0>

12 28
30 73

30 73

MEM_A_ZQ<0>
MEM_A_ZQ<4>

R2900

240

1/20W

201

C2907

0.47UF

CERM-X5R-1

21

1%
MF

8 7 6 5 4 3

20%

4V

201

=PP1V5R1V35_S3_MEM_A

1

2

2

R2901

240

1%
1/20W
MF
201

1

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

=PP1V5R1V35_S3_MEM_A

VDD

FBGA-10.1X12.6-J4

VSS

A8

B1D8F2F8J1J9L1

PP0V75_S3_MEM_VREFDQ_A

28 31 72

PP0V75_S3_MEM_VREFCA_A

28 31 72

8

28

OMIT_TABLE

U2900

28 31 72

28 31 72

VDDQ

VREFDQ

RESET*

MT41K1G4

512MX8-4GBIT-DDR3-1600

N1

L9

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

N9

8

28

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

B2B8C9D1D9

=PP1V5R1V35_S3_MEM_A

0.47UF

2

1

1

20%

4V

2

201

K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J7

J2
K8
J3

F3
G3
H3

G1
F1

H8
H9

R2911

240

1%
1/20W
MF
201201

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13

A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*
ODT0
ODT1

ZQ0
ZQ1

A1

A8

B1D8F2F8J1J9L1

1

1

C2908

20%

4V

CERM-X5R-1

201

VREFCA

N2

MEM_RESET_L

B3

MEM_A_DQ<5> MEM_A_DQ<9>

DQ0

C7

MEM_A_DQ<6>

DQ1

C2

MEM_A_DQ<4>

DQ2

C8

MEM_A_DQ<7>

DQ3

E3

MEM_A_DQ<1>

E8

MEM_A_DQ<3>

D2

MEM_A_DQ<0>

E7

MEM_A_DQ<2>

C3

MEM_A_DQS_P<0>

DQS

D3

MEM_A_DQS_N<0>

B7
A7

NC NC NCNC

H1

MEM_A_CS_L<1> MEM_A_CS_L<1>

H2

MEM_A_CS_L<0>

G9

MEM_A_CKE<0>

F9

MEM_A_CKE<1>

F7

MEM_A_CLK_P<0>

CK

G7

MEM_A_CLK_N<0>

CK*

A3

NC

79

NC

80

NC

NC

81

NC

82

NC

C2909

0.47UF0.47UF

20%
4V

2

2

CERM-X5R-1
201

27 28 29

12 73
7

12 28 30
73

12 28 30
73

R2910

C2917

CERM-X5R-1

MEM_A_A<0>

12 28 30 73

MEM_A_A<1>

12 28 30 73

MEM_A_A<2>

12 28 30 73

MEM_A_A<3>

12 28
30 73

MEM_A_A<4>

12 28
30 73

MEM_A_A<5>

12 28
30 73

MEM_A_A<6>

12 28
30 73

MEM_A_A<7>

12 28
30 73

MEM_A_A<8>

12 28
30 73

MEM_A_A<9>

12 28
30 73

MEM_A_A<10>

12 28
30 73

MEM_A_A<11>

12 28
30 73

MEM_A_A<12>

12 28
30 73

MEM_A_A<13>

12 28 30 73

MEM_A_A<14>

12 28 30 73

MEM_A_A<15>

12 28 30 73

73

MEM_A_BA<0>

12 28 30

MEM_A_BA<1>

12
28 30 73

MEM_A_BA<2>

12 28 30 73

MEM_A_RAS_L

12
28 30 73

MEM_A_CAS_L

12 28 30 73

MEM_A_WE_L

12 28
30 73

MEM_A_ODT<0>

12 28
30 73

MEM_A_ODT<1>MEM_A_ODT<1>

12 28 30 73 12 28

MEM_A_ZQ<1>
MEM_A_ZQ<5>

12

240

1%

1/20W

MF

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

28 31 72

PP0V75_S3_MEM_VREFCA_A

28 31 72

VDD

VDDQ

OMIT_TABLE

U2910

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

N1

N9

L9

PP0V75_S3_MEM_VREFDQ_A

28 31 72

PP0V75_S3_MEM_VREFCA_A

28 31 72

8

28

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

8

28

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

CS1*
CS0*

CKE0
CKE1

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

C2918

CERM-X5R-1

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

1

1

C2919

0.47UF0.47UF

20%

4V

201

20%
4V

2

2

CERM-X5R-1
201

MEM_RESET_L

MEM_A_DQ<10>
MEM_A_DQ<13>
MEM_A_DQ<15>
MEM_A_DQ<8>
MEM_A_DQ<12>
MEM_A_DQ<14>
MEM_A_DQ<11>

MEM_A_DQS_P<1>
MEM_A_DQS_N<1>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

PP0V75_S3_MEM_VREFDQ_A

28 31 72

PP0V75_S3_MEM_VREFCA_A

=PP1V5R1V35_S3_MEM_A

1

C2927

0.47UF

20%

4V

201

2

R2921

240

1%
1/20W
MF
201201

1

2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

CERM-X5R-1

MEM_A_A<0>

12 28 30 73

MEM_A_A<1>

12 28 30 73

27 28 29

MEM_A_A<2>

12 28 30 73

12 73

MEM_A_A<3>

7

12 28
30 73

MEM_A_A<4>

12 28
30 73

MEM_A_A<5>

12 28
30 73

MEM_A_A<6>

12 28
30 73

MEM_A_A<7>

12 28
30 73

MEM_A_A<8>

12 28
30 73

MEM_A_A<9>

12 28
30 73

MEM_A_A<10>

12 28
30 73

MEM_A_A<11>

12 28
30 73

MEM_A_A<12>

12 28
30 73

MEM_A_A<13>

12 28 30 73

MEM_A_A<14>

12 28 30 73

MEM_A_A<15>

12 28 30 73

MEM_A_BA<0>

12 28 30
73

MEM_A_BA<1>

12 28 30
73

MEM_A_BA<2>

12 28 30 73

12 28 30
73

MEM_A_RAS_L

12 28 30
73

MEM_A_CAS_L

12
28 30
73

MEM_A_WE_L

12
28 30 73

MEM_A_ODT<0>

12 28
30 73

MEM_A_ODT<1>

12 28 30 73

MEM_A_ZQ<2>
MEM_A_ZQ<6>

R2920

12

240 240

1%

1/20W

MF

=PP1V5R1V35_S3_MEM_A

28 31 72

VDD

OMIT_TABLE OMIT_TABLE

U2920

FBGA-10.1X12.6-J4

VSS

B1D8F2F8J1J9L1

PP0V75_S3_MEM_VREFDQ_A

28 31 72

PP0V75_S3_MEM_VREFCA_A

28 31 72

8

28

VDDQ

VREFDQ

RESET*

MT41K1G4

512MX8-4GBIT-DDR3-1600

N1

L9

N9

8

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

B2B8C9D1D9

28

CERM-X5R-1

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

C2928

0.47UF

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

1

1

C2929

0.47UF

20%

4V

201

20%
4V

2

2

CERM-X5R-1
201

MEM_RESET_L

MEM_A_DQ<21>
MEM_A_DQ<23>
MEM_A_DQ<20>
MEM_A_DQ<22>
MEM_A_DQ<16>
MEM_A_DQ<19>
MEM_A_DQ<17>
MEM_A_DQ<18>

MEM_A_DQS_P<2>
MEM_A_DQS_N<2>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

27 28 29

12 73
7

73
12 28 30

12
28 30 73

12 28 30 73

R2930

CERM-X5R-1

MEM_A_A<0>

12 28 30 73

MEM_A_A<1>

12 28 30 73

MEM_A_A<2>

12 28 30 73

MEM_A_A<3>

12 28
30 73

MEM_A_A<4>

12 28
30 73

MEM_A_A<5>

12 28
30 73

MEM_A_A<6>

12 28
30 73

MEM_A_A<7>

12 28
30 73

MEM_A_A<8>

12 28
30 73

MEM_A_A<9>

12 28
30 73

MEM_A_A<10>

12 28
30 73

MEM_A_A<11>

12 28
30 73

MEM_A_A<12>

12 28
30 73

MEM_A_A<13>

12 28 30 73

MEM_A_A<14>

12 28 30 73

MEM_A_A<15>

12 28 30 73

MEM_A_BA<0>

12 28 30
73

MEM_A_BA<1>

12 28 30
73

MEM_A_BA<2>

12 28 30 73

MEM_A_RAS_L

12 28 30
73

MEM_A_CAS_L
MEM_A_WE_L

12 28
30 73

MEM_A_ODT<0>

12 28
30 73

MEM_A_ODT<1>

12 28 30 73

MEM_A_ZQ<3>
MEM_A_ZQ<7>

12

240

1%

1/20W

MF

C2937

0.47UF

2

R2931

1%
1/20W
MF
201201

1

=PP1V5R1V35_S3_MEM_A

1

20%

4V

2

201

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

28 31 72

PP0V75_S3_MEM_VREFCA_A

28 31 72

VDD

U2930

FBGA-10.1X12.6-J4

VDDQ

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

N1

N9

L9

PP0V75_S3_MEM_VREFDQ_A

28 31 72

PP0V75_S3_MEM_VREFCA_A

28 31 72

8

28

NF_TDQS*

B2B8C9D1D9

8

28

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

CS1*
CS0*

CKE0
CKE1

VSSQ

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

C2938

0.47UF

CERM-X5R-1

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

12

1

1

C2939

0.47UF

20%

4V

201

MEM_RESET_L

MEM_A_DQ<28>
MEM_A_DQ<25>
MEM_A_DQ<29>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<26>
MEM_A_DQ<24>
MEM_A_DQ<27>

MEM_A_DQS_P<3>
MEM_A_DQS_N<3>

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CKE<1>
MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

20%
4V

2

2

CERM-X5R-1
201

27 28 29

7

12 73

12 73

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73

12 73

12 28 30 73

12 28 30 73

12 28 30 73

12 28 30 73

12 28 30 73

12 28 30 73

D

C

B

A

C2947

CERM-X5R-1

MEM_A_A<0>

12 28
30 73

MEM_A_A<1>

12 28
30 73

MEM_A_A<2>

12 28
30 73

MEM_A_A<3>

12 28
30 73

MEM_A_A<4>

12 28
30 73

MEM_A_A<5>

12 28
30 73

MEM_A_A<6>

12 28
30 73

MEM_A_A<7>

12 28
30 73

MEM_A_A<8>

12 28
30 73

MEM_A_A<9>

12 28
30 73

MEM_A_A<10>

12 28
30 73

MEM_A_A<11>

12 28
30 73

MEM_A_A<12>

12 28
30 73

MEM_A_A<13>

12 28
30 73

MEM_A_A<14>

12 28
30 73

MEM_A_A<15>

12 28
30 73

MEM_A_BA<0>

12 28
30 73

MEM_A_BA<1>

12 28
30 73

MEM_A_BA<2>

12 28
30 73

MEM_A_RAS_L

12 28
30 73

MEM_A_CAS_L

12 28
30 73

MEM_A_WE_L

12 28
30 73

MEM_A_ODT<0>

12 28
30 73

MEM_A_ODT<1>

12 28
30 73

MEM_A_ZQ<8>
MEM_A_ZQ<12>

R2940

12

240

1% 1%

1/20W

MF

1

0.47UF

20%

4V

2

201

2

R2941

240

1%
1/20W
MF
201201

1

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

=PP1V5R1V35_S3_MEM_A

1

C2900

2.2UF

X5R-CERM

C2940

2.2UF

X5R-CERM

C2901

2.2UF

20%
10V

2

X5R-CERM

402

1

C2941

2.2UF

20%
10V

2

X5R-CERM

402

VDD

FBGA-10.1X12.6-J4

VSS

1

20%
10V

2

402

1

20%
10V

2

402

OMIT_TABLE

VDDQ

U2940

MT41K1G4

512MX8-4GBIT-DDR3-1600

N1

N9

L9

B2B8C9D1D9

8

28

1

C2910

2.2UF

X5R-CERM

C2950

2.2UF

X5R-CERM

C2911

2.2UF

20%
10V

2

X5R-CERM

402

1

C2951

2.2UF

20%
10V

2

X5R-CERM

402

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

20%
10V

402

20%
10V

402

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

1

2

1

2

VREFCA

NC

C2948

0.47UF

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

C2920

2.2UF

X5R-CERM

C2960

2.2UF

X5R-CERM

1

1

C2949

0.47UF

20%

4V

201

20%
4V

2

2

CERM-X5R-1CERM-X5R-1
201

MEM_RESET_L

MEM_A_DQ<32>
MEM_A_DQ<39>
MEM_A_DQ<33>
MEM_A_DQ<35>
MEM_A_DQ<36>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<34>

MEM_A_DQS_P<4>
MEM_A_DQS_N<4>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

1

C2921

2.2UF

20%
10V

2

X5R-CERM

402

1

C2961

2.2UF

20%
10V

2

X5R-CERM

402

20%
10V

402

20%
10V

402

27 28 29

12 73
7

73
12 28 30

R2950

1

2

1

2

0.47UF

2

R2951

240

1/20W
MF
201

1

1

20%

4V

2

201

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

VDD

K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J7

J2
K8
J3

F3
G3
H3

G1
F1

H8
H9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13

A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*
ODT0
ODT1

ZQ0
ZQ1

A1

A8

B1D8F2F8J1J9L1

OMIT_TABLE

U2950

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

L9

N1

VDDQ

N9

B2B8C9D1D9

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

C2958

0.47UF

CERM-X5R-1

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

20%

201

MEM_RESET_L
MEM_A_DQ<41>

MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<42>
MEM_A_DQ<40>
MEM_A_DQ<47>

MEM_A_DQS_P<5>
MEM_A_DQS_N<5>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

1

1

C2959

0.47UF

20%

4V

4V

2

2

CERM-X5R-1
201

MEM_A_A<0>

12 28 30 73

MEM_A_A<1>

12 28 30 73

27 28 29

MEM_A_A<2>

12 28 30 73

12 73

MEM_A_A<3>

12 28

7

30 73

MEM_A_A<4>

12 28
30 73

MEM_A_A<5>

12 28
30 73

MEM_A_A<6>

12 28
30 73

MEM_A_A<7>

12 28
30 73

MEM_A_A<8>

12 28
30 73

MEM_A_A<9>

7

12 73

12 73

MEM_A_A<10>

12 28

7

30 73

MEM_A_A<11>

12 28
30 73

MEM_A_A<12>

12 28
30 73

MEM_A_A<13>

12 28 30 73

MEM_A_A<14>

12 28 30 73

MEM_A_BA<0>

12 28 30
73

MEM_A_BA<1>

12 28 30
73

MEM_A_BA<2>

12 28 30 73

73
12 28 30

MEM_A_RAS_L

12 28 30
73

MEM_A_CAS_L

12 28 30 73

MEM_A_WE_L

12 28
30 73

MEM_A_ODT<0>

12 28
30 73

MEM_A_ODT<1>

12 28 30 73

MEM_A_ZQ<10>
MEM_A_ZQ<14>

R2960

240 240

1%

1/20W

MF

C2957

CERM-X5R-1

MEM_A_A<0>

12 28 30 73

MEM_A_A<1>

12 28 30 73

MEM_A_A<2>

12 28 30 73

MEM_A_A<3>

12 28
30 73

MEM_A_A<4>

12 28
30 73

MEM_A_A<5>

12 28
30 73

MEM_A_A<6>

12 28
30 73

MEM_A_A<7>

12 28
30 73

MEM_A_A<8>

12 28
30 73

MEM_A_A<9>

12 28
30 73

MEM_A_A<10>

12 28
30 73

MEM_A_A<11>

12 28
30 73

MEM_A_A<12>

12 28
30 73

MEM_A_A<13>

12 28 30 73

MEM_A_A<14>

12 28 30 73

MEM_A_A<15> MEM_A_A<15>

12 28 30 73 12 28 30 73

MEM_A_BA<0>

12 28 30
73

MEM_A_BA<1>

12 28 30
73

MEM_A_BA<2>

12 28 30 73

MEM_A_RAS_L

12 28 30
73

MEM_A_CAS_L

12 28 30 73

MEM_A_WE_L

12 28
30 73

MEM_A_ODT<0>

12 28
30 73

MEM_A_ODT<1>

12 28 30 73

MEM_A_ZQ<9>
MEM_A_ZQ<13>

12

240

1%

1/20W

MF

201

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

C2930

2.2UF

X5R-CERM

C2970

2.2UF

X5R-CERM

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C2903

20%
10V

402

20%
10V

402

0.1UF

10%

6.3V

2

2

X5R
201

1

1

C2943

0.1UF

10%

6.3V

2

2

X5R
201

1

C2931

20%
10V

2

402

1

C2971

20%
10V

2

402

1

1

C2904

0.1UF

10%

6.3V

2

X5R

1

C2944

0.1UF

10%

6.3V 6.3V

2

X5R
201

1

C2905

0.1UF

10%

6.3V

2

X5R
201201

1

C2945

0.1UF

10%

2

X5R
201

1

C2913

0.1UF

10%

6.3V

2

X5R
201

1

C2953

0.1UF

10%

6.3V

2

X5R
201

1

C2914

0.1UF

10%

6.3V

2

X5R
201

1

C2954

0.1UF

10%

6.3V

2

X5R
201

6 3

C2967

0.47UF

CERM-X5R-1

12

1

C2915

0.1UF

10%

6.3V

2

X5R
201

1

C2955

0.1UF

10%

6.3V

2

X5R
201

20%

4V

201

2

R2961

240

1%
1/20W
MF
201201

1

1

2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

VDD

K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J7

J2
K8
J3

F3
G3
H3

G1
F1

H8
H9

1

C2923

0.1UF

10%

6.3V

2

X5R
201

1

C2963

0.1UF

10%

6.3V

2

X5R
201

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13

A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*
ODT0
ODT1

ZQ0
ZQ1

A1

A8

B1D8F2F8J1J9L1

OMIT_TABLE

U2960

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

VSS

1

C2924

0.1UF

10%

6.3V

2

X5R
201

1

C2964

0.1UF

10%

6.3V

2

X5R
201

VDDQ

MT41K1G4

N1

N9

L9

1

C2925

0.1UF

10%

6.3V

2

X5R
201

1

C2965

0.1UF

10%

6.3V

2

X5R
201

VREFDQ

RESET*

DQ0
DQ1
DQ2

DQ3
NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

CK*

VSSQ

B2B8C9D1D9

1

2

1

2

1

1

1

2

1

C2934

0.1UF

2

1

C2974

0.1UF

2

10%

6.3V
X5R
201

10%

6.3V
X5R
201

C2969

0.47UF

20%
4V

2

CERM-X5R-1
201

27 28 29 27 28 29

12 73
7

73
12 28 30

R2970

1

C2935

0.1UF

10%

6.3V

2

X5R
201

1

C2975

0.1UF

10%

6.3V

2

X5R
201

C2968

0.47UF

20%

4V

CERM-X5R-1

201

VREFCA

N2

MEM_RESET_L MEM_RESET_L

B3

MEM_A_DQ<52>

C7

MEM_A_DQ<55>

C2

MEM_A_DQ<48>

C8

MEM_A_DQ<54>

E3

MEM_A_DQ<53>

E8

MEM_A_DQ<51>

D2

MEM_A_DQ<49>

E7

MEM_A_DQ<50>

C3

MEM_A_DQS_P<6>

D3

MEM_A_DQS_N<6>

B7
A7

H1

MEM_A_CS_L<1>

H2

MEM_A_CS_L<0>

G9

MEM_A_CKE<0>

F9

MEM_A_CKE<1>

F7

MEM_A_CLK_P<0>

CK

G7

MEM_A_CLK_N<0>

A3

NC

79

NC

80

NC

NC

81

NC

82

NC

C2933

0.1UF

10%

6.3V
X5R
201

C2973

0.1UF

10%

6.3V
X5R
201

C2977

0.47UF

CERM-X5R-1

MEM_A_A<0>

12 28 30 73

MEM_A_A<1>

12 28 30 73

MEM_A_A<2>

12 28 30 73

MEM_A_A<3>

12 28
30 73

MEM_A_A<4>

12 28
30 73

MEM_A_A<5>

12 28
30 73

MEM_A_A<6>

12 28
30 73

MEM_A_A<7>

12 28
30 73

MEM_A_A<8>

12 28
30 73

MEM_A_A<9>

12 28
30 73

MEM_A_A<10>

12 28
30 73

MEM_A_A<11>

12 28
30 73

MEM_A_A<12>

12 28
30 73

MEM_A_A<13>

12 28 30 73

MEM_A_A<14>

12 28 30 73

MEM_A_A<15>

12 28 30 73

MEM_A_BA<0>

12 28 30
73

MEM_A_BA<1>

12 28 30
73

MEM_A_BA<2>

12 28 30 73

MEM_A_RAS_L

12 28 30
73

MEM_A_CAS_L

12 28 30 73

MEM_A_WE_L

12 28
30 73

MEM_A_ODT<0>

12 28
30 73

MEM_A_ODT<1>

12 28 30 73

MEM_A_ZQ<11>
MEM_A_ZQ<15>

12

240

1%

1/20W

MF

20%

4V

201

2

R2971

1%
1/20W
MF
201201

1

C2978

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

0.47UF

CERM-X5R-1

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

VDD

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

SYNC_MASTER=J5_MLB

PAGE TITLE

OMIT_TABLE

U2970

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

VSS

VDDQ

MT41K1G4

N1

N9

L9

B2B8C9D1D9

DDR3 SDRAM Bank A (Rank 0)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

1

C2979

0.47UF

20%

4V

201

MEM_A_DQ<56>
MEM_A_DQ<62>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<61>
MEM_A_DQ<63>
MEM_A_DQ<57>
MEM_A_DQ<58>

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

20%
4V

2

2

CERM-X5R-1
201

NCNCNCNC

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

NC
NC
NC
NC
NC

SYNC_DATE=07/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

29 OF 132

SHEET

28 OF 80

124578

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73

7

12 73

12 73

12 73

12 28 30 73

12 28 30 73

12 28 30 73

12 28 30 73

12 28 30
73

12 28 30 73

SIZE

D

B

A

8 7 6 5 4 3

PP0V75_S3_MEM_VREFDQ_B

29 31 72

PP0V75_S3_MEM_VREFCA_B

29 31 72

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

29 31 72

PP0V75_S3_MEM_VREFCA_B

8

29

=PP1V5R1V35_S3_MEM_B

29 31 72

8

29

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B

29 31 72

PP0V75_S3_MEM_VREFCA_B

29 31 72

8

29

PP0V75_S3_MEM_VREFDQ_B

29 31 72

PP0V75_S3_MEM_VREFCA_B

29 31 72

=PP1V5R1V35_S3_MEM_B

12

8

29

D

C

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

R3100

240

1/20W

C3107

0.47UF

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<0>

2

1

R3101

240

1%

1%

1/20W
MF

MF

201

201 201

1

2

1

20%

4V

2

201

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

=PP1V5R1V35_S3_MEM_B

VDD

VDDQ

OMIT_TABLE

U3100

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

N1

N9

L9

PP0V75_S3_MEM_VREFDQ_B

29 31 72

PP0V75_S3_MEM_VREFCA_B

29 31 72

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

8

29

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

CS1*
CS0*

CKE0
CKE1

0.47UF

1

R3111

240

1%
1/20W
MF

2

1

20%

4V

2

201

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

=PP1V5R1V35_S3_MEM_B

VDD

VDDQ

OMIT_TABLE

U3110

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

N1

N9

L9

PP0V75_S3_MEM_VREFDQ_B

29 31 72

PP0V75_S3_MEM_VREFCA_B

29 31 72

DM/TDQS

NF_TDQS*

VSSQ

B2B8C9D1D9

8

29

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

CS1*
CS0*

CKE0
CKE1

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

C3118

0.47UF

CERM-X5R-1

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

1

1

C3119

0.47UF

20%

4V

201

20%
4V

2

2

CERM-X5R-1
201

MEM_RESET_L
MEM_B_DQ<8>

MEM_B_DQ<15>
MEM_B_DQ<12>
MEM_B_DQ<10>
MEM_B_DQ<13>
MEM_B_DQ<11>
MEM_B_DQ<9>
MEM_B_DQ<14>

MEM_B_DQS_P<1>
MEM_B_DQS_N<1>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_CKE<0>MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

12 29 30 73

12 29 30 73

27 28 29

12 29 30 73

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73

30 73
12 29

12 73

12 73

12 29 30 73

12 29 30 73

73

12 29 30
12 29 30
73
12 29 30
73

12

29 30 73
12 29 30

73
12 29 30

73

12 29
30 73

12 29
30 73

R3120

240

1/20W

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<2>
MEM_B_ZQ<6>MEM_B_ZQ<5>MEM_B_ZQ<4>

2

1%
MF

201

1

MEM_B_A<0>

12 29 30 73

MEM_B_A<1>

12 29 30 73

MEM_B_A<2>

12 29 30 73

MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>

12 29
30 73

MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>

12 29 30 73

MEM_B_A<14>

12 29 30 73

73

MEM_B_BA<0>

12 29 30

MEM_B_BA<1>
MEM_B_BA<2>

12
29 30 73

MEM_B_RAS_L

73

MEM_B_CAS_L

12 29 30 73

MEM_B_WE_L
MEM_B_ODT<0>

12 29
30 73

MEM_B_ODT<1>

12 29 30 73

MEM_B_ZQ<1>

2

240

1%

1/20W

MF

201

1

C3117

CERM-X5R-1

1

1

C3108

0.47UF

4V

CERM-X5R-1

201

VREFCA

N2

MEM_RESET_L

B3

MEM_B_DQ<1>

DQ0

C7

MEM_B_DQ<6>

DQ1

C2

MEM_B_DQ<0>

DQ2

C8

MEM_B_DQ<7>

DQ3

E3

MEM_B_DQ<4>

E8

MEM_B_DQ<3>

D2

MEM_B_DQ<5>

E7

MEM_B_DQ<2>

C3

MEM_B_DQS_P<0>

DQS

D3

MEM_B_DQS_N<0>

B7
A7

NC NC NCNC

H1

MEM_B_CS_L<1>

H2

MEM_B_CS_L<0>

G9
F9

MEM_B_CKE<1>

F7

MEM_B_CLK_P<0>

CK

G7

MEM_B_CLK_N<0>

CK*

A3

NC

79

NC

80

NC

NC

81

NC

82

NC

C3109

0.47UF

20%20%
4V

2

2

CERM-X5R-1
201

27 28 29

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73

7

12 73

12 73
7

12 73

12 73

12 29 30
73

12 29 30
73

12 29 30
73

12 29 30

12 29
30 73

R3110

C3127

0.47UF

1

R3121

240

1%
1/20W
MF
201

2

1

20%

4V

2

201

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

=PP1V5R1V35_S3_MEM_B

VDD

VDDQ

OMIT_TABLE

U3120

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

N1

N9

L9

PP0V75_S3_MEM_VREFDQ_B

29 31 72

PP0V75_S3_MEM_VREFCA_B

29 31 72

8

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

B2B8C9D1D9

29

CERM-X5R-1

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

C3128

0.47UF

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

1

1

C3129

0.47UF

20%

4V

201

20%
4V

2

2

CERM-X5R-1
201

MEM_RESET_L

MEM_B_DQ<21>
MEM_B_DQ<23>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<20>
MEM_B_DQ<22>
MEM_B_DQ<16>
MEM_B_DQ<19>

MEM_B_DQS_P<2>
MEM_B_DQS_N<2>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

12 29 30 73

12 29 30 73

27 28 29

12 29 30 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73

7

12 73

7

12 73

7

12 73

30 73
12 29

12 73

12 73

12 29 30 73

12 29 30 73

12 29 30 73 12 29 30 73 12 29 30 73 12 29

12 29 30
73

12 29 30
73

12 29 30 73

12 29 30
73

12 29 30
73

12 29
30 73

12 29
30 73

12 29 30 73 12 29 30 73

R3130

240

1/20W

C3137

0.47UF

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>
MEM_B_A<15>MEM_B_A<15>MEM_B_A<15>MEM_B_A<15>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<3>
MEM_B_ZQ<7>

1

2

R3131

240

1%

1%

1/20W
MF

MF

201

201

2

1

1

20%

4V

2

201

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

=PP1V5R1V35_S3_MEM_B

VDD

VDDQ

OMIT_TABLE

U3130

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

N1

N9

L9

PP0V75_S3_MEM_VREFDQ_B

29 31 72

PP0V75_S3_MEM_VREFCA_B

29 31 72

NF_TDQS*

B2B8C9D1D9

8

29

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

CS1*
CS0*

CKE0
CKE1

VSSQ

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

C3138

0.47UF

CERM-X5R-1

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

1

1

C3139

20%

4V

201

0.47UF

20%
4V

2

2

CERM-X5R-1
201

MEM_RESET_L

MEM_B_DQ<25>
MEM_B_DQ<30>
MEM_B_DQ<24>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<31>
MEM_B_DQ<29>
MEM_B_DQ<26>

MEM_B_DQS_P<3>
MEM_B_DQS_N<3>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

27 28 29

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73

12 73

12 73

12 29 30 73

12 29 30 73

12 29 30 73

12 29 30 73

12 29 30 73

12 29 30 73

D

C

B

A

C3147

CERM-X5R-1

MEM_B_A<0>

12 29
30 73

MEM_B_A<1>

12 29
30 73

MEM_B_A<2>

12 29
30 73

MEM_B_A<3>

12 29
30 73

MEM_B_A<4>

12 29
30 73

MEM_B_A<5>

12 29
30 73

MEM_B_A<6>

12 29
30 73

MEM_B_A<7>

12 29
30 73

MEM_B_A<8>

12 29
30 73

MEM_B_A<9>

12 29
30 73

MEM_B_A<10>

12 29
30 73

MEM_B_A<11>

12 29
30 73

MEM_B_A<12>

12 29
30 73

MEM_B_A<13>

12 29
30 73

MEM_B_A<14>

12 29
30 73

MEM_B_A<15> MEM_B_A<15> MEM_B_A<15> MEM_B_A<15>

12 29
30 73

MEM_B_BA<0>

12 29
30 73

MEM_B_BA<1>

12 29
30 73

MEM_B_BA<2>

12 29
30 73

MEM_B_RAS_L

12 29
30 73

MEM_B_CAS_L

12 29
30 73

MEM_B_WE_L

12 29
30 73

MEM_B_ODT<0>

12 29
30 73

MEM_B_ODT<1>

12 29
30 73

MEM_B_ZQ<8>
MEM_B_ZQ<12>

2

R3140

240

1%

1/20W

201

1

1

0.47UF

20%

4V

2

201

1

R3141

240

1%
1/20W
MFMF
201

2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

=PP1V5R1V35_S3_MEM_B

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

C3101

2.2UF

20%
10V

2

X5R-CERM

402

1

C3141

2.2UF

20%
10V

2

X5R-CERM

402

C3100

C3140

VDD

OMIT_TABLE

U3140

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

VSS

8

29

1

C3110

2.2UF

20%
10V

2

X5R-CERM

402

1

C3150

2.2UF

20% 20%
10V

2

X5R-CERM

402

MT41K1G4

N1

L9

1

20%
10V

2

402

1

10V

2

402

VDDQ

N9

B2B8C9D1D9

C3111

2.2UF

X5R-CERM

C3151

2.2UF

X5R-CERM

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

20%
10V

402

20%
10V

402

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

1

2

1

2

VREFCA

NC

C3148

0.47UF

CERM-X5R-1

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

C3120

2.2UF

X5R-CERM

C3160

2.2UF

X5R-CERM

1

1

C3149

0.47UF

20%

4V

201

20%
4V

2

2

CERM-X5R-1
201

MEM_RESET_L

MEM_B_DQ<32>
MEM_B_DQ<39>
MEM_B_DQ<37>
MEM_B_DQ<34>
MEM_B_DQ<36>
MEM_B_DQ<38>
MEM_B_DQ<33>
MEM_B_DQ<35>

MEM_B_DQS_P<4>
MEM_B_DQS_N<4>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

1

C3121

2.2UF

20%
10V

2

X5R-CERM

402

1

C3161

2.2UF

20%
10V

2

X5R-CERM

402

27 28 29

7

12 73

7

12 73

7

12 73

7

12 73

12 73

7

12 73

7

12 73

7

12 73

12 73

12 73

12 29 30
73

12 29 30
73

12 29 30
73

12 29 30
73

12 29
30 73

12 29
30 73

R3150

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

1

20%
10V

2

402

1

20%
10V

2

402

C3157

CERM-X5R-1

MEM_B_A<0>

12 29 30 73

MEM_B_A<1>

12 29 30 73

MEM_B_A<2>

12 29 30 73

MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>

30 73

MEM_B_A<11>

12 29

MEM_B_A<12>
MEM_B_A<13>

12 29 30 73

MEM_B_A<14>

12 29 30 73

12 29 30 73 12 29 30 73 12 29 30 73

73

MEM_B_BA<0>

12 29 30

MEM_B_BA<1>
MEM_B_BA<2>

12
29 30 73

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_ODT<1>

12 29 30 73

MEM_B_ZQ<9>
MEM_B_ZQ<13>

2

240

1%

1/20W

MF

201

1

C3130

2.2UF

20%
10V

X5R-CERM

402

C3170

2.2UF

20%
10V

X5R-CERM

402

0.47UF

1

R3151

240

1%
1/20W
MF
201

2

1

C3131

2

1

C3171

2

20%

4V

201

2.2UF

X5R-CERM

2.2UF

X5R-CERM

1

2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

VDD

K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J7

J2
K8
J3

F3
G3
H3

G1
F1

H8
H9

20%
10V

402

20%
10V

402

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13

A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*
ODT0
ODT1

ZQ0
ZQ1

A1

A8

B1D8F2F8J1J9L1

1

2

1

2

OMIT_TABLE

U3150

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

VSS

1

C3103

0.1UF

10%

6.3V

2

X5R
201

1

C3143

0.1UF 0.1UF

10%

6.3V

2

X5R
201

VDDQ

MT41K1G4

N1

N9

L9

1

C3104

0.1UF

10%

6.3V

2

X5R
201

1

C3144

10%

6.3V

2

X5R
201

VREFDQ

VREFCA

RESET*

DQ0
DQ1
DQ2

DQ3
NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

CK

CK*

NC

VSSQ

B2B8C9D1D9

1

C3105

0.1UF

10%

6.3V

2

X5R
201

1

C3145

0.1UF

10%

6.3V

2

X5R
201

C3158

0.47UF

20%

4V

CERM-X5R-1

201

N2

MEM_RESET_L

B3

MEM_B_DQ<41>

C7

MEM_B_DQ<46>

C2

MEM_B_DQ<44>

C8

MEM_B_DQ<47>

E3

MEM_B_DQ<45>

E8

MEM_B_DQ<43>

D2

MEM_B_DQ<40>

E7

MEM_B_DQ<42>

C3

MEM_B_DQS_P<5>

D3

MEM_B_DQS_N<5>

B7
A7

H1

MEM_B_CS_L<1>

H2

MEM_B_CS_L<0>

G9

MEM_B_CKE<0>

F9

MEM_B_CKE<1>

F7

MEM_B_CLK_P<0>

G7

MEM_B_CLK_N<0>

A3

NC

79

NC

80

NC

81

NC

82

NC

1

C3113

2

1

C3153

2

1

2

0.1UF

10%

6.3V
X5R
201

0.1UF

10%

6.3V
X5R
201

1

C3159

0.47UF

20%
4V

2

CERM-X5R-1
201

27 28 29

12 73

7

7

7

7

7

7

7

12 29 30
73

12 29 30
73

12 29 30
73

12 29 30
73

12 29
30 73

12 29
30 73

R3160

1

C3114

0.1UF

10%

6.3V

2

X5R
201

1

C3154

0.1UF

10%

6.3V

2

X5R
201

MEM_B_A<0>

12 29 30 73

MEM_B_A<1>

12 29 30 73

MEM_B_A<2>

12 29 30 73

MEM_B_A<3>
MEM_B_A<4>

12 73

MEM_B_A<5>

12 73

MEM_B_A<6>

12 73

MEM_B_A<7>

12 73

MEM_B_A<8>

12 73

MEM_B_A<9>

12 73

MEM_B_A<10>

12 73

30 73

MEM_B_A<11>

12 29

12 73

MEM_B_A<12>

12 73

MEM_B_A<13>

12 29 30 73

MEM_B_A<14>

12 29 30 73

73

MEM_B_BA<0>

12 29 30

MEM_B_BA<1>
MEM_B_BA<2>

12
29 30 73

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<10>
MEM_B_ZQ<14>

240

1%

1/20W

MF

201

CERM-X5R-1

2

1

1

2

1

2

C3167

0.47UF

1

R3161

240

1%
1/20W
MF
201

2

C3115

0.1UF

10%

6.3V
X5R
201

C3155

0.1UF

10%

6.3V
X5R
201

1

20%

4V

2

201

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

VDD

K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
N7
J7

J2
K8
J3

F3
G3
H3

G1
F1

H8
H9

1

C3123

0.1UF

10%

6.3V

2

X5R
201

1

C3163

0.1UF

10%

6.3V

2

X5R
201

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13

A14

A15

BA0
BA1
BA2

RAS*
CAS*
WE*
ODT0
ODT1

ZQ0
ZQ1

A1

A8

B1D8F2F8J1J9L1

OMIT_TABLE

U3160

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

VSS

N1

L9

1

C3124

0.1UF

10%

6.3V

2

X5R
201

1

C3164

0.1UF

10%

6.3V

2

X5R
201

VDDQ

N9

1

C3125

0.1UF

10%

6.3V

2

X5R
201

1

C3165

0.1UF

10%

6.3V

2

X5R
201

B2B8C9D1D9

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

C3168

CERM-X5R-1

VREFCA

DQ0
DQ1
DQ2
DQ3

DQS

CK

CK*

NC

1

C3133

0.1UF

10%

6.3V

2

X5R
201

1

C3173

0.1UF

10%

6.3V

2

X5R
201

0.47UF

N2

B3
C7
C2
C8
E3
E8
D2
E7

C3
D3

B7
A7

H1
H2

G9
F9

F7
G7

A3
79
80
81
82

20%

201

MEM_RESET_L

MEM_B_DQ<52>
MEM_B_DQ<50>
MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<48>
MEM_B_DQ<54>
MEM_B_DQ<49>
MEM_B_DQ<55>

MEM_B_DQS_P<6>
MEM_B_DQS_N<6>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_CKE<0>
MEM_B_CKE<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

NC
NC
NC
NC
NC

1

1

C3169

4V

0.47UF

2

2

1

C3134

0.1UF

10%

6.3V

2

X5R
201

1

C3174

0.1UF 0.1UF

10%

6.3V

2

X5R
201

20%
4V
CERM-X5R-1
201

R3170

12 29 30 73

12 29 30 73

27 28 29

12 29 30 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73
12 73

12 29

7

30 73

7

12 73

7

12 73

30 73
12 29

12 73

12 73

12 29 30 73

12 29 30 73

73

12 29 30
12 29 30
73

12 29 30
73

12

29 30 73
12 29 30

73
12 29 30

73

12 29
30 73

12 29
30 73

12 29 30 73 12 29 30 73

1/20W

1

C3135

0.1UF

10%

6.3V

2

X5R
201

1

C3175

10%

6.3V

2

X5R
201

6 3

C3177

0.47UF

CERM-X5R-1

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_A<13>
MEM_B_A<14>

MEM_B_BA<0>
MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<11>
MEM_B_ZQ<15>

2

240

1%
MF

201

1

20%

4V

201

1

R3171

240

1%
1/20W
MF
201

2

1

2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

VDD

K3

A0

L7

A1

L3

A2

K2

A3

L8

A4

L2

A5

M8

A6

M2

A7

N8

A8

M3

A9

H7

A10/AP

M7

A11

K7

A12/BC*

N3

A13

N7

A14

J7

A15

J2

BA0

K8

BA1

J3

BA2

F3

RAS*

G3

CAS*

H3

WE*

G1

ODT0

F1

ODT1

H8

ZQ0

H9

ZQ1

A1

A8

B1D8F2F8J1J9L1

SYNC_MASTER=J5_MLB

PAGE TITLE

OMIT_TABLE

U3170

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

VSS

VDDQ

MT41K1G4

N1

N9

L9

B2B8C9D1D9

VREFDQ

RESET*

NF_DQ4
NF_DQ5
NF_DQ6
NF_DQ7

DQS*

DM/TDQS

NF_TDQS*

CS1*
CS0*

CKE0
CKE1

VSSQ

C3178

0.47UF

CERM-X5R-1

VREFCA

N2

MEM_RESET_L

B3

MEM_B_DQ<56>

DQ0

C7

MEM_B_DQ<62>

DQ1

C2

MEM_B_DQ<61>

DQ2

C8

MEM_B_DQ<59>

DQ3

E3

MEM_B_DQ<60>

E8

MEM_B_DQ<58>

D2

MEM_B_DQ<57>

E7

MEM_B_DQ<63>

C3

MEM_B_DQS_P<7>

DQS

D3

MEM_B_DQS_N<7>

B7
A7

NCNCNCNC

H1

MEM_B_CS_L<1>

H2

MEM_B_CS_L<0>

G9

MEM_B_CKE<0>

F9

MEM_B_CKE<1>

F7

MEM_B_CLK_P<0>

CK

G7

MEM_B_CLK_N<0>

CK*

A3

NC

79

NC

80

NC

NC

81

NC

82

NC

SYNC_DATE=07/14/2011

DDR3 SDRAM Bank B (Rank 0)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

20%

4V

2

201

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

31 OF 132

SHEET

29 OF 80

124578

1

C3179

0.47UF

20%
4V

2

CERM-X5R-1
201

27 28 29

7

12 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73

7

12 73

7

12 73

12 73

12 73

12 29 30 73

12 29 30 73

12 29 30 73

12 29 30 73

12 29 30
73

12 29 30 73

SIZE

D

B

A

8 7 6 5 4 3

12

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

=PP0V75_S0_MEM_VTT_A

MEM_A_A<3>

12 28 73

IN

12 28 73

MEM_A_CKE<1>

IN

MEM_A_BA<2>

12 28 73

IN

MEM_A_A<14>

12 28 73

IN

MEM_A_A<2>

12 28 73

IN

MEM_A_A<12>

12 28 73

IN

MEM_A_ODT<0>

12 28 73

IN

12 28 73

MEM_A_BA<0>

D

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

12 28 73

IN

MEM_A_A<1>
MEM_A_A<7>

MEM_A_A<8>

MEM_A_CS_L<1>
MEM_A_A<11>
MEM_A_BA<1>
MEM_A_CKE<0>
MEM_A_A<0>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_WE_L
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<15>

MEM_A_A<13>
MEM_A_CAS_L
MEM_A_CS_L<0>
MEM_A_RAS_L
MEM_A_ODT<1>
MEM_A_A<6>

RP3305
RP3301
RP3302
RP3306
RP3303
RP3302
RP3301
RP3305

RP3303
RP3307
RP3306

RP3305
RP3306
RP3302
RP3304
RP3303
RP3304
RP3307
RP3302
RP3303
RP3307
RP3305

RP3307
RP3304
RP3304
RP3301
RP3301
RP3306

C

8

36
36
36
36
36
36
36
36

36
36
36

36
36
36
36
36
36
36
36
36
36
36

36
36
36
36
36
36

1 8
4 5
2 7
2 7
1 8
1 8
2 7
2 7

2 7
3 6
1 8

3 6
4 5
3 6
3 6
4 5
1 8
2 7
4 5
3 6
1 8
4 5

4 5
2 7
4 5
3 6
1 8
3 6

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1

C3300

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3302

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3304

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3306

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3308

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3310

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3303

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3305

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3307

0.47UF

20%
4V

2

CERM-X5R-1
201

D

C

=PP0V75_S0_MEM_VTT_B

12 29 73

MEM_B_WE_L

IN

12 29 73

MEM_B_A<13>

IN

12 29 73

MEM_B_CKE<1>

IN

12 29 73

MEM_B_A<12>

IN

MEM_B_ODT<1>

12 29 73

IN

MEM_B_A<0>

12 29 73

MEM Clock Termination

Place RC end termination after last DRAM
Place Source Cterm at neckdown at first DRAM

R3350

30

CERM

CERM

1 2

5%

1/20W

1

MF

2

1

2

201

R3351

30

1 2

5%

1/20W

MF

201

R3360

30

1 2

5%

1/20W

MF

201

R3361

30

1 2

5%

1/20W

MF

201

5%

25V
201

5%

25V
201

MEM_A_CLK0_TERM_R

MEM_B_CLK0_TERM_R

MEM_A_CLK_N<0>

12 28 73

IN

C3350

PLACE_NEAR=U2900.F7:3.2mm

MEM_A_CLK_P<0>

12 28 73

B

IN

MEM_B_CLK_N<0>

12 29 73

IN

PLACE_NEAR=U3170.F7:3.2mm

MEM_B_CLK_P<0>

12 29 73

IN

3.3PF

C3360

3.3PF

C3351

0.1UF

1 2

10%

6.3V
X5R
201

C3361

0.1UF

1 2

10%

6.3V
X5R
201

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

12 29 73

IN

MEM_B_CS_L<1>
MEM_B_BA<0>
MEM_B_A<6>
MEM_B_ODT<0>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_BA<1>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<3>
MEM_B_A<10>
MEM_B_A<7>
MEM_B_A<1>
MEM_B_A<14>
MEM_B_A<11>
MEM_B_A<2>

MEM_B_BA<2>
MEM_B_CS_L<0>

MEM_B_RAS_L

MEM_B_CAS_L
MEM_B_CKE<0>
MEM_B_A<15>

RP3322
RP3325

RP3328
RP3325

RP3328
RP3325

RP3320
RP3326
RP3330
RP3320
RP3330
RP3330
RP3324
RP3326
RP3324
RP3326
RP3322
RP3326
RP3330
RP3324
RP3324
RP3325

RP3320
RP3320
RP3322

RP3328
RP3328
RP3322

A

6 3

8

36
36

36
36

36
36

36
36
36
36
36
36
36
36
36

36

36
36
36
36

36
36
36

36
36

2 7
1 8

1 8
2 7

2 7
3 6

2 7
4 5
2 7
3 6
1 8
3 6
4 5
2 7
1 8
3 6
3 6
1 8
4 5
3 6
2 7
4 5

4 5
1 8
1 8

4 5
3 6
4 5

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

5%

1/32W

4X0201

5%361/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

1/32W

5%

4X0201

5%

1/32W

4X0201

1/32W

5%

4X0201

5%361/32W

4X0201

SYNC_MASTER=MASTER

PAGE TITLE

1

C3320

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3322

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3324

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3326

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3328

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3330

0.47UF

20%
4V

2

CERM-X5R-1
201

DDR3 Termination

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

C3323

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3325

0.47UF

20%
4V

2

CERM-X5R-1
201

1

C3327

0.47UF

20%
4V

2

CERM-X5R-1
201

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

33 OF 132

SHEET

30 OF 80

124578

SIZE

B

A

D

8 7 6 5 4 3

12

NOTE: Must not enable more than two SO-DIMM margining

=PP3V3_S3_VREFMRGN

8

OMIT

R3418

SHORT

1 2

D

R3419

1 2

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

- =PPDDR_S3_MEMVREF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

C

B

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

DDRVREF_DAC - Stuffs Apple margining circuit.
VREFDQ:LDO - LDO outputs sent to DQ inputs.
VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO - LDO outputs sent to CA inputs.
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

=PPDDR_S3_MEMVREF

8

31

VREFDQ:M1_M3

SSM6N15FEAPE

27 31

PPCPU_MEM_VREFDQ_A

10 72

MEMRESET_ISOL_LS5V_L

=PPDDR_S3_MEMVREF

8

31

2

1

VREFDQ:M1_M3

SSM6N15FEAPE

27 31

PPCPU_MEM_VREFDQ_B

10 72

MEMRESET_ISOL_LS5V_L

5

4

CRITICAL

Q3420

S G

CRITICAL

Q3420

S G

NONE
NONE
NONE

402

OMIT

SHORT

NONE
NONE
NONE

402

SOT563

SOT563

D

6

D

3

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

=I2C_VREFDACS_SCL

42

IN

=I2C_VREFDACS_SDA

42

BI

Addr=0x98(WR)/0x99(RD)

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

Addr=0x30(WR)/0x31(RD)

=I2C_PCA9557D_SCL

42

IN

=I2C_PCA9557D_SDA

42

BI

PCA9557D_RESET_L

25

IN

RST* on ’platform reset’ so that system
watchdog will disable margining.

NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.

PLACE_NEAR=Q3420.6:2mm

VREFDQ:M1_M3

1

C3420

0.1UF

10%
16V

2

X7R-CERM
0402

PLACE_NEAR=R3421.2:1mm

PLACE_NEAR=Q3420.3:2mm

VREFDQ:M1_M3

1

C3440

0.1UF

10%

16V

2

X7R-CERM
0402

PLACE_NEAR=R3441.2:1mm

DDRVREF_DAC

C3400

2.2UF

402-LF

DDRVREF_DAC

6.3V
CERM

DDRVREF_DAC

1

1

C3401

0.1UF

20%

C3402

0.1UF

VREFDQ:M1_M3

1

R3421

1K

1%
1/16W
MF-LF
402

2

20%
10V

2

2

CERM
402

6

7

9

10

1

20%
10V

2

CERM

402

3
4

5

1
2

PLACE_NEAR=Q3420.6:1mm

PP0V75_S3_MEM_VREFDQ_A

VREFDQ:M1_M3

1

R3422

1K

1%
1/16W
MF-LF
402

2

NOTE: CPU DAC output step sizes:
DDR3 (1.5V) 7.70mV per step
DDR3L (1.35V) 6.99mV per step

PLACE_NEAR=Q3420.3:1mm

VREFDQ:M1_M3

1

R3441

1K

1%
1/16W
MF-LF
402

2

PP0V75_S3_MEM_VREFDQ_B

VREFDQ:M1_M3

1

R3442

1K

1%
1/16W
MF-LF
402

2

SCL

SDA

A0

A1

A0
A1
A2

SCL
SDA

THRM

PAD

17

8

VDD

MSOP

DAC5574

GND

3

16

VCC

U3401

PCA9557

QFN

GND

8

CRITICAL
DDRVREF_DAC

U3400

VOUTA

VOUTB

VOUTC

VOUTD

CRITICAL
DDRVREF_DAC

(OD)

P0
P1
P2
P3
P4
P5
P6
P7

RESET*

28 31 72

29 31 72

1

2

4

5

6

7
9

10
11

12

13
14

VREFMRGN_SODIMMA_DQ

VREFMRGN_SODIMMB_DQ

VREFMRGN_SODIMMS_CA

VREFMRGN_MEMVREG_FBVREF

NOTE: MEMVREG and FRAMEBUF share
a DAC output, cannot enable
both at the same time!

NC

VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN

NC

15

DDRVREF_DAC

R3416

1/16W
MF-LF

1

0

5%

402

2

VREFMRGN_MEMVREG_FBVREF_R

DDRVREF_DAC

1

R3413

100K

5%
1/16W
MF-LF
402

2

DDRVREF_DAC

1

R3415

100K

5%
1/16W
MF-LF
402

2

DDRVREF_DAC

1

R3401

100K

5%
1/16W
MF-LF
402

2

DDRVREF_DAC

1

R3402

100K

5%
1/16W
MF-LF
402

2

DDRVREF_DAC

1

R3407

100K

5%
1/16W
MF-LF
402

2

DDRVREF_DAC

1

R3408

100K

5%
1/16W
MF-LF
402

2

A2

A3

DDRVREF_DAC

C3403

0.1UF

20%
10V

CERM

402

DDRVREF_DAC

C3404

0.1UF

20%
10V

CERM

402

DDRVREF_DAC

C3405

0.1UF

CRITICAL

VREFMRGN_FRAMEBUF_BUF

NC

DDRVREF_DAC

B1

U3404

MAX4253

V+

UCSP

A1

A4

V-

B4

VREFMRGN_FRAMEBUF_BUF_R

NC

CERM

1

2

B1

A2

V+

A3

V-

B4

NC

B1

C2

V+

C3

V-

B4

NC

1

2

B1

A2

V+

A3

V-

B4

NC

B1

C2

V+

C3

V-

B4

NC

1

20%
10V

2

402

C2

C3

DDRVREF_DAC

1

R3417

0

5%
1/16W
MF-LF
402

2

B1

V+

V-

B4

buffers at once or VRef source may be overloaded.

VREFDQ:LDO_DAC

R3403

200

PLACE_NEAR=R3404.2:2.54mm

1 2

1%
1/16W
MF-LF

402

VREFDQ:LDO_DAC

R3404

133

1 2

1%

PLACE_NEAR=R3403.2:1mm

1/16W
MF-LF

402

VREFDQ:LDO_DAC

R3405

200

PLACE_NEAR=R3406.2:2.54mm

1 2

1%
1/16W
MF-LF

402

VREFDQ:LDO_DAC

R3406

133

1 2

1%

PLACE_NEAR=R3405.2:1mm

1/16W
MF-LF

402

VREFCA:LDO_DAC

R3409

200

PLACE_NEAR=R3410.2:2.54mm

1 2

1%
1/16W
MF-LF

402

VREFCA:LDO_DAC

R3410

133

1 2

1%

PLACE_NEAR=R3409.2:1mm

1/16W
MF-LF

402

VREFCA:LDO_DAC

R3411

200

PLACE_NEAR=R3412.2:2.54mm

1 2

1%
1/16W
MF-LF

402

VREFCA:LDO_DAC

R3412

133

1 2

1%

PLACE_NEAR=R3411.2:1mm

1/16W
MF-LF

402

DDRREG_FB

Required zero ohm resistors when no VREF margining circuit stuffed

DESCRIPTION

DESCRIPTION

CRITICAL

DDRVREF_DAC

U3402

MAX4253

UCSP

A1

A4

CRITICAL

DDRVREF_DAC

U3402

MAX4253

UCSP

C1

C4

CRITICAL

DDRVREF_DAC

U3403

MAX4253

UCSP

A1

A4

CRITICAL

DDRVREF_DAC

U3403

MAX4253

UCSP

C1

C4

CRITICAL
DDRVREF_DAC

U3404

MAX4253

UCSP

C1

VREFMRGN_MEMVREG_BUF

C4

PLACE_NEAR=R7320.2:1mm

PART NUMBER

PART NUMBER

=PPVTT_S3_DDR_BUF

8

60

10mA max load

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

QTY

116S0004

116S0004

2

2

QTY

114S0218

114S0171

4

2

DDRVREF_DAC

R3414

33.2K

1 2

1%
1/16W
MF-LF

402

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,1K,1%,0402,SM,LF

RES,MTL FILM,332,1%,0402,SM,LF

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V

60

OUT

REFERENCE DES

R3403,R3405

R3409,R3411

REFERENCE DES

R3421,R3422,R3441,R3442

R3404,R3406

CRITICAL

CRITICAL

28 31 72

29 31 72

28 72

29 72

D

C

B

BOM OPTION

VREFDQ:LDO

VREFCA:LDO

BOM OPTION

VREFDQ:M1_DAC

VREFDQ:M1_DAC

A

DAC Channel:
PCA9557D Pin:
Nominal value
Margined target:
DAC range:
VRef current:
DAC step size:

MEM A VREF DQ MEM B VREF DQ

A
1

B
2

0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74)
+3.4mA - -3.4mA (- = sourced)

7.69mV / step @ output

MEM A VREF CA

C
3

MEM B VREF CA

C
4

MEM VREG

D
5

GPU Frame Buffer (1.8V, 70% VRef)

D
6

1.267V (DAC: 0x8B)

1.000V - 2.000V (+/- 500mV)

0.000V - 3.000V (0x00 - 0x74)
+61uA - -61uA (- = sourced)

8.59mV / step @ output

1.056V - 1.442V (+/- 180mV)

0.000V - 3.300V (0x00 - 0xFF)
+6.0mA - -5.0mA (- = sourced)

1.51mV / step @ output

6 3

SYNC_MASTER=J5_MLB

PAGE TITLE

DDR3/FRAMEBUF VREF MARGINING

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

34 OF 132

SHEET

31 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

D

D

518S0767

CRITICAL

J3502

819Q-3506-K281

F-RT-SM

8

6
5

C

4
3
2
1

7

74

74

ALS

=I2C_ALS_SDA
=I2C_ALS_SCL
PP5V_S3_ALSCAMERA_F

7

USB_CAMERA_CONN_N

7

7

USB_CAMERA_CONN_P

CAMERA

PLACE_NEAR=J3502.4:2.54MM

42

BI

42

IN

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

275 mA peak
206 mA nominal max

CRITICAL

L3507

90-OHM

DLP0NS

SYM_VER-1

21

4 3

PLACE_NEAR=J3502.2:2.54MM

USB_CAMERA_N

USB_CAMERA_P

19 74

BI

19 74

BI

L3508

FERR-120-OHM-1.5A

1

C3552

0.1uF

20%
10V

2

CERM
402

0402-LF

12

=PP5V_S3_ALSCAMERA

8

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

ALS/CAMERA CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

35 OF 132

SHEET

32 OF 80

124578

8 7 6 5 4 3

12

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

AB9

PERP_0

AA10

PERN_0

AA12

PERP_1

AB13

PERN_1

AB15
AA16

AA18
AB19

R6

J2

AD23
AC24

W18
W16

Y7

R4
P5

AD3

W4

V1
AB3
AA6

R2

N4
AB5

E14
D13

E16
D15

E18
D17

E20
D19

A6

B5

U6

E6

D5

E8

D7

E10

D9

E12
D11

A4

B3

T5

G24
E24

G22
E22

K1

G4

L24
J24

L22
J22

N2

J6

A16
B17

A18
B19

F3

F1

H1

G2

M3 L2

H3 L4

RECEIVE

PERP_2
PERN_2

PERP_3
PERN_3

PERST_N

PWR_ON_POC_RSTN

MONDC0
MONDC1

MONOBS_P
MONOBS_N

THERMDA

EE_DI
EE_DO
EE_CS_N

EEPROM

EE_CLK

TDI
TMS
TCK
TDO
TEST_EN
TEST_PWR_GOOD

DPSNK0_3_P
DPSNK0_3_N

DPSNK0_2_P
DPSNK0_2_N

DPSNK0_1_P
DPSNK0_1_N

DPSNK0_0_P
DPSNK0_0_N

DPSNK0_AUX_P
DPSNK0_AUX_N

DPSNK0_HPD

DPSNK1_3_P
DPSNK1_3_N

DPSNK1_2_P
DPSNK1_2_N

DPSNK1_1_P
DPSNK1_1_N

DPSNK1_0_P
DPSNK1_0_N

DPSNK1_AUX_P
DPSNK1_AUX_N

DPSNK1_HPD

PA_CIO0_TX_P/DP_SRC_0_P
PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_RX_P
PA_CIO0_RX_N

PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE

PA_CIO1_TX_P/DP_SRC_2_P
PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_RX_P
PA_CIO1_RX_N

PA_LSTX/CIO_1_LSEO
PA_LSRX/CIO_1_LSOE

PA_DPSRC_1_P
PA_DPSRC_1_N

PA_DPSRC_3_P
PA_DPSRC_3_N

PA_AUX_P
PA_AUX_N

PA_DPSRC_HPD

GPIO_0/PA_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2

10%
16V

0201

1/20W

201

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1

2

1

0

5%
MF

2

9

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

NOSTUFF

9

R3630

OUT

R3631

10% 16V

10% 16V

10% 16V

10% 16V

10% 16V

10% 16V

10% 16V

10% 16V

OMIT

R3615

NONE
NONE
NONE
0201

1

R3629

0

5%
1/20W
MF
201

2

OUT

100K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

X5R-CERM0201

X5R-CERM0201

X5R-CERM0201

X5R-CERM0201

X5R-CERM0201

X5R-CERM0201

X5R-CERM0201

X5R-CERM0201

PCIE_TBT_R2D_P<0>
PCIE_TBT_R2D_N<0>

7

75

PCIE_TBT_R2D_P<1>
PCIE_TBT_R2D_N<1>

7

75

PCIE_TBT_R2D_P<2>
PCIE_TBT_R2D_N<2>

7

75

PCIE_TBT_R2D_P<3>
PCIE_TBT_R2D_N<3>

7

75

TBT_PCIE_RESET_L

35

IN

TBT_PWR_ON_POC_RST_L

TP_TBT_MONDC0

7

TP_TBT_MONDC1

1

2

7

DEBUG: For monitoring current/voltage

TBT_MONOBSP
TBT_MONOBSN

DEBUG: For monitoring clock

TP_TBT_THERM_DP

45

Use AA8 GND ball for THERM_DN

TBT_SPI_MOSI

76

76

TBT_SPI_MISO
TBT_SPI_CS_L

76

76

TBT_SPI_CLK

JTAG_TBT_TDI

20

IN

JTAG_TBT_TMS

20

IN

JTAG_TBT_TCK

20

IN

JTAG_TBT_TDO

20

OUT

TBT_TEST_EN
TBT_TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3>

33 79

DP_TBTSNK0_ML_N<3>

33 79

DP_TBTSNK0_ML_P<2>

33 79

DP_TBTSNK0_ML_N<2>

33 79

DP_TBTSNK0_ML_P<1>

33 79

DP_TBTSNK0_ML_N<1>

33 79

DP_TBTSNK0_ML_P<0>

33 79

DP_TBTSNK0_ML_N<0>

33 79

DP_TBTSNK0_AUXCH_P

33 79

DP_TBTSNK0_AUXCH_N

33 79

DP_TBTSNK0_HPD

1

2

1

2

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

DP_TBTSNK1_ML_P<3>

33 79

DP_TBTSNK1_ML_N<3>

33 79

DP_TBTSNK1_ML_P<2>

33 79

DP_TBTSNK1_ML_N<2>

33 79

DP_TBTSNK1_ML_P<1>

33 79

DP_TBTSNK1_ML_N<1>

33 79

DP_TBTSNK1_ML_P<0>

33 79

DP_TBTSNK1_ML_N<0>

33 79

DP_TBTSNK1_AUXCH_P

33 79

DP_TBTSNK1_AUXCH_N

33 79

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

7

69 76

OUT

TBT_A_R2D_C_N<0>

7

69 76

OUT

TBT_A_D2R_P<0>

7

69 76

IN

TBT_A_D2R_N<0>

7

69 76

IN

TBT_A_CONFIG1_BUF

69

OUT

TBT_A_CONFIG2_RC

69

IN

TBT_A_R2D_C_P<1>

7

69 76

OUT

TBT_A_R2D_C_N<1>

7

69 76

OUT

TBT_A_D2R_P<1>

7

69 76

IN

TBT_A_D2R_N<1>

7

69 76

IN

TBT_A_LSTX

69

OUT

TBT_A_LSRX

69

IN

DP_TBTPA_ML_C_P<1>

69 76

OUT

DP_TBTPA_ML_C_N<1>

69 76

OUT

DP_TBTPA_ML_C_P<3>

69 76

OUT

DP_TBTPA_ML_C_N<3>

69 76

OUT

DP_TBTPA_AUXCH_C_P

69 76

BI

DP_TBTPA_AUXCH_C_N

69 76

BI

DP_TBTPA_HPD

69

IN

TBT_A_HV_EN

33 35

OUT

TBT_A_CIO_SEL

69

OUT

TBT_A_DP_PWRDN

33 69

OUT

PCIE_TBT_R2D_C_P<0>

7 9

75

IN

PCIE_TBT_R2D_C_N<0>

7 9

75

IN

PCIE_TBT_R2D_C_P<1>

7 9

75

IN

PCIE_TBT_R2D_C_N<1>

7 9

75

IN

PCIE_TBT_R2D_C_P<2>

7 9

75

D

=PP3V3_S4_TBT

8

33 34 35

1

R3610

47K

5%

1/20W

MF

201

2

35

IN

=PP3V3_TBTLC_RTR

1

201

1

R3691

3.3K

5%

5%
1/20W

MF

MF
201

2

2

(TBT_SPI_MOSI)

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

R3690

3.3K

1/20W

TBTROM_WP_L

C

TBTROM_HOLD_L

C3690

1UF

6.3V
CERM

10%

402

8

1

2

33 34 35

CRITICAL
OMIT_TABLE

8

VCC

5

D

U3690

M95256-RMC6XG

6

MLP

C

1

S*

3

W*

7

HOLD*

THM

VSS

PAD

9

4

75

75

75

Q

IN

PCIE_TBT_R2D_C_N<2>

7 9

IN

PCIE_TBT_R2D_C_P<3>

7 9

IN

PCIE_TBT_R2D_C_N<3>

7 9

IN

2

(TBT_SPI_MISO)

R3692

3.3K

1/20W

201

1

1

5%
MF

2

2

NO STUFF

R3693

3.3K

5%
1/20W
MF
201

C3600
C3601

C3602
C3603

C3604
C3605

C3606
C3607

C3610

0.1UF

X5R-CERM

R3625

DP_TBTSNK0_ML_C_P<0>

9

79

IN

DP_TBTSNK0_ML_C_N<0>

9

79

IN

DP_TBTSNK0_ML_C_P<1>

9

79

IN

DP_TBTSNK0_ML_C_N<1>

9

79

IN

B

A

DP_TBTSNK0_ML_C_P<2>

9

79

IN

DP_TBTSNK0_ML_C_N<2>

9

79

IN

DP_TBTSNK0_ML_C_P<3>

9

79

IN

DP_TBTSNK0_ML_C_N<3>

9

79

IN

DP_TBTSNK0_AUXCH_C_P

9

79

BI

DP_TBTSNK0_AUXCH_C_N

9

79

BI

DP_TBTSNK1_ML_C_P<0>

9

79

IN

DP_TBTSNK1_ML_C_N<0>

9

79

IN

DP_TBTSNK1_ML_C_P<1>

9

79

IN

DP_TBTSNK1_ML_C_N<1>

9

79

IN

DP_TBTSNK1_ML_C_P<2>

9

79

IN

DP_TBTSNK1_ML_C_N<2>

9

79

IN

DP_TBTSNK1_ML_C_P<3>

9

79

IN

DP_TBTSNK1_ML_C_N<3>

9

79

IN

DP_TBTSNK1_AUXCH_C_P

9

79

BI

DP_TBTSNK1_AUXCH_C_N

9

79

BI

SNK0 AC Coupling

C3620
C3621

C3622
C3623

C3624
C3625

C3626
C3627

C3628
C3629

SNK1 AC Coupling

C3630
C3631

C3632
C3633

C3634
C3635

C3636
C3637

C3638
C3639

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

DP_TBTSNK0_ML_P<0>

10% 16V
X5R-CERM0201

DP_TBTSNK0_ML_N<0>

10% 16V
X5R-CERM0201

DP_TBTSNK0_ML_P<1>

10% 16V
X5R-CERM0201

DP_TBTSNK0_ML_N<1>

10% 16V
X5R-CERM0201

DP_TBTSNK0_ML_P<2>

10% 16V
X5R-CERM0201

DP_TBTSNK0_ML_N<2>

10% 16V
X5R-CERM0201

DP_TBTSNK0_ML_P<3>

10% 16V
X5R-CERM0201

DP_TBTSNK0_ML_N<3>

10% 16V
X5R-CERM0201

DP_TBTSNK0_AUXCH_P

10% 16V
X5R-CERM0201

DP_TBTSNK0_AUXCH_N

10% 16V
X5R-CERM0201

DP_TBTSNK1_ML_P<0>

10% 16V
X5R-CERM0201

DP_TBTSNK1_ML_N<0>

10% 16V
X5R-CERM0201

DP_TBTSNK1_ML_P<1>

10% 16V
X5R-CERM0201

DP_TBTSNK1_ML_N<1>

10% 16V
X5R-CERM0201

DP_TBTSNK1_ML_P<2>

10% 16V
X5R-CERM0201

DP_TBTSNK1_ML_N<2>

10% 16V
X5R-CERM0201

DP_TBTSNK1_ML_P<3>

10% 16V
X5R-CERM0201

DP_TBTSNK1_ML_N<3>

10% 16V
X5R-CERM0201

DP_TBTSNK1_AUXCH_P

10% 16V
X5R-CERM0201

DP_TBTSNK1_AUXCH_N

10% 16V
X5R-CERM0201

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

CRITICAL

OMIT_TABLE

U3600

CACTUSRIDGE4C

FCBGA

(SYM 1 OF 2)

JTAG/TEST PORT

SINK PORT 0SINK PORT 1

PORT0PORT1

PETP_0
PETN_0

PETP_1
PETN_1

TRANSMIT

PETP_2
PETN_2

PCIE GEN2

MISC

PCIE_CLKREQ_OD_N

CLOCKS

DISPLAYPORT

(FORCE_PWR)

GPIO_4/WAKE_N_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_6/CIO_SDA_OD
GPIO_7/CIO_SCL_OD

GPIO_8/EN_CIO_PWR_OD*

GPIO_9/OK2GO2SX_OD*

PB_CIO2_TX_P/DP_SRC_0_P
PB_CIO2_TX_N/DP_SRC_0_N

PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE

PB_CIO3_TX_P/DP_SRC_2_P
PB_CIO3_TX_N/DP_SRC_2_N

PORT3 PORT2

PB_LSTX/CIO_3_LSEO
PB_LSRX/CIO_3_LSOE

PORTS

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PETP_3
PETN_3

RSENSE

RBIAS

PCIE_RST_0_N
PCIE_RST_1_N
PCIE_RST_2_N
PCIE_RST_3_N

PCIE RESET

EN_LC_PWR

REFCLK_100_IN_P
REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMU_CLK_OUT

TMU_CLK_IN

DPSRC_3_P
DPSRC_3_N

DPSRC_2_P
DPSRC_2_N

DPSRC_1_P
DPSRC_1_N

DPSRC_0_P
DPSRC_0_N

SOURCE PORT 0

DPSRC_AUX_P
DPSRC_AUX_N

DPSRC_HPD_OD

GPIO_2/GO2SX

GPIO_3

GPIO_14
GPIO_15

PB_CIO2_RX_P
PB_CIO2_RX_N

PB_CIO3_RX_P
PB_CIO3_RX_N

PB_DPSRC_1_P
PB_DPSRC_1_N

PB_DPSRC_3_P
PB_DPSRC_3_N

PB_AUX_P
PB_AUX_N

PB_DPSRC_HPD

AD5

PCIE_TBT_D2R_C_P<0>

75

AD7

PCIE_TBT_D2R_C_N<0>

75

AD9

PCIE_TBT_D2R_C_P<1>

7

75

AD11

PCIE_TBT_D2R_C_N<1>

AD13

PCIE_TBT_D2R_C_P<2>

AD15

PCIE_TBT_D2R_C_N<2>

AD17

PCIE_TBT_D2R_C_P<3>

AD19

PCIE_TBT_D2R_C_N<3>

U20

TBT_RSENSE

W20

TBT_RBIAS

U4

NC

NC

Not used in host mode.

N6

TP_TBT_PCIE_RESET0_L

T1

TP_TBT_PCIE_RESET1_L

Y5

TP_TBT_PCIE_RESET2_L

U2

TP_TBT_PCIE_RESET3_L

W6

=TBT_CLKREQ_L

K5

TBT_EN_LC_PWR

PCIE_CLK100M_TBT_P

AB21
AD21

PCIE_CLK100M_TBT_N

AA24

74

SYSCLK_CLK25M_TBT_R

AB23

TP_TBT_XTAL25OUT

AA4

TBT_TMU_CLK_OUT

Y3

TBT_TMU_CLK_IN

A14

TP_DP_TBTSRC_ML_CP<3>

B15

TP_DP_TBTSRC_ML_CN<3>

A12

TP_DP_TBTSRC_ML_CP<2>

B13

TP_DP_TBTSRC_ML_CN<2>

A10

TP_DP_TBTSRC_ML_CP<1>

B11

TP_DP_TBTSRC_ML_CN<1>

A8

TP_DP_TBTSRC_ML_CP<0>

B9

TP_DP_TBTSRC_ML_CN<0>

C2

TP_DP_TBTSRC_AUXCH_CP

D3

TP_DP_TBTSRC_AUXCH_CN

V3

DP_TBTSRC_HPD

Y1

TBT_GO2SX_BIDIR

W2

TBT_PWR_EN

J4

=TBT_WAKE_L

AA2

TBT_CIO_PLUG_EVENT

AB1

=I2C_TBTRTR_SDA

AC2

=I2C_TBTRTR_SCL

P3

(TBT_EN_CIO_PWR_L)

M5

TBT_GPIO_9

T3

TBT_GPIO_14

V5

TBT_DDC_XBAR_EN_L

R24

TBT_B_R2D_C_P<0>

N24

TBT_B_R2D_C_N<0>

R22

TBT_B_D2R_P<0>

N22

TBT_B_D2R_N<0>

P1

TBT_B_CONFIG1_BUF

H5

TBT_B_CONFIG2_RC

W24

TBT_B_R2D_C_P<1>

U24

TBT_B_R2D_C_N<1>

W22

TBT_B_D2R_P<1>

U22

TBT_B_D2R_N<1>

L6

TBT_B_LSTX

G6

TBT_B_LSRX

A20

DP_TBTPB_ML_C_P<1>

B21

DP_TBTPB_ML_C_N<1>

A22

DP_TBTPB_ML_C_P<3>

B23

DP_TBTPB_ML_C_N<3>

D1

DP_TBTPB_AUXCH_C_P

E2

DP_TBTPB_AUXCH_C_N

K3

DP_TBTPB_HPD

M1

TBT_B_HV_EN
TBT_B_CIO_SEL
TBT_B_DP_PWRDN

6 3

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

1

2

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

33

33

C3640

0.1UF

C3641

0.1UF

C3642

0.1UF

C3643

0.1UF

C3644

0.1UF

C3645

0.1UF

C3646

0.1UF

C3647

0.1UF

R3655

1K

1%
1/20W
MF
201

35

OUT

7

17 75

IN

7

17 75

IN

20 33

BI

25

IN

40

OUT

20

OUT

42

BI

42

IN

WF: Verify logic level!

33 68

OUT

7

70 76

OUT

7

70 76

OUT

7

70 76

IN

7

70 76

IN

70

OUT

70

IN

7

70 76

OUT

7

70 76

OUT

7

70 76

IN

7

70 76

IN

70

OUT

70

IN

70 76

OUT

70 76

OUT

70 76

OUT

70 76

OUT

70 76

BI

70 76

BI

70

IN

33 35

OUT

70

OUT

33 70

OUT

1 2

PCIE_TBT_D2R_P<0>

X5R-CERM0201

10% 16V

1 2

PCIE_TBT_D2R_N<0>

10% 16V

X5R-CERM

1 2

PCIE_TBT_D2R_P<1>

X5R-CERM0201

10% 16V

1 2

PCIE_TBT_D2R_N<1>

X5R-CERM0201

10% 16V

1 2

PCIE_TBT_D2R_P<2>

X5R-CERM0201

10% 16V

1 2

PCIE_TBT_D2R_N<2>

X5R-CERM0201

10% 16V

1 2

PCIE_TBT_D2R_P<3>

X5R-CERM0201

10% 16V

1 2

PCIE_TBT_D2R_N<3>

X5R-CERM0201

10% 16V

35

OUT

NO STUFF

1

2

R3697

100K

5%
1/20W
MF
201

R3632

100K

1/20W

R3699

5%
MF

201

TBT_PWR_REQ_L

TBT_EN_CIO_PWR_L

MAKE_BASE=TRUE

0201

=PP3V3_TBTLC_RTR

1

R3698

10K

5%
1/20W
MF
201

2

1

10K

5%

1/20W

MF

201

2

1

2

OUT

7 9

75

OUT

7 9

OUT

7 9

OUT

7 9

OUT

7 9

OUT

7 9

OUT

7 9

OUT

7 9

OUT

R3695

806

1 2

1%

Divides 3.3V to 1.8V

1/20W

MF

201

1

R3696

1K

5%
1/20W
MF
201

2

19

35

SYNC_MASTER=J5_MLB_KEPLER

PAGE TITLE

NOTE: The following pins require testpoints:

75

0 - GPIO_13
1 - GPIO_1
2 - GPIO_2

75

3 - GPIO_3
4 - GPIO_5

75

5 - PCIE_RST_1_N
6 - PCIE_RST_2_N

75

7 - PCIE_RST_3_N

75

75

75

8

33 34 35

SYSCLK_CLK25M_TBT

=PP3V3_TBTLC_RTR

8

33 34 35

TBT_DDC_XBAR_EN_L

33 68

TBT_GO2SX_BIDIR

20 33

R3681 for CYA,
allows separation
of GPIO_2/GPIO_9
if necessary.
Stuff one of R3861/2.

TBT_GPIO_9

33

TBT_GPIO_14

33

=PP3V3_S4_TBT

8

33 34 35

TBT_A_DP_PWRDN

33 69

TBT_B_DP_PWRDN

33 70

TBT_A_HV_EN

33 35

TBT_B_HV_EN

33 35

Thunderbolt Host (1 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

25 74

IN

R3680

R3683

10K

1/20W

R3685

1/20W

R3688

1/20W

8 - GPIO_15
9 - GPIO_11
10 - GPIO_14
11 - GPIO_0
12 - GPIO_12
13 - GPIO_10
14 - PB_LSTX
15 - PB_LSRX

1

10K

5%

1/20W

MF

201

2

1

R3681

0

5%
1/20W
MF
201

2

NO STUFF

1

1

R3682

10K

5%

5%
1/20W

MF

MF

201

201

2

2

1

1

10K

10K

R3686

10K

5%
MF

201

2

2

1

1

R3687

10K

5%
MF

201

2

2

SYNC_DATE=11/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

36 OF 132

SHEET

33 OF 80

124578

5%
1/20W
MF
201

5%
1/20W
MF
201

SIZE

D

C

B

A

D

8 7 6 5 4 3

=PP1V05_TBTLC_RTR

8

???? mW (Single Port)

250 mW (Dual Port)

D

EDP: 1000 mA

C3700

10UF

20%

6.3V

CERM-X5R

0402-1

C3701

10UF

20%

6.3V

CERM-X5R

0402-1

1

1

C3710

1.0UF

20%
10V

2

2

X5R-CERM
0201-1

1

1

C3715

1.0UF

20%
10V

2

2

X5R-CERM
0201-1

1

C3711

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C3716

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C3712

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C3717

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C3713

1.0UF

20%
10V

2

X5R-CERM
0201-1

C

B

A

1

C3714

1.0UF

20%
10V

2

X5R-CERM
0201-1

AA14
AA20
AA22

AB11
AB17

AC10
AC12
AC14
AC16
AC18
AC20
AC22

J10
J12
J14
J16

K17
T15
U14

G10
G12
G14
G16
G18
H19
K19
M19
P19
T19
V15
V19
W12
W14

AD1
K13

L12
L16

M13
M17

N12
N16

P13
P17

R12
R16

T13
T17

U12
U16

A24

AA8

AB7

AC4
AC6
AC8

C10
C12
C14
C16
C18
C20

J8

V7
W8

G8
H9

K9

L8

M9

N8

P9

R8

T9

U8
V9

A2

B1
B7

VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON

VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE

VCC1P0_DPAUX
VCC1P0_DPAUX

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

CRITICAL

OMIT_TABLE

U3600

CACTUSRIDGE4C

FCBGA

(SYM 2 OF 2)

VCCGND

VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0

VCC3P3
VCC3P3
VCC3P3

VCC3P3_CIO
VCC3P3_CIO
VCC3P3_CIO

VCC3P3_DP
VCC3P3_DP
VCC3P3_DP
VCC3P3_DP

VCC3P3_DPAUX

VCC3P3_POC

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

K11
K15
L10
L14
M11
M15
N10
N14
P11
P15
R10
R14
T11
U10
V11
W10

M7
P7
T7

L18
N18
R18

H11
H13
H15
H17

H7

K7

C22
C24
C4
C6
C8
D21
D23
E4
F11
F13
F15
F17
F19
F21
F23
F5
F7
F9
G20
H21
H23
J18
J20
K21
K23
L20
M21
M23
N20
P21
P23
R20
T21
T23
U18
V13
V17
V21
V23
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y9

C3740

1.0UF

20%
10V

X5R-CERM

0201-1

C3770

1.0UF

20%
10V

X5R-CERM

0201-1

C3790

1.0UF

20%
10V

X5R-CERM

0201-1

1

C3741

1.0UF

20%
10V

2

X5R-CERM

0201-1

1

C3771

1.0UF

20%
10V

2

X5R-CERM

0201-1

=PP3V3_S4_TBT

EDP: 10 mA

1

2

1

2

1

2

C3742

1.0UF

X5R-CERM

0201-1

C3772

1.0UF

X5R-CERM

0201-1

8

20%
10V

20%
10V

33 35

1

2

1

2

C3743

1.0UF

20%
10V

X5R-CERM

0201-1

C3773

1.0UF

20%
10V

X5R-CERM

0201-1

1

2

1

2

C3744

1.0UF

X5R-CERM

0201-1

C3774

1.0UF

X5R-CERM

0201-1

20%
10V

20%
10V

1

2

1

2

C3745

1.0UF

20%
10V

X5R-CERM

0201-1

=PP3V3_TBTLC_RTR

??? mW (Single-Port)

250 mW (Dual-Port)
EDP: 240 mA

1

C3760

10UF

20%

6.3V

2

CERM-X5R
0402-1

=PP1V05_TBTCIO_RTR

???? mW (Single-Port)

2700 mW (Dual-Port)

EDP: 3000 mA

1

1

C3705

10UF

20%

6.3V

2

2

CERM-X5R
0402-1

8

33 35

SYNC_MASTER=J5_MLB_KEPLER

PAGE TITLE

Thunderbolt Host (2 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

6 3

12

SYNC_DATE=11/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

37 OF 132

SHEET

34 OF 80

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

Page Notes

Power aliases required by this page:

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP15V_TBT_REG (15V Boost Output)

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

- =PP3V3_TBTLC_FET (3.3V FET Output)

- =PP3V3_S0_TBTPWRCTL

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP1V05_TBTLC_FET (1.05V FET Output)

Signal aliases required by this page:

- =TBT_CLKREQ_L

D

- =TBT_RESET_L

BOM options provided by this page:

TBTBST:Y - Stuffs 15V boost circuitry.

C

=PP3V3_S0_TBTPWRCTL

8

SSM3K15FV

TBT_EN_LC_PWR

33

IN

TBT_EN_LC_ISOL

64

OUT

=TBT_RESET_L

25

IN

Platform (PCIe) Reset

TBT_CLKREQ_L

17

OUT

Pull-ups provided by SB page.

B

=PP3V3_S0_P3V3TBTFET

8

A

TBT_A_HV_EN

33 35

IN

TBT_B_HV_EN

33 35

IN

Q3840

SOD-VESM-HF

D

3

1

R3810

10K

5%

1/20W

MF

201

2

R3812

0

12

5%

1/20W

MF

201

P1V05TBTS0_PGOOD

TBTBST:Y

Q3805

SSM6N37FEAPE

C3800

0.1UF

X5R-CERM

1

R3840

1

10K

5%

GS

1/20W
MF
201

2

2

NO STUFF

R3816

1/20W

1

C3810

1UF

20%

6.3V
2

X5R

0201

TBT_EN_LC_RC

TBTBST_PWREN_L

TBTBST:Y

Q3805

SSM6N37FEAPE

SOT563

5

SOT563

6

D

2

SG

1

Supervisor & CLKREQ# Isolation

1

10%

201

0201

5%
MF

16V

2

3

6
8

1

0

2

VDD

U3800

SLG4AP016V

TDFN

DLY

MR*

EN
OUT

(OD)

GND

5

1

CRITICAL

SENSE

+

-

RESET*

THRM

PAD

9

0.7V

2

4

7

IN

TBT_EN_LC_ISOL_R

3.3V TBT "LC" Switch

U3810

TPS22924

CSP

A2

VIN

R3811

0

5%

1/20W

MF

201

NO STUFF

64

IN

B2

CRITICAL

C2

12

1

C3811

1UF

20%

6.3V

2

X5R
0201

ON

GND

C1

=PPVIN_SW_TBTBST

8

8-13V Input
Changes required
for 2S.

TBTBST:Y

R3881

330K

1/16W
MF-LF

3

D

SG

4

=PP3V3_TBTLC_RTR

1

R3807

100K

5%
1/20W
MF
201

2

=PP1V05_TBTLC

TBT_PCIE_RESET_L

DLY = 60 ms +/- 20%

=TBT_CLKREQ_L
TBT_CLKREQ_ISOL_L

MAKE_BASE=TRUE

=PP3V3_TBTLC_FET

A1
B1

Max Current = 2A (85C)

VOUT

5%

402

TBTBST:Y

1

2

R3880

470K

1/16W
MF-LF

402

TBTBST:Y

1

R3892

73.2K

1%
1/16W
MF-LF
402

2

<R2>

8

33 34 35

8

Part

Type

R(on)

@ 2.5V

33

IN

TBTBST:Y

1

1

C3880

0.1UF

5%

10%
25V

2

X5R
402

2

TBTBST_PWREN_DIV_L

TBTBST:Y

C3890

2.2UF

20%
10V
X5R-CERM
402

33

OUT

33

IN

8

U3810

TPS22924C

Load Switch

18.3 mOhm Typ

24 mOhm Max

TBT_EN_CIO_PWR_L

CRITICAL
TBTBST:Y

Q3880

SI8409DB

BGA

SGD

4

1

TBTBST:Y

1

C3891

2.2UF

20%
10V

2

X5R-CERM
402

UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)

TBTBST:Y

1

C3892

2.2UF

20%
10V

2

X5R-CERM
402

8

33 34

=PP3V3_S4_TBT

TBTPOCRST_CT

1

C3831

0.0047UF

10%
25V

2

CERM
402

=PP1V05_S0_P1V05TBTREG

8

80

=PP3V3_TBTLC_RTR

8

33 34 35

1

R3820

100K

5%
1/20W
MF
201

2

TBT_EN_CIO_PWR

6

Q3825

SSM6N37FEAPE

SOT563

D

2

SG

1

SI8409DB:
Vds(max): -30V
Vgs(max): +/-12V
Vgs(th): -1.4V
Rds(on): 46mOhm @ 4.5V Vgs
Id(max): 3.7A @ 70C

PPVIN_SW_TBTBST

8

MIN_LINE_WIDTH=0.5 mm

2 3

MIN_NECK_WIDTH=0.25 mm

Voltage not specified here,
add property on another page.

TBTBST:Y

R3891

TBTBST:Y

1

1

C3887

68PF

5%
50V

2

2

CERM
402-1

Intel investigating whether RC is sufficient.

C3830

0.1UF

TBTBST:Y

TBTBST_VC_RC

1

C3893

0.0033UF

10%
50V

2

CERM
402

R3893

49.9K

1/16W
MF-LF

TBTBST:Y

R3894

26.7K

1%

402

1

2

1/16W
MF-LF

402

1

1%

2

TBT "POC" Power-up Reset

1

CRITICAL

VDD

SENSE

U3830

TPS3808

QFN

CT

GND

5

10%
25V
X5R
402

3

1

2

1.05V TBT "CIO" Switch

U3820

TPS22920

CSP

A2
B2
C2

D2

1

C3820

1UF

20%

6.3V

2

X5R
0201

VIN

CRITICAL

ON

GND

VOUT

D1

200K

1/16W
MF-LF

402

6

1

THRM

PAD

7

Thunderbolt 15V Boost Regulator

TBTBST:Y

C3860

10UF

20%
25V
X5R-CERM

1

0603

1%

2

<R1>

TBTBST_EN_UVLO

TBTBST_INTVCC

TBTBST_VC

TBTBST_RT

TBTBST_SS

TBTBST:Y

1

C3894

0.33UF

10%

6.3V

2

CERM-X5R
402

GND_TBTBST_SGND

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V

TBTBST:Y

D

Q3888

SSM6N37FEAPE

SOT563

Max Vgs: 10V

2

S G

TBTBST_SHDN_DIV

TBTBST:Y

1

R3887

330K

5%
1/16W
MF-LF
402

2

62

RESET*

4

MR*

TPS3808G25
Vt = 2.33V +/- 2%
Delay = 27.3ms

=PP1V05_TBTCIO_FET

A1

Max Current = 4A (85C)

B1
C1

TBTBST:Y

1

C3861

2

Pull-up: R3610

10UF

20%
25V
X5R-CERM
0603

1

2

3

4

TBT_PWR_ON_POC_RST_L

TBTPOCRST_MR_L

1

C3825

330PF

10%
16V

2

X7R-CERM
0201

Part

Type

R(on)
@ 1.05V

VIN

25

EN/UVLO

28

INTVCC

30

VC

33

RT

32

SS

34

SYNC

SGND

42324

SGND shorted to
GND inside package,
no XW necessary.

TBTBST:Y

1

R3888

330K

5%
1/16W
MF-LF
402

2

TBTBST:Y

D

Q3888

SSM6N37FEAPE

SOT563

5

S G

SMC_DELAYED_PWRGD

OUT

SSM6N37FEAPE

8

U3820

TPS22920

Load Switch

8 mOhm Typ

11.5 mOhm Max

27

Q3825

6 3

CRITICAL
TBTBST:Y

L3895

3.3UH-6.5A

1 2

IHLP

8

9

CRITICAL
TBTBST:Y

U3890

LT3957

QFN

1213141516

37

33

SOT563

D

3

PART NUMBER

138S0811

TBTBST_BOOST

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

202138

SW

SNS1

SNS2

NC

FBX

GND

17

5

S G

4

TBTBST_SNS1

TBTBST:Y

R3889

5%

1/20W

MF

6

3

1
2
10

NC

35
36

31

TBTBST_SNS2

TBTBST_VSNS

TBTBST:Y

1

C3888

10PF

5%
50V

2

CERM
402

TBTBST_FBX

NO STUFF

1

C3889

100PF

5%
50V

2

CERM
402

Vout = 1.6V * (1 + Ra / Rb)

TBT_A_HV_EN

33 35

39 40 66

IN

TBT_B_HV_EN

33 35

=PP3V3_S0_PCH_GPIO

1

R3830

100K

5%
1/20W
MF
201

2

TBT_SW_RESET_L

QTY

4

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X6S,0603

201

XW3895

TBTBST:Y

R3895

137K

1/16W
MF-LF

<Ra>

TBTBST:Y

R3896

15.8K

1/16W
MF-LF

<Rb>

17 18 19 20 25

8

20

IN

1

1 2

3

12

PLACE_NEAR=C3895.1:2 mm

1

2

OMIT_TABLE

1

2

1

C3896

2

CRITICAL
TBTBST:Y

D3895

PDS540XF

PWRDI5

C3895

4.7UF

10%
35V
X5R-CERM
0603

TBTBST:Y

20%

25V

POLY-TANT

CASE-D3L

1

2

OMIT_TABLE

1

2

0

2

SM

1%

402

1%

402

33UF-0.06OHM

R3850

0

12

5%

1/20W

MF

201

NO STUFF

D3850

1N4448HLP-7

1N4448HLP-7

DFN1006

R3860

0

5%

1/20W

MF

201

NO STUFF

D3860

DFN1006

AK

12

AK

REFERENCE DES

C3895,C3897,C3898,C389A

SYNC_MASTER=J5_MLB_KEPLER

PAGE TITLE

Thunderbolt Power Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

C3897

4.7UF

10%
35V
X5R-CERM
0603

C3865

X5R-CERM

C3850

=PP15V_TBT_REG

Vout = 15.47V
Max Current = 2A?

Freq = 500KHz

OMIT_TABLE

1

C3898

4.7UF

10%
35V

2

X5R-CERM
0603

TBT_A_HV_EN_RC

1

10%

6.3V
0201

NO STUFF

2

1.0UF

X5R-CERM

TBT_B_HV_EN_RC

1

10%

6.3V
0201

NO STUFF

2

1.0UF

CRITICAL

CRITICAL TBTBST:Y

OMIT_TABLE

1

C389A

4.7UF

10%
35V

2

X5R-CERM
0603

TBTBST:Y

C3899

0.001UF

10%
50V
X7R
402

BOM OPTION

SYNC_DATE=11/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

38 OF 132

SHEET

35 OF 80

124578

D

8

1

2

C

69

OUT

70

OUT

B

A

SIZE

D

8 7 6 5 4 3

OMIT_TABLE

L4470

0.6NH+/-0.1NH-0.85A

NOSTUFF

1

C4470

0.1UF

10%
16V

2

7

36 75

OUT

7

36 75

OUT

PCIE_AP_R2D_P
PCIE_AP_R2D_N

X5R-CERM
0201

D

1 2

0201

L4471

0.6NH+/-0.1NH-0.85A

NOSTUFF

1

C4472

0.1UF

10%
16V

2

X5R-CERM
0201

1 2

L4473

1 2

0201

NOSTUFF

0.6NH+/-0.1NH-0.85A

1

C4476

0.1UF

10%

NOSTUFF

16V

2

X5R-CERM
0201

7

36 75

IN

7

36 75

IN

PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N

0.6NH+/-0.1NH-0.85A

1

C4474

0.1UF

10%
16V

2

X5R-CERM
0201

C

PCIE_CLK100M_AP_CONN_P

7

36 78

OUT

PCIE_CLK100M_AP_CONN_N

7

36 78

OUT

PCIE_AP_R2D_PI_P

7

75

0201

OMIT_TABLE

OMIT_TABLE

L4474

1 2

0201

OMIT_TABLE

PLACE_NEAR=J4410.42:2.54MM

1

2

7

75

CRITICAL

L4401

90-OHM-100MA

4 3

PLACE_NEAR=J4400.28:2.54MM

C4433

NOSTUFF

C4471

0.1UF

10%
16V
X5R-CERM
0201

PCIE_AP_R2D_PI_N

NOSTUFF

1

C4473

0.1UF

10%
16V

2

X5R-CERM
0201

NOSTUFF

1

C4475

0.1UF

10%
16V

2

X5R-CERM
0201

NOSTUFF

1

C4477

0.1UF

10%
16V

2

X5R-CERM
0201

DLP11S

SYM_VER-1

21

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

1 2

0.1UF

16V10%

X7R-CERM0402

1 2

10% 16V

C4432

PLACE_NEAR=J4400.29:2.54MM

PCIE_AP_D2R_P

PCIE_AP_D2R_N

0.1UF

X7R-CERM0402

OUT

OUT

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

7

17 75

USB_BT_CONN_P

78

USB_BT_CONN_N

78

7

17 75

IN

IN

7

17 75

IN

7

17 75

IN

PP3V3_S3RS4_BT_F

36

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

NOSTUFF NOSTUFF

1

R4415

15K

1%
1/20W
MF
201

2

1

C4417

0.01UF

10%
16V

2

X7R-CERM
0402

NOSTUFF

1

R4417

15K

1%
1/20W 1/20W
MF
201

2

1

R4416

15K

1%
1/20W
MF
201

2

BTPWR:S4

7

17 75

7

17 75

7

18 27 36 38 39 66

PM_SLP_S4_L

IN

R4411

0

1 2

5%

1/20W

MF

201

SEL OUTPUT

RIO FLEX CONNECTOR

7

18 27 39 66

IN

7

18 27 36 38 39 66

IN

24

7

OUT

7

26 74

BI

7

26 74

BI

42

IN

42

B

BI

25

OUT

7 9

IN

7 9

BI

7

17 75

IN

7

17 75

IN

42

IN

42

BI

25

IN

7

36 78

IN

7

36 78

IN

7

18

IN

7

36

IN

7

36

OUT

7 9

36 74

BI

7 9

36 74

BI

7

39 40

OUT

7

17

OUT

7 9

IN

=PP3V3_S4_RIO

8

A

PM_SLP_S3_L

PM_SLP_S4_L
USB_EXTB_OC_L
USB_EXTB_P
USB_EXTB_N

=I2C_HDMIRDRV_SCL
=I2C_HDMIRDRV_SDA

SDCONN_STATE_CHANGE_RIO

HDMI_IG_DDC_CLK
HDMI_IG_DDC_DATA

PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
=I2C_X29THMSNS_SCL
=I2C_X29THMSNS_SDA

=ENET_RESET_L

PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N

PCIE_WAKE_L
AP_CLKREQ_Q_L
AP_RESET_CONN_L
USB_BT_CONN_P
USB_BT_CONN_N

WIFI_EVENT_L

ENET_CLKREQ_L
SD_PWR_EN

PLACE_NEAR=J4410.33:2.54MM

1

C4410

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

J4410

DF40CG3.0-70DS-0.4V

F-ST-SM

7172

2

1

4

3

6

5
7

8

9

10

1112

1516
1718
19

20

2122
2324
2526

29

30

3132
3334
3536
3738
39

40

4142
4344

4748
49

50

5152
5354
5556
5758

6162
6364
6566
6768
69

70

7374

USB3_EXTB_RX_RC_N
USB3_EXTB_RX_RC_P

USB3_EXTB_TX_C_N

GND_VOID=TRUE

USB3_EXTB_TX_C_P

GND_VOID=TRUE

HDMI_IG_CLK_C_N
HDMI_IG_CLK_C_P

HDMI_IG_DATA_C_N<2>
HDMI_IG_DATA_C_P<2>

HDMI_IG_DATA_C_N<1>
HDMI_IG_DATA_C_P<1>

HDMI_IG_DATA_C_P<0>
HDMI_IG_DATA_C_N<0>

HDMI_HPD_L

PCIE_ENET_D2R_P
PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N

PCIE_AP_R2D_N
PCIE_AP_R2D_P

PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N

GND_VOID=TRUE
GND_VOID=TRUE

C4402

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

OUT

0.1UF

1 2

GND_VOID=TRUE

7 9

78

IN

7 9

78

IN

IN
IN

IN
IN

IN
IN

7

36 40

7

17 75

OUT

7

17 75

OUT

7

17 75

IN

7

17 75

IN

7

36 75

IN

7

36 75

IN

7

36 75

OUT

7

36 75

OUT

10%

7 9

78

7 9

78

7 9

78

7 9

78

7 9

78

7 9

78

GND_VOID=TRUE

16V

0201

X5R-CERM

C4401

7

36

7

36

GND_VOID=TRUE

OUT

IN

516S1058

L USB_BT_WAKE
H USB_BT

USB3_EXTB_TX_N

0.1UF

GND_VOID=TRUE

1 2

USB3_EXTB_TX_P

10% 16V

AP_RESET_CONN_L

AP_CLKREQ_Q_L

X5R-CERM

1

R4453

100K

1%
1/16W
MF-LF
402

2

0201

Supervisor & CLKFREG # Isolation

1

R4454

232K

1%
1/16W
MF-LF
402

2

1

R4455

100K

1%
1/16W
MF-LF
402

2

PART NUMBER

117S0002

BTPWR:S4

L4415

0402-LF

L4416

0402-LF

201

12

12

1

0

5%
MF

2

1
2

10

Y+
Y-

PI3USB102ZLE

SEL OE*

FERR-120-OHM-1.5A

PLACE_NEAR=J3501.27:2.54MM

BTPWR:S3

FERR-120-OHM-1.5A

PLACE_NEAR=J3501.27:2.54MM

BTPWR:S3

R4418

BTMUX_SEL

NOSTUFF

1

C4416

0.01UF

10%
16V

2

CERM

402

19 74

IN

19 74

IN

Delay = 130 ms +/- 20%

PP3V3_WLAN_F

CRITICAL

P3V3WLAN_VMON

2

4

7

=PP3V3_S4_BT

=PP3V3_S3_BT

CRITICAL

NOSTUFF

7

SLG4AP041V

SENSE
VREF

RESET*

IN

QTY

4

DEBUG CURRENT SENSE RD135 connects to PP3V3_WLAN_F

AIRPORT

8

8

9

VCC

U4410

TQFN

GND

3

NOSTUFF

36 40 80

U4440

TDFN
+

-

THRM

PAD

9

5

M+

4

M-

7

D+

6

D-

8

SIGNAL_MODEL=MOJO_MUX

R4420

1 2

1/20W

C4420

15PF

1 2

C4421

15PF

1 2

R4421

1 2

1

VDD

DLY

MR*

EN

OUT

(OD)

GND

5

DESCRIPTION

RES, 0OHM, 0201

PP3V3_S3RS4_BT_F

1

C4415

0.1UF

10%

6.3V

2

X5R
201

USB_BT_WAKE_P

78

USB_BT_WAKE_N

78

USB_BT_P
USB_BT_N

0

GND_VOID=TRUE

5%
MF

201

GND_VOID=TRUE

5%
25V
NPO
201

GND_VOID=TRUE

5%
25V
NPO
201

GND_VOID=TRUE

0

5%

1/20W

MF

201

=PP3V3_S3_WLAN

1

C4440

0.1uF

20%
10V

2

CERM
402

3

6

8

=PP3V3_S3_WLAN

8

36 66

66

IN

7 9

36

BI

74
7 9

36

BI

74

9

AP_RESET_L

AP_PWR_EN

AP_CLKREQ_L

*NOTE: This connector is shielded 70P Hirose Receptacle.

Note: This receptacle mates with the plug with APN 998-4708.

REFERENCE DES

L4470,L4471,L4473,L4474

PM_WLAN_EN

36

SSM3K15FV

NOSTUFF

1

R4414

15K

1%
1/20W
MF
201

2

BTPWR:S4

1

R4412

15K

1%
1/20W
MF
201

2

NOSTUFF

1

R4413

15K

1%
1/20W
MF
201

2

USB3_EXTB_RX_N

USB3_EXTB_RX_P

=PP3V3_S0_HDMI

8

HDMI_HPD

OUT

8

36 66

25

IN

19 24 66

IN

17

OUT

CRITICAL

BTPWR:S4

Q4410

SOD-VESM-HF

1

G S

36 40 80

7

19 74

OUT

7

19 74

OUT

74LVC1G00GF

SOT891

U4450

TPS22924

A2

VIN

B2

CRITICAL

C2

ON

=BT_WAKE_L

3

D

2

=PP1V5_S0_RDRVR

8

=PP5V_S4_RIO

8

=PP3V3_S3_RIO

8

PP3V3_WLAN_F

7

PLACE_NEAR=J4440.4:2.54MM

1

C4493

0.1UF

10%
16V

2

X5R-CERM
0201

6

2

U4430

3

A

1

B

NC

5

4

NC

APN:311S0302

BOM OPTION

3V S3 WLAN FET

Max Current = 2A (85C)

CSP

GND

A1

VOUT

B1

C1

OUT

PP3V3_WLAN_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

Part

Type

R(on)

@ 2.5V

40

RIO POWER CONNECTOR

1

C4490

0.1UF

10%
16V

2

X5R-CERM
0201

PLACE_NEAR=J4440.1:2.54MM

=PP3V3_S4_SMC

8

25 40

PLACE_NEAR=U4430.5:4mm

1

C4430

0.1UF

10%
16V

2

X5R-CERM
0201

HPD sink High: 2.0V-5.3V
HPD sink Low: 0.0V-0.8V

SYNC_MASTER=MASTER

PAGE TITLE

1

C4491

0.1UF

10%
16V

2

X5R-CERM
0201

1

2

PLACE_NEAR=J4440.4:2.54MM

1

R4430

100K

5%
1/20W
MF
201

2

PLACE_NEAR=J4440.2:2.54MM

RIO CONNECTORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

80

U4450

TPS22924C

Load Switch

18.3 mOhm Typ

24 mOhm Max

504050-0691

C4492

0.1UF

10%
16V
X5R-CERM
0201

HDMI_HPD_L

12

CRITICAL

J4400

M-RT-SM

7

1
2
3
4
5
6

8

518s0862

7

36 40

IN

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

44 OF 132

SHEET

36 OF 80

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

C4518 & C4517 Placement Note:
It is critical that these two should be near
to U1800 pin AM1 and AM3.

D2R Passive DeEmphasis

VALUE: 0.0 DB

R4506

0

SATA_SSDRHDD_D2R_P

7

D

37 74

SATA_SSDRHDD_D2R_N

7

37 74

C4515

5.0PF

C4519

5.0PF

R4507

0

GND_VOID=TRUE

1 2

5%

1/20W

NOSTUFF

GND_VOID=TRUE

1 2

0201 +/-0.1PF

NOSTUFF

GND_VOID=TRUE

1 2

+/-0.1PF

0201

GND_VOID=TRUE

1 2

5%

1/20W

C0G

C0G

201MF

SATA_HDD_D2R_RC_P

7

74

25V

SATA_HDD_D2R_RC_N

7

74

25V

201MF

0.01UF

0.01UF

1 2

1 2

10%16V

PLACE_NEAR=U1800.AM1:5MM
GND_VOID=TRUE

C4518
C4517

16V10%

PLACE_NEAR=U1800.AM3:5MM
GND_VOID=TRUE

SATA_HDD_D2R_P

0402X7R-CERM

SATA_HDD_D2R_N

0402X7R-CERM

7

17 74

OUT

7

17 74

OUT

12

D

R4508

0

NOSTUFF

SATA_SSDRHDD_R2D_N

7

37 74

SATA_SSDRHDD_R2D_P

7

37 74

C4521

15PF

C4524

15PF

NOSTUFF

R4510

R2D Passive DeEmphasis

VALUE: 0.0 DB

C

PP3V3_S0_SSD_FLT

7

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V

516S1035 (recpt)

CRITICAL

J4500

DF40CG1.5-48DS-0.4V

F-ST-SM

49

50

2

1
3

4
6

5
7 8
9

10
11 12
13 14
15 16

20

30

40

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

19
21 22

B

7

39 40

IN

7

39 40

OUT

SMC_OOB1_TX_L

SMC_OOB1_RX_L

23 24
25 26
27 28
29
31 32

35 36
37 38
39
41 42
43 44
45 46
47 48

51 52

GND_VOID=TRUE

1 2

5%

1/20W

GND_VOID=TRUE

1 2

GND_VOID=TRUE

1 2

5%25V

GND_VOID=TRUE

1 2

5%01/20W

PLACE_NEAR=L4500.1:2MM

SATA_SSDRHDD_D2R_P
SATA_SSDRHDD_D2R_N

SATA_SSDRHDD_R2D_P
SATA_SSDRHDD_R2D_N

201MF

SATA_HDD_R2D_RC_N

7

74

2015% NPO25V

SATA_HDD_R2D_RC_P

7

74

201NPO

201MF

PLACE_NEAR=J4500.9:3mm

CRITICAL

L4500

FERR-70-OHM-4A

1 2

0603

1

C4501

0.1UF

20%
10V

2

CERM
402

7

37 74

7

37 74

7

37 74

7

37 74

C4522

1 2

0.01UF

C4525

1 2

0.01UF

PP3V3_S0_SSD_R

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=3.3V

1

C4502

0.1UF

20%
10V

2

CERM
402

PLACE_NEAR=L4500.2:2MM

10%

GND_VOID=TRUE

16V

GND_VOID=TRUE

16V10%

SATA_HDD_R2D_C_N

0402X7R-CERM

SATA_HDD_R2D_C_P

0402X7R-CERM

CRITICAL

R4530

0.001

1%
1W
MF

0612

2 1
4 3

7

IN

7

IN

=PP3V3_S0_SSD

ISNS_SSD_P
ISNS_SSD_N

17 74

17 74

C

8

43 78

OUT

43 78

OUT

B

SATA GUMSTICK2 CONNECTOR

L4510

PP5V_S0_HDD_FLT

7

MIN_LINE_WIDTH=0.6MM

A

MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

6 3

FERR-70-OHM-4A

1 2

0603

CRITICAL

PLACE_NEAR=J4500.39:3MM

2

C4510

0.1UF

20%
10V

1

CERM
402

PLACE_NEAR=L4510.1:2MM

=PP5V_S0_HDD

2

C4511

0.1UF

20%
10V

1

CERM
402

PLACE_NEAR=L4510.2:2MM

8

SYNC_MASTER=MASTER

PAGE TITLE

SSD/HDD Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

45 OF 132

SHEET

37 OF 80

SIZE

A

D

124578

8 7 6 5 4 3

12

D

USB Port Power Switch

D

Left USB Port A

=PP5V_S3_LTUSB

8

PM_SLP_S4_L

7

18 27 36 39 66

1

R4690

5.1K

5%
1/16W
MF-LF

402

2

24

OUT

USB_EXTA_OC_L

USB_PWR_EN

CRITICAL

C4690

10UF

20%

6.3V
X5R
603

1

1

C4691

0.1UF

20%
10V

2

2

CERM
402

C4692

0.47UF

10%
10V
X5R

0402

1

220UF-35MOHM

2

CASE-B2-SM1

CRITICAL

C4696

6.3V

POLY-TANT

20%

1

2

C

CURRENT LIMIT (R4600): 2.19A MIN / 2.76A MAX

1

2

SIGNAL_MODEL=MOJO_MUX

9

VCC

5

M+

4

M-

U4650

PI3USB102ZLE

TQFN

7

D+

CRITICAL

6

D-

SMC_DEBUG_YES

8

SELOE*

GND

3

NO_XNET_CONNECTION=TRUE

SMC_DEBUG_NO

Y+
Y-

1
2

10

R4651

0

1 2

5%
1/16W
MF-LF

402

SMC_DEBUG_YES

1

R4650

10K

5%
1/16W
MF-LF
402

2

SMC_DEBUGPRT_EN_L

SEL=0 Choose SMC
SEL=1 Choose USB

NO_XNET_CONNECTION=TRUE

SMC_DEBUG_NO

R4652

0

1 2

5%
1/16W
MF-LF

402

=PP3V42_G3H_SMCUSBMUX

8

SMC_DEBUG_YES

C4650

0.1UF

20%
10V

CERM

SMC_DEBUGPRT_RX_L

39 40

IN

SMC_DEBUGPRT_TX_L

39 40

OUT

USB_EXTA_P

19 74

BI

USB_EXTA_N

19 74

BI

402

B

CRITICAL

U4600

TPS2557DRB

2

IN_0

3

IN_1

8

FAULT*

4

EN

GND

1

SON

IN

THRM

PAD

9

39

OUT1

OUT2

ILIM

6
7

5

USB_ILIM

NO_TEST=TRUE

R4601

22.1K

1/20W

201

USB_ILIM_R

NO_TEST=TRUE

R4600

22.1K

1/20W

201

1%
MF

1%
MF

1

CRITICAL

C4695

2

1

2

10UF

6.3V

20%
X5R

603

PP5V_S3_LTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1

2

USB_EXTA_MUXED_N

74

USB_EXTA_MUXED_P

74

USB3_EXTA_RX_N

7

19 74

OUT

USB3_EXTA_RX_P

7

19 74

OUT

C4605

0.1UF

20%
10V

CERM

402

CRITICAL

2

D4620

ESD0P2RF-02LS

TSSLP-2-1

GND_VOID=TRUE

1

FERR-120-OHM-3A

1

2

90-OHM-50MA

CRITICAL

L4605

1 2

0603

CRITICAL

L4600

TCM0605-1

SYM_VER-1

1

2 3

2

D4621

ESD0P2RF-02LS

TSSLP-2-1

GND_VOID=TRUE

1

PP5V_S3_LTUSB_A_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

4

CRITICAL

NC

6

VBUS

1

GND

D4600

RCLAMP0582N

SLP1210N6

CRITICAL

R4620

0

1 2

5%

1/20W

MF

201

C4620

15PF

1 2

5%
25V
NPO
201

NOSTUFF

NOSTUFF

C4621

15PF

1 2

5%
25V
NPO
201

R4621

0

1 2

5%

1/20W

MF

201

452 3

NC

IO

IO

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

CRITICAL

7

USB3_EXTA_TX_C_P

7

79

7

79

USB3_EXTA_TX_C_N

USB_LT1_N

7

74

USB_LT1_P

7

74

7

79

USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N

7

79

514-0835

J4600

USB3.0-LEFT-D1

F-RT-TH

1

VBUS

2

SSTX+

3

SSTX-

4

GND

5

D-

6

D+

7

GND

8

SXRX+

9

SSRX-

10

GND

11
12
13
14
15
16
17
18
19
20
21
22
23

C

B

USB/SMC Debug Mux

GND_VOID=TRUE

C4611

0.1UF

0.1UF

1 2

16V10%

0201

X5R-CERM

1 2

16V10%

0201

GND_VOID=TRUE

X5R-CERM

CRITICAL

2

D4610

ESD0P2RF-02LS

TSSLP-2-1

GND_VOID=TRUE

1

CRITICAL

2

D4611

ESD0P2RF-02LS

TSSLP-2-1

GND_VOID=TRUE

1

6 3

SYNC_MASTER=J5_AMD

PAGE TITLE

USB 3.0 CONNECTORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=08/24/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

46 OF 132

SHEET

38 OF 80

124578

SIZE

A

D

7

19 74

IN

19 74

IN

USB3_EXTA_TX_N

USB3_EXTA_TX_P

C4610

A

8 7 6 5 4 3

NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

D

LPC_AD<0>

7

17 41 75

BI

LPC_AD<1>

7

17 41 75

BI

LPC_AD<2>

7

17 41 75

BI

LPC_AD<3>

7

17 41 75

BI

LPC_CLK33M_SMC

7

25 75

IN

LPC_FRAME_L

7

17 41 75

IN

SMC_LRESET_L

25

IN

LPC_SERIRQ

7

17 41

BI

PM_CLKRUN_L

7

18 41

OUT

LPC_PWRDWN_L

7

18 25 41

IN

SMC_RUNTIME_SCI_L

20

OUT

SMC_WAKE_SCI_L

20

OUT

SMBUS_SMC_0_S0_SCL

42 77

BI

SMBUS_SMC_0_S0_SDA

42 77

BI

SMBUS_SMC_1_S0_SCL

7

42 77

BI

SMBUS_SMC_1_S0_SDA

7

42 77

BI

SMBUS_SMC_2_S3_SCL

7

42 77

BI

SMBUS_SMC_2_S3_SDA

7

42 77

C

B

BI

SMBUS_SMC_3_SCL

42 77

BI

SMBUS_SMC_3_SDA

42 77

BI

SMBUS_SMC_4_ASF_SCL

40

BI

SMBUS_SMC_4_ASF_SDA

40

BI

SMBUS_SMC_5_G3_SCL

7

42

BI

SMBUS_SMC_5_G3_SDA

7

42

BI

SMC_FAN_0_CTL

46

OUT

SMC_FAN_0_TACH

46

IN

SMC_FAN_1_CTL

46

OUT

SMC_FAN_1_TACH

46

IN

TP_SMC_MPM5_LED_PWR

7

TP_SMC_MPM5_LED_CHG

7

SMC_SYS_KBDLED

48

OUT

SMC_T25_EN_L

40

OUT

SYS_TDM_ONEWIRE

40

BI

SYS_ONEWIRE

56

BI

HISIDE_ISENSE_OC

40

IN

SMC_ODD_DETECT

40

IN

CPU_PECI_R

40

BI

SMC_PECI_L

40

OUT

SMC_BIL_BUTTON_L

40

IN

SMC_DP_HPD_L

40

IN

SMC_PME_S4_WAKE_L

40

IN

SMC_PME_S4_DARK_L

40

IN

SMC_S4_WAKESRC_EN

40 66

OUT

SMC_LID

40 47

IN

ENET_ASF_GPIO

40

OUT

SMS_INT_L

40 49

IN

SMC_BC_ACOK

40 56

IN

G3_POWERON_L

40

IN

PM_SLP_S3_L

7

18 27 36 66

IN

PM_SLP_S4_L

7

18 27 36 38 66

IN

PM_SLP_S5_L

18 66

IN

SMC_ONOFF_L

7

40 47

IN

SMC_RX_L

7

40 41

IN

SMC_TX_L

7

40 41

OUT

USB_SMC_N

9

74

BI

USB_SMC_P

9

74

BI

NC FOR ENG PACKAGE

NC FOR ENG PACKAGE

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR ENG PACKAGE

(OD)
(OD)

(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)

(OD)
(OD)

(OD)

B13
A13
C12
D11
H12
D12
C13
H13
G11
F13
F12
B12

E10
D13

H11
L13
C11

A12

D10

L11
N12
N11
M11

M13
L12

J12

J13

NC
NC

E13

E12

LPC0AD0
LPC0AD1
LPC0AD2
LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0RESET*
LPC0SERIRQ
LPC0CLKRUN*
LPC0PD*
LPC0SCI*
PK5

I2C0SCL
I2C0SDA

M4

I2C1SCL

N2

I2C1SDA

N8

I2C2SCL

M8

I2C2SDA

L8

I2C3SCL

K8

I2C3SDA

N7

I2C4SCL

M7

I2C4SDA

N4

I2C5SCL

N3

I2C5SDA

PM6/FAN0PWM0
PM7/FAN0TACH0
PK6/FAN0PWM1
PK7/FAN0TACH1

G3

PN2/FAN0PWM2
PN3/FAN0TACH2

PN4/FAN0PWM3
PN5/FAN0TACH3
PN6/FAN0PWM4
PN7/FAN0TACH4

J4

PH2/FAN0PWM5

J2

PH3/FAN0TACH5

C4

PECI0RX

C6

PECI0TX

PP0/IRQ116
PP1/IRQ117

M5

PP2/IRQ118
PP3/IRQ119
PP4/IRQ120

L5

PP5/IRQ121

D8

PP6/IRQ122

K6

PP7/IRQ123

D4

PQ0/IRQ124

E4

PQ1/IRQ125

F5

PQ2/IRQ126

N5

PQ3/IRQ127

N6

PQ4/IRQ128

K5

PQ5/IRQ129

M6

PQ6/IRQ130

L6

PQ7/IRQ131

L3

U0RX

M1

U0TX

USB0DM
USB0DP

U4900

LM4FSXAH5BB

BGA

(1 OF 2)

OMIT_TABLE

T3CCP1/PJ5/C2­T3CCP0/PJ4/C2+

AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23

PC5/C1+

SSI0CLK/PA2
SSI0FSS/PA3

SSI0RX/PA4
SSI0TX/PA5

U1RX/B0

U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7

SSI1RX/PF0
SSI1TX/PF1

SSI1CLK/PF2
SSI1FSS/PF3

WT0CCP0/PG4
WT0CCP1/PG5

WT2CCP0/PH0
WT2CCP1/PH1

WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7

T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3

WT5CCP1/PM3

C0­C0+
C1-

PF4
PF5

E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6

NC FOR STACK BOARD

A6

NC FOR STACK BOARD

C1
C2
B1
B2
G2

NC FOR STACK BOARD

G1

NC FOR STACK BOARD

H1

NC FOR STACK BOARD

H2

NC FOR STACK BOARD

B7

NC FOR STACK BOARD

A7

NC FOR STACK BOARD

B8

NC FOR STACK BOARD

A8

1.2V FOR ENG PACKAGE

K2
K1
L2
L1

SPI_DESCRIPTOR_OVERRIDE_L

C5
D5

M2
M3
L4
N1

F11
E11
F4
F3

M9
N9
L10
K10
L9
K9

K7
L7

K3
K4

J3
H4
H3
G4

C9
B9
A9
C8

H10

CPU_PROCHOT_L

SMC_VCCIO_CPU_DIV2

SMC_S5_PWRGD_VIN

CPU_CATERR_L

CPU_THRMTRIP_3V3

SMC_PM_G2_EN
PM_DSW_PWRGD

SMC_DELAYED_PWRGD

SMC_PROCHOT

SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L

SMC_SYS_LED

SMC_GFX_THROTTLE_L

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR STACK BOARD

SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L

PM_PCH_SYS_PWROK

SMC_DEBUGPRT_EN_L

SMC_GFX_OVERTEMP

ALL_SYS_PWRGD

SMC_THRMTRIP

PM_PWRBTN_L
PM_SYSRST_L
MEM_EVENT_L

(OD)

SMC_ADAPTER_EN

SMC_OOB1_RX_L

NC FOR ENG PACKAGE

SMC_OOB1_TX_L

NC FOR ENG PACKAGE

NC FOR ENG PACKAGE

IR_RX_OUT_RC

BDV_BKL_PWM

SMC_BATLOW_L

SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7
SMC_ADC8
SMC_ADC9
SMC_ADC10
SMC_ADC11
SMC_ADC12
SMC_ADC13
SMC_ADC14
SMC_ADC15
SMC_ADC16
SMC_ADC17
SMC_ADC18
SMC_ADC19
SMC_ADC20
SMC_ADC21
SMC_ADC22
SMC_ADC23

S5_PWRGD

40

40

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN

OUT

IN
IN

OUT
OUT
OUT
OUT

IN
OUT
OUT

IN
OUT
OUT
OUT

IN

IN

OUT

IN

IN
OUT

OUT
OUT

OUT

IN
OUT

IN
OUT

OUT

BI

BI

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

11 40 61 72

25 40

11 72

40

40 66

18

35 40 66

40

38 40

38 40

40

40

40

40

40

40

66

18 24 66

38

40

24 66

40

18 24

7

18 25

40

18 40 66

7

37 40

7

37 40

40

40

40 66

=PP3V3_S5_SMC

8

40

C4902

X5R-CERM

1

C4910

1UF

10%
25V

2

402

1UF

20%
10V

0603-1

1

2

1

C4911

1UF

10%
25V

2

X5RX5R
402

1

C4903

0.1UF

20%
10V

2

CERM
402

1

C4907

0.1UF

20%
10V

2

CERM
402

1

2

C4912

1UF

10%
25V
X5R
402

1

C4904

0.1UF

20%
10V

2

CERM
402

1

C4908

0.1UF

20%
10V

2

CERM
402

1

C4913

0.1UF

20%
10V

2

CERM
402

1

C4914

0.1UF

20%
10V

2

CERM
402

1

C4905

0.1UF

20%
10V

2

CERM
402

1

C4909

0.1UF

20%
10V

2

CERM
402

1

C4915

0.1UF

20%
10V

2

CERM
402

1

C4906

0.1UF

20%
10V

2

CERM
402

1

C4916

0.1UF

20%
10V

2

CERM
402

7

40 41 57

7

36 40

40

SMC_RESET_L

IN

WIFI_EVENT_L

BI

NC_SMC_HIB_L

NO_TEST=TRUE

SMC_CLK32K

IN

NC_SMC_XOSC1

NO_TEST=TRUE

SMC_EXTAL

40

SMC_XTAL

40

1

C4917

0.1UF

20%
10V

2

CERM
402

1

R4902

1M

5%
1/20W
MF
201

2

(OD)

SMC_WAKE_L

PP1V2_S5_SMC_VDDC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V

L4901

30-OHM-1.7A

1 2

0402

U4900

LM4FSXAH5BB

RST*

PK4/RTCCLK
WAKE*
HIB*

XOSC0
XOSC1

OSC0
OSC1

VBAT

D6

(2 OF 2)

OMIT_TABLE

VDD

VDDC

G10 C10

B11
N13
M12

M10

N10

G12

G13

K12

D7
E6
E8
E9

F10

J7
J9

J10

J1
J6

K13

BGA

SWCLK/TCK
SWDIO/TMS

SWO/TDO

VDDA

VREFA+
VREFA-

GNDA

GND

PP3V3_S5_SMC_VDDA

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V

A10
A11
B10

TDI

A2

NC

D3

D2
D1

C3

40 43 44 80

E3

A1
C7
D9
E5
F9
H5
H9
J5
J8
J11
K11

1

C4901

0.1UF

20%
10V

2

CERM
402

NC

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

PLACE_NEAR=U4900.A1:4MM

12

SMC_TCK
SMC_TMS
SMC_TDO
SMC_TDI

XW4900

1

C4920

0.01UF

10%
10V

2

X5R-CERM
0201

SM

7

40

41
7

40

41
7

40

41
7

40

41

1

2

7

40

12

C4921

1UF

10%

6.3V
X5R
402

D

C

B

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

A

If SMS interrupt is not used, pull up to SMC rail.

6 3

SYNC_MASTER=D1_SENSORS

PAGE TITLE

SMC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/20/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

49 OF 132

SHEET

39 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

ENET_ASF_GPIO

SMC Reset "Button", Supervisor & AVREF Supply

=PP3V3_S5_SMC

8

39 40

1

R5027

47

1 2

5%

1/20W

MF

201

Mac Mini: 5V

D

Mobiles: 3.42V

GND_SMC_AVSS

39 40 43 44 80

SMC_TPAD_RST_L

47

IN

SMC_ONOFF_L

7

39 40 47

IN

SMC_MANUAL_RST_L

OMIT

1

R5001

0

5%
1/10W
MF-LF
603

2

SILK_PART=SMC_RST

PLACE_SIDE=BOTTOM

MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.

NOTE: Internal pull-ups are to VIN, not V+.

PP3V42_G3H_SMC_SPVSR

MIN_LINE_WIDTH=0.4 mm

1

C5027

4.7UF

20%

6.3V

2

X5R

8

402

C5020

0.47UF

CERM-X5R

C5001

0.01UF

X5R-CERM

0201

MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.42V

=PPVIN_S5_SMCVREF

1

10%

6.3V
2

402

6
7

4

1

10%
10V

2

VREF-3.3V-VDET-3.0V

MR1*
MR2*

DELAY

GND

1

2

V+

(IPU)
(IPU)

U5010

DFN

SN0903048

CRITICAL

3

VIN

RESET*

REFOUT

THRM

PAD

9

NOSTUFF

C5025

CERM-X5R

Debug Power "Buttons"

SMC_ONOFF_L

603

1

0

5%

2

OMIT

1

R5015

0

PLACE_SIDE=TOP

5%
1/10W
MF-LF
603

2

SILK_PART=PWR_BTN

C

R5016

PLACE_SIDE=BOTTOM

SILK_PART=PWR_BTN

1/10W
MF-LF

OMIT

7

39 40 47

OUT

SMC Crystal Circuit

SMC_XTAL

39

SMC_EXTAL

39

1 2

1%

1/20W

MF

201

1

2

SMC_XTAL_R

CRITICAL

Y5010

SM-3.2X2.5MM

12.000MHZ-30PPM-10PF

C5010

12PF

5%
25V
NP0-C0G
0201

1 3

2 4

NCNC

OMIT_TABLE

R5010

2.49K

B

SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ

PART NUMBER

197S0486

QTY

XTAL,12MHZ,30PPM,10PF,3.2X2.5X0.7MM,90C

1

DESCRIPTION

REFERENCE DES

R5000

100K

5%
1/20W
MF
201

2

5

SMC_RESET_R_L

8

1

10UF

20%

6.3V
2

0402-1

=PPVCCIO_S0_SMC

8

40

SMC_VCCIO_CPU_DIV2

39

1

C5011

12PF

5%
25V

2

NP0-C0G
0201

R5028

0

1 2

5%

1/20W

MF

201

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V

1

C5026

0.1UF

10%
10V

2

X5R-CERM
0201

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V

CRITICAL

CRITICALY5010

SMC_BC_ACOK

MAKE_BASE=TRUE

NC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

NC_SMC_GPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_SSD_ISENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

SMC_MEM_ISENSE

MAKE_BASE=TRUE

SMC_VCCIO_ISENSE

MAKE_BASE=TRUE

SMC_AXG_VSENSE

MAKE_BASE=TRUE

SMC_CPU_SA_ISENSE

MAKE_BASE=TRUE

SMC_CPU_SA_VSENSE

MAKE_BASE=TRUE

SMC_LCD_PANEL_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_VSENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_AXG_ISENSE

MAKE_BASE=TRUE

NC_SMC_GPU_P1V35_ISENSE

MAKE_BASE=TRUE

NC_SMC_T25_ISENSE

MAKE_BASE=TRUE

NC_SMC_PCH_CORE_ISENSE

MAKE_BASE=TRUE

SMC_X29_ISENSE

MAKE_BASE=TRUE

SMC_TBT_ISENSE

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_BDV_BKL_PWM

MAKE_BASE=TRUE

SDCONN_STATE_CHANGE_SMC

MAKE_BASE=TRUE

=TBT_WAKE_L

R5012

22

1 2

1/20W

201

5%
MF

SMC_CLK32K

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

SMC_RESET_L

NOSTUFF

1000PF

39 40 43 44 80

1

R5097

100K

1%
1/20W
MF
201

2

1

R5096

100K

1%
1/20W
MF
201

2

1

10%
16V

2

X7R
201

7

39

C5028

=CHGR_ACOK

44 57

HISIDE_ISENSE_OC

39

SMC_ADC0

39

SMC_ADC1

39

SMC_ADC2

39

7

39 41 57

OUT

SMC_ADC3

39

SMC_ADC4

39

SMC_ADC5

39

SMC_ADC6

39

SMC_ADC7

39

SMC_ADC8

39

SMC_ADC9

39

SMC_ADC10

39

SMC_ADC11

39

SMC_ADC12

39

SMC_ADC13

39

SMC_ADC14

39

SMC_ADC15

39

SMC_ADC16

39

SMC_ADC17

39

SMC_ADC18

39

SMC_ADC19

39

SMC_ADC20

39

SMC_ADC21

39

SMC_ADC22

39

SMC_ADC23

39

SMBUS_SMC_4_ASF_SCL

39

SMBUS_SMC_4_ASF_SDA

39

BDV_BKL_PWM

39

SMC_PME_S4_DARK_L

39 40

PM_CLK32K_SUSCLK_R

18

IN

PLACE_NEAR=U1800.N14:5.1mm

HDMI HPD ESD PROTECTION

R5057

1K

IN

HDMI_HPD_L

7

36

1 2

5%

1/20W

MF

201

SMC_DP_HPD_L

MAKE_BASE=TRUE

BOM OPTION

S4 SMC WAKE SOURCES

IN

IN

=PSOC_WAKE_L

=BT_WAKE_L

47 39

36

39

SMC_SYS_LED

39

MEM_EVENT_L

39

SMC_ODD_DETECT

39

IR_RX_OUT_RC

39

39 40 56

43

43

44

44

44

43

44

44

44

43

43

43

80

80

80

80

43

80

IN

33

OUT

SMC_GFX_THROTTLE_L

39

SMC_GFX_OVERTEMP

39 40

SMC_T25_EN_L

39

SMC_GFX_OVERTEMP

39 40

SYS_TDM_ONEWIRE

39

ADC10 AND ADC11 ARE SHARED WITH COMPARATORS ON STACK BOARD

80

80

7

25

CPU_THRMTRIP_3V3

39 40

OUT

39

CRITICAL

MMBT3904LP-7

DFN1006-3

39

OUT

=PP3V3_S4_SMC

1

R5082

100K

5%
1/20W
MF
201

2

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

Q5058

11 39 61 72

20

8

25 36 40

Hall Effect pads

APN: 998-4692

OMIT_TABLE

HALL-EFFECT-SENSOR-MLB-D1

J5050

SM

1

NC NC

2
3
4 5

A

PART NUMBER

607-9320

639-3261 (J4 Hall effect board) reports to 607-9320

QTY

SUBASSY,PCBA HALL EFFECT,J4

1

DESCRIPTION

8
7
6

NCNC

=PP3V42_S3_HALL

SMC_LID_R

8

R5050

0

1 2

5%
1/16W
MF-LF

402

REFERENCE DES

J5050

1

C5050

0.001UF

10%
50V

2

X7R-CERM
0402

SMC_LID

CRITICAL

CRITICAL

39 40 47

BOM OPTION

BATLOW# ISOLATION

=PP3V3_S5_SMCBATLOW

8

1

R5040

100K

5%

1/20W

MF

201

2

SMC_BATLOW_L

39 66 18

IN

CRITICAL

Q5040

SSM3K15AMFVAPE

VESM

D

3

R5041

0

1 2

5%
1/16W
MF-LF

402

NOSTUFF

=PP3V3_SUS_SMC

1

GS

Internal 20K pull-up on PM_BATLOW_L in PCH.

PM_BATLOW_L

2

6 3

NC_ENET_ASF_GPIO

MAKE_BASE=TRUE

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NC_MEM_EVENT_L

MAKE_BASE=TRUE

NC_SMC_ODD_DETECT

MAKE_BASE=TRUE

NC_IR_RX_OUT_RC

MAKE_BASE=TRUE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

NC_T25_EN_L

MAKE_BASE=TRUE

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

NC_SYS_TDM_ONEWIRE

MAKE_BASE=TRUE

CPU_PROCHOT_L

BI

PM_THRMTRIP_L_R

OUT

PM_THRMTRIP_B_L

3

1

2

OUT

8

OUT

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

6

1

3

4

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

CRITICAL

D

Q5059

SSM6N15AFE

SOT563

2

S G

CRITICAL

D

Q5059

SSM6N15AFE

SOT563

5

S G

7

40

40

SMC_PECI_L

IN

SMC_PROCHOT

SMC_THRMTRIP

39

IN

39

IN

39

IN

39

IN

R5058

3.3K

1 2

5%
1/16W
MF-LF

402

CPU_THRMTRIP_3V3

39 40

SPI_DESCRIPTOR_OVERRIDE_L

25 39

SMC_ROMBOOT

7

41

SMC12 PECI SUPPORT

CRITICAL

Q5030

VESM

1

G S

SMC_PECI_L_R

OMIT

1

R5033

NOSTUFF

NONE
NONE
NONE
402

2

CPU_PECI_R

39

OUT

To SMC

SMC12 SPI SUPPORT

SERIES RESISTORS ARE NO STUFFED UNTIL THE TOPOLOGY OF 2 SPI MASTERS IS VERIFIED

R5032

0

1 2

5%

1/20W

MF

201

39

IN

39 40

IN

SSM3K15AMFVAPE

SPI_SMC_MISO

R5022

43

SPI_SMC_MOSI

SPI_SMC_CLK

SPI_SMC_CS_L SPI_MLB_CS_L

PM_THRMTRIP_L

SMC_OOB1_RX_L

7

37 39

SMC_OOB1_TX_L

7

37 39

SMC_PME_S4_DARK_L

39 40

SMC_ONOFF_L

7

39 40 47

G3_POWERON_L

39

SMC_LID

39 40 47

SMC_TX_L

7

39 41

SMC_RX_L

7

39 41

SMC_DEBUGPRT_TX_L

38 39

SMC_DEBUGPRT_RX_L

38 39

SMC_TMS

7

39 41

SMC_TDO

7

39 41

SMC_TDI

7

39 41

SMC_TCK

7

39 41

SMC_BIL_BUTTON_L

39

SMC_BC_ACOK

39 40 56

SMC_S5_PWRGD_VIN

39

SMS_INT_L

39 49

SMC_THRMTRIP

39 40

SMC_ADAPTER_EN

18 39 66

SMC_S4_WAKESRC_EN

39 66

SMC_DELAYED_PWRGD

35 39 66

SMC_PM_G2_EN

39 66

WIFI_EVENT_L

7

36 39

1 2

5%

1/20W

MF

201

R5024

15

1 2

5%

1/20W

MF

201

11 20 72

IN

R5067
R5068
R5069
R5070
R5072
R5071
R5073
R5074
R5075
R5076
R5077
R5078
R5079
R5080
R5081
R5087
R5092

NOSTUFF

NOSTUFF

R5093
R5094
R5095

1

R5088

1K

5%
1/20W
MF
201

2

R5086

R5085
R5090
R5091
R5098

R5089

SYNC_MASTER=D1_SENSORS

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

=PPVCCIO_S0_SMC

3

D

2

1

R5031

330

5%
1/20W
MF
201

2

R5034

43

1 2

5%

1/20W

MF

201

R5021

24

1 2

PLACE_NEAR=U6100.2:1MM

5%

1/20W

MF

201

PLACE_NEAR=U6100.5:1MM

R5023

15

1 2

PLACE_NEAR=U6100.6:1MM

5%

1/20W

MF

201

PLACE_NEAR=U6100.1:1MM

8

25 36 40

100K

1 2

100K

1 2

100K

1 2

10K

1 2

10K

1 2

100K

1 2

10K

1 2

100K

1 2

10K

1 2

100K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

10K

1 2

100K

1 2

100K

1 2

10K

1 2

100K

1 2

10K

1 2

10K

1 2

10K

1 2

100K

1 2

100K

1 2

100K

1 2

10K

1 2

SMC Support

Apple Inc.

From/To CPU/PCH

SPI_MLB_MISO

SPI_MLB_MOSI

SPI_MLB_CLK

39 40

=PP3V3_S4_SMC

5% 201MF

5% 201MF
5% 201MF
5%
5% 201MF
5% 201MF
5% 201MF
5% 201MF
5% 201
5% 201
5% MF
5% MF
5% MF 201
5% MF 201

5% 201MF
5% 201MF
5%
5% MF

5% 201MF

5% 201MF

5% 201MF

PP3V3_WLAN_F

7

36 80

8

40

CPU_PECI

=PP3V3_S5_SMC

8

NO STUFF

1/20W

NO STUFF

1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W

1/20W

5% 201MF

1/20W

5% 201MF

1/20W

1/20W

1/20W

1/20W

5% 201MF

SYNC_DATE=02/20/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

50 OF 132

SHEET

40 OF 80

124578

D

11 20 72

BI

41 50

OUT

41 50

OUT

41 50

OUT

41 50

OUT

MF 2015%

201MF

MF
MF

201
201

MF 2015%

201MF
201

C

B

A

SIZE

D

8 7 6 5 4 3

12

LPC+SPI Connector

D

=PP3V3_S5_LPCPLUS

8

=PP5V_S0_LPCPLUS

8

LPC_CLK33M_LPCPLUS

7

25 75

BI

LPC_AD<0>

7

17 39 75

BI

LPC_AD<2>

7

17 39 75

IN

LPC_AD<1>

7

17 39 75

OUT

LPC_AD<3>

7

17 39 75

IN

SPI_ALT_MOSI

7

41

OUT

LPCPLUS_GPIO

7

20

OUT

LPCPLUS_RESET_L

7

25

IN

SMC_TDO

7

39 40

OUT

TP_SMC_TRST_L

7

TP_SMC_MD1

7

SMC_TX_L

7

39 40

IN

LPCPLUS_CONN:YES

CRITICAL

J5100

DF40C-30DP-0.4V

M-ST-SM

31

32

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

33

34

SPI_ALT_MISO
LPC_FRAME_L

SPIROM_USE_MLB

PM_CLKRUN_L
SPI_ALT_CLK

SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
SMC_TMS

7

41

IN

7

17 39 75

BI

7

20 50

BI

7

18 39

OUT

7

41

IN

7

41

IN

7

17 39

BI

7

18 25 39

IN

7

39 40

OUT

7

39 40

OUT

7

39 40 57

OUT

7

40

OUT

7

39 40

OUT

7

39 40

OUT

D

C

998-4235

C

SPI Bus Series Termination

SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK

43

5%

PLACE_NEAR=R5125.2:5mm

402

SPI_ALT_CS_L

PLACE_NEAR=J5100.14:5mm
PLACE_NEAR=J5100.12:5mm
PLACE_NEAR=J5100.9:5mm
PLACE_NEAR=J5100.11:5mm

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_MLB_MISO

LPCPLUS_R:YES

1

R5128

24

5%
1/16W
MF-LF
402

2

1

R5127

43

5%
1/16W
MF-LF
402

2

LPCPLUS_R:YES

SPI_CS0_R_L

17 75

IN

B

17 75

PLACE_NEAR=U1800.AY1:5mm

17 75

17 75

IN

IN

OUT

SPI_CLK_R

SPI_MOSI_R

SPI_MISO

PLACE_NEAR=U1800.BA2:5mm

PLACE_NEAR=U1800.AV3:5mm

R5112

15

1 2

5%
1/16W
MF-LF

402

R5111

1 2

1/16W
MF-LF

402

R5110

15

1 2

1/16W

15

5%

MF-LF

402

5%

SPI_CS0_L

75

SPI_CLK

75

SPI_MOSI

75

R5123

24

1 2

5%
1/16W
MF-LF

402

R5122

1 2

PLACE_NEAR=U6100.2:5mm

43

5%

PLACE_NEAR=R5127.2:5mm

1/16W
MF-LF

402

1

R5126

43

5%
1/16W
MF-LF
402

2

LPCPLUS_R:YES

R5121

1 2

43

5%

PLACE_NEAR=R5126.2:5mm

1/16W
MF-LF

402

LPCPLUS_R:YES

1

R5125

43

5%
1/16W
MF-LF
402

2

R5120

1 2

1/16W
MF-LF

7

41

7

41

7

41

7

41

40 50

OUT

40 50

OUT

40 50

OUT

40 50

IN

B

A

SYNC_MASTER=D1_SENSORS

PAGE TITLE

LPC+SPI Debug Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=02/20/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

51 OF 132

SHEET

41 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

PCH SMBus "0" Connections

=PP3V3_S0_SMBUS_PCH

8

42

1

1

201

R5201

1K

1K

5%

5%

1/20W
MF

MF

201

2

2

=I2C_TBTRTR_SCL
=I2C_TBTRTR_SDA

TBT

U3600

(WRITE: 0XXX READ: 0XXX)

AUDIO

(WRITE: 0X34 READ: 0X35)

U6411

33

33

SMC

U4900

(MASTER)

SMB_0_S0_CLK
SMB_0_S0_DATA

AUDIO

(WRITE: 0X32 READ: 0X33)

U6410

SMC

U4900

(MASTER)

SMB_2_S3_CLK
SMB_2_S3_DATA =I2C_TPAD_SDA

AUDIO

(WRITE: 0XE0 READ: 0XE1)

(WRITE: 0X76 READ: 0X77)

U6400

AUDIO

U6750

(WRITE: 0X30/31 READ: 0X32/33)

49

49

Panther Point

U1800

(MASTER)

SMBUS_PCH_CLK

7

17 75

D

MAKE_BASE=TRUE

SMBUS_PCH_DATA

7

17 75

MAKE_BASE=TRUE

R5200

1/20W

VRef DACs

U3300

(Write: 0x98 Read: 0x99)

=I2C_VREFDACS_SCL

31

=I2C_VREFDACS_SDA

31

Margin Control

U3301

(Write: 0x30 Read: 0x31)

=I2C_PCA9557D_SCL

31

=I2C_PCA9557D_SDA

31

MIKEY

U6751

C

(WRITE: 0X72 READ: 0X73)

=I2C_MIKEY_SCL

54

=I2C_MIKEY_SDA

54

XDP Connectors

J2500 & J2550

(MASTER)

=SMBUS_XDP_SCL

24

=SMBUS_XDP_SDA

24

SMC "0" SMBus Connections

=PP3V3_S0_SMBUS_SMC_0_S0

8

R5250

4.7K

1/20W

77

SMBUS_SMC_0_S0_SCL

39

MAKE_BASE=TRUE

77

SMBUS_SMC_0_S0_SDA

39

MAKE_BASE=TRUE

SMC "2" SMBUS CONNECTIONS

NOTE: SMC RMT bus remains powered and may be active in S3 state

=PP3V3_S3_SMBUS_SMC_2_S3

8

R5270

1/20W

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMS

U5920

=I2C_SMC_SMS_SCL

=I2C_SMC_SMS_SDA

201

1

1

R5251

4.7K

5%

5%
1/20W
MF

MF

201

2

2

GPU Temp (Ext)

EMC1414-A: U5550

(Write: 0x98 Read: 0x99)

=SMBUS_GPUTHMSNS_SCL
=SMBUS_GPUTHMSNS_SDA

SMC

U4900

(MASTER)

45

45

SMB_5_CLK
SMB_5_DATA

Battery

Battery Manager - (Write: 0x16 Read: 0x17)

1

1

201

R5271

1K

1K

5%

5%
1/20W

MF

MF
201

2

2

Trackpad

(Write: 0x90 Read: 0x91)

J5800

=I2C_TPAD_SCL

SMC

U4900

47

47

(MASTER)

SMB_3_CLK
SMB_3_DATA

ALS

J3502

(Write: 0x72 Read: 0x73)

=I2C_ALS_SCL
=I2C_ALS_SDA

GYRO

(WRITE: 0XD0 READ: 0XD1)

U5940

=I2C_SMC_GYRO_SCL
=I2C_SMC_GYRO_SDA

32

32

Panther Point

U1800

(MASTER)

SML_PCH_0_CLK

49

49

17 75

MAKE_BASE=TRUE

SML_PCH_0_DATA

17 75

MAKE_BASE=TRUE

SMC "5" SMBUS CONNECTIONS

=PP3V42_G3H_SMBUS_SMC_5

8

R5280

2.0K

1/20W

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

MAKE_BASE=TRUE

SMC "3" SMBUS CONNECTIONS

=PP3V3_S3_SMBUS_SMC_3

8

DEBUG_ADC

R5290

4.7K

1/20W

77

SMBUS_SMC_3_SCL

39

MAKE_BASE=TRUE

77

SMBUS_SMC_3_SDA

39

MAKE_BASE=TRUE

PCH "SMLink 0" Connections

=PP3V3_S0_SMBUS_PCH

8

42

R5210

8.2K

1/20W

201

201

201

1

1

R5281

2.0K

5%

5%

1/20W

MF

MF
201

2

2

Battery Charger

ISL6258 - U7000

(Write: 0x12 Read: 0x13)

=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA

57

57

D

Battery

J6955

(See Table)

=SMBUS_BATT_SCL
=SMBUS_BATT_SDA

DEBUG_ADC

1

1

R5291

4.7K

5%

5%

1/20W
MF

MF

201

2

2

DEBUG SENSOR ADC A

(Write: 0x10 Read: 0x11)

UD000

=I2C_SMC_ADCS_SCL
=I2C_SMC_ADCS_SDA

1

1

R5211

8.2K

5%

5%

1/20W

MF

MF
201

2

2

56

56

C

HDMI Redriver (on RIO)

B

=I2C_HDMIRDRV_SCL
=I2C_HDMIRDRV_SDA

=I2C_BKL_1_SCL
=I2C_BKL_1_SDA

A

J4410

(WRITE: 0xCC READ: 0xCD)

LED BACKLIGHT

U9700

(WRITE: 0X58 READ: 0X59)

36

36

SMC

U4900

(MASTER)

71

71

PCH "SMLink 1" Connections

SMB_1_S0_CLK
SMB_1_S0_DATA

SMC "1" SMBUS CONNECTIONS

=PP3V3_S0_SMBUS_SMC_1_S0

8

R5260

1/20W

SMBUS_SMC_1_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

201

1

1

R5261

1K

1K

5%

5%

1/20W
MF

MF

201

2

2

Panther Point

(Write: 0x88 Read: 0x89)

SMLink 1 is slave port to
access PCH & CPU via PECI.

U1800

SML_PCH_1_CLK

17 75

SML_PCH_1_DATA

17 75

SPKR TEMP

(WRITE: 0XD8 READ: 0XD9)

(WRITE: 0X38 READ: 0X39)

U6420

U6421

=I2C_SPKRTHMSNS_SCL

=I2C_SPKRTHMSNS_SDA

6 3

CPU/DDR3/PCH/AIRFLOW TEMP

EMC1414-A: U5570

(Write: 0x98 Read: 0x99)

=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA

X29 TEMP

TMP105: U5523

(WRITE: 0X92 READ: 0X93)

=I2C_X29THMSNS_SCL
=I2C_X29THMSNS_SDA

45

45

36

36

SYNC_MASTER=MASTER

PAGE TITLE

SMBus Connections

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

52 OF 132

SHEET

42 OF 80

124578

SIZE

B

A

D

8 7 6 5 4 3

CPU/PCH VCCIO & TBT 1.05V Load Side Current Sense (IC1C)

Gain: 200x, EDP: 20 A
Rsense: 0.001 (R7640)
V across Rsense: 15 mV
SMC ADC: 11

=PP3V3_S0_ISNS

8

80

D

CPUVCCIOS0_CS_N

63 78

IN

PLACE_NEAR=R7640.3:5MM

CPUVCCIOS0_CS_P

63 78

IN

PLACE_NEAR=R7640.4:5MM

CRITICAL

DDR 1.35V S3 (Memory) Current Sense (IM0C)

Gain: 364.9x, EDP: 9 A
Rsense: 0.001 (R5370)
V across Rsense: 9 mV
SMC ADC: 10

=PPVIN_S3_MEM_ISNS_R

8

IN

123

R5370

0.001

1%
1W

C

=PPVIN_S3_MEM_ISNS

8

OUT

B

A

8

10 13 16

MF-1
0612

4

78

SSD Current Sense (ISDC)

Gain: 649.35x, EDP: 5 A (16.5 W)
Rsense: 0.001 (R5370)
V across Rsense: 5 mV
SMC ADC: 06

37 78

IN

37 78

IN

CPU Core Voltage Sense (VC0C)

Gain: 1x
SMC ADC: 00

=PPVCORE_S0_CPU

8

10 13 15

AXG Core Voltage Sense (VN0C)

Gain: 1x
SMC ADC: 12

=PPVCORE_S0_CPU_VCCAXG

5

4

LOADISNS:YES

ISNS_1V35_S3_MEM_P

ISNS_1V35_S3_MEM_N

ISNS_SSD_P

ISNS_SSD_N

PLACE_NEAR=R7550.2:5 MM

3

V+

U5360

INA210

SC70

IN-

GND

2

R5371

2.74K

1 2

R5372

2.74K

1 2

R5381

1.54K

1 2

R5382

1.54K

1 2

PLACE_NEAR=R7510.2:5 MM

XW5320

SM

1 2

XW5330

SM

1 2

6

OUT

1

REFIN+

78

1%
1/16W
MF-LF

402

78

1%
1/16W
MF-LF

402

78

1%
1/20W

MF

201

78

1%
1/20W

MF

201

CPUVSENSE_IN

AXGVSENSE_IN

1

C5360

0.1uF

20%
10V

2

CERM
402

LOADISNS:YES

CPUVCCIO_IOUT

LOADISNS:YES

PLACE_NEAR=U4900.A6:5MM

=PP3V3_S3_ISNS

8

43

ISNS_1V35_S3_MEM_R_P

ISNS_1V35_S3_MEM_R_N

1

R5373

1M

1%
1/16W
MF-LF
402

2

=PP3V3_S3_ISNS

8

43

ISNS_3V3_S0_SSD_R_P

ISNS_3V3_S0_SSD_R_N

1

R5383

1M

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U4900.E2:5MM

R5329

4.53K

1 2

1%

1/20W

MF

201

PLACE_NEAR=U4900.C1:5MM

R5339

4.53K

1 2

1%

1/20W

MF

201

R5369

4.53K

1 2

1/20W

201

1%
MF

SMC_VCCIO_ISENSE

1

C5369

2

GND_SMC_AVSS

CRITICAL

U5370

OPA2330

8

3

2

NO_XNET_CONNECTION=TRUE

5

6

NO_XNET_CONNECTION=TRUE

1

2

DFN

V+

1

V-

THRM

4

9

R5374

1M

1 2

1%
1/16W
MF-LF

402

CRITICAL

U5370

OPA2330

8

DFN

V+

7

V-

THRM

4

9

R5384

1M

1 2

1%
1/16W
MF-LF

402

SMC_CPU_VSENSE

PLACE_NEAR=U4900.E2:5MM

C5329

0.22UF

20%

6.3V
X5R
0201

GND_SMC_AVSS

SMC_AXG_VSENSE

PLACE_NEAR=U4900.C1:5MM

1

C5339

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

0.22UF

20%

6.3V
X5R
0201

LOADISNS:YES

PLACE_NEAR=U4900.A6:5MM

ISNS_1V35_S3_MEM_IOUT

PLACE_NEAR=U4900.B6:5MM

ISNS_3V3_S0_SSD_IOUT

PLACE_NEAR=U4900.B4:5MM

OUT

OUT

OUT

PLACE_NEAR=U5370.8:3MM

1

C5370

0.1UF

20%
10V

2

CERM
402

R5379

4.53K

1 2

1%

1/20W

MF

201

R5389

4.53K

1 2

1%

1/20W

MF

201

40

39 40 43 44 80

40

39 40 43 44 80

40

39 40 43 44 80

SMC_MEM_ISENSE

1

C5379

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.B6:5MM

GND_SMC_AVSS

SMC_SSD_ISENSE

1

C5389

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.B4:5MM

GND_SMC_AVSS

OUT

OUT

40

39 40 43 44 80

40

39 40 43 44 80

CPUIMVP_ISNS1_P

61 62 78

IN

PLACE_NEAR=R7510.4:5MM

LOADISNS:YES

CPUIMVP_ISNS2_P

61 62 78

IN

PLACE_NEAR=R7520.3:5MM

LOADISNS:YES

CPUIMVP_ISNS1_N

62 78

IN

PLACE_NEAR=R7510.3:5MM

LOADISNS:YES

CPUIMVP_ISNS2_N

62 78

IN

PLACE_NEAR=R7520.4:5MM

LOADISNS:YES

CPUIMVP_ISNS1G_P

62 78

IN

PLACE_NEAR=R7550.3:5MM

LOADISNS:YES

CPUIMVP_ISNS2G_P

62 78

IN

PLACE_NEAR=R7560.3:5MM

LOADISNS:YES

CPUIMVP_ISNS1G_N

62 78

IN

PLACE_NEAR=R7550.4:5MM

LOADISNS:YES

CPUIMVP_ISNS2G_N

62 78

IN

PLACE_NEAR=R7560.4:5MM

LOADISNS:YES

CPU Core Load Side Current Sense (IC0C)

Gain: 161.7x, EDP: 53 A
Rsense: 2x of 0.00075 (R7510, R7520), Rsum: 0.000375
V across Rsense: 19.8 mV
SMC ADC: 01

NO_XNET_CONNECTION=TRUE

R5345

4.42K

1 2

0.1%

1/16W

MF

NO_XNET_CONNECTION=TRUE

0402

R5346

4.42K

1 2

1/16W

R5347

4.42K

1 2

1/16W

R5348

4.42K

1 2

1/16W

R5355

4.42K

1 2

1/16W

R5356

4.42K

1 2

1/16W

R5357

4.42K

1 2

1/16W

R5358

4.42K

1 2

1/16W

CPUIMVP_ISNS_P

78

0.1%
MF

NO_XNET_CONNECTION=TRUE

0402

CPUIMVP_ISNS_N

78

0.1%
MF

NO_XNET_CONNECTION=TRUE

0402

0.1%
MF

0402

AXG Core Load Side Current Sense (IN0C)

Gain: 190.6x, EDP: 46 A
Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375
V across Rsense: 17.25 mV
SMC ADC: 18

NO_XNET_CONNECTION=TRUE

0.1%
MF

NO_XNET_CONNECTION=TRUE

0402

CPUIMVP_ISNSG_P

78

0.1%
MF

NO_XNET_CONNECTION=TRUE

0402

CPUIMVP_ISNSG_N

78

0.1%
MF

NO_XNET_CONNECTION=TRUE

0402

0.1%
MF

0402

PART NUMBER

117S0008

LOADISNS:YES

R5342

2.21K

1 2

0.1%

1/16W

MF

0402

R5343

2.21K

1 2

0.1%

1/16W

MF

LOADISNS:YES

0402

LOADISNS:YES

R5352

1.54K

1 2

1%
1/16W
MF-LF

402

R5353

1.54K

1 2

1%
1/16W
MF-LF

LOADISNS:YES

402

QTY

3

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

CPUIMVP_ISUM_R_P

78

CPUIMVP_ISUM_R_N

78

1

R5344

715K

2

CPUIMVP_ISUMG_R_P

78

CPUIMVP_ISUMG_R_N

78

1

R5354

715K

2

DESCRIPTION

=PP3V3_S0_IMVPISNS

8

43

0.1%
1/16W
MF
402

LOADISNS:YES

NO_XNET_CONNECTION=TRUE

=PP3V3_S0_IMVPISNS

8

43

0.1%
1/16W
MF
402

LOADISNS:YES

NO_XNET_CONNECTION=TRUE

U5340

5

ISL28133

V+

V-

2

R5341

715K

1 2

0.1%

1/16W

MF

402

5

V+

V-

2

R5351

715K

1 2

0.1%

1/16W

MF

402

SC70-5

U5350

ISL28133

SC70-5

1

3

NO_XNET_CONNECTION=TRUE

1

3

NO_XNET_CONNECTION=TRUE

REFERENCE DES

C5349,C5359,C5369

LOADISNS:YES
CRITICAL

4

CPUIMVP_ISUM_IOUT

LOADISNS:YES

PLACE_NEAR=U4900.E1:5MM

LOADISNS:YES

NO_XNET_CONNECTION=TRUE

LOADISNS:YES
CRITICAL

4

CPUIMVP_ISUMG_IOUT

LOADISNS:YES

PLACE_NEAR=U4900.H1:5MM

LOADISNS:YES

NO_XNET_CONNECTION=TRUE

LOADISNS:YES

PLACE_NEAR=U5340.5:3MM

1

C5340

0.1UF

20%
10V

2

CERM
402

R5349

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_ISENSE

1

C5349

0.22UF

20%

6.3V

2

X5R
0201

LOADISNS:YES

PLACE_NEAR=U4900.E1:5MM

GND_SMC_AVSS

LOADISNS:YES

PLACE_NEAR=U5350.5:3MM

1

C5350

0.1UF

20%
10V

2

CERM
402

R5359

4.53K

1 2

1%

1/20W

MF

201

SMC_AXG_ISENSE

1

C5359

0.22UF

20%

6.3V

2

X5R
0201

LOADISNS:YES

PLACE_NEAR=U4900.H1:5MM

GND_SMC_AVSS

CRITICAL

SYNC_MASTER=D1_SENSORS

PAGE TITLE

BOM OPTION

LOADISNS:NO

Power Sensor: Load Side

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

12

40

OUT

39 40 43 44 80

40

OUT

39 40 43 44 80

SYNC_DATE=02/20/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

PAGE

53 OF 132

SHEET

124578

<BRANCH>

43 OF 80

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

CPU High Side Current Sense (IC0R)

Gain: 50x, EDP: 17.4 A
Rsense: 0.003 (R5400)
V across Rsense: 52.2 mV
SMC ADC: 08

D

C

=PPVIN_S5_HS_COMPUTING_ISNS

8

OUT

CRITICAL

=PPVIN_S5_HS_COMPUTING_ISNS_R

8

IN

OTHER High Side Current Sense (IO0R)

Gain: 100x, EDP: 8.8 A
Rsense: 0.003 (R5410)
V across Rsense: 26.4 mV
SMC ADC: 09

=PPVIN_S5_HS_OTHER_ISNS

8

OUT

=PPVIN_S5_HS_OTHER_ISNS_R

8

IN

CRITICAL

Charger (BMON Production) Current Sense (IPBR)

Charger Gain: 36x, EDP: 6.6 A
Rsense: 0.010 (R7050)
SMC ADC: 07

0612

0.003

R5400

0612

0.003

R5410

PLACE_NEAR=U5400.4:10MM

4

ISNS_HS_COMPUTING_N

78

MF
1W
1%

ISNS_HS_COMPUTING_P

78

123

PLACE_NEAR=U5400.5:10MM

PLACE_NEAR=U5410.4:10MM

4

ISNS_HS_OTHER_N

78

MF
1W
1%

ISNS_HS_OTHER_P

78

123

PLACE_NEAR=U5410.5:10MM

CHGR_BMON

57

IN

B

DC-In (AMON) Current Sense (ID0R)

Charger Gain: 20x, EDP: 4.6 A
Rsense: 0.020 (R7020)
SMC ADC: 04

=PP3V3_S0_HS_COMPUTING_ISNS

8

3
V+

U5400

INA214

5

SC70

IN-

CRITICAL

4

IN+ REF

GND

2

=PP3V3_S0_HS_OTHER_ISNS

8

3

V+

U5410

INA214

5

SC70

IN-

4

IN+ REF

GND

1%
MF

2

SMC_BMON_ISENSE

1

C5429

3300PF

10%
10V

2

X7R-CERM
0201

PLACE_NEAR=U4900.A4:5MM

CRITICAL

PLACE_NEAR=U4900.A4:5MM

R5429

300K

1 2

1/20W

201

GND_SMC_AVSS

OUT

OUT

6

1

6

1

1

C5401

0.1UF

20%
10V

2

CERM
402

HS_COMPUTING_IOUT

PLACE_NEAR=U4900.B5:5MM

1

C5411

0.1UF

20%
10V

2

CERM
402

HS_OTHER_IOUT

PLACE_NEAR=U4900.A5:5MM

40

OUT

39 40 43 44 80

R5409

4.53K

1 2

1%

1/20W

MF

201

R5419

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_HI_ISENSE

1

C5409

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.B5:5MM

GND_SMC_AVSS

SMC_OTHER_HI_ISENSE

1

C5419

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.A5:5MM

GND_SMC_AVSS

40 66

OUT

39 40 43 44 80

=PPBUS_S0_VSENSE

8

OUT

40

39 40 43 44 80

40 57

IN

66

IN

PLACE_NEAR=R5400.1:10 MM

=CHGR_ACOK

PM_SUS_EN

PBUS Voltage Sense & Enable (VP0R)

Gain: 0.167x
SMC ADC: 05

CRITICAL

Q5480

NTUD3169CZ

SOT-963

IN

XW5480

SM

1 2

Enables PBUS VSense
divider when in S0.

=PBUSVSENS_EN

PBUS_S0_VSENSE_IN

R5481

100K

1/16W
MF-LF

402

N-CHANNEL

G

2

1

G

5

4

1

1%

2

P-CHANNEL

6

D

S

3

D

S

PBUSVSENS_EN_L_DIV

DC In Voltage Sense & Enable (VD0R)

Gain: 0.167x
SMC ADC: 03

CRITICAL

Enables DC-In VSense
divider when AC present.

R5493

0

NOSTUFF

1 2

5%

1/20W

MF

201

R5494

0

1 2

5%

1/20W

MF

201

=PPDCIN_S5_VSENSE

8

DCIN_VSENSE_EN

1

R5491

100K

1%
1/16W
MF-LF

402

2

Q5490

NTUD3169CZ

SOT-963

N-CHANNEL

G

2

1

G

5

4

P-CHANNEL

6

D

S

3

D

S

PDCINVSENS_EN_L_DIV

PBUSVSENS_EN_L

R5482

PBUS_S0_VSENSE

DCINVSENS_EN_L

R5492

DCIN_S5_VSENSE

100K

1/16W
MF-LF

100K

1/16W
MF-LF

402

402

1

1%

2

1

1%

2

PLACE_NEAR=U4900.A3:5MM

1

R5488

27.4K

1%
1/16W
MF-LF

Rthevenin = 4573 Ohms

402

2

1

R5489

5.49K

1/16W
MF-LF

PLACE_NEAR=U4900.A3:5MM

PLACE_NEAR=U4900.F1:5MM

R5498

27.4K

1/16W
MF-LF

R5499

5.49K

1/16W
MF-LF

PLACE_NEAR=U4900.F1:5MM

1%

402

2

1

1%

Rthevenin = 4573 Ohms

402

2

1

1%

402

2

1

2

1

2

SMC_PBUS_VSENSE

PLACE_NEAR=U4900.A3:5MM

C5489

0.22UF

20%

6.3V
X5R
0201

GND_SMC_AVSS

SMC_DCIN_VSENSE

PLACE_NEAR=U4900.F1:5MM

C5499

0.22UF

20%

6.3V
X5R
0201

GND_SMC_AVSS

OUT

OUT

D

40

39 40 43 44 80

C

B

40

39 40 43 44 80

PLACE_NEAR=U4900.B3:5MM

R5439

45.3K

57

IN

CHGR_AMON

1 2

1/20W

A

201

1%
MF

SMC_DCIN_ISENSE

1

C5439

2200PF

10%
10V

2

X7R-CERM
0201

PLACE_NEAR=U4900.B3:5MM

GND_SMC_AVSS

40

OUT

39 40 43 44 80

6 3

SYNC_MASTER=D1_SENSORS

PAGE TITLE

Power Sensor: High Side

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=02/20/2012

<SCH_NUM>

<E4LABEL>

<BRANCH>

54 OF 132

44 OF 80

SIZE

A

D

8 7 6 5 4 3

12

Thermal Sensor A:
PCH Proximity, Left Fin Pipe, Right Fin Stack

I2C Write: 0x98, I2C Read: 0x99

R5550

47

=PP3V3_S0_GPUTHMSNS

8

D

Thermal Diode: None

Placement Note:
None.

GPUTHMSNS_D_P

78

Q5501

BC846BLP

DFN1006H4-3

Thermal Diode: Left Fin Stack (Th1H)

Placement Note:
Place Q5501 on the top side on the corner
close to the Left Fin Stack.

2

CRITICAL

1

3

GPUTHMSNS_D_N

78

GPU_TDIODE_P

78

GPU_TDIODE_N

78

3

CRITICAL

2

1

Q5503

BC846BLP

DFN1006H4-3

Thermal Diode: Right Heat Pipe (Th2H)

Placement Note:
Place Q5503 under the top side on the corner
close to the Right Fin Stack.

1 2

1/16W
MF-LF

402

PLACE_NEAR=U5550.2:5mm

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

0.0022uF

PLACE_NEAR=U5550.3:5mm

PLACE_NEAR=U5550.4:5mm

0.0022uF

PLACE_NEAR=U5550.5:5mm

PP3V3_S0_GPUTHMSNS_R

MIN_LINE_WIDTH=0.38 mm

5%

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C5551

10%
50V

2

CERM

402

1

C5552

10%
50V

2

CERM

402

U5550

EMC1414-A-AIA

2

DP1

DN1

4

DP2/DN3

5

DN2/DP3

GND
6

1

C5550

1
VDD

DFN

THERM*/ADDR

ALERT*

SMDATA

SMCLK

THRM_PAD

11

0.1uF

20%
10V

2

CERM
402

7

GPUTHMSNS_THM_L

83

GPUTHMSNS_ALERT_L

9

=SMBUS_GPUTHMSNS_SDA

10

=SMBUS_GPUTHMSNS_SCL

R5551

10K

1/16W
MF-LF

402

1

5%

2

Thermal Sensor: PCH Proximity (TP0P)

Placement Note:
Place U5550 on top side on top
of PCH.

1

R5552

10K

5%
1/16W
MF-LF
402

2

D

42

BI

42

BI

C

C

Thermal Sensor B:
CPU Proximity, Memory Proximity, Airflow

I2C Write: 0x98, I2C Read: 0x99

R5570

47

=PP3V3_S0_CPUTHMSNS

8

DDR3THMSNS_D1_P

Thermal Diode: Memory Proximity (TM0P)

Placement Note:
Place Q5506 on the bottom side, below the
row of Memory device, between 2nd/3rd device.

78

Q5502

BC846BLP

DFN1006H4-3

B

2

CRITICAL

1

3

CPUTHMSNS_D2_P

78

CPUTHMSNS_D2_N

Thermal Diode: Airflow (TA0P)

Placement Note: Placement Note:
Place Q5502 on the bottom side, below left
underneath the left fan well in the neck.

Q5506

BC846BLP

DFN1006H4-3

Q5504

BC846BLP

DFN1006H4-3

Thermal Diode: Airflow (TA1P)

Place Q5504 on the either side,
near LCD connector and DCIN connector.

3

2

3

CRITICAL

2

78

CRITICAL

78

1

1

DDR3THMSNS_D1_N

1 2

1/16W
MF-LF

402

PLACE_NEAR=U5570.2:5mm

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

0.0022uF

PLACE_NEAR=U5570.3:5mm

PLACE_NEAR=U5570.4:5mm

0.0022uF

PLACE_NEAR=U5570.5:5mm

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm

5%

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C5571

10%
50V

2

CERM

402

1

C5590

10%
50V

2

CERM

402

U5570

EMC1414-A-AIA

2

DP1

DN1

4

DP2/DN3

5

DN2/DP3

GND
6

1

C5570

0.1uF

1
VDD

DFN

THERM*/ADDR

ALERT*

SMDATA

SMCLK

THRM_PAD

11

20%
10V

2

CERM
402

7

CPUTHMSNS_THM_L

83

CPUTHMSNS_ALERT_L

9

=I2C_CPUTHMSNS_SDA

10

=I2C_CPUTHMSNS_SCL

R5571

10K

1/16W
MF-LF

402

1

5%

2

Thermal Sensor: CPU Proximity (Tc0P)

Placement Note:
Place U5570 on top side, on top of
the CPU.

1

R5572

10K

5%
1/16W
MF-LF
402

2

42

BI

42

BI

B

Thermal Sensor: T29 Die

TP_TBT_THERM_DP

33

BI

A

1 2

XW5520

SM

PLACE_NEAR=U3600.B1:2mm

Note: Use GND pin B1 on U3600 for N leg.

TBT_THERMD_P

78

MAKE_BASE=TRUE

1

R5520

10K

5%
1/16W
MF-LF
402

TBT_THERMD_N

78

2

NOSTUFF

PLACE_SIDE=TOP

6 3

SYNC_MASTER=D1_SENSORS

PAGE TITLE

Thermal Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/20/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

55 OF 132

SHEET

45 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

=PP5V_S0_FAN_LT

8

=PP3V3_S0_FAN_LT

8

SMC_FAN_0_TACH

39 39

OUT OUT

R5651

100K

5%
1/16W
MF-LF

402

39

IN

1

2

Left Fan

R5655

47K

1 2

5%
1/16W
MF-LF

402

5

G

S D

4

FAN_LT_TACH

7

Q5660

2N7002DW-X-G

SOT-363

3

FAN_LT_PWM

7

R5650

1/16W
MF-LF

47K

Right Fan

=PP5V_S0_FAN_RT

8

=PP3V3_S0_FAN_RT

8

1

5%

402

2

CRITICAL

J5650

FF14A-5C-R11DL-B-3H

F-RT-SM

6

NC

1
2
3
4
5

NC NC

7

NC

39

SMC_FAN_1_TACH

SMC_FAN_1_CTLSMC_FAN_0_CTL

IN

R5661

100K

1/16W
MF-LF

1

5%

402

2

S D

1

2

G

R5665

47K

1 2

5%
1/16W
MF-LF

402

Q5660

2N7002DW-X-G

SOT-363

6

FAN_RT_TACH

7

FAN_RT_PWM

7

R5660

1/16W
MF-LF

47K

1

5%

402

2

CRITICAL

J5660

FF14A-5C-R11DL-B-3H

F-RT-SM

6

NC

1
2
3
4
5

7

NC

518S0769518S0769

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=J5_MLB

PAGE TITLE

Fan Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

56 OF 132

SHEET

46 OF 80

124578

8 7 6 5 4 3

12

D

C

B

A

PSOC USB CONTROLLER

PLACE_SIDE=BOTTOM

=PP3V3_S4_TPAD

8

47

=PSOC_WAKE_L

40

OUT

PICKB_L

7

47

BUTTON_DISABLE

47

Z2_HOST_INTN

7

47

WS_LEFT_SHIFT_KEY

47

WS_LEFT_OPTION_KEY

47

WS_CONTROL_KEY

47

Z2_KEY_ACT_L

7

47

TPAD_VBUS_EN

66

IN

PSOC_MISO

7

47

PSOC_F_CS_L

7

47

PSOC_MOSI

7

47

PSOC_SCLK

7

47

Z2_MISO

7

47

Z2_CS_L

7

47

Z2_MOSI

7

47

Z2_SCLK

7

47

TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
TP_ISSP_SCLK_P1_1

ISSP SCLK/I2C SCL

USB_TPAD_P

9

74

USB_TPAD_N

9

74

IC

TMP102

3V3 LDO

PSOC

18V BOOSTER

BOM Options available to CSA 5

TPAD_5V:S4 Original implementation off PP5V_S4
TPAD_5V:LDO_S4 PP5V_S5 LDO power in S4 only
TPAD_5V:LDO_S5 PP5V_S5 LDO power

59 66

IN

PIN NAME

TPAD_5V_FET:YES

=P5VS4_EN

V+

VDD
VOUT

VDD

VIN

Q5721

SSM3K15FV

SOD-VESM-HF

1

G S

R5704

1.5

2 1

R5701

1 2

1/20W

R5702

1 2

1/20W

CURRENT

10UA
80UA

60MA (MAX)
60MA (MAX)

8MA (TYP)
14MA (MAX)

4MA (MAX)

5%
1/16W
MF-LF

402

NC

NC
NC

24

5%
MF

201

24

5%
MF

201

R5703

78
26

78
26

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

PP3V3_S3_PSOC

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

1

220K

5%

1/20W

MF

201

2

P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1

USB_TPAD_R_P

USB_TPAD_R_N

R_SNS V_SNS

All RC values are TBD

=PP5V_S5_TPAD

8

TPAD_5V_FET:YES

3

D

2

1

R5721

220K

5%

1/20W

MF

201

2

P5VCUMULUS_EN_L

- USB INTERFACES TO MLB

- SPI HOST TO Z2

- TRACKPAD PICK BUTTONS

- KEYBOARD SCANNER

BYPASS=U5701.49:50:5 mm

1

2

51

P0_3

P0_5

P0_1

CY8C24794

50

VDD

VSS

P0_7

CRITICAL

OMIT

U5701

MLF

(SYM-VER2)

P0_4

P0_6

55

P2_5

P2_7

337S2983

P7_0

P7_7

VSS

VDD

P1_1

P1_3

P1_5

P1_7

15

5V TRACKPAD S4 FET

D+

D-

20

21

19

0.0255 V

0.204 V

0.6 V

0.012 V

0.012 V

0.021 V

0.0188 V

TPAD_5V_FET:YES

TPAD_5V_FET:YES

R5722

3.3K

1 2

1/20W

201

24

235722 49

1

C5702

100PF

5%
25V

2

NP0-CERM
0201

BYPASS=U5701.22:19:5 mm

0.255E-6 W

16.32E-6 W

0.72E-3 W

75.2E-6 W

C5722

0.033UF

10%
16V
X5R
402

5%
MF

C5704

100PF

5%
25V
NP0-CERM
0201

45544653475248

435644

P2_4

P2_6

P0_2

P0_0

P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0

THRML

P1_0

P1_2

P1_4

P1_6

25182617271628

TP_ISSP_SDATA_P1_0

ISSP SDATA/I2C SDA

1

2

BYPASS=U5701.22:19:8 mm

POWER

36E-3 W

96E-6 W

294E-6 W

1

2

P5VCUMULUS_SS

BYPASS=U5701.49:50:8 mm

1

C5705

0.1UF

10%

6.3V

2

X5R
201

BYPASS=U5701.49:50:11 mm

1

2

WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18

421

WS_KBD17

412

WS_KBD16N

403

WS_KBD15_C

394

WS_KBD14

385

WS_KBD13

376

WS_KBD12

367

WS_KBD11

358

WS_KBD10

349

WS_KBD9

3310

WS_KBD8

3211

WS_KBD7

3112

WS_KBD1

3013

WS_KBD2

2914

WS_KBD3

C5706

4.7UF

20%

6.3V
X5R
402

PAD

WS_KBD4
WS_KBD5
WS_KBD6

Z2_CLKIN
TP_P7_7

(PP3V3_S3_PSOC)

C5703

0.1UF

10%

6.3V
X5R
201

TPAD_5V_FET:NO

R5720

1 2

TPAD_5V_FET:YES

SIA413DJ

4 7

1

C5701

4.7UF

20%

6.3V

2

X5R
402

BYPASS=U5701.22:19:11 mm

0

5%
1/16W
MF-LF

402

CRITICAL

Q5720

SC70-6L

S

D

G

TPAD_5V_FET:YES

3

C5723

0.01UF

1 2

10%
10V
X5R
201

47

39 40

1

PP5V_S5RS4_CUMULUS

6 3

7

47

7

47

7

47

7

47

7

47

7

47

7

47

47

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

BUTTON_DISABLE

Q5701

SSM6N37FEAPE

IN

SOT563

SMC_LID

5V TPAD FET

MOSFET

CHANNEL

RDS(ON)

LOADING

VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM

6

D

2

SG

1

SiA413

P-TYPE 12V

29 mOhm @4.5V

16 mA (EDP)

47

BOM GROUP
TPAD_5V_LDO:S4
TPAD_5V_LDO:S5

=PP3V3_S4_TPAD

8

47

=PP5V_S4_TPAD

8

FERR-120-OHM-1.5A

PP5V_S5RS4_CUMULUS

47

www.qdzbwx.com

TPAD Buttons Disable

PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED

LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V

PLACE_NEAR=J5700.18:3MM

FERR-120-OHM-1.5A

TPAD_5V:S4

1

C5700

0.1UF

10%

PLACE_NEAR=J5700.18:3MM

10V

2

X5R-CERM
0201

TPAD_5V:S5

PLACE_NEAR=J5700.18:3MM

L5707

1 2

0402-LF

TPAD_5V:S5

1

C5707

0.1UF

10%

PLACE_NEAR=J5700.18:3MM

10V

2

X5R-CERM
0201

47

47

47

47

R5708

0

1 2

5%

1/20W

MF

201

TPAD_5V:S4

NOSTUFF

1

C5708

0.1UF

10%

6.3V

2

X5R
201

L5700

1 2

0402-LF

47

=PP3V3_S4_TPAD

8

WS_LEFT_SHIFT_KBD

7

WS_LEFT_OPTION_KBD

7

WS_CONTROL_KBD

7

=PP3V3_S4_TPAD

8

47

WS_KBD15_C

47

WS_KBD15_C

Z
1
0

TPAD_5V_FET:YES,TPAD_5V:S5

CAP_COMP_H CAP_COMP_L

BOM OPTIONS

TPAD_5V_FET:NO,TPAD_5V:S5

7

=PP3V42_G3H_TPAD

8

4

OE

(IPD)

1

IN_1

(IPD)

2

IN_2

(IPD)

3

IN_3

(IPD)

CAPS:EXT

1

R5730

10K

5%
1/20W
MF
201

2

CAPS:EXT

1

R5731

10K

5%
1/20W
MF
201

2

Caps Lock LED Drive

1
0
1

IPD Flex Connector

PP3V3_TPAD_CONN

VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM

PP5V_S4_CUMULUS

VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM

10

VDD

U5750

SLG4AP021

TQFN

THRM

GND

PAD

5

CAPS:EXT

1

R5732

10K

5%
1/20W
MF
201

2

CAPS:EXT

1

R5733

20K

5%
1/20W
MF
201

2

Q5736 Q5738

1
1
0

off

off

on

47

42

42

47

47

47

47

47

47

47

47

47

47

47

11

CAPS:EXT

1

R5734

20K

5%
1/20W
MF
201

2

CAP_VREF_L

CAP_VREF_H

CAPS:EXT

1

R5735

10K

5%
1/20W
MF
201

2

Z2_CLKIN

7

=I2C_TPAD_SCL

=I2C_TPAD_SDA

PSOC_SCLK

7

PSOC_MOSI

7

Z2_SCLK

7

PSOC_MISO

7

Z2_MISO

7

Z2_MOSI

7

PSOC_F_CS_L

7

Z2_CS_L

7

Z2_KEY_ACT_L

7

PICKB_L

7

Z2_HOST_INTN

7

OUT_1

OUT_2

OUT_3

OUT_ALL#

off
off

on

FF14-18C-R11DL

1

R5700

220K

5%

1/20W

MF

201

2

1

C5750

0.1UF

10%
16V

2

X7R-CERM
0402

9

WS_LEFT_SHIFT_KEY

8

WS_LEFT_OPTION_KEY

7

WS_CONTROL_KEY

Pull-up in U5010.

6

SMC_TPAD_RST_L

CAPS:EXT

R5740

CAPS:EXT

V+

U5730

LM393ADGKR

MSOP

6
5

2
3

GND

4

LED Current

none

source

sink

8

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

CRITICAL

J5700

F-RT-SM

20

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

19

7

39 40

1

10K

5%

1/20W

MF

201

2

7

1

Keyboard Connector

518S0848

CAPS:INT

R5714

WS_KBD15_C

47

WS_KBD16N

47

SMC_ONOFF_L

OUT

C5710

0.1UF

PLACEMENT_NOTE=NEAR J5713

47

SMC Manual Reset & Isolation

47

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

47

40

OUT

R5738

1 2

R5715

1 2

R5710

1 2

1

20%
10V

2

CERM

402

Keys ANDed with MSP power to isolate when MSP is not powered.

CAPS:EXT CAPS:EXT

1

10K

5%

1/20W

MF

201

2

CAP_COMP_H

CAPS:EXT
CRITICAL

SSM3K15AMFVAPE

CAP_COMP_L

Q5734

D

VESM

1

G S

SYNC_MASTER=D2_MLB_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

=PP3V3_S4_TPAD

8

47

=PP3V42_G3H_TPAD

8

47

WS_KBD1

7

47

WS_KBD2

7

47

WS_KBD3

7

47

WS_KBD4

7

47

WS_KBD5

7

47

WS_KBD6

7

47

WS_KBD7

7

47

WS_KBD8

7

47

WS_KBD9

7

47

WS_KBD10

7

47

WS_KBD11

7

47

WS_KBD12

7

47

113

1%
1/16W
MF-LF

402

0

5%
1/16W
MF-LF

402

1K

5%
1/16W
MF-LF

402

No IPD on OE input pin PP3V3_S4 (symbol error).

R5736

10K

1/20W

WS_KBD13

7

47

WS_KBD14

7

47

WS_KBD15_CAP

7

47

WS_KBD16_NUM

7

WS_KBD17

7

47

WS_KBD18

7

47

WS_KBD19

7

47

WS_KBD20

7

47

WS_KBD21

7

47

WS_KBD22

7

47

WS_KBD23

7

47

WS_KBD_ONOFF_L

7

WS_LEFT_SHIFT_KBD

7

47

WS_LEFT_OPTION_KBD

7

47

WS_CONTROL_KBD

7

47

1

5%
MF

201

2

CAP_COMP_L_INV

3

2

KEYBOARD/TRACKPAD (1 OF 2)

Apple Inc.

R

FF14A-30C-R11DL-B-3H

1

S

2

G

D

6

CAP_SOURCE

113

1/20W

113

1/20W

G

201

201

1

1%
MF

2

1

1%
MF

2

3

2

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

WS_KBD15_CAP

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

CAP_SINK

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

D

S

CAPS:EXT

R5737

CAPS:EXT

R5739

1

J5713

CRITICAL

518S0752

CAPS:EXT

Q5736

NTZD3152P

SOT-563-HF

CAPS:EXT

Q5738

DMN3730UFB4

DFN1006H4-3

SYM_VER_1

SYNC_DATE=12/08/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

57 OF 132

SHEET

47 OF 80

124578

32

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

31

F-RT-SM

D

C

B

7

47

A

SIZE

D

8 7 6 5 4 3

=PP3V3_S0_TPAD

8

1

R5858

470K

5%
1/16W
MF-LF
402

2

SMC_SYS_KBDLED

39 48

OUT

D

1

R5859

4.7K

5%
1/16W
MF-LF
402

2

7

48

SMC_KBDLED_PRESENT_L

7

KBDLED_CATHODE2

7

48

PP_KBD_BOOST_VOUT

Keyboard Backlight Driver & Detection

To detect Keyboard backlight, SMC will

tristate and read SMC_SYS_KBDLED:

If LOW, keyboard backlight present

If HIGH, keyboard backlight not present

Keyboard Backlight Connector

516S0899

CRITICAL

J5815

AA07A-S010-VA1

F-ST-SM

12
11

1

2

34
56
78
9

10

13
14

KBDLED_CATHODE1
PP_KBD_BOOST_VOUT

J5815 PIN 5 IS GROUNDED

7

48

7

48

ON KEYBOARD BACKLIGHT FLEX

12

D

C

PART NUMBER

138S0811

QTY

2

=PP5V_S0_KBDLED

8

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X6S,0603

B

SMC_SYS_KBDLED

39 48

A

GND_KBDLED_AGND

48

XW5810

SM

1 2

R5851

0

1 2

5%
1/16W
MF-LF

402

REFERENCE DES

C5810,C5811

PPVIN_S0_KBDLED_L

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

OMIT_TABLE

C5810

4.7UF

10%
35V

X5R-CERM

0603

R5802

1 2

5%
1/16W
MF-LF

402

I_LED= 804/RSET

NOSTUFF

1

C5854

33PF

5%
50V

2

CERM
402

CRITICAL

CRITICAL

OMIT_TABLE

1

1

2

C5811

4.7UF

10%
35V

2

X5R-CERM
0603

PPVIN_S0_KBDLED_C

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

0

1

R5850

100K

5%
1/16W
MF-LF

402

2

1

R5855

40.2K

1%
1/16W
MF-LF
402

2

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

BOM OPTION

1

C5812

0.1UF

10%
25V

2

X5R
402

GND_KBDLED_AGND

48

PVDC_KBDLED

GND_KBDLED_AGND

48

KBDLED_EN

SMC_SYS_KBDLED_FILTER

KBDLED_RSET

KBDLED_FSW
KBDLED_COMP

1

1

R5856

137K

1%
1/16W
MF-LF
402

2

FSW =1 MHZ
SEE SPEC FOR OTHERS

C5853

33PF

5%
50V

2

CERM
402

KBDLEDCOMP_RC

152S1701 COMBO

CRITICAL

PST041H-CDH46D14-SM

KBDLED_FPW

1

R5854

10K

5%
1/16W
MF-LF
402

2

1

C5855

0.0082UF

10%
25V

2

X7R
402

L5850

1 2

1

2

1

C5852

1UF

10%
25V

2

X5R
603-1

10UH-20%-1.4A-0.17OHM

1

R5810

0

5%
1/16W
MF-LF
402

2

KBDLED_SW1

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

SWITCH_NODE=TRUE

C5850

1UF

10%
25V
X5R
603-1

6

5

3

8

4

2

NOSTUFF

1

R5857

100K

5%
1/16W
MF-LF
402

2

1

C5851

0.01UF

10%
16V

2

X7R-CERM
0402

11

VDC

U5850

TQFN

EN

PWMI

RSET

FPW/DIRECTPWM

FSW

COMP

CRITICAL

PGND

AGND

1

10

7

VIN

LX

OVP

ISL97682

CH1

CH2

NC

THRM

PAD

17

371S0490

9

12

13

KBDLED_CATHODE1_R

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

15

VOLTAGE=35V

14

NC

16

NC

XW5800

1 2

CRITICAL

D5850

SOD-323
A K

PMEG4010BEA

XW5850

KBDLED_CATHODE2_R

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V

SM

2

SM

1

1

R5870

237K

1%
1/16W
MF-LF
402

2

1

R5871

10K

1%
1/16W
MF-LF
402

2

KBDBKLT:ENG

1

C5860

1.0UF

10%
50V

2

X5R
0603 0402

1

C5861

1.0UF

10%
50V

2

X5R
0603

NOSTUFF

1

C5870

33PF

5%
50V

2

CERM
402

NOSTUFF

1

C5871

33PF

5%
50V

2

CERM
402

GND_KBDLED_AGND

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=30V

1

C5862

1.0UF

10%
50V

2

X5R
0603

PP_KBDBOOST_XW

PART NUMBER

116S0004

KBDLED_OVP

R5852

10.2

1 2

0.1%

KBDBKLT:ENG

1/16W

TF

402

R5853

10.2

1 2

0.1%

1/16W

TF

402

6 3

1

C5863

1.0UF

10%
50V

2

X5R
0603

48

KBDLED_CATHODE1

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V

KBDLED_CATHODE2

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V

1

C5864

220PF

10%
50V

2

X7R-CERM

QTY

RES,MTL FILM,1/16W,0,5,0402,SMD,LF

2

PP_KBD_BOOST_VOUT

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=30V

DESCRIPTION

7

48

7

48

7

48

REFERENCE DES

R5852,R5853

SYNC_MASTER=D2_MLB_KEPLER

PAGE TITLE

CRITICAL

CRITICAL

KEYBOARD/TRACKPAD (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTION

KBDBKLT:PROD

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

58 OF 132

SHEET

48 OF 80

124578

SYNC_DATE=12/08/2011

SIZE

C

B

A

D

8 7 6 5 4 3

=PP3V3_S3_SMS

8

D

BYPASS=U5920.14:13:8 mm

Desired orientation when placed on top-side (view top):

+Y

+Z (up)

+X

C5926

10UF

39 40

OUT

7

Front of system

BYPASS=U5920.14:13:8 mm

SMS

20%

6.3V
X5R
603

SMS_INT_L
TP_SMS_INT2

SMS

1

1

C5922

0.1UF

10%

6.3V

2

2

X5R
201

PLACEMENT_NOTE=See schematic for orientation.

SMS

R5924

1/20W

10K

1

5%

MF

201

2

2

NC

NC

3

NC

10

RESERVED

15

11

INT1CSSDA/SDI/SDO

9

INT2

SMS

14

VDD

U5920

LIS331DLH

LGA

CRITICAL

GND

5

121316

VDD_IO

SCL/SPC

1

PLACE_SIDE=TOP

8

7

SDO

6

4

338S0687

SMS

R5920

10K

5%

1/20W

MF

SMS_I2C_SEL

SMS_ADDR_SELECT
I2C_SMC_SMS_SDA_R
I2C_SMC_SMS_SCL_R

201

NOSTUFF

1

2

R5925

1/20W

SMS

R5921

1/20W

1

10K

10K

5%

MF

201

2

1

5%

MF

201

2

SMS

R5923

0

1 2

R5922

1 2

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)
SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

NOTE: SDA and SCL have internal pull-ups to VDD_IO.

1/20W

SMS

1/20W

5%

MF

201

0

5%

MF

201

=I2C_SMC_SMS_SDA

=I2C_SMC_SMS_SCL

42

BI

42

IN

C

Circle indicates pin 1 location when placed
in correct orientation

12

D

C

=PP3V3_S3_GYRO

8

GYRO

1

C5940

0.1UF

10%

6.3V

2

GYRO

1

R5944

10K

5%
1/20W
MF
201

2

CS PU = I2C

INT ARE PUSH-PULL

B

TP_IRQ_GYRO_INT2_L
TP_GYRO_SYNC

TP_IRQ_GYRO_INT1_L

PLLFILT_GYRO1

GYRO_CS

PLLFILT_GYRO

GYRO

1

C5942

0.47UF

10%

6.3V

2

CERM-X5R
402

GYRO

1

R5945

10K

5%
1/20W
MF
201

2

GYRO

1

C5945

0.01UF

10%
10V

2

X5R
201

GYRO

14

5
6
8

7

RES/VDD

AP3GDL8B

CS
DRDY/

INT2

DEN

INT1
PLLFILT

15

16

VDD_IO

VDD

U5940

LGA

SDA_SDI_SDO

CRITICAL

GND

13

1

SCL_SPC

SDO_SA0

RES0
RES1
RES2
RES3

X5R
201

338S0927 = 8KHZ

2

I2C_SMC_GYRO_SCL_R

3

I2C_SMC_GYRO_SDA_R

4

9
10
11
12

A

6 3

GYRO

1

C5941

0.1UF

10%

6.3V

2

X5R
201

GYRO

1

C5943

10UF

20%

6.3V

2

CERM-X5R
0402-1

GYRO

R5946

1 2

GYRO

R5947

1 2

1/20W

1/20W

0

5%

MF

201

0

5%

MF

201

GYRO

(WRITE: 0XD0 READ: 0XD1)

=I2C_SMC_GYRO_SCL

=I2C_SMC_GYRO_SDA

42

IN

B

42

BI

SIZE

A

D

SYNC_MASTER=J5_MLB

PAGE TITLE

DIGITAL ACCELEROMETER & GYRO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

59 OF 132

SHEET

49 OF 80

124578

8 7 6 5 4 3

12

D

C

DUAL I/O MODE (MODE 0 & 3) SUPPORTED

=PP3V3_SUS_ROM

8

40 41 40 41

IN IN

40 41

IN

7

20 41

IN

NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.

High Speed CLK Frequency - 50MHz for fast read dual I/O

1

R6101

3.3K

5%
1/20W
MF
201

2

SPI_MLB_CLK

SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB

C6100

0.1UF

X5R-CERM

0201

1

10%
16V

2

6

1
3
7

SCK

SST25VF064C

CE*
WP*

RST*/HOLD*

VDD

U6100

64MBIT

WSON

OMIT_TABLE

VSS

CRITICAL

SI/SIO0

SO/SOI1

THRM_PAD

984

5

2

SPI_MLB_MOSI

SPI_MLB_MISO

40 41

OUT

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

SPI ROM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/20/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

61 OF 132

SHEET

50 OF 80

124578

8 7 6 5 4 3

12

www.qdzbwx.com

AUDIO CODEC

L6201

FERR-22-OHM-1A-0.065-OHM

8

IN

=PP1V5_S0_AUDIO

1 2

0201

D

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

8

55

MERRY = LOW

FG = HIGH

55

55

7

7

SPKRCONN_L_ID

IN

SPKRCONN_R_ID

IN

1 2

GPIO3 = SPKR AMP SHDN CONTROL

R6252

0

5%
1/16W
MF-LF

402

R6253

0

1 2

5%
1/16W
MF-LF

402

1

R6250

10K

5%
1/16W
MF-LF
402

2

53

51 54

1

R6251

10K

2

55

8

5%
1/16W
MF-LF
402

OUT

IN

IN

51 54 55

AUD_GPIO_3

AUD_SENSE_A

=PP3V3_S0_AUDIO_DIG

51 52 54 55

PP4V5_AUDIO_ANALOG

IN

C6216

1UF

10%
10V
X5R
402-1

C

HDA_BIT_CLK

17 75

IN

HDA_SYNC

17 75

IN

HDA_SDIN0

17 75

IN

HDA_SDOUT

17 75

OUT

HDA_RST_L

17 75

IN

B

7

54

OUT

R6211

22

1 2

5%
1/16W
MF-LF

402

AUD_SPDIF_OUT_JACK

U6201 CONSUMES 40MA MAX. FROM 1.5V RAIL

1

2

7

55

1

C6226

0.1UF

10%

6.3V

2

X5R
201

R6220

33

1 2

5%
1/16W
MF-LF

402

1

C6211

0.1UF

10%

6.3V

2

X5R
201

CRITICAL

C6221

AUD_DMIC_SDA1

IN

15UF

1

2

1

2

C6210

4.7UF

20%
4V
X5R-1
402

R6210

2.67K

1%
1/20W
MF
201

AUD_SDI_R

75

1

R6254

0

5%
1/20W
MF
201

2

PP1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V

1

20%

4V

2

X5R

0402

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CRITICAL

C6222

15UF

20%
4V
X5R
0402

AUD_SPDIF_IN

7

AUD_SPDIF_OUT

CRITICAL

1

C6220

15UF

20%
4V

2

X5R
0402

1

2

C6219

TANT-POLY

0805-LLP-1

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CS4206_FP
CS4206_FN

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CS4206_FLYP
CS4206_FLYC

1

2

CS4206_FLYN

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

GND_AUDIO_CODEC

51 52 54 55

1

10UF

20%
16V

2

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

VBIAS_DAC

SPKRCONN_L_ID_R

SPKRCONN_R_ID_R

CRITICAL

C6223

15UF

20%

4V

X5R

0402

APPLE P/N 353S2355

29

44
41

2

12

14
15

13

45
43
42

3

1

6

10

8
5

11

47
48

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=0V

9

VA_REF

VD

VBIAS_DAC

VHP_FILT+
VHP_FILT-

GPIO0/DMIC_SDA1
GPIO1/DMIC_SDA2
GPIO2
GPIO3

U6201

CS4206B

/SPDIF_OUT2

SENSE_A

FLYP
FLYC
FLYN

VL_HD

CRITICAL

VL_IF

BITCLK

SYNC

SDI
SDO

RESET*

SPDIF_IN
SPDIF_OUT

THRM_PAD

DGND

7

49

24

46

VA_HP

QFN

LINEOUT_L1+
LINEOUT_L1­LINEOUT_R1+
LINEOUT_R1-

LINEOUT_L2+
LINEOUT_L2­LINEOUT_R2+
LINEOUT_R2-

AGND

26

25

VA

HPOUT_L
HPOUT_R

HPREF

MICBIAS

VCOM

LINEIN_L+
LINEIN_C­LINEIN_R+

MICIN_L+
MICIN_L­MICIN_R+
MICIN_R-

VREF+_ADC

DMIC_SCL

C6218

0.1UF

X7R-CERM

1

10%
16V

2

0402

38
40

39

35
34
36
37

31
30
32
33

16

CS4206_VCOM

28

21

22

23

18
17
19
20

27

AUD_DMIC_CLK_R

4

C6224

1UF

TANT

0603-SM

1

C6217

10UF

20%
16V

2

TANT-POLY
0805-LLP-1

R6241

0

1 2

5%

1/20W

MF

201

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CS4206_VREF_ADC

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

1

1

C6225

20%
16V

10UF

20%
16V

2

2

TANT-POLY
0805-LLP-1

NC

CRITICAL

C6214

0.1UF

X5R-CERM

0201

10%
16V

1

2

AUD_DMIC_CLK

CRITICAL

1

C6213

10UF

20%
10V

2

X5R-CERM
0402-1

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

PP5V_AUDIO_HPAMP

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_HP_PORT_L
AUD_HP_PORT_R

AUD_HP_PORT_REF

AUD_LO1_L_P
AUD_LO1_L_N
AUD_LO1_R_P
AUD_LO1_R_N

AUD_LO2_L_P
AUD_LO2_L_N
AUD_LO2_R_P
AUD_LO2_R_N

TP_AUD_CODEC_MICBIAS

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

NC_AUD_LI_P_L
NC_AUD_LI_REF
NC_AUD_LI_P_R

AUD_MIC_INL_P
AUD_MIC_INL_N

55

OUT

51

51 54 55

IN

51 52 54 55

51 52 54 55

52 54

OUT

52 54

OUT

54

IN

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

7

NC
NC
NC

54 78

IN

54 78

IN

TP_AUD_MIC_INRP

TP_AUD_MIC_INRN

D

LFT SUBWOOFER AMP. SIG. SOURCE

RT. SUBWOOFER AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

C

EXT MIC CODEC INPUT

7

7

B

4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2456

L6202

D1: PLACE XW6201 NEAR 5V SOURCE

XW6201

SM

=PP5V_S0_AUDIO

8

IN

A

1 2

8

51 54

PP5V_S0_AUDIO_XW

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

=PP3V3_S0_AUDIO_DIG

IN

FERR-22-OHM-1A-0.065-OHM

1 2

0201

L6200

FERR-22-OHM-1A-0.065-OHM

1 2

0201

R6200

2.2K

1 2

5%

1/20W

MF

201

1

C6200

2

1UF

10%
10V
X5R
402

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V

PP5V_AUDIO_HPAMP

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V

4V5_REG_IN

4V5_REG_EN

51

1

2

6

4

C6201

1UF

10%
10V
X5R
402

IN

EN

U6200

TPS71745

SON

CRITICAL

GND

2

OUT

NR/FB

XW6200

1 2

1

3

4V5_NR

5

NC

SM

CRITICAL

C6202

0.1UF

X5R-CERM

0201

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

CRITICAL

1

1

C6203

10%
16V

1.0UF

20%
10V

2

2

X5R-CERM
0201-1

GND_AUDIO_CODEC

OUT

51 54 55

51 52 54 55

6 3

NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS

SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012

PAGE TITLE

AUDIO: CODEC/REGULATOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

62 OF 132

SHEET

51 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

D

C

D

C

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

AUD_HP_PORT_L

51 54

51 54

IN

B

AUD_HP_ZOBEL_L

NC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

GND_AUDIO_CODEC

51 54 55

IN

AUD_HP_ZOBEL_R

NC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_R

51 54

51 54

IN

CRITICAL

C6300

0.1UF

R6300

R6310

1/20W

CRITICAL

C6310

0.1UF

6.3V

10%
X5R

201

6.3V

1/20W

39

5%
MF

201

1

10%

2

X5R
201

1

39

5%
MF

201

2

1

2

1

2

1

R6302

10K

1%
1/20W
MF
201

2

1

R6312

10K

1%
1/20W
MF
201

2

A

6 3

OUT

B

OUT

SIZE

A

D

PAGE TITLE

AUDIO: HEADPHONE FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/06/2012SYNC_MASTER=D1_AUDIO

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

63 OF 132

SHEET

52 OF 80

124578

8 7 6 5 4 3

PP5V_S0_AUDIO_AMP_L

9

53

CRITICAL

CRITICAL

L6610

FERR-1000-OHM

1 2

51 78

AUD_LO2_L_N

IN

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

APN: 353S2888 & 353S2958

D

GAIN = +3 DB
1ST ORDER FC (L&R) = NOM 569 HZ
1ST ORDER FC (SUB) = NOM 9 HZ

51 78

IN

AUD_LO2_L_P

AUD_SPKRAMP_SHUTDOWN_L

53

51 78

IN

C

51 78

PP5V_S0_AUDIO_AMP_R

9

53

1

2

CRITICAL

C6632

47UF

20%

6.3V
POLY-TANT

C2

CRITICAL

VDD

U6630

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

OUT+
OUT-

GAIN

EDGE

C1

CRITICAL

1

CRITICAL

L6630

FERR-1000-OHM

51 78

51 78

IN

IN

AUD_LO1_R_P

AUD_LO1_R_N

1 2

0402

CRITICAL

L6631

FERR-1000-OHM

1 2

78

0402

AUD_SPKRAMP_RSUBIN_P

78

AUD_SPKRAMP_RSUBIN_N

CRITICAL

CRITICAL

C6634

0.22UF

1 2

C6633

0.22UF

1 2

10%
16V
CERM
402

RSUBIN_N

10%
16V

CERM

402

RSUBIN_P

NO_TEST=TRUE

NO_TEST=TRUE

AUD_SPKRAMP_SHUTDOWN_L

53

C6635

47UF

20%

6.3V

2

POLY-TANT
0805-LLP 0805-LLP

AUD_LO2_R_N

IN

C3

B3

A3

TP_SWR_GAIN

B2

0402

L6611

FERR-1000-OHM

1 2

0402

CRITICAL

AUD_LO2_R_P

FERR-1000-OHM

1 2

CRITICAL

78

78

1 2

L6621

0402

PLACE_NEAR=U6630.C2:5.1MM

1

C6631

0.1UF

10%
16V

2

X7R-CERM
0402

AUD_SPKRAMP_LIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LIN_N

51

CRITICAL

L6620

FERR-1000-OHM

0402

78

NO_TEST=TRUE

AUD_GPIO_3

IN

78

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

CRITICAL

C6614

0.01UF

1 2

10%
50V

X7R-CERM

0402

CRITICAL

1 2

53

CRITICAL

C6624

0.01UF

1 2

10%
50V

X7R-CERM

0402

C6613

0.01UF

1 2

10%
50V

X7R-CERM

0402

78

L6601

FERR-1000-OHM

0402

CRITICAL

PP5V_S0_AUDIO_AMP_R

9

CRITICAL

C6623

0.01UF

1 2

10%
50V

X7R-CERM

0402

AUD_SPKRAMP_SHUTDOWN_L

53

SPKRCONN_SR_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SR_OUT_N

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

78

78

NO_TEST=TRUE

NO_TEST=TRUE

SPKRAMP_LIN_P
SPKRAMP_LIN_N

NO_TEST=TRUE

78

SPKRAMP_RIN_N

NOSTUFF

C6612

47UF

6.3V

TANT-POLY

CASE-A4

R6600

100K

1/16W
MF-LF

402

C6622

POLY-TANT

0805-LLP

CRITICAL

NO_TEST=TRUE

SPKRAMP_RIN_P

R6601

100K

5%

1/20W

MF

201

1

20%

2

A1

PVDD

U6610

MAX98300

WLP

A3

IN+

B3

IN-

C2

SHDN*

B2

NC

1

5%

2

1

47UF

20%

6.3V

2

1

2

PGND

A2

PVDD

U6620

MAX98300

A3

IN+

B3

IN-

C2

SHDN*

B2

NC

PGND

B1

OUT+

C1

OUT-

C3

GAIN

A1

WLP

OUT+
OUT-

GAIN

A2

PLACE_NEAR=U6610.A1:5.1MM

1

C6611

0.1UF

10%
16V

2

X7R-CERM
0402

CKPLUS_WAIVE=ndifpr_badterm
CKPLUS_WAIVE=pdifpr_badterm

SPKR_L_GAIN

1

R6610

100K

5%
1/16W
MF-LF

402

2

PLACE_NEAR=U6620.A1:5.1MM

1

C6621

0.1UF

10%
16V

2

X7R-CERM
0402

B1

C1

C3

SPKR_R_GAIN

1

R6620

100K

5%
1/16W
MF-LF

402

2

SPKRCONN_L_OUT_N

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

7

55 78

OUT

7

55 78

OUT

SPKRCONN_R_OUT_N

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

B

12

SPKRCONN_L_OUT_P

7

55 78

OUT

OUT

7

55 78

OUT

7

55 78

OUT

D

7

55 78

C

B

9

53

CRITICAL

L6640

FERR-1000-OHM

51 78

51 78

AUD_LO1_L_N

IN

AUD_LO1_L_P

IN

1 2

0402

CRITICAL

L6641

FERR-1000-OHM

1 2

0402

78

78

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_N

CRITICAL

CRITICAL

C6643

0.22UF

1 2

C6644

0.22UF

1 2

10%
16V
CERM
402

NO_TEST=TRUE

LSUBIN_P

10%
16V

CERM

402

NO_TEST=TRUE
LSUBIN_N

AUD_SPKRAMP_SHUTDOWN_L

53

A

6 3

PP5V_S0_AUDIO_AMP_L

CRITICAL

1

C6645

47UF

20%

6.3V

2

POLY-TANT
0805-LLP

1

2

CRITICAL

C6642

47UF

20%

6.3V
POLY-TANT
0805-LLP

PLACE_NEAR=U6640.C2:5.1MM

1

C6641

0.1UF

10%
16V

C2

CRITICAL

VDD

U6640

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

OUT+
OUT-

GAIN

EDGE

C1

CKPLUS_WAIVE=ndifpr_badterm

C3

CKPLUS_WAIVE=pdifpr_badterm

B3

A3

TP_SWL_GAIN

B2

2

X7R-CERM
0402

SPKRCONN_SL_OUT_N

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SL_OUT_P

7

55 78

OUT

7

55 78

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

OUT

AUDIO: SPEAKER AMP

Apple Inc.

R

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

66 OF 132

SHEET

53 OF 80

SIZE

A

D

124578

I2C PULLUPS ON SOUTHBRIDGE PAGE

=I2C_MIKEY_SCL

42

IN

=I2C_MIKEY_SDA

42

BI

D

AUD_I2C_INT_L

19

OUT

AUD_IPHS_SWITCH_EN

25

IN

AUD_PORTA_DET_L

55

IN

C

8 7 6 5 4 3

PP4V5_AUDIO_ANALOG

51 55

51 54

R6757

1 2

1/20W

R6758

33

1 2

5%

1/20W

MF

201

NOSTUFF

R6761

47K

1 2

5%

1/20W

MF

201

GND_AUDIO_CODEC

51 52 54 55

AUD_MIC_INL_P

51 78

OUT

AUD_MIC_INL_N

51 78

OUT

=PP3V3_S0_AUDIO_DIG

8

33

5%
MF

201

54

54

HS_HDET

CRITICAL

C6752

CRITICAL

C6753

1

C6755

R6762

10K

1/20W

1

5%
MF

201

2

4.7UF

20%

6.3V

2

X5R-CERM1
402

AUDIO_SCL
AUDIO_SDA

1

R6755

100K

5%

1/20W

MF

201

2

0.1UF

1 2

10%

6.3V
X5R
201

0.1UF

1 2

10%

6.3V
X5R
201

HS_MIC_HI_RC

78

1

R6756

100K

1/20W

201

HS_MIC_LO_RC

78

R/C6750 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
(SEE RADAR # 6210118)

1

5%
MF

2

2

CRITICAL

C3

B3

D3

A3

A1

B2

CRITICAL

C6750

6800PF

10%
10V
X5R-X7R-CERM
0201

AVDD

U6751

CD3282A1

WCSP

SCL

SDA

INT*

ENABLE

HDET

CS

DGND

C2

NO_XNET_CONNECTION=TRUE

PORT B LEFT(HEADSET MIC)

HP=80HZ, LP=10.63KHZ

MIKEY 1A
APN:353S2640
MIKEY ADDRESS: WRITE=72H, READ=73H

A2

C1

MICBIAS

DETECT

BYPASS

R6750

2.2K

1 2

1/20W

R6759

1 2

1/20W

HS_MIC_BIAS

B1

HS_SW_DET

D1

HS_RX_BP

AGND

D2

5%
MF

201

0

5%
MF

201

R6760

1/20W

NOSTUFF

GND_AUDIO_CODEC

51 52 54 55

NO_XNET_CONNECTION=TRUE

1

C6756

0.01UF

10%
10V

2

X5R-CERM
0201

1

47K

5%
MF

201

2

=PP3V42_G3H_AUDIO

8

1

R6754

1K

5%

1/20W

MF

201

2

CRITICAL

1

C6758

27PF

5%
25V

2

NP0-C0G
0201

R6751

1K

12

5%

1/20W

MF

201

GND_AUDIO_CODEC

51 52 54
55

AUD_HP_PORT_REF

51

L6754

FERR-22-OHM-1A-0.065-OHM

1 2

0201

NO_XNET_CONNECTION=TRUE

1

2

R6752

2.2K

1 2

1%

1/20W

MF

201

C6751

10UF

20%
10V
X5R-CERM
0402-1

1

C6791

10UF

20%
10V

2

X5R-CERM
0402-1

XW6751

SM

1 2

PLACE_NEAR=U6750.D1:5.1MM

NO_XNET_CONNECTION=TRUE

GND_AUDIO_CODEC

51 52 54 55

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=3.42V

PP3V42_GH3_AUDIO_LC

1

C6790

1UF

10%
10V

2

X5R
402

GND_AUDIO_CODEC

51 52 54 55

R6753

2.2K

1 2

1%

1/20W

MF

201

HS_MIC_HI

78

78

HS_MIC_LO

CHS_CLAMPI

CHS_CLAMPO

54

IN

54

BI

54

54

AUDIO_SCL
AUDIO_SDA

IN
IN

NO_XNET_CONNECTION=TRUE

AUDIO JACK: HP CONNECTOR WITH MIKEY & CHS

1

C6754

0.1UF

10%
16V

2

X5R-CERM
0201

A1

VDD

U6750

TS3A8235YFP

WCSP

CRITICAL

D4

RAMPI

D3

RAMPO

C4

CLAMPI

B4

CLAMPO

D2 B1

MIC

D1

REF

A3

SCL

A4

SDA

A2

ADDR

C2B2B3

US_HS_GND
CH_HS_GND

GND1

GND2

GND

C3

MIC1
MIC2

C1

51

CH_HS_MIC

FERR-33-OHM-0.8A-0.09-OHM

US_HS_MIC

54

OUT

54

OUT

=PP3V3_S0_AUDIO_DIG

8

51 54

7

OUT

AUD_TIPDET_INV

55

OUT

51 52

IN

1 2

US_HS_GND

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM

CH_HS_GND

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM

AUD_SPDIF_OUT_JACK

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.1MM

FERR-33-OHM-0.8A-0.09-OHM

CRITICAL

L6701

0201

CRITICAL

L6700

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6702

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6704

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6703

1 2

0201

AUD_CONN_MIC

7

AUD_CONN_SLEEVE_XW

7

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

AUD_CONN_MIC_XW

7

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

AUD_CONN_HP_LEFT

7

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM

AUD_CONN_SLEEVE

7

APN:510S0009

CRITICAL

J6701

51138-0274

F-ST-SM

22
21

1

2
3 4
5 6
7 8
9

10

11 12
13 14
15 16
17 18

20

19

23
24

12

D

C

CRITICAL

L6705

B

51 52

IN

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.1MM

I2C ADDRESSES

MIKEY U6751 READ 0111 0011 0X73
MIKEY U6751 WRITE 0111 0010 0X72
CHS U6750 READ 0111 0111 0X77
CHS U6750 WRITE 0111 0110 0X76

55

OUT

AUD_TYPEDET

A

6 3

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6706

FERR-470-OHM

1 2

0201

AUD_CONN_HP_RIGHT

7

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM

AUD_CONN_TYPEDET

7

SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

AUDIO: JACK

Apple Inc.

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

67 OF 132

SHEET

54 OF 80

124578

SIZE

B

A

D

8 7 6 5 4 3

12

CODEC OUTPUT SIGNAL PATHS

FUNCTION

HP/LINE OUT

TWEETERS

SUB

SPDIF OUT

CODEC INPUT SIGNAL PATHS

D

FUNCTION

DMIC 1

DMIC2

SPDIF IN

HEADSET MIC

SYSTEM INT AND GPIO LINES

FUNCTION

MIKEY ENABLE

MIKEY INTERRUPT

PERIPHERAL DETECT

VOLUME

0X02 (2)

0X04 (4)

0X03 (3)

N/A

CONVERTER

0X02 (2)

0X04 (4)

0X03 (03)

0X08 (8)

CONVERTER

0X06 (6)

0X05 (5)

0X07 (7)

0X06 (6)

INT

PIRQ H

PIRQ F

C

55

51 54 55

B

=PP3V3_S0_AUDIO

8

51 55

1

R6866

475K

1%
1/20W
MF
201

2

R6892

IN

AUD_TIPDET_INV

54

A

NOM R6892-C6860 FC = 106Hz
SSM6N15FE Vth = 0.8V to 1.5V
SSM6N15FE IGSS = +/-1uA
FLEX-SIDE RPULLDOWN = 100k (TB 49.9k in REV 3)

1.5K

1 2

1%
1/16W
MF-LF

402

AUD_TIPDET_INV_R

1

C6860

1UF

10%

2

APN:376S0613

SSM6N15AFE

25V
402X5R

PIN COMPLEX

0X09 (9,A)

0X0B (11)

0X0A (10)

0X10 (16)

PIN COMPLEX

0X0E (D,E)

0X12 (12,C)

0X0F (15)

0X0D (13,V22,B,LEFT)

GPIO

SATA4GP/GPIO 16

GPIO 5

GPIO 3

51 55

OUT

IN

GND_AUDIO_CODEC

51 52 54 55

PP4V5_AUDIO_ANALOG

1

R6865

47K

5%
1/20W
MF
201

2

AUD_TIPDET_FET1

Q6803

SOT563

6

D

2

SG

1

MUTE CONTROL

N/A

GPIO_3

GPIO_3

N/A

VREF

3V3 N/A

3V3

N/A

MIKEY

PORT B DETECT(SPDIF DELEGATE)

AUD_SENSE_A

1

R6896

20.0K

1%
1/16W
MF-LF
402

2

AUD_PORTA_DET_L

6

Q6897

SSM6N15AFE

SOT563

D

2

SG

1

AUD_OUTJACK_INSERT_L

R6802

R6803

100K

12

5%

1/20W

MF

201

FERR-33-OHM-0.8A-0.09-OHM

AUD_TYPEDET_OD_INV

R6867

1 2

1/16W
MF-LF

402

CRITICAL

L6801

1 2

0201

0

5%

AUD_TIPDET_FET2

51 52 54 55

DET ASSIGNMENT

0X09 (B)

N/A

N/A

0X0C (A)

DET ASSIGNMENT

0X0C (12,C)

N/A

MIKEY

PORT A DETECT (HEADPHONES)

54

Q6897

SSM6N15AFE

SOT563

5

100K

12

5%

1/20W

MF

201

6

D

SOT563

N-CHN

S

1

Q6800

DMC2400UV

AUD_IP_PERIPHERAL_DET

EXTRACTION NOTIFICATION

AUD_OUTJACK_INSERT_L

3

25V
402X5R

D

5

SG

4

Q6803

SSM6N15AFE

SOT563

1

C6891

1UF

10%

2

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

51 55

8

51

1

R6895

39.2K

1%
1/16W
MF-LF
402

2

AUD_PORTB_DET_L

3

D

SG

4

AUD_TYPEDET_OD

3

D

G

P-CHN

SOT563

S

Q6800

DMC2400UV

4

G

2

AUD_TYPEDET_OD

OUT

AUD_DMIC_SDA1

7

OUT

AUD_DMIC_CLK

51

OUT

NC

OUT

1

R6801

150K

2

5

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

19

OUT

51 55

55

PP4V5_AUDIO_ANALOG

1%
1/20W
MF
201

AUD_TYPEDET

1

C6800

55

IN

55

0.1UF

PLACE_NEAR=Q6800.4:5.1MM

10%

6.3V
2

X5R
201

8

55

Alternate Parts

MIN_LINE_WIDTH=0.40MM

CON_DMIC_PWR

CON_DMIC_CLK

7

SPEAKERID

R6810

100K

1/16W
MF-LF

402

R6812

100K

1/16W
MF-LF

402

SPEAKERID

MIN_NECK_WIDTH=0.15MM

VOLTAGE=3.3V

1

1%

2

1

1%

2

FF14A-6C-R11DL-B-3H

NC

NC

SPEAKERID

1

R6811

100K

1%
1/16W
MF-LF
402

2

SPKRCONN_R_ID

1

R6813

100K

1%
1/16W
MF-LF
402

2

SPEAKERID

55

MCP6514_POS

R6885

7

0

1 2

5%
1/16W
MF-LF

402

R6884

0

1 2

CON_DMIC_SDA1

7

5%
1/16W
MF-LF

402

R6883

0

1 2

5%
1/16W
MF-LF

402

=PP5V_S4_AUDIO

8

55

SPKRCONN_L_ID

7

IN IN

54

IN

51 54 55

51 52 54 55

MCP6514_NEG

=PP5V_S4_AUDIO

PART NUMBER

SPEAKERID

R6814

274K

1%
1/16W
MF-LF

402

SPEAKERID

R6815

90.9K

1%
1/16W
MF-LF

402

ALTERNATE FOR
PART NUMBER

353S1286353S3452
376S1081376S0975

1

2

1

2

1

2

BOM OPTION

SPEAKERID

C6811

4.7UF

20%
10V
X5R-CERM
0402

REF DES

U6800
Q6800

2-MIC CONNECTOR

CRITICAL

J6801

F-RT-SM

7

1
2
3
4
5
6

8

7

51 55

SPEAKERID

R6816

100K

1 2

1/16W
MF-LF

402

=PP5V_S4_AUDIO

8

3

4

SPEAKERID

R6817

45.3K

1 2

1%
1/16W
MF-LF

402

COMMENTS:

MAXIM ALT TO MICROCHIP
TOSHIBA ALT TO DIODES

1%

SPEAKERID
CRITICAL

U6800

5

MCP6541T

SC70-5

2

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

SPEAKERID

1

C6810

0.1UF

10%

6.3V

2

X5R
201

1

MCP6514_OUT

SPKRCONN_L_OUT_P

7

53 78

IN

SPKRCONN_L_OUT_N

7

53 78

IN

SPKRCONN_L_ID

7

51 55

OUT

SPKRCONN_SL_OUT_P

7

53 78

IN

SPKRCONN_SL_OUT_N

7

53 78

IN

SPKRCONN_R_OUT_P

7

53 78

IN

SPKRCONN_R_OUT_N

7

53 78

IN

SPKRCONN_R_ID

7

51 55

OUT

SPKRCONN_SR_OUT_P

7

53 78

IN

SPKRCONN_SR_OUT_N

7

53 78

IN

SPEAKERID

L6802

FERR-1000-OHM

1 2

AUDIO CONNECTOR DETECT STATES

AUD_J1_TYPEDET_R 1 1 0

AUD_J1_TIPDET_R 0 1 1

AUD_OUTJACK_INSERT_L 1 0 0

AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV

0402

SPEAKER CONNECTOR

SPKR_MATCH_DRV_R

NOTHING SPDIF HEADPHONE

PAGE TITLE

AUDIO: JACK TRANSLATORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

HP=80HZ

APN: 518S0627

PORT C DETECT(SPEAKER MISMATCH)

51 55

NC

SPEAKERID

R6820

33

1 2

1/16W
MF-LF

5%

402

SPKR_MATCH_DRV

51 52 54 55

CRITICAL

J6802

78171-6006

M-RT-SM

7

1
2
3
4
5
6

8

CRITICAL

J6803

78171-6006

M-RT-SM

7

1
2
3
4
5
6

8

AUD_SENSE_A

OUT

SPEAKERID

R6894

AUD_PORTC_DET_L

SPEAKERID

Q6896

SSM6N15AFE

SOT563

2

GND_AUDIO_CODEC

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

68 OF 132

SHEET

55 OF 80

124578

10K

1/16W
MF-LF

SYNC_DATE=06/06/2012SYNC_MASTER=D1_AUDIO

402

D

C

1

1%

2

6

D

B

SG

1

A

SIZE

D

D

C

CRITICAL

J6900

53780-8608

F-RT-SM

10

1
2
3
4
5
6
7
8

9

518S0543

8 7 6 5 4 3

MagSafe DC Power Jack

PP18V5_DCIN_FUSE

7

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

NC

PLACE COMPONENTS NEAR BATTERY CONNECTOR AREA

VOLTAGE=18.5V

ADAPTER_SENSE

7

NO STUFF

1

C6905

0.1UF

10%
50V

2

X7R
603-1

1-Wire OverVoltage Protection

The chassis ground will otherwise float and can

send transients onto ADAPTER_SENSE when AC is

connected.

C6900

0.1UF

CERM

20%
10V

402

CRITICAL

F6905

6AMP-32V-0.0095OHM

1 2

0603

SMC_BC_ACOK_VCC

1

1

2

VCC

U6900

MAX9940

SC70-5

5

EXT INT

CRITICAL

NC GND

2

3

NC

PPVBAT_G3H_CONN

CRITICAL

U6901

TC7SZ08FEAPE

SOT665

4

=PP3V42_G3H_ONEWIREPROT

1

2

5

2

A

4

Y

1

R6929

2.0K

5%
1/16W
MF-LF
402

2

1

B

3

SYS_ONEWIRE

DCIN_ISOL_BLEEDER_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

7

57

C6908

0.1UF

20%

PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

10V
CERM
402

SMC_BC_ACOK

=PP18V5_DCIN_ISOL

8

39

BI

Q6930

2N7002

SOT23-HF1

1

R6930

1K

2

3

D

S

2

8

39 40

IN

BLEEDER

CRITICAL

D6920

SBR0330CW

SOT-323
1

2

BLEEDER

5%
1/16W
MF-LF
402

BLEEDER

1

G

DCIN_ISOL_BLEEDER_NGATE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

www.qdzbwx.com

3

DCIN_ISOL_BLEEDER_PSRC

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

1

C6920

0.1UF

10%

BLEEDER

50V

2

X7R
603-1

2

BLEEDER

S

1

G

D

3

BLEEDER

1

R6921

10K

5%
1/16W
MF-LF
402

2

Q6920

AO3407A

SOT23

Q6910

SI5419DU

POWERPAK

5A

D

1

DCIN_ISOL_GATE_R

S

5

G

C6912

4

0.047UF

0402

6.8V Zener

=PP18V5_DCIN_CONN

1

10%
25V

2

X5R

R6911

10K

1 2

1/20W

1%
MF

201

8

1

R6912

68K

1%
1/20W
MF
201

2

1

2

Input impedance of 68K meets
sparkitecture requirements
for both MPM4 and MPM5.

R6910

When input voltage is 2V the FET will be off

100K

blocking the leakage path and 22.1K can be

5%
1/20W
MF

properly detected.

201

When input voltage is at 16V+, FET will
conduct and power charger and 3.42V reg

DCIN_ISOL_GATE

K

D6910

GDZT2R6.8

GDZ-0201

A

12

D

C

7

C6950

0.1UF

10%
25V
X5R
402

1

2

C6960

1UF

603-1

10%
25V
X5R

1

2

B

A

SYSDET_3_4

OMIT

998-4777

CRITICAL

J6950

INTERPOSER-D1-TOP

COMBO-SM

A1

A1
A2
A3
A4
A6
A7
A8
A9
A10

B1
B2
B3
B4
B6
B7
B8
B9
B10

C1
C2
C3
C4
C6
C7
C8
C9
C10

D1
D2
D3
D7
D8
D9
D10

E2
E3
E8
E9

E10

F2
F3
F8
F9

F10

G1
G2
G3
G7
G8

G10

H1
H2
H3
H4
H6
H7

J1
J2
J3
J4
J7
J6

STIFF

TALL

SHRT

A10

B10

C10

D10

A2
A3
A4
A6
A7
A8
A9

B1
B2
B3
B4
B6
B7
B8
B9

C1
C2
C3
C4
C6
C7
C8
C9

D1
D2
D3
D7
D8
D9

E2
E3
E8
E9
E10

F2
F3
F8
F9
F10

G1
G2
G3
G7
G8
G10

H1
H2
H3
H4
H6
H7

J1
J2
J3
J4
J7
J6

63

64

65

=PPBUS_G3H

8

57

SH6950

4.0OD2.7ID-1.8H

2

1

R6920

47

1 2

1%

1/3W

MF

805

R6905

10

1 2

5%

1/8W

MF-LF

805

=SMBUS_BATT_SCL

PP18V5_DCIN_CONN_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

PPBUS_G3H_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

42

BI

CRITICAL

D6905

SBR0330CW

SOT-323
1

2

3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

PART NUMBER

138S0811

OMIT_TABLE

C6992

4.7UF

10%
35V

X5R-CERM

0603

1

2

QTY

3

OMIT_TABLE

C6991

4.7UF

10%
35V

X5R-CERM

0603

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X6S,0603

OMIT_TABLE

C6990

4.7UF

X5R-CERM

0603

10%
35V

1

2

1

2

NC

CRITICAL

D6950

RCLAMP2402B

3

=SMBUS_BATT_SDA

1

SC-75

3

2

42

BI

Pin 63 (SH0962) is Neoconix stiffener, 860-1533
Pin 64 (SH0961) is Neoconix tall locator pin. 860-1530
Pin 65 (SH0960) is Neoconix short clocking pin. 860-1529

6 3

REFERENCE DES

C6990,C6991,C6992

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

6

3

BOOST

VIN

U6990

LT3470AED

DFN

8 4

SHDN*

CRITICAL

7

NC

GND

SW

BIAS

1

FB

THRM

PAD

5

9

P3V42G3H_BOOST

DIDT=TRUE

NO_TEST=TRUE

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm

2

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

P3V42G3H_FB

CRITICAL

CRITICAL

1

C6994

0.22UF

10%
10V

2

CERM

10UH-30%-0.85A-460MOHM

402

1

2

Vout = 1.25V * (1 + Ra / Rb)

SYNC_MASTER=MASTER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTION

CRITICAL

L6995

1 2

C6995

22PF

5%
50V
CERM
201

=PP3V42_G3H_REG

1

1%
MF

2

1

1%
MF

2

Vout = 3.425V

100MA MAX OUTPUT

(Switcher limit)

CRITICAL

1

C6999

22UF

20%

6.3V

2

X5R
0603

2520

R6995

R6996

348K

1/20W

201

200K

1/20W

201

<Ra>

<Rb>

DC-In & Battery Connectors

Apple Inc.

R

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

69 OF 132

SHEET

56 OF 80

124578

8

B

A

SIZE

D

8 7 6 5 4 3

12

PPDCIN_G3H_DRAINS

MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=18.5V

Inrush Limiter

FROM ADAPTER

=PPDCIN_S5_CHGR

8

D

1

2

=PPDCIN_S5_CHGR_ISOL

8

CRITICAL

D7005

SBR0330CW

SOT-323
1

ACIN pin threshold is 3.2V, +/- 50mV
Divider sets ACIN threshold at 13.55V
Input impedance of ~90K meets

sparkitecture requirements

=PP3V42_G3H_CHGR

66

8

C

1

2

R7012

1/16W
MF-LF

R7010

68.1K

1%
1/16W
MF-LF
402

402

1

1K

1%

2

SMC_RESET_L

IN

C7002

1UF

10%
10V
X5R
402

1

2

GND_CHGR_AGND

R7000

0

1 2

5%

42

1/16W
MF-LF

42

402

66

57

IN

BI

IN

Float CELL for 1S

1

R7011

21.5K

1%
1/16W
MF-LF
402

2

B

1

R7015

100K

1%
1/16W
MF-LF
402

2

CHGR_VCOMP_R

1

R7042

0

5%
1/16W
MF-LF
402

2

CHGR_VNEG_R

1

C7016

470PF

10%
50V

2

CERM
0402

CHGR_ICOMP_RC

1

C7042

0.068UF

10%
10V

2

X5R-CERM
0402

1

C7015

330PF

5%
50V

2

COG
402

R7016

3.01K

1/16W
MF-LF

402

77

77

1

1%

2

2

30mA max load

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

NO STUFF

1

R7002

100K

5%
1/16W
MF-LF
402

2

CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL

CHGR_ACIN
CHGR_ICOMP

CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N

1

C7050

1UF

10%
16V

2

X5R
402

C7011

0.01UF

X7R-CERM

C7085

0.1UF

10%
25V
X5R
402

R7086

10%

0402

1

R7085

470K

1/16W
MF-LF

402

2

332K

1%
1/16W
MF-LF

402

3

CHGR_DCIN_D_R

57

1

2

1%

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

1

2

R7001

4.7

1 2

5%
1/16W
MF-LF

402

19

VDD

12

CRITICAL

VHST

13

SMB_RST_N

11

SCL

U7000

10

SDA

4

VFRQ

6

CELL

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

(AGND)

29

1

C7000

1UF

10%
10V16V

2

X5R
402-1

Q7080

IRF9395TRPBF

DIRECTFET-MC

(CHGR_AGATE)

R7005

20

1 2

5%
1/16W
MF-LF

402

PP5V1_CHGR_VDDP

57

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

20

VDDP

DCIN

SGATE
AGATE

TQFN

CSIP
CSIN

BOOT

UGATE

ISL6259

PHASE

LGATE

BGATE

AMON

20V/V

BMON

36V/V

(OD)

ACOK

THRM_PAD

PGND

353S2929

22

XW7000

SM

1 2

PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm

C7005

0.22UF

X5R-CERM

0603-1

2

S

G

3

(CHGR_DCIN)

C7001

2

CHGR_DCIN

57

26

CHGR_SGATE

1

CHGR_AGATE

28

CHGR_CSI_P

77

27

CHGR_CSI_N

77

25

CHGR_BOOT

24

CHGR_UGATE

23

21

CHGR_LGATE

16

CHGR_BGATE

9

CHGR_AMON

15

CHGR_BMON

14

=CHGR_ACOK

(GND)

(CHGR_CSO_P)
(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

1

10%
50V

2

GND_CHGR_AGND

57

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

Reverse-Current Protection

1

C7080

4.7UF

10%
35V

2

X5R-CERM

0603

NOSTUFF

NCNCNC

879

D

CRITICAL

1

1UF

10%
10V

2

X5R
402

10

415

S

D

G

6

1

C7020

0.047UF

10%
10V

2

X5R-CERM
0402

NO_XNET_CONNECTION=TRUE

C7022

0.1UF

R7025

1/16W
MF-LF

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE
DIDT=TRUE

44

OUT

44

OUT

44 40

OUT

1

C7026

0.001UF

10%
50V

2

X7R-CERM

0402

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

(CHGR_SGATE)

R7021

1 2

R7022

1 2

1

1

C7021

10%
25V
X5R
402

1

0

5%

402

2

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

0.1UF

10%
25V

2

2

X5R
402

NO_XNET_CONNECTION=TRUE

CHGR_BOOT_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

1

C7025

0.22UF

10%
10V

2

CERM
402

PLACE_NEAR=U7000.25:2mm

SWITCH_NODE=TRUE

DIDT=TRUE

10

5%
1/16W
MF-LF

402

10

5%
1/16W
MF-LF

402

R7051
R7052

CHGR_DCIN_D_R

57

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=18.5V

1

R7080

100K

5%
1/16W
MF-LF
402

2

1

R7081

62K

5%
1/16W
MF-LF
402

2

CHGR_CSI_R_P

78

CHGR_CSI_R_N

78

CRITICAL

2

1

6

3 4 5

1 2

2.2

1 2

0

4

Q7030

RJK03P0DPA

WPAK

7

CHGR_PHASE

CHGR_CSO_R_P

78

1/16W

CHGR_CSO_R_N

78

1/16W

(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)

4025%

C7090

4.7UF

X5R-CERM

0603

OMIT_TABLE

10%
35V

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

P5V1_VIN

1

2

R7092

1 2

MF-LF

1/16W

0

NC

CRITICAL

123

R7020

0.02

0.5%
1W
MF
RL1632W

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

Max Current = 8.5A

(L7030 limit)
f = 400 kHz

CRITICAL

L7030

1 2

PIME103T-4R7MS

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

CRITICAL

R7050

0.01

0.5%
1W
MF

0612-3

1 2
3 4

MF-LF

MF-LF

4.7UH-20%-8.5A-18.3MOHM

4025%

4025%

For Erp Lot6 spec

P5V1_BOOST

DIDT=TRUE

3

6

BOOST

VIN

U7090

LT3470A

DFN

8 4

SHDN*

CRITICAL

7

NC

GND

SW

BIAS

FB

THRM

PAD

5

9

PART NUMBER

138S0811 CRITICAL

NO_TEST=TRUE

P5V1_SW

MIN_LINE_WIDTH=0.5 mm

2

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

1

C7094

1

0.22UF

10%
10V

CERM

33UH-20%-0.39A-0.435OHM

402

2

CRITICAL

L7095

1 2

DP418C-SM

P5V1_BIAS

1

C7095

22PF

5%
50V

2

CERM
201

P5V1_FB

Vout = 1.25V * (1 + Ra / Rb)

QTY

1

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X6S,0603

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

1

<Ra>

1

R7095

681K

1/20W

R7096

200K

1/20W

1%
MF

201

<Rb>

1%
MF

201

2

2

1

2

REFERENCE DES

C7090

CRITICAL

C7098

10UF

20%
25V
X5R-CERM
0603

NOTE: C7080 is the same APN, but NOSTUFFed per <rdar://problem/11815538>.

1

C7030

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

CRITICALCRITICAL

1

C7031

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

CRITICAL

1

C7032

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

1

C7035

1.0UF

10%
50V

2

X5R
0603

1

C7036

1.0UF

10%
50V

2

X5R
0603

PLACE_NEAR=Q7030.5:1mm

1

C7037

0.001UF

20%
50V

2

CERM
0402

PLACE_NEAR=C7036.1:3mm

CRITICAL

F7040

12AMP-32V

1 2

1206

CRITICAL

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

C7055

1UF

10%
25V
X5R
402

1

C7040

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C7056

2

0.1UF

10%
25V
X5R
402

1

2

1

C7045

0.001UF

10%
50V

2

X7R-CERM
0402

C7057

0.01UF

X7R-CERM

0402

10%
50V

CRITICAL

Q7055

SI7137DP

SO-8

SYM-VER-2

S

3
2

1

1

2

D

G

4

NOSTUFF

R7090

0

(P5V1_BIAS)

CRITICAL

1

C7099

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1 2

5% 402

MF-LF

1/16W

R7091

0

1 2

MF-LF

4025%

1/16W

Vout = 5.50V
100MA MAX OUTPUT
(Switcher limit)

BOM OPTION

TO SYSTEM

=PPBUS_G3H

TO/FROM BATTERY

5

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

CHGR_DCIN

PP5V1_CHGR_VDDP

56

8

56

7

57

57

D

C

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

70 OF 132

SHEET

57 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

System Agent Power Supply

12

D

DESCRIPTION

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

1

1

C7122

0.001UF

10%
35V

12

20%
50V

2

2

CERM
0402

PLACE_NEAR=C7121.1:3mm

PPVCCSA_S0_REG_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

VCCSAS0_CS_P

78 80

VCCSAS0_CS_N

78 80

1

R7142

1K

1%
1/16W
MF-LF
402

2

NO_XNET_CONNECTION=TRUE

20%
16V

1/16W
MF-LF

402

1

2

1K

1%

QTY

1

OMIT_TABLE

C7121

1.0UF

CERM-X5R

0402

PLACE_NEAR=Q7100.2:1mm

CRITICAL

L7100

1.0UH-7A

1 2

PIMB053T-SM

152S1302

1

C7140

2

1000PF

5%

25V

NP0-C0G

402

PART NUMBER

138S0812 CRITICAL

=PPVIN_S0_VCCSAS0

8

=PP5V_S0_VCCSAS0

8

PVCC

PGND

2

20

CRITICAL

1

C7101

10UF

20%
10V

2

X5R
603

BOOT

UGATE

PHASE

LGATE

1

R7101

2.2

5%
1/16W
MF-LF

402

EN

10

FB

7

SREF

12

VO

11

OCSET

PGOOD

4

RTN

FSEL

8

SET0

9

SET1

6

VID0

5

VID1

XW7100

2

19

VCC

U7100

ISL95875

UTQFN

CRITICAL

(ENDIAN SWAP)

GND

3

SM

1 2

PLACE_NEAR=U7100.3:1mm

PP5V_S0_VCCSAS0_VCC

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

66

C

CPU_VCCSASENSE

13 72

IN

VCCSAS0_RTN

2

XW7101

PLACE_NEAR=C1761.2:1mm

SM

1

B

R7151

1.62K

1 2

1%
1/16W
MF-LF

402

R7153

1.62K

1 2

1%
1/16W
MF-LF

402

1

C7106

10PF

5%

50V

2

CERM

402

1

R7154

4.64K

1%
1/16W
MF-LF
402

2

1

R7152

4.64K

1%
1/16W
MF-LF
402

2

C7103

0.022UF

X5R-X7R-CERM

0402

1

C7105

10PF

5%
50V

2

CERM
402

10%
16V

1

2

1

R7147

41.2K

1%
1/16W
MF-LF
402

2

1

R7148

52.3K

1%
1/16W
MF-LF
402

2

R7150

82.5K

1 2

1%
1/16W
MF-LF

402

VCCSAS0_SET_R

1

R7149

499K

1%
1/16W
MF-LF
402

2

IN

66

OUT

NO STUFF

R7103

1

C7102

2.2UF

10%
16V

2

X5R
603

13 72

13 72

=PVCCSA_EN

CPU_VCCSASENSE_DIV

VCCSAS0_SREF

NO_TEST=TRUE

VCCSAS0_VO
VCCSAS0_OCSET
PVCCSA_PGOOD
VCCSAS0_RTN_DIV

NO_TEST=TRUE

VCCSAS0_FSEL

VCCSAS0_SET0

1

VCCSAS0_SET1

0

5%
1/16W
MF-LF

402

2

CPU_VCCSA_VID<1>

IN

CPU_VCCSA_VID<0>

IN

VCCSAS0_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

14

13

INTEL TABLE:

VCCSAS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

VCCSAS0_VBST

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

1815

17

16

1

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

VCCSAS0_LL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE
DIDT=TRUE

VCCSAS0_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

(VCCSAS0_OCSET)

(VCCSAS0_VO)

R7130

0

5%
1/16W
MF-LF

402

VCCSAS0_DRVH

CRITICAL

C7120

1

C7130

1

2

0.22UF

10%
10V

2

CERM
402

2

1

6

3 4 5

68UF

POLY-TANT

CASE-D2E-SM

376S0944

CRITICAL

Q7100

RJK0222DNS

HWSON

7

R7141

NO_XNET_CONNECTION=TRUE

REFERENCE DES

CRITICAL

R7140

0.001

2%
1W
MF

0612

12
34

C7121

1

C7160

1000PF

10%
16V

2

X7R-CERM
0201

CRITICAL

OCP = R7141 x 8.5uA / R7140
OCP = 8.5A

BOM OPTION

=PPVCCSA_S0_REG

6A Max Output
f = 500 kHz

8

80

D

C

B

VID1 VID0 Voltage

0 0 0.9V

1 0 0.8V

0 1 0.725V

1 1 0.675V

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

System Agent Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

71 OF 132

SHEET

58 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PPVIN_S5_P5VP3V3

8

CRITICAL

C7243

68UF

POLY-TANT

CASE-D2E-SM

=PP5V_S4_REG

8

59

20%
16V

1

2

CRITICAL

C7240

68UF

POLY-TANT

CASE-D2E-SM

20%
16V

CRITICAL

1

2

CASE-D2E-SM

C7242

68UF

POLY-TANT

20%
16V

VOUT = 5.0V
12A MAX OUTPUT
F = 600 KHZ F = 600 KHZ

C

CRITICAL

1

C7253

330UF

20%

6.3V

2

POLY-TANT
CASE-D3L-SM

CRITICAL

C7252

330UF

6.3V

POLY-TANT

CASE-D3L-SM

20%

1

2

1

C7271

0.001UF

10%
50V

2

X7R-CERM
0402

CRITICAL

C7250

10UF

20%
25V

X5R-CERM

0603

1

2

2

1

152S0688

CRITICAL

L7220

1.0UH-21A-0.006OHM

PCMB103T-1R0MS

2

P5VS4_VSW

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

PLACE_NEAR=L7220.1:3MM

XW7222

1

PLACE_NEAR=L7220.1:3MM

P5VS4_VFB1_R

1

R7220

40.2K

0.5%
1/16W
MF-LF
0402

2

B

1

R7221

10.0K

0.5%
1/16W
MF
402

2

XW7220

2

SM

1

PLACE_NEAR=L7220.2:3MM

2

XW7221

SM

1

P5VS4_CSP1_R

OMIT_TABLE

1

1

C7241

1.0UF

10%
35V

2

2

CERM-X5R
0402

NO STUFF

1

R7299

1

5%
1/10W
MF-LF
603

2

P5VS4_SNUBR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

NO STUFF

C7299

0.0033UF

1

C7270

0.001UF

20%
50V

2

CERM
0402

CRITICAL

CSD58872Q5D

VIN

1

VSW

6
7
8

PGND

1

10%
50V

2

CERM

402

Q7220

SON5X6

9

TG

TGR

BG

R7256

3.01K

1/16W
MF-LF

402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1

C7224

0.1UF

10%
50V

2

X7R
603-1

3

P5VS4_TG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

4

5

C7218

0.1UF

X7R-CERM

R7247

1 2

1

1%

2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1 2

10%
16V

0402

1.5K

1%
1/16W
MF-LF

402

PART NUMBER

C7200

SKIP_5V3V3:AUDIBLE

1

R7244

1

5%
1/16W
MF-LF

402

2

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

1

C7237

150PF

5%

50V

2

CERM

402

QTY

2

1

1UF

10%
25V

2

X5R

603-1

SKIP_5V3V3:INAUDIBLE

R7201

1

R7200

0

5%

1/20W

MF

201

2

P5VP3V3_SKIPSEL

P5VS4_VBST

DIDT=TRUE

P5VS4_DRVH

DIDT=TRUE

P5VS4_LL

DIDT=TRUE

P5VS4_DRVL

DIDT=TRUE

P5VS4_CSP1
P5VS4_CSN1

P5VS4_VFB1
P5VS4_COMP1

=P5VS4_EN

47 66

IN

P5VS4_PGOOD

66

OUT

1

R7237

10K

1%
1/16W
MF-LF
402

2

P5VS4_COMP1_R P3V3S5_CSP2_R

1

C7236

4700PF

10%
100V

2

CERM
402

(P5VP3V3_VREF2)

DESCRIPTION

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

=PP5V_S4_REG

8

59

1

0

5%

1/20W

MF

201

2

R7236

12.1K

1%
1/16W
MF-LF

402

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

6
19
14

31

1

32

30

7

8

11

9
10

4

5

1

2

REFERENCE DES

C7241,C7281

2

23

VIN

V5SW

SKIPSEL1
SKIPSEL2
OCSEL

DRVL1

CSP1

MODE
VFB1 VFB2

GND

28

XW7200

PLACE_NEAR=U7200.28:1MM

29

VREG5

CRITICAL

U7201

QFN

TPS51980

THRM_PAD

2

SM

1

22

VREG3

33

VBST2VBST1

DRVH2DRVH1

DRVL2

COMP2COMP1

PGOOD2PGOOD1

CSP2
CSN2CSN1

P5VP3V3_VREG3
P5VP3V3_VREF2

13

VREF2

12

EN

26

DIDT=TRUE

24

DIDT=TRUE

25

SW2SW1

EN2EN1

DIDT=TRUE

27

DIDT=TRUE

18
17

3

RF

16
15

21
20

CRITICAL

CRITICAL138S0812

1

C7201

0.22UF

10%
10V

2

CERM

402

=P5VS5_EN

P3V3S5_VBST
P3V3S5_DRVH
P3V3S5_LL
P3V3S5_DRVL
P3V3S5_CSP2

P3V3S5_CSN2
P3V3S5_RF

P3V3S5_VFB2
P3V3S5_COMP2

=P3V3S5_EN
P3V3S5_PGOOD

1

R7238

12.1K

1%
1/16W
MF-LF
402

2

P3V3S5_COMP2_R

(P5VP3V3_VREF2)

BOM OPTION

1

C7203

2.2UF

20%
10V

2

X5R-CERM
402

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

OUT

R7239

C7238

4700PF

100V
CERM

IN

IN

10%
402

66

66

66

10K

1/16W
MF-LF

1

2

402

1

1%

2

=PP5V_S5_LDO

VOUT = 5V
100MA MAX OUTPUT

CRITICAL

1

C7205

10UF

20%

6.3V

2

X5R
603

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

R7263

0

1 2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1

2

MIN_LINE_WIDTH=0.6 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

DIDT=TRUE

MF-LF

GATE_NODE=TRUE

402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1

R7206

165K

1%
1/16W
MF-LF

402

2

C7239

47PF

5%
50V
CERM
402

8

C7264

P3V3S5_TG

C7288

0.1UF

X7R-CERM

R7246

1 2

1/16W
MF-LF

0.1UF

603-1

1 2

10%
16V

0402

806

1%

402

10%
50V
X7R

1

2

1

2

1

6

R7216

5.23K

1%
1/16W
MF-LF
402

2

3 4 5

CRITICAL

C7284

68UF

POLY-TANT

CASE-D2E-SM

376S0958

CRITICAL

Q7260

FDMS3602S

POWER56

7

PHASE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

1

2

CRITICAL

1

2

CASE-D2E-SM

C7280

POLY-TANT

20%
16V

NO STUFF

P3V3S5_SNUBR

NO STUFF

C7298

0.001UF

10%
50V
X7R
402

68UF

20%
16V

152S0754

CRITICAL

1.0UH-22A

PCMC063T-SM

R7298

1/10W
MF-LF

603

CRITICAL

1

C7282

2

POLY-TANT

CASE-D2E-SM

L7260

1

10

5%

2

XW7260

1

68UF

20%
16V

2

12

PLACE_NEAR=L7260.1:3MM

PLACE_NEAR=L7260.2:3MM

2

SM

1

OMIT_TABLE

1

C7281

1.0UF

10%
35V

2

CERM-X5R
0402

=PP3V3_S5_REG

0.001UF

CRITICAL

1

2

PLACE_NEAR=L7260.2:3MM

2

XW7262

SMSM

1

P3V3S5_VFB2_R

2

XW7261

SM

1

1

C7283

0.001UF

20%
50V

2

CERM
0402

VOUT = 3.3V

10.5A MAX OUTPUT

X7R-CERM

0402

10UF

20%
25V
X5R-CERM
0603

1

10%
50V

2

R7260

23.2K

1/16W
MF-LF

R7261

10.0K

1/16W

0.5%

0402

0.5%

402

CRITICAL

1

C7292

330UF

20%

6.3V

2

POLY-TANT
CASE-D3L-SM

1

2

1

MF

2

C7272

C7290

D

8

C

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

5V / 3.3V Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

72 OF 132

SHEET

59 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

PART NUMBER

138S0812 CRITICAL

QTY

2

DESCRIPTION

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

D

REFERENCE DES

C7332,C7335

CRITICAL

BOM OPTION

D

DDR3 (1V5R1V35 S3) REGULATOR

=PPVIN_S3_DDRREG

8

CRITICAL

1

C7336

68UF

20%
16V

2

POLY-TANT

=PPVIN_S0_DDRREG_LDO

8

VTT Enable

1

R7318

51.1K

1%
1/16W
MF-LF
402

2

CRITICAL

1

C7301

10UF

20%
10V

2

X5R-CERM

0402-1

PLACE_NEAR=U7300.2:1mm

12 15

V5IN

17

S3

16

19
18

TPS51916

S5

6

VREF

CRITICAL

8

REFIN

MODE
TRIP

PGND

10

DESCRIPTION

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

RES,MTL FILM,1/16W,60.4K,1,0402,SMD,LF

MOSFET,N-CH,30V,100MA,7.0OHM,SOT-723,HF

RES, MTL FILM,1/16W,150k,0402,SMD,LF

2

VLDOIN

U7300

QFN

VTT

GND

7

4

VDDQSNS

THRM

PADGND

VBST
DRVH

SW

DRVL

PGOOD

VTT

VTTSNS

VTTREF

21

XW7300

MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST

DDRREG_DRVH

14

DDRREG_LL

13

SWITCH_NODE=TRUE

DIDT=TRUE

DDRREG_DRVL

11

DDRREG_PGOOD

20

DDRREG_VDDQSNS

9

=PPVTT_S0_DDR_LDO

8

3
1

DDRREG_VTTSNS
=PPVTT_S3_DDR_BUF

5

10mA max load

2

C7350

0.22UF

SM

1

PLACE_NEAR=U7300.21:1mm

REFERENCE DES

R7316

R7316

Q7319

R7319

=PP5V_S3_DDRREG

8

CRITICAL

1

C7300

10UF

20%
10V

2

X5R-CERM

0402-1

PLACE_NEAR=U7300.12:1mm

C

DDRREG_FB

31

IN

=DDRVTT_EN

9

27

IN

=DDRREG_EN

66

IN

DDRREG_1V8_VREF

1

1

C7315

0.1UF

10%
16V

2

X7R-CERM

0402

PLACE_NEAR=U7300.6:1mm

OMIT_TABLE

DDRREG_P1V35_L

Q7319

SSM3K15FV

SOD-VESM-HF

CRITICAL

OMIT_TABLE

B

R7319

150K

1/16W
MF-LF

1

G S

1

1%

402

2

3

D

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

2

VOLTAGE=0V

MEM_VDD_SEL_1V5_L

R7315

20.0K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U7300.8:5mm

OMIT_TABLE

1

R7316

100K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U7300.8:5mm

IN

1

C7316

0.01UF

10%
16V

2

X7R-CERM
0402

PLACE_NEAR=U7300.8:1mm

24

PART NUMBER

114S0411

114S0391

376S0612

114S0428

1

R7317

200K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U7300.19:3mm

VDDQ/VTTREF Enable

DDRREG_MODE
DDRREG_TRIP

PLACE_NEAR=U7300.18:3mm

QTY

1

1

1

1

CASE-D2E-SM

NO_TEST=TRUE

GATE_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

C7360, C7361 close to memory

1

10%
10V

2

CERM

402

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

OUT

1

2

R7325

402

5%

0

1 2

9

XW7360

SM

1 2

PLACE_NEAR=C7361.1:3mm

CRITICAL

C7360

10UF

X5R-CERM

0603

PLACE_NEAR=C7361.1:1mm

CRITICAL

C7331

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

MF-LF

1/16W

1

20%
25V

2

BOM OPTION

PPDDR:1V5

PPDDR:1V35

PPDDR:1V5

PPDDR:1V5

CRITICAL

1

C7334

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PLACE_NEAR=Q7330.5:1mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST_RC

MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm

(DDRREG_LL)

CRITICAL

1

C7361

10UF

20%
25V

2

X5R-CERM
0603

PLACE_NEAR=C7360.1:3mm

OMIT_TABLE

1

C7332

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=Q7330.5:1mm

(DDRREG_DRVH)

C7325

0.1UF

1 2

10%
25V
X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

OMIT_TABLE

1

C7335

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=C7332.1:3mm

1

6

1

2

2

3 4 5

C7333

0.001UF

20%
50V
CERM
0402

PHASE

CRITICAL

Q7330

FDMS3602S

POWER56

0.68UH-18A-3.3MOHM

7

152S0905

CRITICAL

L7330

1 2

PCMB103T

CRITICAL

1

C7342

330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

CRITICAL

1

C7340

330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

CRITICAL

C7341

330UF

POLY-TANT

CASE-B2-SM1

2.0V

C

=PPDDR_S3_REG

Vout = 1.5V

15.5A max output

1

C7346

0.001UF

10%
50V

2

X7R-CERM

1

1

C7345

10UF

20%

20%
25V

2

2

X5R-CERM
0603

0402

2

XW7301

SM

1

PLACE_NEAR=C7340.1:1mm

(Q7335 limit)
f = 400 kHz

8

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

1.5V DDR3 Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=MASTER

<E4LABEL>

<BRANCH>

73 OF 132

60 OF 80

SIZE

A

D

8 7 6 5 4 3

12

=PP5V_S0_CPUIMVP

R7401

10

PP5V_S0_CPUIMVP_VCC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

D

C

VOLTAGE=5V

1

R7468

5.76K

1%
1/20W
MF
201

2

1

CRITICAL

2

R7469

100KOHM

0402

CPU_PROCHOT_L

11 39 40 72

OUT

1

R7466

5.76K

1%
1/20W
MF
201

2

1

CRITICAL

R7467

100KOHM

0402

2

=PPVCCIO_S0_CPUIMVP

8

1

C7450

47PF

5%
50V

2

CERM
402

OMIT

1

R7464

NOSTUFF

NONE
NONE
NONE
0201

2

1

R7465

200K

1%
1/20W
MF
201

2

66

IN

13 72

IN

13 72

IN

13 72

IN

CPUIMVP_VR_ON
CPU_VIDSOUT

CPU_VIDSCLK
CPU_VIDALERT_L

R7479

54.9

1/16W
MF-LF

PLACE_NEAR=U7400.23:2mm

1

R7462

196K

1%
1/20W
MF
201

2

1

R7463

137K

1%
1/20W
MF
201

2

1

1

R7480

130

1%

1%
1/16W
MF-LF

402

402

2

2

PLACE_NEAR=U7400.21:2mm

1

R7460

301K

1%
1/20W
MF
201

2

1

R7461

137K

1%
1/20W
MF
201

2

CPUIMVP_AXG_PWN2

62

OUT

CPUIMVP_PGOOD

66

OUT

CPUIMVP_AXG_PGOOD

9

OUT

CPUIMVP_NTC
CPUIMVP_NTCG

CPUIMVP_SLEW
CPUIMVP_IMAXA

CPUIMVP_IMAXB

C7401

2.2UF

20%
10V

X5R-CERM

402

1

2

13

DRVPWMB

37

DRVPWMA

NC

45

CSPA3

4

VRHOT*

24

POKA

12

POKB

47

EN

21

VDIO

23

CLK

22

ALERT*

39

THERMA

40

THERMB

38

SR

35

IMAXA

36

IMAXB

8

CSPBAVE

AGND

5

1 2

1/16W
MF-LF

462919

VCC

VDDA

U7400

MAX15119GTM

QFN

CRITICAL

GNDSB

GNDSA

2

7

20

49

5%

402

VDDB

CSPAAVE

PAD

THRM

BSTA1

CSPA1

CSPA2
BSTA2

CSPB2

CSPB1

CSNB

PGNDA

30

TONB

TONA

DHA1
LXA1
DLA1

CSNA

DHA2
LXA2
DLA2

BSTB

1

48

25

27

26
28
42

41
43
3

FBA

44
34
32
33
31

14
16

DHB

15

LXB

18

DLB

11
9
10
6

FBB

PGNDB

17

XW7400

CPUIMVP_TONB
CPUIMVP_TONA
CPUIMVP_BOOT1

CPUIMVP_UGATE1
CPUIMVP_PHASE1
CPUIMVP_LGATE1
CPUIMVP_ISUM1P

CPUIMVP_ISUM
CPUIMVP_ISUMN
CPUIMVP_FBA

CPUIMVP_ISUM2P
CPUIMVP_BOOT2
CPUIMVP_UGATE2
CPUIMVP_PHASE2
CPUIMVP_LGATE2

CPUIMVP_BOOT1G
CPUIMVP_UGATE1G
CPUIMVP_PHASE1G
CPUIMVP_LGATE1G

CPUIMVP_FBB

NO_TEST=TRUE

SM

1

12

2

1

C7402

2.2UF

20%
10V

2

X5R-CERM
402

PLACE_NEAR=U7400.29:2mm
PLACE_NEAR=U7400.19:2mm

Note: value needs scrubbing

C7418

100PF

5%
25V
CERM
201

R7402

182K

1 2

1%

1/20W

MF

201

NO STUFF

1

C7419

100PF

5%
25V

2

CERM
201

1

2

OUT
OUT
OUT
OUT

61

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

61

C7403

2.2UF

20%
10V
X5R-CERM
402

R7403

1 2

62

62

62

62

62

62

NO_TEST=TRUE

62

62

62

62

62

62

1

2

182K

1%

1/20W

MF

201

NO STUFF

C7414

100PF

5%
25V
CERM
201

8

NO STUFF

1

C7415

100PF

5%
25V

2

CERM
201

62

=PPVIN_S0_CPUIMVP

NO STUFF

1

C7416

100PF

5%
25V

2

CERM
201

IN

OUT

NO STUFFNO STUFF

1

C7423

100PF

5%
25V

2

CERM
201

8

62

NO_XNET_CONNECTION=TRUE

R7406

200

1 2

R7407

1 2

C7408

220PF

1 2

62

OUT

62

62

10%
25V

X7R-CERM

0201

C7409

1000PF

CPUIMVP_ISUM_R

1 2

10%
16V
X7R
201

R7410

1

1 2

5%

1/20W

MF

201

CPUIMVP_ISNS1_P

5%

1/20W

MF

NO_XNET_CONNECTION=TRUE

201

200

CPUIMVP_ISNS2_P

5%

1/20W

MF

201

CPUIMVP_ISUMG2P

CPUIMVP_ISUMG1P

NO_TEST=TRUE

CPUIMVP_ISUMGN

43 62 78

IN

43 62 78

IN

62

IN

62

IN

62

IN

D

C

GND_CPUIMVP_SGND

B

PLACE_NEAR=Q7510.1:1mm
PLACE_NEAR=Q7550.1:1mm

CPUIMVP_ISUMG_AVEP

62

IN

NO_TEST=TRUE

A

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0V

C7441

NO_XNET_CONNECTION=TRUE

1000PF

X7R-CERM

NO_XNET_CONNECTION=TRUE

10%
16V

0201

1

C7440

1000PF

10%
16V

2

X7R-CERM
0201

1

2

NO_XNET_CONNECTION=TRUE

R7440

10

CPU_AXG_SENSE_R

CPU_VCCSENSE_R CPU_VCCSENSE_N

NO STUFF

1

C7442

1000PF

10%
16V

2

X7R
201

NO STUFF

1

C7443

1000PF

10%
16V

2

X7R
201

PLACE HOLDERPLACE HOLDER

1 2

R7441

10

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

5%

1/20W

MF

201

CPU_AXG_SENSE_N

13 72

IN

CPUIMVP_FBA

61

13 72

IN

CPUIMVP_FBB

61

6 3

C7413

100PF

1 2

5%

50V
CERM
0402

R7412

8.06K

1 2

1%
1/16W
MF-LF

402

CPUIMVP_FBA_R

R7422

16.9K

1 2

1%
1/16W
MF-LF

402

NO_XNET_CONNECTION=TRUE

1

C7412

1000PF

10%
16V

2

X7R-CERM
0201

CPUIMVP_FBB_R

R7413

10

1

C7422

1000PF

10%
16V

2

X7R-CERM
0201

SYNC_MASTER=MASTER

PAGE TITLE

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

R7423

10

1 2

5%

1/20W

MF

201

CPU_VCCSENSE_P

CPU_AXG_SENSE_P

CPU IMVP7 & AXG VCore Regulator

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

13 72

IN

13 72

IN

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=MASTER

<E4LABEL>

<BRANCH>

74 OF 132

61 OF 80

SIZE

B

A

D

8 7 6 5 4 3

=PPVIN_S0_CPUIMVP

8

61 62

PHASE 1

CPUIMVP_BOOT1

61

IN

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1

61

IN

D

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

61

IN

MIN_LINE_WIDTH=0.6 MM

61

IN

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1

DIDT=TRUE

GATE_NODE=TRUE

=PPVIN_S0_CPUIMVP

8

61 62

PHASE 2

CPUIMVP_BOOT2

61

IN

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

C

CPUIMVP_UGATE2

61

IN

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

61

IN

61

IN

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

CPUIMVP_PHASE2

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE2

MIN_LINE_WIDTH=0.5 MM

=PPVIN_S0_CPUAXG

8

AXG PHASE 1

B

CPUIMVP_BOOT1G

61

IN

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1G

61

IN

MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM

61

IN

61

IN

CPUIMVP_PHASE1G

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1G

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

R7551

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_BOOT1_RC

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

1

R7511

0

5%
1/16W
MF-LF

402

2

DIDT=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_BOOT2_RC

R7521

1/16W
MF-LF

DIDT=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_BOOT1G_RC

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

1

0

5%

C7551

1/16W

0.22UF

MF-LF

402

2

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

1

C7511

0.22UF

10%
10V

2

CERM
402

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

0

5%

402

10%
10V

CERM

402

DIDT=TRUE

1

2

1

C7521

2

1

2

0.22UF

10%
10V

376S1010

CERM
402

376S1010

376S1010

4

CRITICAL

1

C7513

68UF

20%
16V

2

POLY-TANT

7

8

CRITICAL

Q7510

D

IRF6802SDTRPBF

G

2

DIRECTFET-SA

S

3

CASE-D2E-SM

NCNC

128

7

CRITICAL

D

Q7515

S

5

6

CRITICAL

Q7510

D

IRF6802SDTRPBF

DIRECTFET-SA

S

4

649135PBF

DIRECTFET_S3C

376S1011

CRITICAL

1

C7523

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7524

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

G

4

356

G

1

NCNC

128

7

CRITICAL

D

Q7525

S

6

CRITICAL

Q7550

IRF6802SDTRPBF

DIRECTFET-SA

7

CRITICAL

Q7551

649135PBF

DIRECTFET_S3C

S

649135PBF

DIRECTFET_S3C

376S1011

1

2

376S1011

CRITICAL

C7553

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7554

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

0.36UH-20%-36A-0.00108OHM

L7550

1 2

PIMS103T-SM

152S1538

G

4

356

5

D

G

1

S

4

NCNC

128

D

G

356

AXG PHASE 2

=PP5V_S0_CPUIMVP

8

61

AXG_PHASE2

1

AXG_PHASE2

1

R7540

10K

5%
1/16W
MF-LF
402

A

2

CPUIMVP_AXG_PWN2

61

IN

CPUIMVP_SKIP

AXG_PHASE2

2

PWN

6

SKIP*

5

VDD

U7542

MAX17491

TQFN

CRITICAL

THRM

GND

3

PAD

1

BST

8

DH

7

LX

4

DL

9

C7541

1UF

10%
16V

2

X5R
402

CPUIMVP_BOOT2G

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE2G

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE2G

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE2G

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

AXG_PHASE2

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

CPUIMVP_BOOT2G_RC

MIN_LINE_WIDTH=0.25 MM

R7542

1/16W
MF-LF

402

DIDT=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

1

0

5%

2

OMIT_TABLE

CRITICAL

1

C7515

4.7UF

10%
35V

2

X5R-CERM
0603

0.36UH-20%-36A-0.00108OHM

NOSTUFF

CRITICAL

1

C7525

4.7UF

10%
35V

2

X5R-CERM
0603

0.36UH-20%-36A-0.00108OHM

OMIT_TABLE

CRITICAL

1

C7516

4.7UF

10%
35V

2

X5R-CERM
0603

PLACE_NEAR=Q7510.1:1mm

CRITICAL

L7510

1 2

PIMS103T-SM

152S1538

NOSTUFF

CRITICAL

1

C7526

4.7UF

10%
35V

2

X5R-CERM
0603

PLACE_NEAR=Q7510.1:1mm

1 2

CRITICAL

L7520

PIMS103T-SM

152S1538

THESE TWO CAPS ARE FOR EMC

1

2

THESE TWO CAPS ARE FOR EMC

OMIT_TABLE

1

C7517

1.0UF

10%
35V

2

CERM-X5R
0402

PPVCORE_S0_CPU_PH1

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.25V

OMIT_TABLE

C7527

1.0UF

10%
35V
CERM-X5R
0402

PLACE_NEAR=C7527.1:3mm

PPVCORE_S0_CPU_PH2

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.25V

Removed snubber with EMC’s comment

NO_XNET_CONNECTION=TRUE

NOSTUFF

CRITICAL

1

C7555

4.7UF

10%
35V

2

X5R-CERM
0603

PPVCORE_S0_AXG_R

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

CPUIMVP_ISNS1G_P

NO_XNET_CONNECTION=TRUE

AXG_PHASE2

1

C7542

0.22UF

10%
10V

2

CERM
402

NOSTUFF

CRITICAL

1

C7556

4.7UF

10%
35V

2

X5R-CERM
0603

R7553

46.4

1/20W

PLACE_NEAR=Q7550.1:1mm

R7550

0.00075

1%
1W
MF

0612

1 2
3 4

1

1%
MF

201

2

1

C7518

0.001UF

10%
50V

2

X7R-CERM
0402

PLACE_NEAR=C7517.1:3mm

NO_XNET_CONNECTION=TRUE

1

C7528

0.001UF

10%
50V

2

X7R-CERM
0402

NOSTUFF

R7598

NO_XNET_CONNECTION=TRUE

OMIT_TABLE

THESE TWO CAPS ARE FOR EMC

1

C7557

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=C7557.1:3mm

CRITICAL

200

1/20W

201

1%
MF

1

2

1

C7558

0.001UF

10%
50V

2

X7R-CERM
0402

1

2

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS1G_N

1

R7554

10

NO_XNET_CONNECTION=TRUE

1%
1/20W
MF
201

2

CPUIMVP_ISUMGN

1

C7574

2200PF

10%
10V

2

X7R-CERM

CPUIMVP_ISUMG1P

0201

1

C7519

0.001UF

10%
50V

2

X7R-CERM
0402

NOSTUFF

1

R7599

200

1%

1/20W

MF

201

2

NO_XNET_CONNECTION=TRUE

CRITICAL

46.4

1/20W

OUTOUT

IN

IN

CRITICAL

R7520

0.00075

1 2
3 4

1

1%
MF

201

2

1

C7559

2

43 78 43 62 78

61 62

61

1

C7522

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1%
1W
MF

0612

0.001UF

10%
50V
X7R-CERM
0402

1

R7524

10

1%
1/20W
MF
201

2

C7529

0.001UF

10%
50V
X7R-CERM
0402

R7523

PLACE_NEAR=U7400.10:1mm

CRITICAL

1

C7510

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

R7510

0.00075

1%
1W
MF

0612

1 2
3 4

1

R7513

46.4

1/20W

201

1%
MF

1

R7514

10

2

2

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS2_N
CPUIMVP_ISNS2_P

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U7400.43:1mm

1

C7572

2200PF

10%
10V

2

X7R-CERM
0201

CRITICAL

1

C7560

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

376S1010

8

62

4

61 62

OUT

G

2

G

CPUIMVP_ISUMGN

CRITICAL

1

C7512

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PART NUMBER

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS1_N
CPUIMVP_ISNS1_P

NO_XNET_CONNECTION=TRUE

1%
1/20W
MF
201

PART NUMBER

138S0811

OUT
OUT

CPUIMVP_ISUMN

CPUIMVP_ISUM2P

7

8

CRITICAL

Q7550

D

IRF6802SDTRPBF

DIRECTFET-SA

S

3

NCNC

128

7

AXG_PHASE2

CRITICAL

D

Q7561

649135PBF

DIRECTFET_S3C

376S1011

S

356

NO_XNET_CONNECTION=TRUE

QTY

4

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

8

62

43 78

OUT

43 61 78

OUT

CPUIMVP_ISUMN

PLACE_NEAR=U7400.43:1mm

1

C7571

2200PF

10%
10V

2

X7R-CERM
0201

CPUIMVP_ISUM1P

QTY

4

CAP,CER,4.7UF,10%,25V,X6S,0603

8

62

43 78

43 61 78

61 62

IN

61

IN

CRITICAL

1

C7561

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7562

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

0.36UH-20%-36A-0.00108OHM

1 2

PIMS103T-SM

43 78 43 78

OUT OUT

Removed snubber with EMC’s comment

1

R7563

200

1%

1/20W

MF

201

2

CPUIMVP_ISUMG_AVE_RP

NO_TEST=TRUE

C7568

1000PF

X7R-CERM

0201

10%
16V

1

2

DESCRIPTION

61 62

IN

61

IN

DESCRIPTION

OMIT_TABLE

CRITICAL

1

C7563

4.7UF

10%
35V

2

X5R-CERM
0603

AXG_PHASE2

CRITICAL

L7560

PPVCORE_S0_AXG2_L

152S1538

CPUIMVP_ISNS2G_P

CPUIMVP_ISNS1G_P

AXG_PHASE2

1

R7564

200

NO_XNET_CONNECTION=TRUE
1%
1/20W
MF
201

2

1

R7566

0

5%
1/20W
MF
201

2

NOSTUFF

1

C7569

330PF

10%
16V

2

X7R
201

REFERENCE DES

C7517,C7527,C7557,C7565

REFERENCE DES

C7515,C7516,C7563,C7564

CRITICAL

1

C7550

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

OMIT_TABLE

CRITICAL

1

C7564

4.7UF

10%
35V

2

X5R-CERM
0603

PLACE_NEAR=Q7560.1:1mm

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

AXG_PHASE2

NO_XNET_CONNECTION=TRUE

CRITICAL

1

C7552

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

THESE TWO CAPS ARE FOR EMC

OMIT_TABLE

1

C7565

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=C7565.1:3mm

AXG_PHASE2

CRITICAL

R7560

0.00075

1%
1W
MF

0612

1 2
3 4

1

R7561

46.4

1%

1/20W

MF

201

2

43 62 78

OUT

CPUIMVP_ISUMG_AVEP

SYNC_MASTER=MASTER

PAGE TITLE

CPU IMVP7 & AXG VCore Output

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

CRITICAL138S0812

CRITICAL

CRITICAL

1

C7566

0.001UF

10%
50V

2

X7R-CERM
0402

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS2G_N

AXG_PHASE2

1

R7562

10

1%
1/20W
MF

NO_XNET_CONNECTION=TRUE

201

2

CPUIMVP_ISUMGN

PLACE_NEAR=U7400.10:1mm

1

C7573

2200PF

10%
10V

2

X7R-CERM
0201

CPUIMVP_ISUMG2P

61

OUT

6 3

1

C7567

0.001UF

10%
50V

2

X7R-CERM
0402

AXG_PHASE2

12

BOM OPTION

BOM OPTION

CRITICAL

1

2

8

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

75 OF 132

SHEET

62 OF 80

124578

C7580

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

62

61 62

OUT

61

OUT

SYNC_DATE=MASTER

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

CPU_VCCIOSENSE_P

13 72

CPU_VCCIOSENSE_N

C

13 72

1

402

402

1

R7644

3.01K

1%

1%
1/16W
MF-LF
402

2

2

<Ra>

1

1

R7645

2.74K

1%

1%
1/16W
MF-LF
402

2

2

<Rb>

1

C7604

47PF

50V

CERM

402

1

C7605

5%

47PF

5%
50V

2

2

CERM
402

C7602

1

C7603

0.047UF

10%
16V

2

X7R-CERM
0402

66

66

2.2UF

R7604

3.01K

1/16W
MF-LF

R7605

2.74K

1/16W
MF-LF

B

PP5V_S0_CPUVCCIOS0_VCC

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

IN

OUT

1

1

10%
16V

2

X5R
603

2

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

CPU VCCIO (1.05V S0) Regulator

=PPVIN_S0_CPUVCCIOS0

8

=PP5V_S0_CPUVCCIOS0

8

=CPUVCCIOS0_EN
CPUVCCIOS0_FB
CPUVCCIOS0_SREF
CPUVCCIOS0_VO
CPUVCCIOS0_OCSET
CPUVCCIOS0_PGOOD
CPUVCCIOS0_RTN
CPUVCCIOS0_FSEL
NOSTUFF

R7603

0

5%
1/16W
MF-LF
402

CPUVCCIOS0_AGND

1

R7601

2.2

5%
1/16W
MF-LF

402

2

13

VCC

U7600

ISL95874

3

6

4

8

7

9

2

5

UTQFN

EN

CRITICAL

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

GND

1

XW7600

SM

1 2

PLACE_NEAR=U7600.1:1mm

PVCC

PGND

1

2

14

BOOT

UGATE

PHASE

LGATE

16

CPUVCCIOS0_VBST_RC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

1

C7601

10UF

20%
10V
X5R-CERM
0402-1

R7630

0

2

CPUVCCIOS0_VBST

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

12

11

10

CPUVCCIOS0_LL

MIN_NECK_WIDTH=0.2 mm

15

SWITCH_NODE=TRUE
DIDT=TRUE

5%
1/16W
MF-LF
402

CPUVCCIOS0_DRVH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

CPUVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

(CPUVCCIOS0_OCSET)

(CPUVCCIOS0_VO)

1

2

C7630

1UF

10%
16V
X5R
402

PART NUMBER

CRITICAL

1

C7620

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

2

1

6

3 4 5

OCP = R7641 x 8.5uA / R7640
OCP = 26.265A
Vout = 0.5V * (1 + Ra / Rb)

CRITICAL

Q7630

RJK0230DPA

WPAK

0.36UH-20%-36A-0.00108OHM

7

QTY

138S0812 CRITICAL

CRITICAL

1

C7621

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

152S1538

CRITICAL

L7630

1 2

PIMS103T-SM

R7631

2.2

5%
1/10W
MF-LF
603

NOSTUFF

R7641

3.48K

1%
1/16W
MF-LF

402

12

PPCPUVCCIO_S0_REG_R

DIDT=TRUE

NOSTUFF

1

C7640

2

1000PF

12

5%

25V

NP0-C0G

402

DESCRIPTION

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

CRITICAL

1

C7626

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

MIN_LINE_WIDTH=0.6 mmMIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

CPUVCCIOS0_SNUB

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

NO_TEST=TRUE

1

C7631

0.001UF

10%
50V

2

CERM
402

CPUVCCIOS0_CS_P

43 78

CPUVCCIOS0_CS_N

43 78

1

R7642

3.48K

1%
1/16W
MF-LF
402

2

CRITICAL

R7640

0.001

REFERENCE DES

1

C7622

0.001UF

20%
50V

2

CERM
0402

PLACE_NEAR=C7624.1:3mm

2%
1W
MF

0612

12
34

C7627

270UF

CASE-B2-SM

C7624

OMIT_TABLE

1

C7624

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=Q7630.2:1mm

1

20%

2V

2

TANT

C7625

270UF

CASE-B2-SM

TANT

20%

2V

CRITICAL

1

2

C7623

0.001UF

CERM
0402

BOM OPTION

=PPCPUVCCIO_S0_REG

20%
50V

Vout = 1.05V

20.5A Max Output

1

2

f = 500 kHz

8

D

C

B

A

SYNC_MASTER=MASTER

PAGE TITLE

CPUVCCIO (1.05V) Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

76 OF 132

SHEET

63 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

=PP3V3_S0_P1V5S0

D

8

66

IN

66

OUT

=P1V5S0_EN
P1V5S0_PGOOD

353S2535

2

EN

3

POR

SKIP

1

VIN

U7770

ISL8009B

DFN

CRITICAL

GND

THRM_PAD

7

CRITICAL

1

C7770

22UF

20%

6.3V

2

X5R
0603

8

LX

6

VFB

54

RSI

9

P1V5_S0_SW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE
DIDT=TRUE

P1V5_S0_FB

152S1051

CRITICAL

L7770

2.2UH-2A-0.155-OHM

1 2

2512

C7776

47PF

5%

50V

CERM

402

=PP1V5_S0_REG

8

Vout = 1.508V

1

R7780

1

100K

1%
1/16W
MF-LF

2

402

2

<Ra>

1

R7781

113K

1%
1/16W
MF-LF
402

2

<Rb>

Max Current = 1.5A
Freq = 1.6MHZ

CRITICAL

1

C7773

22UF

20%

6.3V

2

X5R
0603

Cougar Point requires JTAG pull-ups to be powered at 1.05V in SUS.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

=PP3V3_SUS_P1V05SUSLDO

8

1.5V S0 Switcher

1.05V SUS LDO

CRITICAL

XDP_PCH

U7740

TPS720105

SON

4

XDP_PCH

C7740

1UF

6.3V
CERM

10%

402

BIAS

6

IN

3

EN

1

2

GND
5

THRM

PAD

7

OUT

1

2

NC

NC

1

2

=PP1V05_SUS_LDO

8

Vout = 1.05V
Max Current = 0.35A

XDP_PCH

C7741

2.2UF

10%

6.3V
X5R
402

D

Vout = 0.8V * (1 + Ra / Rb)

C

=PP3V3_S0_P1V8S0

8

1

C7760

22UF

20%

6.3V

2

X5R
0603

PLACE_NEAR=C7768.1:3mm

66

1

C7764

0.022UF

10%
16V

2

X5R-X7R-CERM
0402

P1V8S0_SS

P1V8_S0_COMP_RC

1

C7765

0.0015UF

10%
50V

2

X7R-CERM
0402-1

1.8V S0 Switcher

1

2

=P1V8S0_EN

IN

R7765

3.24K

1 2

1/16W
MF-LF

C7761

0.1UF

10%
25V
X5R
402

1%

402

1

C7768

1UF

10%

6.3V

2

X5R

PLACE_NEAR=U7760.A3:1mm

402

P1V8S0_COMP

NO_TEST=TRUE

B2

B3

C2

C1

B1

U7760

MAX15053EWL

WLP

SKIP

CRITICAL

EN

SS/REFIN

FB

COMP

GND

A1

IN

LX

PGOOD

P1V8SO_FB

A3

A2
C3

P1V8S0_SW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

P1V8S0_PGOOD

MAX CURRENT = 2A

152S1415

1.0UH-20%-4.5A-24MOHM

1 2

1

R7767

10K

1%
1/16W
MF-LF

66

OUT

402

2

P1V8_S0_RC

1

C7767

100PF

5%
50V

NOSTUFF

2

CERM
402

F = 1MHZ

CRITICAL

L7760

PIMB042T-SM

NOSTUFF

1

R7760

20.0K

1%
1/16W
MF-LF
402

2

1

R7761

10K

1%
1/16W
MF-LF
402

2

1

C7766

100PF

5%
50V

2

CERM
0402

1

C7762

22UF

20%

6.3V

2

X5R
0603

=PP1V8_S0_REG

1

C7772

22UF

20%

6.3V

2

X5R
0603

1

C7763

0.1UF

10%
25V

2

X5R
402

8

Vout = 1.8V

C

SIZE

B

A

D

B

=PP5V_S4_P1V05TBTS0

8

C7724

1000PF

X7R-CERM

35

35

1

10%
16V

2

0201

IN

OUT

CRITICAL

C7720

22UF

20%

6.3V
X5R

0603

TBT_EN_LC_ISOL

P1V05TBTS0_PGOOD

1

2

5

EN

7

PG

4

SYNCH

SGND

9

10

1

2

VIN

U7720

ISL8014A

QFN

CRITICAL

PGND

11

12

3

VDD

THRM_PAD

17

VFB

LX
LX

NC

A

1.05V TBT S0 Regulator

152S1415

L7720

1.0UH-20%-4.5A-24MOHM

PIMB042T-SM

14

15

8

16

6
13

P1V05TBTS0_SW

SWITCH_NODE=TRUE
DIDT=TRUE

P1V05TBTS0_FB

NC
NC
NC

1 2

CRITICAL

R7720

1/20W

28K

1%

MF

201

<Ra>

R7721

90.9K

1%
1/16W
MF-LF

402

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

6 3

=PP1V05_S0_P1V05TBTREG_R

22UF

1

20%

6.3V
2

X5R

0603

Vout = 1.05V
Max Current = 3A
Freq = 1 MHz

1

C7723

47PF

5%

1

2

1

2

25V

2

NP0-C0G-CERM
0201

CRITICAL

1

C7721

22UF

20%

6.3V

2

X5R
0603

CRITICAL

C7722

80

8

SYNC_MASTER=MASTER

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

77 OF 132

SHEET

64 OF 80

124578

8 7 6 5 4 3

NOSTUFF

R7803

0

1 2

5%
1/16W
MF-LF

402

=PP3V3_S5_P3V3SUSFET

8

1

=PP3V3_S4_FET

MOSFET

CHANNEL

RDS(ON)

LOADING

1

D

=PP3V3_S3_FET

MOSFET SiA427

CHANNEL

RDS(ON)

LOADING

1

=PP5V_S3_FET

MOSFET

CHANNEL

RDS(ON)

LOADING

8

3.3V S4 FET

3.3V S3 FET

8

5V S3 FET

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

0.7? A (EDP)

8

P-TYPE 8V/5V

26 mOhm @1.8V

3 A (EDP)

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

3 A (EDP)

5V_SUS FET INPUT FILTER

=PP5V_S5_P5VSUSFET

8

PLACE_NEAR=Q7840.4:5mm

66

IN

=P3V3S0_EN

66

R7843

0

1 2

5%
1/16W
MF-LF

402

66

IN

IN

8

=P3V3SUS_EN

NO STUFF

C7843

2.2UF

20%
10V

X5R-CERM

402

=P5VSUS_EN

=PP3V3_S0_P3V3S0FET

Q7812

SSM6N37FEAPE

Q7802

SSM6N37FEAPE

SOT563

5

PP5V_S5_P5VSUSFET_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MM

1

VOLTAGE=5V

Q7842

2

SSM3K15FV

SOD-VESM-HF

1

G S

3

D

SOT563

5

SG

4

3

2

R7832

R7822

100K

5%
1/16W
MF-LF

402

R7842

220K

1/16W
MF-LF

402

1

47K

5%
1/16W
MF-LF

402

2

P3V3S0_EN_L

3

D

SG

4

D

4 7

CRITICAL

Q7850

SIA427DJ

4 7

376S0945

CRITICAL

Q7800

SIA427DJ

SC70-6L

S

3

CRITICAL

Q7810

SIA427DJ

4 7

SC70-6L

S

G

3

G

SC70-6L

S

3

C7850

0.01UF

1 2

X7R-CERM

C7800

0.01UF

1 2

G

10%
16V

0402

X7R-CERM

0402

C7810

0.01UF

1 2

X7R-CERM

D

D

10%
16V

10%
16V

0402

3.3V S4 FET

=PP3V3_S4_P3V3S4FET

8

1

D

=P3V3S4_EN

66

IN

SSM6N37FEAPE

SOT563

2

SG

1

6

D

Q7802

R7802

220K

5%
1/16W
MF-LF

402

2

P3V3S4_EN_L

1

C7809

0.033UF

R7800

5.1K

5%
1/16W
MF-LF

402

1

10%
16V

2

X5R
402

2

P3V3S3_S4

3.3V S3 FET

=PP3V3_S3_P3V3S3FET

8

R7810

47K

1/16W
MF-LF

402

C7811

0.033UF

5%

1

10%
16V

2

X5R
402

P3V3S3_SS

1

6

D

Q7812

SSM6N37FEAPE

SOT563

2

SG

=P3V3S3_EN

66

IN

1

R7812

100K

5%
1/16W
MF-LF

402

2

P3V3S3_EN_L

1 2

5V S3 FET

C

66

IN

=P5VS3_EN

=PP5V_S4_P5VS3FET

8

Q7852

SSM3K15FV

SOD-VESM-HF

1

G S

R7850

47K

1/16W
MF-LF

C7851

0.033UF

5%

402

1

10%
16V

2

X5R
402

P5VS3_SS

D

2

100K

5%
1/16W
MF-LF

402

2

P5VS3_EN_L

1 2

1

R7852

3

1

2

P3V3SUS_EN_L

1

5%

2

P5VSUS_EN_L

3.3V SUS FET

C7821

0.033UF

10%
16V
X5R
402

R7820

12K

1 2

5%
1/16W
MF-LF

402

5V SUS FET

C7841

0.033UF

10%
16V
X5R
402

R7840

3.3K

1 2

5%
1/16W
MF-LF

402

3.3V S0 FET

C7831

0.033UF

10%
16V

X5R
402

R7830

33K

1 2

5%
1/16W
MF-LF

402

CRITICAL

Q7820

SIA427DJ

SC70-6L

S

4 7

1

CRITICAL

Q7840

SIA413DJ

4 7

CRITICAL

PWRPK-1212-8

3

SC70-6L

S

3

Q7830

SI7615DN

2

P3V3SUS_SS

1

2

P5VSUS_SS

S

1

2

P3V3S0_SS

1 2 3

G

4

G

G

C7820

0.01UF

1 2

X7R-CERM

C7840

0.01UF

1 2

X7R-CERM

C7830

0.01UF

1 2

10%
16V

X7R-CERM

0402

1

D

=PP3V3_SUS_FET

8

3.3V SUS FET

MOSFET SiA427

CHANNEL

=PP5V_SUS_FET

RDS(ON)

LOADING

8

10%
16V

0402

1

D

5V SUS FET

MOSFET

CHANNEL

=PP3V3_S0_FET

RDS(ON)

LOADING

8

3.3V S0 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

10%
16V

0402

D

5

12

P-TYPE 8V/5V

26 mOhm @1.8V

100? mA (EDP)

SiA413

P-TYPE 12V

29 mOhm @4.5V

2 mA (EDP)

SI7615DN

P-TYPE 20V/12V

5.5 mOhm @4.5V

5.6 A (EDP)

D

C

1.5V S3/S0 FET

=PPVIN_S3_P1V5S3RS0_FET

D

G

S

PG

5

7

P1V5S3RS0FET_GATE

6

8

8

1.5V S3/S0 FET

R7801

0

1 2

5%
1/16W
MF-LF

402

P1V5S3RS0FET_GATE_R

APN 376S0651

5

CRITICAL

D

Q7801

S

1 2 3

SI7108DN

PWRPK-1212-8-HF

4

G

=PP1V5_S3RS0_FET

MOSFET

CHANNEL

RDS(ON)

LOADING

8

SI7108DN

N-TYPE

6 mOhm @4.5V

5 A (EDP)

B

=PP5V_S5_P1V5S3RS0FET

8

1

C7801

0.1UF

20%
10V

2

CERM

402

P1V5CPU_EN

27

IN

B

NO STUFF

C7802

1

1UF

10%
10V

2

X5R

402

2

3

ON

SHDN*

1

VCC

U7801

SLG5AP020

TDFN

CRITICAL

THRM

GND

PAD

4

9

P1V5S3RS0_RAMP_DONE

A

9

OUT

5.0V S0 FET

=PP5V_S4_P5VS0FET

8

1

R7862

220K

5%
1/16W
MF-LF

402

2

P5V0S0_EN_L

Q7865

SSM3K15FV

SOD-VESM-HF

=P5VS0_EN

66

IN

1

G S

3

D

2

R7860

10K

1 2

1/16W
MF-LF

402

5%

C7861

0.033UF

1

10%
16V

2

X5R
402

P5V0S0_SS

6 3

S

1 2 3

CRITICAL

Q7860

SI7615DN

PWRPK-1212-8

G

4

=PP5V_S0_FET

D

5

C7860

0.01UF

1

2

10%
16V

X7R-CERM

0402

SYNC_MASTER=MASTER

PAGE TITLE

5.0V S0 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

Power FETs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

SI7615DN

P-TYPE 20V/12V

5.5 MOHM @4.5V

5 A (EDP)

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

78 OF 132

SHEET

65 OF 80

124578

SIZE

A

D

D

C

8

66

B

8

S0PGOOD_ISL

R7960

A

S0PGOOD_ISL

R7961

59

OUT

SMC_PM_G2_EN

39 40

IN

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

8

59

24 39 66

=PP3V3_S0_VMON

1

R7951

2

1

R7952

7.15K

1%
1/16W
MF-LF
402

2

66

66

Thresholds:
VDD: 2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V

=PP5V_S0_VMON

6.04K

=PP1V5_S3RS0_VMON

8

66

1

S0PGOOD_ISL

R7970

1%
1/16W
MF-LF

402

2

1/16W
MF-LF

P5V_DIV_VMON

1

S0PGOOD_ISL

15.0K

R7971

1%
MF-LF

402

12.4K

1/16W

2

MF-LF

1/16W

8 7 6 5 4 3

Mobile System Power State Table

SMC_ADAPTER_EN

toggle 3Hz

X
1
0
1
0
1
0

1

SMC_PM_G2_ENABLE

1
1
1
1
1
1
1
0
0

SMC_S4_WAKESRC_EN

1
1
1
1
1
0 0
0
0
0

PM_SUS_EN

1
1
1
0
0

0
0
0

PM_SLP_S5_L

1
1
1
0
0
0
0
0
0 0

3.3V S4 ENABLE

PM_SLP_S5_L:100K pull down on PCH page

PM_SLP_S5_L

18 39

IN

0.1uF

CERM

20%
10V

402

1

2

5

VCC

U7940

74AUP1G3208

SOT891

1

A

3

B

6

C

GND

2

4

44

Y

6

2

1

NC

5

3

NC

PM_SUS_EN

MAKE_BASE=TRUE

U7970

74LVC1G32

SOT891

4

P5V3V3_S4_EN

MAKE_BASE=TRUE

NOSTUFF

R7915

1 2

=P5VSUS_EN
=P3V3SUS_EN

NO STUFF

R7917

0

1 2

5%
1/16W
MF-LF

402

1

C7930

0.1uF

20%
10V

CERM

6

VDD

SOT23-6

GND

2

402

RESET*

MR*

SSM6N37FEAPE

SMC_ADAPTER_EN

IN IN

R7933

2

15

PM_RSMRST_L

PM_RSMRST_L goes to U1800.C21

3

NC

"WLAN" = ("S3" && "AP_PWR_EN")

NOTE: S3 term is guaranteed by S3 pull-up

on open-drain AP_PWR_EN signal.

Q7920

SOT563

=PP3V3_SUS_CNTRL

1

100K

5%
1/16W
MF-LF

402

2

6

D

2

SG

1

18

OUT

NO STUFF

R7929

1/16W
MF-LF

402

1

0

5%

2

18 27 36 39 66

PM_SLP_S3_LPM_SLP_S4_L

1
1
1
0
0
0
0
0

1
0
0
0
0
0
0
0
0

0

5%
1/16W
MF-LF

402

PM_SLP_S3_L:100K pull down in PCH page

8

66

25

24 39 66

IN

61

IN

7

18 27 36 39 66

IN

65

OUT

65

OUT

=PP3V3_S5_PCHPWRGD

8

=PP3V3_S0_SB_PM

8

ALL_SYS_PWRGD

CPUIMVP_PGOOD

AC_EN_L

Q7920

SSM6N37FEAPE

PM_SLP_S3_L

7

=TBTAPWRSW_EN
=TBTBPWRSW_EN

=P3V3S4_EN

=P5VS4_EN

S0 ENABLE

PM_SLP_S3_L

CHGR VFRQ Generation

=PP3V42_G3H_CHGR

8
57

Q7931

SSM3K15FV

SOD-VESM-HF

1

G S

PLACE_NEAR=U1800.P12:7mm

6

D

S G

1

3

D

SOT563

5

SG

4

7

18 27 36 38 39

PM_SLP_S4_L:100K pull down in PCH page

69

OUT

70

OUT

65

OUT

47 59

OUT

R7978

100

1 2

5%
1/16W
MF-LF

402

R7931

100K

5%
1/16W
MF-LF

1 2

402

CHGR_VFRQ

3

D

2

R7950

1/16W
MF-LF

OUT

1

1K

5%

402

2

1

A

U7950

2

B

SMC_DELAYED_PWRGD

35 39 40

PM_WLAN_EN_L

Q7925

SSM6N15AFE

SOT563

2

AP_PWR_EN

=P5VS5_EN

PLACE_NEAR=U7201.20:7mm

R7941

100K

1/16W
MF-LF

P3V3S5_PGOOD

R7974

=PP3V3_S5_VMON

8

15.0K

1%
1/16W
MF-LF
402

VMON_3V3_DIV

=PP1V5_S3RS0_VMON

8

PP1V5_S3RS0

=PP1V05_S0_VMON

8

S0PGOOD_ISL

=PP1V05_S0_VMON

8

66

1

S0PGOOD_ISL

10K

R7972

1%

6.04K

1%

1/16W

402

2

MF-LF

402

P1V5_DIV_VMON

1

S0PGOOD_ISL

R7973

1%

15.0K

1%

1/16W

402

2

MF-LF

402

S5 Rail Enables & PGOOD

R7940

100

1 2

5%
1/16W
MF-LF

PLACE_NEAR=U7201.21:7mm

1

5%

402

2

402

S5_PWRGD

MAKE_BASE=TRUE

1

C7942

0.0033UF

10%
50V

2

CERM
402

NO STUFF

OUT

CPUVCORE ENABLE

0

1 2

5%

PLACE_NEAR=U7400.7:5mm

1/16W
MF-LF

402

1

R7956

150K

1%
1/16W
MF-LF

402

2

R7953

1K

1 2

5%
1/16W
MF-LF

402

R7954

1K

1 2

5%
1/16W
MF-LF

402

R7955

1K

1 2

5%
1/16W
MF-LF

402

Worst-Case Thresholds:

VMON_Q2_BASE

VMON_Q3_BASE

VMON_Q4_BASE

Q2: 0.XXXV
Q3: 0.640V

3.3V w/Divider: 2.345V
Q4: 0.660V

S0PGD_C

NC

NC

S0 Rail PGOOD Circuitry

(ISL Version in development)

=PP3V3_S0_VMON

8

66

1

C7960

0.1uF

20%
10V

CERM

402

1

2

P1V05_VID_VMON

1

2

2

ISL88042IRTEZ

3

V2MON

5

V3MON

6

2

VDD

U7960

TDFN

CRITICAL

GND

4

S0PGOOD_ISL

7

THRM_PAD

P3V3S5_EN

MAKE_BASE=TRUE

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

SMC-->PM_DSW_PWRGD

39

CPUIMVP_VR_ONALL_SYS_PWRGD

=P3V3S5_EN

61

OUT

S0 Rail PGOOD (BJT Version)

ALL_SYS_PWRGD

6

4

Q7950

Q1

5

8

7

2

1

(IPU)

MR*

RST*V4MON

9

353S2310

Q2

Q3

CRITICAL

Q4

3

R7957

1/16W
MF-LF

64

64

59

63

58

1

8

ASMCC0179

DFN2015H4-8

353S2809

S0PGD_BJT_GND_R

1

100

5%

402

2

P1V5S0_PGOOD

IN

P1V8S0_PGOOD

IN

P5VS4_PGOOD

IN

CPUVCCIOS0_PGOOD

IN

PVCCSA_PGOOD

IN

NC

S0PGOOD_ISL

R7962

ALL_SYS_PWRGD_R

1 2

=PP3V3_S0_PWRCTL

8 9

R7968

100

1 2

5%
1/16W
MF-LF

402

NO STUFF

R7965

100

1 2

5%
1/16W
MF-LF

402

R7969

100

1 2

5%
1/16W
MF-LF

402

330

5%
1/16W
MF-LF

402

Run (S0)

Sleep (S3AC)

Sleep (S3)

59

OUT

=PP3V3_S5_PWRCTL

8

66

PLACE_NEAR=U7940.1:2.3mm

SMC_BATLOW_L:100K pull up on SMC page

PM_SLP_SUS_L:100K pull down on PCH page

=PP3V3_SUS_CNTRL

8

66

Deep Sleep (S4AC)

Deep Sleep (S4)

Deep Sleep (S5AC)

Deep Sleep (S5)

Battery Off (G3HotAC)

Battery Off (G3Hot)

C7970

0.1uF

SMC_S4_WAKESRC_EN

39 40

IN

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

8

66

39 40

IN

18

IN

24 39 66

66

No stuff C7931, 12ms
Min delay time

U7930 Sense input
threhold is 3.07V

Sus_PGOOD_CT

1

R7967

10K

5%
1/16W
MF-LF

402

2

R7966

100

1 2

5%
1/16W
MF-LF

402

R7963

100

1 2

5%
1/16W
MF-LF

402

OUT

ALL_SYS_PWRGD

State

1

20%
10V

2

CERM

402

3.3V/5.0V Sus ENABLE

PLACE_NEAR=U7940.1:2.3mm

C7940

SMC_BATLOW_L

PM_SLP_SUS_L

3.3V SUS Detect

=PP3V3_S5_PWRCTL

8

PLACE_NEAR=U7930.6:2.3mm

CRITICAL

SENSE

U7930

TPS3808G33DBVRG4

4

CT

1

C7931

0.001UF

20%
50V

2

CERM
402

NO STUFF

24 39 66

18 39 40

6 3

PM_SLP_S4_L

IN

(PM_SLP_S3_R_L)

R7987

2

33K

5%

1/16W

1

MF-LF
402

PLACE_NEAR=U7100.15:6mm

PVCCSA_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7100.15:6mm

57

1

C7987

0.47UF

10%

6.3V

2

CERM-X5R
402

VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency

1

C7950

0.1UF

20%
10V

2

CERM
402

74LVC2G08GT

8

SOT833

7

Y

08

4

R7925

10K

5%
1/16W
MF-LF

1 2

402

2

R7911

5.1K

5%

1/16W

MF-LF

1

402

PLACE_NEAR=U7300.16:6mm

1

C7910

0.47UF

10%

6.3V

2

CERM-X5R
402

R7981

2

20K

5%

1/16W

1

MF-LF
402

PLACE_NEAR=U7600.3:6mm

CPUVCCIOS0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7600.3:6mm

1

C7981

0.47UF

10%

6.3V

2

CERM-X5R
402

PCH S0 PWRGD

PM_S0_PGOOD

Q7925

SSM6N15AFE

SOT563

5

19 24 36

IN

1.2V, 5V, 3.3V, DDR S3 ENABLE

2

R7912

5%

1/16W
MF-LF

1

402

PLACE_NEAR=Q7812.2:6mm

NO STUFF

1

C7912

0.47UF

10%

6.3V

2

CERM-X5R
402

0

R7985

20K

5%
1/16W
MF-LF

1 2

402

2

R7913

0

5%

1/16W
MF-LF

1

402

PLACE_NEAR=Q7842.2:6MM

NO STUFF

1

C7913

0.47UF

10%

6.3V

2

CERM-X5R
402

P1V05S0_EN

PLACE_NEAR=U7770.3:6mm

1

C7984

0.47UF

10%

6.3V

2

CERM-X5R
402

NC

74LVC2G08GT

8

SOT833

5

A

3

SYS_PWROK_R

Y

U7950

6

08

B

4

NC

R7948

0

1 2

5%
1/16W
MF-LF

402

=PP3V3_S3_WLAN

R7926

10K

5%

1/16W
MF-LF

1 2

402

3

D

SG

4

8

SYNC_MASTER=MASTER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

R7914

5%

1/16W
MF-LF

1

402

PLACE_NEAR=U4900.K5:6MM

2

0

R7916

3.3K

5%

1/16W

MF-LF

1

402

PLACE_NEAR=U4900.K5:6MM

P1V2S3_EN

P5VS3_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

NO STUFF

1

C7914

0.47UF

10%

6.3V

2

CERM-X5R
402

PM_SLP_S3_R_L

MAKE_BASE=TRUE

R7988

10K

5%
1/16W
MF-LF

1 2

402

P1V5S0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7770.3:6mm

1

C7988

0.47UF

10%

6.3V

2

CERM-X5R
402

R7949

1K

1 2

5%
1/16W
MF-LF

402

NO STUFF

1

C7916

0.47UF

10%

6.3V

2

CERM-X5R
402

2

R7986

5.1K

5%
1/16W
MF-LF

1

402

PLACE_NEAR=U7760.B3:6mm

P1V8S0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7760.B3:6mm

1

C7986

0.47UF

10%

6.3V

2

CERM-X5R
402

PM_PCH_SYS_PWROK

PM_PCH_APWROK

PM_PCH_PWROK

MAKE_BASE=TRUE

36

PM_WLAN_EN

36

OUT

Power Control 1/ENABLE

Apple Inc.

R

12

TPAD_VBUS_EN

=P5VS3_EN

=P3V3S3_EN

=DDRREG_EN

=P5VS0_EN
=P3V3S0_EN
=PBUSVSENS_EN
=TBT_S0_EN

=P1V8S0_EN

=P1V5S0_EN

(Replaced by TBT_EN_LC_ISOL)

=CPUVCCIOS0_EN
=PVCCSA_EN

18 24 39

OUT

18

OUT

18 25

OUT

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

79 OF 132

SHEET

66 OF 80

124578

OUT

OUT

OUT

OUT

65

OUT

65

OUT

44

OUT

69 70

OUT

64

OUT

64

OUT

63

OUT

58

OUT

SYNC_DATE=MASTER

47

65

65

60

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

SIZE

D

C

B

A

D

D

LCD PANEL INTERFACE (eDP)

PPVOUT_S0_LCDBKLT

7

71 80

LED_RETURN_6

7

71

LED_RETURN_5

7

71

LED_RETURN_4

7

71

LED_RETURN_3

7

71

LED_RETURN_2

7

LCD_HPD

10

OUT

9

OUT

DP_INT_AUX_C_P

9

79

BI

DP_INT_AUX_C_N

9

79

BI

DP_INT_ML_C_P<0>

9

79

C

IN

LCD_PWR_EN

R9010

1/16W
MF-LF

402

1K

5%

1

2

C9009

0.1UF

X7R-CERM

0402

10%
16V

CRITICAL

U9000

FPF1009

MFET-2X2-8IN

ON

2

VIN_1

3

VIN_2

1

2

GND
617

VOUT_1

VOUT_2

THRM

PAD

4

5

8

9

=PP5V_S0_LCD

8

B

LCD Panel HPD & AUX strapping

7

1

R9001

1M

5%
1/20W
MF
201

2

67 79

7

67

79

LCD_HPD_CONN

7

67

A

IN

9

79

IN

9

79

IN

9

79

IN

9

79

IN

9

79

IN

9

79

IN

9

79

IN

1

C9011

0.1UF

10%
16V

2

X7R-CERM
0402

=PP3V3_S0_LCD

DP_INT_AUX_N
DP_INT_AUX_P

DP_INT_ML_C_N<0>

DP_INT_ML_C_P<1>

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<2>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<3>

LCD Panel Current XW Short

EDP: 1 A, Refdes: XW9020

PP5VR3V3_SW_LCD_ISNS

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1

C9012

10UF

20%

6.3V

2

X5R
603

NO_XNET_CONNECTION=TRUE

1

R9003

1M

5%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

1

R9002

1M

5%
1/20W
MF
201

2

R9000

XW9020

1 2

0

1 2

C9028

0.1UF

C9029

0.1UF

C9020

C9021

C9022
C9023

C9024
C9025

C9026

C9027

SM

NC_ISNS_LCD_PANELN
NC_ISNS_LCD_PANELP

1/20W

1 2

1 2

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

PP5VR3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

10%
X5R-CERM

10%
X5R-CERM

NO_XNET_CONNECTION=TRUE

MF 2015%

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

16V
0201

16V
0201

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

FERR-220-OHM

1 2

1

C9001

0.1UF

10%
16V

2

X5R-CERM

0201

7

80

OUT

7

80

OUT

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

DP_INT_ML_P<0>

67 79

DP_INT_ML_N<0>

67 79

DP_INT_ML_P<1>

67 79

DP_INT_ML_N<1>

67 79

DP_INT_ML_P<2>

67 79

DP_INT_ML_N<2>

67 79

DP_INT_ML_P<3>

67 79

DP_INT_ML_N<3>

67 79

71

71

67 79

67 79

CRITICAL

L9000

0805

C9002

0.1UF

X5R-CERM

0201

BP9000

BEAD-PROBE

BP9001

BEAD-PROBE

BP9002

BEAD-PROBE

BP9003

BEAD-PROBE

BP9004

BEAD-PROBE

BP9005

BEAD-PROBE

BP9006

BEAD-PROBE

BP9007

BEAD-PROBE

LED_RETURN_1

7

LCD_HPD_CONN

7

67

LCD_FSS

DP_INT_AUX_P

7

67 79

DP_INT_AUX_N

7

67 79

BEAD_PROBE=TRUE

DP_INT_ML_P<0>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_N<0>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_P<1>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_N<1>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_P<2>

BEAD_PROBE=TRUE

DP_INT_ML_N<2>

BEAD_PROBE=TRUE

DP_INT_ML_P<3>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_N<3>

67 79

PP5VR3V3_SW_LCD

7

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1

10%
16V

2

SM

NO_XNET_CONNECTION=TRUE

1
SM

1

NO_XNET_CONNECTION=TRUE

SM

1

SM

1

NO_XNET_CONNECTION=TRUE

SM

1

SM

1

NO_XNET_CONNECTION=TRUE

SM

1

SM

1

NO_XNET_CONNECTION=TRUE

C9003

1000PF

100V

X7R-CERM

0603

R9011

1M

1 2

5%

NO_XNET_CONNECTION=TRUE

1/20W

MF

201

R9013

1M

1 2

5%

1/20W

MF

201

R9015

1M

1 2

5%

1/20W

MF

201

R9017

1M

1 2

5%

1/20W

MF

201

1

C9000

10%

1000PF

2

X7R-CERM

R9012

1M

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

R9014

1M

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

R9016

1M

1 2

5%

1/20W

MF

201

TRUE

R9018

1M

1 2

5%

1/20W

MF

201

100V
0603

10%

NC

1

2

6 3

CRITICAL

J9000

20525-130E-01

F-RT-SM

31

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

33
34
35
36
37
38
39
40
41

32

518S0829

SYNC_MASTER=D1_SENSORS
PAGE TITLE

eDP Display Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/11/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

90 OF 132

SHEET

67 OF 80

124578

8 7 6 5 4 3

12

D

=PP3V3_S0_DDCMUX

8

R9251

DDC Crossbar

On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC.

DP_TBTPA_DDC_CLK

69

C

OUT

DP_TBTPA_DDC_DATA

69

BI

DP_TBTPB_DDC_CLK

70

OUT

DP_TBTPB_DDC_DATA

70

BI

TBT_DDC_XBAR_EN_L

33

IN

SAI/SBI = 1: INA == OUTA0, INB == OUTB0
SAI/SBI = 0: INA == OUTB0, INB == OUTA0

Only necessary on dual-port hosts.

NEVER SEND AUXCH THROUGH CROSSBAR!

13

VCC

U9200

TS3DS10224

16

ENA

QFN

CRITICAL

1

INA+

2

INA-

14

SAI

10

ENB

3

INB+

4

INB-

12 11

SBI

GND

5

OUTA1+
OUTA1-

OUTA0+
OUTA0-

OUTB1+
OUTB1-

OUTB0+
OUTB0-

PAD

THRM

21

SAO

SBO

20
19

18
17

15

6
7

8
9

1

C9280

0.1UF

20%
10V

2

CERM
402

1

2.2K

1%
1/20W
MF
201

2

R9252

1

2.2K

1%
1/20W
MF
201

2

DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA

R9253

1

2.2K

1%
1/20W
MF
201

2

R9254

1

2.2K

1%
1/20W
MF
201

2

9

IN

9

BI

9

IN

9

BI

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

DDC Crossbar

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

92 OF 132

SHEET

68 OF 80

124578

8 7 6 5 4 3

12

PART NUMBER

138S0811

QTY

1

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X5R,0603,MURATA

3.3V/HV Power MUX

V3P3 must be S4 to support

wake from Thunderbolt devices.

=PP3V3_S4_TBTAPWRSW

D

CRITICAL

C9487

100UF

6.3V

POLY-TANT

CASE-B2-SM

OMIT_TABLE

8

CRITICAL

1

C9480

22UF

X5R-CERM-1

1

C9415

4.7UF

10%
25V

2

X5R-CERM
0603

66

IN

35

IN

66 70

IN

6.3V

20%
603

20%

2

=PPHV_SW_TBTAPWRSW

8

18.9V Max

1

1

C9481

0.1UF

10%
16V

2

2

X5R-CERM
0201

0.1UF

10%
25V
X5R
402

1

2

C9410

=TBTAPWRSW_EN
TBT_A_HV_EN_RC
=TBT_S0_EN

C

For 12V systems:

PART NUMBER

118S0145
118S0145

Nominal Min Max

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT_A_D2R_P<0>

7

33 76

OUT

TBT_A_D2R_N<0>

7

33 76

OUT

DP_TBTPA_ML_C_P<3>

33 76

IN

DP_TBTPA_ML_C_N<3>

33 76

B

IN

7

33 76

OUT

7

33 76

OUT

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>

QTY

2
2

DESCRIPTION

RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF

RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF

GND_VOID=TRUE

0.47UF

0.47UF

C9478
C9479

0.47UF

0.47UF

(Both C’s)

1 2

1 2

GND_VOID=TRUE

0.22UF

0.22UF

GND_VOID=TRUE

(Both C’s)

1 2

1 2

GND_VOID=TRUE

69 76

69 76

C9474
C9475

C9476
C9477

Nominal Min Max

IV3P3 1100mA 1030mA 1200mA

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19
20

6
7

RSVD

5

EN

11 10

HV_EN

17

S0

V3P3OUT

V3P3

VHV

CRITICAL

U9410

CD3210A0RGP

QFN

ISET_V3P3

ISET_S0

ISET_S3

GND

123

4

13

TBTHV:P15V

R9413

22.6K

1/20W

<RHVS3> <RHVS0>

201

OUT

RSVD

THRM

1%
MF

PAD

21

1

2

REFERENCE DES

R9410,R9413
R9411,R9414

4V20%

201

CERM-X5R-1

4V

20%

CERM-X5R-1

201

1 2

20%

6.3V

X5R

0201

1 2

20%

6.3V

X5R

0201

TBT_A_BIAS

69

1

R9498

2.2K

5%

1/20W

MF

201

2

GND_VOID=TRUE

4V

20%

CERM-X5R-1

201

20% 4V

CERM-X5R-1

201

DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N

C9498

C0G-CERM

REFERENCE DES

18

12
14

1

C9485

0.1UF

10%
16V

2

X5R-CERM

0201

1516

8

TBTAPWRSW_ISET_V3P3

7

TBTAPWRSW_ISET_S0

7

9

TBTAPWRSW_ISET_S3

7

12V: See
below

TBTAPWRSW_ISET_S3_R

7

TBTAPWRSW_ISET_S0_R

TBTHV:P15V

1

R9414

22.6K

1%
1/20W
MF
201

2

TBT_A_D2R_C_P<0>

7

76

TBT_A_D2R_C_N<0>

7

76

NO_XNET_CONNECTION=TRUE

DP_TBTPA_ML_P<3>

76

DP_TBTPA_ML_N<3>

76

TBT: Unused

1

R9499

2.2K

5%
1/20W
MF
201

2

GND_VOID=TRUE

TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>

1

30PF

5%

25V

2

0201

C9415

1

C9486

10UF

20%

6.3V

2

CERM-X5R
0402

TBTHV:P15V

R9410

22.6K

1/20W

Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

ILIM = 40000 / RISET

CRITICAL

GND_VOID=TRUE

1

R9494

1K

5%

1/20W

MF

201

2

1

C9499

30PF

5%
25V

2

C0G-CERM
0201

CRITICAL

CRITICAL

PP3V3_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PPHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

1

C9411

0.1UF

10%
25V

2

X5R
402

1

1%
MF

201

2

BOM OPTION

TBTHV:P15V

1

R9411

22.6K

1%
1/20W
MF
201

2

BOM OPTION

TBTHV:P12V
TBTHV:P12V

GND_VOID=TRUE

1

R9495

1K

5%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

R9478

R9479

D9498

BAR90-02LRH

D9499

BAR90-02LRH

650NH-5%-0.430MA-0.52OHM

650NH-5%-0.430MA-0.52OHM

470K

470K

CRITICAL

CRITICAL

SIGNAL_MODEL=TBTPINSIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

GND_VOID=TRUE

(Both D’s)

A K

A K

CRITICAL

L9498

NO_XNET_CONNECTION=TRUE

CRITICAL

L9499

NO_XNET_CONNECTION=TRUE

0603

0603

69

1

R9412

36.5K

1%
1/20W
MF
201

2

<RV3P3>

C9400

0.01UF

X7R-CERM

1 2

1 2

TSLP-2-7

TSLP-2-7

12

12

FERR-120-OHM-3A

1 2

1

10%
50V

2

0402

76

76

GND_VOID=TRUE

GND_VOID=TRUE

5%
MF 201

5%
MF 201

1

2

1/20W

1/20W

TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

L9400

0603

C9401

0.01UF

10%
50V
X7R-CERM
0402

DP_TBTPA_AUXCH_C_N

33 76

BI

DP_TBTPA_AUXCH_C_P

33 76

BI

DP_TBTPA_ML_C_P<1>

33 76

IN

DP_TBTPA_ML_C_N<1>

33 76

IN

PP3V3_SW_TBTAPWR

69

33

OUT

PP3V3RHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

TBT Dir

DP Dir

TBT_A_LSRX

Y = B

R9401

1 2

1/20W

PP3V3_SW_TBTAPWR

69

0.1UF

0.1UF

0.22UF

0.22UF

5

VCC

GND

2

1 2

10% 16V
X5R-CERM0201

1 2

10% 16V
X5R-CERM0201

1 2

20%

6.3V

X5R

0201

1 2

20%

6.3V

X5R

0201

3

1

B

6

C

CRITICAL

U9460

74AUP1T97

1

C9460

0.1UF

10%
16V

2

X5R-CERM
0201

SOT891

C9430
C9431

C9432
C9433

4

Y A

Thunderbolt Connector A

12

5%
MF

201

CRITICAL

B2
B4
B6

B10
B12

B16
B18
B20

514-0836

For J9400 TBT SMT pads
(3, 5, 17 & 19):

SHIELD PINS

J9400

HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
AUX_CHP
AUX_CHN
DP_PWR

SHIELD PINS

S22

S24

S15

S16

MDP-D1

F-RT-TH

PORT B

S20

S21

S12

S13

S14

GND0
ML_LANE0P
ML_LANE0N

GND1
ML_LANE1P
ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

S17

S18

S19

C9420

X5R-CERM

SIGNAL_MODEL=TBT_MUX

TBT_A_CIO_SEL

33

IN

DP_AUXIO_EN

25 70

IN

76

DP_TBTPA_AUXCH_N
DP_TBTPA_AUXCH_P

76

DP_TBTPA_DDC_DATA

68

BI

DP_TBTPA_DDC_CLK

68

IN

TBT_A_CONFIG1_BUF

33

OUT

DP_TBTPA_ML_P<1>

76

DP_TBTPA_ML_N<1>

76

TBT_A_LSTX

33

IN

TBT_A_LSRX_UNBUF
TBT_A_DP_PWRDN

33

IN

DP_TBTPA_HPD

33

OUT

B1
B3
B5
B7B8
B9
B11
B13B14
B15
B17
B19

0.1UF

0201

10%
16V

DP Dir

1

2

C9421

1

0.1UF

10%
16V

2

X5R-CERM

0201

R9426

1M

5%

1/20W

MF

201

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

(0-18.9V)

TBT Dir

TBT: TX_0

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

1

R9427

10K

5%
1/20W
MF
201

2

1 24

2

7
8

4
5

11
10

14
13

6

1

2

GND_VOID=TRUE

C9405

0.01UF

X5R-CERM

TBT_A_R2D_P<0>

7

76

7

76

TBT_A_R2D_N<0>
TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

TBT_A_R2D_P<1>

7

76

TBT_A_R2D_N<1>

7

76

CRITICAL

CBTL05023

BIASIN

AUXIO_EN

AUX­AUX+

DDC_DAT
DDC_CLK

CA_DETOUT

DP+
DP-

LSTX
LSRX

DP_PD

HPDOUT

1

10%
25V

2

0201

GND_VOID=TRUE

C9406

0.01UF

X5R-CERM

3
VDD

U9420

HVQFN

GND
9

10%
25V

0201

15

21

R9429

BIASOUT

AUXIO­AUXIO+

CA_DET

DPMLO+
DPMLO-

THMPAD

25

1

2

1

100K

5%

1/20W

MF

201

2

23
22

1816

19
20

1712

HPD

1

R9428

100K

5%
1/20W
MF
201

2

C9470
C9471

GND_VOID=TRUE

1

R9470

470K

5%
1/20W
MF
201

2

C9472
C9473

GND_VOID=TRUE

1

R9472

470K

5%
1/20W
MF
201

2

470k R’s for ESD protection
on AC-coupled signals.

TBT_A_BIAS

VOLTAGE=3.3V

1

C9425

0.1UF

10%
16V

2

X5R-CERM
0201

DP_A_AUXCH_DDC_N
DP_A_AUXCH_DDC_P

TBT: RX_1 Bias Sink

TBT_A_CONFIG1_RC

DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_A_HPD

GND_VOID=TRUE

(Both C’s)

1 2

1 2

GND_VOID=TRUE

1

2

GND_VOID=TRUE

(Both C’s)

1 2

1 2

1

2

20%
X5R

20%
X5R

GND_VOID=TRUE

R9471

470K

5%
1/20W
MF
201

20%
X5R

20%
X5R

GND_VOID=TRUE

GND_VOID=TRUE

R9473

470K

5%
1/20W
MF
201

0.22UF

0.22UF

0.22UF

0.22UF

TBT_A_R2D_C_P<0>

6.3V
0201

TBT_A_R2D_C_N<0>

6.3V
0201

DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBT_A_R2D_C_P<1>

6.3V
0201

TBT_A_R2D_C_N<1>

6.3V
0201

69

69 76

69 76

69

69 76

69 76

69

69 76

69 76

D

C

7

33 76

IN

7

33 76

IN

B

7

33 76

IN

7

33 76

IN

TBT_A_HPD

A

69

TBT_A_CONFIG1_RC

69

TBT_A_CONFIG2_RC

33

OUT

1

R9452

1M

5%

1/20W 1/20W

MF

201

2

1

R9451

1M

5%
MF

201

2

C9494

330PF

X7R-CERM

0201

10%
16V

SIZE

A

D

SYNC_MASTER=J5_MLB_KEPLER

1

C9402

0.01UF

10%
16V

2

X5R-CERM

1

1

1

C9495

330PF

10%
16V

2

2

X7R-CERM
0201

R9441

100K

5%
1/20W
MF
201

2

0201

DP Source must pull
down HPD input with

greater than or equal
to 100K (DPv1.1a).

Sink HPD range:
High: 2.0 - 5.0V

Low: 0 - 0.8V

PAGE TITLE

Thunderbolt Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=11/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

94 OF 132

SHEET

69 OF 80

124578

8 7 6 5 4 3

12

D

CRITICAL

C9687

100UF

POLY-TANT

CASE-B2-SM

OMIT_TABLE

6.3V

C

For 12V systems:

PART NUMBER

118S0145
118S0145

Nominal Min Max

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT_B_D2R_P<0>

7

33 76

OUT

TBT_B_D2R_N<0>

7

33 76

OUT

DP_TBTPB_ML_C_P<3>

33 76

IN

DP_TBTPB_ML_C_N<3>

33 76

B

IN

7

33 76

OUT

7

33 76

OUT

TBT_B_D2R_P<1>
TBT_B_D2R_N<1>

PART NUMBER

138S0811

V3P3 must be S4 to support

wake from Thunderbolt devices.

=PP3V3_S4_TBTBPWRSW

8

CRITICAL

1

C9680

22UF

X5R-CERM-1

1

C9615

4.7UF

10%
25V

2

X5R-CERM
0603

66

IN

35

IN

66 69

IN

20%

6.3V
603

=TBTBPWRSW_EN
TBT_B_HV_EN_RC
=TBT_S0_EN

20%

2

=PPHV_SW_TBTBPWRSW

8

18V Max

QTY

2
2

QTY

1

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X5R,0603,MURATA

3.3V/HV Power MUX

Nominal Min Max

IV3P3 1100mA 1030mA 1200mA

1

1

C9681

0.1UF

10%
16V

2

2

X5R-CERM
0201

0.1UF

10%
25V
X5R
402

1

2

C9610

DESCRIPTION

RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF

RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF

GND_VOID=TRUE

0.47UF

0.47UF

C9678
C9679

0.47UF

0.47UF

(Both C’s)

1 2

1 2

GND_VOID=TRUE

0.22UF

0.22UF

GND_VOID=TRUE

(Both C’s)

1 2

1 2

GND_VOID=TRUE

70 76

70 76

C9674
C9675

C9676
C9677

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

V3P3

20

6

VHV

7

CD3210A0RGP

RSVD

5

EN

11 10

HV_EN

17

S0

123

TBTHV:P15V

4V20%

CERM-X5R-1

201

4V20%

CERM-X5R-1

201

1 2

20%
X5R

1 2

20%
X5R

TBT_B_BIAS

70

R9698

GND_VOID=TRUE

4V20%

201

CERM-X5R-1

4V20%

CERM-X5R-1

201

DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N

18

V3P3OUT

12

OUT

14

RSVD

ISET_S0

ISET_S3

THRM

PAD

13

1%
MF

201

C9685

1516

8

9

21

1

2

CRITICAL

U9610

QFN

ISET_V3P3

GND

4

R9613

22.6K

1/20W

<RHVS3> <RHVS0>

REFERENCE DES

R9610,R9613
R9611,R9614

TBT_B_D2R_C_P<0>

7

76

TBT_B_D2R_C_N<0>

7

76

DP_TBTPB_ML_P<3>

201

76

DP_TBTPB_ML_N<3>

76

TBT: Unused

1

1

R9699

2.2K

5%

5%
1/20W

MF

MF
201

2

2

GND_VOID=TRUE

TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>

C9698

30PF

C0G-CERM

0201

6.3V
0201

6.3V
0201

2.2K

1/20W

REFERENCE DES

C9615

1

1

0.1UF

10%
16V

X5R-CERM

0201

TBTBPWRSW_ISET_V3P3

7

2

2

TBTBPWRSW_ISET_S0
TBTBPWRSW_ISET_S3

7

12V: See
below

TBTBPWRSW_ISET_S3_R
TBTBPWRSW_ISET_S0_R

7

TBTHV:P15V

1

R9614

22.6K

1%
1/20W
MF
201

2

ILIM = 40000 / RISET

CRITICAL

GND_VOID=TRUE

R9694

NO_XNET_CONNECTION=TRUE

1

1

C9699

25V

5%

30PF

5%
25V

2

2

C0G-CERM
0201

CRITICAL

C9686

10UF

20%

6.3V
CERM-X5R
0402

TBTHV:P15V

R9610

22.6K

1/20W

201

Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

1

1K

5%

1/20W

MF

201

2

BOM OPTION

CRITICAL

PP3V3_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PPHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

1

C9611

0.1UF

10%
25V

2

X5R
402

TBTHV:P15V

1

1

R9611

22.6K

1%

1%

1/20W
MF

MF

201

2

2

BOM OPTION

TBTHV:P12V
TBTHV:P12V

GND_VOID=TRUE

1

R9695

1K

5%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

R9678

R9679

D9698

BAR90-02LRH

D9699

BAR90-02LRH

650NH-5%-0.430MA-0.52OHM

650NH-5%-0.430MA-0.52OHM

470K

470K

CRITICAL

CRITICAL

SIGNAL_MODEL=TBTPIN

SIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

(Both D’s)

A K

A K

GND_VOID=TRUE

CRITICAL

L9698

0603

NO_XNET_CONNECTION=TRUE

CRITICAL

L9699

0603

NO_XNET_CONNECTION=TRUE

70

1

R9612

36.5K

1%
1/20W
MF
201

2

<RV3P3>

C9600

0.01UF

X7R-CERM

1 2

1 2

TSLP-2-7

TSLP-2-7

12

12

FERR-120-OHM-3A

1 2

1

10%
50V

2

0402

76

76

GND_VOID=TRUE

GND_VOID=TRUE

5%

5%

1

2

1/20W

201MF

1/20W

201MF

TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N

L9600

0603

C9601

0.01UF

10%
50V
X7R-CERM
0402

DP_TBTPB_AUXCH_C_N

33 76

BI

DP_TBTPB_AUXCH_C_P

33 76

BI

DP_TBTPB_ML_C_P<1>

33 76

IN

DP_TBTPB_ML_C_N<1>

33 76

IN

70

33

OUT

PP3V3RHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

TBTBCONN_20_RC

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

TBT Dir

DP Dir

TBT_B_LSRX

Y = B

R9601

1 2

1/20W

PP3V3_SW_TBTBPWR

70

0.1UF

0.1UF

0.22UF

0.22UF

5

VCC

GND

2

1 2

16V10%
0201X5R-CERM

1 2

16V10%
0201X5R-CERM

1 2

6.3V

20%

0201

X5R

1 2

6.3V

20%

0201

X5R

3

1

B

6

C

CRITICAL

U9660

74AUP1T97

1

C9660

0.1UF

10%
16V

2

X5R-CERM
0201

SOT891

C9630
C9631

C9632
C9633

4

Y A

Thunderbolt Connector B

12

5%
MF

201

CRITICAL

A2
A4
A6

A10
A12

A16
A18
A20

514-0836

For J9600 TBT SMT pads
(3, 5, 17 & 19):

SHIELD PINS

J9400

HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
AUX_CHP
AUX_CHN
DP_PWR

SHIELD PINS

S11S2S23

MDP-D1

F-RT-TH

PORT A

S9

S10

S1

S3S4S5

GND0
ML_LANE0P
ML_LANE0N

GND1
ML_LANE1P
ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

S6S7S8

C9620

X5R-CERM

SIGNAL_MODEL=TBT_MUX

TBT_B_CIO_SEL

33

IN

DP_AUXIO_EN

25 69

IN

DP_TBTPB_AUXCH_N

76

DP_TBTPB_AUXCH_P

76

DP_TBTPB_DDC_DATA

68

BI

DP_TBTPB_DDC_CLK

68

IN

TBT_B_CONFIG1_BUF

33

OUT

DP_TBTPB_ML_P<1>

76

76

DP_TBTPB_ML_N<1>
TBT_B_LSTX

33

IN

TBT_B_LSRX_UNBUFPP3V3_SW_TBTBPWR
TBT_B_DP_PWRDN

33

IN

DP_TBTPB_HPD

33

OUT

A1
A3
A5
A7A8
A9
A11
A13A14
A15
A17
A19

0.1UF

0201

10%
16V

DP Dir

1

2

TBT: TX_0

C9621

0.1UF

10%
16V

X5R-CERM

0201

R9626

(0-18.9V)

TBT Dir

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

1

1

R9627

10K

5%
1/20W

2

MF
201

2

1 24

BIASIN

2

AUXIO_EN

7

AUX-

8

AUX+

4

DDC_DAT

5

DDC_CLK

CA_DETOUT

11

DP+

10

DP-

14

LSTX

13

LSRX

6

DP_PD

HPDOUT

1

1M

5%

1/20W

MF

201

2

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

TBT_B_R2D_P<0>

7

76

TBT_B_R2D_N<0>

7

76

TBTBCONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

GND_VOID=TRUE

TBT_B_R2D_P<1>

7

76

TBT_B_R2D_N<1>

7

76

3

15

VDD

CRITICAL

U9620

CBTL05023

HVQFN

GND
9

21

GND_VOID=TRUE

C9605

0.01UF

10%
25V

X5R-CERM

0201

C9606

0.01UF

10%
25V

X5R-CERM

0201

R9629

BIASOUT

AUXIO­AUXIO+

CA_DET

DPMLO+
DPMLO-

THMPAD

25

1

2

1

2

HPD

100K

1/20W

1

5%
MF

201

2

23
22

1816

19
20

1712

GND_VOID=TRUE

1

R9670

470K

5%
1/20W
MF
201

2

GND_VOID=TRUE

1

R9672

470K

5%
1/20W
MF
201

2

470k R’s for ESD protection
on AC-coupled signals.

1

R9628

100K

5%
1/20W
MF
201

2

C9670

0.22UF

C9671

0.22UF

C9672

0.22UF

C9673

0.22UF

VOLTAGE=3.3V

1

2

TBT_B_BIAS

C9625

0.1UF

10%
16V
X5R-CERM
0201

DP_B_AUXCH_DDC_N
DP_B_AUXCH_DDC_P

TBT: RX_1 Bias Sink

TBT_B_CONFIG1_RC

DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_B_HPD

GND_VOID=TRUE

(Both C’s)

GND_VOID=TRUE

(Both C’s)

1 2

1 2

GND_VOID=TRUE

GND_VOID=TRUE

1

R9671

470K

5%
1/20W
MF
201

2

1 2

1 2

GND_VOID=TRUE

GND_VOID=TRUE

1

R9673

470K

5%
1/20W
MF
201

2

20%
X5R

20%
X5R

20%
X5R

20%
X5R

TBT_B_R2D_C_P<0>

6.3V
0201

TBT_B_R2D_C_N<0>

6.3V
0201

DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBT_B_R2D_C_P<1>

6.3V
0201

TBT_B_R2D_C_N<1>

6.3V
0201

70

70 76

70 76

70

70 76

70 76

70

70 76

70 76

D

C

7

33 76

IN

7

33 76

IN

B

7

33 76

IN

7

33 76

IN

TBT_B_HPD

A

70

TBT_B_CONFIG1_RC

70

TBT_B_CONFIG2_RC

33

OUT

R9652

1/20W

201

SIZE

A

D

SYNC_MASTER=J5_MLB_KEPLER

1

C9602

0.01UF

10%
16V

2

X5R-CERM

1

1

R9651

1M

1M

5%

5%
1/20W

MF

MF
201

2

2

C9694

330PF

X7R-CERM

0201

10%
16V

1

1

C9695

330PF

10%
16V

2

2

X7R-CERM
0201

1

R9641

100K

5%
1/20W
MF
201

2

0201

DP Source must pull
down HPD input with

greater than or equal
to 100K (DPv1.1a).

Sink HPD range:
High: 2.0 - 5.0V

Low: 0 - 0.8V

PAGE TITLE

Thunderbolt Connector B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=11/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

96 OF 132

SHEET

70 OF 80

124578

8 7 6 5 4 3

F9700

3AMP-32V-467

=PPBUS_S0_LCDBKLT

D

8

1 2

603-HF

BOTTOM

PPBUS_S0_LCDBKLT_FUSED

SSM6N15AFE

LCD_BKLT_EN

9

IN

C

BKLT_PLT_RST_L

25

IN

R9753 AND R9757 NEED TO BE 402 PACK FOR LAB ACCESS

7 9

R9753

R9757

IN

LCD_BKLT_PWM

=I2C_BKL_1_SCL

42

=I2C_BKL_1_SDA

42

PPBUS_S0_LCDBKLT_PWR

8

B

71

LCD_BKLT_PWM SHOULD BE KEPT AWAY FROM BOOST CIRCUIT

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

1

R9788

301K

1%
1/16W
MF-LF
402

2

LCDBKLT_EN_DIV

1

R9789

147K

1%
1/16W
MF-LF
402

2

LCDBKLT_EN_L

3

Q9707

SOT563

D

5

SG

4

SSM6N15AFE

0

1 2

0

1 2

R9731

1 2

301K

1%
1/16W
MF-LF

402

0.1UF

X7R-CERM

0402

10%
16V

1

2

C9782

LCDBKLT_DISABLE

2

1/16W

1/16W

R9715

100K

1%
1/16W
MF-LF
402

D

SG

MF-LF

MF-LF

R9704

0

1 2

5%
1/16W
MF-LF

402

Q9707

SOT563

1 2

CRITICAL

Q9706

FDC638APZ_SBMS001

SSOT6-HF

4

1 2 5 6

3

PPBUS_S0_LCDBKLT_PWR

8

71

=PP3V3_S0_BKL_VDDIO

6

1

4025%

4025%

8

NO STUFF

1

C9704

33PF

5%
50V

2

CERM
402

PPBUS S0 LCDBkLT FET

MOSFET

CHANNEL

RDS(ON)

LOADING

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

PLACE_NEAR=U9701.22:3MM

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.715 A (EDP)

80

THERE IS A SENSE RESISTOR BETWEEN
PPBUS_SW_LCDBKLT_PWR
AND PPBUS_SW_BKL
ON THE SENSOR PAGE

PLACE_NEAR=L9710.1:5MM

CRITICAL

1

2

1

C9714

0.01UF

10%
16V

2

X7R-CERM
0402

BKL_ISET
BKL_SCL
BKL_SDA

LVDS_BKL_PWM_RC

TP_BKL_FAULT

7

BKLT_EN

7

(EEPROM should set EN_I_RES=1)

1

R9714

16.2K

1/16W
MF-LF

402

1%

2

I_LED=22.7MA
I_LED=369/Riset

FPWM=19.2KHZ

details in spec

C9712

10UF

10%
25V
X5R
805

PLACE_NEAR=U9701.22:5MM

1

C9710

1UF

10%
25V

2

X5R
603-1

1

R9716

12.7K

1%
1/16W
MF-LF

402

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

=PP5V_S0_BKL

8

PLACE_NEAR=L9710.1:3MM

1

C9713

0.1UF

10%
25V

2

X5R
402

PLACE_NEAR=U9701.8:3MM

1

C9711

0.1UF

10%
16V

2

X7R-CERM
0402

82322

VDDIO VLDO

U9701

6

GD

1

R9765

10K

5%
1/16W
MF-LF
402

2

5

FSET

20

FILTER

3

ISET

10

11

SDA

2

PWM

7

FAULT

4

EN

BKL_SGND

PLACE_NEAR=U9701.9:10MM

CRITICAL

GND_SW

9

1

BKL_FSET

BKL_FLT

PLACE XW9710 AWAY FROM U9701.1 AND U9701.15
ADD VIAS IN TPAD OF U9701

*L9710, Q9701, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER.

22UH-20%-2.4A-0.105OHM

VOLTAGE=12.6V
MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

1 2

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

BKL_FET_CNTL

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

VIN

LLP

24

BKL_SW

SW

21

BKL_FB

FB

12

BKL_ISEN1

OUT1

13

BKL_ISEN2

OUT2

14

BKL_ISEN3

OUT3SCLK

LP8545SQX-EXTJ

GND_S

15

16

OUT4

17

OUT5

18

OUT6

19

VSYNC

THRM

PAD

GND_L

25

(APN: 353S3376)

PWM RES = 9+3

XW9710

SM

1 2

BKL_ISEN4
BKL_ISEN5
BKL_ISEN6
BKL_VSYNC_R

NEED VALUE CHANGES FOR 55V AND 96 LEDS !!!

CRITICAL

L9710

PPBUS_S0_LCDBKLT_PWR_SW

DEM8030C-SM

152S1527

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=50V

SWITCH_NODE=TRUE

4

1

R9755

10K

5%
1/16W
MF-LF
402

2

1 2 3

NEED TO BE CHANGED TO 371S0704

PLACE_NEAR=L9710.2:3MM

5

CRITICAL

Q9701

SI7308DN

PWRPK-1212-8

PLACE_NEAR=L9710.2:3MM

CRITICAL

D9701

POWERDI-123

A K

DFLS260

R9708

63.4K

1/16W
MF-LF

R9709

59.0K

1/16W
MF-LF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.14:10MM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=U9701.18:10MM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

C9715, C9716 SHOULD BE PLACED IN T-BONE. SAME FOR C9718,C9719
C9715, C9716 SHOULD BE PLACED ON TOP SIDE. PLACE C9718,C9719 ON BOTTOM SIDE

1

1%

402

2

1

1%

402

2

LCDBKLT:ENG

PLACE_NEAR=U9701.12:10MM

R9717

1 2

PLACE_NEAR=U9701.13:10MM

R9718

1 2

R9719

1 2

PLACE_NEAR=U9701.16:10MM

R9720

1 2

PLACE_NEAR=U9701.17:10MM

R9721

1 2

R9722

1 2

PLACE_NEAR=D9701.2:5MM

CRITICAL

1

C9715

2.2UF

10%
100V

2

X7R-CERM
1210

PLACE_NEAR=D9701.2:3MM

R9717-R9722 CAN BE 0OHM IN PRODUCTION, ADD BOM OPTION

10.2

0.1%

1/16W

TF

402

LCDBKLT:ENG

10.2

0.1%

1/16W

TF

402

LCDBKLT:ENG

10.2

0.1%

1/16W

TF

402

LCDBKLT:ENG

10.2

0.1%

1/16W

TF

402

LCDBKLT:ENG

10.2

0.1%

1/16W

TF

402

CRITICAL

1

C9716

2.2UF

10%
100V

2

X7R-CERM
1210

PLACE_NEAR=D9701.2:3MM

LED_RETURN_1

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LCDBKLT:ENG

10.2

1/16W

TF

402

0.1%

LED_RETURN_6

CRITICAL

1

C9718

2.2UF

10%
100V

2

X7R-CERM
1210

PLACE_NEAR=D9701.2:5MM

CRITICAL

1

C9719

2.2UF

10%
100V

2

X7R-CERM
1210

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

1

C9717

1000PF

10%
100V

2

X7R-CERM
0603

PLACE_NEAR=R9708.1:5MM

OUT

OUT

OUT

OUT

7

67

7

67

7

67

7

OUT

7

67

7

OUT

12

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=55V

67

67

D

7

67 80

C

B

A

PART NUMBER

116S0004

QTY

6

DESCRIPTION

RES,MTL FILM,1/16W,0,5,0402,SMD,LF

6 3

REFERENCE DES

R9717,R9718,R9719,R9720,R9721,R9722

CRITICAL

CRITICAL

BOM OPTION

LCDBKLT:PROD

SYNC_MASTER=J5_MLB_KEPLER

PAGE TITLE

LCD Backlight Driver (LP8545)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/21/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

97 OF 132

SHEET

71 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

CPU Signal Constraints

CPU_50S
CPU_55S

LAYER

ALLOW ROUTE
ON LAYER?

*

=50_OHM_SE =50_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=27P4_OHM_SE

*

MINIMUM LINE WIDTH

=50_OHM_SE

=27P4_OHM_SECPU_27P4S

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=50_OHM_SE

=55_OHM_SE=55_OHM_SE

=27P4_OHM_SE =27P4_OHM_SE

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

LAYER

D

SPACING_RULE_SET

CPU_AGTL
CPU_8MIL
CPU_COMP

CPU_ITP =4x_DIELECTRIC

CPU_VCCSENSE

Most CPU signals with impedance requirements are 50-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.

LINE-TO-LINE SPACING

*
*
* ?

=STANDARD

8 MIL

=4X_DIELECTRIC
* ?
*

=6X_DIELECTRIC

WEIGHT

?
?

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

CPU_AGTL?TOP,BOTTOM

CPU_VID

CPU_VREF

LAYER

*
*

LINE-TO-LINE SPACING

=2x_DIELECTRIC

0.457 MM
12 MIL

SOURCE: IVB PLATFORM DG , Tables 205-207

PCI-Express

PCIE_85D

SPACING_RULE_SET

PCIE

CLK_PCIE

LAYER

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF

*

=90_OHM_DIFFCLK_PCIE_90D =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

LAYER

LINE-TO-LINE SPACING

* ?

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF
=90_OHM_DIFF =90_OHM_DIFF

WEIGHT

=6X_DIELECTRIC

=5X_DIELECTRIC

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

C

B

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

0.1MM0.1MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

DMI_S2N
DMI_S2N
DMI_N2S
DMI_N2S
FDI_DATA PCIE_85D PCIE
FDI_DATA PCIE_85D PCIE
FDI_FSYNC
FDI_LSYNC
FDI_INT CPU_50S
DMI_CLK100M

I125

DMI_CLK100M

I126

CPU_EDP_COMP

I132

CPU_PEG_COMP

I130

CPU_CFG CPU_ITP

I133

XDP_CLK_CPU
XDP_CLK_CPU
XDP_CLK_PCH
XDP_CLK_PCH
DPLL_REF_CLK120M

I138

DPLL_REF_CLK120M

I139

XDP_TDI CPU_50S CPU_ITP
XDP_TDO CPU_50S CPU_ITP
XDP_TMS CPU_50S CPU_ITP
XDP_TCK CPU_50S CPU_ITP
XDP_TRST_L
XDP_BPM CPU_50S CPU_ITP
XDP_BPM_L
XDP_BDRESET_L

I134

XDP_PRDY_L

I135

XDP_PREQ_L

I136

CPU_CATERR_L
CPU_PROC_SEL_L CPU_50S

I115

CPU_PECI
CPU_PROCHOT_L
XDP_CPU_PWRGD
PM_THRMTRIP_L
PM_SYNC CPU_50S
PM_MEM_PWRGD
CPU_PWRGD

I150

CPU_SM_RCOMP

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

I120

CPU_VCCSENSE

I121

CPU_VCCSENSE

I122

CPU_VCCSENSE

I123

CPU_VCCSASENSE CPU_50S

I137

CPU_MEM_VREF CPU_VREF

I140

CPU_MEM_VREF CPU_VREF

I141

PHYSICAL

PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE

CPU_50S
CPU_50S

CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE

CPU_27P4S
CPU_27P4S
CPU_50S
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE

CPU_50S CPU_ITP

CPU_50S CPU_ITP
CPU_50S CPU_ITP
CPU_50S CPU_ITP
CPU_50S CPU_ITP

CPU_50S

CPU_50S CPU_VID
CPU_50S
CPU_50S CPU_ITP
CPU_50S

CPU_50S
CPU_50S
CPU_27P4S
CPU_50S CPU_VID
CPU_50S CPU_VID
CPU_50S CPU_VID
CPU_55S CPU_VID
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S

CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S

NET_TYPE

SPACING

CPU_AGTL
CPU_AGTL
CPU_AGTL

CPU_COMP
CPU_COMP

CLK_PCIE

CPU_AGTL
CPU_AGTL

CPU_AGTL

CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_COMP

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_AGTL

DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
FDI_DATA_P<7:0>
FDI_DATA_N<7:0>

FDI_FSYNC<1..0>

FDI_LSYNC<1..0>
FDI_INT
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

CPU_EDP_COMP
CPU_PEG_COMP
CPU_CFG<17..0>
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
DPLL_REF_CLK_P
DPLL_REF_CLK_N

XDP_CPU_TDI

XDP_CPU_TDO

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_BPM_L<3..0>

XDP_BPM_L<7..4>

XDP_DBRESET_L

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L
CPU_CATERR_L

CPU_PROC_SEL_L
CPU_PECI

CPU_PROCHOT_L

XDP_CPU_PWRGD

PM_THRMTRIP_L
PM_SYNC
PM_MEM_PWRGD

CPU_PWRGD
CPU_SM_RCOMP<2..0>

CPU_VIDSOUT

CPU_VIDSCLK

CPU_VIDALERT_L

CPU_VCCSA_VID<1..0>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPU_VCC_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_VALSENSE_N

CPU_VCCSASENSE

PPCPU_MEM_VREFDQ_A

PPCPU_MEM_VREFDQ_B

7

10 18

7

10 18

7

10 18

7

10 18

7

10 18

7

10 18

10 18

10 18

10 18

7

11 17

7

11 17

10

10

10 24

11 17

11 17

17 24

17 24

11 17

11 17

11 24

11 24

11 24

11 24

11 24

11 24

11 24

11 24 25

11 24

11 24

11 39

11 20

11 20 40

11 39 40 61

24

11 20 40

11 18

11 18 27

11 20 24

11

13 61

13 61

13 61

13 58

13 61

13 61

13 63

13 63

13 61

13 61

10

10

10

10

13 58

10 31

10 31

D

C

B

CPU_MEM_VREF CPU_VREF

I144

CPU_MEM_VREF CPU_VREF

I145

CPU_MEM_VREF CPU_VREF

I146

CPU_MEM_VREF CPU_VREF

I147

I148

I149

XDP_CLK_ITP
XDP_CLK_ITP

CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFCA_B

XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N

A

6 3

24

24

28 31

29 31

28 31

29 31

SYNC_MASTER=J5_MLB

PAGE TITLE

CPU Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/13/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

100 OF 132

SHEET

72 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

Memory Bus Constraints

D

MEM_37S

MEM_40S

MEM_72D

MEM_50S

MEM_85D

SPACING_RULE_SET

MEM_CLK2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CMD2CMD

MEM_CMD2MEM

MEM_DATA2DATA

MEM_DATA2MEM

MEM_DQS2MEM

MEM_2OTHER

MEM_DQBL2BL

MEM_DQCH2CH

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

*

=37_OHM_SE =37_OHM_SE =37_OHM_SE

*

*

=72_OHM_DIFF

*

=85_OHM_DIFF

*

LINE-TO-LINE SPACING

* ?

* ?

*

* ?

* ?

*

*

* ?

MINIMUM LINE WIDTH

=4X_DIELECTRIC

=3X_DIELECTRIC

=3X_DIELECTRIC

=2X_DIELECTRIC

=3X_DIELECTRIC

=2X_DIELECTRIC

=3X_DIELECTRIC

=4X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

=6X_DIELECTRIC

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

MEM_CTRL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*

MEM_*

MEM_*

MEM_CTRLMEM_CTRL

MEM_*

* *

AREA_TYPE

*

AREA_TYPE

*

*

AREA_TYPE

*

AREA_TYPE

=40_OHM_SE

=72_OHM_DIFF

=50_OHM_SE

=85_OHM_DIFF

WEIGHT

?*

?*

?*

?

?

?

SPACING_RULE_SET

MEM_CLK2MEM

SPACING_RULE_SET

MEM_CTRL2MEM

MEM_CTRL2CTRL

SPACING_RULE_SET

MEM_DQS2MEM

SPACING_RULE_SET

MEM_2OTHER

MINIMUM NECK WIDTH

=40_OHM_SE =40_OHM_SE=40_OHM_SE

=72_OHM_DIFF

=50_OHM_SE=50_OHM_SE

=85_OHM_DIFF =85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DQ_BYTE*

MEM_*_DQ_BYTE*

MEM_A_DQ_BYTE*

MEM_B_DQ_BYTE*

MEM_A_DQ_BYTE* MEM_B_DQ_BYTE*

MAXIMUM NECK LENGTH

=37_OHM_SE

=72_OHM_DIFF

=50_OHM_SE

MEM_*

MEM_CMD

MEM_*

=SAME

MEM_A_DQ_BYTE*

MEM_B_DQ_BYTE*

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

=STANDARD

=72_OHM_DIFF

=STANDARD =STANDARD

=85_OHM_DIFF

AREA_TYPE

AREA_TYPE

*

*

*

*

*

*

*

SPACING_RULE_SET

MEM_CMD2MEM

MEM_CMD2CMD

SPACING_RULE_SET

MEM_DATA2MEM

MEM_DATA2DATA

MEM_DQBL2BL

MEM_DQBL2BL

MEM_DQCH2CH

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=72_OHM_DIFF

=85_OHM_DIFF

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK
MEM_A_CLK

MEM_A_CNTL

MEM_A_CNTL

I101

MEM_A_CNTL

I102

MEM_A_CNTL

I103

MEM_A_CNTL

I104

MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD

MEM_A_DQ_BYTE0 MEM_50S
MEM_A_DQ_BYTE1 MEM_50S MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3

I105

MEM_A_DQS0

I106

MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7

MEM_B_CLK
MEM_B_CLK

MEM_B_CNTL

I110

MEM_B_CNTL

I111

MEM_B_CNTL

MEM_B_CNTL

I109

NET_TYPE

PHYSICAL

MEM_37S

MEM_37S
MEM_37S

MEM_37S
MEM_37S
MEM_40S
MEM_40S
MEM_40S

MEM_40S

MEM_50S MEM_A_DQ_BYTE2
MEM_50S MEM_A_DQ_BYTE3
MEM_50SMEM_A_DQ_BYTE4
MEM_50SMEM_A_DQ_BYTE5

MEM_50SMEM_A_DQ_BYTE7

MEM_85D
MEM_85D
MEM_85D
MEM_85D

MEM_37S
MEM_37S

MEM_37S

MEM_37S

SPACING

MEM_CLKMEM_72D
MEM_CLKMEM_72D

MEM_CTRL

MEM_CTRL
MEM_CTRL

MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMDMEM_40S
MEM_CMD

MEM_A_DQ_BYTE0

MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6MEM_50SMEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7

MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D

MEM_CLKMEM_72D
MEM_CLKMEM_72D

MEM_CTRL
MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CKE<1..0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

MEM_B_CS_L<3..0>

MEM_B_ODT<1..0>

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

7

12 28

7

12 28

7

12 28

7

12 28

7

12 28

7

12 28

7

12 28

7

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 29 30

12 29 30

12 29 30

12 29 30

12 29 30

12 29 30

D

C

B

DDR3 (Memory Down):

DQ signals should be matched within 0.508mm of associated DQS pair

.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.

SOURCE: Chief River SFF Platform DG, Rev 0.7 (#460452), Section 2.6.3

A

MEM_B_CMD

I108

MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD

MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE0MEM_50S
MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE1MEM_50S
MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE2MEM_50S
MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE3MEM_50S
MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE4MEM_50S
MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE5MEM_50S
MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE6MEM_50S
MEM_B_DQ_BYTE7 MEM_B_DQ_BYTE7MEM_50S

MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7

MEM_CMDMEM_40S

MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_CMDMEM_40S

MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D

MEM_B_A<15..0>

MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

6 3

12 29 30

12 29 30

12 29 30

12 29 30

12 29 30

7

12 29

7

12 29

7

12 29

7

12 29

7

12 29

7

12 29

7

12 29

7

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

SYNC_MASTER=J5_MLB

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/13/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

101 OF 132

SHEET

73 OF 80

124578

SIZE

B

A

D

8 7 6 5 4 3

Digital Video Signal Constraints

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

12

SPACING

D

SATA Interface Constraints

LAYER

SATA_90D

SATA_37SE

SATA_50SE

SPACING_RULE_SET

SATA

SATA_ICOMP

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

LAYER

*

*

*

*

*

ALLOW ROUTE
ON LAYER?

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

LINE-TO-LINE SPACING

C

USB 2.0 Interface Constraints

LAYER

PCH_USB_RBIAS

USB_85D

SPACING_RULE_SET

USB

USB_RBIAS

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

LAYER

USB 3.0 INTERFACE CONSTRAINTS

LAYER

USB3_85D

SPACING_RULE_SET

B

USB3

SOURCE: CR SFF PLATFORM DESIGN GUIDE V0.7, TABLE 4-211, 1X1+

LAYER

System Clock Signal Constraints

CLK_SLOW_55S

CLK_25M_55S

SPACING_RULE_SET

CLK_SLOW

CLK_25M =5x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

*

*

*

*

LAYER

LAYER

=STANDARD =STANDARD

=85_OHM_DIFF

LINE-TO-LINE SPACING

*

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

LINE-TO-LINE SPACING

ALLOW ROUTE
ON LAYER?

*

*

LINE-TO-LINE SPACING

* ?

MINIMUM LINE WIDTH

=5:1_SPACING

15 MIL

MINIMUM LINE WIDTH

=4:1_SPACING

15 MIL

MINIMUM LINE WIDTH

=5:1_SPACING

=2x_DIELECTRIC

MINIMUM NECK WIDTH

=90_OHM_DIFF

=50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

=85_OHM_DIFF

WEIGHT

=85_OHM_DIFF

WEIGHT

MINIMUM LINE WIDTH

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

NOTE: 25MHz system clocks very sensitive to noise.

?*

MAXIMUM NECK LENGTH

=90_OHM_DIFF

=37_OHM_SE=37_OHM_SE

=50_OHM_SE

SATA

=STANDARD =STANDARD

=85_OHM_DIFF

USB

USB3

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=85_OHM_DIFF

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=85_OHM_DIFF=85_OHM_DIFF

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=37_OHM_SE

LINE-TO-LINE SPACING

=5:1_SPACING

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

=85_OHM_DIFF

LINE-TO-LINE SPACING

=4:1_SPACING

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF

LINE-TO-LINE SPACING

=5:1_SPACING

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

WEIGHT

WEIGHT

WEIGHT

SATA_HDD_R2D

I257

SATA_HDD_R2D SATA_90D

I259

SATA_HDD_D2R SATA_90D

I258

SATA_HDD_D2R SATA_90D

I260

SATA_HDD_D2R SATA

I261

SATA_HDD_D2R

I262

SATA_HDD_R2D

I264

SATA_HDD_R2D

I263

SATA_HDD_D2R

I265

SATA_HDD_D2R

I266

SATA_HDD_R2D

I267

SATA_HDD_R2D

I268

=90_OHM_DIFF=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE=50_OHM_SE

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

SATA_HDD_R2D SATASATA_90D
SATA_HDD_R2D SATASATA_90D
SATA_HDD_D2R SATASATA_90D
SATA_HDD_D2R

SATA_HDD_D2R

I232

SATA_HDD_D2R

I233

SATA_HDD_R2D

I234

SATA_HDD_R2D

I235

SATA_90D SATA

SATA_90D

SATA_90D SATA
SATA_90D SATA
SATA_90D SATA
SATA_90D SATA
SATA_90D SATA
SATA_90D SATA

SATA
SATA
SATA

SATASATA_90D

SATA_90D SATA

SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D

SATA_HDD_R2D_RDRIN_P
SATA_HDD_R2D_RDRIN_N
SATA_HDD_D2R_RDROUT_P
SATA_HDD_D2R_RDROUT_N
SATA_HDD_D2R_RDRIN_P
SATA_HDD_D2R_RDRIN_N
SATA_HDD_R2D_RDROUT_N
SATA_HDD_R2D_RDROUT_P
SATA_HDD_D2R_RC_P
SATA_HDD_D2R_RC_N
SATA_HDD_R2D_RC_N
SATA_HDD_R2D_RC_P

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N

SATA_SSDRHDD_D2R_P
SATA_SSDRHDD_D2R_N

SATA_SSDRHDD_R2D_P

SATA_SSDRHDD_R2D_N

7

7

7

7

7

7

7

7

7

37

7

37

7

37

7

37

7

17 37

7

17 37

7

17 37

7

17 37

7

37

7

37

7

37

7

37

D

C

=85_OHM_DIFF

=85_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

PCH_SATA3_ICOMP

I213

PCH_SATA_ICOMP

USB_EXTB

I236

USB_EXTB

I237

USB_EXTB
USB_EXTB
USB_HUB2_UP
USB_HUB2_UP
USB_EXTA
USB_EXTA
USB_EXTB
USB_EXTB
USB_EXTC
USB_EXTC
USB_CAMERA
USB_CAMERA
USB_BT
USB_BT
USB_TPAD
USB_TPAD
USB_SMC
USB_SMC
PCH_USB_RBIAS
USB_EXTD

I238

USB_EXTD

I239

USB_EXTA

I245

USB_EXTA

I244

USB_CAMERA

I247

USB_CAMERA

I246

USB_EXTA

I248

USB_EXTA

I249

USB3_EXTB_TX USB3_85D USB3

I220

USB3_EXTB_TX USB3_85D USB3

I221

USB3_EXTB_RX USB3_85D USB3

I222

USB3_EXTB_RX USB3_85D USB3

I223

USB3_EXTA_TX USB3_85D

I230

I229

USB3_EXTA_RX USB3_85D

I228

I231

SATA_50SE
SATA_37SE

USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
PCH_USB_RBIAS
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D

USB3_85DUSB3_EXTA_TX

USB3_85DUSB3_EXTA_RX

SATA_ICOMP
SATA_ICOMP

USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB_RBIAS
USB
USB
USB
USB
USB
USB
USB
USB

USB3
USB3
USB3
USB3

PCH_SATA3COMP

PCH_SATAICOMP
USB_EXTB_XHCI_P

USB_EXTB_XHCI_N
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_HUB_UP_P
USB_HUB_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_P
USB_EXTB_N
USB_EXTD_P
USB_EXTD_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_SMC_P
USB_SMC_N
PCH_USB_RBIAS
USB_EXTD_XHCI_P
USB_EXTD_XHCI_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_CAMERA_P
USB_CAMERA_N
USB_LT1_P
USB_LT1_N
USB3_EXTB_TX_P
USB3_EXTB_TX_N
USB3_EXTB_RX_P
USB3_EXTB_RX_N

USB3_EXTA_TX_P
USB3_EXTA_TX_N
USB3_EXTA_RX_P
USB3_EXTA_RX_N

17

17

19 26

19 26

19 26

19 26

19 26

19 26

19 38

19 38

7

7

7

7

7 9

7 9

9

9

9

9

19

19 26

19 26

38

38

19 32

19 32

7

7

19 36

19 36

7

7

19 38

7

7

7

26 36

26 36

32

32

47

47

39

39

38

38

19 36

19 36

19 38

19 38

19 38

36

36

B

A

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

SYSCLK_CLK32K_RTC

I256

SYSCLK_CLK25M_SB

I255

I254

SYSCLK_CLK25M_ENET

I253

I252

SYSCLK_CLK25M_TBT

I251

I250

CLK_SLOW_55S CLK_SLOW

CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S

PHYSICAL

NET_TYPE

SPACING

CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M

SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB

SYSCLK_CLK25M_SB_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT_R

17 25

17 25

17

25 33

33

6 3

SYNC_MASTER=J5_MLB_KEPLER

PAGE TITLE

PCH Constraints 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/21/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

102 OF 132

SHEET

74 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

LPC Bus Constraints

LAYER

LPC_50S

CLK_LPC_50S

SPACING_RULE_SET

LPC

CLK_LPC

D

SMBus Interface Constraints

SMB_50S

SPACING_RULE_SET

SMB

LAYER

LAYER

LAYER

HD Audio Interface Constraints

LAYER

HDA_50S

SPACING_RULE_SET

HDA

LAYER

SIO Signal Constraints

LAYER

CLK_SLOW_55S

ALLOW ROUTE
ON LAYER?

*

=50_OHM_SE

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE

LINE-TO-LINE SPACING

*

* ?

ALLOW ROUTE
ON LAYER?

*

LINE-TO-LINE SPACING

*

*

*

*

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=50_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE

C

SPACING_RULE_SET

CLK_SLOW

LAYER

LINE-TO-LINE SPACING

*

MINIMUM LINE WIDTH

6 MIL

8 MIL

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

8 MIL

MINIMUM NECK WIDTH

=50_OHM_SE =50_OHM_SE

=50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

=50_OHM_SE

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=50_OHM_SE

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE=50_OHM_SE

MAXIMUM NECK LENGTH

=55_OHM_SE

DIFFPAIR PRIMARY GAP

=STANDARD

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=STANDARD

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD
LPC_FRAME_L
LPC_RESET_L

PCH_LPC_CLK0

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

SPI_CLK

SPI_MOSI

SPI_MISO

PCIE_ENET_R2D
PCIE_ENET_R2D
PCIE_ENET_D2R
PCIE_ENET_D2R

NET_TYPE

PHYSICAL

LPC_50S
LPC_50S
LPC_50S

CLK_LPC_50S
CLK_LPC_50S
CLK_LPC_50S

SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S

HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S

SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55SSPI_CS0
SPI_55S

PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE

LPC
LPC
LPC

CLK_LPC
CLK_LPC
CLK_LPC

SMB
SMB
SMB
SMB
SMB
SMB

HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA

SPI
SPI
SPI
SPI
SPI
SPI
SPI

SPACING

LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L

LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA

HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R

SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L

PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N

7

17 39 41

7

17 39 41

25

19 25

7

25 39

7

25 41

7

17 42

7

17 42

17 42

17 42

17 42

17 42

17 51

17

17 51

17

17

17 51

17 51

51

17 51

17 25

17 41

41

17 41

41

17 41

17 41

41

7

17 36

7

17 36

7

17 36

7

17 36

12

D

C

SPI Interface Constraints

LAYER

SPI_55S

SPACING_RULE_SET

SPI

*

LAYER

*

B

A

ALLOW ROUTE
ON LAYER?

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

8 MIL

PCIE_AP_R2D

I275
I276

I278

I277

PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_D2R
PCIE_AP_D2R

PCIE_AP_D2R
PCIE_AP_D2R
PCIE_AP_D2R
PCIE_AP_D2R

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE =55_OHM_SE=55_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MAXIMUM NECK LENGTH

=55_OHM_SE

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE

PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE

PCIE
PCIE
PCIE

PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N

PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N

7

36

7

36

7

17 36

7

17 36

7

17 36

7

17 36

7

36

7

36

7

36

7

36

B

PCIE_CLK100M_PCH

I253

PCIE_CLK100M_PCH

I254

PCIE_CLK100M_TBT

I262

PCIE_CLK100M_TBT

I261

PCH_CLK96M

I255

PCH_CLK96M

I257

PCH_CLK100M_SATA

I256

PCH_CLK100M_SATA

I259

I258

I260

PCIE_CLK100M_SSD

I279

PCIE_CLK100M_SSD

I280

PCIE_CLK100M_ENET
PCIE_CLK100M_ENET
PCIE_CLK100M_AP
PCIE_CLK100M_AP
PCIE_CLK100M_FW
PCIE_CLK100M_FW
PCIE_CLK100M_EXCARD
PCIE_CLK100M_EXCARD

I263

PCIE_TBT_R2D PCIE_85D

I264

PCIE_TBT_R2D PCIE_85D

I265

I267

I266

I268

I270

I269

CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CPU_50S
CPU_50S

CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D

CLK_PCIE_90D
CLK_PCIE_90D

CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D

PCIE_85DPCIE_TBT_R2D

CLK_PCIE
CLK_PCIECLK_PCIE_90D

CLK_PCIE
CLK_PCIE

CLK_PCIE
CLK_PCIE
CLK_PCIEPCIE_CLK100M
CLK_PCIECLK_PCIE_90DPCIE_CLK100M
CLK_PCIECLK_PCIE_90D
CLK_PCIECLK_PCIE_90D
CLK_PCIE
CLK_PCIE
CLK_PCIECLK_PCIE_90D
CLK_PCIE
CLK_PCIE
CLK_PCIE

PCIE
PCIE
PCIE
PCIEPCIE_TBT_R2D PCIE_85D
PCIEPCIE_TBT_D2R PCIE_85D
PCIEPCIE_85DPCIE_TBT_D2R
PCIEPCIE_85DPCIE_TBT_D2R
PCIEPCIE_TBT_D2R PCIE_85D

6 3

PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN

PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N

PCIE_TBT_R2D_C_P<3..0>
PCIE_TBT_R2D_C_N<3..0>
PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>
PCIE_TBT_D2R_P<3..0>
PCIE_TBT_D2R_N<3..0>
PCIE_TBT_D2R_C_P<3..0>
PCIE_TBT_D2R_C_N<3..0>

7

17

7

17

7

17 33

7

17 33

17

17

7

17

17

17

7

17 25

7 9

17

7 9

17

7 9

17

7 9

17

7

17 36

7

17 36

7

17 36

7

17 36

7 9

17

7 9

17

7

17

7

17

7 9

33

7 9

33

7

33

7

33

7 9

33

7 9

33

7

33

7

33

SYNC_MASTER=J5_MLB

PAGE TITLE

PCH Constraints 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

103 OF 132

SHEET

75 OF 80

SIZE

A

D

124578

8 7 6 5 4 3

DisplayPort Signal Constraints
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

Thunderbolt SPI Signal Constraints

LAYER

TBT_SPI_55S

SPACING_RULE_SET

LAYER

TBT_SPI

D

Thunderbolt/DP Connector Signal Constraints

LAYER

TBTDP_85D =85_OHM_DIFF

SPACING_RULE_SET

LAYER

TBTDP

NOTE: Thunderbolt high-speed nets are NOT directly assigned to TBTDP_*D physical rules.
TABLE_PHYSICAL_ASSIGNMENT symbols must be used to create the assignments.
Proper differential impedance depends on mDP connector used.
For 514-0637: R2D nets (SMT pins) = 80D, D2R nets (TH pins) = 100D

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

ALLOW ROUTE
ON LAYER?

*

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

LINE-TO-LINE SPACING

=5x_DIELECTRIC

*

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

TBTDP

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM?=7x_DIELECTRIC

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

12

Thunderbolt/DP Net Properties

ELECTRICAL_CONSTRAINT_SET

I308

I309

I305

I304

TBT_A_R2D
TBT_A_R2D

TBT_A_R2D

DP_TBTPA_ML
DP_TBTPA_ML
DP_TBTPA_ML
DP_TBTPA_ML
DP_LSX_ML
DP_LSX_ML

TBT_A_D2R1
TBT_A_D2R1
TBT_A_D2R0
TBT_A_D2R0

TBT_A_D2R1
TBT_A_D2R1
TBT_A_D2R0
TBT_A_D2R0

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL

TBTDP_85D
TBTDP_85D
TBTDP_85DTBT_A_R2D
TBTDP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D

NET_TYPE

SPACING

TBTDP
TBTDP
TBTDP
TBTDP

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

TBTDP
TBTDP
TBTDP
TBTDP

TBTDP
TBTDP
TBTDP
TBTDP

TBT_A_R2D_C_P<1..0>
TBT_A_R2D_C_N<1..0>
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>

DP_TBTPA_ML_C_P<3..1:2>
DP_TBTPA_ML_C_N<3..1:2>
DP_TBTPA_ML_P<3..1:2>
DP_TBTPA_ML_N<3..1:2>
DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>
TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>
TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

7

7

7

7

33 69

33 69

69

69

69

69

7

7

7

7

7

7

7

7

33 69

33 69

69

69

69

69

69

69

33 69

33 69

33 69

33 69

D

Digital Video Signal Constraints

HDMI_90D

C

SPACING_RULE_SET

DISPLAYPORT

HDMI

B

LAYER

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

*

*
*

LINE-TO-LINE SPACING

=3x_DIELECTRIC
=3x_DIELECTRIC

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=85_OHM_DIFF =85_OHM_DIFFDP_85D
=90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF

WEIGHT

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

DISPLAYPORT

HDMI

LAYER

TOP,BOTTOM
TOP,BOTTOM

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC
=4x_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TBT_A_AUXCH
TBT_A_AUXCH
TBT_A_AUXCH
TBT_A_AUXCH

TBT_A_D2R1
TBT_A_D2R1

TBT_A_R2D TBTDP_85D
TBT_A_R2D TBTDP_85D
TBT_A_R2D
TBT_A_R2D

DP_TBTPB_ML DISPLAYPORT
DP_TBTPB_ML
DP_TBTPB_ML DISPLAYPORT
DP_TBTPB_ML DISPLAYPORT
DP_LSX_ML
DP_LSX_ML

TBT_A_D2R0
TBT_A_D2R0
TBT_A_D2R1

I310

TBT_A_D2R1

I311

TBT_A_D2R0
TBT_A_D2R0
TBT_A_D2R1

I306

TBT_A_D2R1

I307

TBT_B_AUXCH
TBT_B_AUXCH DISPLAYPORT
TBT_B_AUXCH DISPLAYPORT
TBT_B_AUXCH DISPLAYPORT

TBT_A_D2R1
TBT_A_D2R1

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
TBTDP_85D
TBTDP_85D

TBTDP_85D
TBTDP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
TBTDP_85D
TBTDP_85D

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
TBTDP
TBTDP

TBTDP
TBTDP
TBTDP
TBTDP

DISPLAYPORT

DISPLAYPORT
DISPLAYPORT

TBTDP
TBTDP
TBTDP
TBTDP

TBTDP
TBTDP
TBTDP
TBTDP
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
TBTDP
TBTDP

DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_N
DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

TBT_B_R2D_C_P<1..0>
TBT_B_R2D_C_N<1..0>
TBT_B_R2D_P<1..0>
TBT_B_R2D_N<1..0>

DP_TBTPB_ML_C_P<3..1:2>
DP_TBTPB_ML_C_N<3..1:2>
DP_TBTPB_ML_P<3..1:2>
DP_TBTPB_ML_N<3..1:2>
DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBT_B_D2R_C_P<0>
TBT_B_D2R_C_N<0>
TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>

TBT_B_D2R_P<0>
TBT_B_D2R_N<0>
TBT_B_D2R_P<1>
TBT_B_D2R_N<1>
DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_P
DP_TBTPB_AUXCH_N
DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N

33 69

33 69

69

69

69

69

69

69

7

33 70

7

33 70

7

70

7

70

33 70

33 70

70

70

70

70

Only used on dual-port hosts.

7

70

7

70

7

70

7

70

7

33 70

7

33 70

7

33 70

7

33 70

33 70

33 70

70

70

70

70

70

70

C

B

Thunderbolt IC Net Properties

ELECTRICAL_CONSTRAINT_SET

TBT_SPI_MOSI
TBT_SPI_MISO

A

TBT_SPI_CS_L

6 3

PHYSICAL

DP_85D
DP_85D
DP_85D
DP_85D

TBT_SPI_55STBT_SPI_CLK
TBT_SPI_55S
TBT_SPI_55S
TBT_SPI_55S

NET_TYPE

SPACING

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

TBT_SPI
TBT_SPI
TBT_SPI
TBT_SPI

DP_TBTSRC_ML_C_P<3..0>
DP_TBTSRC_ML_C_N<3..0>
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N

TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L

Only used on hosts supporting Thunderbolt video-in

33

33

33

33

SYNC_MASTER=T29_CR

PAGE TITLE

Thunderbolt Constraints

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

R

SYNC_DATE=08/31/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

105 OF 132

SHEET

76 OF 80

124578

SIZE

A

D

8 7 6 5 4 3

12

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_SCL
SMBUS_SMC_5_SDA

D

SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA

SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

CHGR_CSI
CHGR_CSI

CHGR_CSO
CHGR_CSO

1TO1_DIFFPAIR
1TO1_DIFFPAIR

1TO1_DIFFPAIR
1TO1_DIFFPAIR

C

PHYSICAL

PHYSICAL

NET_TYPE

NET_TYPE

SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB

SPACING

SPACING

SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_SCL
SMBUS_SMC_5_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA

CHGR_CSI_P
CHGR_CSI_N

CHGR_CSO_P
CHGR_CSO_N

7

7

7

7

39 42

39 42

39 42

39 42

57

57

57

57

39 42

39 42

39 42

39 42

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=J5_MLB

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

106 OF 132

SHEET

77 OF 80

124578

8 7 6 5 4 3

12

SENSE_1TO1_55S
THERM_1TO1_55S

DIFFPAIR

AUDIODIFF

SPACING_RULE_SET

D

SENSE
THERM
AUDIO

SPACING_RULE_SET

GND

SPACING_RULE_SET

GND_P2MM
PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND
GND
GND
GND
GND

C

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_72D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_37S 0.09 MM 100 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

PCIE_85D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

USB_85D

CPU_27P4S

USB3_85D

*
*

ALLOW ROUTE
ON LAYER?

=1:1_DIFFPAIR
=1:1_DIFFPAIR

LAYER

*

=1:1_DIFFPAIR

*

LAYER

LAYER

LINE-TO-LINE SPACING

=2:1_SPACING

* ?

=2:1_SPACING

* ?

=2:1_SPACING

*

LINE-TO-LINE SPACING

*

LAYER

LINE-TO-LINE SPACING

*
*

MEM_CLK
MEM_CMD

MEM_CTRL

MEM_*_DQ_BYTE*

MEM_DQS

LAYER

ALLOW ROUTE
ON LAYER?

*

*

*

*

*

TOP

BOTTOM

TOP

=STANDARD

0.20 MM

0.20 MM

AREA_TYPE

*
*
*
*
*

MINIMUM LINE WIDTH

=55_OHM_SE
=55_OHM_SE

0.1 MM 0.1 MM

WEIGHT

WEIGHT

WEIGHT

1000
1000

SPACING_RULE_SET

GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM

MINIMUM LINE WIDTH

ISL10

DP_85D

PCIE_85D 0.075 MM

ISL9

ISL10

B

DDR3 Loaded Segment Constraint Relaxations
Alternate single ended and differential impedances between devices.

NET_PHYSICAL_TYPE

Graphics ,SATA Constraint Relaxations
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

NET_PHYSICAL_TYPE

AREA_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

PHYSICAL_RULE_SET

BGA 100_DIFF_BGADP_85D

SATA_90D

100_DIFF_BGABGA
100_DIFF_BGABGACLK_PCIE_90D

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_50SMEM_37S BGA_MEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_50SBGA_MEMMEM_40S

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_85DMEM_72D BGA_MEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=55_OHM_SE
=55_OHM_SE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_COMP

CPU_VCCSENSE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_PCIE

PCIE
SATA
USB3

CLK_PCIE SB_POWER

SATA
USB3

USB

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

0.09 MM 100 MIL

0.09 MM 100 MIL

0.09 MMMEM_85D

0.09 MM

0.1 MM

0.1 MM

0.075 MMUSB3_85D

0.075 MM

=55_OHM_SE
=55_OHM_SE

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR =1:1_DIFFPAIR=1:1_DIFFPAIR=1:1_DIFFPAIR

10 MM

GND
GND

GND
GND
GND
GND
GNDUSB

SB_POWER
SB_POWER PWR_P2MM
SB_POWER

0.1 MM 0.1 MM

AREA_TYPE

SPACING_RULE_SET

*
*

AREA_TYPE

SPACING_RULE_SET

*
*
*
*
*
*
*
*
*

DIFFPAIR PRIMARY GAP

GND_P2MM
GND_P2MM

GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
PWR_P2MM
PWR_P2MM

PWR_P2MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

100 MIL

10 mm

500 MIL
100 MIL0.23 MM
500 MIL

*
*
*
*
*

PHYSICAL_RULE_SET

AUDIODIFF

1:1_DIFFPAIR

THERM_1TO1_55STHERM_1TO1_55S

DIFFPAIR

NET_PHYSICAL_TYPE

AREA_TYPE

AUDIODIFF

1TO1_DIFFPAIR

SENSE_1TO1_55S SENSE_1TO1_55S

DIFFPAIR

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

0.090 MM

0.090 MM

0.090 MM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

D1 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR THERM_1TO1_55S

I430

SENSE_DIFFPAIR THERM_1TO1_55S

I431

SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S

I432

SENSE_DIFFPAIR

I433

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S

I405

SENSE_DIFFPAIR

I406

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S

HDMI_CLK HDMIHDMI_90D

I414

HDMI_CLK HDMIHDMI_90D

I413

HDMI_DATA

I416

HDMI_DATA

I415

NET_TYPE

PHYSICAL

THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S

SPACING

THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM

THERM
THERM
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE

HDMIHDMI_90D
HDMIHDMI_90D

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N

GPUTHMSNS_D_P

GPUTHMSNS_D_N

GPU_TDIODE_P

GPU_TDIODE_N

TBT_THERMD_P

TBT_THERMD_N

DDR3THMSNS_D1_P

DDR3THMSNS_D1_N
CPUVCCIOS0_CS_P
CPUVCCIOS0_CS_N

CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
ISNS_LCD_PANEL_P
ISNS_LCD_PANEL_N
ISNS_1V35_S3_MEM_P
ISNS_1V35_S3_MEM_N
ISNS_SSD_P
ISNS_SSD_N
ISNS_3V3_S0_SSD_R_P
ISNS_3V3_S0_SSD_R_N
ISNS_WLAN_P
ISNS_WLAN_N
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N

ISNS_TBT_P
ISNS_TBT_N

ISNS_1V35_S3_MEM_R_P

ISNS_1V35_S3_MEM_R_N
VCCSAS0_CS_P
VCCSAS0_CS_N

HDMI_IG_CLK_C_P

HDMI_IG_CLK_C_N

HDMI_IG_DATA_C_P<2..0>
HDMI_IG_DATA_C_N<2..0>

45

45

9

9

45

45

45

45

45

45

45

45

43 63

43 63

13

13

43

43

37 43

37 43

43

43

80

80

43

43

58 80

58 80

7 9

7 9

7 9

7 9

D1 Specific Net Properties

PCIE_CLK100M_AP

10

10

36

36

36

36

PCIE_CLK100M_AP

USB_BT
USB_BT
USB_BT

I434

USB_BT

I435

AUDIO_DIFFPAIR

I358

AUDIO_DIFFPAIR

I357

AUDIO_DIFFPAIR

I360

AUDIO_DIFFPAIR

I359

AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR

SENSE_DIFFPAIR

I421

SENSE_DIFFPAIR SENSE_1TO1_55S

I420

SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
SENSE_DIFFPAIR

I428

SENSE_DIFFPAIR

I429

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR

I422

SENSE_DIFFPAIR

I423

SENSE_DIFFPAIR

I424

SENSE_DIFFPAIR

I425

SENSE_DIFFPAIR

I426

SENSE_DIFFPAIR

I427

AUDIO_DIFFPAIR

I343

AUDIO_DIFFPAIR

I344

AUDIO_DIFFPAIR

I345

AUDIO_DIFFPAIR

I346

AUDIO_DIFFPAIR

I348

AUDIO_DIFFPAIR

I347

AUDIO_DIFFPAIR

I350

AUDIO_DIFFPAIR

I349

AUDIO_DIFFPAIR

I351

AUDIO_DIFFPAIR

I352

AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR

I361

AUDIO_DIFFPAIR

I362

AUDIO_DIFFPAIR

I397

AUDIO_DIFFPAIR

I398

AUDIO_DIFFPAIR

I399

AUDIO_DIFFPAIR

I400

AUDIO_DIFFPAIR

I401

AUDIO_DIFFPAIR

I402

AUDIO_DIFFPAIR

I403

AUDIO_DIFFPAIR

I404

AUDIO_DIFFPAIR

I438

AUDIO_DIFFPAIR

I439

AUDIO_DIFFPAIR

I440

AUDIO_DIFFPAIR

I441

AUDIO_DIFFPAIR

I445

AUDIO_DIFFPAIR

I444

AUDIO_DIFFPAIR

I443

AUDIO_DIFFPAIR

I442

USB_TPAD
USB_TPAD
USB_HUB USB_85D

I436

USB_HUB USB_85D

I437

DIFFPAIR
DIFFPAIR

DIFFPAIR
DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF

NET_TYPE

PHYSICAL

CLK_PCIE_90D
CLK_PCIE_90D
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
USB_85D
USB_85D
USB_85D
USB_85D

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
USB_85D
USB_85D

SPACING

CLK_PCIE
CLK_PCIE

USB
USB
USB
USB

AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
USB
USB
USB
USB

SB_POWER
SB_POWER
SB_POWER

GND

PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N

CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N

USB_BT_CONN_P
USB_BT_CONN_N
USB_BT_WAKE_P
USB_BT_WAKE_N

SPKRCONN_SL_OUT_P
SPKRCONN_SL_OUT_N

SPKRCONN_SR_OUT_P
SPKRCONN_SR_OUT_N
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N

CPUIMVP_ISNSG_P
CPUIMVP_ISNSG_N
CPUIMVP_ISNS1G_P
CPUIMVP_ISNS1G_N

CPUIMVP_ISNS2G_P

CPUIMVP_ISNS2G_N
CPUIMVP_ISUMG_R_P
CPUIMVP_ISUMG_R_N

ISNS_HS_OTHER_P

ISNS_HS_OTHER_N

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N
CPUIMVP_ISNS_P
CPUIMVP_ISNS_N
CPUIMVP_ISNS1_P
CPUIMVP_ISNS1_N
CPUIMVP_ISNS2_P
CPUIMVP_ISNS2_N
CPUIMVP_ISUM_R_P
CPUIMVP_ISUM_R_N

AUD_LO1_L_P
AUD_LO1_L_N
AUD_LO1_R_P
AUD_LO1_R_N
AUD_LO2_L_P
AUD_LO2_L_N
AUD_LO2_R_P
AUD_LO2_R_N
AUD_MIC_INL_P

AUD_MIC_INL_N
AUD_SPKRAMP_LIN_P
AUD_SPKRAMP_LIN_N
AUD_SPKRAMP_RIN_P
AUD_SPKRAMP_RIN_N
AUD_SPKRAMP_LSUBIN_P
AUD_SPKRAMP_LSUBIN_N
AUD_SPKRAMP_RSUBIN_P
AUD_SPKRAMP_RSUBIN_N

RSUBIN_P

RSUBIN_N

LSUBIN_P

LSUBIN_N

SPKRAMP_LIN_P
SPKRAMP_LIN_N
SPKRAMP_RIN_P
SPKRAMP_RIN_N

HS_MIC_HI_RC

HS_MIC_LO_RC
HS_MIC_HI
HS_MIC_LO

SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N
USB_TPAD_R_P
USB_TPAD_R_N

PU_USBHUB_DN4_P
PU_USBHUB_DN4_N

PP3V3_S5
PP3V3_S0
PP1V5_S3RS0_CPUDDR

GND

57

57

57

57

7

36

7

36

36

36

36

36

7

53 55

7

53 55

7

53 55

7

53 55

7

53 55 78

7

53 55 78

7

53 55 78

7

53 55 78

43

43

43 62

43 62

43 62

43 62

43

43

44

44

44

44

43

43

43 61 62

43 62

43 61 62

43 62

43

43

51 53

51 53

51 53

51 53

51 53

51 53

51 53

51 53

51 54

51 54

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

54

54

54

54

7

53 55 78

7

53 55 78

7

53 55 78

7

53 55 78

26 47

26 47

9

9

7 8

7 8

8

D

C

B

Memory Constraint Relaxations

A

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

TOP

ALLOW ROUTE
ON LAYER?

LAYER

MEM_72D 6.35 MM

BOTTOM

MEM_85D

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.127 MM

0.1 MM

MAXIMUM NECK LENGTH

6.35 MM

DIFFPAIR PRIMARY GAP

6 3

SIZE

A

D

SYNC_MASTER=J5_MLB

PAGE TITLE

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Project Specific Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

108 OF 132

SHEET

78 OF 80

124578

8 7 6 5 4 3

12

D1 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

STANDARD

D

55_OHM_SE

LAYER

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

*
* Y

ALLOW ROUTE
ON LAYER?

Y

Y

55_OHM_SE

ALLOW ROUTE
ON LAYER?

Y
Y* =STANDARD

ALLOW ROUTE
ON LAYER?

Y

*

Y =STANDARD =STANDARD

ALLOW ROUTE
ON LAYER?

Y

* =STANDARD

Y =STANDARD

ALLOW ROUTE
ON LAYER?

Y

C

50_OHM_SE
50_OHM_SE

40_OHM_SE
40_OHM_SE

37_OHM_SE
37_OHM_SE

27P4_OHM_SE

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

27P4_OHM_SE

LAYER

ALLOW ROUTE
ON LAYER?

72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF

85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

* N

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

Y
Y
Y

ALLOW ROUTE
ON LAYER?

Y
Y
Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=50_OHM_SE

=DEFAULT =DEFAULT

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.090 MM

0.076 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.090 MM

0.070 MM 0.070 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.145 MM

0.105 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.165 MM

0.120 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.265 MM

0.190 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=STANDARD

0.124 MM

0.124 MM

0.140 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=STANDARD

0.089 MM

0.089 MM

0.110 MM

=50_OHM_SE

0.090 MM

0.076 MM

0.090 MM

0.095 MM

0.090 MM

0.095 MM

0.090 MM

0.095 MM

0.1 MM

0.124 MM

0.124 MM

0.140 MM

=STANDARD =STANDARD

0.089 MM

0.089 MM

0.110 MM

BOARD AREAS

NO_TYPE,BGA,BGA_MEM

MAXIMUM NECK LENGTH

10 MM
10 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

MAXIMUM NECK LENGTH

BOARD UNITS
(MIL or MM)

MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0 MM

=DEFAULT =DEFAULT

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARDN*

0.200 MM

0.200 MM

0.120 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD

0.180 MM

0 MM

=STANDARD* Y

=STANDARD=STANDARDY*

=STANDARD

0.200 MM

0.200 MM

0.120 MM

0.180 MM0.180 MM

0.180 MM

0.180 MM0.180 MM

ALLEGRO
VERSION

16.2

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

SPACING_RULE_SET

LAYER

DEFAULT

STANDARD =DEFAULT

P072_SPACE

*
*
*

LINE-TO-LINE SPACING

0.1 MM

0.071 MM

WEIGHT

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

* *

AREA_TYPE

BGA

TABLE_SPACING_ASSIGNMENT_HEAD

SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

P072_SPACE

D

Stackup-Defined Spacing Rules

WEIGHT

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

C

J4 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

SPACING_RULE_SET

1:1_SPACING
1:1_SPACING
1:1_SPACING

Note: Outer dielectric is 0.058 mm nominal,
Inner dielectric is 0.053 mm nominal.

SPACING_RULE_SET

1x_DIELECTRIC
1x_DIELECTRIC
1X_DIELECTRIC

LAYER

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

LAYER

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

LINE-TO-LINE SPACING

0.1 MM

0.1 MM

0.101 MM

LINE-TO-LINE SPACING

0.058 MM

0.053 MM

0.101 MM

B

*

*

*

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

A

90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF

100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF

100_DIFF_BGA
100_DIFF_BGA
100_DIFF_BGA

LAYER

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ISL3,ISL4

ISL9,ISL10

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

LAYER

1:1_DIFFPAIR

ALLOW ROUTE
ON LAYER?

*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=STANDARD =STANDARD
Y
Y
Y

N
Y
Y
Y

Y
Y

0.081 MM 0.081 MM

0.081 MM

0.099 MM

MINIMUM LINE WIDTH

=STANDARD

0.081 MM

0.090 MM

MINIMUM NECK WIDTH

=STANDARD

0.065 MM 0.065 MM

0.065 MM

0.079 MM

MINIMUM LINE WIDTH

=100_OHM_DIFF =100_OHM_DIFF

0.065 MM

0.079 MM

MINIMUM NECK WIDTH

=100_OHM_DIFF

0.075 MM 0.075 MM

0.075 MM

MINIMUM LINE WIDTH

=STANDARD

0.075 MM

MINIMUM NECK WIDTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARDN

DIFFPAIR PRIMARY GAP

0.200 MM

0.200 MM

0.200 MM 0.200 MM

DIFFPAIR PRIMARY GAP

0.125 MM 0.125 MM

DIFFPAIR PRIMARY GAP

DP_TBT_AUXCH

I64

DP_TBT_AUXCH

I63

DP_TBT_AUXCH

I65

DP_TBT_AUXCH

I67

DP_TBT_ML

I66

DP_TBT_ML

I69

DP_TBT_ML

I68

DP_TBT_ML

I70

DP_TBT_AUXCH

I72

DP_TBT_AUXCH

I71

DP_TBT_AUXCH

I74

DP_TBT_AUXCH

I73

DP_TBT_ML

I75

DP_TBT_ML

I77

DP_TBT_ML

I76

DP_TBT_ML

I78

DP_INT_ML

I62

DP_INT_ML

I61

DP_INT_AUX

I59

DP_INT_AUX

I60

DP_INT_AUX

I57

DP_INT_AUX

I58

DP_INT_ML

I56

DP_INT_ML

I55

DP_INT_ML

I54

DP_INT_ML

I53

USB3_EXTB_RX

I41

USB3_EXTB_RX

I42

USB3_EXTA_RX

I43

USB3_EXTA_RX

I44

USB3_EXTA_TX

I45

USB3_EXTA_TX

I46

USB3_EXTB_TX

I47

USB3_EXTB_TX USB3_85D USB3

I48

0.200 MM0.200 MM

0.200 MM0.200 MM

0.200 MM0.200 MM

=STANDARD=STANDARD

0.200 MM

0.200 MM

0.125 MM0.125 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF=100_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.1 MM 0.1 MMY

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D
DP_85D
DP_85D

USB3_85D USB3

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

USB3USB3_85D
USB3USB3_85D
USB3USB3_85D
USB3USB3_85D
USB3USB3_85D
USB3USB3_85D

DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK0_ML_C_P<3..0>
DP_TBTSNK0_ML_C_N<3..0>
DP_TBTSNK1_ML_C_P<3..0>
DP_TBTSNK1_ML_C_N<3..0>
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
DP_TBTSNK0_ML_P<3..0>
DP_TBTSNK0_ML_N<3..0>
DP_TBTSNK1_ML_P<3..0>
DP_TBTSNK1_ML_N<3..0>

DP_INT_ML_C_P<3..0>
DP_INT_ML_C_N<3..0>
DP_INT_AUX_C_P
DP_INT_AUX_C_N
DP_INT_AUX_P
DP_INT_AUX_N

DP_INT_ML_P<3..0>
DP_INT_ML_N<3..0>
DP_INT_ML_F_P<3..0>
DP_INT_ML_F_N<3..0>

USB3_EXTB_RX_RC_P
USB3_EXTB_RX_RC_N

USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N
USB3_EXTA_TX_C_P
USB3_EXTA_TX_C_N
USB3_EXTB_TX_C_P
USB3_EXTB_TX_C_N

6 3

9

33

9

33

9

33

9

33

9

33

9

33

9

33

9

33

33

33

33

33

33

33

33

33

9

67

9

67

9

67

9

67

7

67

7

67

67

67

SYNC_MASTER=J5_MLB

PAGE TITLE

7

36

7

36

7

38

7

38

7

38

7

38

7

36

7

36

PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

109 OF 132

SHEET

79 OF 80

124578

SIZE

B

A

D

8 7 6 5 4 3

12

LCD Backlight Current Sense (IBLC)

Gain: 500x. EDP: 0.9 A
Rsense: 0.005 (RD200 / XWD200)
V across Rsense: 4.5 mV
SMC AD: 17

D

=PPBUS_SW_BKL

8

OUT

NC_ISNS_LCDBKLTN

2

XWD200

PPBUS_SW_LCDBKLT_PWR

71

IN

Airport X29 Current Sense (IAPC)

Gain: 500x. EDP: 1.06 A
Rsense: 0.005 (RD230 / XWD230)
V across Rsense: 5.3 mV
SMC AD: 22

PP3V3_WLAN_F

7

36 40

OUT

MIN_LINE_WIDTH=0.6 mm

C

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

XWD230

PP3V3_WLAN_R

36

IN

7

SM

7

1

2

7

SM

7

1

NC_ISNS_LCDBKLTP

=PP3V3_S0_ISNS

8

43 80

LOADISNS:YES

=PP3V3_S0_ISNS

8

43 80

NC_ISNS_WLANN

NC_ISNS_WLANP

LOADISNS:YES

1

CD200

3

V+

UD200

INA211

5

SC70

IN-

4

GND

OUT

REFIN+

2

0.1UF

20%
10V

2

CERM
402

LOADISNS:YES

6

ISNS_LCDBKLT_IOUT

1

RD209

4.53K

1 2

1/20W

PLACE_NEAR=U4900.G1:5MM

LOADISNS:YES

SMC_LCDBKLT_ISENSE

1%

1

MF

CD209

201

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.G1:5MM

LOADISNS:YES

40

OUT

www.qdzbwx.com

1

CD230

3

V+

UD230

INA211

5

SC70

IN-

4

GND

OUT

REFIN+

2

0.1UF

20%
10V

2

CERM
402

LOADISNS:YES

6

ISNS_WLAN_IOUT

1

RD239

4.53K

1 2

1/20W

PLACE_NEAR=U4900.B8:5MM

LOADISNS:YES

201

1%
MF

SMC_X29_ISENSE

1

CD239

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.B8:5MM

LOADISNS:YES

GND_SMC_AVSS

OUT

40

39 40 43 44 80

CPU SA Current Sense (IC2C)

Gain: 500x. EDP: 6 A
Rsense: 0.001 (R7140)
V across Rsense: 6 mV
SMC AD: 13

VCCSAS0_CS_N

58 78

IN

VCCSAS0_CS_P

58 78

IN

LCD Panel Current Sense (ILDC)

Gain: 500x. EDP: 1 A
Rsense: 0.005 (R9020, XW9020)
V across Rsense: 5 mV
SMC AD: 15

NC_ISNS_LCD_PANELN

7

67

NC_ISNS_LCD_PANELP

7

67

=PP3V3_S0_ISNS

8

43 80

LOADISNS:YES

=PP3V3_S0_ISNS

8

43 80

LOADISNS:YES

3

V+

UD210

INA211

5

SC70

IN-

4

GND

2

3

V+

UD220

INA211

5

SC70

IN-

4

GND

2

OUT

OUT

6

1

REFIN+

6

1

REFIN+

1

CD210

0.1UF

20%
10V

2

CERM
402

LOADISNS:YES

ISNS_CPU_SA_IOUT

PLACE_NEAR=U4900.G1:5MM

LOADISNS:YES

1

CD220

0.1UF

20%
10V

2

CERM
402

LOADISNS:YES

ISNS_LCD_PANEL_IOUT

PLACE_NEAR=U4900.B2:5MM

LOADISNS:YES

RD219

4.53K

1 2

1%

1/20W

MF

201

RD229

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_SA_ISENSE

1

CD219

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.G1:5MM

LOADISNS:YES

GND_SMC_AVSSGND_SMC_AVSS

SMC_LCD_PANEL_ISENSE

1

CD229

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.B2:5MM

LOADISNS:YES

GND_SMC_AVSS

OUT

OUT

40

39 40 43 44 80 39 40 43 44 80

40

39 40 43 44 80

D

C

Thunderbolt TBT Current/Voltage Sense (IHSP/VHSP)

Gain: 1000x. EDP: 2.8 A
Rsense: 0.001 (RD240)
V across Rsense: 2.8 mV
SMC AD: 23

=PP1V05_S0_P1V05TBTREG

8

35

B

OUT

=PP1V05_S0_P1V05TBTREG_R

8

64

IN

RD240

0.001

1%
1W
MF

0612

LCD Backlight Voltage Sense (VBLC)

Gain: 0.04434

PPVOUT_S0_LCDBKLT

7

67 71

A

XWD240

1 2

PLACE_NEAR=RD240.1:10 MM

123

ISNS_TBT_N

78

ISNS_TBT_P

78

4

XWD250

SM

1 2

SM

=PP3V3_S0_ISNS

8

43 80

TBTISNS:YES

VOUT_S0_LCDBKLT_XW

LOADISNS:YES

LOADISNS:YES

P1V05TBT_IN

3

V+

UD240

INA212

5

SC70

IN-

4

GND

2

1

RD256

1M

1%
1/16W
MF-LF
402

2

VOUT_S0_LCDBKLT_DIV

1

RD257

46.4K

1%
1/16W
MF-LF
402

2

OUT

REFIN+

PLACE_NEAR=U4900.A8:5MM

LOADISNS:YES

PLACE_NEAR=XWD240.2:10MM

TBTISNS:NO

1

CD240

0.1UF

20%
10V

2

CERM
402

TBTISNS:YES

6

ISNS_TBT_IOUT

1

RD259

4.53K

1 2

1%

1/20W

MF

201

RD248

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=XWD240.2:10MM

TBTISNS:YES

SMC_LCDBKLT_VSENSE

1

CD259

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.A8:5MM

LOADISNS:YES

GND_SMC_AVSS

IVSNS_TBT_IVOUT

RD247

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=U4900.A8:5MM

OUT

40

39 40 43 44 80

RD249

4.53K

1 2

1%

1/20W

MF

201

SMC_TBT_ISENSE

1

CD249

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.A8:5MM

GND_SMC_AVSS

OUT

40

39 40 43 44 80

6 3

CPU SA Voltage Sense (VC2C)

Gain: 1x
SMC ADC: 14

=PPVCCSA_S0_REG

8

58

PART NUMBER

117S0008
117S0008

PLACE_NEAR=R7140.1:5 MM

XWD260

SM

1 2

QTY

3
3

DESCRIPTION

RES,MTL FILM,100K,1/16W,0201,SMD,LF

RES,MTL FILM,100K,1/16W,0201,SMD,LF

PLACE_NEAR=U4900.B1:5MM

CPUVCCSA_IN

RD269

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_SA_VSENSE

1

2

GND_SMC_AVSS

REFERENCE DES

CD209,CD219,CD229

CD239,CD259

PLACE_NEAR=U4900.B1:5MM

CD269

0.22UF

20%

6.3V
X5R
0201

CRITICAL

40

OUT

39 40 43 44 80

BOM OPTION

LOADISNS:NO
LOADISNS:NO

SYNC_MASTER=D1_SENSORS

PAGE TITLE

Power Sensors: Extended

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=07/11/2012

<SCH_NUM>

<E4LABEL>

<BRANCH>

132 OF 132

80 OF 80

SIZE

B

A

D