apple K87 SCRATCHO 051-8561 REV C Datasheet

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

3456

ECNREV

DESCRIPTION OF REVISION

12

CK APPD

DATE

0000897412

C

PRODUCTION RELEASED

2010-04-26

SCHEM MLB_LDO K87

D

SCRATCHO

D

04/26/2010

(.csa)

Page

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

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10

TABLE_TABLEOFCONTENTS_ITEM

C

B

TABLE_TABLEOFCONTENTS_ITEM

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

1

1 NA 2 3 4 5 6 7 8 9

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

BOM Configuration

5

Revision History

6

Revision History

7

FUNC TEST

8

Power Aliases

9

SIGNAL ALIAS

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling

13

eXtended Debug Port(MiniXDP)

14

MCP CPU Interface

15

MCP Memory Interface

16

MCP PCIe Interfaces

17

MCP Graphics

18

MCP SATA, USB & Ethernet

19

MCP HDA, LPC & MISC

20

MCP Power & Ground

23

MCP89 Memory Rail Gating

24

MCP89 GFX Core Rail Gating

25

MCP Standard Decoupling

26

MCP Graphics Support

28

SB Misc

29

DDR3 SO-DIMM Connector A

31

DDR3 SO-DIMM Connector B

32

SO-DIMM Pinswaps

33

FSB/DDR3 Vref Margining

34

X16 WIRELESS CONNECTOR

37

Ethernet PHY (RTL8211CL)

39

ETHERNET CONNECTOR

45

SATA Connectors

46

External USB Connectors

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

K87 SMBus Connections

Contents

Sync

MASTER MASTER (K84_MLB) MASTER MASTER MASTER MASTER (K84_MLB) T27_MLB T27_MLB T27_MLB (K84_MLB) T27_MLB T27_MLB T27_MLB T27_MLB T27_MLB T27_MLB T27_MLB K6_MLB T27_MLB (T27_MLB) T27_MLB (T27_MLB) T27_MLB T27_MLB MASTER T27_MLB MASTER MASTER MASTER MASTER (K84_MLB) T27_MLB (T27_MLB) (T27_MLB) MASTER

Date

NA MASTER MASTER (01/19/2009) MASTER MASTER MASTER MASTER (02/04/2009) 02/16/2010 02/16/2010 02/16/2010 (02/25/2009) 02/16/2010 02/16/2010 02/16/2010 02/16/2010 02/16/2010 02/16/2010 02/16/2010 02/16/2010 12/15/2009 (11/16/2009) 02/16/2010 (10/07/2009) 02/16/2010 02/16/2010 MASTER 02/16/2010 MASTER MASTER MASTER MASTER (10/03/2009) 02/16/2010 (10/27/2009) (12/15/2009) MASTER

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

Page

(.csa)

53

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Voltage Sensing

54

Current Sensing

55

Thermal Sensors

56

Fan Connector

57

WELLSPRING 1

58

WELLSPRING 2

59

SMS

60

DEBUG SENSORS AND ADC

61

SPI ROM

62

AUDIO: CODEC/REGULATOR

63

AUDIO: LINE INPUT FILTER

65

AUDIO: HEADPHONE FILTER

66

AUDI0: SPEAKER AMP

67

AUDIO: JACK

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

72

5V/3.3V SUPPLY

73

1.5V/0.75V DDR3 SUPPLY

74

IMVP6 CPU VCore Regulator

75

MCP VCore Regulator

76

CPU VTT(1.05V) SUPPLY

77

Misc Power Supplies

78

Power Sequencing

79

POWER FETS

90

LVDS CONNECTOR

93

DISPLAYPORT SUPPORT

94

DisplayPort Connector

97

LCD Backlight Driver (MC34845)

98

LCD Backlight Support

100

CPU/FSB Constraints

101

Memory Constraints

102

MCP Constraints 1

103

MCP Constraints 2

104

Ethernet Constraints

106

SMC Constraints

108

K87 SPECIFIC CONSTRAINTS

109

K87 RULE DEFINITIONS

Contents

Sync

T27_MLB T27_MLB MASTER T27_MLB T27_MLB MASTER MASTER MASTER T27_MLB AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO MASTER (K6_MLB) (K6_MLB) (K6_MLB) (K84_MLB) (K6_MLB) (K84_MLB) MASTER (T27_MLB) MASTER (K84_MLB) K6_MLB MASTER MASTER (K84_MLB) T27_MLB T27_MLB T27_MLB T27_MLB MASTER T27_MLB MASTER MASTER

Date

02/16/2010 02/02/2010 MASTER 02/16/2010 02/16/2010 MASTER MASTER MASTER 02/16/2010 02/16/2010 02/16/2010 02/16/2010 02/16/2010 02/16/2010 02/16/2010 MASTER (11/06/2009) (10/27/2009) (11/06/2009) (11/18/2009) (10/27/2009) (02/04/2009) MASTER (10/27/2009) MASTER (10/19/2009) 02/16/2010 MASTER MASTER (10/19/2009) 02/16/2010 02/16/2010 02/16/2010 02/16/2010 MASTER 02/16/2010 MASTER MASTER

C

B

A

Schematic / PCB #’s

PART NUMBER

051-8561 CRITICAL

QTY

1

DESCRIPTION

SCHEM,MLB_LDO,K87

PCBF,MLB_LDO,K87820-2877

8 7 6 5 4 2 1

REFERENCE DES

SCH

PCB

CRITICAL

BOM OPTION

3

DRAWING TITLE

SCHEM,MLB_LDO,SCRATCHO,K87

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

1 OF 109

SHEET

1 OF 76

SIZE

A

D

345678

U1000

INTEL CPU

PG 10

PG 14

K86K87

CULV

FSB

64-Bit

1067/1333 MHz

2.4GHZ 1.2GHZ PENRYN

D

GPIOs

PG 19

FSB INTERFACE

MAIN

MEMORY

PG 15

J1300

MINI XDP CONN

PG 13

2 UDIMMs

DDR3-1067/1333MHZ

J3100

J2900

DIMM

PG 29,30

J6950

HALL EFFECT CONN

U5920

J6950,U7000

U5535,U5515

VOLTAGE AND CURRNET SENSING

J5601

PG 69

SMS

PG 59

DC/BATT

PG 69,70

TEMP SENSORS

PG 55

POWER SENSE

PG 53,54

FAN CONN

PG 56

POWER SUPPLY

2 1

PG 70-79

D

MISC

PG 19

J4501

SATA

CONN

HD

PG 45

J4500

SATA

CONN ODD

LVDS

CONN

PG 45

PG 90

PG 94

PG 34

C

J9000

J9400

DISPLAY PORT

J3401

B

AIR PORT

1.05V/3GHZ.

SATA

PG 18

LVDS OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

RGB OUT

PG 17

PCI-E

UP TO

20 LANES3

PG 16

RGMII

LAN

PG 17

NVIDIA

MAC

PG 17

MCP

U1400

PCI

SPI

PG 18

LPC

PG 19

PWR

CTRL

11

10

USB

PG 18

98764 51 20

(UP TO 12 DEVICES)

3

SMB

PG 19

HDA

PG 19

U6100

SPI

BOOT ROM

PG 61

J3401

BLUETOOTH

PG 34

J1300

MINI XDP CONN

J5800

TRACKPAD

CONN

PG 58

TRACKPAD/

KEYBOARD

PG 13

U4900

SMSLID

J9000U5701

B,0BSB

SMC

PG 49

CAMERA

PG 90PG 57

ADC

Ser

Fan

Prt

J4600, J4610

EXTERNAL USB

CONN

PG 46

J5100

LPC+SPI CONN

PG 51

C

B

U3700

GIGABIT

10/100/1000 E-NET

RTL8251CA

PG 37

J3900

E-NET

CONN

PG 32

LINE IN

FILTER FILTER

A

PG 63

8 7 5 4 2 1

U6201

AUDIO CODEC

PG 62

HEADPHONE

PG 65

J6701,J6702,J6703,J6704

AUDIO CONNS

PG 67

U6610, U6620, U6630

SPEAKER

AMPS

PG 66

SIZE

A

D

SYNC_MASTER=MASTER

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

2 OF 109

SHEET

2 OF 76

36

345678

2 1

D

(9 TO 12.6V)

C

B

A

AC

ADAPTER

IN

J6950

3S2P

MCP89

U1400

PM_SLP_S4_L

PM_SLP_S3_L

PM_SLP_RMGT_L

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

PP18V5_DCIN_CONN

K86/K87 POWER SYSTEM ARCHITECTURE

Q7080

PPDCIN_G3H_OR_PBUS

DCIN(16.5V)

PPVBAT_G3H_CONN

F6905

6A FUSE

SMC_DCIN_ISENSE

01

A

R7020

Q7055

CHGR_EN

(S5)

ENABLES

VIN

PBUS SUPPLY/ BATTERY CHARGER

ISL6259

U7000

PPVBAT_G3H_CHGR_R

CHGR_BGATE

VOUT

PPVBAT_G3H_CHGR_REG

R7050

SMC_BATT_ISENSE

A

01

PPBUS_G3H

Q7085

8A FUSE

F7040

IMVP_VR_ON_R

02

24

CPU VCORE

VIN

ISL9504B

VR_ON

PPBUS_G3H

VOUT

U7100

PGOOD

PBUS_VSENSE

CPUVTTS0_EN (S0)

02

04

VIN

U7750

VIN

EN1

(RT)

EN2

TPS51125

U7201

PGOOD1,2

P5V3V3_PGOOD

VOUT

PP0V9_S5_REG

5V

3.3V

PP5V_S3_REG

VOUT1

(13A MAX CURRENT)

PP3V3_S5_REG

VOUT2

(5.5A MAX

VREG3

AP_PWR_EN

09

14

10

Q7890

09-1

09-3

RC DELAY

09-2

RC DELAY

PM_WLAN_EN_L

P3V3S3_EN

DDRREG_EN

P5VS3_EN_L

15

SMC

U4900

P16

SMC_PM_G2_EN

P60

(S5)

04

U7840

04

P0V9S5_EN

P5VS3_EN_L

P3V3S5_EN_L

EN

ISL8009B

02

VIN

MC34845

ENA

U9700

S5

S3

VOUT

VIN

TPS51116

PPVOUT_SW_LCDBKLT

02

1.5V

VOUT1

0.75V

VOUT2

U7300

MCPCORES0_EN

BKLT_EN

02

13

21

Q7930

PP3V3S0_EN

MCP_CORE

EN

ISL9563A

U7500

VIN

P0V9_ENET_EN

PP1V5R1V35_SW_MCP

(12A MAX CURRENT)

(1A MAX CURRENT)

PPMCPCORE_S0_R

VOUT

(25A MAX CURRENT)

PP1V5_S3_REG

PP0V75_S0_REG

PM_SLP_S3_L

P1V8S0_EN

P1V5S0_EN

CPUVTTS0_EN

DDRVTT_EN

MCPCORES0_EN

Q7890,Q7891

15-3

15-4

15-5

15-6

PM_SLP_S3_L SMC_ADAPTER_EN

PBUSVSENS_EN

(S0)

P5VS0_EN

(S0)

RC

P3V3S0_EN

DELAY

BKLT_EN

04-1

=DDRREG_EN

=DDTVTT_EN

15-1

15-2

8 7 5 4 2 1

02

Q5315

V

PBUS_G3H_VSENSE

SMC_CPU_ISENSE

VR_PWRGOOD_DELAY

CURRENT)

P3V3S3_EN

Q7930

P3V3S0_EN

07

PP0V9_ENET_FET

11

17

22

R7525

ENABLE

3.425V G3HOT LT3470

U6990

VOUT

02

VIN

EN_PSV

VOUT

CPUVTT

(1.05V)

TPS51117

U7600

PGOOD

CPUVTTS0_PGOOD

SMC_CPU_VSENSE

V

PPMCPCORE_S0_REG

PPVCORE_S0_CPU

27

12

Q7910

Q7960

PM_SLP_RMGT_L

TPS62202

PP3V42_G3H_REG

PP1V05_S0

(8A MAX CURRENT)

(44A MAX CURRENT)

06

Q3450

P3V3ENET_EN_L

1.05V

NCP1529

U7710

PP3V3_S0_FET

1.8V

U7760

1.5V

FDC638P

Q7920

PP1V8_S0_REG

PP1V5_S0_FET

03

21

25

Q7948

P5VS0_EN

PP3V3_S3_FET

P3V3_S3_WLAN

PP1V05_S0_REG

17

18

19

1.05V

TPS74701

U7740

PP1V05_S0_MCP_PLL_OR

SMC PWRGD

RN5VD30A-F

U5010

PP5V_S0_FET

10

11

12

PP3V3_S0 PP1V5_S0 PP1V05_S0

36

04

16

P5V3V3_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

MCPPLLDO_PGOOD

S0PGOOD_RST_L

20

RST*

V1

U7870

V2

ISL88042

V3

MCP_PS_PWRGD

U2850

4.5V AUDIO MAX8840

VIN

U6200

EN

23

ALL_SYS_PWRGD

RSMRST_PWRGD

09

SMC_ONOFF_L

08

MCP89

PWRBTN*

PLTRST*

RSMRST*

PWRGD

CPUPWRGD(GPIO49)

CPU_RESET#

U1400

28

CPU

PWRGOOD

U1000

PP4V5_AUDIO_ANALOG

VOUT

SMC

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

PLT_RST*

P17(BTN_OUT)

SLP_S5_L SLP_S4_L SLP_S3_L

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)

U4900

SYNC_MASTER=MASTER

PAGE TITLE

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

RESET*

RST*

08-1

30

LPC_RESET_L

CPU_PWRGD

29

FSB_CPURST_L

31

18

PM_RSMRST_L

IMVP_VR_ON_R

PM_PWRBTN_L SMC_RESET_L

18-2

24

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

3 OF 109

SHEET

3 OF 76

SIZE

D

C

B

A

D

BOM Variants

BOM NUMBER

639-1115

639-1116

085-1799

Development BOM

PART NUMBER

D

085-1632 CRITICAL

BOM Groups (always-present)

BOM GROUP

K86_K87_COMMON

K86_K87_COMMON1

K87_SPECIFIC

K86_SPECIFIC

BOM OPTIONS

K86_K87_DEVELOPMENT_PVT

BOM OPTION

DEVELOPMENT_BOM

QTY

BOM NAME

PCBA,MLB_LDO,FOXCONN,K87

PCBA,MLB_LDO,MOLEX,K87

K87 MLB_LDO DEVELOPMENT BOM

DESCRIPTION

1

K87 MLB_LDO DEVELOPMENT BOM

REFERENCE DES

DEVEL

K86_K87_COMMON,K87_SPECIFIC,FOX_DDR_CONN,EEEE:DD16

K86_K87_COMMON,K87_SPECIFIC,MOLEX_DDR_CONN,EEEE:DD17

CRITICAL

BOM OPTIONS

K86_K87_COMMON1,PROJECT_PHASE:PROD,COMMON,ALTERNATE,BOOTROM:PROG,WELLSPRING:PROG,MCP_T_DIODE_SENSOR

DP_ESD,MIKEY,MCPPLL_R:REG,ENET1V05:INT,LED:K86_K87,S0PGOOD_BJT,ENET_ESD,VFRQ:SLPS3,SMC_DEBUG:YES,SPI:25MHZ,XDP,OLD_AUDIO_SWITCH

CPU:2.4GHZ,IMVP6:2PHASE,SMC:PROG_K87,MCP89M:A02

CPU:1.2GHZ,IMVP6:1PHASE,SMC:PROG_K86,MCP83M

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEE #’s

PART NUMBER

826-4393

QTY

1

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM

Part Substitutions (differences with K6/K69)

PART NUMBER

114S0125

QTY

1

DESCRIPTION

RES,MTL FILM,1/16W,113 OHM,1,0402,SMD,LF

REFERENCE DES

[EEEE_DD16]

[EEEE_DD17]

[EEEE_DD18]

[EEEE_DD19]

REFERENCE DES

R5714

345678

CRITICAL

CRITICAL826-4393

CRITICAL

2 1

BOM OPTION

EEEE:DD16

EEEE:DD17

EEEE:DD18

EEEE:DD19

D

BOM OPTION

LED:K86_K87

BOM Groups (project phase-dependent)

BOM GROUP

PROJECT_PHASE:DEV

K86_K87_DEVELOPMENT_ONLY

K86_K87_DEVELOPMENT_PVT

K86_K87_DEBUG:DEV

K86_K87_DEBUG:PROD

DEVELOPMENT_BOM

K86_K87_DEBUG:PRODPROJECT_PHASE:PROD

DEBUG_ADC,LPCPLUS_CON,S0PGOOD_ISL,EFI_DEBUG,MCPPLL_LDO,EXT1V05,XDP_CON,LPCPLUS

LPCPLUS_CON,XDP_CON,VREFMRGN:YES,LPCPLUS

VREFMRGN:YES,BMON:ENG,BKLT:ENG,SENS_R:ENG

VREFMRGN:NO,BMON:PROD,BKLT:PROD,SENS_R:PROD,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES

Module Parts

PART NUMBER

C

B

337S3680

337S3792

337S3797 CRITICAL MCP89M:A01

337S3866

337S3876

516S0706

516-0201

516S0790

870-1940

870-1939

870-1938

353S2718 IS NEW INTERSIL PART FOR FIXING B4 DONGLE ISSUE 514-0704 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0692 PART FOR RJ45 CONNECTOR 514-0705 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0689 PART FOR USB CONNECTORS 514-0706 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0691 PART FOR MINI DP CONNECTOR 514-0718 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0694 PART FOR AUDIO CONNECTOR

QTY

1

4

3

5

3

Programmable Parts

338S0563

335S0610

337S2983

341S2677

1

DESCRIPTION

PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA

CDC,SLGYW,PRQ,1.2,10W,800,R0,1M,BGA

IC,MCP89M-A01,31X31MM,BGA1168

IC,MCP89M-A02,31X31MM,BGA1168

IC,MCP83M-A02,31X31MM,BGA1168

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA

CONN,204P,SODIMM,P=0.6MM

CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA

CONN,204P,SODIMM,P=0.6MM

SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97

POGO PIN,MED,NOISE-IMPROVED,SILVER,K87

POGO PIN,TALL,NOISE-IMPROVED,SILVER,K87

POGO PIN,THIN,NOISE-IMPROVED,SILVER,K87

LOCKED BOOTROM APN IS 341S2488 (QL: old info?)

IC,SMC,HS8/2117,9X9MM,TLP,HF

SUBASSY, IC, SMC, K87

SUBASSY, IC, SMC, K86

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

SUBASSY, IC, BOOT ROM, K86/K87

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

IC,WELLSPRING CONTROLLER,K87

REFERENCE DES

SCREW1,SCREW2,SCREW3,SCREW4

ZS0900,ZS0901,ZS0902,ZS0903

ZS0908,ZS0909,ZS0911

ZS0904,ZS0905,ZS0906,ZS0907,ZS0910

ZS0912,ZS0913,ZS0914,ZS0915,ZS0919

ZS0917,ZS0918,ZS0916

Alternate Parts

PART NUMBER

152S0693

128S0093

A

152S0874

152S0847

104S0018 104S0023

353S2811

353S2988 353S2987

ALTERNATE FOR PART NUMBER

152S0778

152S0685152S0796

157S0055157S0058

138S0602138S0603

128S0218

152S0516

152S0586

353S1832

376S0634376S0908

376S0634376S0907

376S0868376S0912

BOM OPTION

REF DES

ALL

COMMENTS:

DALE/VISHAY, MAGLAYERS AS ALTERNATE

CYNTEC AS ALTERNATE

DELTA AS ALTERNATE

MURATA AS ALTERNATE

KEMET AS ALTERNATE

MAGLAYERS AS ALTERNATE

DALE/VISHAY AS ALTERNATE

NEW IMPROVED INTERSIL PART AS ALTERNATE

MIC5365 AS ALTERNATE

TOSHIBA AS ALTERNATE

FAIRCHILD AS ALTERNATE

ONSEMI(NEW SPEC) AS ALTERNATE

TABLE_ALT_HEAD

TABLE_ALT_ITEM

8 7 5 4 2 1

U1000

U1400

J3100

J2900

J3100

J2900

U4900

U6100

U5701

BOM OPTIONS

CRITICAL

CRITICAL CPU:1.2GHZ

CRITICAL

CRITICAL516-0213

CRITICAL452-1708

CRITICAL870-1940

CRITICAL

CRITICAL870-1939

CRITICAL

CRITICAL341T0252

CRITICAL341T0250

CRITICAL

CRITICAL341T0251

CRITICAL

BOM OPTION

CPU:2.4GHZ

MCP89M:A02

MCP83M

FOX_DDR_CONN

MOLEX_DDR_CONN

SMC:BLANK

SMC:PROG_K87

SMC:PROG_K86

BOOTROM:BLANK

BOOTROM:PROG

WELLSPRING:BLANK

WELLSPRING:PROG

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOTTOM

36

K86/K87 BOARD STACK-UP

TOP

2 3 4 5 6 7 8

9 10 11

SIGNAL GROUND

SIGNAL(High Speed)

SIGNAL(High Speed) GROUND POWER POWER

GROUND

SIGNAL(High Speed)

SIGNAL(High Speed) GROUND SIGNAL

SYNC_MASTER=(K84_MLB)

PAGE TITLE

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(01/19/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

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SHEET

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SIZE

C

B

A

D

Revision History

10/1/2009:

2009-12-03: Proto 0 release 1.0.0 2009-12-04: 1.1.0

2009-12-07: 1.2.0

D

2009-12-08: 1.3.0

2009-12-08: 1.4.0

2009-12-09: 1.5.0

2009-12-10: 1.6.0

2009-12-11: 1.7.0

2009-12-16: 1.8.0

C

2009-12-17: 1.9.0

2009-12-22: 1.10.0

2010-01-06: 1.11.0

B

2010-01-07: 1.12.0

2010-01-08: 2.0.0

2010-01-13: 2.1.0

2010-01-13: 2.2.0

2010-01-15: 2.3.0

A

2010-01-18: 2.4.0

INITIAL RELEASE 0.0.1-

- ALL PAGES SYNC’ED FROM K84

- REPLACED K84 MCP AND CPU PAGES WITH K6 PAGES

- UPDATED SCHEMATIC AND PCB PART NUMBER INFO

csa 2: Updated CPU block text to include CPU description for both K86 and K87 csa 3: Updated text note to include "K86" in title csa 4: Added BOM entry under Module Parts table to include CULV processor (337S3779) to minimize delta on this page between K86 and K87 per Diana

csa 74: Component value changes per Leo (Intersil):

R7417 from 5.36k => 6.34k, 1% (114S0296) C7434 from 0.12uF => 0.022uF, 10% (132S0102) Implemented different stuffing options for 1-phase vs 2-phase: Added IMVP6:2PHASE to the following components: R7417, C7428, R7409, R7411, C7406, R7414, C7414, C7413 Added BOM table to insert the following APNs for IMVP6:1PHASE: R7417 = 7.68k 1% (114S0304) C7428 = 0.22uF 10% (132S0102) R7409 = 1.58k 1% (114S0236) R7411 = 255 1% (114S0160) C7406 = 470pF 10% (132S4720) R7414 = 97.6k 1% (114S0410) C7414 = 1000pF 10% (132S0045) C7413 = 100pF 5% (131S1027) Updated table to add new values for 1phase (PWM freq., Max current, Load line)

STILL NEED TO UPDATE VALUE OF C7428!

csa 45: Added passive deemphasis to SATA HDD D2R lines:

Added R4585, R4586 (51.1 ohm, 1%, 114S0093) and OMITted Added C4585, C4586 (10pF, 5%, 131S0029) and NOSTUFFed Added BOM table to stuff 0-ohms until we get go-ahead for filter

csa 8: Deleted net properties for the following nets:

=PP3V3_S0_CPUVTTISNS’ =PP5V_S0_HDD’ =PP5V_S0_MCPREG’ =PP1V05_S0_MCP_AVDD_UF’ =PPSPD_S0_MEM_B’ =PP3V3_S0_PWRCTL’ =PP3V3_S0_DPCONN’ csa 34: Deleted net properties for =PP3V3_S3_WLAN csa 74: Changed C7434 from NOSTUFF to IMVP6:2PHASE per Intersil Added IMVP6:2PHASE to R7413 per Intersil Changed C7428 from 0.47uF => 0.33uF (132S0101) per Intersil Changed component color to Green Cosmetic cleanup csa 90: Deleted net properties for =PP5V_S3_CAMERA csa 98: Deleted net properties for =PPBUS_S0_LCDBKLT csa 108: Added NET_PHYSICAL property to SATA_HDD_D2R_FILT_P and _N

multiple: Added parentheses for SYNC_DATE property on all pages that have broken sync.

csa 4: Deleted entry in Module Parts table for R6612, R6617, R6630, R6633 since they were removed when we switched from piezo to dynamic speakers csa 69: Changed J6955 symbol to K87 Hall effect assembly (339S0114)

csa 69: Added OMIT to J6955, BOM table to stuff K84 Hall effect connector

csa 45: Added PLACEMENT_NOTE for passive deemphasis circuit. csa 74: Changed 1PHASE BOM table to correctly call out 132S0080 (0.22uF) instead of 0.022uF

*** Resynced all synced pages and picked up the following (change notes from T27): csa 18: T27: Swapped USB_EXTB and USB_EXTD for NVRN-612340 (pg. 18). <radar:7416825> Ensure USB_EXTB is on ports 8-11 (NVRN-612340) T27: Changed USB_RBIAS from 931-ohms to 887-ohms per DG v1.3 (pg. 18). <radar:7459260 > Design Guide v1.3 updates csa 20; T27: Added CKPLUS_WAIVE properties to dismiss false errors (pg. 20). <radar:7368529> TASK: Waive false CheckPlus errors *** Started syncing the following pages: csa 29,31: Began syncing from T27 per <radar:7424246 > BOM: K87 needs omit on J3100 and J2900 from T27 T27: Added BOMOPTIONs and APNs for Foxconn and Molex SO-DIMM connectors (pp. 29, 31). csa 54: Began syncing from T27 per <radar:7432091 > BATT_ISENSE filter change to address lower max sink current on ISL6259 BMON pin (K17 auto-shutdown issue) C5490 changed from CAP_402-0.022UF,10%,16V,CERM-X5R to CAP_402-0.022UF,20%,16V,CERM T27: Added CKPLUS_WAIVE properties to dismiss false errors (pg. 54). T27: Added gain note for U5402 and SMC_BATT_ISENSE (pg. 54). T27: Changed RC balance on BATT_ISENSE, same time constant (pg. 54). csa 57: Began syncing from T27 per <radar:7304029 > T27 schematic bom option for R5714 & R5030 to keep K87 in sync R5714 has BOMOPTION LED:K6_K69, and we need to substitute a different part on csa 4 *** Made the following changes to follow T27 on the following unsynced pages: csa 25: T27: Removed R2575 & R2580 per DG v1.3 (pg. 25). per <radar:7459260 > Design Guide v1.3 updates *** Other changes csa 4: Added BOM table to substitute in parts that have BOMOPTION xxx:K6_K69 (to allow sync with T27) Added R5714 (114S0125) to table with BOMOPTION LED:K86_K87

csa 4: Added BOM table entry for MCP89-A02 per <radar:7416858 > Task: Get part numbers for A02 rev. Changed K87_MCP BOM group to call out MCP89-A02 csa 34: Changed U3440 from AP002 part to AP016 (343S0511) per <radar:7459498> BOM: APN updates for FPF1009 and SAK parts Changed R3454 to 100k, 1% (114S0411) to match T27 and K69 Updated DLY text note for U3440 to match T27 Changed R3440 color to green, deleted WF text note about needing PU csa 72: Changed L7220 from 152S0693 to 152S0778 per <rdar://problem/7347216> K69 L7260 combo footprint Alternates table on csa 4 already has 152S0778 as alternate to 152S0693

csa 4: Per <rdar://problem/7473229> K86: Move to MCP83 Added BOM table entry for MCP83M (337S3876) This is for K86 ONLY. Adding entry to minimize delta on csa 4 between K87 and K86 BOMOPTION is "MCP83M" Per <rdar://problem/7495072> K87: Call out LED:K86_K87 BOMOPTION in the K87_MISC BOM group Added LED:K86_K87 BOMOPTION to the K87_MISC BOM group Per <rdar://problem/7495116> K87: remove ON Semi alternate for Q2300 (376S0624) Removed table entry that says 376S0868 is an alternate for 376S0624 Per <rdar://problem/7495021> K86/K87: Replace "S" APNs with "T" APNs for programmed SMC and BR Changed BOOTROM:PROG to call out 341T0251 (SUBASSY, IC, BOOT ROM, K86/K87) Created SMC:PROG_K87 pointing to 341T0252 (SUBASSY, IC, SMC, K87) Created SMC:PROG_K86 pointing to 341T0250 (SUBASSY, IC, SMC, K86) Changed K87_PROGPARTS BOM group to point to SMC:PROG_K87 csa 69: Per <rdar://problem/7494087> K87: remove OMIT from J6955 and delete BOM table Deleted BOM table for Hall effect assembly Changed text note to say "HALL EFFECT ASSEMBLY" Deleted OMIT BOMOPTION from J6955 Added text note with part numbers for components of the assembly "Assembly APN: 339S0114

- BOM: 639-0680

- PCBF: 820-2801

- MCO: 056-3515

- Conn APN:518S0788" csa 74: Cosmetic change: moved R7413, C7406 BOMOPTION label so they don’t look like wire name csa 78: Per <rdar://problem/7495000> K87: Add NOSTUFF to R7872 to disconnect U7870 from ALL_SYS_PWRGD Changed BOMOPTION for R7872 from S0PGOOD_ISL to NOSTUFF

csa 7: Per <rdar://problem/7517432> K86/K87 functional net property needed on signals in schematics Added the following functional test points under the J5100 LPC+SPI CONN FUNC_TEST group LPCPLUS_GPIO LPC_SERIRQ SMC_TMS

csa 23: *** BROKE SYNC WITH T27 Per <rdar://problem/7519025> K86/K87: update all instances of 376S0786 schematic symbols Updated Q2355 and Q2356 with new schematic symbols Need to resync with T27 once the change has been made there csa 70: Per <rdar://problem/7519048> K86/K87: Change U7000 to 353S2929 Changed U7000 from 353S2392 to 353S2929 Updated APN text note

csa 45: Per <rdar://problem/7524364> K86/K87: change SATA HDD D2R passive EQ values Removed NOSTUFF from C4585, C4586 Removed OMIT from R4585, R4586 Deleted BOM table that stuffsdel the bypass option Changed R4585, R4586 to 114S0065 (27.4 ohm, 1%) Changed C4585, C4586 to 131S4713 (47pF, 5%)

csa 4: Per <rdar://problem/7540383> K86: Update CPU part number to 337S3792 Changed U1000 CPU:1.2GHZ BOMOPTION from 337S3779 to 337S3792

csa 4: Cosmetic: changed text sizes and alignment Per <rdar://problem/7540522> K86/K87: Production Debug Components Changed 085-1093 to call out K87_DEVEL_PVT instead of K87_DEVEL_ENG Changed K87_COMMON to call out K87_DEBUG_PVT instead of K87_DEBUG_ENG Diff from the two changes above: Toggled: VREFMRGN:YES ==> VREFMRGN:NO BMON:ENG ==> BMON:PROD BKLT:ENG ==> BKLT:PROD SENS_R:ENG ==> SENS_R:PROD Removed: DEBUG_ADC, S0PGOOD_ISL, EFI_DEBUG, MCPPLL_LDO, EXT1V05, MCP_T_DIODE_SENSOR, XDP_CON Unchanged: LPCPLUS, DEVEL_BOM, SMC_DEBUG:YES, XDP Added LPCPLUS_CON to K87_DEVEL_ENG (does not change BOM for DVT) Changed all instances of K87_DEBUG_xxxx to K87_DEBUG:xxxx Changed all instances of K87_DEVEL_xxxx to K87_DEVEL:xxxx csa 51: (Per <rdar://problem/7540522> K86/K87: Production Debug Components) Changed J5100 BOMOPTION from LPCPLUS to LPCPLUS_CON to unstuff connector at DVT

csa 74: Per <rdar://7525313 > K86 CPU loadline, OCP update Keeping K86 and K87 pgs identical for CSA 74, modifying BOM table for IMVP 1 phase on K87’s schematic to reflect changes for K86. IMVP6:1PHASE BOM Table: R7417 changed to 7.87K (APN 114S0305) R7416 added to BOM Table, 16.9K, (APN 114S0336) Added IMVP6:2PHASE BOM option to R7416 for K87’s 13.7K csa 74, csa 79: Per <rdar://7542674 > K86/K87 Text note change Cleaned up text notes for 1phase, 2phase, and edp #s per radar request.

csa 4: Per <rdar://problem/7549122> K86/K87: Switch to new BOM group structure Reverted back to ENG BOM, no longer PROD BOM (i.e. reverted much of 2.2.0 changes) Changed BOM group structure to match that in the radar (see PDF attached to radar) Net change was to move LPCPLUS to the 639 (from the 085) Switching from Engineering to Production BOM should only require changing PROJECT_PHASE:DEV to PROJECT_PHASE:PROD Per <rdar://problem/7544629> K86/K87: Update MCP83 description on csa 4 Changed description for 337S3876 to "IC,MCP83M-A02,31X31MM,BGA1168" csa 23: Per <rdar://problem/7544657> K86/K87: Fix schematic symbol for Q2355, Q2356 *** Started syncing with K6 Syncing with K6 to pick up new symbols for Q2355 and Q2356 Should switch syncing back to T27 once it is updated there csa 37: Per <rdar://problem/7548726> K86/K87 Ethernet series R’s need to be 0 ohmed Changed R3790-R3795 to 116S0004 (0-ohm, 0402) from 22-ohm

345678

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

8 7 5 4 2 1

2010-01-19: 2.5.0

csa 37: Per <rdar://problem/7554342> K86/K87: Change L3720 to 152S1182 Changed L3720 to 152S1182 (IND,PWR,SHD,4.7UH,20%,0.91A,31X31X12MM) for lower ESR

2010-01-22: 2.6.0

csa 4: Per <rdar://problem/7571786> K86/K87: Add E3T EEE code for K86 to schematic Added row to EEE table for E3T Changed BOMOPTIONs to be mutually exclusive (changed "_" to ":")

2010-01-28: 2.7.0

*** Resynced with T27 and K6 (no differences) *** Resynced Audio pages with the following changes:

-pg. 62, changed R6211 to 22 Ohms

-pg. 66, added C6602

-pg. 67, no stuffed R6712 and R6713 csa 45: Per <rdar://problem/7561001> K87:EMC: Radiated Emissions: Right Audio emissions fail Added L4530, L4531 (APN 155S0137) to SIL connector pins csa 97: Per <rdar://problem/7589365> K86/k87: Compensation settings change to provide more phase margin, reduce ripple Changed R9726 from 22k to 10k (114S0315) and removed NOSTUFF Changed C9705 from 8.2nF to 33nF (132S0131) Changed C9706 from 120pF to 220pF (131S2225)

2010-02-02: 2.8.0

*** Resynced with T27 and K6 (no differences) *** Resynced Audio pages with the following changes:

-pg. 67, added BOM options for U6700, R6712, and R6713 to support MAX14560 and MAX14504 csa 97: Changed R9710 from 7.32K 0402 1% to 7.68K (APN 114S0304) to support old K84 panel csa 4: Added OLD_AUDIO_SWITCH BOM OPTION to K86_K87_COMMON1

2010-02-15: 2.9.0 2010-02-15: 2.10.0

csa 54: Broke sync with T27. Per <rdar://problem/7605797> K69/K86/K87 sensor IN1C unreliable U5400 changed from OPA348 to OPA330. C5434 changed to NOSTUFF

2010-02-16: 2.11.0

Resync with T27 and K6. Clean up and rerelease schematic.

2010-02-18: 2.12.0

Per <rdar://7644836> K87 power component update

CSA 74: R7417 changed to 5.90K, C7428 changed to 0.47uF, C7434 changed to 0.033uF CSA 75: R7572 changed to 147K CSA 70: R7015 changed to 56.2K, C7015 changed to 1000pF, C7042 changed to 0.068uF

Per <rdar://7634730> K86/K87: add an RC on the LVDS_IG_BKL_PWM

CSA 97: R9725 changed to 200ohm, C9799 of 47pF added. R9726.1 connection moved to LVDS_IG_BKLPWM

2010-02-18: 2.16.0

Per <rdar://7676934> K86/K87: Hall eff documentation change. Substitute 607-6831 for doc purposes

CSA 69: J6955 BOMOPTION change to OMIT. Added BOM table with 607-6831 for J6955

Per <rdar://7488543> K86/K86 Task: Measure each Power supply in MLB

CSA 74: For K86 only: C7434 = 0.1uF added, R7417 changed to 8.25Kohm CSA 12: For K86 only: C1272 = 330uF added.

Per <rdar://7685202> K86/K87 schematic: change U9700 to 353S2965 for Freescale backlight issue

CSA 97: U9700 changed to APN 353S2965

2010-02-18: 2.17.0

Per <rdar://7686179> K86/K87 schematic: Change audio jack part number for new connector cap

CSA 67: J6700 changed from APN 514-0718 to 514-0750

2010-02-25: 2.18.0

Per <rdar://7685811> K86/K87 schematic: add additional 639 for differentiation between Foxconn and Molex DIMM connectors

CSA 4: MOLEX_DDR_CONN added to Module Parts, removed from Alternate table. Added second 639 and EEEE # to BOM table

2010-02-25: 2.19.0, 2.20.0

Per <rdar://7678515> K87:EMC:ESD: System hangs on air/contact discharge to MPM connector

CSA 69: C6970, C6971, C6972 of 1000pF (APN 131S0222) added

2010-02-26: 2.21.0

Per <rdar://7488543> K87/K86 Task Measure each power supply in mlb.

CSA 12: C1200, C1204, C1207, C1209, C1211, C1219, C1202, C1216 NOSTUFFED CSA 12: Added pads for 0603 caps (APN 138S0635). Compoonents C1230, C1231, C1232, C1233, C1234, C1235, C1236, C1237. CSA 74: Changed C7434 from 0.033uF to 0.047uF (APN 132S0189) per Liang

2010-03-04: B.0.0

Per <rdar://7683852> K87 Proto1: 5 of 6 systems failing graphics noise (Underwater) acoustic spec by up to 3.1dB

CSA 12: C1233, C1230, C1237, C1234 changed from NOSTUFF to STUFFED.

** MLB_LDO branch 2010-03-09: 0.8.0

Summary of changes for MLB_LDO: CSA 25: U2590 added, APN 353S2971. R2592 of 10K and C2592 of 1UF, C2593 of 1UF added. Nets MCP_PLL_LDO_EN and PP3V3_S0_LDO_R added.

2010-03-22: A.1.0

CSA 25: Copied from K6

Added C2599, R2597, R2596, U2593, Q2592, R2599, C2594, U2594, R2598, C2598 with BOMOPTION HTOL_SENSE:YES Added R2594 and R2591 with LDO:ADJ BOMOPTION Changed BOMOPTION names from LDO:YES and LDO:NO to MCPHVDD:P2V5 and MCPHVDD:P3V3 Added BOM TABLE with LDO:FIXED, LDO:ADJ, and HTOL_SENSE:NO stuffing options

CSA 50: Removed SMC alias to TP for SMC_NB_MISC_ISENSE to enable sense circuitry connection to SMC

Removed SMC_P10 alias to TP_SMC_P10

CSA 8: Added =PP3V42_G3H_OPA330 alias to power U2594

Added =PP3V3_S0_OPA330 alias to power U2593

CSA 4: Added MCPHVDD:P2V5, LDO:FIXED, HTOL_SENSE:YES to BOM Group K86_K87_DEBUG:PROD

2010-03-22: A.2.0

Per <rdar://7783507> K87: Add cap to DDC line to avoid DDC line glitch issue

CSA 93: Added C9303 3300pF cap on DP_CA_DET.

CSA 25: Changed U2594 power to 3V3_S0 from 3V42_G3H.

2010-03-22: A.3.0

CSA 77: Deleted U7740 1.05V LDO circuit to free space for U2592 and current mirror circuit.

2010-03-22: A.4.0

Reverted the changes and synced back to A.0.0 Per <rdar://7783507> K87: Add cap to DDC line to avoid DDC line glitch issue

CSA 93: Added C9303 3300pF cap on DP_CA_DET.

2010-03-22: A.5.0

CSA 25: Added R2591,R2594 for LDO:ADJ option. Changed U2592 to LDO:FIXED option. CSA 4: Added Alternate part for U2592 LDO. 353S2987(TI), 353S2988(Micrel) to 353S2986(Intersil).

2010-03-30: A.7.0

2010-03-31: A.8.0

2010-04-1: A.9.0

2010-04-1: A.10.0

2010-04-14: B.0.0

2010-04-14: C.0.0

LDO:FIXED, MCPHVDD:P2V5 added in bom table.

Reverted the changes and synced back to A.2.0. CSA 4: Added Alternate part for U2592 LDO. 353S2987(TI), 353S2988(Micrel) to 353S2986(Intersil).

LDO:FIXED, MCPHVDD:P2V5 added in bom table.

CSA 25,49,50: Changed Q2592 gate control pin to SMC_P24 from SMC_P10.

CSA 25: Added R2600 0ohm resistor to help layout change.

CSA 25: Changed R2600 refdes to R2550 to match with page#.

rdar://7822714 CSA 69: R6905 kept same 1ohm. C6900 changed to 2.2uF. 138S0592. CSA 4: Devel BOM# changed to 085-1799. And BOM OPTIONS to K86_K87_DEVELOPMENT_PVT.

Removed Intersil LDO(353S2986).

CSA 4: Added Toshiba(376S0908), Fairchild(376S0907) as an alternate to 376S0634.

Added ONsemi new spec part(376S0912) as an alternate to Q2300(376S0868).

36

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Revision History

Apple Inc.

R

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=MASTER

051-8561

C.0.0

5 OF 109

5 OF 76

SIZE

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Revision History

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

345678

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PAGE TITLE

Revision History

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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FAN CONNECTORS FUNC_TEST

I12

I15

I16

TRUE TRUE TRUE

PP5V_S0 FAN_RT_PWM FAN_RT_TACH

(NEED TO ADD 1 GND TP)

MIC FUNC_TEST

D

I238 I237

I239

TRUE TRUE TRUE

BI_MIC_N BI_MIC_P BI_MIC_SHIELD

SPEAKER FUNC_TEST

I227

I226

I228

I230

I229

I231

TRUE TRUE TRUE TRUE TRUE TRUE

SPKRAMP_L_N_OUT

SPKRAMP_L_P_OUT

SPKRAMP_R_N_OUT SPKRAMP_R_P_OUT SPKRAMP_SUB_N_OUT SPKRAMP_SUB_P_OUT

LVDS FUNC_TEST

I258

I417

I260

I245

I262

I261

I256

I257

I255

I252

I253

C

I254

I250

I251

I313

I246

I247

I248

I249

I395

TRUE TRUE

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

I297

I294

TRUE TRUE

(NEED TO ADD 5 GND TP)

PP3V3_S0_LCD_DDC_F

PP3V3_SW_LCD_PANEL_F

PPVOUT_S0_LCDBKLT LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<2> LVDS_IG_A_CLK_F_N LVDS_IG_A_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6 PP5V_S3_CAMERA_F

USB_CAMERA_CONN_P USB_CAMERA_CONN_N

SATA ODD CONN FUNC_TEST

I264

I268

I269

I267

I265

I266

TRUE TRUE TRUE TRUE TRUE TRUE

PP5V_SW_ODD SMC_ODD_DETECT

SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N

(NEED TO ADD 4 GND TP)

SATA HDD/SIL FUNC_TEST

B

I319

I314

I315

I318

I317

I307

TRUE TRUE TRUE TRUE TRUE TRUE

PP5V_S0_HDD_FLT SATA_HDD_R2D_P

SATA_HDD_R2D_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SYS_LED_ANODE_R

(NEED TO ADD 4 GND TP)

BATT POWER CONN FUNC_TEST

I322

I321

I320

I305

TRUE TRUE TRUE TRUE

PPVBAT_G3H_CONN SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SYS_DETECT_L

(NEED TO ADD 3 GND TP)

HALL EFFECT CONNECTOR FUNC_TEST

I326

I308

TRUE TRUE

PP3V42_G3H SMC_LID_R

(NEED TO ADD 3 GND TP)

A

8 7 5 4 2 1

62

8 7

42

75 53 52

53 52

52 51

64

(NEED 2 TP)

7 64

67 64 46

7

64

9

64

9

71 64

9

71 64

9

71 64

9

71 64

9

71 64

9

71 64

9

75 64

67 64

64

7

75 64

7

46 33

35 33

71 33

(NEED 4 TP)

33

7

71 33

33

(NEED 3 TP)

55 54

74 38

54

(NEED 2 TP)

8 7

54

(NEED 2 TP)

(NEED 4 TP)

I303

I301

I302

I300

I299

I298

I293

I288

I292

I295

I290

I271

I289

I418

I374

I372

I370

I371

I369

I368

I361

I366

I365

I363

I364

I362

I360

I359

I357

I358

I377

I378

I354

I355

I344

I345

I346

I347

I349

I348

I350

I352

I351

I353

I327

I328

I329

I343

I342

I341

I339

I340

I338

I336

I337

I333

I335

I334

I332

I330

I331

I312

I304

X16 WIRELESS CONN FUNC_TEST

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

PP3V3_S3_BT_F CONN_PCIE_MINI_D2R_P CONN_PCIE_MINI_D2R_N CONN_PCIE_MINI_R2D_P CONN_PCIE_MINI_R2D_N PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N PP3V3_WLAN PCIE_WAKE_L CONN_USB2_BT_P CONN_USB2_BT_N AP_CLKREQ_Q_L AP_RESET_CONN_L

(NEED TO ADD 4 GND TP)

IPD_FLEX_CONN FUNC_TEST

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

PP3V3_S3 PP18V5_S3 Z2_CS_L Z2_DEBUG3 Z2_MOSI Z2_MISO Z2_SCLK Z2_BOOST_EN Z2_HOST_INTN Z2_CLKIN Z2_KEY_ACT_L Z2_RESET PSOC_MISO PSOC_MOSI PSOC_SCLK SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL PSOC_F_CS_L PICKB_L

(NEED TO ADD 2 GND TP)

KEYBOARD CONN FUNC_TEST

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

PP3V3_S3 PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD

(NEED TO ADD 1 GND TP)

DC POWER CONN FUNC_TEST TRUE

TRUE

PP18V5_DCIN_FUSE ADAPTER_SENSE

(NEED TO ADD 2 GND TP)

Functional Test Points

(NEED 4 TP)

(NEED 2 TP)

30

75 30

9

75 30

9

75 30

9

75 30

30

7

30 16

75 30

30

8 7

44

7

44 43

44

44 43

74 38

44 43

8 7

43

54

I287

I285

I280

I281

I282

I376

I396

I283

I279

I278

I270

I273

I274

I275

I276

I410

I393

I392

I391

I390

I389

I388

I386

I385

I383

I382

I381

I380

I397

I409

I412 I411

I413

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

POWER NETS FUNC_TEST

PPVCORE_S0_CPU PPVCORE_S0_MCP PP1V05_S0

PP1V5_S0 PP1V8_S0 PP5V_S0 PP5V_S0 PP3V3_S0

PP1V5R1V35_S3 PP3V3_S3

PP5V_S3 PP3V3_S5 PP3V42_G3H

PPBUS_G3H PP0V9_ENET PP3V3_ENET PP3V3_G3_RTC

PP3V3_WLAN PP5V_SW_ODD

PP5V_S0_HDD_FLT PP3V3_S5_AVREF_SMC

PP18V5_S3 PP3V3_SW_LCD_PANEL_F

PPVOUT_S0_LCDBKLT

PP4V5_AUDIO_ANALOG

SMC_PM_G2_EN

PM_SLP_S4_L

PM_SLP_S3_L

PP5V_S3_CAMERA_F

PP0V9_S5

PPDDRVTT_S0

PP1V05_S0_MCP_PLL_UF

PPVTT_S3_DDR_BUF

(NEED TO ADD 6 GND TP)

FSB SIGNALS WITH NOTEST

I398 I399

I400

I401

I402

I404 I403

I405

I406 I407

I408

NO_TEST=TRUE

NO_TEST=TRUE NO_TEST=TRUE

NO_TEST=TRUE

39

8

39

8

62

8

75 62

8

62

8 7

62

8 7

75 62

8

75

8

8 7

8

75 62

8

8 7

39

8

30

7

46 33

7

33

7

36 35

44

7

64

7

48

62 35

64

7

8

FSB_A_L<35..3> FSB_ADS_L FSB_ADSTB_L<1..0>

FSB_D_L<63..0>

FSB_DINV_L<3..0>

FSB_DSTB_L_N<3..0> FSB_DSTB_L_P<3..0> FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L<4..0>

36

J5100 LPC+SPI CONN FUNC_TEST

I421

I442

I446 I445

I444

I443 I447

I448

I449

23 20 19

67 64 46

62 36 35 19

66 62 35 19

69 14 10

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

SYNC_MASTER=MASTER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

PP3V42_G3H SPI_CLK SPI_CS0_L SPI_MISO SPI_MOSI SPIROM_USE_MLB LPCPLUS_GPIO LPC_SERIRQ SMC_TMS

(NEED TO ADD 2 GND TP)

FUNC TEST

Apple Inc.

R

8 7

72 37

72 37 19

72 37

47 37 19

37 19

37 35 19

37 36 35

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

7 OF 109

SHEET

7 OF 76

SIZE

D

C

B

A

D

345678

2 1

"S3" RAILS

63 57

=PPVCORE_S0_CPU_REG

58

D

=PPCPUVTT_S0_REG

60

=PPMCPCORE_S0_REG

59

(CPU VCORE PWR)

(MCP VCORE AFTER SENSE RES)

LVDDR VRef/VTT (0.75V/0.675V) Rails

=PPVTT_S0_DDR_LDO

57

C

=PPVTT_S3_DDR_BUF

57 29

=PP1V5_S0_FET

63

=PP1V8_S0_REG

61

=PP1V05_S0_MCP_PLL_OR

B

61

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=1.25V MAKE_BASE=TRUE

=PPVCORE_S0_CPU

PP1V05_S0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_CPU =PP1V05_S0_MCP_FSB =PP1V05_S0_MCP_PE_DVDD =PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_PLL_UF_R =PP1V05_S0_MCP_M2CLK_DLL =PP1V05_S0_MCP_PLL_IFP =PP1V05_S0_MCP_DP0_VDD =PP1V05_SW_MCP_FSB

PPVCORE_S0_MCP

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PPVCORE_S0_MCP =PPVCORE_S0_MCPGFXFET

PPDDRVTT_S0

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE

=PPDDRVTT_S0_MEM_A =PPDDRVTT_S0_MEM_B

PPVTT_S3_DDR_BUF

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE

PP1V5_S0

MIN_LINE_WIDTH=1.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5_S0_CPU =PP1V5_S0_MCP_PLL_VLDO =PP1V8R1V5_S0_AUDIO =PP3V3R1V5_S0_AUDIO =PP3V3R1V5_S0_MCP_HDA

PP1V8_S0

MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=1.8V MAKE_BASE=TRUE

=PP3V3R1V8_S0_MCP_IFP_VDD

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_MCP_PLL_UF

39

7

12 11

7

62

13 12 11 10

23 20 14

8

23

23 20

61

23 15

24 17

23 20

7

39

23 20

22

7

26

27

7

75 62

7

12 11

61

48

23 19

7

24 17

7

23

63 62 61

=PP5V_S0_FET

63

=PP3V3_S0_FET

63

=PP3V3_ENET_FET

9

=PP0V9_ENET_FET

63

"ENET" RAILS

PP5V_S0

MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S0_HDD =PP5V_S0_MCPREG =PP5V_S0_MCPFSBFET =PP5VR3V3_S0_DPCADET =PP5V_S0_CPUVTTS0

=PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT

=PP5V_S0_CPU_IMVP

PP3V3_S0

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S0_XDP =PP3V3_S0_MCP =PP3V3_S0_ODD

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_FAN_RT =PP3V3_S0_AUDIO

=PP3V3_S0_IMVP

=PP3V3_S0_LCD_DDC =PP3V3_S0_MCP_GPIO

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_HVDD =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_DPCONN =PPSPD_S0_MEM_A =PPSPD_S0_MEM_B =PP3V3_S0_PWRCTL =PP3V3_S0_CPUVTTISNS

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_P1V8S0 =PP3V3_S0_MCP_PLL_VLDO =PP3V3_S0_MCPDDRISNS =PP3V3_S0_DEBUGROM =PP3V3_S0_MCPCOREISNS =PP3V3_S0_OPA330

PP3V3_ENET

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MAKE_BASE=TRUE

=PP3V3_ENET_PHY =PP3V3_ENET_MCP_PLL_MAC =PP3V3_ENET_MCP_RMGT

ENET1V05:INT

R0814

0

1 2

5%

1/16W MF-LF

402

PP0V9_ENET

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.9V

MAKE_BASE=TRUE

=PP0V9_ENET_MCP_RMGT

PP3V3_ENET_PHY_VDDREG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_ENET_PHY_VDDREG

7

23 20

62

7

33

59

22

66

60

37

42

58

75 62

7

13

23 20

33

38

42

53 52 48

58

64

19 18 17

23

23 20

36

41

66

26

27

62

40

38

61

40

37

40

23

7

31

9

23

23 20 18

9

31

=PP3V3_S3_FET

63

=PP5V_S3_REG

56

=PP0V9_S5_REG

61

=PP3V3_S5_REG

56

0 MA

4250 MA

"S5" RAILS

105/241 MA

=PPDDR_S3_REG

PP1V5R1V35_S3

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PPLVDDR_S3_MEM_A =PPLVDDR_S3_MEM_B =PP1V5R1V35_S3_MCP_MEM =PP1V5R1V35_S0_MCPDDRFET =PPVIN_S0_DDRREG_LDO

PP3V3_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_PDCISENS

=PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_TPAD =PP3V3_S3_SMS =PP3V3_S3_BT =PP3V3_S3_SMBUS_SMC_MGMT

PP5V_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE

=PP5V_S3_EXTUSB =PP5V_S3_CAMERA =PP5V_S3_AUDIO_AMP =PP5V_S3_MCPDDRFET =PP5V_S3_AUDIO =PP5V_S3_DEBUG_ISNS =PP5V_S3_SYSLED =PP5V_S3_TPAD =PP5V_S3_ODD =PP5V_S3_DEBUG_ADC_AVDD =PP5V_S3_DEBUG_ADC_DVDD =PP5V_S3_P5VS0FET =PP5V_S3_DDRREG

PP0V9_S5

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP0V9_S5_MCP_VDD_AUXC

=PP0V9_ENET_P0V9ENETFET

PP3V3_S5

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE

=PP3V3_S5_MCP_GPIO =PP3V3_S5_ROM =PP3V3_S0_LCD_PANEL =PP3V3_S5_MCP =PP3V3_S5_MCPPWRGD =PP3V3_S5_P3V3S3FET =PP3V3_S5_P3V3S0FET =PP3V3_S5_P0V9S5 =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR =PP3V3_S5_VMON =PP3V3_S5_P0V9ENETFET

=PP3V42_G3H_REG

75

7

26

27

15

21

57

7

38

29

30

19

45

30

38

7

34

64

51

21

46

36

44

33

46

63

57

7

63

7

47

64

25

63

61

63

66

62

63

54

44 43

52 50 48

23 20

75 62

19 18

23 20

=PP18V5_DCIN_CONN

54

=PPBUS_G3H

55

=PPBUS_S5_CPUREGS_ISNS

40

DIGITAL GROUND

GND

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=0V

"G3H" RAILS"S0,S0M" RAILS

PP3V42_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.42V MAKE_BASE=TRUE

=PPVIN_S5_SMCVREF =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_TPAD

=PP3V3_S5_SMC =PP3V3_S5_LPCPLUS PP3V3_G3_RTC =PP3V42_G3H_ONEWIRE =PP3V42_G3H_HALL =PP3V42_G3H_BMON_ISNS =PP3V42_G3H_OPA330

PP18V5_G3H

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.3 MM VOLTAGE=18.5V MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE

=PPVIN_S0_MCPCORE =PPBUS_S0_LCDBKLT

=PPVIN_S5_3V3S5 =PPVIN_S3_5VS3 =PPBUS_S5_CPUREGS_ISNS_R =PPVIN_S3_DDRREG

PPBUS_S5_IMVP_VTT_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.3 MM VOLTAGE=12.6V MAKE_BASE=TRUE

=PPVIN_S0_CPUVTTS0 =PPVIN_S5_CPU_IMVP

7

36

38

62

62 55

34

43

36 35

37

7

54

40

55

39

7

59

68

56

40

57

60

58

D

23 20 19

C

B

UNUSED MCP PE0[3:0] AVDD/DVDD

=PP1V05_S0_MCP_PE_DVDD0

20

=PP1V05_S0_MCP_PE_AVDD0

20

(SINCE PE0[3:0] IS NOT USED ON K6)

(CONNECTS TO MCP BALLS)

=PP1V05_S0_MCP_PE_DVDD1

20

=PP1V05_S0_MCP_PE_AVDD1

20

A

=PP1V05_S0_MCP_PE_DVDD

PP1V05_S0_MCP_PE_AVDD

MAKE_BASE=TRUE

(CONNECTS TO THE DECAPS)

8 23

(CONNECTS TO THE DECAPS)

23

RTL8211_REGOUT

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm VOLTAGE=1.05V

PP1V05_S0_REG

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm VOLTAGE=1.05V

=RTL8211_REGOUT

31

61

=PP1V05_S0_REG

FIX ME!! OUTPUT OF REGULATOR VALUES

8 7 5 4 2 1

ENET1V05:INT

R0812

ENET1V05:EXT

R0813

0

1 2

402

1 2

402

PP1V05_ENET

5%

1/16W05%

MF-LF

VOLTAGE=1.05V

=PP1V05_ENET_PHY

MAKE_BASE=TRUE

MF-LF

1/16W

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm

31

SIZE

A

D

SYNC_MASTER=MASTER

PAGE TITLE

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

8 OF 109

SHEET

8 OF 76

36

345678

PCI-E ALIASES

PCIE_MINI_R2D_C_P

HEATSINK STANDOFFS

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

1

STDOFF-4.5OD.98H-1.1-3.48-TH

LEFT OF CPU

D

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0903

1

STDOFF-4.5OD.98H-1.1-3.48-TH

BELOW MCP

Z0901

1

ABOVE CPU

Z0904

1

BELOW CPU

FAN STANDOFF

OMIT

Z0905

3P2R2P7

1

30

PCIE_MINI_R2D_C_N

CONN_PCIE_MINI_D2R_P

7

75 30

CONN_PCIE_MINI_D2R_N

75 30

7

PCIE_CLK100M_MINI_P

30

PCIE_CLK100M_MINI_N

30

CONN_PCIE_MINI_R2D_P

7

75 30

CONN_PCIE_MINI_R2D_N

75 30

7

=PEG_D2R_N<15:0>

16

=PEG_D2R_P<15:0>

16

=PEG_R2D_C_N<15:0>

16

=PEG_R2D_C_P<15:0>

16

PEG_CLK100M_P

71 16

PEG_CLK100M_N

71 16

PEG_CLKREQ_L

16

UNUSED GPU LANES

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

OMIT

ZS0901

SM

OMIT

Z0907

3P2R2P7

1

OMIT

Z0910

3P2R2P7

1

(870-1794 )

2.0DIA-MED-EMI-MLB-K84

OMIT

ZS0902

SM

PCIE_FW_D2R_P

71 16

PCIE_FW_D2R_N

71 16

PCIE_FW_R2D_C_P

71 16

PCIE_FW_R2D_C_N

71 16

FW_PWR_EN

16

FW_CLKREQ_L

16

FW_PME_L

16

PCIE_CLK100M_FW_P

71 16

PCIE_CLK100M_FW_N

71 16

ENET_CLKREQ_L

16

PCIE_CLK100M_ENET_P

71 16

PCIE_CLK100M_ENET_N

71 16

PCIE_ENET_D2R_P

71 16

PCIE_ENET_D2R_N

71 16

PCIE_ENET_R2D_C_P

71 16

PCIE_ENET_R2D_C_N

71 16

ENET_ENERGY_DET

18 63 62 61

IN

UNUSED FIREWIRE LANE

UNUSED ETHERNET LANE

OMIT

Z0906

3P2R2P7

1

C

MLB MOUNTING (TO TOPCASE) SCREW HOLES

OMIT

Z0911

3P2R2P7

1

LVDS CONNECTOR HOLE

OMIT

Z0913

3P2R2P7

1

OMIT

2.0DIA-MED-EMI-MLB-K84

ZS0900

SM

1 1 1

EMI IO MEDIUM POGO PINS

2.0DIA-MED-EMI-MLB-K84

B

OMIT

2.0DIA-MED-EMI-MLB-K84

ZS0908

SM

EMI TALL POGO PINS

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0904

SM

1

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0912

SM

1

OMIT

2.0DIA-MED-EMI-MLB-K84

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0909

SM

OMIT

ZS0905

1 1

ZS0913

(870-1698 )

SM

OMIT OMIT

SM

2.0DIA-MED-EMI-MLB-K84

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0906

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0914

11

OMIT

ZS0911

SM

2.0DIA-MED-EMI-MLB-K84

OMIT

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0907

1

SM

OMIT

ZS0903

SM

11 1 1

OMIT

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0915

1

SM

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIE_AP_R2D_P

PCIE_AP_R2D_N

NC_PEG_D2R_N<15:0>

NO_TEST=TRUE

NC_PEG_D2R_P<15:0>

NO_TEST=TRUE

NC_PEG_R2D_C_N<15:0>

NO_TEST=TRUE

NC_PEG_R2D_C_P<15:0>

NO_TEST=TRUE

TP_PEG_CLK100M_P

TP_PEG_CLK100M_N

TP_PCIE_CLKREQ_L

TP_PCIE_FW_D2R_P TP_PCIE_FW_D2R_N TP_PCIE_FW_R2D_C_P TP_PCIE_FW_R2D_C_N TP_FW_PWR_EN TP_FW_CLKREQ_L TP_FW_PME_L

TP_PCIE_CLK100M_FW_P

TP_PCIE_CLK100M_FW_N

TP_ENET_CLKREQ_L

TP_PCIE_CLK100M_ENET_P

TP_PCIE_CLK100M_ENET_N TP_PCIE_ENET_D2R_P

TP_PCIE_ENET_D2R_N TP_PCIE_ENET_R2D_C_P

TP_PCIE_ENET_R2D_C_N

R0970

100K

1 2

1/16W MF-LF

402

2.0DIA-TALL-EMI-MLB-M97-M98

5%

=PP3V3_ENET_FET

OMIT

ZS0910

SM

1

OMIT

ZS0919

SM

1

MAKE_BASE=TRUE

71 16

71 16 30

71 16

71

17

8

OUT

19

USB_EXTD_P

72 18

USB_EXTD_N

72 18

USB_EXTC_P

72 18

USB_EXTC_N

72 18

USB_MINI_P

72 18

USB_MINI_N

72 18

USB_SDCARD_P

72 18

USB_SDCARD_N

72 18

USB_WM_P

72 18

USB_WM_N

72 18

USB_IR_N

72 18

USB_IR_P

72 18

USB_T57_P

72 18

USB_T57_N

72 18

=MCP_IFPA_TXD_P<0..2>

IN

=MCP_IFPA_TXD_N<0..2>

IN

=MCP_IFPAB_DDC_CLK

IN

=MCP_IFPAB_DDC_DATA

BI

=MCP_IFPA_TXD_P<3>

IN

=MCP_IFPA_TXD_N<3>

IN

=MCP_IFPB_TXC_P

IN

=MCP_IFPB_TXC_N

IN

=MCP_IFPB_TXD_P<0..3>

IN

=MCP_IFPB_TXD_N<0..3>

IN

LCD_IG_BKLT_PWM

IN

LCD_IG_BKLT_EN

IN

LCD_IG_PWR_EN

IN

=MCP_IFPA_TXC_P

IN

=MCP_IFPA_TXC_N

IN

DP_IG_ML0_P<0..3>

17

IN

DP_IG_ML0_N<0..3>

17

IN

DP_IG_AUX_CH0_P

17

BI

DP_IG_AUX_CH0_N

17

BI

DP_IG_ML1_P<0..3>

17

IN

DP_IG_ML1_N<0..3>

17

IN

DP_IG_AUX_CH1_P

17

BI

DP_IG_AUX_CH1_N

17

BI

DP_IG_HPD0

17

OUT

DP_AUX_CH_C_N

65

BI

DP_AUX_CH_C_P

65

BI

DP_CA_DET

OUT

DP_IG_HPD1

17

MCP_MEM_VDD_SEL_1V5

IN

USB ALIASES

UNUSED USB PORTS

TP_USB_EXTD_P TP_USB_EXTD_N TP_USB_EXTC_P TP_USB_EXTC_N TP_USB_MINI_P TP_USB_MINI_N TP_USB_SDCARD_P TP_USB_SDCARD_N TP_USB_WM_P TP_USB_WM_N TP_USB_IR_N TP_USB_IR_P TP_USB_T57_P TP_USB_T57_N

LVDS ALIASES

LVDS_IG_A_DATA_P<0..2>

LVDS_IG_A_DATA_N<0..2>

LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA NC_LVDS_IG_A_DATA_P3

NC_LVDS_IG_A_DATA_N3

NC_LVDS_IG_B_CLK_P

NC_LVDS_IG_B_CLK_N

NC_LVDS_IG_B_DATA_P<0..3>

NC_LVDS_IG_B_DATA_N<0..3>

LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N

DISPLAY PORT ALIASES

DP_EXT_ML_P<0..3> DP_IG_ML_P<0..3>

DP_EXT_ML_N<0..3> DP_IG_ML_N<0..3>

DP_IG_AUX_CH_P DP_IG_AUX_CH_N TP_DP_IG_ML1P<0..3> TP_DP_IG_ML1N<0..3> TP_DP_IG_AUX_CH1P TP_DP_IG_AUX_CH1N DP_EXT_HPD

DP_EXT_AUX_CH_C_N DP_EXT_AUX_CH_C_P

DP_EXT_CA_DET

R0940

100K

1 2

5% 1/16W MF-LF

402

MCP89 MISC ALIASES

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_MCP_MEM_VDD_SEL_1V5

MAKE_BASE=TRUE

OUT OUT

MAKE_BASE=TRUE

TP_ENET_RESET_L

18 73 31

TP_MCP_CLK25M_BUF0_R

18

TP_ENET_MDC

18

TP_ENET_TX_CTRL

18

TP_ENET_CLK125M_TXCLK

18

TP_ENET_TXD<0..3>

18

=PP3V3_ENET_PHY

31

8

71 64

7

OUT

71 64

7

OUT

64

7

OUT

7

64

BI

68 67

OUT

68

OUT

64

OUT

71 64

OUT

71 64

OUT

75 66

71

75 66

71

71 65

BI

71 65

BI

23 20 18

8

=PP3V3_ENET_MCP_RMGT

CPU FSB FREQUENCY STRAPS

CPU_BSEL<0:2>

69 10 14

IN

MAKE_BASE=TRUE

CPU_PECI_MCP

66

IN

75 66

BI

75 66

BI

66 65

IN

14

SMC_SYS_KBDLED

35

=CHGR_ACOK

55 54 36 35

IN

IMVP6_VR_TT

58

IN

IMVP6_NTC

58

IN

A

EMI THINBC POGO PINS

OMIT

ZS0917

2.0DIA-MLB-THIN-BC-K84

SM

1

2.0DIA-MLB-THIN-BC-K84

OMIT

ZS0918

1

SM

8 7 5 4 2 1

(870-1820 )

OMIT

ZS0916

2.0DIA-MLB-THIN-BC-K84

SM

1

NOSTUFF

ZS0920

2.0DIA-MLB-THIN-BC-K84

SM

1

36

2 1

ETHERNET ALIASES

ENET_RESET_L MCP_CLK25M_BUF0_R ENET_MDC ENET_TX_CTRL ENET_CLK125M_TXCLK ENET_TXD<0..3>

ENET1V05:INT

1

R0915

0

5% 1/16W MF-LF 402

2

ENET1V05:EXT

1

R0916

0

5% 1/16W MF-LF 402

2

MCP89 ETHERNET VREF

SMC ALIASES

CHARGER SIGNAL

CPU VCORE ALIASES

SYNC_MASTER=(K84_MLB)

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

RTL8211_ENSWREG

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2mm

=RTL8211_ENSWREG

1

R0957

1.47K

1% 1/16W MF-LF

402

2

MCP_RGMII_VREF

1

R0958

1.47K

=MCP_BSEL<0:2>

TP_SMC_SYS_KBDLED

SMC_BC_ACOK

TP_IMVP6_VR_TT

TP_IMVP6_NTC

1% 1/16W MF-LF

402

2

TP_CPU_PECI_MCP

1

C0958

0.1UF

20% 10V

2

CERM 402

OUT

SIGNAL ALIAS

Apple Inc.

R

MAKE_BASE=TRUE

BSEL<2..0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

73 31

31

OUT

18

OUT

FSB MHZ

266 133 200

(166)

333

100 (400) (RSVD)

OUT

SYNC_DATE=(02/04/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

9 OF 109

SHEET

9 OF 76

SIZE

D

C

B

A

D

345678

2 1

OMIT

ADS* BNR*

BPRI*

DEFER*

DRDY* DBSY*

BR0*

IERR* INIT*

LOCK*

RESET*

RS0* RS1* RS2*

TRDY*

HIT*

HITM*

BPM0* BPM1* BPM2* BPM3* PRDY* PREQ*

TRST*

DBR*

THERMDA THERMDC

BCLK0 BCLK1

TCK TDI TDO TMS

H1

FSB_ADS_L

E2

FSB_BNR_L

G5

FSB_BPRI_L

H5

FSB_DEFER_L

F21

FSB_DRDY_L

E1

FSB_DBSY_L

F1

FSB_BREQ0_L

D20

CPU_IERR_L

69

B3

CPU_INIT_L

H4

FSB_LOCK_L

C1

FSB_CPURST_L

F3

FSB_RS_L<0>

F4

FSB_RS_L<1>

G3

FSB_RS_L<2>

G2

FSB_TRDY_L

G6

FSB_HIT_L

E4

FSB_HITM_L

AD4

XDP_BPM_L<0>

AD3

XDP_BPM_L<1>

AD1

XDP_BPM_L<2>

AC4

XDP_BPM_L<3>

AC2

XDP_BPM_L<4>

AC1

XDP_BPM_L<5>

AC5

XDP_TCK

AA6

XDP_TDI

AB3

XDP_TDO

AB5

XDP_TMS

AB6

XDP_TRST_L

C20

XDP_DBRESET_L

D21

CPU_PROCHOT_L

A24

CPU_THERMD_P

B25

CPU_THERMD_N

C7

PM_THRMTRIP_L

A22

FSB_CLK_CPU_P

A21

FSB_CLK_CPU_N

BI BI BI

BI

14 69

IN

BI

13 14 69

IN

14 69

IN

14 69

IN

14 69

IN

14 69

IN

BI BI

BI BI BI BI BI

10 13 69

IN

10 13 69

IN

OUT

10 13 69

IN

10 13 69

IN

OUT

OUT OUT

OUT

14 69

IN

14 69

IN

CPU JTAG Support

XDP_TMS

10 13 69

XDP_TDI

10 13 69

XDP_TDO

10 13 69

PLACE_NEAR=J1300.51:12.7 mm

XDP_TCK

10 13 69

XDP_TRST_L

10 13 69

7

14 69

7

14 69

7

14 69

7

14 69

13 69

10 13 69

13 25

41 75

14 36 69

R1091

54.9

1 2

R1094

1 2

1/16W MF-LF

402

649

1/16W MF-LF

402

R1000

54.9

1/16W MF-LF

=PP1V05_S0_CPU

1

1%

402

2

8

11 12 13

D

OMIT

AD26

AF26

E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25

N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24

C23 D25 C24

AF1 A26

B22 B23 C21

C3

D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*

D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1*

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2

U1000

PENRYN

FCBGA

2 OF 4

DATA GRP 0DATA GRP 1

MISC

DATA GRP 3 DATA GRP 2

FSB_D_L<0>

7

14 69

BI

FSB_D_L<1>

7

14 69

1

R1001

54.9

1% 1/16W MF-LF

402

2

1

R1002

68

5% 1/16W MF-LF

402

2

R1090

54.9

1 2

1% 1/16W MF-LF

402

1%

R1092

54.9

1 2

1% 1/16W MF-LF

402

R1093

54.9

1 2

1% 1/16W MF-LF

402

1%

BI

OUT

1

R1005

1K

1% 1/16W MF-LF 402

2

1

R1006

2.0K

1% 1/16W MF-LF 402

2

NO STUFF

R1011

13 69

14 36 69

PLACE_NEARs:

R1005.2: R1006.1: C1014.1:

NO STUFF

R1010

1 2

1

1K

5% 1/16W MF-LF

402

2

U1000.AD26:12.7 mm U1000.AD26:12.7 mm U1000.AF26:12.7 mm

NO STUFF

C1014

0

5% 1/16W MF-LF

402

NO STUFF

1

R1012

1K

5% 1/16W MF-LF 402

2

0.1uF

1

10% 16V

2

X5R 402

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

29 69

9

69

OUT

9

69

OUT

9

69

OUT

FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTB_L_N<1> FSB_DSTB_L_P<1> FSB_DINV_L<1>

CPU_GTLREF CPU_TEST1

CPU_TEST2 TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5 TP_CPU_TEST6

TP_CPU_TEST7

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46*

D47* DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63* DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

Y22

FSB_D_L<32>

AB24

FSB_D_L<33>

V24

FSB_D_L<34>

V26

FSB_D_L<35>

V23

FSB_D_L<36>

T22

FSB_D_L<37>

U25

FSB_D_L<38>

U23

FSB_D_L<39>

Y25

FSB_D_L<40>

W22

FSB_D_L<41>

Y23

FSB_D_L<42>

W24

FSB_D_L<43>

W25

FSB_D_L<44>

AA23

FSB_D_L<45>

AA24

FSB_D_L<46>

AB25

FSB_D_L<47>

Y26

FSB_DSTB_L_N<2>

AA26

FSB_DSTB_L_P<2>

U22

FSB_DINV_L<2>

AE24

FSB_D_L<48>

AD24

FSB_D_L<49>

AA21

FSB_D_L<50>

AB22

FSB_D_L<51>

AB21

FSB_D_L<52>

AC26

FSB_D_L<53>

AD20

FSB_D_L<54>

AE22

FSB_D_L<55>

AF23

FSB_D_L<56>

AC25

FSB_D_L<57>

AE21

FSB_D_L<58>

AD21

FSB_D_L<59>

AC22

FSB_D_L<60>

AD23

FSB_D_L<61>

AF22

FSB_D_L<62>

AC23

FSB_D_L<63>

AE25

FSB_DSTB_L_N<3> FSB_DSTB_L_P<3>

AF24

FSB_DINV_L<3>

AC20

R26

CPU_COMP<0>

69

U26

CPU_COMP<1>

69

AA1

CPU_COMP<2>

69

CPU_COMP<3>

69

Y1

E5

CPU_DPRSTP_L

B5

CPU_DPSLP_L

D24

FSB_DPWR_L

D6

CPU_PWRGD

D7

FSB_CPUSLP_L

AE6

CPU_PSI_L

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

7

14 69

BI

14 58 69

IN

14 69

IN

14 69

IN

13 14 69

IN

14 69

IN

58

OUT

R1023

54.9

1/16W MF-LF

1

1%

402

2

1

2

R1021

54.9

1/16W MF-LF

R1022

27.4

1% 1/16W MF-LF 402

1

1%

402

2

1

R1020

27.4

1% 1/16W MF-LF 402

2

C

B

PLACE_NEARs:

R1020.1:

U1000.R26:12.7 mm U1000.U26:12.7 mm

R1021.1: R1022.1:

U1000.AA1:12.7 mm

R1023.1:

U1000.Y1:12.7 mm

AA4 AB2 AA3

D22

J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1

K3 H2 K2 J3 L1

Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3

V1

A6 A5 C4

D5 C6 B4 A3

M4 N5 T2 V3 B2 F6 D2

D3

A3* A4* A5* A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0*

REQ0* REQ1* REQ2* REQ3* REQ4*

A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1*

A20M* FERR* IGNNE*

STPCLK* LINT0 LINT1 SMI*

RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8

U1000

PENRYN

FCBGA

1 OF 4

ADDR GROUP0

ADDR GROUP1

ICH

RESERVED

CONTROL

XDP/ITP SIGNALS

THERMAL

PROCHOT*

THERMTRIP*

H CLK

FSB_A_L<3>

7

14 69

BI

FSB_A_L<4>

7

14 69

BI

FSB_A_L<5>

7

14 69

BI

FSB_A_L<6>

7

14 69

BI

FSB_A_L<7>

7

14 69

BI

FSB_A_L<8>

7

14 69

BI

FSB_A_L<9>

7

14 69

BI

FSB_A_L<10>

7

14 69

BI

FSB_A_L<11>

7

14 69

BI

FSB_A_L<12>

7

14 69

BI

FSB_A_L<13>

7

14 69

D

C

BI

FSB_A_L<14>

7

14 69

BI

FSB_A_L<15>

7

14 69

BI

FSB_A_L<16>

7

14 69

BI

FSB_ADSTB_L<0>

7

14 69

BI

FSB_REQ_L<0>

7

14 69

BI

FSB_REQ_L<1>

7

14 69

BI

FSB_REQ_L<2>

7

14 69

BI

FSB_REQ_L<3>

7

14 69

BI

FSB_REQ_L<4>

7

14 69

BI

FSB_A_L<17>

7

14 69

BI

FSB_A_L<18>

7

14 69

BI

FSB_A_L<19>

7

14 69

BI

FSB_A_L<20>

7

14 69

BI

FSB_A_L<21>

7

14 69

BI

FSB_A_L<22>

7

14 69

BI

FSB_A_L<23>

7

14 69

BI

FSB_A_L<24>

7

14 69

BI

FSB_A_L<25>

7

14 69

BI

FSB_A_L<26>

7

14 69

BI

FSB_A_L<27>

7

14 69

BI

FSB_A_L<28>

7

14 69

BI

FSB_A_L<29>

7

14 69

BI

FSB_A_L<30>

7

14 69

BI

FSB_A_L<31>

7

14 69

BI

FSB_A_L<32>

7

14 69

BI

FSB_A_L<33>

7

14 69

BI

FSB_A_L<34>

7

14 69

BI

FSB_A_L<35>

7

14 69

BI

FSB_ADSTB_L<1>

7

14 69

BI

CPU_A20M_L

14 69

IN

CPU_FERR_L

14 69

OUT

CPU_IGNNE_L

14 69

IN

CPU_STPCLK_L

14 69

IN

CPU_INTR

14 69

IN

CPU_NMI

14 69

IN

CPU_SMI_L

14 69

IN

TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2 TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3

B

A

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU FSB

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

10 OF 109

SHEET

10 OF 76

SIZE

A

D

345678

2 1

A4

(CPU CORE POWER) =PPVCORE_S0_CPU

A10 A12 A13 A15 A17 A18 A20

B10 B12 B14 B15 B17 B18 B20

C10 C12 C13 C15 C17 C18

D10 D12 D14 D15 D17 D18

E10 E12 E13 E15 E17 E18 E20

F10 F12 F14 F15 F17 F18 F20 AA7

AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18

A7 A9

B7 B9

C9

D9

VCC

E7 E9

F7 F9

OMIT

U1000

PENRYN

FCBGA

3 OF 4

(BR1#)

VCCSENSE

VSSSENSE

D

C

B

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCC

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18

(CPU IO POWER 1.05V)

AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

=PP1V05_S0_CPU

(CPU INTERNAL PLL POWER 1.5V) =PP1V5_S0_CPU

CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

4500 mA (before VCC stable) 2500 mA (after VCC stable)

8

11 12

44 A (SV Design Target) 41 A (SV HFM)

30.4 A (SV LFM) 23 A (LV Design Target)

8

10 12 13

8

12

130 mA

58 69

OUT

58 69

OUT

58 69

OUT

58 69

OUT

58 69

OUT

58 69

OUT

58 69

OUT

1

R1100

100

1% 1/16W MF-LF 402

2

PLACE_NEAR=U1000.AF7:25.4 mm

PLACE_NEAR=U1000.AE7:25.4 mm

1

R1101

100

1% 1/16W MF-LF 402

2

=PPVCORE_S0_CPU

58 69

OUT

58 69

OUT

8

11 12

A8 A11 A14 A16 A19 A23 AF2

B6

B8 B11 B13 B16 B19 B21 B24

C5

C8 C11 C14 C16 C19

C2 C22 C25

D1

D4

D8 D11 D13 D16 D19 D23 D26

E3

E6

E8 E11 E14

VSS VSS E16 E19 E21 E24

F5

F8 F11 F13 F16 F19

F2 F22 F25

G4

G1 G23 G26

H3

H6 H21 H24

J2

J5 J22 J25

K1

K4 K23 K26

L3

L6 L21 L24

M2

M5 M22 M25

N1

N4 N23 N26

P3

B1

(Socket-P KEY)

OMIT

U1000

PENRYN

FCBGA

4 OF 4

P6 P21 P24 R2 R5 R22 R25 T1 T4

T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

D

C

B

A

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU Power & Ground

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

11 OF 109

SHEET

11 OF 76

36

CPU VCore HF and Bulk Decoupling

4X 330UF. 20X 22UF 0805

PLACEMENT_NOTE (C1200-C1219):

345678

2 1

D

Place inside socket cavity on secondary side.

Place inside socket cavity on secondary side.Place inside socket cavity on secondary side.

Place inside socket cavity on secondary side.

=PPVCORE_S0_CPU

8

11

NO STUFF CRITICAL

1

C1200

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1210

22UF

20%

6.3V

2

CERM-X5R 805

1

C1201

22UF

20%

6.3V

2

CERM-X5R 805

NO STUFF NO STUFF CRITICAL

1

C1211

22UF

20%

6.3V

2

CERM-X5R 805

NO STUFF CRITICALCRITICAL

1

C1202

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1212

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1203

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1213

22UF

20%

6.3V

2

CERM-X5R 805

NO STUFF CRITICAL

1

C1204

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1214

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1205

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1215

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1206

22UF

20%

6.3V

2

CERM-X5R 805

NO STUFF

CRITICAL

1

C1216

22UF

20%

6.3V

2

CERM-X5R 805

NO STUFF

CRITICAL

1

C1207

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1217

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1208

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1218

22UF

20%

6.3V

2

CERM-X5R 805

NO STUFF

CRITICAL

1

C1209

22UF

20%

6.3V

2

CERM-X5R 805

CRITICAL

1

C1219

22UF

20%

6.3V

2

CERM-X5R 805

D

PLACEMENT_NOTE (C1240-C1243): Place on secondary side.

Place on secondary side.

CRITICAL NO STUFF

1

C

C1240

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT D2T-SM

1

2

CRITICAL

C1230

22UF

20%

6.3V X5R-CERM 603

CRITICAL

1

C1241

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT D2T-SM

NO STUFF CRITICAL

1

C1231

22UF

20%

6.3V

2

X5R-CERM 603

3 2

NO STUFF CRITICAL

1

C1232

22UF

20%

6.3V

2

X5R-CERM 603

CRITICAL

1

C1242

470UF-4MOHM

20%

2.0V POLY-TANT D2T-SM

1

2

CRITICAL

C1233

22UF

20%

6.3V X5R-CERM 603

CRITICAL

1

C1243

470UF-4MOHM

20%

2.0V

3 2

POLY-TANT D2T-SM

1

2

CRITICAL

C1234

22UF

20%

6.3V X5R-CERM 603

NO STUFF CRITICAL

1

C1235

22UF

20%

6.3V

2

X5R-CERM 603

NO STUFF CRITICAL

1

C1236

22UF

20%

6.3V

2

X5R-CERM 603

CRITICAL

1

C1237

22UF

20%

6.3V

2

X5R-CERM 603

C

VCCA (CPU AVdd) DECOUPLING

B

=PP1V5_S0_CPU

8

11

C1250

1x 10uF, 1x 0.01uF

BYPASS=U1000.B26::4 mm

1

C1251

10uF

6.3V

20% X5R

603

0.01UF

10% 16V

2

CERM 402

B

VCCP (CPU I/O) DECOUPLING

=PP1V05_S0_CPU

8

10 11 13

CRITICAL

C1260

POLY-TANT

A

8 7 5 4 2 1

1x 330uF, 6x 0.1uF 0402

PLACEMENT_NOTE=Place C1260 between CPU & NB.

1

330UF

2.0V

D2T-SM2

1

C1261

0.1UF

20%

20% 10V

32

2

CERM 402

1

C1262

0.1UF

20% 10V

2

CERM 402

1

2

C1263

0.1UF

20% 10V CERM 402

1

C1264

0.1UF

20% 10V

2

CERM 402

1

C1265

0.1UF

20% 10V

2

CERM 402

1

C1266

0.1UF

20% 10V

2

CERM 402

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

12 OF 109

SHEET

12 OF 76

36

345678

2 1

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

D

USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.

MCP89-SPECIFIC PINOUT

=PP3V3_S0_XDP

8

=PP1V05_S0_CPU

8

10 11 12

XDP

1

R1315

54.9

1% 1/16W MF-LF

402

2

XDP_BPM_L<5>

10 69

BI

XDP_BPM_L<4>

10 69

BI

XDP_BPM_L<3>

10 69

BI

XDP_BPM_L<2>

10 69

IN

XDP_BPM_L<1>

10 69

IN

XDP_BPM_L<0>

10 69

IN

C

XDP

R1399

1K

10 14 69

IN

CPU_PWRGD

1 2

5% 1/16W MF-LF

402

TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3

XDP_PWRGD

PM_LATRIGGER_L

19

IN

JTAG_MCP_TCK

19

OUT

SMBUS_MCP_0_DATA

19 38 72

BI

SMBUS_MCP_0_CLK

19 38 72

BI

XDP_TCK

10 69

OUT

XDP_OBS20

OBSFN_A0 OBSFN_A1

OBSDATA_A0 OBSDATA_A1

OBSDATA_A2 OBSDATA_A3

OBSFN_B0 OBSFN_B1

OBSDATA_B0 OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2 HOOK3

XDP

C1300

0.1uF

TCK1 TCK0

10% 16V X5R 402

SDA SCL

1

2

B

XDP_CON

CRITICAL

J1300

DF40C-60DS-0.4V

F-ST-SM-HF 1

2

3

4

5

6

7

8

9

10

11

12

13

14 16

15

18

17

20

19

22

21

24

23 25

26 28

27

30

29

32

31

34

33

36

35

38

37

40

39 41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

NC

56

57

58

59

60

518S0774

OBSFN_C0 OBSFN_C1

OBSDATA_C0 OBSDATA_C1

OBSDATA_C2 OBSDATA_C3

OBSFN_D0 OBSFN_D1

OBSDATA_D0 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. TDO TRSTn TDI TMS XDP_PRESENT#

XDP

1

C1301

0.1uF

10% 16V

2

X5R 402

JTAG_MCP_TDO JTAG_MCP_TRST_L

TP_XDP_OBSDATA_C0 TP_XDP_OBSDATA_C1

TP_XDP_OBSDATA_C2 TP_XDP_OBSDATA_C3

JTAG_MCP_TDI JTAG_MCP_TMS

TP_XDP_OBSDATA_D0 TP_XDP_OBSDATA_D1

TP_XDP_OBSDATA_D2 TP_XDP_OBSDATA_D3

FSB_CLK_ITP_P FSB_CLK_ITP_N

XDP_CPURST_L

69

XDP_DBRESET_L

XDP_TDO XDP_TRST_L XDP_TDI XDP_TMS

19

IN

19

OUT

19

OUT

19

OUT

14 69

IN

14 69

IN

10 25

OUT

10 69

IN

10 69

OUT

10 69

OUT

10 69

OUT

XDP

R1303

1K

1 2

5% 1/16W MF-LF

402

FSB_CPURST_L

PLACE_NEAR=U1000.C1:5 MM

10 14 69

IN

D

C

B

Direction of XDP module

Please avoid any obstructions

ON ODD-NUMBERED SIDE OF J1300

A

8 7 5 4 2 1

36

SYNC_MASTER=(K84_MLB)

PAGE TITLE

eXtended Debug Port(MiniXDP)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(02/25/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

13 OF 109

SHEET

13 OF 76

SIZE

A

D

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

FSB_DSTB_L_P<0>

7

10 69

BI

FSB_DSTB_L_N<0>

7

10 69

BI

FSB_DINV_L<0>

7

10 69

BI

FSB_DSTB_L_P<1>

7

10 69

BI

FSB_DSTB_L_N<1>

7

10 69

BI

FSB_DINV_L<1>

7

10 69

BI

FSB_DSTB_L_P<2>

7

10 69

D

C

B

=PP1V05_S0_MCP_FSB

8

14 20 23

1

10 36 69

IN

10 69

IN

9

IN

9

IN

9

IN

R1410

PM_THRMTRIP_L CPU_FERR_L

=MCP_BSEL<2> =MCP_BSEL<1> =MCP_BSEL<0>

54.9

1% 1/16W MF-LF

402

R1430

49.9

1/16W MF-LF

2

1%

402

121

R1415

62

5% 1/16W MF-LF 402

2

R1435

49.9

1% 1/16W MF-LF 402

2

A

121

R1431

49.9

1/16W MF-LF

R1436

49.9

1%

1/16W MF-LF 402

402

2

BI

FSB_DSTB_L_N<2>

7

10 69

BI

FSB_DINV_L<2>

7

10 69

BI

FSB_DSTB_L_P<3>

7

10 69

BI

FSB_DSTB_L_N<3>

7

10 69

BI

FSB_DINV_L<3>

7

10 69

BI

FSB_A_L<3>

7

10 69

BI

FSB_A_L<4>

7

10 69

BI

FSB_A_L<5>

7

10 69

BI

FSB_A_L<6>

7

10 69

BI

FSB_A_L<7>

7

10 69

BI

FSB_A_L<8>

7

10 69

BI

FSB_A_L<9>

7

10 69

BI

FSB_A_L<10>

7

10 69

BI

FSB_A_L<11>

7

10 69

BI

FSB_A_L<12>

7

10 69

BI

FSB_A_L<13>

7

10 69

BI

FSB_A_L<14>

7

10 69

BI

FSB_A_L<15>

7

10 69

BI

FSB_A_L<16>

7

10 69

BI

FSB_A_L<17>

7

10 69

BI

FSB_A_L<18>

7

10 69

BI

FSB_A_L<19>

7

10 69

BI

FSB_A_L<20>

7

10 69

BI

FSB_A_L<21>

7

10 69

BI

FSB_A_L<22>

7

10 69

BI

FSB_A_L<23>

7

10 69

BI

FSB_A_L<24>

7

10 69

BI

FSB_A_L<25>

7

10 69

BI

FSB_A_L<26>

7

10 69

BI

FSB_A_L<27>

7

10 69

BI

FSB_A_L<28>

7

10 69

BI

FSB_A_L<29>

7

10 69

BI

FSB_A_L<30>

7

10 69

BI

FSB_A_L<31>

7

10 69

BI

FSB_A_L<32>

7

10 69

BI

FSB_A_L<33>

7

10 69

BI

FSB_A_L<34>

7

10 69

BI

FSB_A_L<35>

7

10 69

BI

FSB_ADSTB_L<0>

7

10 69

BI

FSB_ADSTB_L<1>

7

10 69

BI

FSB_REQ_L<0>

7

10 69

BI

FSB_REQ_L<1>

7

10 69

BI

FSB_REQ_L<2>

7

10 69

BI

FSB_REQ_L<3>

7

10 69

BI

FSB_REQ_L<4>

7

10 69

BI

FSB_ADS_L

7

10 69

IN

FSB_BNR_L

10 69

IN

FSB_BREQ0_L

10 69

IN

FSB_DBSY_L

10 69

IN

FSB_DRDY_L

10 69

IN

FSB_HIT_L

7

10 69

IN

FSB_HITM_L

7

10 69

IN

FSB_LOCK_L

7

10 69

IN

FSB_TRDY_L

10 69

BI

CPU_PECI_MCP

9

OUT

CPU_PROCHOT_L

10 36 69

OUT

FSB_RS_L<0>

10 69

OUT

FSB_RS_L<1>

10 69

OUT

FSB_RS_L<2>

10 69

OUT

69

MCP_BCLK_VML_COMP_VDD

69

MCP_BCLK_VML_COMP_GND

69

MCP_CPU_COMP_VCC

69

MCP_CPU_COMP_GND

K34

CPU_DSTBP0*

K35

CPU_DSTBN0*

L37

CPU_DBI0*

T31

CPU_DSTBP1*

T30

CPU_DSTBN1*

P28

CPU_DBI1*

K33

CPU_DSTBP2*

K32

CPU_DSTBN2*

N35

CPU_DBI2*

C36

CPU_DSTBP3*

D36

CPU_DSTBN3*

A35

CPU_DBI3*

U38

CPU_A3*

U34

CPU_A4*

U35

CPU_A5*

T34

CPU_A6*

W37

CPU_A7*

W38

CPU_A8*

T37

CPU_A9*

Y38

CPU_A10*

W35

CPU_A11*

Y36

CPU_A12*

U33

CPU_A13*

W34

CPU_A14*

Y37

CPU_A15*

Y35

CPU_A16*

AF38

CPU_A17*

AB35

CPU_A18*

Y34

CPU_A19*

AE38

CPU_A20*

AC36

CPU_A21*

AF36

CPU_A22*

AC38

CPU_A23*

AB36

CPU_A24*

AB38

CPU_A25*

AB37

CPU_A26*

AC34

CPU_A27*

AE36

CPU_A28*

AF37

CPU_A29*

AC37

CPU_A30*

AC35

CPU_A31*

AE37

CPU_A32*

AE35

CPU_A33*

AE33

CPU_A34*

AE34

CPU_A35*

W36

CPU_ADSTB0*

AB34

CPU_ADSTB1*

U36

CPU_REQ0*

T36

CPU_REQ1*

U37

CPU_REQ2*

T38

CPU_REQ3*

T35

CPU_REQ4*

AE31

CPU_ADS*

AE32

CPU_BNR*

AE30

CPU_BR0*

AE29

CPU_DBSY*

U29

CPU_DRDY*

W32

CPU_HIT*

AB31

CPU_HITM*

AC32

CPU_LOCK*

AC29

CPU_TRDY*

AH34

CPU_PECI

U28

CPU_PROCHOT*

W33

CPU_THERMTRIP*

AB32

CPU_FERR*

B34

CPU_BSEL2

C34

CPU_BSEL1

A34

CPU_BSEL0

AB29

CPU_RS0*

AC33

CPU_RS1*

AC31

CPU_RS2*

AH37

BCLK_VML_COMP_VDD

AH38

BCLK_VML_COMP_GND

AH36

CPU_COMP_VCC

AH35

CPU_COMP_GND

8 7 5 4 2 1

(1 OF 11)

CPU_D0* CPU_D1* CPU_D2* CPU_D3* CPU_D4* CPU_D5* CPU_D6* CPU_D7* CPU_D8*

CPU_D9* CPU_D10* CPU_D11* CPU_D12* CPU_D13* CPU_D14* CPU_D15* CPU_D16* CPU_D17* CPU_D18* CPU_D19* CPU_D20* CPU_D21* CPU_D22* CPU_D23* CPU_D24* CPU_D25* CPU_D26* CPU_D27* CPU_D28* CPU_D29* CPU_D30* CPU_D31* CPU_D32* CPU_D33* CPU_D34* CPU_D35* CPU_D36* CPU_D37* CPU_D38* CPU_D39*

FSB

CPU_D40* CPU_D41* CPU_D42* CPU_D43* CPU_D44* CPU_D45* CPU_D46* CPU_D47* CPU_D48* CPU_D49* CPU_D50* CPU_D51* CPU_D52* CPU_D53* CPU_D54* CPU_D55* CPU_D56* CPU_D57* CPU_D58* CPU_D59* CPU_D60* CPU_D61* CPU_D62* CPU_D63*

CPU_BPRI*

CPU_DEFER*

BCLK_OUT_CPU_N BCLK_OUT_CPU_P

BCLK_OUT_ITP_N BCLK_OUT_ITP_P

BCLK_OUT_NB_N BCLK_OUT_NB_P

BCLK_IN_P BCLK_IN_N

CPU_A20M*

CPU_IGNNE*

CPU_INIT*

CPU_INTR

CPU_NMI CPU_SMI*

CPU_PWRGD

CPU_RESET*

CPU_DPRSLPVR

CPU_SLP*

CPU_DPSLP*

CPU_DPWR* CPU_STPCLK* CPU_DPRSTP*

N38 N36 P36 L36 N34 L35 P37 P38 H36 L34 K37 K36 K38 N37 H37 L38 N28 U30 N29 P34 T29 T32 U32 T33 P31 P30 N30 P33 N31 T28 P35 P29 H33 G34 L30 L31 L33 P32 N32 N33 H35 K31 H34 K30 L32 G33 H32 G35 C37 D37 H38 G38 G37 G36 B35 E35 B36 E36 C35 D34 E38 D38 E34 E37

Y31 Y30

AF32 AF33

AF35 AF34

AF28 AF29

AF30 AF31

W30 AB30 AB28 W31 AC30 AC28 Y32 AE28 G1 Y33 AB33 U31 Y29 W29

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

FSB_BPRI_L FSB_DEFER_L

FSB_CLK_CPU_N FSB_CLK_CPU_P

FSB_CLK_ITP_N FSB_CLK_ITP_P

FSB_CLK_MCP_N

69

FSB_CLK_MCP_P

69

CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L CPU_PWRGD FSB_CPURST_L PM_DPRSLPVR FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

7

10 69

BI

10 69

OUT

10 69

OUT

10 69

OUT

10 69

OUT

13 69

OUT

13 69

OUT

Loop-back clock for delay matching.

10 69

OUT

10 69

OUT

10 69

OUT

10 69

OUT

10 69

OUT

10 69

OUT

10 13 69

OUT

58 69

OUT

10 69

OUT

10 69

OUT

10 69

OUT

10 69

OUT

10 58 69

OUT

=PP1V05_S0_MCP_FSB

NO STUFF

1

R1440

150

5% 1/16W MF-LF 402

2

10 13 69

OUT

36

8

14 20 23

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP CPU Interface

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

14 OF 109

SHEET

14 OF 76

SIZE

D

C

B

A

D

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0

MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0

(2 OF 11)

MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N

MEMORY PARTITION 0

+VIO_M2CLK_DLL_1 +VIO_M2CLK_DLL_2

+VIO_PLL_MEM_1 +VIO_PLL_MEM_2

+VIO_PLL_FSB_1 +VIO_PLL_FSB_2

+VIO_PLL_CPU_1 +VIO_PLL_CPU_2 +VIO_PLL_CPU_3 +VIO_PLL_CPU_4

MCLK0A_1_P MCLK0A_1_N

MCLK0A_0_P MCLK0A_0_N

AK11 AL11 AH13 AH14 AL10 AK10 AN11 AJ13 AK13 AK14 AJ16 AH16 AJ14 AL13 AM14 AN14 AK17 AL17 AN17 AJ19 AH17 AJ17 AM16 AM17 AN26 AH29 AK29 AL29 AM25 AM26 AL28 AK28 AM28 AP29 AL31 AN32 AP28 AN28 AN31 AM31 AR34 AM32 AL33 AL35 AP32 AP33 AM35 AL32 AJ35 AJ31 AH32 AH33 AJ34 AL34 AJ33 AJ32

AM11 AL14 AN16 AJ29 AP31 AM34 AJ30

AP5 AP7 AR8 AP8 AR4 AR5 AM8 AN8

AR7

MEM_A_DQ<63>

28 70

BI

MEM_A_DQ<62>

28 70

BI

MEM_A_DQ<61>

28 70

BI

MEM_A_DQ<60>

28 70

BI

MEM_A_DQ<59>

28 70

D

C

B

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

OUT

28 70

OUT

28 70

OUT

28 70

OUT

28 70

OUT

28 70

OUT

28 70

OUT

28 70

OUT

MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0>

MEM_A_DM<7> MEM_A_DM<6> MEM_A_DM<5> MEM_A_DM<4> MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>

MRAS0* MCAS0*

MWE0*

MBA0_2 MBA0_1 MBA0_0

MA0_15 MA0_14 MA0_13 MA0_12 MA0_11 MA0_10

MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0

MCS0A_1* MCS0A_0*

MODT0A_1 MODT0A_0

MCKE0A_1 MCKE0A_0

AN7 AM7 AN10 AM10 AN13 AM13 AL16 AK16 AH28 AJ28 AM29 AN29 AP34 AP35 AH31 AG31

AN19 AL19 AL20

AL25 AN20 AM19

AK26 AK25 AJ20 AJ26 AH25 AM20 AH26 AN23 AJ25 AM22 AM23 AN22 AL23 AK22 AK23 AL22

AF24 AG25

AF25 AG26

AF26 AG28

AC26 AD26 AE26 AF27

AH23 AJ23

AJ22 AH22

AH19 AK20

AH20 AK19

AL26 AN25

MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0>

MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_BA<2> MEM_A_BA<1> MEM_A_BA<0>

MEM_A_A<15> MEM_A_A<14> MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0>

=PP1V05_S0_MCP_M2CLK_DLL

PP1V05_S0_MCP_PLL_FSBMEM

20 mA

25 mA

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CS_L<1> MEM_A_CS_L<0>

MEM_A_ODT<1> MEM_A_ODT<0>

MEM_A_CKE<1> MEM_A_CKE<0>

AR10

AP10

AT10 AU10 AR13 AR14 AR11 AP11 AT11 AP13 AV14 AU14 AR17 AP17 AP14 AT13 AP16 AR16 AU26 AT26 AU29 AT29 AV25 AV26 AV28 AV29 AT31 AR32 AT34 AU34 AR29 AR31 AU32 AT32 AV35 AT35 AR37 AP38 AV34 AU35 AR36 AR38 AM36 AM37 AJ36 AL36 AP37 AP36 AJ38 AJ37

AV10 AT14 AR28 AV32 AT37 AM38

AG23 AG22

AP1 AR3 AV4 AU4 AP3 AP2 AU3 AT4 AT5 AT7 AU8

AV5 AU5

AT8

AT2 AU7

MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0

MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0

MEM_COMP_GND MEM_COMP_VDD

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70 27 70

OUT OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

26 70

OUT

8

70 mA

OUT OUT

23

26 70

21 26 70

23

=PP1V5R1V35_SW_MCP_MEM

20 21 23

1

R1510

40.2

1% 1/16W MF-LF

402

2

1

R1511

40.2

1% 1/16W MF-LF

402

2

550 mA

MEM_B_DQ<63>

28 70

BI

MEM_B_DQ<62>

28 70

BI

MEM_B_DQ<61>

28 70

BI

MEM_B_DQ<60>

28 70

BI

MEM_B_DQ<59>

28 70

BI

MEM_B_DQ<58>

28 70

BI

MEM_B_DQ<57>

28 70

BI

MEM_B_DQ<56>

28 70

BI

MEM_B_DQ<55>

28 70

BI

MEM_B_DQ<54>

28 70

BI

MEM_B_DQ<53>

28 70

BI

MEM_B_DQ<52>

28 70

BI

MEM_B_DQ<51>

28 70

BI

MEM_B_DQ<50>

28 70

BI

MEM_B_DQ<49>

28 70

BI

MEM_B_DQ<48>

28 70

BI

MEM_B_DQ<47>

28 70

BI

MEM_B_DQ<46>

28 70

BI

MEM_B_DQ<45>

28 70

BI

MEM_B_DQ<44>

28 70

BI

MEM_B_DQ<43>

28 70

BI

MEM_B_DQ<42>

28 70

BI

MEM_B_DQ<41>

28 70

BI

MEM_B_DQ<40>

28 70

BI

MEM_B_DQ<39>

28 70

BI

MEM_B_DQ<38>

28 70

BI

MEM_B_DQ<37>

28 70

BI

MEM_B_DQ<36>

28 70

BI

MEM_B_DQ<35>

28 70

BI

MEM_B_DQ<34>

28 70

BI

MEM_B_DQ<33>

28 70

BI

MEM_B_DQ<32>

28 70

BI

MEM_B_DQ<31>

28 70

BI

MEM_B_DQ<30>

28 70

BI

MEM_B_DQ<29>

28 70

BI

MEM_B_DQ<28>

28 70

BI

MEM_B_DQ<27>

28 70

BI

MEM_B_DQ<26>

28 70

BI

MEM_B_DQ<25>

28 70

BI

MEM_B_DQ<24>

28 70

BI

MEM_B_DQ<23>

28 70

BI

MEM_B_DQ<22>

28 70

BI

MEM_B_DQ<21>

28 70

BI

MEM_B_DQ<20>

28 70

BI

MEM_B_DQ<19>

28 70

BI

MEM_B_DQ<18>

28 70

BI

MEM_B_DQ<17>

28 70

BI

MEM_B_DQ<16>

28 70

BI

MEM_B_DQ<15>

28 70

BI

MEM_B_DQ<14>

28 70

BI

MEM_B_DQ<13>

28 70

BI

MEM_B_DQ<12>

28 70

BI

MEM_B_DQ<11>

28 70

BI

MEM_B_DQ<10>

28 70

BI

MEM_B_DQ<9>

28 70

BI

MEM_B_DQ<8>

28 70

BI

MEM_B_DQ<7>

28 70

BI

MEM_B_DQ<6>

28 70

BI

MEM_B_DQ<5>

28 70

BI

MEM_B_DQ<4>

28 70

BI

MEM_B_DQ<3>

28 70

BI

MEM_B_DQ<2>

28 70

BI

MEM_B_DQ<1>

28 70

BI

MEM_B_DQ<0>

28 70

BI

MEM_B_DM<7>

28 70

OUT

MEM_B_DM<6>

28 70

OUT

MEM_B_DM<5>

28 70

OUT

MEM_B_DM<4>

28 70

OUT

MEM_B_DM<3>

28 70

OUT

MEM_B_DM<2>

28 70

OUT

MEM_B_DM<1>

28 70

OUT

MEM_B_DM<0>

28 70

OUT

MCP_MEM_COMP_GND

70

MCP_MEM_COMP_VDD

70

OMIT

U1400

MCP89M-A01

FBGA

(3 OF 11)

MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1* MCAS1*

MWE1*

MBA1_2 MBA1_1 MBA1_0

MA1_15 MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6

MEMORY PARTITION 1

MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MRESET0*

MCLK1A_1_P MCLK1A_1_N

MCLK1A_0_P MCLK1A_0_N

MCS1A_1* MCS1A_0*

MODT1A_1 MODT1A_0

MCKE1A_1 MCKE1A_0

AR2 AR1 AV7 AV8 AU11 AV11 AU13 AV13 AT28 AU28 AU31 AV31 AU36 AT36 AL38 AL37

AR19 AU17 AT17

AR25 AT19 AR20

AP26 AR26 AV16 AP25 AT23 AP20 AU23 AV22 AV23 AT22 AU22 AP23 AR23 AP22 AR22 AT20

AP4

AU20 AV20

AU19 AV19

AU16 AP19

AT16 AV17

AU25 AT25

MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>

MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>

MEM_B_A<15> MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>

=PP1V5R1V35_S3_MCP_MEM

1

R1520

1K

5% 1/16W MF-LF 402

2

MEM_RESET_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_CS_L<1> MEM_B_CS_L<0>

MEM_B_ODT<1> MEM_B_ODT<0>

MEM_B_CKE<1> MEM_B_CKE<0>

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

28 70

BI

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

8

26 27

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

27 70

OUT

21 27 70

OUT

21 27 70

OUT

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Memory Interface

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

15 OF 109

SHEET

15 OF 76

36

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

PEG_CLKREQ_L

9

IN

AP_CLKREQ_L

30

D

C

IN

ENET_CLKREQ_L

9

IN

FW_CLKREQ_L

9

IN

FW_PWR_EN

9

OUT

FW_PME_L

9

IN

PCIE_WAKE_L

7

30

IN

=PEG_D2R_P<0>

9

IN

=PEG_D2R_N<0>

9

IN

=PEG_D2R_P<1>

9

IN

=PEG_D2R_N<1>

9

IN

=PEG_D2R_P<2>

9

IN

=PEG_D2R_N<2>

9

IN

=PEG_D2R_P<3>

9

IN

=PEG_D2R_N<3>

9

IN

TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN

PCIE_FW_D2R_P

9

71

IN

PCIE_FW_D2R_N

9

71

IN

PCIE_AP_D2R_P

9

71

IN

PCIE_AP_D2R_N

9

71

IN

PCIE_ENET_D2R_P

9

71

IN

PCIE_ENET_D2R_N

9

71

IN

PP3V3_S0_MCP_PLL_HVDD

23

50 mA

PP1V05_S0_MCP_PLL_PEXSATA

23

325 mA

100 mA

80 mA

120 mA

25 mA

W4

PEA_CLKREQ*/GPIO_49

(IPU)

W5

PEB_CLKREQ*/GPIO_50

(IPU)

W7

PEC_CLKREQ*/GPIO_51

(IPU)

W8

PED_CLKREQ*/GPIO_52

(IPU)

W6

PEE_CLKREQ*/GPIO_53

(IPU)

W9

PEF_CLKREQ*/GPIO_54

(IPU)

U3

PE_WAKE*

(IPU-S5)

AC1

PE0_RX0_P

AB1

PE0_RX0_N

AC5

PE0_RX1_P

AC4

PE0_RX1_N

AC10

PE0_RX2_P

AC11

PE0_RX2_N

AB7

PE0_RX3_P

AB6

PE0_RX3_N

AB9

PE0_RX4_P

AB8

PE0_RX4_N

Y2

PE0_RX5_P

Y3

PE0_RX5_N

AB11

PE1_RX0_P

AB10

PE1_RX0_N

Y10

PE1_RX1_P

Y11

PE1_RX1_N

V11

+3.3V_PLL_HVDD_1

V13

+3.3V_PLL_HVDD_2

AH10

+VIO_PLL_PE

AG11

+VIO_PLL_XREF_XS_1

AF12

+VIO_PLL_XREF_XS_2

AF13

+VIO_PLL_XREF_XS_3

AH8

+VIO_PLL_SATA_1

AH9

+VIO_PLL_SATA_2

AH11

+VIO_PLL_H

(4 OF 11)

PE0_REFCLK_P PE0_REFCLK_N

PE1_REFCLK_P PE1_REFCLK_N

PE2_REFCLK_P PE2_REFCLK_N

PE3_REFCLK_P PE3_REFCLK_N

PE4_REFCLK_P PE4_REFCLK_N

PE5_REFCLK_P PE5_REFCLK_N

PCI EXPRESS

(IPD)

PE0_TX0_P PE0_TX0_N

PE0_TX1_P PE0_TX1_N

PE0_TX2_P PE0_TX2_N

PE0_TX3_P PE0_TX3_N

PE0_TX4_P PE0_TX4_N

PE0_TX5_P PE0_TX5_N

PE1_TX0_P PE1_TX0_N

PE1_TX1_P PE1_TX1_N

PEX_RST*

PEX0_TERM_P

B

Y1 W1

W3 W2

U4 U5

U7 U6

U9 U8

W10 W11

AC3 AC2

AB2 AB3

AC6 AC7

AC8 AC9

AB4 AB5

Y5 Y4

Y7 Y6

Y9 Y8

U1

U2

PEG_CLK100M_P PEG_CLK100M_N

PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N

PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N

TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N

=PEG_R2D_C_P<0> =PEG_R2D_C_N<0>

=PEG_R2D_C_P<1> =PEG_R2D_C_N<1>

=PEG_R2D_C_P<2> =PEG_R2D_C_N<2>

=PEG_R2D_C_P<3> =PEG_R2D_C_N<3>

TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN

PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N

PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N

PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N

PCIE_RESET_L

NO STUFF

1

R1600

10K

5% 1/16W MF-LF 402

2

MCP_PEX0_TERMP

71

PLACE_NEAR=U1400.U2:12.7 mm

R1610

2.49K

1/16W MF-LF

9

71

OUT

9

71

OUT

9

71

OUT

9

71

OUT

9

71

OUT

9

71

OUT

9

71

OUT

9

71

OUT

PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1 PE1 ports are Gen1-only. 2 RCs: x1, x1

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

71

OUT

9

71

OUT

71

9

OUT

9

71

OUT

9

71

OUT

9

71

OUT

25

OUT

1

1%

402

2

If PE0[3:0] are not used, +VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND

If PE0[4:5] and PE1[0:1] are not used, +VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP PCIe Interfaces

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

16 OF 109

SHEET

16 OF 76

36

345678

2 1

OMIT

D

PP3V3_S0_MCP_DAC

24

140 mA

TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF

DP_IG_ML0_P<3>

9

OUT

DP_IG_ML0_N<3>

9

OUT

DP_IG_ML0_P<2>

9

OUT

DP_IG_ML0_N<2>

9

OUT

DP_IG_ML0_P<1>

9

OUT

DP_IG_ML0_N<1>

9

OUT

DP_IG_ML0_P<0>

9

OUT

DP_IG_ML0_N<0>

9

OUT

DP_IG_ML1_P<3>

9

OUT

DP_IG_ML1_N<3>

9

OUT

DP_IG_ML1_P<2>

9

OUT

DP_IG_ML1_N<2>

9

C

NOTE: 100K pull-downs required if HPLUG_DET0/HPLUG_DET1 are not used.

OUT

DP_IG_ML1_P<1>

9

OUT

DP_IG_ML1_N<1>

9

OUT

DP_IG_ML1_P<0>

9

OUT

DP_IG_ML1_N<0>

9

OUT

DP_IG_HPD0

9

IN

DP_IG_HPD1

9

IN

SATARDRVR_A_EN

17

OUT

DP_IG_AUX_CH0_P

9

17

BI

DP_IG_AUX_CH0_N

17

9

BI

DP_IG_AUX_CH1_P

9

BI

DP_IG_AUX_CH1_N

9

BI

PP3V3_S0_MCP_PLL_DP_USB

23

210 mA

180 mA

30 mA

=PP1V05_S0_MCP_PLL_IFP

8

24

60 mA

PP1V05_S0_MCP_PLL_CORE

23

160 mA

B

=PP3V3R1V8_S0_MCP_IFP_VDD

8

24

180 mA

=PP1V05_S0_MCP_DP0_VDD

8

24

160 mA

40 mA 60 mA

40 mA 20 mA

B29

+3.3V_RGBDAC

C29

RGB_DAC_RSET

D29

RGB_DAC_VREF

D26

DP0_3_P/TMDS0_TXC_P

E26

DP0_3_N/TMDS0_TXC_N

G26

DP0_2_P/TMDS0_TX0_P

F26

DP0_2_N/TMDS0_TX0_N

F25

DP0_1_P/TMDS0_TX1_P

G25

DP0_1_N/TMDS0_TX1_N

E25

DP0_0_P/TMDS0_TX2_P

D25

DP0_0_N/TMDS0_TX2_N

F28

DP1_3_P/TMDS0B_TXC_P

G28

DP1_3_N/TMDS0B_TXC_N

E28

DP1_2_P/TMDS0_TX3_P

D28

DP1_2_N/TMDS0_TX3_N

A28

DP1_1_P/TMDS0_TX4_P

A29

DP1_1_N/TMDS0_TX4_N

C28

DP1_0_P/TMDS0_TX5_P

B28

DP1_0_N/TMDS0_TX5_N

H26

HPLUG_DET0/GPIO_20

J26

HPLUG_DET1/GPIO_21

J25

HPLUG_DET2/GPIO_22

L28

DDC_CLK2/DP_AUX_CH0_P

K28

DDC_DATA2/DP_AUX_CH0_N

K25

DDC_CLK3/DP_AUX_CH1_P

K26

DDC_DATA3/DP_AUX_CH1_N

M23

+3.3V_PLL_DP0_1

N22

+3.3V_PLL_DP0_2

N21

+3.3V_PLL_USB_1

M22

+3.3V_PLL_USB_2

N23

+VIO_PLL_IFPAB_1

L24

+VIO_PLL_IFPAB_2

M25

+VIO_PLL_CORE_LEG

N25

+VIO_PLL_SPPLL0_1

L26

+VIO_PLL_SPPLL0_2

M26

+VIO_PLL_V

N24

+VIO_PLL_NV_1

L25

+VIO_PLL_NV_2

A22

+VDD_IFPA

A23

+VDD_IFPB

A26

+VIO_DP0_1

B26

+VIO_DP0_2

C26

+VIO_DP0_3

U1400

MCP89M-A01

FBGA

(5 OF 11)

RGB

LCD_BKL_CTL/GPIO_57

LCD_PANEL_PWR/GPIO_58

DDC_CLK0/GPIO_38

DDC_DATA0/GPIO_39

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

IFPA_TXC_P IFPA_TXC_N

IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N

FLAT PANEL

IFPB_TXD7_P IFPB_TXD7_N

DDC_CLK1/GPIO_40

DDC_DATA1/GPIO_41

LCD_BKL_ON/GPIO_59

IFPAB_VPROBE

IFPAB_RSET

TMDS0_VPROBE

TMDS0_RSET

F29 H25

C31 B31 A31

D31 E31

K22 L22

C22 B22 E22 D22 F22 G22 H22 J22

B23 C23

L23 K23 J23 H23 G23 F23 D23 E23

J28 G29

A25 B25 C25

L20

K20

H28

F31

AUD_IP_PERIPHERAL_DET MIKEY_MIC_LOAD_DET

TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC

=MCP_IFPA_TXC_P =MCP_IFPA_TXC_N

=MCP_IFPA_TXD_P<0> =MCP_IFPA_TXD_N<0> =MCP_IFPA_TXD_P<1> =MCP_IFPA_TXD_N<1> =MCP_IFPA_TXD_P<2> =MCP_IFPA_TXD_N<2> =MCP_IFPA_TXD_P<3> =MCP_IFPA_TXD_N<3>

=MCP_IFPB_TXC_P =MCP_IFPB_TXC_N

=MCP_IFPB_TXD_P<0> =MCP_IFPB_TXD_N<0> =MCP_IFPB_TXD_P<1> =MCP_IFPB_TXD_N<1> =MCP_IFPB_TXD_P<2> =MCP_IFPB_TXD_N<2> =MCP_IFPB_TXD_P<3> =MCP_IFPB_TXD_N<3>

=MCP_IFPAB_DDC_CLK =MCP_IFPAB_DDC_DATA

(GMUX_INT) LCD_IG_BKLT_PWM LCD_IG_BKLT_EN LCD_IG_PWR_EN

MCP_IFPAB_VPROBE MCP_IFPAB_RSET

MCP_TMDS0_VPROBE MCP_TMDS0_RSET

17 53

IN

17

IN

RGB DAC Disable: Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs). Connect +3.3V_RGBDAC pin to GND.

NOTE: No Composite/S-Video/Component Video support on MCP89

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

BI

9

OUT

9

OUT

9

OUT

24 71

OUT

24 71

OUT

24 71

OUT

24 71

OUT

MCP Signal =MCP_IFPA_TXC_P/N

=MCP_IFPA_TXD_P/N<0> =MCP_IFPA_TXD_P/N<1> =MCP_IFPA_TXD_P/N<2> =MCP_IFPA_TXD_P/N<3> =MCP_IFPB_TXC_P/N =MCP_IFPB_TXD_P/N<0> =MCP_IFPB_TXD_P/N<1> =MCP_IFPB_TXD_P/N<2> =MCP_IFPB_TXD_P/N<3> =MCP_IFPAB_DDC_CLK =MCP_IFPAB_DDC_DATA

LVDS: Power +VDD_IFPx at 1.8V TMDS: Power +VDD_IFPx at 3.3V

TMDS/HDMI TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0> TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2> (UNUSED) (UNUSED) TMDS_IG_TXD_P/N<3> TMDS_IG_TXD_P/N<4> TMDS_IG_TXD_P/N<5> (UNUSED) TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA

NOTE: TMDS/HDMI not supported on IFPA/B for MCP89 A01.

Interface Mode

LVDS LVDS_IG_A_CLK_P/N

LVDS_IG_A_DATA_P/N<0> LVDS_IG_A_DATA_P/N<1> LVDS_IG_A_DATA_P/N<2> LVDS_IG_A_DATA_P/N<3> LVDS_IG_B_CLK_P/N LVDS_IG_B_DATA_P/N<0> LVDS_IG_B_DATA_P/N<1> LVDS_IG_B_DATA_P/N<2> LVDS_IG_B_DATA_P/N<3> LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA

D

C

B

DDC Mode Pull-downs

NOTE: DP_AUX_CH1 also requires pull-downs if used for dual-mode DisplayPort (DP++). If unused no pulls are necessary, if used for TMDS/HDMI only then only pull-ups are necessary.

100K 100K

1 2 1 2

5% 5%

1/16W

MF-LF

1/16W

DP_IG_AUX_CH0_P

402

DP_IG_AUX_CH0_N

402

9

17

9

17

R1710 R1711

A

GPIO Pull-Ups

=PP3V3_S0_MCP_GPIO

10K

R1780 R1781 R1782

10K 10K

1 2 1 2 1 2

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

8

18 19

MF-LF

1/16W

5% 5% 5%

1/16W 1/16W

MF-LF MF-LF

SATARDRVR_A_EN

402

AUD_IP_PERIPHERAL_DET

402

MIKEY_MIC_LOAD_DET

402

17

17 53

17

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Graphics

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

17 OF 109

SHEET

17 OF 76

36

345678

2 1

OMIT

U1400

MCP89M-A01

FBGA

SATA_HDD_R2D_C_P

33 71

OUT

SATA_HDD_R2D_C_N

33 71

OUT

SATA_HDD_D2R_N

33 71

IN

SATA_HDD_D2R_P

33 71

D

=PP3V3_S0_MCP_GPIO

8

17 19

1

R1800

100K

5% 1/16W MF-LF

R1810

49.9

1/16W MF-LF

402

2

1

1%

402

2

C

MXM_GOOD_L

=PP3V3_ENET_MCP_RMGT

8 9

20 23

B

1

R1811

49.9

1% 1/16W MF-LF

402

2

IN

SATA_ODD_R2D_C_P

33 71

OUT

SATA_ODD_R2D_C_N

33 71

OUT

SATA_ODD_D2R_N

33 71

IN

SATA_ODD_D2R_P

33 71

IN

TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN

TP_SATA_C_D2RN TP_SATA_C_D2RP

TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN

TP_SATA_D_D2RN TP_SATA_D_D2RP

MCP_SATA_TERMP

71

1

R1805

2.49K

1% 1/16W MF-LF 402

2

ENET_RXD<0>

31 73

IN

ENET_RXD<1>

31 73

IN

ENET_RXD<2>

31 73

IN

ENET_RXD<3>

31 73

IN

ENET_CLK125M_RXCLK

31 73

IN

ENET_RX_CTRL

31 73

IN

ENET_ENERGY_DET

9

IN

PP3V3_ENET_MCP_PLL_MAC

23

20 mA

MCP_MII_COMP_VDD

73

MCP_MII_COMP_GND

73

AH4

SATA_A0_TX_P

AH5

SATA_A0_TX_N

AJ4

SATA_A0_RX_N

AJ5

SATA_A0_RX_P

AJ3

SATA_A1_TX_P

AJ2

SATA_A1_TX_N

AH2

SATA_A1_RX_N

AH3

SATA_A1_RX_P

AJ6

SATA_B0_TX_P

AJ7

SATA_B0_TX_N

AH7

SATA_B0_RX_N

AH6

SATA_B0_RX_P

AL4

SATA_B1_TX_P

AL3

SATA_B1_TX_N

AL1

SATA_B1_RX_N

AL2

SATA_B1_RX_P

AH1

SATA_LED*/GPIO_30

AJ1

SATA_TERMP

G4

NC_1

NC

E7

NC_2

NC

F7

NC_3

NC

F4

NC_4

NC

B14

RGMII_RXD0

C14

RGMII_RXD1

D16

RGMII_RXD2

F16

RGMII_RXD3

E16

RGMII_RXCLK

A14

RGMII_RXCTL

H14

RGMII_INTR/GPIO_35

M16

+3.3V_PLL_MAC_DUAL

D13

RGMII_COMP_VDD

E13

RGMII_COMP_GND

Internal MAC Disable: Connect RGMII_RXD<0:3> together to 10K pull-down.

Connect RGMII_RXCLK to 10K pull-down. Connect RGMII_RXCTL to 10K pull-down. Connect RGMII_INTR to 10K pull-down (if not used as GPIO). +3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail. RGMII_COMP_VDD/_GND must remain connected as shown. Connect RGMII_VREF to 10K pull-down. Connect RGMII_MDIO to 10K pull-down. All other pins can be left TP or NC.

(6 OF 11)

USB

SATA

Internal 19.5K Pull-Downs on all USB pairs

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

USB_OC0*/GPIO_25

USB_OC1*/GPIO_26 USB_OC2*/GPIO_27_MGPIO_0 USB_OC3*/GPIO_28_MGPIO_1

USB_RBIAS_GND

RGMII_TXCLK RGMII_TXCTL

LAN

RGMII_RESET*

USB0_N USB0_P

USB1_P USB1_N

USB2_P USB2_N

USB3_P USB3_N

OHCI0/EHCI0OHCI1/EHCI1

USB4_P USB4_N

USB5_P USB5_N

USB6_P USB6_N

USB7_P USB7_N

USB8_P USB8_N

USB9_P USB9_N

USB10_P USB10_N

USB11_N USB11_P

RGMII_VREF

RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3

RGMII_MDC

RGMII_MDIO

BUF_25MHZ

External A

C20 B20

J20 H20

C19 B19

G20 F20

E20 D20

E19 D19

G19 F19

J17 H17

J19 H19

C17 B17

E17 D17

G17 F17

A17 L17 K17 K19

L19

C13

G13 H13 F14 D14

G14 E14

F13 K13

J13

J14

USB_EXTA_N USB_EXTA_P

AirPort (PCIe Mini-Card)

USB_MINI_P USB_MINI_N

T57

USB_T57_P USB_T57_N

External C

USB_EXTC_P USB_EXTC_N

Watermelon

USB_WM_P USB_WM_N

Camera/External E

USB_CAMERA_P USB_CAMERA_N

SD Card/ExpressCard

USB_SDCARD_P USB_SDCARD_N

External D

USB_EXTD_P USB_EXTD_N

Geyser Trackpad/Keyboard

USB_TPAD_P USB_TPAD_N

External B

USB_EXTB_P USB_EXTB_N

IR

USB_IR_P USB_IR_N

Bluetooth

USB_BT_N USB_BT_P

MCP_USB_RBIAS_GND

72

MCP_RGMII_VREF

TP_ENET_TXD<0> TP_ENET_TXD<1> TP_ENET_TXD<2> TP_ENET_TXD<3>

TP_ENET_CLK125M_TXCLK TP_ENET_TX_CTRL

TP_ENET_MDC ENET_MDIO

TP_MCP_CLK25M_BUF0_R

TP_ENET_RESET_L

34 72

BI

34 72

BI

9

72

BI

9

72

BI

9

72

BI

9

72

BI

9

72

BI

9

72

BI

9

72

BI

9

72

BI

64 72

BI

64 72

BI

9

72

BI

9

72

BI

9

72

BI

9

72

BI

43 72

BI

43 72

BI

34 72

BI

34 72

BI

9

72

BI

9

72

BI

30 72

BI

30 72

BI

9

IN

9

BI

9

31 73

R1850

8.2K

1/16W MF-LF

1

R1851

8.2K

5% 1/16W MF-LF 402

2

1

R1852

5%

402

2

8.2K

1/16W MF-LF

=PP3V3_S5_MCP_GPIO

1

R1853

8.2K

5% 1/16W MF-LF 402

2

1

5%

402

2

USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L USB_EXTD_OC_L

1

R1860

887

1% 1/16W MF-LF 402

2

34

OC2# Also for EXTE OC3# Also for EXCARD

8

19

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP SATA, USB & Ethernet

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

BRANCH

PAGE

18 OF 109

SHEET

18 OF 76

C.0.0

36

345678

2 1

=PP3V3R1V5_S0_MCP_HDA

8

D

C

HDA Output Caps

For EMI Reduction on HDA interface

HDA_SDOUT_R HDA_BIT_CLK_R

HDA_RST_R_L HDA_SYNC_R

B

C1950

10PF

CERM

1

5%

50V

2

402

1

2

C1952

10PF

CERM

C1951

10PF

5% 50V CERM 402

1

5%

50V

2

402

1

C1953

10PF

5% 50V

2

CERM 402

GPIO Pull-Ups/Downs

=PP3V3_S5_MCP_GPIO =PP3V3_S3_MCP_GPIO =PP3V3_S0_MCP_GPIO

R1980 R1981 R1999 R1986

R1983 R1984 R1985 R1987

R1988 R1989 R1990

A

R1991 R1992

R1993 R1994 R1995

R1996 R1997 R1998

10K

10K 100K 100K

10K

10K 100K 100K

10K

10K 100K

100K 100K 100K

10K 100K

20K

1 2 1 2

1 2

1 2 1 2 1 2 1 2

1 2

23

70 mA

LPC_AD<0>

35 37 72

BI

LPC_AD<1>

35 37 72

BI

LPC_AD<2>

35 37 72

BI

LPC_AD<3>

35 37 72

BI

NOTE: MCP89 A01 has strong (~10K) pull-downs on these pins.

19 72

8

18

8

17 18 19

1/16W5%MF-LF

5%

1/16W

MF-LF MF-LF

1/16W

5% 5%

1/16W

MF-LF

5% 5% 5% 5%

5% 5% 402 5%

5% 402 5% 402 5% 402

5%

MF-LF1/16W MF-LF1/16W MF-LF1/16W MF-LF

1/16W

1/16W MF-LF

MF-LF

1/16W

MF-LF1/16W

1/16W

MF-LF

MF-LF1/16W MF-LF1/16W MF-LF1/16W

1/16W MF-LF

MF-LF

1/16W

MF-LF

1/16W

1/16W MF-LF

R1910 R1911 R1912 R1913

PP3V3_G3_RTC

7 8

20 23

SDCARD_RESET

402

T57_RESET

402

GFXVCORE_PWR_EN

402

SPIROM_USE_MLB

402

MCP_CPU_VTT_EN_L

402

MLB_RAM_VENDOR

402

T57_PWR_EN

402

LPCPLUS_GPIO

402

ODD_PWR_EN_L

4025%

MEM_EVENT_L

402

ENET_LOW_PWR SMC_IG_THROTTLE_L

402

MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3>

4025%

AP_PWR_EN

402

ARB_DETECT_L

402

SPI_MISO

4025%

22

22 22

R1920

49.9K

1/16W MF-LF

1%

402

R1900

49.9

1/16W MF-LF

1 2 1 2 1 2 1 2

121

2

1

1%

402

2

5% 5%221/16W MF-LF 5% 5%

R1921

49.9K

1% 1/16W MF-LF 402

19

19 22

7

19 37 47

19

7

19 37

19 33

19 26 27 35

19

19 36

19 59

19 30 62

19

7

19 37 72

HDA_SDIN0

48 72

IN

AUD_IPHS_SWITCH_EN

53

OUT

Output limited to +VDD_HDA. Confirmed OK for this signal.

72

MCP_HDA_PULLDN_COMP

402 402 402 402

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

MF-LF1/16W

MF-LF1/16W MF-LF1/16W

TP_MLB_RAM_SIZE

PM_CLKRUN_L

35 37 25 72

IN

SMC_WAKE_SCI_L

35

IN

PM_LATRIGGER_L

13

OUT

AUD_I2C_INT_L

53

IN

SMC_RUNTIME_SCI_L

35

IN

PM_PWRBTN_L

35

IN

PM_SYSRST_DEBOUNCE_L

25

IN

RTC_RST_L

PM_RSMRST_L

35

IN

MCP_PS_PWRGD

25

IN

MCP_WAKE_REQ_L

36

OUT

PM_BATLOW_L

35

IN

MCP_MEM_VDD_EN

21 62

OUT

MCP_MEM_VTT_EN

21

OUT

SM_INTRUDER_L

SMC_IG_THROTTLE_L

19 36

OUT

T57_RESET

19

OUT

GFXVCORE_PWR_EN

19 22

OUT

SPIROM_USE_MLB

7

19 37 47

BI

JTAG_MCP_TDI

13

IN

JTAG_MCP_TDO

13

OUT

JTAG_MCP_TMS

13

IN

JTAG_MCP_TRST_L

13

IN

JTAG_MCP_TCK

13

IN

MCP_CLK25M_XTALIN

25

IN

MCP_CLK25M_XTALOUT

25

OUT

RTC_CLK32K_XTALIN

25

IN

RTC_CLK32K_XTALOUT

25

OUT

121

R1930

10K

5% 1/16W MF-LF

402

D6

70 mA

R1931

100K

5% 1/16W MF-LF 402

2

+VDD_HDA

E2

HDA_SDATA_IN0

(IPD)

E3

HDA_SDATA_IN1/GPIO_2

(IPD)

D3

HDA_PULLDN_COMP

K1

LPC_AD0

L1

LPC_AD1

L2

LPC_AD2

L3

LPC_AD3

K2

LPC_DRQ0*/GPIO_43

(IPU)

L6

LPC_CLKRUN*/GPIO_42

D11

SIO_PME*/GPIO_31

G11

EXT_SMI*/GPIO_32

B3

A20GATE/GPIO_55

H2

KBRDRSTIN*/GPIO_56

J10

PWRBTN*

F10

RSTBTN*

G16

RTC_RST*

C11

PWRGD_SB

C2

PWRGD

H16

MCP_WAKE_REQ*

A7

MCP_WAKE_DIS*

(IPU-S5)

B7

MCP_MEMVDD_EN/GPIO_44

G10

MEMVTT_EN/GPIO_45

J16

INTRUDER*

G5

MGPU_PIO0/GPIO_6

H5

MGPU_PIO1/GPIO_7

H10

MGPU_PIO2/GPIO_23

J11

MGPU_PIO3/GPIO_24

C10

JTAG_TDI

D10

JTAG_TDO

B10

JTAG_TMS

E10

JTAG_TRST*

A10

JTAG_TCK

A11

XTALIN

B11

XTALOUT

B16

XTALIN_RTC

C16

XTALOUT_RTC

Platform-Specific Connections

LPC_RESET_L

IN

PM_SLP_S4_L

7

19 35 36 62 35

IN

MAKE_BASE=TRUE

NOTE: MCP SLP_S5# signal has the behavior of Intel’s SLP_S4# signal.

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

(IPU) (IPU) (IPU) (IPU)

(IPU-S5) (IPU-S5)

(IPU)

(IPD)

OMIT

U1400

MCP89M-A01

FBGA

(7 OF 11)

HDA

(IPU)

(IPU-S5)

MISC_VDDEN0/GPIO_47 MISC_VDDEN1/GPIO_48

(IPU)

MISC_VDDEN2/GPIO_17 MISC_VDDEN3/GPIO_18 MISC_VDDEN4/GPIO_19 MEM_VDD_SEL/GPIO_46

FANRPM0/GPIO_60/MGPIO_2

FANRPM1/GPIO_63/MGPIO_3

MISC LPC

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

BUF_SIO_CLK/GPIO_33

R1965

33

1 2

5% 1/16W MF-LF

402

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

LPC_SERIRQ

(IPU)

LPC_FRAME*

LPC_RESET*

(IPD)

LPC_CLK0

FANCTL0/GPIO_61

FANCTL1/GPIO_62

SLP_S3*

(IPD)

SLP_RMGT*

(IPD)

SLP_S5*

(IPD)

MCP_VID0/GPIO_13 MCP_VID1/GPIO_14 MCP_VID2/GPIO_15 MCP_VID3/GPIO_16

SPI_CS0*/GPIO_10

SPI_CLK/GPIO_11

SPI_DI/GPIO_08 SPI_DO/GPIO_09

SPKR/GPIO_1

THERM_DIODE_P THERM_DIODE_N

SMB_CLK0

SMB_DATA0

SUS_CLK/GPIO_34

TEST_MODE_EN

PKG_TEST

PKG_TEST2

LPC_PWRDWN_L

PM_SLP_S5_L

E1

E4

D1

D2

L8

L7

K7

L5

K10 C8 A8 D8 G8 C7

H7 H6 G6 H4

C4 K9 D5

K3 K4 K5 K6

E11 D7 F11 B8

H3

G3 G2

A4 B4 A5 B5 C5

H1

H11

D4 L16 K16

=PP3V3_S0_MCP_GPIO

2

R1961

10K

5% 1/16W MF-LF 402

1

HDA_SDOUT_R

19 72

HDA_BIT_CLK_R

19 72

HDA_RST_R_L

19 72

HDA_SYNC_R

19 72

LPC_SERIRQ

LPC_FRAME_R_L

LPC_RESET_L LPC_CLK33M_SMC_R

MCP_CPU_VTT_EN_L MLB_RAM_VENDOR T57_PWR_EN SMC_ADAPTER_EN LPCPLUS_GPIO MCP_MEM_VDD_SEL_1V5

ODD_PWR_EN_L MEM_EVENT_L ENET_LOW_PWR SDCARD_RESET

PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L

MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3>

SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R

MCP_SPKR MCP_THMDIODE_P

MCP_THMDIODE_N SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN

ARB_DETECT_L PM_CLK32K_SUSCLK_R

8

17 18 19

R1951

22

1 2

5% 1/16W MF-LF

402

R1953

22

1 2

5% 1/16W MF-LF

402

19

BI

IN

BI

OUT

IN

OUT

IN

OUT OUT OUT

OUT OUT OUT OUT

OUT OUT

IN

OUT

OUT OUT

OUT

BI

OUT

BI

OUT

19

OUT

R1950

22

1 2

5% 1/16W MF-LF

402

R1952

22

1 2

5% 1/16W MF-LF

402

R1960

22

1 2

5%

1/16W MF-LF

402

19

35 36 62

7

19 37

9

19 33

19 26 27 35

19

7

35 62 66

62

7

19 35 36 62

19 59

37 72

7

19 37 72

37 72

41 75

13 38 72

38 72

19 30 62

25 72

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

HDA_SYNC

LPC_FRAME_L

NOTE: MCP89 A01 has strong (~10K) pull-downs on these pins.

OUT

1

R1970

10K

5% 1/16W MF-LF 402

2

48 72

OUT

48 72

OUT

48 72

OUT

48 72

OUT

7

35 37

BI

35 37 72

OUT

19 25 72

OUT

BUF_SIO_CLK Frequency

Frequency

24 MHz

14.31818 MHz

BIOS Boot Select

I/F LPC SPI

NOTE: MCP89 does not support FWH, only LPC ROMs. So Apple designs will not use LPC for BootROM override.

SPI Frequency Select

Frequency

25.0 MHz

31.2 MHz

42.7 MHz

62.5 MHz

NOTE: 42 & 62 MHz use FAST_READ command.

36

MCP_SPKR: 0 = USER mode (Normal boot mode)

1 = SAFE mode (For ROMSIP recovery) Connects to SMC for automatic recovery.

Straps not provided on this page.

HDA_SYNC

LPC_FRAME#

0 1

SPI_DO

SPI_CLK 0 0 1 1

D

1 0

C

0 1 0 1

B

MCP_TEST_MODE_EN

1

R1959

10K

5% 1/16W MF-LF 402

2

35 37 19 25 72

OUT

NO STUFF

1

R1966

10K

5% 1/16W MF-LF 402

2

1

R1975

1K

1% 1/16W MF-LF 402

2

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP HDA, LPC & MISC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

19 OF 109

SHEET

19 OF 76

SIZE

A

D

36

NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

OMIT

U1400

MCP89M-A01

=PP1V05_SW_MCP_FSB

8

23

D

=PP1V05_S0_MCP_FSB

8

14 23

200 mA

C

G32 K29 D32 L29 Y26 V26 P27 T27 J29 N27 P26 F32 A32 H29 W26 U27 G31 C32 E32 M28 H30 U26 T26 H31 B32 R26 N26

W27 W28 Y27 Y28

+VTT_CPU_1 +VTT_CPU_2 +VTT_CPU_3 +VTT_CPU_4 +VTT_CPU_5 +VTT_CPU_6 +VTT_CPU_7 +VTT_CPU_8 +VTT_CPU_9 +VTT_CPU_10 +VTT_CPU_11 +VTT_CPU_12 +VTT_CPU_13 +VTT_CPU_14 +VTT_CPU_15 +VTT_CPU_16 +VTT_CPU_17 +VTT_CPU_18 +VTT_CPU_19 +VTT_CPU_20 +VTT_CPU_21 +VTT_CPU_22 +VTT_CPU_23 +VTT_CPU_24 +VTT_CPU_25 +VTT_CPU_26 +VTT_CPU_27

+VTT_CPU2_1 +VTT_CPU2_2 +VTT_CPU2_3 +VTT_CPU2_4

FBGA

(8 OF 11)

+VDD_MEM_1 +VDD_MEM_2 +VDD_MEM_3 +VDD_MEM_4 +VDD_MEM_5 +VDD_MEM_6 +VDD_MEM_7 +VDD_MEM_8

+VDD_MEM_9 +VDD_MEM_10 +VDD_MEM_11 +VDD_MEM_12 +VDD_MEM_13 +VDD_MEM_14 +VDD_MEM_15 +VDD_MEM_16 +VDD_MEM_17 +VDD_MEM_18 +VDD_MEM_19

POWER I

+VDD_MEM_20 +VDD_MEM_21 +VDD_MEM_22 +VDD_MEM_23 +VDD_MEM_24 +VDD_MEM_25 +VDD_MEM_26 +VDD_MEM_27 +VDD_MEM_28 +VDD_MEM_29 +VDD_MEM_30 +VDD_MEM_31

=PP1V5R1V35_SW_MCP_MEM

AG14 AL7 AF18 AF21 AM1 AM4 AK8 AG13 AF16 AF22 AG20 AM5 AG19 AF23 AJ9 AF19 AG17 AL6 AG16 AH12 AM2 AF15 AM3 AL5 AL8 AF17 AJ11 AJ8 AF14 AJ10 AF20

4300 mA2000 mA

NOTE: VDD_COREx_SENSE signals should NOT be used for remote sensing unless COREA/COREB are powered by separate regulators. Instead connect regulator sense point as close to COREB FET as possible.

15 21 23

=PPVCORE_S0_MCP

8

23

8450 mA (0.85V)

TP_MCP_VDDCOREA_SENSEP TP_MCP_VDDCOREA_SENSEN

=PP1V05_S0_MCP_PE_DVDD0

8

200 mA (DVDD0 & DVDD1) (PE0[3:0])

Okay to GND if not using PE0[3:0]

=PP1V05_S0_MCP_PE_DVDD1

8

200 mA (DVDD0 & DVDD1) (PE0[5:4], PE1[1:0])

=PP1V05_S0_MCP_PE_AVDD0

8

500 mA (AVDD0 & AVDD1) (PE0[3:0])

Okay to GND if not using PE0[3:0]

=PP1V05_S0_MCP_PE_AVDD1

8

500 mA (AVDD0 & AVDD1) (PE0[5:4], PE1[1:0])

B

=PP3V3_S0_MCP_HVDD

8

23

30 mA

=PP3V3_S0_MCP

8

23

250 mA

=PP0V9_S5_MCP_VDD_AUXC

8

23

150 mA

PP3V3_G3_RTC

7 8

19 23

?? uA (G3) 5 mA (S0)

CKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2Gnd

CKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2GndCKPLUS_WAIVE=PwrTerm2Gnd

T3

+VDD_COREA_1

AB22

+VDD_COREA_2

AB20

+VDD_COREA_3

R13

+VDD_COREA_4

R7

+VDD_COREA_5

T6

+VDD_COREA_6

T13

+VDD_COREA_7

R11

+VDD_COREA_8

AB17

+VDD_COREA_9

R10

+VDD_COREA_10

AB18

+VDD_COREA_11

T1

+VDD_COREA_12

T2

+VDD_COREA_13

AB21

+VDD_COREA_14

R4

+VDD_COREA_15

AB19

+VDD_COREA_16

P13

+VDD_COREA_17

R2

+VDD_COREA_18

T8

+VDD_COREA_19

R8

+VDD_COREA_20

T4

+VDD_COREA_21

R5

+VDD_COREA_22

T7

+VDD_COREA_23

T5

+VDD_COREA_24

T9

+VDD_COREA_25

U22

+VDD_COREA_26

V22

+VDD_COREA_27

W22

+VDD_COREA_28

Y22

+VDD_COREA_29

AA22

+VDD_COREA_30

P12

+VDD_COREA_31

P10

+VDD_COREA_32

P11

+VDD_COREA_33

L10

+VDD_COREA_SENSE

L9

GND_COREA_SENSE

AF7

+VIO_PE_DVDD0_1

AF8

+VIO_PE_DVDD0_2

AE9

+VIO_PE_DVDD0_3

AE10

+VIO_PE_DVDD0_4

AE6

+VIO_PE_DVDD1_1

AE7

+VIO_PE_DVDD1_2

AE8

+VIO_PE_DVDD1_3

AC13

+VIO_PE_AVDD0_1

AB12

+VIO_PE_AVDD0_2

AC12

+VIO_PE_AVDD0_3

AD11

+VIO_PE_AVDD0_4

AD13

+VIO_PE_AVDD0_5

AB13

+VIO_PE_AVDD0_6

Y12

+VIO_PE_AVDD1_1

Y13

+VIO_PE_AVDD1_2

AA13

+VIO_PE_AVDD1_3

W12

+VIO_PE_AVDD1_4

W13

+VIO_PE_AVDD1_5

T11

+3.3V_HVDD_1

T12

+3.3V_HVDD_2

U13

+3.3V_HVDD_3

U11

+3.3V_1

U12

+3.3V_2

F5

+3.3V_3

E29

+3.3V_4

E5

+3.3V_5

L11

+VDD_DUAL_AUXC_1

M17

+VDD_DUAL_AUXC_2

M20

+VDD_DUAL_AUXC_3

A16

+3.3V_VBAT

OMIT

U1400

MCP89M-A01

FBGA

(9 OF 11)

POWER II

+VDD_COREB_SENSE

+VIO_SATA_AVDD_1 +VIO_SATA_AVDD_2 +VIO_SATA_AVDD_3 +VIO_SATA_AVDD_4 +VIO_SATA_AVDD_5

+VIO_SATA_DVDD_1 +VIO_SATA_DVDD_2 +VIO_SATA_DVDD_3 +VIO_SATA_DVDD_4 +VIO_SATA_DVDD_5 +VIO_SATA_DVDD_6 +VIO_SATA_DVDD_7 +VIO_SATA_DVDD_8

+VIO_SATA_DVDD_9 +VIO_SATA_DVDD_10 +VIO_SATA_DVDD_11 +VIO_SATA_DVDD_12

+VDD_DUAL_RMGT_1

+VDD_DUAL_RMGT_2

+3.3V_DUAL_RMGT_1 +3.3V_DUAL_RMGT_2

+3.3V_DUAL_USB_1

+3.3V_DUAL_USB_2

+VDD_COREB_1 +VDD_COREB_2 +VDD_COREB_3 +VDD_COREB_4 +VDD_COREB_5 +VDD_COREB_6 +VDD_COREB_7 +VDD_COREB_8

+VDD_COREB_9 +VDD_COREB_10 +VDD_COREB_11 +VDD_COREB_12 +VDD_COREB_13 +VDD_COREB_14 +VDD_COREB_15 +VDD_COREB_16 +VDD_COREB_17 +VDD_COREB_18 +VDD_COREB_19 +VDD_COREB_20 +VDD_COREB_21 +VDD_COREB_22 +VDD_COREB_23 +VDD_COREB_24 +VDD_COREB_25 +VDD_COREB_26 +VDD_COREB_27 +VDD_COREB_28 +VDD_COREB_29 +VDD_COREB_30 +VDD_COREB_31 +VDD_COREB_32 +VDD_COREB_33 +VDD_COREB_34 +VDD_COREB_35 +VDD_COREB_36 +VDD_COREB_37 +VDD_COREB_38 +VDD_COREB_39 +VDD_COREB_40 +VDD_COREB_41 +VDD_COREB_42

GND_COREB_SENSE

+3.3V_DUAL_1

+3.3V_DUAL_2

=PPVCORE_SW_MCP_GFX

M4 M2 P4 N12 N4 N14 V20 N10 P3 P1 N11 N6 P6 N2 N9 N8 M10 N3 N1 M5 M7 P2 M8 M11 V19 N7 N16 P5 N5 N13 N15 P9 V17 V18 M14 M13 Y19 Y20 Y17 Y18 P7 P8

U10

TP_MCP_VDDCOREB_SENSEP

T10

TP_MCP_VDDCOREB_SENSEN PP1V05_S0_MCP_SATA_AVDD

AE1 AE2 AE3 AE4 AE5

=PP1V05_S0_MCP_SATA_DVDD

AF1 AF2 AF3 AF4 AF5 AF6 AF9 AF10 AF11 AE11 AE12 AE13

=PP0V9_ENET_MCP_RMGT

L12 L13

=PP3V3_ENET_MCP_RMGT

A13 B13

=PP3V3_S5_MCP

A20

200 mA

A19

F8

40 mA

E8

345678

15350 mA (0.85V)

300 mA

100 mA

140 mA

300 mA

240 mA

22 24

23

8

8 9

8

2 1

OMIT

U1400

MCP89M-A01

FBGA

M37

D18

AD5

AT1

AT3

AA8

J32

H15 D33 B18 M32

K18

F34

R35 AR9 AA2

R32

V32

K24 K21

AG8 AN5

AD2 D15 AG2 L15

(10 OF 11) GND_1 GND_2 GND_3 GND_4 GND_5 GND_6

B1

GND_7 GND_8

J2

GND_9 GND_10 GND_11

C1

GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20

B6

GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28

B2

GND_29

E6

GND_30

J5

GND_31 GND_32 GND_33 GND_34 GND_35

V8

GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42

H8

GND_43 GND_44 GND_45 GND_46 GND_47 GND_48

J7

GND_49 GND_50 GND_51 GND_52 GND_53 GND_54

J8

GND_55 GND_56 GND_57

V2

GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67

AP21

AM21 AU37 AC27

AM30

AP24 AM33 AE27 AJ24 AH18

AM18

AJ21 AK35

AN34 AD10

AA10

AG29

AP12 AM12 AH21

AR33

AA32 AG34

23

18 23

23

AK37

AD32

AK32 AR12 AN35 AN37

GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98

GND

GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134

AD7 B12 D12 E12 G12 A2 AL12 AM6 AD37 AG32 H12 AR35 H9 G24 V10 V5 AL30 G7 V29 AP15 AN2 AJ12 AR15 N20 D21 E21 G21 H21 AR27 AM27 AP27 AM15 AA31 AM9 AH24 K12 J31 E30 AK7 V7 M31 AU12 AP6 B37 A36 F35 L27 D35 AL24 AP30 AH15 B21 AV3 AT38 B38 AA21 AD4 A37 AP18 AN4 B24 D30 V4 AA7 AD34 AK4 R37

AU24 AU15

AD35 AJ18 AL18 AR24

AM24

AR21

AU30

AH27

AA34 AK31

AU21

AL21 AA11

AK34

AR30 AU33

AH30

AU27

AG10

AU38

AJ15

AL27 AV37

AG5

AA5 G18

AU9

H24 B30

D24

AK5 N18 E24 K15 M19

E18

K11

V34

M34 B27 V28 C38 D27 R34 J35

E15

J34

AU1

E27 L21

H18 B15 AA4

L18

G15

N19 H27

B9

J4

E9

A3

D9 L4

OMIT

U1400

MCP89M-A01

FBGA

(11 OF 11) GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198 GND_199

GND_200 GND_201 GND_202 GND_203 GND_204 GND_205 GND_206 GND_207 GND_208 GND_209 GND_210 GND_211 GND_212 GND_213 GND_214 GND_215 GND_216 GND_217 GND_218 GND_219 GND_220 GND_221 GND_222 GND_223 GND_224 GND_225 GND_226 GND_227 GND_228 GND_229 GND_230

GND

GND_231 GND_232 GND_233 GND_234 GND_235 GND_236 GND_237 GND_238 GND_239 GND_240 GND_241 GND_242 GND_243 GND_244 GND_245 GND_246 GND_247 GND_248 GND_249 GND_250 GND_251 GND_252 GND_253 GND_254 GND_255 GND_256 GND_257 GND_258 GND_259 GND_260 GND_261 GND_262 GND_263 GND_264

E33 M35 AV2 AK2 AU6 F37 C3 J37 V35 G27 AA35 AU18 AR6 AV36 B33 AJ27 G9 AG35 AG7 AD8 AU2 AP9 AD31 V37 AA37 AG37 AL15 AR18 L14 K14 F2 K27 AL9 AB26 M29 G30 R28 R29 R31 U17 K8 Y21 V31 U18 W21 U19 W18 U20 W17 V21 AA28 AA29 N17 AD28 AD29 AG4 W19 W20 AA26 AB27 AA17 AA18 AA19 AA20 U21

D

C

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Power & Ground

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

20 OF 109

SHEET

20 OF 76

36

345678

2 1

D

C2300 helps reduce input rail droop during Q2300 turn-on.

=PP1V5R1V35_S0_MCPDDRFET

8

=PP5V_S3_MCPDDRFET

8

21

C

MCP_MEM_VDD_EN

19 62

IN

MCPMEM_CNFG

1

R2305

560K

1% 1/16W MF 402

2

SLG5AP031

2

EN

3

CNFG

U2305

CRITICAL

GND

4

<R1>

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

PLACE_NEAR=Q2300.9:2 mm

1

VCC

TDFN

G

S

DONE

THRM

PAD

9

1

C2305

0.1UF

20% 10V

2

CERM 402

5

D

7

MCPMEM_GATE

(G driven to VCC)

6

8

TP_MCPMEM_DONE

CRITICAL

C2300

100UF

6.3V

CERM-X5R

1206-1

1

20%

2

4

G

SENSE

7

CRITICAL

9

STMFS485NST1G

Q2300

D

DFN

8

NC

6

KELVIN

S

321 5

MCPDDRFET_KELVIN

K1

NC

MCPDDRFET_SENSE

PP1V5R1V35_SW_MCP

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE

=PP1V5R1V35_SW_MCP_MEM

NV Requirements:

- Min Ramp-Up Time: 20 uS (10% to 90%)

- Max Ramp-Up Time: 65 uS (ENABLE to 90%)

- FET Ron <= 3.8 mOhms

Part Type Rds(on) Loading

(OR 1.35V)

Q2300

STMFS4854N N-Channel 10 mOhm @3.2V

4.3 A (EDP)

OUT

4250 mA

40

15 20 23

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.

D

C

Gated Rail Savings: 120mW

DIMM CKE Clamps

CKE must be held low to keep memory in self-refresh.

B

=PP5V_S3_MCPDDRFET

8

21

MCP_MEM_VTT_EN

19

IN

R2350

Q2350

SSM3K15FV

SOD-VESM-HF

1

10K

5% 1/16W MF-LF

402

G S

1

2

MEMVTT_EN_L

3

D

2

A

CRITICAL

Q2355

NTUD3170NZXXG

SOT-963

G

5

4

G

2

1

CRITICAL

Q2356

NTUD3170NZXXG

SOT-963

G

5

4

G

2

1

D

S

D

S

D

S

D

S

8 7 5 4 2 1

Clamps enable before MCP89 MEMVDD rail switched off. Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89. Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM. Q2355/Q2356 chosen for low output capacitance.

3

MEM_A_CKE<0>

6

MEM_A_CKE<1>

15 26 70

BI

15 26 70

BI

NO STUBS on CKE signals!

3

MEM_B_CKE<0>

6

MEM_B_CKE<1>

15 27 70

BI

15 27 70

BI

36

SYNC_MASTER=K6_MLB

PAGE TITLE

MCP89 Memory Rail Gating

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

BRANCH

PAGE

23 OF 109

SHEET

21 OF 76

C.0.0

SIZE

B

A

D

345678

2 1

D

C2400 helps reduce input rail droop during Q2400 turn-on.

=PPVCORE_S0_MCPGFXFET

8

CRITICAL

1

C2400

100UF

20%

6.3V

2

CERM-X5R 1206-1

=PP5V_S0_MCPFSBFET

8

5 6 7 8

1

C

GFXVCORE_PWR_EN

19

IN

MCPGFX_CNFG

1

C2406

2

820PF

10%

50V

CERM

402

2

3

VCC

U2405

SLG5AP033

TDFN

EN

CRITICAL

CNFG

GND

4

THRM

PAD

DONE

9

1

2

5

D

7

G

6

S

8

C2405

0.1UF

20% 10V CERM 402

MCPGFX_GATE

(G driven to VCC)

TP_MCPGFX_DONE

4

G

<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

CRITICAL

D

Q2400

SI4838BDY

SO-8

S

31 2

NV Requirements:

- Min Ramp-Up Time: 100 uS (10% to 90%)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

- FET Ron <= 2.5 mOhms NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

PLACE_NEAR=C2400.1:1 mm

XW2400

SM

1 2

PLACE_NEAR=Q2400.5:2 mm

XW2401

SM

1 2

PLACE_NEAR=C2400.2:1 mm

Part Type Rds(on) Loading

PPVCORE_SW_MCP_GFX

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0.9V MAKE_BASE=TRUE

=PPVCORE_SW_MCP_GFX

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

Q2400

Si4838BDY N-Channel

3.2 mOhm @2.5V

15.35 A (EDP)

20 24

59 75

OUT

59 75

OUT

D

C

Gated Rail Savings: 860mW

SIZE

B

A

D

B

A

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP89 GFX Core Rail Gating

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=12/15/2009

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

24 OF 109

SHEET

22 OF 76

MCP Non-GFX Core Power

=PPVCORE_S0_MCP

8

20

8450 mA (0.85V)

212

1

4.7UF

20% 4V X5R 402

C2500 C2501

10UF

20%

6.3V X5R

603-1

1

C2502

1UF

10% 10V 10V

2

X5R 402-1

1

C2503

0.22UF

20%

6.3V

2

X5R 402

1

C2504

0.1UF

20% 10V

2

CERM 402

1

2

0.1UF

20% 10V CERM 402

1

C2506C2505

20% 10V

2

CERM 402

1

C2507

0.1UF0.1UF

20%

2

CERM 402

1

C2508

0.1UF

20% 10V

2

CERM 402

=PP1V05_S0_MCP_AVDD_UF

8

800 mA

L2560

30-OHM-5A

0603

C2560

10UF

6.3V

603-1

20% X5R

21

212

1

C2561

4.7UF

20% 4V X5R 402

345678

2 1

MCP 1.05V PCIe Analog Power

1

C2562

1UF

10% 10% 10V

2

X5R 402-1

1

C2563

1UF

10V

2

X5R 402-1

1

C2564

0.1UF

20% 10V

2

CERM 402

1

C2565

0.1UF

20% 10V

2

CERM 402

PP1V05_S0_MCP_PE_AVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

C2566

0.1UF

20% 10V

2

CERM 402

500 mA

8

D

C

MCP Memory Power

=PP1V5R1V35_SW_MCP_MEM

15 20 21

4300 mA (1.5V)

MCP CPU FSB (VTT) Power

=PP1V05_SW_MCP_FSB

8

20

2000 mA

MCP 0.9V AUX Core Power

=PP0V9_S5_MCP_VDD_AUXC

8

20

150 mA

MCP 1.05V PCIE Digital Power

=PP1V05_S0_MCP_PE_DVDD

8

200 mA

C2510

4.7UF

C2520

10UF

6.3V

603-1

C2530

2.2UF

6.3V

CERM

402-LF

20%

4V X5R 402

20% X5R

20%

1

2

212

1

C2526

0.1uF

20% 10V

2

CERM 402

1

2

1

C2511

0.1UF

20% 10V

2

CERM 402

1

C2521

4.7UF

20% 4V X5R 402

1

C2531

1UF

10% 10V

2

X5R 402-1

1

C2527

0.1uF

20% 10V

2

CERM 402

1

C2512

20% 10V

2

CERM 402

1

C2522

1UF

10% 10V

2

X5R 402-1

1

C2532

2.2UF

20%

6.3V

2

CERM 402-LF

1

C2513

0.1UF0.1UF

20% 10V

2

CERM 402

1

2

0.1UF

20% 10V CERM 402

1

2

C2515C2514

0.1UF

20% 10V CERM 402

1

C2516

0.1UF

20% 10V

2

CERM 402

1

C2517

0.1UF

20% 10V

2

CERM 402

1

C2518

0.1UF

20% 10V

2

CERM 402

1

C2519

0.1UF

20% 10V

2

CERM 402

MCP S0 FSB (VTT) Power

=PP1V05_S0_MCP_FSB

8

14 20

200 mA

1

C2523 C2525

1UF

10% 10V

2

X5R 402-1

C2524

4.7UF

20% X5R

402

1

1UF

4V

10% 10V

2

X5R 402-1

MCP 0.9V MAC/SMU Power

=PP0V9_ENET_MCP_RMGT

8

20

140 mA

1

C2528

4.7uF

20%

4V X5R 402

C2529

0.1uF

20% 10V

2

CERM 402

MCP 1.05V SATA Digital Power

=PP1V05_S0_MCP_SATA_DVDD

8

20

100 mA

1

C2533

2.2UF

20%

6.3V

2

CERM 402-LF

1

C2534

0.1uF

20% 10V

2

CERM 402

1

C2535

0.1uF

20% 10V

2

CERM 402

C2536

4.7UF

1

C2537

0.1uF

20%

4V X5R 402

20% 10V

2

CERM 402

=PP1V05_S0_MCP_PLL_UF

8

555 mA

PLACE_NEAR=R2570.1:50 mil

GND_MCP_PLL_FSB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=0V

L2567

30-OHM-5A

0603

C2567

10UF

6.3V

603-1

CRITICAL

L2570

220-OHM-2.2A

0603

C2570

4.7UF

CRITICAL

L2575

220-OHM-2.2A

0603

C2575

4.7UF

CRITICAL

L2580

220-OHM-2.2A

0603

C2580

4.7UF

20% X5R

402

20% X5R

402

20% X5R

402

21

4V

21

4V

21

4V

212

1

2

1

2

1

2

1

C2568

4.7UF

20% 4V X5R 402

R2570

0.33

1 2

1/16W

0402

5% MF

MCP 1.05V SATA Analog Power

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

C2569

0.1UF

20% 10V

2

CERM 402

300 mA

MCP 1.05V CPU/FSB/MEM PLL Power

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

1

C2571

0.1UF

20% 10V

2

CERM 402

1

C2576

0.1UF

20% 10V

2

CERM 402

1

C2581

0.1UF

20% 10V

2

CERM 402

1

C2572

0.1uF

20% 10V

2

CERM 402

1

C2577

0.1uF

20% 10V

2

CERM 402

1

C2582

0.1uF

20% 10V

2

CERM

VOLTAGE=1.05V

1

2

1

2

1

2

20

PP1V05_S0_MCP_PLL_FSBMEM

C2573

0.1UF

20% 10V CERM 402

MCP 1.05V PCIe/SATA PLL Power

PP1V05_S0_MCP_PLL_PEXSATA

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

C2578

0.1UF

20% 10V CERM 402

1

C2579

0.1UF

20% 10V

2

CERM 402

MCP 1.05V Core/Misc PLL Power

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

C2583

0.1UF

20% 10V CERM 402402

1

C2584

0.1UF

20% 10V

2

CERM 402

70 mA

D

15

16

325 mA

C

17

160 mA

MCP 1.05V Memory DLL Power

=PP1V05_S0_MCP_M2CLK_DLL

8

15

550 mA

C2540

4.7UF

1

20%

4V

2

X5R 402

B

MCP 3.3V/1.5V HDA Power

=PP3V3R1V5_S0_MCP_HDA

8

19

70 mA

C2548

4.7UF

6.3V CERM

1

20%

603

2

MCP 3.3V PCIe/SATA I/O PLL Power

=PP3V3_S0_MCP_HVDD

8

20

30 mA

C2549

0.1uF

20% 10V CERM 402

MCP 3.3V I/O Power

=PP3V3_S0_MCP

8

20

250 mA

C2543

4.7uF

6.3V CERM

1

C2544

212

0.1uF

20% 10V CERM

20%

603 402

1

C2545

0.1uF

20% 10V

2

CERM 402

1

C2546

0.1uF

20% 10V

2

CERM 402

1

C2547

0.1uF

20% 10V

2

CERM 402

MCP 3.3V AUX/USB Power

=PP3V3_S5_MCP

8

20

240 mA

1

C2550

4.7uF

20%

6.3V CERM

603

MCP 3.3V MAC/SMU Power

=PP3V3_ENET_MCP_RMGT

8 9

A

18 20

300 mA

C2553

4.7uF

20%

6.3V CERM

603

C2551

0.1uF

20% 10V

2

CERM 402

MCP 3.3V MAC PLL Power

=PP3V3_ENET_MCP_PLL_MAC

8

1

C2554

0.1uF

20% 10V

2

CERM 402

20 mA

MCP 2.0V-3.3V RTC Power

PP3V3_G3_RTC

7 8

19 20

? uA (G3) 5 mA (S0)

4.7UF

20%

6.3V CERM

603

CRITICAL

L2555

0402

C2555

4.7UF

1

2

6.3V CERM

C2552

FERR-240-OHM-200MA

DO NOT SYNC FROM T27. DECOUPLING CAP VALUES CHANGED. Current #s from MCP89 A01 Bring-Up Support doc (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009)

8 7 5 4 2 1

=PP3V3_S0_OPA330

8

23

HTOL_SENSE:YES

1

C2599

0.1UF

20%

2

10V CERM

1

C2541

4.7UF

20%

6.3V CERM

603

PP3V3_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM

21

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

C2556

0.1UF

20%

603

20% 10V

2

CERM 402

C2542

0.1uF

20% 10V

2

CERM 402

8

MCPHVDD:P2V5

R2592

20 mA

=PP3V3_S0_MCP_PLL_UF

260 mA

10K

1/16W MF-LF

402

18

1

5%

2

MCP_PLL_LD0_EN

MCPHVDD:P2V5

1

C2593

1UF

10% 10V

2

X5R 402

PART NUMBER

353S2987 353S2979 116S0004

MCPHVDD:P3V3

R2593

0

1 2

CRITICAL

OMIT_TABLE

U2592

MIC5365-2.5V

1

VIN

3

EN

QTY

1 1 1

PP3V3_S0_LDO_R

MIN_LINE_WIDTH=0.4 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

VOLTAGE=3.3V

MF-LF

402

LDO:ADJ

SC70

GND 2

VOUT

NC

5

4

LDO_ADJ

LDO:ADJ

DESCRIPTION

IC,TPS71725,LDO REG,2.5V,150MA,SC70

IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF

RES,0402,0,5%,1/16W

PP3V3_S0_LDO_R_BRDG

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

1

R2594

10K

5% 1/16W MF-LF

402

2

1

R2591

10K

5% 1/16W MF-LF

402

2

CRITICAL

L2595

220-OHM-2.2A

0603

PLACE_NEAR=R2595.1:50 mil

402

R2550

0

5% 1/16W MF-LF

402

MCPHVDD:P2V5

1

C2592

1UF

10% 10V

2

X5R 402

21

GND_MCP_PLL_DP_USB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=0V

HTOL_SENSE:YES

R2597

1/16W MF-LF

23

HTOL_SENSE:YES

R2596

1 2

SMC_P24

35

IN

HTOL_SENSE:YES

4.7UF

6.3V CERM

1

20%

2

603

C2595

REFERENCE DES

U2592 U2592 R2596

1K

1%

402

=PP3V3_S0_OPA330

8

1K

CRITICAL

1%

1/16W

Q2592

MF-LF

NTZD3152P

402

SOT-563-HF

HTOL_SENSE:YES

S

1

G

2

R2599

100K

5% 1/16W MF-LF

402

R2595

0.33

1 2

5%

1/16W

MF

0402

CRITICAL

CRITICAL CRITICAL CRITICAL

D

6

1

C2596

0.1UF

20% 10V

2

CERM 402

SMC_N_MIRROR

2

3

-IN

V-

4

1

+IN

PP3V3_S0_MCP_HVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MCP 3.3V DP & USB PLL Power

OPA_MIRROR_OUT

V+

SC70-5

OPA330

5

U2593

CRITICAL

HTOL_SENSE:YES

R2590

845K

1 2

1/16W 1% MF-LF

1

2

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

2

402

HTOL_SENSE:YES

C2594

0.1UF

20% 10V CERM 402

CRITICAL

L2590

FERR-240-OHM-200MA

0402

PP3V3_S0_MCP_PLL_DP_USB

C2597

0.1uF

20% 10V CERM 402

BOM OPTION

LDO:FIXED

LDO:ADJ

HTOL_SENSE:NO

4

S

HTOL_SENSE:YES

SOT-563-HF

5

G

SMC_P_FOLLOW

21

C2590

4.7UF

Q2592

D

3

1

+IN

3

-IN

SMC_N_FOLLOW

1

20%

2

6.3V CERM

603

NTZD3152P

CRITICAL

HTOL_SENSE:YES

CRITICAL

U2594

OPA330

SC70-5

5

V+

4

V-

2

1

C2591

0.1UF

2

20% 10V CERM 402

PLACEMENT_NOTEs: Place close to SMC

Place close to SMC

(For R and C)

HTOL_SENSE:YES

R2598

4.53K

1 2

1% 1/16W MF-LF

402

MCP 3.3V PLL Power

PP3V3_S0_MCP_PLL_HVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

210 mA

SYNC_MASTER=(T27_MLB)

PAGE TITLE

MCP Standard Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SMC_NB_MISC_ISENSE

HTOL_SENSE:YES

C2598

1

0.22UF

20%

6.3V X5R

2

402

GND_SMC_AVSS

16

50 mA

OUT

35 36 39 40

SYNC_DATE=(11/16/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

25 OF 109

SHEET

23 OF 76

SIZE

B

35

A

D

36

345678

2 1

MCP GFX Core Power

=PPVCORE_SW_MCP_GFX

20 22

15350 mA (0.85V)

MCP 3.3V RGBDAC Power

PP3V3_S0_MCP_DAC

140 mA

17

D

212

1

C2601

4.7UF

20% 4V X5R 402

C2600

10UF

6.3V

603-1

20% X5R

D

1

C2602

1UF

10% 10V

2

X5R 402-1

1

C2603

1UF

10% 10V

2

X5R 402-1

1

C2604

0.22UF

20%

6.3V

2

X5R 402

1

C2605

0.22UF

20%

6.3V

2

X5R 402

1

C2606

0.1UF

20% 10V

2

CERM 402

1

C2607

0.1UF

20% 10V

2

CERM 402

1

C2608

0.1UF

20% 10V

2

CERM 402

1

C2609

0.1UF

20% 10V

2

CERM 402

1

C2610

0.1UF

20% 10V

2

CERM 402

1

C2611

0.1UF

20% 10V

2

CERM 402

1

C2612

0.1UF

20% 10V

2

CERM 402

R2670

1/16W MF-LF

402

GND_MCP_DAC_P3V3

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

1

VOLTAGE=0V MAKE_BASE=TRUE

0

5%

If RGBDAC is used, requires ferrite (155S0382)

2

plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap. If RGBDAC is not used, tie to GND.

MCP 3.3V/1.8V IFP Interface Power

=PP3V3R1V8_S0_MCP_IFP_VDD

8

17

180 mA (1.8V LVDS)

C2620

4.7uF

6.3V CERM

20% 603

212

1

C2621

0.1uF

20% 10V CERM 402

MCP 1.05V IFP PLL Power

=PP1V05_S0_MCP_PLL_IFP

8

17

60 mA

C2630

4.7uF

20% X5R

402

1

C2631

0.1uF

20%

4V

10V

2

CERM 402

MCP 1.05V DisplayPort Power

=PP1V05_S0_MCP_DP0_VDD

8

17

160 mA

1

C2640

4.7UF

20% X5R

402

C

MCP_TMDS0_RSET

17 71

MCP_TMDS0_VPROBE

17 71

NO STUFF

C2650

0.1UF

20% 10V

CERM

402

1

C2641

0.1uF

20%

4V

10V

2

CERM 402

C

MCP_IFPAB_RSET

17 71

MCP_IFPAB_VPROBE

1

R2650

1

1K

1% 1/16W MF-LF 402

2

17 71

NO STUFF

C2655

0.1UF

20% 10V

CERM

402

NO STUFF

1

R2655

1

1K

1% 1/16W MF-LF

2

402

2

B

A

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

8 7 5 4 2 1

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Graphics Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

26 OF 109

SHEET

24 OF 76

36

345678

2 1

RTC Crystal

R2810

0

10M

1/16W MF-LF

402

1 2

1/16W

1

MF-LF

5%

2

RTC_CLK32K_XTALOUT_R

5%

402

CRITICAL

Y2810

32.768K

7X1.5X1.4-SM

41

RTC_CLK32K_XTALOUT

19

IN

NO STUFF

R2811

D

RTC_CLK32K_XTALIN

19

OUT

C2810

12pF

1 2

5%

50V

CERM

402

C2811

12pF

1 2

5%

50V

CERM

402

19 72

IN

LPC_RESET_L

MCP 25MHz Crystal

R2815

0

1/16W MF-LF

402

1 2

1/16W

1

MF-LF

1M

5%

2

MCP_CLK25M_XTALOUT_R

5%

402

CRITICAL

Y2815

25.0000M

SM-3.2X2.5MM

31

MCP_CLK25M_XTALOUT

19

IN

MCP_CLK25M_XTALIN

19

OUT

NO STUFF

R2816

C

C2815

12pF

1 2

5%

50V

CERM

402

NC

2 4

NC

C2816

12pF

1 2

5%

50V

CERM

402

16

IN

19 72

IN

PCIE_RESET_L

MAKE_BASE=TRUE

LPC_CLK33M_SMC_R

Platform Reset Connections

LPC Reset (Unbuffered)

R2881

PLACE_NEAR=U1400.K7:5 MM

PCIE Reset (Unbuffered)

PLACE_NEAR=U1400.L5:5 MM

33

1 2

5% 1/16W MF-LF

402

R2893

1 2

5% 1/16W MF-LF

402

R2825

33

1 2

5% 1/16W MF-LF

402

R2883

33

1 2

5% 1/16W MF-LF

402

R2891

0

1 2

5% 1/16W MF-LF

0

402

R2894

0

1 2

5% 1/16W MF-LF

402

R2826

33

1 2

5% 1/16W MF-LF

402

LPCPLUS_RESET_L

SMC_LRESET_L

PCA9557D_RESET_L

BKLT_PLT_RST_L

AP_RESET_L

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

37

OUT

D

35

OUT

29

OUT

68

OUT

30

OUT

C

35 72

OUT

37 72

OUT

B

MCP S0 PWRGD & CPU_VLD

=PP3V3_S5_MCPPWRGD

8

0.1UF

CERM

20% 10V

402

1

2

U2850

5

1

2

74LVC1G08GW

SOT353

B

4

MCP_PS_PWRGD

Y

A

3

C2850

A

VR_PWRGOOD_DELAY

58

IN

ALL_SYS_PWRGD

35 62

IN

DO NOT SYNC WTIH T27. REMOVED PCIE RESET SIGNALS +CAESAR XTAL

8 7 5 4 2 1

R2829

22

PM_CLK32K_SUSCLK_R

19 72

IN

PLACE_NEAR=U1400.H11:5 MM

1 2

5% 1/16W MF-LF

402

PM_CLK32K_SUSCLK

35 72

OUT

B

System Reset Circuit

PM_SYSRST_L

35

IN

XDP_DBRESET_L

10 13 19

IN

19

OUT

PLACEMENT_NOTE=Place R2897 on BOTTOM

XDP

R2896

0

1 2

5% 1/16W MF-LF

R2897

402

SILK_PART=SYS RST

OMIT

1/16W MF-LF

402

R2899

1 2

1/16W

1

MF-LF

0

5%

2

10K pull-up to 3.3V S0 inside MCP

33

5%

402

PM_SYSRST_DEBOUNCE_L

NO STUFF

1

C2899

1UF

10% 10V

2

X5R 402

SIZE

A

D

OUT

SYNC_MASTER=(T27_MLB)

PAGE TITLE

SB Misc

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(10/07/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

28 OF 109

SHEET

25 OF 76

36

Page Notes

Power aliases required by this page:

- =PPLVDDR_S3_MEM_A

- =PPDDRVTT_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V) Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA BOM options provided by this page:

(NONE) NOTE: J3100 is OMITted on this page.

D

Proper APN(s) required elsewhere.

C

B

=PPSPD_S0_MEM_A

8

1

C2940

2.2UF

A

8 7 5 4 2 1

6.3V CERM

402-LF

20%

2

=PPDDRVTT_S0_MEM_A

8

MEM_A_CKE<0>

15 21 70

IN

MEM_A_BA<2>

15 70

IN

MEM_A_A<12>

15 70

IN

MEM_A_A<9>

15 70

IN

MEM_A_A<8>

15 70

IN

MEM_A_A<5>

15 70

IN

MEM_A_A<3>

15 70

IN

MEM_A_A<1>

15 70

IN

MEM_A_CLK_P<0>

15 70

IN

MEM_A_CLK_N<0>

15 70

IN

MEM_A_A<10>

15 70

IN

MEM_A_BA<0>

15 70

IN

MEM_A_WE_L

15 70

IN

MEM_A_CAS_L

15 70

IN

MEM_A_A<13>

15 70

IN

MEM_A_CS_L<1>

15 70

IN

=MEM_A_DQ<32>

28

BI

=MEM_A_DQ<33>

28

BI

=MEM_A_DQS_N<4>

28

BI

=MEM_A_DQS_P<4>

28

BI

=MEM_A_DQ<34>

28

BI

=MEM_A_DQ<35>

28

BI

=MEM_A_DQ<40>

28

BI

=MEM_A_DQ<41>

28

BI

=MEM_A_DM<5>

28

IN

=MEM_A_DQ<42>

28

BI

=MEM_A_DQ<43>

28

BI

=MEM_A_DQ<48>

28

BI

=MEM_A_DQ<49>

28

BI

=MEM_A_DQS_N<6>

28

BI

=MEM_A_DQS_P<6>

28

BI

=MEM_A_DQ<50>

28

BI

=MEM_A_DQ<51>

28

BI

=MEM_A_DQ<56>

28

BI

=MEM_A_DQ<57>

28

BI

=MEM_A_DM<7>

28

IN

=MEM_A_DQ<58>

28

BI

=MEM_A_DQ<59>

28

BI

MEM_A_SA<0>

MEM_A_SA<1>

1

402

R2941

10K

5%

1/16W MF-LF 402

2

R2940

10K

1/16W MF-LF

SPD Addr: 0xA0(Wr)/0xA1(Rd)

=PPLVDDR_S3_MEM_A

8

73

CKE0

75

VDD

77

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

NC

79

BA2

81

VDD

83

A12/BC*

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD CK0 CK0*

VDD A10/AP BA0

VDD WE* CAS*

VDD A13 S1*

VDD TEST

VSS DQ32 DQ33

VSS DQS4* DQS4

VSS DQ34 DQ35

VSS DQ40 DQ41

VSS DM5

VSS DQ42 DQ43

VSS DQ48 DQ49

VSS DQS6* DQS6

VSS DQ50 DQ51

VSS DQ56 DQ57

VSS DM7

VSS DQ58 DQ59

VSS SA0 VDDSPD SA1

VTT

NC

Foxconn: 516-0201 Molex: 516-0213

1

C2900

10UF

6.3V

CRITICAL

J2900

F-RT-THB

C2901

20%

2

X5R 603

KEY

CKE1

OMIT

(SYMBOL 2 OF 2)

CK1*

DDR3-SODIMM-DUAL-M97-3

RAS*

ODT0

ODT1

VREFCA

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5*

DQS5

DQ46 DQ47

DQ52 DQ53

DQ54 DQ55

DQ60 DQ61

DQS7*

DQS7

DQ62 DQ63

EVENT*

VDD

VSS

VTT

A15 A14

A11

CK1

BA1

S0*

DM4

DM6

SDA SCL

VDD

A7

A6 A4

A2 A0

NC

10UF

6.3V

20% X5R

603

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

345678

2 1

DDR3 Plane Stitching Caps (Space evenly across plane split)

2

1

2

C2910

0.1UF

20% 10V

1

CERM 402

2

C2911

0.1UF

20% 10V

1

CERM 402

2

C2912

0.1UF

20% 10V

1

CERM 402

2

C2913

0.1UF

20% 10V

1

CERM 402

2

C2914

0.1UF

20% 10V

1

CERM 402

2

C2915

0.1UF

20% 10V

1

CERM 402

2

C2916

0.1UF

20% 10V

1

CERM 402

2

C2917

0.1UF

20% 10V

1

CERM 402

2

C2918

0.1UF

20% 10V

1

CERM 402

2

C2919

0.1UF

20% 10V

1

CERM 402

2

C2920

0.1UF

20% 10V

1

CERM 402

2

C2921

0.1UF

20% 10V

1

CERM 402

2

C2922

0.1UF

20% 10V

1

CERM 402

2

C2923

0.1UF

20% 10V

1

CERM 402

D

"Factory" (top) slot

PPVREF_S3_MEM_VREFDQ_A

NC

MEM_A_CKE<1>

MEM_A_A<15> MEM_A_A<14>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6> MEM_A_A<4>

MEM_A_A<2> MEM_A_A<0>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_BA<1> MEM_A_RAS_L

MEM_A_CS_L<0> MEM_A_ODT<0>

MEM_A_ODT<1>

=MEM_A_DQ<36> =MEM_A_DQ<37>

=MEM_A_DM<4>

=MEM_A_DQ<38> =MEM_A_DQ<39>

=MEM_A_DQ<44> =MEM_A_DQ<45>

=MEM_A_DQS_N<5> =MEM_A_DQS_P<5>

=MEM_A_DQ<46> =MEM_A_DQ<47>

=MEM_A_DQ<52> =MEM_A_DQ<53>

=MEM_A_DM<6>

=MEM_A_DQ<54> =MEM_A_DQ<55>

=MEM_A_DQ<60> =MEM_A_DQ<61>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_A_DQ<62> =MEM_A_DQ<63>

MEM_EVENT_L =I2C_SODIMMA_SDA =I2C_SODIMMA_SCL

C2936

0.1UF

CERM

20% 10V

402

29

PPVREF_S3_MEM_VREFCA_A

1

C2935

2.2UF

20%

6.3V

212

CERM 402-LF

C2930

2.2UF

20%

6.3V CERM

402-LF

1

C2931

0.1UF

20% 10V

2

CERM 402

29

=MEM_A_DQ<0>

28

=MEM_A_DQ<1>

28

BI

=MEM_A_DM<0>

28

IN

=MEM_A_DQ<2>

28

BI

=MEM_A_DQ<3>

28

BI

=MEM_A_DQ<8>

28

BI

=MEM_A_DQ<9>

28

BI

=MEM_A_DQS_N<1>

28

BI

=MEM_A_DQS_P<1>

28

BI

=MEM_A_DQ<10>

28

BI

=MEM_A_DQ<11>

28

BI

=MEM_A_DQ<16>

28

BI

=MEM_A_DQ<17>

28

BI

=MEM_A_DQS_N<2>

28

BI

=MEM_A_DQS_P<2>

28

BI

=MEM_A_DQ<18>

28

BI

=MEM_A_DQ<19>

28

BI

=MEM_A_DQ<24>

28

BI

=MEM_A_DQ<25>

28

BI

=MEM_A_DM<3>

28

IN

=MEM_A_DQ<26>

28

BI

28

BI

15 21 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

28

BI

28

BI

28

IN

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

IN

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

19 27 35

OUT

38

BI

38

IN

1

VREFDQ

3

VSS

5

DQ0 DQ1

VSS

DM0

VSS DQ2 DQ3

VSS DQ8 DQ9

VSS DQS1* DQS1

VSS DQ10 DQ11

VSS DQ16 DQ17

VSS DQS2* DQS2

VSS DQ18 DQ19

VSS DQ24 DQ25

VSS DM3

VSS DQ26 DQ27

VSS

CRITICAL

OMIT

J2900

F-RT-THB

(SYMBOL 1 OF 2)

RESET*

DDR3-SODIMM-DUAL-M97-3

KEY

7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

Foxconn: 516-0201 Molex: 516-0213

SYNC_MASTER=T27_MLB

PAGE TITLE

DDR3 SO-DIMM Connector A

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DQ4 DQ5

DQS0*

DQS0

VSS

DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3*

DQS3

VSS DQ30 DQ31

VSS

2 4

=MEM_A_DQ<4>

6

=MEM_A_DQ<5>

8 10

=MEM_A_DQS_N<0>

12

=MEM_A_DQS_P<0>

14 16

=MEM_A_DQ<6>

18

=MEM_A_DQ<7>

20 22

=MEM_A_DQ<12>

24

=MEM_A_DQ<13>

26 28

=MEM_A_DM<1>

30

MEM_RESET_L

32 34

=MEM_A_DQ<14>

36

=MEM_A_DQ<15>

38 40

=MEM_A_DQ<20>

42

=MEM_A_DQ<21>

44 46

=MEM_A_DM<2>

48 50

=MEM_A_DQ<22>

52

=MEM_A_DQ<23>

54 56

=MEM_A_DQ<28>

58

=MEM_A_DQ<29>

60 62

=MEM_A_DQS_N<3>

64

=MEM_A_DQS_P<3>

66 68

=MEM_A_DQ<30>

70

=MEM_A_DQ<31>=MEM_A_DQ<27>

72

Apple Inc.

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28

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28

BIBI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

IN

15 27

IN

28

BI

28

BI

28

BI

28

BI

28

IN

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

29 OF 109

SHEET

26 OF 76

SIZE

C

B

A

D

36

Page Notes

Power aliases required by this page:

- =PPLVDDR_S3_MEM_B

- =PPDDRVTT_S0_MEM_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V) Signal aliases required by this page:

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA BOM options provided by this page:

(NONE) NOTE: J3100 is OMITted on this page.

D

Proper APN(s) required elsewhere.

C

B

=PPSPD_S0_MEM_B

8

1

C3140

2.2UF

A

8 7 5 4 2 1

6.3V CERM

402-LF

20%

2

=PPDDRVTT_S0_MEM_B

8

MEM_B_CKE<0>

15 21 70

IN

MEM_B_BA<2>

15 70

IN

MEM_B_A<12>

15 70

IN

MEM_B_A<9>

15 70

IN

MEM_B_A<8>

15 70

IN

MEM_B_A<5>

15 70

IN

MEM_B_A<3>

15 70

IN

MEM_B_A<1>

15 70

IN

MEM_B_CLK_P<0>

15 70

IN

MEM_B_CLK_N<0>

15 70

IN

MEM_B_A<10>

15 70

IN

MEM_B_BA<0>

15 70

IN

MEM_B_WE_L

15 70

IN

MEM_B_CAS_L

15 70

IN

MEM_B_A<13>

15 70

IN

MEM_B_CS_L<1>

15 70

IN

=MEM_B_DQ<32>

28

BI

=MEM_B_DQ<33>

28

BI

=MEM_B_DQS_N<4>

28

BI

=MEM_B_DQS_P<4>

28

BI

=MEM_B_DQ<34>

28

BI

=MEM_B_DQ<35>

28

BI

=MEM_B_DQ<40>

28

BI

=MEM_B_DQ<41>

28

BI

=MEM_B_DM<5>

28

IN

=MEM_B_DQ<42>

28

BI

=MEM_B_DQ<43>

28

BI

=MEM_B_DQ<48>

28

BI

=MEM_B_DQ<49>

28

BI

=MEM_B_DQS_N<6>

28

BI

=MEM_B_DQS_P<6>

28

BI

=MEM_B_DQ<50>

28

BI

=MEM_B_DQ<51>

28

BI

=MEM_B_DQ<56>

28

BI

=MEM_B_DQ<57>

28

BI

=MEM_B_DM<7>

28

2

R3140

10K

5% 1/16W MF-LF 402

1

IN

28

BI

28

BI

=MEM_B_DQ<58> =MEM_B_DQ<59>

MEM_B_SA<0>

MEM_B_SA<1>

1

R3141

10K

5% 1/16W MF-LF 402

2

SPD Addr: 0xA2(Wr)/0xA3(Rd)

=PPLVDDR_S3_MEM_B

8

C3100

10UF

20%

6.3V X5R 603

73

CKE0

75 77

NC

79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125

NC

127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

209 210 211 212

CRITICAL

VDD NC

BA2

J3100

F-RT-BGA3

VDD A12/BC* A9

VDD A8 A5

VDD A3 A1

VDD CK0 CK0*

VDD A10/AP BA0

VDD WE* CAS*

VDD A13 S1*

VDD TEST

VSS DQ32 DQ33

VSS DQS4* DQS4

VSS DQ34 DQ35

VSS DQ40 DQ41

VSS DM5

VSS DQ42 DQ43

VSS DQ48 DQ49

VSS DQS6* DQS6

VSS DQ50 DQ51

VSS DQ56 DQ57

VSS DM7

VSS DQ58 DQ59

VSS SA0 VDDSPD SA1

VTT

MTG PINS

MTG PIN

MTG PIN MTG PIN

MTG PIN

Foxconn: 516s0706 Molex: 516s0790

1

2

KEY

OMIT

(2 OF 2)

DDR3-SODIMM

VREFCA

EVENT*

MTG PIN

C3101

10UF

CKE1

VDD

A15 A14

VDD

A11

A7

VDD

A6 A4

VDD

A2 A0

VDD

CK1

CK1*

VDD

BA1

RAS*

VDD

S0*

ODT0

VDD

ODT1

NC

VDD

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5*

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7*

DQS7

VSS DQ62 DQ63

VSS

SDA SCL

VTT

6.3V

20% X5R

603

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208207

345678

2 1

DDR3 Plane Stitching Caps (Space evenly across plane split)

1

2

C3110

0.1UF

20%

2

10V

1

CERM 402

2

C3111

0.1UF

20% 10V

1

CERM 402

2

C3112

0.1UF

20% 10V

1

CERM 402

2

C3113

0.1UF

20% 10V

1

CERM 402

2

C3114

0.1UF

20% 10V

1

CERM 402

2

C3115

0.1UF

20% 10V

1

CERM 402

2

C3116

0.1UF

20% 10V

1

CERM 402

2

C3117

0.1UF

20% 10V

1

CERM 402

2

C3118

0.1UF

20% 10V

1

CERM 402

2

C3119

0.1UF

20% 10V

1

CERM 402

2

C3120

0.1UF

20% 10V

1

CERM 402

2

C3121

0.1UF

20% 10V

1

CERM 402

2

C3122

0.1UF

20% 10V

1

CERM 402

2

C3123

0.1UF

20% 10V

1

CERM 402

D

"Expansion" (bottom) slot

PPVREF_S3_MEM_VREFDQ_B

NC

MEM_B_CKE<1>

MEM_B_A<15> MEM_B_A<14>

MEM_B_A<11> MEM_B_A<7>

MEM_B_A<6> MEM_B_A<4>

MEM_B_A<2> MEM_B_A<0>

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_CS_L<0> MEM_B_ODT<0>

MEM_B_ODT<1>

=MEM_B_DQ<36> =MEM_B_DQ<37>

=MEM_B_DM<4>

=MEM_B_DQ<38> =MEM_B_DQ<39>

=MEM_B_DQ<44> =MEM_B_DQ<45>

=MEM_B_DQS_N<5> =MEM_B_DQS_P<5>

=MEM_B_DQ<46> =MEM_B_DQ<47>

=MEM_B_DQ<52> =MEM_B_DQ<53>

=MEM_B_DM<6>

=MEM_B_DQ<54> =MEM_B_DQ<55>

=MEM_B_DQ<60> =MEM_B_DQ<61>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_B_DQ<62> =MEM_B_DQ<63>

MEM_EVENT_L =I2C_SODIMMB_SDA =I2C_SODIMMB_SCL

C3136

0.1UF

CERM

20% 10V

402

29

PPVREF_S3_MEM_VREFCA_B

1

C3135

2.2UF

20%

6.3V

212

CERM 402-LF

C3130

2.2UF

20%

6.3V CERM

402-LF

1

C3131

0.1UF

20% 10V

2

CERM 402

29

=MEM_B_DQ<0>

28

=MEM_B_DQ<1>

28

BI

=MEM_B_DM<0>

28

IN

=MEM_B_DQ<2>

28

BI

=MEM_B_DQ<3>

28

BI

=MEM_B_DQ<8>

28

BI

=MEM_B_DQ<9>

28

BI

=MEM_B_DQS_N<1>

28

BI

=MEM_B_DQS_P<1>

28

BI

=MEM_B_DQ<10>

28

BI

=MEM_B_DQ<11>

28

BI

=MEM_B_DQ<16>

28

BI

=MEM_B_DQ<17>

28

BI

=MEM_B_DQS_N<2>

28

BI

=MEM_B_DQS_P<2>

28

BI

=MEM_B_DQ<18>

28

BI

=MEM_B_DQ<19>

28

BI

=MEM_B_DQ<24>

28

BI

=MEM_B_DQ<25>

28

BI

=MEM_B_DM<3>

28

IN

=MEM_B_DQ<26>

28

BI

=MEM_B_DQ<27>

28

BI

15 21 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

15 70

IN

28

BI

28

BI

28

IN

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

IN

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

19 26 35

OUT

38

BI

38

IN

1

VREFDQ

3

VSS

5

DQ0 DQ1

VSS

DM0

VSS DQ2 DQ3

VSS DQ8 DQ9

VSS DQS1* DQS1

VSS DQ10 DQ11

VSS DQ16 DQ17

VSS DQS2* DQS2

VSS DQ18 DQ19

VSS DQ24 DQ25

VSS DM3

VSS DQ26 DQ27

VSS

CRITICAL

J3100

F-RT-BGA3

7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71

OMIT

(1 OF 2)

DDR3-SODIMM

RESET*

KEY

DQ4 DQ5

DQS0*

DQS0

VSS

DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3*

DQS3

VSS DQ30 DQ31

VSS

Foxconn: 516s0706 Molex: 516s0790

SYNC_MASTER=T27_MLB

PAGE TITLE

DDR3 SO-DIMM Connector B

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

2 4

=MEM_B_DQ<4>

6

=MEM_B_DQ<5>

8 10

=MEM_B_DQS_N<0>

12

=MEM_B_DQS_P<0>

14 16

=MEM_B_DQ<6>

18

=MEM_B_DQ<7>

20 22

=MEM_B_DQ<12>

24

=MEM_B_DQ<13>

26 28

=MEM_B_DM<1>

30

MEM_RESET_L

32 34

=MEM_B_DQ<14>

36

=MEM_B_DQ<15>

38 40

=MEM_B_DQ<20>

42

=MEM_B_DQ<21>

44 46

=MEM_B_DM<2>

48 50

=MEM_B_DQ<22>

52

=MEM_B_DQ<23>

54 56

=MEM_B_DQ<28>

58

=MEM_B_DQ<29>

60 62

=MEM_B_DQS_N<3>

64

=MEM_B_DQS_P<3>

66 68

=MEM_B_DQ<30>

70

=MEM_B_DQ<31>

72

Apple Inc.

R

28

BI

28

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28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

IN

15 26

IN

28

BI

28

BI

28

BI

28

BI

28

IN

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

28

BI

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

31 OF 109

SHEET

27 OF 76

SIZE

C

B

A

D

36

345678

Host Partition A 0 -> SO-DIMM A 0

MEM_A_DQS_P<0>

15 70

BI

MEM_A_DQS_N<0>

15 70

BI

MEM_A_DM<0>

15 70

IN

MEM_A_DQ<0>

15 70

BI

MEM_A_DQ<1>

15 70

BI

MEM_A_DQ<2>

15 70

BI

MEM_A_DQ<3>

15 70

BI

MEM_A_DQ<4>

15 70

BI

MEM_A_DQ<5>

15 70

BI

MEM_A_DQ<6>

15 70

BI

MEM_A_DQ<7>

15 70

D

C

B

A

BI

HOST PARTITION A 1 -> SO-DIMM A 1

MEM_A_DQS_P<1>

15 70

BI

MEM_A_DQS_N<1>

15 70

BI

MEM_A_DM<1>

15 70

IN

MEM_A_DQ<8>

15 70

BI

MEM_A_DQ<9>

15 70

BI

MEM_A_DQ<10>

15 70

BI

MEM_A_DQ<11>

15 70

BI

MEM_A_DQ<12>

15 70

BI

MEM_A_DQ<13>

15 70

BI

MEM_A_DQ<14>

15 70

BI

MEM_A_DQ<15>

15 70

BI

HOST PARTITION A 2 -> SO-DIMM A 3

MEM_A_DQS_P<2>

15 70

BI

MEM_A_DQS_N<2>

15 70

BI

MEM_A_DM<2>

15 70

IN

MEM_A_DQ<16>

15 70

BI

MEM_A_DQ<17>

15 70

BI

MEM_A_DQ<18>

15 70

BI

MEM_A_DQ<19>

15 70

BI

MEM_A_DQ<20>

15 70

BI

MEM_A_DQ<21>

15 70

BI

MEM_A_DQ<22>

15 70

BI

MEM_A_DQ<23>

15 70

BI

HOST PARTITION A 3 -> SO-DIMM A 2

MEM_A_DQS_P<3>

15 70

BI

MEM_A_DQS_N<3>

15 70

BI

MEM_A_DM<3>

15 70

IN

MEM_A_DQ<24>

15 70

BI

MEM_A_DQ<25>

15 70

BI

MEM_A_DQ<26>

15 70

BI

MEM_A_DQ<27>

15 70

BI

MEM_A_DQ<28>

15 70

BI

MEM_A_DQ<29>

15 70

BI

MEM_A_DQ<30>

15 70

BI

MEM_A_DQ<31>

15 70

BI

Host Partition A 4 -> SO-DIMM A 4

MEM_A_DQS_P<4>

15 70

BI

MEM_A_DQS_N<4>

15 70

BI

MEM_A_DM<4>

15 70

IN

MEM_A_DQ<32>

15 70

BI

MEM_A_DQ<33>

15 70

BI

MEM_A_DQ<34>

15 70

BI

MEM_A_DQ<35>

15 70

BI

MEM_A_DQ<36>

15 70

BI

MEM_A_DQ<37>

15 70

BI

MEM_A_DQ<38>

15 70

BI

MEM_A_DQ<39>

15 70

BI

Host Partition A 5 -> SO-DIMM A 5

MEM_A_DQS_P<5>

15 70

BI

MEM_A_DQS_N<5>

15 70

BI

MEM_A_DM<5>

15 70

IN

MEM_A_DQ<40>

15 70

BI

MEM_A_DQ<41>

15 70

BI

MEM_A_DQ<42>

15 70

BI

MEM_A_DQ<43>

15 70

BI

MEM_A_DQ<44>

15 70

BI

MEM_A_DQ<45>

15 70

BI

MEM_A_DQ<46>

15 70

BI

MEM_A_DQ<47>

15 70

BI

Host Partition A 6 -> SO-DIMM A 6 Host Partition B 6 -> SO-DIMM B 6

MEM_A_DQS_P<6>

15 70

BI

MEM_A_DQS_N<6>

15 70

BI

MEM_A_DM<6>

15 70

IN

MEM_A_DQ<48>

15 70

BI

MEM_A_DQ<49>

15 70

BI

MEM_A_DQ<50>

15 70

BI

MEM_A_DQ<51>

15 70

BI

MEM_A_DQ<52>

15 70

BI

MEM_A_DQ<53>

15 70

BI

MEM_A_DQ<54>

15 70

BI

MEM_A_DQ<55>

15 70

BI

MEM_A_DQS_P<7>

15 70

BI

MEM_A_DQS_N<7>

15 70

BI

MEM_A_DM<7>

15 70

IN

MEM_A_DQ<56>

15 70

BI

MEM_A_DQ<57>

15 70

BI

MEM_A_DQ<58>

15 70

BI

MEM_A_DQ<59>

15 70

BI

MEM_A_DQ<60>

15 70

BI

MEM_A_DQ<61>

15 70

BI

MEM_A_DQ<62>

15 70

BI

15 70

BI

MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

=MEM_A_DQS_P<0> =MEM_A_DQS_N<0>

=MEM_A_DM<0> =MEM_A_DQ<0> =MEM_A_DQ<1> =MEM_A_DQ<3> =MEM_A_DQ<2> =MEM_A_DQ<4> =MEM_A_DQ<5> =MEM_A_DQ<6> =MEM_A_DQ<7>

=MEM_A_DQS_P<1> =MEM_A_DQS_N<1> =MEM_A_DM<1>

=MEM_A_DQ<12> =MEM_A_DQ<8> =MEM_A_DQ<15> =MEM_A_DQ<10> =MEM_A_DQ<13> =MEM_A_DQ<9> =MEM_A_DQ<11> =MEM_A_DQ<14>

=MEM_A_DQS_P<3> =MEM_A_DQS_N<3> =MEM_A_DM<3>

=MEM_A_DQ<24> =MEM_A_DQ<30> =MEM_A_DQ<26> =MEM_A_DQ<27> =MEM_A_DQ<29> =MEM_A_DQ<28> =MEM_A_DQ<25> =MEM_A_DQ<31>

=MEM_A_DQS_P<2> =MEM_A_DQS_N<2> =MEM_A_DM<2>

=MEM_A_DQ<17> =MEM_A_DQ<20> =MEM_A_DQ<23> =MEM_A_DQ<18> =MEM_A_DQ<22> =MEM_A_DQ<21> =MEM_A_DQ<16> =MEM_A_DQ<19>

=MEM_A_DQS_P<4> =MEM_A_DQS_N<4> =MEM_A_DM<4>

=MEM_A_DQ<33> =MEM_A_DQ<32> =MEM_A_DQ<34> =MEM_A_DQ<35> =MEM_A_DQ<36> =MEM_A_DQ<37> =MEM_A_DQ<38> =MEM_A_DQ<39>

=MEM_A_DQS_P<5> =MEM_A_DQS_N<5> =MEM_A_DM<5>

=MEM_A_DQ<45> =MEM_A_DQ<41> =MEM_A_DQ<43> =MEM_A_DQ<47> =MEM_A_DQ<40> =MEM_A_DQ<42> =MEM_A_DQ<46> =MEM_A_DQ<44>

=MEM_A_DQS_P<6> =MEM_A_DQS_N<6> =MEM_A_DM<6>

=MEM_A_DQ<52> =MEM_A_DQ<55> =MEM_A_DQ<54> =MEM_A_DQ<49> =MEM_A_DQ<48> =MEM_A_DQ<53> =MEM_A_DQ<51> =MEM_A_DQ<50>

=MEM_A_DQS_P<7> =MEM_A_DQS_N<7> =MEM_A_DM<7>

=MEM_A_DQ<61> =MEM_A_DQ<60> =MEM_A_DQ<58> =MEM_A_DQ<59> =MEM_A_DQ<57> =MEM_A_DQ<56> =MEM_A_DQ<62> =MEM_A_DQ<63>

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8 7 5 4 2 1

Host Partition B 0 -> SO-DIMM B 0

MEM_B_DQS_P<0>

15 70

BI

MEM_B_DQS_N<0>

15 70

BI

MEM_B_DM<0>

15 70

IN

MEM_B_DQ<0>

15 70

BI

MEM_B_DQ<1>

15 70

BI

MEM_B_DQ<2>

15 70

BI

MEM_B_DQ<3>

15 70

BI

MEM_B_DQ<4>

15 70

BI

MEM_B_DQ<5>

15 70

BI

MEM_B_DQ<6>

15 70

BI

MEM_B_DQ<7>

15 70

BI

Host Partition B 1 -> SO-DIMM B 2

MEM_B_DQS_P<1>

15 70

BI

MEM_B_DQS_N<1>

15 70

BI

MEM_B_DM<1>

15 70

IN

MEM_B_DQ<8>

15 70

BI

MEM_B_DQ<9>

15 70

BI

MEM_B_DQ<10>

15 70

BI

MEM_B_DQ<11>

15 70

BI

MEM_B_DQ<12>

15 70

BI

MEM_B_DQ<13>

15 70

BI

MEM_B_DQ<14>

15 70

BI

MEM_B_DQ<15>

15 70

BI

Host Partition B 2 -> SO-DIMM B 3

MEM_B_DQS_P<2>

15 70

BI

MEM_B_DQS_N<2>

15 70

BI

MEM_B_DM<2>

15 70

IN

MEM_B_DQ<16>

15 70

BI

MEM_B_DQ<17>

15 70

BI

MEM_B_DQ<18>

15 70

BI

MEM_B_DQ<19>

15 70

BI

MEM_B_DQ<20>

15 70

BI

MEM_B_DQ<21>

15 70

BI

MEM_B_DQ<22>

15 70

BI

MEM_B_DQ<23>

15 70

BI

Host Partition B 3 -> SO-DIMM B 1

MEM_B_DQS_P<3>

15 70

BI

MEM_B_DQS_N<3>

15 70

BI

MEM_B_DM<3>

15 70

IN

MEM_B_DQ<24>

15 70

BI

MEM_B_DQ<25>

15 70

BI

MEM_B_DQ<26>

15 70

BI

MEM_B_DQ<27>

15 70

BI

MEM_B_DQ<28>

15 70

BI

MEM_B_DQ<29>

15 70

BI

MEM_B_DQ<30>

15 70

BI

MEM_B_DQ<31>

15 70

BI

Host Partition B 4 -> SO-DIMM B 4

MEM_B_DQS_P<4>

15 70

BI

MEM_B_DQS_N<4>

15 70

BI

MEM_B_DM<4>

15 70

IN

MEM_B_DQ<32>

15 70

BI

MEM_B_DQ<33>

15 70

BI

MEM_B_DQ<34>

15 70

BI

MEM_B_DQ<35>

15 70

BI

MEM_B_DQ<36>

15 70

BI

MEM_B_DQ<37>

15 70

BI

MEM_B_DQ<38>

15 70

BI

MEM_B_DQ<39>

15 70

BI

Host Partition B 5 -> SO-DIMM B 5

MEM_B_DQS_P<5>

15 70

BI

MEM_B_DQS_N<5>

15 70

BI

MEM_B_DM<5>

15 70

IN

MEM_B_DQ<40>

15 70

BI

MEM_B_DQ<41>

15 70

BI

MEM_B_DQ<42>

15 70

BI

MEM_B_DQ<43>

15 70

BI

MEM_B_DQ<44>

15 70

BI

MEM_B_DQ<45>

15 70

BI

MEM_B_DQ<46>

15 70

BI

MEM_B_DQ<47>

15 70

BI

MEM_B_DQS_P<6>

15 70

BI

MEM_B_DQS_N<6>

15 70

BI

MEM_B_DM<6>

15 70

IN

MEM_B_DQ<48>

15 70

BI

MEM_B_DQ<49>

15 70

BI

MEM_B_DQ<50>

15 70

BI

MEM_B_DQ<51>

15 70

BI

MEM_B_DQ<52>

15 70

BI

MEM_B_DQ<53>

15 70

BI

MEM_B_DQ<54>

15 70

BI

MEM_B_DQ<55>

15 70

BI

Host Partition B 7 -> SO-DIMM B 7Host Partition A 7 -> SO-DIMM A 7

MEM_B_DQS_P<7>

15 70

BI

MEM_B_DQS_N<7>

15 70

BI

MEM_B_DM<7>

15 70

IN

MEM_B_DQ<56>

15 70

BI

MEM_B_DQ<57>

15 70

BI

MEM_B_DQ<58>

15 70

BI

MEM_B_DQ<59>

15 70

BI

MEM_B_DQ<60>

15 70

BI

MEM_B_DQ<61>

15 70

BI

MEM_B_DQ<62>

15 70

BI

MEM_B_DQ<63>MEM_A_DQ<63>

15 70

BI

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE

=MEM_B_DQS_P<0> =MEM_B_DQS_N<0> =MEM_B_DM<0>

=MEM_B_DQ<0> =MEM_B_DQ<1> =MEM_B_DQ<2> =MEM_B_DQ<3> =MEM_B_DQ<4> =MEM_B_DQ<5> =MEM_B_DQ<6> =MEM_B_DQ<7>

=MEM_B_DQS_P<2> =MEM_B_DQS_N<2> =MEM_B_DM<2>

=MEM_B_DQ<17> =MEM_B_DQ<16> =MEM_B_DQ<19> =MEM_B_DQ<23> =MEM_B_DQ<21> =MEM_B_DQ<20> =MEM_B_DQ<22> =MEM_B_DQ<18>

=MEM_B_DQS_P<3> =MEM_B_DQS_N<3> =MEM_B_DM<3>

=MEM_B_DQ<29> =MEM_B_DQ<25> =MEM_B_DQ<26> =MEM_B_DQ<30> =MEM_B_DQ<28> =MEM_B_DQ<24> =MEM_B_DQ<27> =MEM_B_DQ<31>

=MEM_B_DQS_P<1> =MEM_B_DQS_N<1> =MEM_B_DM<1>

=MEM_B_DQ<9> =MEM_B_DQ<13> =MEM_B_DQ<14> =MEM_B_DQ<15> =MEM_B_DQ<8> =MEM_B_DQ<12> =MEM_B_DQ<11> =MEM_B_DQ<10>

=MEM_B_DQS_P<4> =MEM_B_DQS_N<4> =MEM_B_DM<4>

=MEM_B_DQ<32> =MEM_B_DQ<36> =MEM_B_DQ<34> =MEM_B_DQ<35> =MEM_B_DQ<37> =MEM_B_DQ<33> =MEM_B_DQ<38> =MEM_B_DQ<39>

=MEM_B_DQS_P<5> =MEM_B_DQS_N<5> =MEM_B_DM<5>

=MEM_B_DQ<41> =MEM_B_DQ<40> =MEM_B_DQ<43> =MEM_B_DQ<42> =MEM_B_DQ<44> =MEM_B_DQ<45> =MEM_B_DQ<47> =MEM_B_DQ<46>

=MEM_B_DQS_P<6> =MEM_B_DQS_N<6> =MEM_B_DM<6>

=MEM_B_DQ<52> =MEM_B_DQ<49> =MEM_B_DQ<55> =MEM_B_DQ<51> =MEM_B_DQ<50> =MEM_B_DQ<54> =MEM_B_DQ<53> =MEM_B_DQ<48>

=MEM_B_DQS_P<7> =MEM_B_DQS_N<7> =MEM_B_DM<7>

=MEM_B_DQ<56> =MEM_B_DQ<57> =MEM_B_DQ<62> =MEM_B_DQ<59> =MEM_B_DQ<60> =MEM_B_DQ<61> =MEM_B_DQ<63> =MEM_B_DQ<58>

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36

2 1

SYNC_MASTER=MASTER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SO-DIMM Pinswaps

Apple Inc.

R

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

32 OF 109

SHEET

28 OF 76

SIZE

D

C

B

A

D

345678

2 1

=PP3V3_S3_VREFMRGN

8

OMIT

R3300

SHORT

1 2

D

OMIT

R3310

SHORT

1 2

C

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

116S0004 CRITICAL

B

116S0004 CRITICAL

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm

NONE

MIN_NECK_WIDTH=0.2 mm

NONE

VOLTAGE=3.3V

NONE

402

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm

NONE

MIN_NECK_WIDTH=0.2 mm

NONE

VOLTAGE=3.3V

NONE

402

QTY

2 2

VREFMRGN:YES

C3300

2.2UF

20%

6.3V CERM

402-LF

=I2C_VREFDACS_SCL

38

IN

=I2C_VREFDACS_SDA

38

BI

Addr=0x98(WR)/0x99(RD)

VREFMRGN:YES

Addr=0x30(WR)/0x31(RD)

=I2C_PCA9557D_SCL

38

IN

=I2C_PCA9557D_SDA

38

BI

PCA9557D_RESET_L

25

IN

RST* on ’platform reset’ so that system watchdog will disable margining.

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

DESCRIPTION

RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF

1

2

C3310

0.1UF

CERM

VREFMRGN:YES

1

C3301

0.1UF

20% 10V

2

CERM 402

10

1

20% 10V

2

402

3 4 5

1 2

REFERENCE DES

8

VDD

SCL

MSOP

7

SDA

9

A0

A1

GND

3

VCC

U3310

PCA9557

QFN

A0 A1 A2

SCL SDA

THRM

GND

PAD

17

R3331,R3333

CRITICAL VREFMRGN:YES

U3300

16

VOUTA

2

VOUTB

4

VOUTC

5

VOUTD

DAC5574

CRITICAL VREFMRGN:YES

16

6

(OD)

P0

7

P1

9

P2

10

P3

11

P4

12

P5

13

P6

14

P7

RESET*

8

VREFMRGN_SODIMMA_DQ VREFMRGN_SODIMMB_DQ VREFMRGN_SODIMMS_CA VREFMRGN_MEMVREG_FBVREF

NOTE: MEMVREG and FRAMEBUF share a DAC output, cannot enable both at the same time!

NC

VREFMRGN_DQ_SODIMMA_EN VREFMRGN_DQ_SODIMMB_EN VREFMRGN_CA_SODIMMA_EN VREFMRGN_CA_SODIMMB_EN VREFMRGN_MEMVREG_EN

(RSVD for FBVREF)

NC

VREFMRGN_CPUGTLREF_EN

15

CRITICAL

BOM OPTION

VREFMRGN:NOR3321,R3323 VREFMRGN:NO

VREFMRGN:YES

1

R3320

100K

5% 1/16W MF-LF 402

2

VREFMRGN:YES

1

R3325

100K

5% 1/16W MF-LF 402

VREFMRGN:YES

2

VREFMRGN:YES

1

R3330

100K

5% 1/16W MF-LF 402

2

VREFMRGN:YES

1

R3335

100K

5%

VREFMRGN:YES

1/16W MF-LF 402

2

C3320

0.1UF

20% 10V

CERM

402

C3330

0.1UF

20% 10V

CERM

402

C3340

0.1UF

20% 10V

CERM

402

1

2

1

2

1

2

B1

V+

V-

B4

B1

V+

V-

B4

B1

V+

V-

B4

B1

V+

V-

B4

B1

V+

V-

B4

U3320

MAX4253

UCSP

A1

VREFMRGN:YES

A4

U3320

MAX4253

UCSP

C1

VREFMRGN:YES

C4

U3330

MAX4253

UCSP

A1

VREFMRGN:YES

A4

U3330

MAX4253

UCSP

C1

VREFMRGN:YES

C4

U3340

MAX4253

UCSP

C1

VREFMRGN:YES

C4

A2

A3

C2

C3

A2

A3

C2

C3

C2

C3

NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.

VREFMRGN:YES

=PPVTT_S3_DDR_BUF

8

57

10mA max load

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_MEMVREG_BUF

R3321

200

1 2

1% 1/16W MF-LF

402

VREFMRGN:YES

R3322

133

1 2

1% 1/16W MF-LF

402

VREFMRGN:YES

R3323

200

1 2

1% 1/16W MF-LF

402

VREFMRGN:YES

R3324

133

1 2

1% 1/16W MF-LF

402

VREFMRGN:YES

R3331

200

1 2

1% 1/16W MF-LF

402

VREFMRGN:YES

R3332

133

1 2

1% 1/16W MF-LF

402

VREFMRGN:YES

R3333

200

1 2

1% 1/16W MF-LF

402

VREFMRGN:YES

R3334

133

1 2

1% 1/16W MF-LF

402

VREFMRGN:YES

R3342

22.6K

1 2

1% 1/16W MF-LF

402

PLACE_NEAR=J2900.1:2.54mm

PPVREF_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3321.2:1mm

PLACE_NEAR=J3100.1:2.54mm

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3323.2:1mm

PLACE_NEAR=J2900.126:2.54mm

PPVREF_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3331.2:1mm

PLACE_NEAR=J3100.126:2.54mm

PPVREF_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

PLACE_NEAR=R3333.2:1mm

DDRREG_FB

PLACE_NEAR=R7320.2:1mm

26

D

27

26

27

57

OUT

C

B

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA BOM options provided by this page:

VREFMRGN:YES - Stuffs VREF Margining Circuitry. VREFMRGN:NO - Bypasses VREF Margining Circuitry.

A

DAC Channel: PCA9557D Pin: Nominal value Margined target: DAC range: VRef current: DAC step size:

8 7 5 4 2 1

MEM A VREF DQ

A 1 2

MEM B VREF DQ

B

MEM A VREF CA

C 3

0.75V (DAC: 0x3A)

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced)

7.69mV / step @ output

MEM B VREF CA

C 4

VREFMRGN:YES

1

R3340

100K

5% 1/16W MF-LF 402

2

VREFMRGN:YES

1

R3345

100K

5% 1/16W MF-LF 402

2

MEM VREG

D 5

1.5V (DAC: 0x3A)

1.998V - 1.002V (+/- 498mV)

0.000V - 1.501V (0x00 - 0x74)

0.7V (DAC: 0x8B)

0.200V - 1.050V (+/- 500mV)

0.000V - 1.191V (0x00 - 0x5C)

B1

V+

V-

B4

U3340

MAX4253

UCSP

A1

VREFMRGN:YES

A4

A2

A3

CPU GTLREF (FSB)

D 7

VREFMRGN_CPUGTLREF_BUF

+33uA - -33uA (- = sourced) +750uA - -528uA (- = sourced)

8.59mV / step @ output

9.24mV / step @ output

36

VREFMRGN:YES

R3344

267

1 2

1% 1/16W MF-LF

402

CPU_GTLREF

PLACE_NEAR=R1005.2:1mm

SYNC_MASTER=T27_MLB

PAGE TITLE

FSB/DDR3 Vref Margining

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

10 69

OUT

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

33 OF 109

SHEET

29 OF 76

SIZE

A

D

345678

2 1

D

PCIE_WAKE_L

PLACE_NEAR=J3401.15:2MM

C3431

0.1uF

CONN_PCIE_MINI_R2D_P

7 9

75

CONN_PCIE_MINI_R2D_N

7 9

75

516S0582

CRITICAL

J3401

500913-0302

F-ST-SM

32

C

(AP_RESET_CONN_L)

(AP_CLKREQ_Q_L)

NC NC

31

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

34

33

PCIE_CLK100M_MINI_CONN_P

7

75

PCIE_CLK100M_MINI_CONN_N

7

75

CONN_USB2_BT_P

7

75

CONN_USB2_BT_N

7

75

PP3V3_S3_BT_F

7

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

C3432

0.01UF

10% 16V

PLACE_NEAR=L3406.1:2MM

2

CERM 402

PLACE_NEAR=J3401.11:2MM

PLACE_NEAR=J3401.23:2MM

1 2

16V10% 402X5R

0.1uF

1 2

X5R 40210% 16V

C3430

PLACE_NEAR=J3401.17:2MM

CRITICAL

L3401

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

1 2

CRITICAL

L3403

90-OHM

DLP0NS

SYM_VER-1

4 3

1 2

L3406

2 1

FERR-120-OHM-1.5A

0402-LF

PLACE_NEAR=J3401.27:2MM

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

CONN_PCIE_MINI_D2R_P

CONN_PCIE_MINI_D2R_N

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

USB_BT_P

USB_BT_N

B

PP3V3_WLAN_F

121

R3440

100K

1/16W MF-LF

A

R3453

232K

1%

5%

1/16W MF-LF 402

402

2

P3V3WLAN_VMON

AP_RESET_CONN_L

7

DLY = 60 ms +/- 20%

AP_CLKREQ_Q_L

7

1

R3454

100K

1% 1/16W MF-LF 402

2

DO NOT SYNC WITH K84. CHANGED MINI_RESET_CONN_L CIRCUIT FROM SCHMITT TRIGGER TO SLG PART COPIED FROM K69. R3453 IS DIFFERENT FROM K6

30 46

Supervisor & CLKREQ# Isolation

CRITICAL

2

4

7

1

VDD

U3440

SLG4AP016V

TDFN

SENSE

+

-

0.7V

THRM

PAD

DLY

GND

9

RESET*

IN

3

MR*

6

EN

8

OUT

(OD)

5

=PP3V3_S3_WLAN

1

C3440

0.1uF

20% 10V

2

CERM 402

AP_RESET_L

AP_PWR_EN AP_CLKREQ_L

8

30

25

IN

19 62

IN

16

OUT

8 7 5 4 2 1

=PP3V3_S3_BT

D

7

16

OUT

9

IN

9

IN

7 9

75

OUT

7 9

75

AIRPORT

C

9

IN

9

IN

18 72

BI

BLUETOOTH

18 72

BI

SENS_R:ENG

8

727 MA PEAK

606 MA NOMINAL MAX

PP3V3_WLAN

7

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V

C3422

0.1uF

PLACE_NEAR=J3401.29:2MM

20% 10V

CERM

402

155S0367

L3404

FERR-120-OHM-3A

0603

1

C3421

0.1uF

20%

2

10V

CERM

402

PLACE_NEAR=Q3450.5:2MM

21

PLACE_NEAR=Q3450.7:2MM

1

2

PP3V3_WLAN_F

30 46

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V

1

C3420

10UF

20% 10V

2

X5R 805

CRITICAL

R3452

0.002

1%

1/4W

MF

1206

21

PP3V3_WLAN_R

MIN_LINE_WIDTH=1 mm

43

MIN_NECK_WIDTH=0.5 mm VOLTAGE=3.3V

ISNS_AIRPORT_P ISNS_AIRPORT_N

PART NUMBER

101S0245

QTY

RES,0OHM,5%,1/4W,MF-LF,1206

1

3V S3 WLAN FET

MOSFET CHANNEL RDS(ON) LOADING

DESCRIPTION

CRITICAL

Q3450

TPCP8102

23V1K-SM

7 85 6

C3450

0.1UF

1 2

10% 16V X5R 402

TPCP8102 P-TYPE 20-30 MOHM @2.5V

0.727 A (EDP)

S

D

G 4

C3451

0.033UF

P3V3WLAN_SS

46 75

OUT

46 75

OUT

REFERENCE DES

31 2

1

10% 16V

2

X5R 402

R3450

R3452

SYNC_MASTER=MASTER

PAGE TITLE

33K

1 2

5% 1/16W MF-LF

402

CRITICAL

=PP3V3_S3_WLAN

1

R3451

10K

5% 1/16W MF-LF 402

2

PM_WLAN_EN_L

BOM OPTION

SENS_R:PROD

X16 WIRELESS CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8

30

62

IN

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

34 OF 109

SHEET

30 OF 76

SIZE

B

A

D

36

345678

2 1

D

(43mA typ - 1000base-T)

WF: Marvell numbers, update for Realtek

(19mA typ - Energy Detect)

C

ENET_CLK125M_TXCLK

9

73

IN

ENET_RESET_L

9

73

IN

ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE.

B

HENCE, RC (C3725 AND R3725) ARE NOT STUFFED.

=PP3V3_ENET_PHY

8 9

R3796

0

1 2

5% 1/16W 402 MF-LF

R3724

1 2

1

CRITICAL

L3705

FERR-120-OHM-1.5A

0402-LF

2

PP3V3_ENET_PHYAVDD

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.

ENET_CLK125M_TXCLK_R

73

0

5% 1/16W MF-LF

402

NO STUFF

1

C3725

0.1UF

20% 10V

2

CERM 402

R3730

2.49K

1/16W MF-LF

402

1

1%

2

1

2

=RTL8211_ENSWREG

9

IN

ENET_TXD<0>

9

73

IN

ENET_TXD<1>

9

73

IN

ENET_TXD<2>

9

73

IN

ENET_TXD<3>

9

73

IN

ENET_TX_CTRL

9

73

IN

ENET_MDC

9

73

IN

ENET_MDIO

18 73

BI

RTL8211_PHYRST_L

RTL8211_RSET

RTL8211_CLK125

RTL8211_CLK25M_CKXTAL1

31 73

IN

TP_RTL8211_CKXTAL2

R3731

22

5% 1/16W MF-LF 402

PLACE_NEAR=U3700.15:1.5 MM

1

C3700

0.1UF

10% 16V

2

X5R 402

PLACE_NEAR=U3700.6:1.5 MM

1

C3705

0.1UF

10% 16V

2

X5R 402

R3720

PLACE_NEAR=U3700.21:1.5 MM

1

C3701

0.1UF

10% 16V

2

X5R 402

PLACE_NEAR=U3700.41:1.5 MM

1

C3706

0.1UF

10% 16V

2

X5R 402

10K

5% 1/16W MF-LF

402

2

PLACE_NEAR=U3700.37:1.5 MM

NO STUFF

121

R3725

4.7K

5% 1/16W MF-LF 402

39

22

23 24 25 26

27

30 31

29

46

32

42 43

1

C3702

0.1UF

10% 16V

2

X5R 402

ENSWREG

TXC

TXD[0] TXD[1] TXD[2] TXD[3]

TXCTL

MDC MDIO

PHYRSTB*

RSET

CLK125

CKXTAL1 CKXTAL2

6

41

AVDD33

C3714

2.2UF

10%

6.3V X5R 402

1521374445

DVDD33

VDDREG

CRITICAL

U3700

RTL8251CA-VB-GR

TQFP

RGMII/MII

MANAGEMENT

RESET

REFERENCE

CLOCK

GND

7

203347

ENET1V05:EXT

1

R3722

0

5%

2

1/16W MF-LF 402

2

3

FB10

MEDIA DEPENDENT

LED

40

10

36

28

AVDD10

DVDD10

REGOUT

RXD[0]

RXD[1]/TXDLY

RXD[2]/AN0 RXD[3]/AN1

RXCTL

MDI+[0] MDI-[0]

MDI+[1] MDI-[1]

MDI+[2] MDI-[2]

MDI+[3] MDI-[3]

LED0/PHYAD0 LED1/PHYAD1

LED2/RXDLY

Reserved for EMI per RealTek request.

PLACE_NEAR=U3700.28:1.5 MM

C3710

0.1UF

10% 16V X5R 402

C3715

2.2UF

10%

6.3V X5R 402

PP1V05_ENET_PHYAVDD_R

MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V

R3750

48

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

19

RXC

14 16 17 18

13

1 2

4 5

8 9

11 12

34 35 38

PLACE_NEAR=U3700.36:1.5 MM

1

C3711

0.1UF

10% 16V

2

X5R 402

1

C3716

0.1UF

10% 16V

2

X5R 402

121

402

R3751

4.7K

5%

5% 1/16W MF-LF 402

2

4.7K

1/16W MF-LF

RTL8211_REGOUT_L

73

NO STUFF

C3790

10PF

50V

CERM

402

1

5%

2

1

2

FERR-120-OHM-1.5A

PP1V05_ENET_PHYAVDD

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

1

PLACE_NEAR=U3700.10:1.5 MM

2

PLACE_NEAR=C3721.1:3 MM

ENET1V05:INT

402 5%

0

DIDT=TRUE

CRITICAL

L3715

R3721

1 2

MF-LF

1/16W

CRITICAL

ENET1V05:INT

L3720

4.7UH-0.91A

PLE031B-SM

PLACE_NEAR=U3700.48:5 MM

ENET_CLK125M_RXCLK_R

ENET_RXD_R<0> ENET_RXD_R<1> ENET_RXD_R<2> ENET_RXD_R<3>

ENET_MDI_P<0> ENET_MDI_N<0>

ENET_MDI_P<1> ENET_MDI_N<1>

ENET_MDI_P<2> ENET_MDI_N<2>

ENET_MDI_P<3> ENET_MDI_N<3>

RTL8211_PHYAD0 RTL8211_PHYAD1 RTL8211_RXDLY

1

R3755

4.7K

5% 1/16W MF-LF

402

2

=PP1V05_ENET_PHY

(221mA typ - 1000base-T) ( 7mA typ - Energy Detect)

1

WF: Marvell numbers, update for Realtek

0402-LF

PLACE_NEAR=U3700.45:5 MM

ENET1V05:INT

R3752

BI BI

R3756

21

4.7K

1/16W MF-LF

32 73

4.7K

1/16W MF-LF

C3723

5%

402

5%

402

PLACE_NEAR=U3700.36:5 MM PLACE_NEAR=U3700.28:5 MM

2

0.1UF

10% 16V X5R 402

1

2

1

2

1

2

PLACE_NEAR=L3720.2:5 MM

ENET1V05:INT

C3721

R3790 R3791

R3792 R3793 R3794

R3795

1

R3757

4.7K

5% 1/16W MF-LF 402

2

8

ENET1V05:INT

1

C3722

22UF

20%

6.3V

2

CERM-X5R 805

PLACE_NEAR=U3700.44:5 MM

1

0.1UF

10% 16V

2

X5R 402

1 2

0

1 2

0

1 2

0

1 2

0

1 2

0

1 2

0

=PP3V3_ENET_PHY_VDDREG

If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

8

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor. If internal switcher is not used, VDDREG and REGOUT can float.

ENET1V05:INT

1

C3720

22UF

20%

6.3V

2

CERM-X5R 805

PLACE_NEAR=L3720.2:5 MM

5%

5% 5% 5% 5%

5%

MF-LF1/16W

MF-LF1/16W MF-LF1/16W MF-LF1/16W MF-LF1/16W

1/16W MF-LF

=RTL8211_REGOUT

ENET_CLK125M_RXCLK

402

ENET_RXD<0>

402

ENET_RXD<1>

402

ENET_RXD<2>

402

ENET_RXD<3>

402

ENET_RX_CTRLENET_RXCTL_R

402

8

18 73

OUT

18 73

OUT

18 73

OUT

18 73

OUT

18 73

OUT

18 73

OUT

D

C

B

NOTE: MCP89 CAN PROVIDE 25MHZ CLOCK, BUT CLOCK RUNS WHENEVER RMGT RAILS ARE POWERED. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

A

Configuration Settings:

PHYAD = 01 (PHY Address 00001) AN[1:0] = 11 (Full auto-negotiation) RXDLY = 0 (RXCLK transitions with data) TXDLY = 0 (No TXCLK Delay)

DO NOT SYNC, EXTERNAL 1.05V REGULATOR OPTION

8 7 5 4 2 1

MCP_CLK25M_BUF0_R

9

73

IN

RTL8211 25MHz Clock

R3746

22

1 2

1/16W

PLACEMENT_NOTE=Place close to U1400

MF-LF

RTL8211_CLK25M_CKXTAL1

5%

402

31 73

OUT

SIZE

A

D

SYNC_MASTER=MASTER SYNC_DATE=MASTER

PAGE TITLE

Ethernet PHY (RTL8211CL)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

37 OF 109

SHEET

31 OF 76

36

- COPY THIS PAGE FROM K36 CSA.39

345678

2 1

D

ENET_MDI_x<1> pinswapped for layout

ENET_CONN_CTAP

PLACE_NEAR=T3900.3:2.54 MM

PLACE_NEAR=T3900.4:2.54 MM

1

C3900

0.1UF

10% 16V

2

X5R 402

PLACE_NEAR=T3901.3:2.54 MM

1

C3901

0.1UF

10% 16V

2

X5R 402

PLACE_NEAR=T3901.4:2.54 MM

1

C3902

0.1UF

10% 16V

2

X5R 402

1

C3903

0.1UF

10% 16V

2

X5R 402

D

ETHERNET CONNECTOR

CRITICAL

T3901

ENET_MDI_P<1>

31 73

BI

ENET_MDI_N<1>

31 73

BI

C

ENET_MDI_P<3>

31 73

BI

ENET_MDI_N<3>

31 73

BI

1

2

3

4

5

6

SM

TX

TLA-6T213HF

RX

12

11

10

ENET_CENTER_TAP<1>

9

ENET_CENTER_TAP<3>

8

7

1/16W

1%

1/16W

R3903

1 2

R3902

1 2

MF-LF

75

402

73

ENET_MDI_TRAN_P<1>

73

ENET_MDI_TRAN_N<1>

ENET_MDI_TRAN_P<3>

73

ENET_MDI_TRAN_N<3>

CRITICAL

T3902

ENET_MDI_N<2>

31 73

BI

ENET_MDI_P<2>

31 73

BI

ENET_MDI_N<0>

31 73

BI

ENET_MDI_P<0>

31 73

BI

Transformers should be mirrored on opposite

1102945 761102945 76

IONCNC

IO

IONCNC

IONCIO

IO

NC

B

D3900

RCLAMP0524P

SLP2510P8

ENET_ESD CRITICAL

3

GND

D3901

RCLAMP0524P

SLP2510P8

ENET_ESD CRITICAL

sides of the board

IONCIO

D3900.1: D3900.5:

D3901.1: D3901.5:

GND

3

1

2

3

4

5

6

PLACE_NEAR=T3901.6:4 MM PLACE_NEAR=T3902.2:4 MM

PLACE_NEAR=T3902.6:4 MM PLACE_NEAR=T3901.2:4 MM

SM

TX

TLA-6T213HF

RX

12

11

10

ENET_CENTER_TAP<2>

9

ENET_CENTER_TAP<0>

8

7

R3901

1 2

1%

1/16W MF-LF

R3900

1 2

1/16W

75

402

75

MF-LF1%402

ENET_BOB_SMITH_CAP

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM

1

2

CRITICAL

C3910

1000PF

10% 2KV CERM 1206

73

ENET_MDI_TRAN_N<2>

ENET_MDI_TRAN_P<2>

73

ENET_MDI_TRAN_N<0>

73

ENET_MDI_TRAN_P<0>

CRITICAL

J3900

RJ45-10/100TX-K83

F-R-TH1

1 2 3 4 5 6 7 8

9 10 11 12

ENET_MDI

TRAN_P0 TRAN_N0 TRAN_P1 TRAN_P2 TRAN_N2 TRAN_N1 TRAN_P3 TRAN_N3

SHIELD

PINS

514-0704

C

B

A

DO NOT SYNC FROM K6, WITH K84’S CONNECTOR

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=MASTER SYNC_DATE=MASTER

PAGE TITLE

ETHERNET CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

39 OF 109

SHEET

32 OF 76

36

345678

CRITICAL

SIL

518S0519

CRITICAL

J4502

78171-0002

M-RT-SM

L4530

R4531

4.7

12

SYS_LED_ANODE

D

36

402

5%

MF-LF

1/16W

SYS_LED_ANODE_R

7

1

C4531

0.001UF

10% 50V

2

CERM 402

FERR-1000-OHM

0402

L4531

FERR-1000-OHM

0402

21

SYS_LED_ANODE_UF

21

SYS_LED_RETURN_UF

3

1 2

4

ODD_PWR_EN_L

19

IN

ODD Power Control

=PP5V_S3_ODD

8

R4596

100K

5%

1/16W

Q4596

SOT563

2

MF-LF

402

D

SG

=PP3V3_S0_ODD

8

33

Q4596

SSM6N15FEAPE

R4597

SOT563

5

100K

1/16W MF-LF

402

1

5%

2

D

SG

SSM6N15FEAPE

ODD_PWR_EN

3

4

1

2

ODD_PWR_EN_LS5V_L

6

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

ensure the drive is unpowered in S3/S5.

1

R4595

100K

1 2

5% 1/16W MF-LF

402

1

C4595

0.068UF

10% 10V

2

CERM 402

ODD_PWR_SS

CRITICAL

SATA ODD

=PP3V3_S0_ODD

8

33

CRITICAL

1

R4590

C

SMC_ODD_DETECT

7

35

OUT

Indicates disc presence

33K

1/16W MF-LF

402

5%

2

J4500

54722-0164

F-ST-SM 1 3 5 7 9

11 13 15

516S0616

2 4 6 8 10 12 14 16

SATA_ODD_R2D_P

7

71

SATA_ODD_R2D_N

7

71

SATA_ODD_D2R_C_N

7

71

SATA_ODD_D2R_C_P

7

71

FL4520

90-OHM-100MA

DLP11S

SYM_VER-1

43

75

12

75

PLACE_NEAR=J4500.6:4MM

CRITICAL

FL4525

90-OHM-100MA

DLP11S

SYM_VER-1

4 3

1 2

PLACE_NEAR=J4500.10:4MM

75

SATA_ODD_R2D_UF_P

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_N

SATA_ODD_D2R_UF_P

PLACE_NEAR=C4520:3MM

1 2

0.01UF

1 2

0.01UF

PLACE_NEAR=U1400.AJ2:3MM

PLACE_NEAR=FL4525.3:3MM

1 2

0.01UF

1 2

0.01UF

PLACE_NEAR=C4526:3MM

Q4590

TPCP8102

23V1K-SM

31 2

S

C4521

10% 402

CERM

16V

C4520

10%

CERM

16V

C4526

16V

CERM

C4525

CERM

16V 402

402

D

G

4

C4596

0.01UF

1 2

10% 16V

CERM

402

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

402

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

7 85 6

PP5V_SW_ODD

7

46

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

SATA_ODD_D2R_N

SATA_ODD_D2R_P

PP5V_SW_ODD_R

SENS_R:ENG

R4598

0.002

1/4W 1206

18 71

IN

18 71

IN

18 71

OUT

18 71

OUT

1 3

1% MF

2

2 1

CRITICAL

4

ISNS_ODD_P

ISNS_ODD_N

D

46 75

OUT

46 75

OUT

C

SENS_R:ENG

CRITICAL

L4500

PP5V_S0_HDD_FLT

7

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2MM

B

VOLTAGE=5V

PLACE_NEAR=J4501.9:3mm

SATA HDD

SATA_HDD_D2R_C_P

7

FERR-70-OHM-4A

CRITICAL

J4501

54722-0164

F-ST-SM 1 3 5 7 9

NC

11 13 15

516S0616

2 4 6 8 10 12 14 16

71

SATA_HDD_D2R_C_N

7

71

SATA_HDD_R2D_N

7

71

SATA_HDD_R2D_P

7

71

0603

21

PP5V_S0_HDD_R

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

CRITICAL

FL4502

90-OHM-100MA

DLP11S

SYM_VER-1

PLACE_NEAR=J4501.6:3MM

CRITICAL

FL4501

90-OHM-100MA

DLP11S

SYM_VER-1

PLACE_NEAR=J4501.12:3MM

43

SATA_HDD_D2R_UF_P

75

12

SATA_HDD_D2R_UF_N

75

43

SATA_HDD_R2D_UF_N

75

12

SATA_HDD_R2D_UF_P

75

2

C4502

0.1UF

20% 10V

1

CERM 402

PLACE_NEAR=L4500.2:2mm

R4599

0.002

1%

1/4W

MF

1206

21 43

ISNS_HDD_P ISNS_HDD_N

C4516

0.01UF

C4515

0.01UF

PLACE_NEAR=J4501.6:3MM PLACE_NEAR=C4516.1:3MM

C4511

0.01UF

C4510

0.01UF

PLACE_NEAR=C4510.1:3MM PLACE_NEAR=J4501.14:3MM

=PP5V_S0_HDD

1 2

10% 16V

1 2

16V

10%

1 2

16V10%

1 2

10% 16V

OUT

CERM

8

46 75

402

PART NUMBER

101S0245

SATA_HDD_D2R_FILT_P

75

SATA_HDD_D2R_FILT_N

75

QTY

2

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

A

8 7 5 4 2 1

DESCRIPTION

RES,0OHM,5%,1/4W,MF-LF,1206

Passive de-emphasis filter Use 0-ohm resistors and NOSTUFF caps if not using

C4586

1 2

IN

1 2

18 71

CERM

MF-LF

CERM

5%

47PF

R4586

27.4

R4585

27.4

C4585

47PF

50V 402

1%

1/16W

1%

1/16W

50V 402

REFERENCE DES

R4599,R4598

PLACEMENT_NOTE: Place R4585,R4586,C4585,C4586 on the same side.

CRITICAL

Resistors should be on inside, with SATA passing straight through.

SATA_HDD_D2R_P

402

SATA_HDD_D2R_N

36

BOM OPTION

SENS_R:PROD

18 71

OUT

18 71

OUT

SYNC_MASTER=MASTER SYNC_DATE=MASTER

PAGE TITLE

SATA Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

45 OF 109

SHEET

33 OF 76

SIZE

B

A

D

345678

POR IS METAL USB CONNECTOR PARTS

2 1

D

Port Power Switch

CRITICAL

U4690

TPS2064DGN

=PP5V_S3_EXTUSB

8

USB_EXTA_OC_L

18

OUT

USB_EXTB_OC_L

18

OUT

1

C4690

10UF

20%

6.3V X5R 603

C

We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough.

Can NOSTUFF one of C4616 or C4696, BUT NOT BOTH

=USB_PWR_EN

62

IN

CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION

C4691

2

0.1UF

20% 10V CERM 402

NOSTUFF

CRITICAL

1

C4616

100UF

20%

6.3V

22

POLY-TANT CASE-B2-SM

CRITICAL

1

C4696

100UF

20%

6.3V

2

POLY-TANT CASE-B2-SM

2

IN

OUT1

MSOP

8

OC1*

3

OUT2

EN1

5

OC2*

4

EN2

TPAD

GND

91

C4695

PLACE_NEAR:J4600.1:3 MM

U4690.7: U4690.6:

PLACE_NEAR:J4610.1:3 MM

7

6

1

10UF

20%

6.3V 2

X5R 603

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

1

C4617

10UF

20%

6.3V

2

X5R 603

USB_EXTA_MUXED_N

72 75

USB_EXTA_MUXED_P

72 75

C4605

0.01uF

CERM

1

20% 16V

2

402

USB/SMC Debug Mux

=PP3V42_G3H_SMCUSBMUX

8

SMC_DEBUG:YES

B

SMC_RX_L

35 36 37

IN

SMC_TX_L

35 36 37

OUT

USB_EXTA_P

18 72

BI

USB_EXTA_N

18 72

BI

C4650

0.1UF

CERM

1

20% 10V

2

402

SMC_DEBUG:NO

R4651

1 2

1/16W MF-LF

5 4

7 6

8

0

5%

402

93

VCC

SMC_DEBUG:YES

M+ M-

U4650

PI3USB102ZLE

TQFN

D+ D-

CRITICAL

GND

SMC_DEBUG:NO

R4652

1 2

1/16W MF-LF

1

Y+

2

Y-

10

SELOE*

0

5%

402

1

R4650

10K

5% 1/16W MF-LF 402

2

USB_DEBUGPRT_EN_L

SEL=0 Choose SMC SEL=1 Choose USB

USB_EXTB_N

18 72

BI

USB_EXTB_P

18 72

BI

35

IN

USB PORT A (FRONT PORT)

PLACE_NEAR=J4600.1:3 mm

CRITICAL

L4605

FERR-220-OHM-2.5A

CRITICAL

L4600

4 3

1 2

PLACE_NEAR=D4600.3:2 mm PLACE_NEAR=D4600.2:2 MM

PLACE_NEAR=J4610.1:3 MM

1

C4615

0.01uF

20% 16V

2

CERM 402

21

PP5V_S3_RTUSB_A_F

0603

90-OHM DLP0NS

SYM_VER-1

FERR-220-OHM-2.5A

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

75

CRITICAL

L4615

0603

CRITICAL

L4610

90-OHM DLP0NS

4 3

1 2

PLACE_NEAR=D4610.2:2 MM PLACE_NEAR=D4610.3:2 mm

CONN_USB_EXTA_N

CONN_USB_EXTA_P

2534

IOIONC

NC

6

VBUS

1

GND

D4600

RCLAMP0502N

SLP1210N6

CRITICAL

We can add protection to 5V if we want, but leaving NC for now

21

PP5V_S3_RTUSB_B_F

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

SYM_VER-1

NOSTUFF

CONN_USB_EXTB_N

75

CONN_USB_EXTB_P

75

D4610

RCLAMP0502N

SLP1210N6

NOSTUFF

USB PORT B (BACK PORT)

CRITICAL

J4600

USB

F-RT-TH-K84

5 6

1 2 3 4

7 8

514-0705

D4600.5

PLACE_NEAR=J4600.2:2 MM

D4600.4

PLACE_NEAR=J4600.3:2 MM

Place L4600 and L4605 at connector pin

CRITICAL

J4610

USB

F-RT-TH-K84

5 6

1 2 3 4

2534

IOIONC

NC

VBUS

GND

CRITICAL

6 1

7 8

514-0705

D4610.5

PLACE_NEAR=J4610.2:2 MM

D4610.4

PLACE_NEAR=J4610.3:2 MM

D

C

B

A

DO NOT SYNC WITH K84. UPDATED PLACE NEAR NOTES UPDATED SMC_DEBUG BOMOPTION, STUFFED C4690

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=(K84_MLB)

PAGE TITLE

External USB Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(10/03/2009)

DRAWING NUMBER

051-8561

REVISION

BRANCH

PAGE

46 OF 109

SHEET

34 OF 76

C.0.0

36

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

D

SMC_P10

(EXCARD_PWR_EN)

C

36

SMC_RSTGATE_L

36

OUT

ALL_SYS_PWRGD

25 62

IN

RSMRST_PWRGD

62

IN

PM_RSMRST_L

19

OUT

IMVP_VR_ON

58

OUT

PM_PWRBTN_L

19

OUT

36

23

40

LPC_AD<0>

19 37 72

BI

LPC_AD<1>

19 37 72

BI

LPC_AD<2>

19 37 72

BI

LPC_AD<3>

19 37 72

BI

LPC_FRAME_L

19 37 72

IN

SMC_LRESET_L

25

IN

LPC_CLK33M_SMC

25 72

IN

LPC_SERIRQ

7

19 37

BI

36

SMB_MGMT_DATA

38

BI

SMS_ONOFF_L

45

OUT

SMC_GFX_THROTTLE_L

36

OUT

SMC_SYS_KBDLED

9

OUT

SMC_TX_L

34 35 36 37

OUT

SMC_RX_L

34 35 36 37

IN

SMB_0_S0_CLK

38

BI

SMC_P20

SMC_P24

SMC_BMON_MUX_SEL

SMC_P41

(OC)

345678

PP3V3_S5_AVREF_SMC

7

36

=PP3V3_S5_SMC

8

36

1

C4902

22UF

20%

6.3V CERM

B12

P10

A13

P11

A12

P12

B13

P13

D11

NC

NC NC NC

NC

NC NC

P14

C13

P15

C12 J11

P16 P66

D10

P17

D13

P20

E11

P21

D12

P22

F11

P23

E13

P24

E12

P25

F13

P26

E10

P27

A9

P30

D9

P31

C8

P32

B7

P33

A8

P34

D8

P35

D7

P36

D6

P37

D4

P40

A5

P41

B4

P42

A1

P43

C2

P44

B2

P45

C1

P46

C3

P47

G2

P50

F3

P51

E4

P52

U4900

H8S2117

LGA-HF

(1 OF 3)

OMIT

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81 P82 P83 P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

L13 K12 K11 J12 K13 J10

H12

N10 M11 L10 N11 N12 M13 N13 L12

A7 B6 C7 D5 A6 B5 C6

J4 G3 H2 G1 H4 G4 F4 F1

SMC_PM_G2_EN

NC NC NC

SMC_ADAPTER_EN

NC

SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L

SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE

SMC_WAKE_SCI_L

NC

PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L SMB_MGMT_CLK

(OC)

SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK SMB_0_S0_DATA

(OC)

OUT

IN IN

IN IN IN IN IN IN IN IN

OUT

IN

OUT

IN

BI

IN IN IN IN IN IN IN

BI

7

62

19 36 62

36

40

39

36

40

39

40

23

19

19 37

34 35 36 37

38

36 43

9

36 54

36

7

19 62 66

7

19 36 62

19

25 72

38

NOTE: P94 and P95 are shorted in some platforms.

805

1

C4903

0.1UF

20%

2

10V

2

CERM 402

R4999

4.7

1 2

5% 1/16W MF-LF

402

1

C4904

0.1UF

20% 10V

2

CERM 402

PLACE_NEAR=C4920.1:2 mm

PP3V3_S5_SMC_AVCC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.10 MM VOLTAGE=3.3V

BYPASS=U4900.M12:L9:5 mm

36 37 55

IN

36

1

2

C4920

0.1UF

SMC_RESET_L SMC_XTAL

SMC_EXTAL

C4905

0.1UF

20% 10V CERM 402

20% 10V

CERM

402

1

C4906

0.1UF

20% 10V

2

CERM 402

1

2

M12

AVCC

D3

RES*

A3

XTAL

A2

EXTAL

VSS

L3

D2

H10

M1

B1

U4900

H8S2117

LGA-HF

(3 OF 3)

OMIT

C5

F10

B11

E1

L11

VCLVCC

AVREF

ETRST

XW4900

SM

2 1

BYPASS=U4900.E1:D2:5 mm

SMC_VCL

0.47UF

10%

6.3V

CERM-X5R

402

NC

SMC_KBC_MDE

1

R4902

10K

5% 1/16W MF-LF 402

2

GND_SMC_AVSS

1

2

R4909

10K

5% 1/16W MF-LF

402

1

R4998

10K

5% 1/16W MF-LF 402

2

23 36 39 40

AVSS

MD1 MD2

NMI

NC

12

C4907

E5

D1 H1

E3

H3

L9

121

R4901

10K

5% 1/16W MF-LF 402

2

SMC_MD1

SMC_NMI

SMC_TRST_L

NO STUFF

1

R4903

0

5% 1/16W MF-LF 402

2

D

37

IN

37

IN

37

IN

C

(DEBUG_SW_1) (DEBUG_SW_2)

B

(EXCARD_CP)

(EXCARD_OC_L)

A

36

PM_SYSRST_L

25

OUT

USB_DEBUGPRT_EN_L

34

OUT

MEM_EVENT_L

19 26 27

BI

36

SYS_ONEWIRE

54

BI

PM_BATLOW_L

19

OUT

SMC_RUNTIME_SCI_L

19

OUT

SMC_ODD_DETECT

7

33

IN

36

SMC_GFX_OVERTEMP_L

36

IN

SMC_FAN_0_CTL

42

OUT

SMC_FAN_1_CTL

36

OUT

SMC_FAN_2_CTL

36

OUT

SMC_FAN_3_CTL

36

OUT

SMC_FAN_0_TACH

42

IN

SMC_FAN_1_TACH

36

IN

SMC_FAN_2_TACH

36

IN

SMC_FAN_3_TACH

36

IN

SMS_X_AXIS

45

IN

SMS_Y_AXIS

45

IN

SMS_Z_AXIS

45

IN

SMC_ANALOG_ID

36

IN

SMC_NB_CORE_ISENSE

36

IN

SMC_NB_DDR_ISENSE

36

IN

SMC_ADC14

36

IN

SMC_ADC15

36

IN

SMC_PA0 SMC_PA1

SMC_PA5

SMC_PB3 SMC_PB4

SMC_PB6

(OC) (OC) (OC) (OC) (OC) (OC)

(See below)

NC

A10 C10 B10 C11 A11

G11 G13 F12 H13 G10 G12 H11 J13

M10

K10

N3

PA0

N1

PA1

M3

PA2

M2

PA3

N2

PA4

L1

PA5

K3

PA6

L2

PA7

B8

PB0

C9

PB1

B9

PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0

N9

PD1 PD2

L8

PD3

M9

PD4

N8

PD5

K9

PD6

L7

PD7

SMC_PB3: SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay.

8 7 5 4 2 1

U4900

H8S2117

LGA-HF

(2 OF 3)

OMIT

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

K1 J3 K2 J1 K4 K5

N5 M6 L5 M5 N4 L4 M4

M8 N7 K8 K7 K6 N6 M7 L6

E2 F2 J2 A4 B3 C4

SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_G3H_POWERON_L

SMC_SYS_LED SMC_LID

NC NC

SMC_MCP_SAFE_MODE

NC NC

NC

=SMC_SMS_INT SMB_BSA_DATA

(OC)

SMB_BSA_CLK

(OC)

SMB_A_S3_DATA

(OC)

SMB_A_S3_CLK

(OC)

SMB_B_S0_DATA

(OC)

SMB_B_S0_CLK

(OC)

SMC_PROCHOT SMC_THRMTRIP

NC

SMC_PH3

NC NC

36

IN

36 37

IN

36 37

IN

36 37

OUT

7

36 37

IN

36

IN

36

OUT

36 43 54

IN

36

OUT

36

IN

38

BI

38

BI

38

BI

38

BI

38

BI

38

BI

36

OUT

36

OUT

36

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

H8S2117-R: (SMC_PECI) (SMC_PECI_VREF) (SMC_PECI_VSTP)

SYNC_MASTER=T27_MLB

PAGE TITLE

SYNC_DATE=02/16/2010

SMC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

36

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

49 OF 109

SHEET

35 OF 76

SIZE

B

A

D

345678

2 1

SMC Reset "Button", Supervisor & AVREF Supply

=PP3V3_S5_SMC

8

35 36

=PPVIN_S5_SMCVREF

8

Desktops: 5V Mobiles: 3.42V

1

C5020

0.47UF

10%

6.3V 2

CERM-X5R

C5001

0.01UF

10% 16V

CERM

402

1

2

SMC_TPAD_RST_L

43

D

IN

SMC_ONOFF_L

35 36 43

IN

SMC_MANUAL_RST_L

OMIT

1

R5001

0

5% 1/10W MF-LF 603

2

SILK_PART=SMC_RST

1 V+

U5010

VREF-3.3V-VDET-3.0V

6

MR1*

(IPU)

MR2*

DELAY

GND

(IPU)

2

SN0903048

7

4

3

VIN

DFN

RESET*

REFOUT

THRM

PAD

9

PLACEMENT_NOTE=Place R5001 on BOTTOM side MR1* and MR2* must both be low to cause manual reset.

Used on mobiles to support SMC reset via keyboard. NOTE: Internal pull-ups are to VIN, not V+.

Debug Power "Buttons"

SMC_ONOFF_L

603

OMIT

1

R5015

0

5%

1/10W MF-LF 603

2

SILK_PART=PWR_BTN PLACEMENT_NOTEs:

Place R5014 on TOP side Place R5015 on BOTTOM side

OMIT

R5014

1/10W MF-LF

SILK_PART=PWR_BTN

C

SMC Crystal Circuit

SMC_XTAL

35

SMC_EXTAL

35

1 2

1/16W MF-LF

5%

402

SMC_XTAL_R

CRITICAL

Y5010

20.00MHZ

5X3.2-SM

R5010

0

B

System (Sleep) LED Circuit

5

8

C5025

10uF

20%

6.3V X5R 603

OUT

1

2

1

R5000

1K

5% 1/16W MF-LF 402

2

SMC_RESET_L PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=3.3V

1

C5026

0.01UF

10% 16V

2

CERM 402

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

35 36 43

C5010

15pF

1 2

5%

50V

CERM

402

C5011

15pF

1 2

5%

50V

CERM

402

7

23 35 39 40

35 37 55

OUT

35

TO CPU

CPU_PROCHOT_L

10 14 69

BI

PM_THRMTRIP_L

10 14 69

OUT

SMC Aliases

SMC_MCP_VSENSE

39

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

40

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

40

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

40

MAKE_BASE=TRUE

TP_SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

TP_SMC_GPU_ISENSE

MAKE_BASE=TRUE

TP_SMC_GPU_VSENSE

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_L

35 19

IN

SMS_INT_L

MAKE_BASE=TRUE

MCP_WAKE_REQ_L

19

IN

SMC_MCP_SAFE_MODE

35 19

IN

SMC_ADC14 SMC_ADC15 SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE

SMC_ANALOG_ID SMC_GPU_ISENSE SMC_GPU_VSENSE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

=SMC_SMS_INT

SMC_G3H_POWERON_L

MAKE_BASE=TRUE

R5096

0

1 2

5% 1/16W MF-LF

402

MCP_SPKR

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35

OUT

35 36

OUT

SMC FSB to 3.3V Level Shifting

=PP3V3_S0_SMC

8

36

1

R5061

100K

5% 1/16W MF-LF 402

2

CPU_PROCHOT_BUF

3

Q5060

5

DMB53D0UV

SOT-563

4

6

1

3

4

R5062

1 2

D

S G

D

S G

3.3K CPU_PROCHOT_L_R

5% 1/16W MF-LF

402

Q5059

SSM6N15FEAPE

SOT563

2

SMC_PROCHOT

Q5059

SSM6N15FEAPE

SOT563

5

SMC_THRMTRIP

SMC Pull-ups

SMC_PA0

35

SMC_PA1

35

SMC_PB4

35

SMC_PB6

35

SMC_ONOFF_L

35 36 43

SMC_LID

35 43 54

SMC_TX_L

34 35 37

SMC_RX_L

34 35 37

SMC_TMS

7

35 37

SMC_TDO

35 37

SMC_TDI

35 37

SMC_TCK

35 37

SMC_BIL_BUTTON_L

35

SMC_BC_ACOK

9

35 54

SMS_INT_L

36

SMC_GFX_OVERTEMP_L

35

SMC_G3H_POWERON_L

35 36

SMC_PA5

35

R5091 R5092 R5088 R5095

R5070 R5071 R5073 R5074

R5077 R5078 R5079 R5080 R5081 R5087 R5093 R5094 R5098

R5089

G

2

100K 100K

10K 10K

10K

100K

10K

100K

10K 10K 10K 10K 10K

470K

10K 10K

100K

10K

1

R5060

10K

5% 1/16W MF-LF 402

2

SMC_PROCHOT_3_3_L

6 D

Q5060

DMB53D0UV

SOT-563

S 1

=PP3V3_S5_SMC

8

35 36

1 2 1 2 1 2 1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

5% 402 5% 402

5%

12

5%

=PP3V3_S0_SMC

8

36

5% 402

TO SMC

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF1/16W MF-LF

1/16W 1/16W MF-LF

1/16W

MF-LF

4025% 4025% 4025% 4025%

4025% 4025%

4025% 4025% 4025% 4025% 4025% 4025% 402 4025% 402

35

OUT

D

35

IN

35

IN

C

B

=PP5V_S3_SYSLED

8

121

R5031

1.74K

1/16W MF-LF

1%

402

R5030

66.5

1% 1/16W MF-LF 402

2

SYS_LED_ILIM

SYS_LED_L_VDIV

1

R5032

5.49K

1% 1/16W MF-LF

402

A

2

SYS_LED_L

SMC_SYS_LED

35

IN

R5030,R5031,R5032 CHANGED FOR DIMMER LED

8 7 5 4 2 1

Target Current: 7.5 mA

5 46

E

BD

Q1

1 2 3

Q2

C

GS

Q5030

DMB54D0UV

SOT-563

SYS_LED_ANODE

SMC Pull-downs

SMC_BS_ALRT_L

SMC_FAN_1_CTL

35

IN

TP_SMC_FAN_1_TACH

MAKE_BASE=TRUE

SMC_FAN_2_CTL

35

IN

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

SMC_FAN_3_CTL

35

IN

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_RSTGATE_L

35

IN

SMC_P10

35

IN

SMC_P20

35

IN

SMC_P41

35

IN

SMC_PB3

35

IN

SMC_PH3

35

33

OUT

IN

NO_TEST=TRUE

TP_SMC_FAN_1_CTL

MAKE_BASE=TRUE

SMC_FAN_1_TACH

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMC_FAN_2_TACH

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

SMC_FAN_3_TACH

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

TP_SMC_P10

MAKE_BASE=TRUE

TP_SMC_P20

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

TP_SMC_PB3

MAKE_BASE=TRUE

TP_SMC_PH3

MAKE_BASE=TRUE

NO_TEST=TRUE

35

OUT

35

OUT

35

OUT

Unused Pins

35

SMC_ADAPTER_EN

19 35 62

SMC_CASE_OPEN

35

PM_SLP_S4_L

7

19 35 62

SYNC_MASTER=(T27_MLB)

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

R5076 R5085 R5086 R5090

100K

1 2

10K

1 2

10K

1 2

100K

1 2

SMC Support

Apple Inc.

R

MF-LF MF-LF1/16W MF-LF MF-LF

402 4025% 4025% 402

1/16W

5%

1/16W 1/16W

5%

SYNC_DATE=(10/27/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

50 OF 109

SHEET

36 OF 76

SIZE

A

D

36

345678

2 1

LPC+SPI Connector

CRITICAL

LPCPLUS_CON

J5100

D

=PP3V3_S5_LPCPLUS

8

=PP5V_S0_LPCPLUS

8

LPC_AD<0>

19 35 72

BI

LPC_AD<1>

19 35 72

BI

SPI_ALT_MOSI

37 72

SPI_ALT_MISO

37 72

LPC_FRAME_L

19 35 72

IN

PM_CLKRUN_L

19 35

OUT

SMC_TMS

7

35 36

OUT

LPCPLUS_RESET_L

25

IN

SMC_TDO

35 36

OUT

SMC_TRST_L

35

IN

SMC_MD1

35

OUT

SMC_TX_L

34 35 36

IN

55909-0374

M-ST-SM

31

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29

33

32

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

34

LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>

SPIROM_USE_MLB SPI_ALT_CLK

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO

OUT

37 72

OUT OUT OUT OUT OUT OUT

25 72

IN

19 35 72

BI

19 35 72

BI

7

19 47

7

19 35

BI

19 35

IN

35 36

35 36 55

35

34 35 36

7

19

516S0573

D

C

SPI Bus Series Termination

SPI_ALT_MISO SPI_ALT_MOSI SPI_ALT_CLK

47

5%

402

SPI_ALT_CS_L

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_MLB_MISO

1/16W MF-LF

LPCPLUS

1

R5127

0

5%

402

2

R5123

1 2

LPCPLUS

R5128

R5110

15

402

1 2

5% 1/16W MF-LF

15

5%

402

SPI_CS0_R_L

19 72

IN

R5111

15

402

1 2

1/16W MF-LF

5%

SPI_CLK_R

19 72

IN

R5112

SPI_MOSI_R

19 72

IN

SPI_MISO

7

19 72

OUT

1 2

1/16W MF-LF

SPI_CS0_L

7

72

SPI_CLK

7

72

SPI_MOSI

7

72

B

1/16W MF-LF

15

5% 1/16W MF-LF

402

47

402

5%

LPCPLUS

1

2

R5126

1/16W MF-LF

R5122

47

1 2

5% 1/16W MF-LF

402

LPCPLUS

R5125

1/16W MF-LF

R5121

47

1 2

5% 1/16W MF-LF

402

1

47

5%

402

2

R5120

1 2

1/16W MF-LF

1

47

5%

402

2

37 72

OUT

47 72

IN

B

EFI Debug ROM

=PP3V3_S0_DEBUGROM

8

EFI_DEBUG

R5101

1/16W MF-LF

A

NO STUFF

R5102

1/16W MF-LF

8 7 5 4 2 1

EFI_DEBUG

1

R5103

0

5%

5% 1/16W

402

MF-LF 402

2

DEBUGROM_E2 DEBUGROM_E1

NO STUFF

121

R5104

0

5%

1/16W MF-LF 402

2

Write: 0xAC/0xAE Read: 0xAD/0xAF

EFI_DEBUG

C5101

0.1UF

CERM

1

20% 10V

2

402

3

E2

2

E1

7

WC*

EFI_DEBUG

8

VCC

U5101

M24M01-R

SO8N

CRITICAL

VSS

4

E0/NC0

5

=I2C_DEBUGROM_SDA

SDA

6

=I2C_DEBUGROM_SCL

SCL

1

NC

38

BI

38

IN

SYNC_MASTER=(T27_MLB)

PAGE TITLE

LPC+SPI Debug Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(12/15/2009)

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

051-8561

C.0.0

51 OF 109

37 OF 76

SIZE

A

D

36

345678

2 1

MCP89 SMBus "0" Connections

=PP3V3_S0_SMBUS_MCP_0

8

121

402

R5201

1K

5%

1/16W MF-LF 402

2

SO-DIMM "A"

(Write: 0xA0 Read: 0xA1)

J2900U1400

=I2C_SODIMMA_SCL =I2C_SODIMMA_SDA

SO-DIMM "B"

(Write: 0xA2 Read: 0xA3)

J3100

=I2C_SODIMMB_SCL

NBC

=I2C_SODIMMB_SDA

Mikey

CD3275: U6880

(Write: 0x72 Read: 0x73)

=I2C_MIKEY_SCL =I2C_MIKEY_SDA

26

27

53

MCP89

(MASTER)

SMBUS_MCP_0_CLK

72 19 13

D

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

72 19 13

MAKE_BASE=TRUE

R5200

1/16W MF-LF

Debug Devices

(Not stuffed in production)

Vref DACs

DAC5574: U3300

(Write: 0x98 Read: 0x99)

=I2C_VREFDACS_SCL

29

=I2C_VREFDACS_SDA

29

Margin Control

PCA9557: U3310

C

(Write: 0x30 Read: 0x31)

=I2C_PCA9557D_SCL

29

=I2C_PCA9557D_SDA

29

SMC "0" SMBus Connections

=PP3V3_S0_SMBUS_SMC_0_S0

8

10K

402

121

R5251

10K

5%

5% 1/16W MF-LF 402

2

121

R5271

1K

5%

5% 1/16W MF-LF 402

2

Debug Temp

TMP442A: U5535

(WRITE: 0X98 READ: 0X99)

=I2C_MCPTHMSNS_SCL =I2C_MCPTHMSNS_SDA

Trackpad

(Write: 0x90 Read: 0x91)

J5800

=I2C_TPAD_SCL =I2C_TPAD_SDA

41

44

SMC

U4900

(MASTER)

SMB_0_S0_CLK

35

SMB_0_S0_DATA

35 35

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

8

SMC

U4900

(MASTER)

SMB_A_S3_CLK

35

SMB_A_S3_DATA

35

74

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

74

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3

SMBUS_SMC_A_S3_SCL

74

7

MAKE_BASE=TRUE

74

SMBUS_SMC_A_S3_SDA

7

MAKE_BASE=TRUE

R5250

1/16W MF-LF

R5270

1/16W MF-LF

SMC "Battery A" SMBus Connections

=PP3V42_G3H_SMBUS_SMC_BSA

8

121

402

R5281

2.61K

1%

1/16W MF-LF 402

2

Battery Charger

ISL6259 - U7000

(Write: 0x12 Read: 0x13)

=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA

BATTERY

J6950

(See Table)

=SMBUS_BATT_SCL =SMBUS_BATT_SDA

The bus formerly known as "Battery B"

121

402

R5291

4.7K

5%

1/16W MF-LF 402

2

Debug ADC

LT2309: U6000

(Write: 0x10 Read: 0x11)

=I2C_SMC_ADCS_SCL =I2C_SMC_ADCS_SDA

SMC

U4900

(MASTER)

SMB_BSA_CLK

35

SMB_BSA_DATA

74

SMBUS_SMC_BSA_SCL

7

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

74

7

MAKE_BASE=TRUE

R5280

2.61K

1/16W MF-LF

Battery

Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)

SMC "Management" SMBus Connections

=PP3V3_S3_SMBUS_SMC_MGMT

8

SMC

U4900

(MASTER)

SMB_MGMT_CLK

35 46

SMB_MGMT_DATA

35

SMBUS_SMC_MGMT_SCL

74

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

74

MAKE_BASE=TRUE

R5290

4.7K

1/16W MF-LF

55

54

46

D

C

EFI Debug Serial

M24M01: U5101 (Write: 0xAC/0xAE Read: 0xAD/0xAF)

=I2C_DEBUGROM_SCL

37

=I2C_DEBUGROM_SDA

37

MCP89 SMBus "1" Connections

=PP3V3_S0_SMBUS_MCP_1

8

NO STUFF

MCP89

B

(Write: 0xE0 Read: 0xE1)

U1400

SMBUS_MCP_1_CLK

72 19

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

72 19

MAKE_BASE=TRUE

R5230

2.0K

1/16W MF-LF

R5235

MCP89 SMBus 1 is slave port to access internal thermal sensors

Another slave port is available at 0x10/0x11, probably not used.

1/16W MF-LF

402

NO STUFF

121

R5231

2.0K

5%

5% 1/16W MF-LF 402

2

121

R5236

0

5%

5% 1/16W MF-LF 402

2

SMC "B" SMBus Connections

=PP3V3_S0_SMBUS_SMC_B_S0

8

402

121

R5261

4.7K

5%

5% 1/16W MF-LF 402

2

Prod Temp

EMC1413: U5515

(Write: 0x98 Read: 0x99)

=I2C_CPUTHMSNS_SCL =I2C_CPUTHMSNS_SDA

SMC

U4900

(MASTER)

SMB_B_S0_CLK

35

SMB_B_S0_DATA

35

74

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

74

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

R5260

4.7K

1/16W MF-LF

41

B

A

SYNC_MASTER=MASTER

PAGE TITLE

K87 SMBus Connections

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

52 OF 109

SHEET

38 OF 76

SIZE

A

D

345678

2 1

CPU Voltage Sense / Filter

PPVCORE_S0_CPU

8 7

XW5309

SM

1 2

PLACE_NEAR=U1000.AA13:19.05 mm

CPUVSENSE_IN

D

R5309

4.53K

1 2

1% 1/16W MF-LF

402

Place RC close to SMC

SMC_CPU_VSENSE

1

C5309

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

35

OUT

40 39 36 35 23

D

MCP Voltage Sense / Filter

PPVCORE_S0_MCP

8 7

XW5359

SM

1 2

PLACE_NEAR=U1400.AB22:5 mm

MCPVSENSE_IN

R5359

4.53K

1 2

1% 1/16W MF-LF

402

Place RC close to SMC

SMC_MCP_VSENSE

1

C5359

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

36

OUT

40 39 36 35 23

C

PBUS Voltage Sense Enable & Filter

Q5315

NTUD3169CZ

SOT-963

N-CHANNEL

G

=PBUSVSENS_EN

62

IN

Enables PBUS VSense divider when high.

PPBUS_G3H

8 7

B

R5315

100K

1/16W MF-LF

1

1%

402

2

1

G

5

4

P-CHANNEL

PBUSVSENS_EN_L_DIV

6

D

S

D

S

PBUSVSENS_EN_L

3

PBUS_G3H_VSENSE

R5316

100K

1/16W MF-LF

1

1%

402

2

1

R5385

27.4K

1% 1/16W MF-LF

RTHEVENIN = 4573 Ohms

402

2

R5386

5.49K

1/16W MF-LF

SMC_PBUS_VSENSE

1

C5385

0.22UF

1%

20%

6.3V

2

X5R 402

GND_SMC_AVSS

402

35

OUT

40 39 36 35 23

B

Place RC close to SMC

A

SYNC_MASTER=T27_MLB

PAGE TITLE

Voltage Sensing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

53 OF 109

SHEET

39 OF 76

SIZE

A

D

345678

2 1

MCP MEM VDD Current Sense / Filter

=PP3V3_S0_MCPDDRISNS

8

=PP3V3_S0_MCPCOREISNS

1

C5400

0.1uF

20%

R5410

1/16W MF-LF

R5412

118

1/16W MF-LF

402

CERM

5%

1%

10V

2

402

1

0

2

3

1

2

U5400

OPA330

5

1

3

+IN

-IN

SC70-5

V+

V-

2

MCPDDR_SENSE_E

Q5401

2SA2154MFV-YAE

SOD 1

MCPDDR_SENSE_B

MCPDDR_SENSE_C

PLACEMENT_NOTEs: Place close to SMC

Place close to SMC (For R and C)

4

MCPDDR_SENSE_AMP

NO STUFF

1

C5434

0.1UF

10% 16V

2

X5R 402

R5417

4.53K

1 2

1% 1/16W MF-LF

402

2

R5411

0

5% 1/16W MF-LF

402

1

SMC_MCP_DDR_ISENSE

1

C5435

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

59

36

OUT

40 39 36 35 23

D

MCPDDRFET_KELVIN

21

IN

MCPDDRFET_SENSE

21

IN

C

MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter

=PP3V3_S0_CPUVTTISNS

8

=PPBUS_S5_CPUREGS_ISNS_R

8

=PPBUS_S5_CPUREGS_ISNS

8

CRITICAL

R5492

0.01

0612-1

0.5%

3

IN-

V+

U5402

INA213

SC70

(50V/V)

GND

2

OUT

1 3

1W MF

75

2

4

75

ISNS_CPUVTT_N

ISNS_CPUVTT_P

5

1

C5417

0.1uF

20% 10V

2

CERM 402

6

CPUVTT_IOUT

14

REFIN+

PLACEMENT_NOTEs: Place close to SMC

Place close to SMC (For R and C)

R5418

4.53K

1 2

1% 1/16W MF-LF

402

SMC_CPU_FSB_ISENSE

1

C5436

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

8

(Sense R "output")

MCPCORES0_VO

IN

MCPCORES0_ISP_R

IN

(Sense R "input")

Sense R is R7525, 1mOhm Max Vdiff = 24.8mV

36

OUT

40 39 36 35 23

3 V+

U5420

INA214

5

SC70

IN-

4 1

IN+ REF

(100V/V)

GND

OUT

2

1

C5420

0.1uF

20% 10V

2

CERM 402

6

MCPCORE_IOUT

Gain: 100x

Scale: 10A / V Max VOut: 2.48V

CPU VCore Load Side Current Sense / Filter

B

MCP VCore Current Sense Filter

R5416

4.53K

58

MCPCORES0_IMON

59

IN

IMVP6_IMON

IN

PLACEMENT_NOTEs: Place close to SMC

Place close to SMC

Place close to SMC (For R’s and C)

R5415

0

1 2

5% 1/16W MF-LF

402

NOTE: Do not stuff R5415 and R7593 at the same time!

R5471

6.19K

1 2

1% 1/16W MF-LF

402

1 2

1% 1/16W MF-LF

402

R5480

17.4K

1/16W MF-LF

SMC_MCP_CORE_ISENSE

1

C5472

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

PLACEMENT_NOTEs: Place close to SMC

Place close to SMC (For R and C)

SMC_CPU_ISENSE

1

C5470

0.22UF

1%

20%

6.3V

2

402

X5R 402

2

GND_SMC_AVSS

36

OUT

D

40 39 36 35 23

C

35

OUT

40 39 36 35 23

B

=PP3V42_G3H_BMON_ISNS

8

PLACEMENT_NOTE=Place near sense resistor

Charger/Load side

CKPLUS_WAIVE=PdifPr_badTerm

74 55

IN

CHGR_CSO_R_N

74 55

IN

CKPLUS_WAIVE=NdifPr_badTerm

Battery side

NOTE: Monitoring current from battery to PBUS (battery discharge) across R7008

CHGR_BMON

55

A

IN

From charger

8 7 5 4 2 1

Battery (BMON) Current Sense, MUX & Filter

BMON:ENG

1

3

V+

U5403

INA213

5

SC70

IN-

BMON:ENG

(50V/V)

For engineering, stuff BMON_ENG For production, stuff BMON_PROD

GND

OUT

REFIN+

2

C5418

0.1uF

20% 10V

2

CERM 402

6

BMON_INA_OUTCHGR_CSO_R_P

14

BMON:ENG

C5459

0.1uF

CERM

20% 10V

402

1

2

BMON:ENG

U5413

NC7SB3157P6XG

SC70

1

B1

1

2

GND

0

3

B0

VER 1

6

SEL

5

VCC

4

A

BMON:PROD

R5431

0

2 1

5% 1/16W MF-LF

402

PLACEMENT_NOTE=Place R5431 next to U5413

BMON:ENG

1

2

SMC_BMON_MUX_SEL

BMON_AMUX_OUT

R5423

100K

5% 1/16W MF-LF 402

PLACEMENT_NOTEs: Place close to SMC

(For R and C)

35

IN

R5401

45.3K

1 2

1% 1/16W MF-LF

402

ISL6259 Gain: 36x INA213 Gain: 50x

SMC_BATT_ISENSE

1

C5490

0.022UF

20% 16V

2

CERM 402

GND_SMC_AVSS

NOTE: R5401/C5490 changed due to low source/sink current of ISL6259.

35

OUT

40 39 36 35 23

DC-IN (AMON) Current Sense Filter

R5481

4.53K

CHGR_AMON

55 35

IN

PLACEMENT_NOTEs: Place close to SMC

Place close to SMC (For R and C)

1 2

1% 1/16W MF-LF

402

SMC_DCIN_ISENSE

1

C5487

0.22UF

20%

6.3V

2

X5R 402

GND_SMC_AVSS

SYNC_MASTER=T27_MLB

PAGE TITLE

OUT

40 39 36 35 23

Current Sensing

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/02/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

54 OF 109

SHEET

40 OF 76

SIZE

A

D

36

345678

2 1

CPU PROXIMITY/HDD FLEX AREA/FINSTACK THERMAL SENSOR

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

U5515

EMC1413

DP1

CRITICAL

DN1

DP2/DN3

DN2/DP3

GND

6

1

VDD

DFN

THERM*/ADDR

ALERT*

SMDATA

SMCLK

THRM_PAD

11

1

C5515

0.1uF

20% 10V

2

CERM 402

CPUTHMSNS_THERM_L

8

CPUTHMSNS_ALERT_L

9

=I2C_CPUTHMSNS_SDA

10

=I2C_CPUTHMSNS_SCL

PLACEMENT NOTE: PLACE U5515 NEAR CPU

R5516

1/16W MF-LF

10K

121

R5517

10K

1%

5% 1/16W MF-LF

402

2

38

BI

38

BI

D

CPUTHMSNS_D1_P

75

CPUTHMSNS_D1_N

75

CPUTHMSNS_D2_P

75

CPUTHMSNS_D2_N

75

R5515

47

1 2

5% 1/16W MF-LF

402

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

1

C5521

0.0022uF

10% 50V

2

CERM

402

1

C5520

0.0022uF

10% 50V

2

CERM

402

APN 353S2571

2 7 3

4 5

=PP3V3_S0_CPUTHMSNS

8

D

PLACEMENT_NOTE=PLACE CLOSE TO J4501 IN A CONVENIENT LOCATION

DETECT HDD TEMPERATURE

DETECT FIN-STACK TEMPERATURE

BC846BMXXH

Q5502

SOT732-3

Q5501

SOT732-3

3

1

2

3

1

2

C

MCP DIE/CPU DIE/MCP PROXIMITY THERMAL SENSOR

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

MCP_T_DIODE_SENSOR

R5535

47

=PP3V3_S0_MCPTHMSNS

8

BI

MCP_THMDIODE_P

MCP_THMDIODE_N

CPU_THERMD_P

CPU_THERMD_N

MCP_T_DIODE_SENSOR

C5522

100PF

CERM

MCP_T_DIODE_SENSOR

C5540

100PF

CERM

1

5%

50V

2

402

1

5%

50V

2

402

75 19

B

DETECT MCP DIE TEMPERATURE

75 19

75 10

DETECT CPU DIE TEMPERATURE

75 10

1 2

5% 1/16W MF-LF

402

APN 353S2795

PP3V3_S0_MCPTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

1 2

3 4

8

V+

U5535

TMP442A

DXP1

SOT23-8

DXN1

MCP_T_DIODE_SENSOR

DXP2 DXN2

GND

5

SCL SDA

MCP_T_DIODE_SENSOR

1

C5535

0.1uF

20% 10V

2

CERM 402

7

=I2C_MCPTHMSNS_SCL

6

=I2C_MCPTHMSNS_SDA

PLACEMENT NOTE: PLACE U5535 NEAR MCP

B

38

BI

38

BI

A

SYNC_MASTER=MASTER

PAGE TITLE

Thermal Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

55 OF 109

SHEET

41 OF 76

SIZE

A

D

345678

2 1

D

=PP5V_S0_FAN_RT

8

=PP3V3_S0_FAN_RT

8

C

R5660

47K

5% 1/16W MF-LF

402

35

OUT

35

IN

SMC_FAN_0_TACH

R5661

SMC_FAN_0_CTL

100K

1/16W MF-LF

R5665

47K

1 2

1

5%

402

1

GS

2

1/16W MF-LF

402

5%

FAN_RT_TACH

7

Q5660

SSM3K15FV

SOD-VESM-HF

D

FAN_RT_PWM

7

3

1

2

CRITICAL

J5601

78171-0004

M-RT-SM

5

NC

1 2 3 4

6

NC

518S0521

5V DC TACH MOTOR CONTROL GND

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

Fan Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

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56 OF 109

SHEET

42 OF 76

345678

2 1

PSOC USB CONTROLLER

- USB INTERFACES TO MLB

- SPI HOST TO Z2

- TRACKPAD PICK BUTTONS

- KEYBOARD SCANNER

=PP3V3_S3_TPAD

44 43

8

D

PICKB_L

44

7

BUTTON_DISABLE

43

Z2_HOST_INTN

44

7

WS_LEFT_SHIFT_KEY

43

WS_LEFT_OPTION_KEY

43

WS_CONTROL_KEY

43

Z2_KEY_ACT_L

44

7

TP_P4_5 Z2_DEBUG3

44

7

Z2_RESET

44

7

PSOC_MISO

44

7

PSOC_F_CS_L

44

7

PSOC_MOSI

44

C

7

PSOC_SCLK

44

7

Z2_MISO

44

7

Z2_CS_L

44

7

Z2_MOSI

44

7

Z2_SCLK

44

7

TP_PSOC_SCL TP_PSOC_SDA TP_PSOC_P1_3 TP_ISSP_SCLK_P1_1

ISSP SCLK/I2C SCL

USB_TPAD_P

72 18

USB_TPAD_N

72 18

R5704

1.5

5% 1/16W MF-LF

402

NC

R5701

24

1 2

5%

1/16W MF-LF

402

R5702

24

1 2

5%

1/16W MF-LF

402

12

PP3V3_S3_PSOC

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V

56

1 2 3 4 5 6 7 8

9 10 11 12 13 14

75

P2_5

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P2_7

P1_5

P1_7

USB_TPAD_R_P

USB_TPAD_R_N

NC

525150

535455

VSS

P0_3

P0_5

P0_7

P0_1

CRITICAL

OMIT

U5701

CY8C24794

MLF

(SYM-VER2)

337S2983

D+

D-

P1_1

P1_3

VSS

BYPASS=U5701.49:50:5 mm

1

C5704

100PF

5% 50V

2

CERM 402

44

47

48

49

454643

VDD

P0_6

P7_7

VDD

1

2

BYPASS=U5701.22:19:5 mm

P0_4

P0_2

P0_0

P7_0

P1_0

P1_2

2524232221201918171615

C5702

100PF

5% 50V CERM 402

P2_6

P1_4

282627

P2_4

P1_6

BYPASS=U5701.49:50:8 mm

1

C5705

0.1UF

10% 16V

2

X7R-CERM 402

P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0

THRML

PAD

TP_ISSP_SDATA_P1_0

ISSP SDATA/I2C SDA

1

C5703

0.1UF

10% 16V

2

X7R-CERM 402

BYPASS=U5701.22:19:8 mm

BYPASS=U5701.49:50:11 mm

1

2

WS_KBD23 WS_KBD22 WS_KBD21 WS_KBD20 WS_KBD19 WS_KBD18

42

WS_KBD17

41

WS_KBD16N

40

WS_KBD15_C

39

WS_KBD14

38

WS_KBD13

37

WS_KBD12

36

WS_KBD11

35

WS_KBD10

34

WS_KBD9

33

WS_KBD8

32

WS_KBD7

31

WS_KBD1

30

WS_KBD2

29

WS_KBD3

57

WS_KBD4 WS_KBD5 WS_KBD6

Z2_CLKIN TP_P7_7

(PP3V3_S3_PSOC)

1

C5701

4.7UF

20%

6.3V

2

X5R 603

BYPASS=U5701.22:19:11 mm

C5706

4.7UF

20%

6.3V X5R 603

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

43

7

44

7

IC

TMP102

3V3 LDO

PSOC

18V BOOSTER

SMC Manual Reset & Isolation

Left shift, option & control keys combined with power button cause SMC RESET# assertion. Keys ANDed with PSOC power to isolate when PSOC is not powered.

B

43

7

TPAD Buttons Disable

43

BUTTON_DISABLE

54 36 35

43

SSM6N15FEAPE

SMC_LID

IN

Q5701

SOT563

2

PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

6

D

THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED

SG

1

LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V

A

7

43

7

8 7 5 4 2 1

PIN NAME

V+

VDD VOUT

VDD

VIN

=PP3V42_G3H_TPAD

43

8

=PP3V3_S3_TPAD

44 43

8

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KBD

WS_CONTROL_KBD

CURRENT

10UA 80UA

60MA (MAX) 60MA (MAX)

8MA (TYP) 14MA (MAX)

4MA (MAX)

R_SNS V_SNS POWER

9

OUT_A

OUT_B

OUT_A

OUT_B

0.255E-6 W

16.32E-6 W

0.72E-3 W

75.2E-6 W

4

8

4

8

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

CRITICAL

2

IN_A1

(IPD)

3

IN_A2

(IPD)

7

IN_A3_B2

(IPD)

6

IN_B1

(IPD)

CRITICAL

2

IN_A1

(IPD)

3

IN_A2

(IPD)

7

IN_A3_B2

(IPD)

6

IN_B1

(IPD)

0.0255 V

0.204 V

0.6 V

0.012 V

0.021 V

0.0188 V

1

VDD

U5750

SLG4AP006

TDFN

THRM

GND

PAD

5

1

VDD

U5755

SLG4AP006

TDFN

THRM

GND

PAD

5

36E-3 W

96E-6 W

294E-6 W

1

C5750

0.1UF

10% 16V

2

X7R-CERM 402

WS_LEFT_SHIFT_KEY

WS_LEFT_OPTION_KEY

1

C5755

0.1UF

10%

2

16V X7R-CERM 402

SSM6N15FEAPE

SMC_TPAD_RST

WS_CONTROL_KEY

36 35

Q5701

SOT563

36

43

SMC_ONOFF_L

OUT

PLACEMENT_NOTE=NEAR J5713

43

Pull-up in U5010.

3

D

5

SG

4

43

Keyboard Connector

=PP3V3_S3_TPAD

44 43

8

=PP3V42_G3H_TPAD

43

8

WS_KBD1

43

7

WS_KBD2

43

7

WS_KBD3

43

7

WS_KBD4

43

7

WS_KBD5

43

7

WS_KBD6

43

7

WS_KBD7

43

7

WS_KBD8

43

7

WS_KBD9

43

7

WS_KBD10

43

7

WS_KBD11

43

7

WS_KBD12

43

7

WS_KBD13

43

7

WS_KBD14

43

7

WS_KBD15_CAP

7

WS_KBD16_NUM

7

WS_KBD17

43

7

WS_KBD18

43

7

WS_KBD19

43

7

WS_KBD20

43

7

WS_KBD21

43

7

WS_KBD22

43

7

WS_KBD23

43

7

WS_KBD_ONOFF_L

7

WS_LEFT_SHIFT_KBD

43

7

WS_LEFT_OPTION_KBD

43

7

WS_CONTROL_KBD

43

7

SYNC_MASTER=T27_MLB

PAGE TITLE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

WS_KBD15_C

WS_KBD16N

C5710

0.1UF

20% 10V

CERM

402

SMC_TPAD_RST_L

LED:K6_K69

R5714

470

1 2

1% 1/16W MF-LF

402

R5715

10K

1 2

1% 1/16W MF-LF

402

R5710

1K

1 2

5% 1/16W

1

MF-LF

402

2

OUT

36

32

NC

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

31

NC

F-RT-SM

FF14-30A-R11B-B-3H

J5713

CRITICAL

518S0637

SYNC_DATE=02/16/2010

WELLSPRING 1

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

57 OF 109

SHEET

43 OF 76

SIZE

D

C

B

A

D

345678

2 1

D

OMIT

=PP5V_S3_TPAD

8

C

R5805

SHORT

C5816

0.1UF

X7R-CERM

BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION

- DROOP LINE REGULATION

- RIPPLE TO MEET ERS

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

NONE NONE NONE

402

16V

10%

402

12

212

PP5V_S3_P18V5S3

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V

PP5V_S3_P18V5S3_VIN

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=5V

1

C5817

2.2UF

10%

16V

X5R 603

NC

1

L

3

DO

THRML

PAD

CRITICAL

L5801

3.3UH-870MA

VLF3010AT-SM-HF

2

VIN

U5805

TPS61045

QFN

CTRL

CRITICAL

PGND

6

7

9

GND

21

4

FB

5

8

SW

P18V5S3_SW

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE

P18V5S3_FB

Z2_BOOST_EN

1

R5811

100K

1% 1/16W MF-LF 402

2

CRITICAL

D5802

B0520WSXG

C5818

44

7

SOD-323

1 2

39PF

CERM

50V

OMIT

R5806

SHORT

1UF

25V

1 2

NONE NONE NONE

402

1

10%

2

X5R

PP18V5_S3_R

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V

1

R5812

1

1M

1%

5%

1/16W MF-LF

2

402

2

1

R5813

71.5K

1% 1/16W MF-LF 402

2

C5819

603-1

PP18V5_S3

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V

44

7

IPD Flex Connector

CRITICAL

J5800

=PP3V3_S3_TPAD

43

8

Z2_CS_L

43

7

Z2_DEBUG3

43

7

Z2_MOSI

43

7

Z2_MISO

43

7

Z2_SCLK

43

7

Z2_BOOST_EN

44

7

Z2_HOST_INTN

43

7

Z2_CLKIN

43

7

55560-0228

M-ST-SM 2 4 6

8

10 12 14 16 18

NC

20 22

1 3 5 7 9 11 13 15 17 19 21

PP18V5_S3

Z2_KEY_ACT_L Z2_RESET PSOC_F_CS_L PICKB_L PSOC_MISO PSOC_MOSI PSOC_SCLK =I2C_TPAD_SDA =I2C_TPAD_SCL

7

44

43

7

43

7

43

7

43

7

43

7

43

7

43

7

38

D

C

516S0689

B

A

DO NOT SYNC FROM T27. REMOVED KEYBOARD BKLIGHT CIRCUIT

8 7 5 4 2 1

B

SIZE

A

D

SYNC_MASTER=MASTER

PAGE TITLE

WELLSPRING 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

58 OF 109

SHEET

44 OF 76

36

345678

2 1

D

R5921 PULLS UP SEL PINS TO ENTER STANDBY MODE WHEN PIN IS NOT BEING DRIVEN BY SMC

10K

402

R5922

10

1 2

5% 1/16W MF-LF

402

1

5%

2

C5922

0.1UF

SMS_PWRDN

MAKE_BASE=TRUE

10% 16V X5R 402

1

2

PP3V3_S3_SMS_FILT

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

=PP3V3_S3_SMS

8

R5921

C

SMS_ONOFF_L

35

IN

1/16W MF-LF

Analog SMS

C5926

0.01UF

10% 16V CERM 402

7

DNC

NC

12

SEL0

6

SEL1

5

ST

1

2

VDD

U5920

BMA141

LGA

CRITICAL

GND

4

3

AMUX

AX

AY

AZ

11

NC

10

SMS_X_AXIS

9

SMS_Y_AXIS

8

SMS_Z_AXIS

C5923

0.033UF

10% 16V X5R 402

Desired orientation when placed on board top-side:

35

OUT

35

OUT

35

OUT

1

C5924

0.033UF

10% 16V

2

X5R 402

1

C5925

0.033UF

10% 16V

2

X5R 402

Circle indicates pin 1 location when placed in correct orientation

+Z (up)

+Y

Front of system

+X

D

C

B

A

DO NOT SYNC WITH K84. REMOVED NO STUFF ON C5923,C5924,C5925. ADDED PLACE NEARS

8 7 5 4 2 1

C4950-C4952 CAP VALUES WILL BE USED TO GET CUT-OFF FREQUENCY OF ~146HZ

PLACE_NEARs:

C5923.1:

PLACE_NEAR=U4900.M10:2.54MM PLACE_NEAR=U4900.N9:2.54MM

C5924.1:

PLACE_NEAR=U4900.K10:2.54MM

C5925.1:

36

SYNC_MASTER=MASTER

PAGE TITLE

SMS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

59 OF 109

SHEET

45 OF 76

SIZE

B

A

D

345678

DEBUG_ADC

R6003

10

PLACEMENT_NOTE=PLACE NEAR Q3450

PP3V3_WLAN_F

30

PLACE_NEAR=J3401.22:25.4mm

D

46

OMIT

XW6010

SM

1 2 1 2

=PP5V_S3_DEBUG_ISNS

8

P3V3_WLAN_F_XW

DEBUG_ADC

1

R6010

634K

1% 1/16W MF-LF 402

2

P3V3_WLAN_F_DIV DEBUG_ADC

1

R6011

1M

1% 1/16W MF-LF 402

2

33

PLACEMENT_NOTE=PLACE RC NEAR U6000

DEBUG_ADC

R6012

226K

1 2

1% 1/16W MF-LF

402

DIVIDER: ~ 2/3

DEBUG_ADC

R6030

243

IN

ISNS_AIRPORT_P

75 30

C

1 2

1% 1/16W MF-LF

402

ISNS_AIRPORT_R_P

75

DEBUG_ADC

R6031

243

75 30

IN

ISNS_AIRPORT_N

1 2

1% 1/16W MF-LF

402

ISNS_AIRPORT_R_N

75

NO STUFF

C6032

470PF

10% 50V

CERM

402

1

2

DEBUG_ADC

1

R6032

301K

1% 1/16W MF-LF 402

2

DEBUG_ADC

PLACEMENT_NOTE=PLACE NEAR Q4590

PP5V_SW_ODD

7

PLACE_NEAR=J4500.9:25.4mm

ADC_CH0

1

2

DEBUG_ADC

C6012

2.2UF

10%

6.3V X5R 402

46

DEBUG_ADC

5

1

+IN

V+

3

-IN

V-

2

R6033

301K

1 2

1%

1/16W

NO STUFF

MF-LF

C6033

402

470PF

1 2

10% 50V

CERM

402

U6030

OPA330

SC70-5

4

OMIT

XW6020

SM

P5V_SW_ODD_XW

DEBUG_ADC

1

C6030

0.1UF

20% 10V

2

CERM 402

ISNS_AIRPORT_IOUT

GAIN: 1239X

DEBUG_ADC

1

R6020

1M

1% 1/16W MF-LF 402

2

DEBUG_ADC

1

R6021

681K

1% 1/16W MF-LF 402

2

PLACEMENT_NOTE=PLACE RC NEAR U6000

DEBUG_ADC

R6022

226K

1 2

1/16W MF-LF

DIVIDER: ~ 2/5

DEBUG_ADC

R6034

226K

1 2

1% 1/16W MF-LF

402

1%

402

ADC_CH2

DEBUG_ADC

1

C6034

2.2UF

10%

6.3V

2

X5R 402

46

ADC_CH1P5V_SW_ODD_DIV

DEBUG_ADC

1

C6022

2.2UF

10%

6.3V

2

X5R 402

75 33

46

IN

=PP5V_S3_DEBUG_ADC_AVDD

8

ADC_CH3 unused, so pulling down.

DEBUG_ADC

ISNS_ODD_P

1 2

DEBUG_ADC

ISNS_ODD_N

1 2

1 2 1 2

1/16W MF-LF

402

1

R6005

1K

5% 1/16W MF-LF

402

2

R6050

499

1% 1/16W MF-LF

402

R6051

499

1% 1/16W MF-LF

402

PP5V_S3_DEBUG_ADC_AVDD_FILT

5%

75

DEBUG_ADC

1

C6000

0.1UF

20% 10V

2

CERM 402

ADC_CH0

46

ADC_CH1

46

ADC_CH2

46

ADC_CH3 ADC_CH4

46

ADC_CH5

46

ADC_CH6

46

ADC_CH7

46

I2C ADDRESS: 0X10 / 0X11 ADC RANGE: 0V TO 4.096V LSB: 0.001V

ISNS_ODD_R_P

ISNS_ODD_R_N

NO STUFF

C6052

470PF

CERM

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

DEBUG_ADC

1

C6001

10UF

20%

6.3V

2

X5R 603

13

12

U6000

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

COM

LTC2309

DEBUG_ADC

22

23 24

1

2 3

4 5

6

GND

11

10918

1

3

DEBUG_ADC

1

R6052

1

280K

10% 50V

402

1% 1/16W MF-LF

2

402

2

DEBUG_ADC

R6053

1 2

280K

1/16W MF-LF

402

PP5V_S3_DEBUG_ADC_DVDD_FILT

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

21

DVDDAVDD

AD0

QFN

AD1

SDA SCL

VREF

REFCOMP

THRM

PAD

202519

DEBUG_ADC

U6051

OPA330

5

SC70-5

+IN

V+

4

-IN

V-

2

1%

NO STUFF

C6053

470PF

1 2

10% 50V

CERM

402

2 1

14

15

17

ADC_SDA

16

ADC_SCL

7

8

ISNS_ODD_IOUT

DEBUG_ADC

1

C6002

0.1UF

20% 10V

2

CERM 402

DEBUG_ADC

R6001

1 2

1/16W MF-LF

ADC_VREF

ADC_REFCOMP DEBUG_ADC

1

C6004

0.1UF

20% 10V

2

CERM 402

DEBUG_ADC

1

C6051

0.1UF

20% 10V

2

CERM 402

PLACEMENT_NOTE=PLACE RC NEAR U6000

GAIN: 561X

PLACEMENT_NOTE=PLACE CLOSE TO U4900

33

5%

DEBUG_ADC

402

1 2

DEBUG_ADC

1

C6003

10UF

20%

6.3V

2

X5R 603

R6002

33

5% 1/16W MF-LF

402

DEBUG_ADC

1

C6005

10UF

20%

6.3V

2

X5R 603

R6054

226K

1 2

1/16W MF-LF

402

1%

DEBUG_ADC

R6004

10

=PP5V_S3_DEBUG_ADC_DVDD

5% 1/16W MF-LF

402

=I2C_SMC_ADCS_SDA

PLACEMENT_NOTE=PLACE CLOSE TO U4900

=I2C_SMC_ADCS_SCL

DEBUG_ADC

1

C6006

2.2UF

20%

6.3V

2

CERM 402-LF

ADC_CH4

DEBUG_ADC

1

C6054

2.2UF

10%

6.3V

2

X5R 402

8

D

38

BI

38

IN

46

C

=PP5V_S3_DEBUG_ISNS

46

8

B

75 33

=PP5V_S3_DEBUG_ISNS

8

46

IN-

3

V+

U6050

INA210

SC70

DEBUG_ADC

GND

2

OUT

6

14

REFIN+

A

75 67

IN

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

5

DEBUG_ADC

1

C6050

0.1UF

20% 10V

2

CERM 402

ISNS_LCDBKLT_IOUT

GAIN: 200X

PLACEMENT_NOTE=PLACE RC NEAR U6000

DEBUG_ADC

R6074

226K

1 2

1% 1/16W MF-LF

402

ADC_CH6

DEBUG_ADC

1

C6074

2.2UF

10%

6.3V

2

X5R 402

46

PPVOUT_S0_LCDBKLT

67 64

7

ISNS_HDD_P

IN

ISNS_HDD_N

IN

PLACE_NEAR=J9000.38:25.4mm

OMIT

XW6080

1 2

8 7 5 4 2 1

DEBUG_ADC

SM

PVOUT_S0_LCDBKLT_XW

R6060

412

1 2

1/16W MF-LF

R6061

412

1 2

1/16W MF-LF

DEBUG_ADC

1

R6080

2

PVOUT_S0_LCDBKLT_DIV DEBUG_ADC

1

R6081

2

1%

402

1%

402

1M

1% 1/16W MF-LF 402

75K

1% 1/16W MF-LF 402

75

ISNS_HDD_R_P

ISNS_HDD_R_N

NO STUFF

C6062

470PF

PLACEMENT_NOTE=PLACE RC NEAR U6000

CERM

10% 50V

402

DEBUG_ADC

1

2

DEBUG_ADC

R6082

226K

1 2

1% 1/16W MF-LF

402

DIVIDER: 3/40

1

R6062

348K

1% 1/16W MF-LF 402

2

36

ADC_CH7

DEBUG_ADC

1

C6082

2.2UF

10%

6.3V

2

X5R 402

DEBUG_ADC

R6063

1 2

46

1

3

348K

1% 1/16W MF-LF

402

+IN

-IN

DEBUG_ADC

U6061

OPA330

5

SC70-5

V+

V-

2

NO STUFF

C6063

470PF

1 2

10% 50V

CERM

402

4

DEBUG_ADC

1

C6061

0.1UF

20% 10V

2

CERM 402

PLACEMENT_NOTE=PLACE RC NEAR U6000

ISNS_HDD_IOUT

GAIN: 845X

SYNC_MASTER=MASTER

PAGE TITLE

DEBUG_ADC

R6064

226K

1 2

1% 1/16W MF-LF

402

DEBUG SENSORS AND ADC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

ADC_CH5

1

2

DEBUG_ADC

C6064

2.2UF

10%

6.3V X5R 402

46

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

60 OF 109

SHEET

46 OF 76

SIZE

B

A

D

345678

2 1

D

=PP3V3_S5_ROM

8

SPI:31MHZ&SPI:62MHZ

R6150

C

NOTE: If HOLD* is asserted ROM will ignore SPI cycles.

1/16W MF-LF

IN IN

72 37

IN

37 19

7

IN

1

10K

R6101

3.3K

5%

5% 1/16W MF-LF

402

2

SPI_MLB_CLK

SPI_MLB_CS_L SPI_WP_L SPIROM_USE_MLB

SPI:25MHZ&SPI:41MHZ

C6100

0.1UF

R6152

10K

1/16W MF-LF

1

20% 10V

2

CERM

402

6

SCLK

1

CE*

3

WP*/ACC

7

HOLD*

1

5%

402

2

CRITICAL

VCC

U6100

32MBIT

SOP

OMIT

GND

SI/SIO0

SO/SIO1

4 8

MX25L3205DM2I-12G

SPI:41MHZ&SPI:62MHZ

1

R6151

10K

5% 1/16W MF-LF 402

2

5

2

SPI_MLB_MOSI

SPI_MLB_MISO

SPI:25MHZ&SPI:31MHZ

1

R6153

10K

5% 1/16W MF-LF 402

2

72 37 72 37

72 37

OUT

D

C

MCP89 SPI Frequency Select

Frequency

25.0 MHz

31.2 MHz

B

41.7 MHz

62.5 MHz

NOTE: 42 & 62 MHz use FAST_READ command.

A

8 7 5 4 2 1

SPI_MOSI

0 0 1 1

SPI_CLK

0 1 0 1

B

SIZE

A

D

SYNC_MASTER=T27_MLB

PAGE TITLE

SPI ROM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

61 OF 109

SHEET

47 OF 76

36

345678

AUDIO CODEC

L6201

8

IN

=PP1V8R1V5_S0_AUDIO

FERR-220-OHM

0402

D

GND_AUDIO_HP_AMP

52 50 48

PP4V5_AUDIO_ANALOG

48

7

IN

GPIO0 = ANALOG SW CONTROL

GPIO1 = HP AMP CONTROL

GPIO3 = SPKR AMP SHDN CONTROL

53 52 48

52

OUT

50

OUT

NC

51

OUT

53

IN

8

IN

AUD_GPIO_0 AUD_GPIO_1 TP_AUD_GPIO_2 AUD_GPIO_3

AUD_SENSE_A

=PP3V3_S0_AUDIO

VD MUST BE LESS THAN OR EQUAL TO VL_HD

21

1

C6226

2

0.1UF

10% 16V X5R 402

C6211

2

0.1UF

10% 16V X5R 402

C6221

10UF

20%

6.3V X5R 603-1

CRITICAL

C6210

1

R6210

2.67K

1% 1/16W MF-LF 402

2

4.7UF

20% 4V X5R-1 402

PP1V8R1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V

CRITICAL

1

C6220

10UF

20%

6.3V

2

C6222

2.2UF

20%

6.3V CERM 402-LF

X5R

603-1

212

C6219

TANT-POLY

2012-LLP

CS4206_FP CS4206_FN

CS4206_FLYP CS4206_FLYC

1

C6223

CS4206_FLYN

10UF

2.2UF

402-LF

20% 16V

20%

6.3V CERM

1

2

VBIAS_DAC

C

HDA_BIT_CLK

72 19

IN

HDA_SYNC

72 19

IN

72 19

OUT

IN IN

NC

52

OUT

HDA_SDIN0

HDA_SDOUT HDA_RST_L

TP_AUD_SPDIF_IN

AUD_SPDIF_OUT

72 19

B

GND_AUDIO_CODEC

53 52 49 48

R6211

22

1 2

5% 1/16W MF-LF

402

HDA_SDIN_CODEC

72

R6212

1 2

1/16W MF-LF

AUD_SPDIF_OUT_CHIP

39

5%

402

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM VOLTAGE=0V

APPLE P/N 353S2355

9

VA_REF

VD

29

VBIAS_DAC

44

VHP_FILT+

41

VHP_FILT-

2

GPIO0/DMIC_SDA1

12

GPIO1/DMIC_SDA2

/SPDIF_OUT2

14

GPIO2

15

GPIO3

13

SENSE_A

45

FLYP

43

FLYC

42

FLYN

3

VL_HD

1

VL_IF

6

BITCLK

10

SYNC

8

SDI

5

SDO

11

RESET*

47

SPDIF_IN

48

SPDIF_OUT

THRM_PAD

DGND

7

24

VA_HP

U6201

CS4206ACNZC

QFN

CRITICAL

49

46

25

VA

HPOUT_L HPOUT_R

HPREF

LINEOUT_L1+ LINEOUT_L1LINEOUT_R1+ LINEOUT_R1-

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-

MICBIAS

LINEIN_L+ LINEIN_CLINEIN_R+

MICIN_L+ MICIN_LMICIN_R+ MICIN_R-

VREF+_ADC

DMIC_SCL

AGND

26

VCOM

C6218

0.1UF

1

10% 16V

2

X5R 402

38

40

39

35 34

36

37

31 30

32

33

16

CS4206_VCOM

28

21

22 23

18

17 19

20

27

4

C6224

0603-SM

1UF

TANT

=PP5V_S3_AUDIO

=PP3V3R1V5_S0_AUDIO

PP4V5_AUDIO_ANALOG

1

C6217

10UF

2

20% 16V TANT-POLY 2012-LLP

C6216

1UF

10% 10V X5R 402-1

1

2

C6215

0.1UF

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

1

10% 16V

2

X5R 402

C6214

0.1UF

1

C6213

10UF

CRITICAL

10% 16V X5R 402

20%

6.3V

2

X5R 603-1

GND_AUDIO_HP_AMP

GND_AUDIO_CODEC

AUD_HP_PORT_L AUD_HP_PORT_R

AUD_HP_PORT_REF

TP_AUD_LO1_P_L TP_AUD_LO1_N_L

AUD_LO1_R_P AUD_LO1_R_N

AUD_LO2_L_P AUD_LO2_L_N AUD_LO2_R_P AUD_LO2_R_N

AUD_CODEC_MICBIAS

AUD_MIC_IN_L_P AUD_MIC_IN_L_N AUD_MIC_IN_R_P AUD_MIC_IN_R_N

CS4206_VREF_ADC

TP_AUD_DMIC_CLK

1

C6225

10UF

20% 16V

2

TANT-POLY 2012-LLP

NC

NOSTUFF

1

R6213

100K

5% 1/16W MF-LF 402

2

2 1

52 50 48

8

48

7

IN

52 50 48

53 52 49 48

50

OUT

50

OUT

52

IN

NC NC

51

OUT

SUB SPKR AMP. SIG. SOURCE

51

OUT

51

OUT

LFT. SPKR AMP. SIG. SOURCE

51

OUT

51

OUT

RT. SPKR AMP. SIG. SOURCE

51

OUT

53

OUT

AUD_LI_P_L AUD_LI_REF AUD_LI_P_R

49

IN

49

IN

49

IN

53

IN

53

IN

53

IN

53

IN

EXT MIC CODEC INPUT

BI MIC CODEC INPUT

D

C

B

4.5V POWER SUPPLY FOR CODEC APPLE P/N 353S2281

L6200

52 50 48

53 52 48

8

IN

8

IN

=PP5V_S3_AUDIO

=PP3V3_S0_AUDIO

FERR-220-OHM

0402

R6200

2.21K

1 2

1% 1/16W MF-LF

402

A

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=5V

21

4V5_REG_IN

4V5_REG_EN

1

C6200

1UF

10% 10V

2

X5R 402

XW6200

SM

1 2

NOSTUFF

R6201

0

1 2

5% 1/16W MF-LF

402

XW6201

SM

1 2

1

2

6

4

C6201

1UF

10% 10V X5R 402

IN

EN

U6200

TPS71745

SON

CRITICAL

GND

2

OUT

NR/FB

NC

1

3

4V5_NR

5

1

C6202

0.1UF

10% 16V

2

X7R-CERM

402

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=0V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

1

C6203

1UF

10% 10V

2

X5R 402

GND_AUDIO_CODEC

GND_AUDIO_HP_AMP

48

7

OUT

53 52 49 48

52 50 48

8 7 5 4 2 1

NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS

36

SYNC_MASTER=AUDIO

PAGE TITLE

AUDIO: CODEC/REGULATOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

62 OF 109

SHEET

48 OF 76

SIZE

A

D

345678

2 1

D

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS) FC_HP = 3.6 HZ FC_LP = 43KHZ VIN = 2VRMS, CODEC VIN = 1.14 VRMS

CRITICAL

R6301

7.87K

52

IN

AUD_LI_L

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

1 2

1% 1/16W MF-LF

402

AUD_LI_L_DIV

MIN_LINE_WIDTH=.1MM

C

NOSTUFF

1

C6303

820PF

10% 50V

2

CERM 402

MIN_LINE_WIDTH=.1MM

AUD_LI_GND

52

IN

53 52 48

GND_AUDIO_CODEC

IN

B

R6311

7.87K

52

IN

AUD_LI_R

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

1 2

1% 1/16W MF-LF

402

MIN_NECK_WIDTH=.1MM

1

R6300

10

1% 1/16W MF-LF 402

2

AUD_LI_R_DIV

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

NOSTUFF

1

C6313

820PF

10% 50V

2

CERM 402

1

R6302

21.5K

1% 1/16W MF-LF 402

2

1

R6312

21.5K

1% 1/16W MF-LF 402

2

C6301

2.2UF

1 2

20% 10V

X5R-CERM

402

CRITICAL

C6302

2.2UF

1 2

20% 10V

X5R-CERM

402

CRITICAL

C6312

2.2UF

1 2

20% 10V

X5R-CERM

402

CRITICAL

C6311

2.2UF

1 2

20% 10V

X5R-CERM

402

AUD_LI_P_L

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MMMIN_NECK_WIDTH=.1MM

AUD_LI_REF

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_P_R

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

48

OUT

C

48

OUT

B

48

OUT

A

8 7 5 4 2 1

36

PAGE TITLE

AUDIO: LINE INPUT FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

051-8561

REVISION

BRANCH

PAGE

63 OF 109

SHEET

49 OF 76

C.0.0

SIZE

A

D

345678

2 1

D

21

1

2

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_PP5V_F

1

2

C6521

10UF

20%

6.3V X5R 603

C6520

0.1UF

10% 16V X7R-CERM 402

1

R6522

100K

5% 1/16W MF-LF 402

2

R6530

13.7K

1 2

1% 1/16W MF-LF

402

L6520

=PP5V_S3_AUDIO

8

48 52

R6520

CS4206 HP OUTPUT ZOBEL NETWORK

AUD_HP_PORT_L

48 50

IN

AUD_HP_ZOBEL_L

NC

C

GND_AUDIO_HP_AMP

48 50 52

IN

AUD_HP_ZOBEL_R

NC

AUD_HP_PORT_R

48 50

IN

NOSTUFF

CRITICAL

C6500

X7R-CERM

NOSTUFF

R6510

NOSTUFF

CRITICAL

C6510

0.1UF

X7R-CERM

0.1UF

R6500

39

5% 1/16W MF-LF

402

10% 16V

402

1

10% 16V

2

402

1

39

5% 1/16W MF-LF

402

2

1

2

1

2

48

IN

AUD_GPIO_1

0

1 2

5% 1/16W MF-LF

402

B

FERR-120-OHM-1.5A

AUD_LO_AMP_INL_M

50

AUD_LO_AMP_INR_M

50

AUD_GPIO_1_R

GND_AUDIO_HP_AMP

48 50 52

0402-LF

48 50

IN

HP/LO AMP

APN: 353S1637

12

VDD

CRITICAL

6

INL

8

INR

MAX9724A

5

SHDN*

PAD

SGND

THRM

7

13

MAX9724 GAIN/FILTER COMPONENTS

AV_PB = -1V/V, FC_LPF = 35.2KHZ

AUD_LO_AMP_INL_M

U6500

TQFN

2

PGND

9

SVSS

OUTL OUTR

C1P C1N

11

10

1

3

PVSS

4

MAX9724_SVSS

CRITICAL

1

C6522

1UF

10% 10V

2

X5R 402

CRITICAL

C6530

330PF

1 2

5% 50V COG 402

R6531

13.7K

1 2

1%

1/16W MF-LF

402

50

MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.2MM

MAX9724_C1P

MAX9724_C1N

CRITICAL

1

C6523

1UF

10% 10V

2

X5R 402

CRITICAL

1

C6524

1UF

10% 10V

2

X5R 402

AUD_LO_AMP_OUTL

1

R6523

2.21K

1%

1/16W

MF-LF

402

2 1

AUD_LO_AMP_OUTL

AUD_LO_AMP_OUTR

R6524

2.21K

1% 1/16W MF-LF 402

2

50 52

OUT

50 52

OUT

50 52

OUT

D

C

B

48 50

IN

AUD_HP_PORT_R

R6532

13.7K

1 2

1% 1/16W MF-LF

402

A

8 7 5 4 2 1

AUD_LO_AMP_INR_M

36

50

R6533

13.7K

1 2

1% 1/16W MF-LF

402

CRITICAL

C6531

330PF

1 2

5%

50V COG 402

AUD_LO_AMP_OUTR

SYNC_MASTER=AUDIO

PAGE TITLE

50 52

OUT

AUDIO: HEADPHONE FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

65 OF 109

SHEET

50 OF 76

SIZE

A

D

345678

2 1

SATELLITE SUB

GAIN SPRK AMP. INPUT REFERRED CLIP POINT = ~-6dBFS

D

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

C

796Hz < HPF FC < 936Hz 80 Hz < HPF FC < 94 Hz

6DB (2V/V)

=PP5V_S3_AUDIO_AMP

51

8

L6610

AUD_LO2_R_P

48

IN

AUD_LO2_R_N

48

IN

AUD_GPIO_3

48

IN

SPKRAMP_SHDN

51

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

=PP5V_S3_AUDIO_AMP

51

8

FERR-1000-OHM

0402

L6611

FERR-1000-OHM

0402

L6620

AUD_LO1_R_P

48

IN

AUD_LO1_R_N

48

IN

SPKRAMP_SHDN

51

FERR-1000-OHM

SPKRAMP_INR_P

21

SPKRAMP_INR_N

21

R6610

21

0402

SPKRAMP_INSUB_P

L6621

FERR-1000-OHM

0402

0

1 2

5% 1/16W MF-LF

402

SPKRAMP_INSUB_N

21

CRITICAL

C6610

0.01UF

1 2

10% 25V X7R 402

CRITICAL

C6611

0.01UF

1 2

10% 25V X7R 402

CRITICAL

C6620

0.1UF

1 2

10%

16V

X5R 402

CRITICAL

C6621

0.1UF

1 2

10%

16V

X5R 402

C6607

1UF

10%

10V

X5R 402

LM48311_R_P LM48311_R_N

1

R6611

100K

5% 1/16W MF-LF 402

2

APN:353S2621

LM48311_SUB_P

LM48311_SUB_N

APN:353S2621

1

C6602

2

0.01UF

10% 16V CERM 402

C6608

1UF

10%

10V

X5R 402

PVDD

CRITICAL

U6610

LM48311

A1

IN+

C1

IN-

A2

SD*

PGND

B3

1

2

A1 C1

A2

PVDD

CRITICAL

U6620

LM48311

IN+ IN-

SD*

PGND

B3

BGA

D

CRITICAL

C6601

1

B1B2

VDD

A3

OUTA

C3

OUTB

GND

C2

47UF

20%

6.3V

2

TANT1 2012-LLP

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_P_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_R_N_OUT

52

7

OUT

52

7

OUT

C

CRITICAL

C6603

1

B1B2

VDD

A3

OUTA

C3

OUTB

GND

C2

47UF

20%

6.3V

2

TANT1 2012-LLP

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_P_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_SUB_N_OUT

52

7

OUT

52

7

OUT

B

APN:353S2621

=PP5V_S3_AUDIO_AMP

51

8

ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM

L6630

FERR-1000-OHM

21

0402

SPKRAMP_INL_P

48

IN

AUD_LO2_L_P

L6631

AUD_LO2_L_N

48

IN

A

SPKRAMP_SHDN

51

FERR-1000-OHM

0402

21

SPKRAMP_INL_N

CRITICAL

C6630

0.01UF

1 2

10% 25V X7R 402

CRITICAL

C6631

0.01UF

1 2

10% 25V X7R 402

LM48311_L_P

LM48311_L_N

C6609

1UF

10%

10V

X5R 402

1

2

B1B2

PVDD

VDD

CRITICAL

U6630

LM48311

BGA

A1

IN+

C1

IN-

A2

SD*

PGND

B3

A3

OUTA

C3

OUTB

GND

C2

8 7 5 4 2 1

CRITICAL

C6605

1

47UF

20%

6.3V

2

TANT1 2012-LLP

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_P_OUT

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM SPKRAMP_L_N_OUT

36

52

7

OUT

52

7

OUT

SYNC_MASTER=AUDIO

PAGE TITLE

AUDI0: SPEAKER AMP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

BRANCH

PAGE

66 OF 109

SHEET

51 OF 76

C.0.0

SIZE

A

D

=PP3V3_S0_AUDIO

53 48

8

D

APN:514-0750

AUDIO-JACK-TRANS-CFR-K86K87

C

J6700

F-RT-TH

CRITICAL

AUDIO

PHS DETECT

GND

HP DETECT

A - VIN B - VCC

OPERATING VOLTAGE 3.3

C - GND

POF

SHELL

SHIELD

PINS

8 2 1 7 6

5 3 4

9 10 11

12 13 14

AUD_CONNJ1_MIC

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

AUD_CONNJ1_SLEEVE

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_TIP AUD_CONNJ1_RING

AUD_IP_PERPH_DET_JACK

AUD_CONNJ1_TIPDET

1

C6700

1UF

10%

6.3V

2

CERM 402

AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

CRITICAL

DZ6702

6.8V-100PF

402

2

1

CRITICAL

DZ6701

6.8V-100PF

402

CRITICAL

DZ6705

6.8V-100PF

2

1

DZ6704

CRITICAL

6.8V-100PF

402

2

1

402

CRITICAL

2

DZ6703

6.8V-100PF

402

1

DZ6700

6.8V-100PF

CRITICAL

1

2

402

1

FERR-1000-OHM

FERR-120-OHM-1.5A

FERR-220-OHM

1

C6701

100PF

5%

50V

2

CERM 402

L6701

21

0402

L6702

21

0402

CRITICAL

L6703

L6704

0402

CRITICAL

L6705

0402

L6706

0402

10K

5% 1/16W MF-LF

402

4.7

5% 1/16W MF-LF

402

21

0402-LF

CRITICAL

FERR-220-OHM

FERR-1000-OHM

R6700

1 2

R6701

1 2

AUD_SPDIF_OUT

21

AUD_IP_PERPH_DET

21

AUD_J1_SLEEVEDET_R

AUD_J1_TIPDET_R

HS_MIC_P

HS_MIC_N

AUD_CONN_L

AUD_CONN_R

345678

48

IN

75 53

OUT

PLACE_NEAR=J6700:3MM

XW6702

75 53

OUT

52

BI

52

BI

53

OUT

53

OUT

53

OUT

SM

1 2

PLACE_NEAR=J6700:3MM

XW6700

SM

GND_AUDIO_HP_AMP

1 2

PLACE_NEAR=J6700:3MM

XW6701

SM

1 2

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

MIC CONNECTOR

APN:518S0520

BI_MIC_N

75 53

7

BI_MIC_SHIELD

53

7

BI_MIC_P

75 53

7

2 1

AUD_HP_PORT_REF

AUD_LI_GND

AUD_CONN_GND

49

52

50 48

48

OUT

CRITICAL

J6701

78171-0003

M-RT-SM

4

1 2 3

5

D

C

SPEAKER CONNECTORS

B

A

GND STUFFING OPTIONS FOR CMOS SWITCH

DO NOT SYNC K84. UPDATED PLACE NEARS

8 7 5 4 2 1

AUD_LO_AMP_OUTL

50

IN

AUD_LO_AMP_OUTR

50

IN

AUD_LI_L

49

OUT

AUD_LI_R

49

OUT

AUD_GPIO_0

48

IN

AUD_CONN_GND

52

53 49 48

R6715

GND_AUDIO_CODEC

50 48

0

1 2

5% 1/16W MF-LF

402

=PP5V_S3_AUDIO

8

AUD_SWITCH_GND

R6714

0

1 2

5% 1/16W MF-LF

402

1

R6721

100K

5% 1/16W MF-LF 402

2

1

C6710

1UF

10% 10V

2

X5R 402

C6711

0.0033UF

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.2MM

MIN_NECK_WIDTH=0.15MM

10% 50V CERM

402

SWITCH_CP

1

2

MAX14560EWC+

C4

NC1

C1

NC2

A4

NO1

A1

NO2

C2

CB

A2

NEG

A3

VCC

U6700

WLP

CRITICAL

OMIT

GND

C3

B3

COM1

COM2

EN*

B4

B1

B2

ANALOG AUDIO IO SWITCH

GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED

NOSTUFF

R6727

0

1 2

5% 1/16W MF-LF

402

PART#

353S2803 CRITICAL

OLD_AUDIO_SWITCH

1

R6713

24K

5% 1/16W MF-LF 402

2

DESCRIPTION

QTY

1

IC, MAX14560, Dual SPDT

1

IC, MAX14504, Dual SPDT

AUD_CONN_L

OLD_AUDIO_SWITCH

1

R6712

24K

5% 1/16W MF-LF 402

2

AUD_CONN_R

52

BI

52

BI

REFERENCE DESIGNATOR(S)

U6700

SPKRAMP_SUB_P_OUT

51

7

IN

SPKRAMP_SUB_N_OUT

51

7

IN

NOSTUFF NOSTUFF

C6705

100PF

SPKRAMP_R_P_OUT

51

7

IN

SPKRAMP_R_N_OUT

51

7

IN

C6707

CRITICAL BOM OPTION

CRITICAL353S2536

36

1

5%

50V

2

CERM

402

NOSTUFF

1

100PF

5%

50V

2

CERM CERM

402

NEW_AUDIO_SWITCH

OLD_AUDIO_SWITCH

51

1

C6704

100PF

5%

50V

2

CERM 402

NOSTUFF

1

C6706

100PF

2

SPKRAMP_L_P_OUT

7

IN

SPKRAMP_L_N_OUT

7

IN

NOSTUFF

C6703

100PF

R6707

1 2

R6709

5%

50V

402

TABLE_5_HEAD

TABLE_5_ITEM

APN:518S0519

NOSTUFF

1

C6702

5%

50V

2

CERM

402

0

5% 1/10W MF-LF

603

R6708

1 2

1/10W MF-LF

0

1 2

5% 1/10W MF-LF

603

R6710

100PF

5%

50V

2

CERM 402

SPKRAMP_SUB_P_OUT_CONN SPKRAMP_SUB_N_OUT_CONN

0

5%

603

SPKRAMP_R_P_OUT_CONN

SPKRAMP_R_N_OUT_CONN

0

1 2

5% 1/10W MF-LF

603

SYNC_MASTER=AUDIO

PAGE TITLE

AUDIO: JACK

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

CRITICAL

J6702

78171-0002

M-RT-SM 3

1 2

4

78171-0002

Apple Inc.

LEFT PIEZO

CRITICAL

J6703

M-RT-SM

3

1

DYN. FULL RANGE

2

4

CRITICAL

J6704

78171-0003

M-RT-SM

4

1 2

RT. PIEZO

3

5

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

67 OF 109

SHEET

52 OF 76

SIZE

B

A

D

CODEC OUTPUT SIGNAL PATHS

FUNCTION HP/LINE OUT LINE IN SATELLITES SUB SPDIF OUT

CODEC INPUT SIGNAL PATHS

FUNCTION BUILT-IN MIC

D

48

52

53 52 49 48

53

HEADSET MIC

AUD_SENSE_A

OUT

PP3V3_S0_AUDIO_F

53

AUD_J1_TIPDET_R

IN

GND_AUDIO_CODEC

PP3V3_S0_AUDIO_F

C

AUD_J1_SLEEVEDET_R

53 52

IN

GND_AUDIO_CODEC

53 52 49 48

MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM

PP3V3_S0_AUDIO_F

53

VOLTAGE=3.3V

FERR-1000-OHM

8

IN

=PP3V3_S0_AUDIO

53 52 48

PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA

B

AUD_IP_PERPH_DET

52

GND_AUDIO_CODEC

53 52 49 48

L6862

0402

VOLUME 0X02 (2) 0X05 (5) 0X04 (4) 0X03 (3) N/A

1

R6801

300K

5% 1/16W MF-LF 402

2

R6802

47K

1 2

5% 1/16W MF-LF

402

1

R6804

220K

5% 1/16W MF-LF 402

2

21

1

C6802

0.01UF

10% 16V

2

CERM 402

C6861

0.1UF

10V 402

MIKEY

1

R6862

300K

5% 1/16W MF-LF 402

2

SSM6N15FEAPE

AUD_J1_DET_RC

1

C6801

0.1UF

20%

2

CERM

R6803

220K

1 2

5% 1/16W MF-LF

402

SSM6N15FEAPE

1

20%

2

CERM

R6860

1 2

CONVERTER 0X02 (2) 0X05 (5) 0X04 (4) 0X03 (03) 0X08 (8)

CONVERTER 0X06 (6) 0X06 (6)

PIN COMPLEX 0X09 (9,A) 0X0C (12) 0X0B (11) 0X0A (10) 0X10 (16)

PIN COMPLEX 0X0D (13,B,RIGHT) 0X0D (13,V22,B,LEFT)

APN:376S0613

AUD_OUTJACK_INSERT_L

3

SOT563

D

5

SG

4

10V 402

Q6800

AUD_J1_SLEEVEDET_INV

6

SOT563

D

2

SG

1

Q6800

EXTRACTION NOTIFICATION CKT

MIKEY

Q6802

MIKEY

15K

5% 1/16W MF-LF

402

SSM6N15FEAPE

PERPH_DET_FILT

SOT563

MIKEY

1

C6860

0.1UF

20% 10V

2

CERM 402

2

MUTE CONTROL GPIO_0 AND GPIO_1 GPIO_0 AND GPIO_1 GPIO_3 GPIO_3 N/A

VREF/ENABLE MIC_BIAS (80%) MCP79 GPIO_38

PORT A DETECT (HEADPHONES)

1

R6806

39.2K

1% 1/16W MF-LF 402

2

AUD_PORTA_DET_L AUD_PORTB_DET_L

3

D

SOT563

5

SG

4

AUD_J1_SLEEVEDET_R

53 52

Q6802

SSM6N15FEAPE

AUD_J1_TIPDET_INV

MIKEY

SOT563

D

SG

MIKEY

1

2

6

1

R6864

220K

5% 1/16W MF-LF 402

Q6801

SSM6N15FEAPE

DET ASSIGNMENT 0X09 (A) 0X09 (A) AND UI ELEMENT N/A N/A 0X0D (B)

DET ASSIGNMENT N/A MCP79 GPIO_17 (PERIPH DETECT)

MCP79 GPIO_4 (LOAD DETECT)

PORT B DETECT(SPDIF DELEGATE)

Q6801

SSM6N15FEAPE

SOT563

2

MIKEY

1

R6865

100K

5% 1/16W MF-LF 402

2

AUD_PERPH_DET_R

3

D

5

SG

4

345678

2 1

D

PORT B LEFT(HEADSET MIC)

HP=80HZ, LP=8.82KHZ

MIKEY

NOSTUFF

5% 1/16W MF-LF 402

L6880

FERR-1000-OHM

0402

C6880

1

R6805

20.0K

1% 1/16W MF-LF 402

2

NC

6

D

SG

1

NC

38

19

=PP3V3_S0_AUDIO

53 52 48

8

PULLUPS ON MCP PAGE

=I2C_MIKEY_SCL

IN

=I2C_MIKEY_SDA

BI

AUD_I2C_INT_L

OUT

AUD_IPHS_SWITCH_EN

IN

1

R6885

10K

2

NOSTUFF

GND_AUDIO_CODEC

53 52 49 48

AUD_MIC_IN_L_P

48

MIKEY

R6861

0

1 2

5% 1/16W MF-LF

402

AUD_IP_PERIPHERAL_DET

OUT

AUD_MIC_IN_L_N

48

OUT

GND_AUDIO_CODEC

53 52 49 48

AUD_CODEC_MICBIAS

48

IN

17

OUT

53 52 49 48

48

GND_AUDIO_CODEC

AUD_MIC_IN_R_P

OUT

AUD_MIC_IN_R_N

OUT

GND_AUDIO_CODEC

PLACE_NEAR=J6701:3MM

XW6851

SM

1 2

MIKEY

CRITICAL

C6886

0.1UF

1 2

PLACE_NEAR=C6886:3MM

1 2

CRITICAL

C6851

0.1UF

1 2

10% 25V

R6853

X5R 402

1 2

10% 25V X5R 402

R6850

100

1% 1/16W MF-LF

402

C6850

0.1UF

1 2

10% 25V X5R 402

2.4K

1%

1/16W

MF

402-1

MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V

21

PP3V3_S0_HS_RX

CRITICAL

MIKEY

R6880

100K

1/16W MF-LF

CRITICAL

XW6880

1 2

1UF

10%

6.3V

CERM 402

5%

402

MIKEY

C6883

0.1UF

1 2

10% 25V X5R 402

SM

1

2

1

2

U6880

6

SCL

5

SDA

7

INT*

8

ENABLE

GND THM

4

HS_MIC_HI_RC

MIKEY

1

R6883

100K

5% 1/16W MF-LF 402

2

3

AVDD

CD3275

DRC

MICBIAS

9

MIKEY

DETECT

BYPASS

PORT B RIGHT(BUILT-IN MIC)

R6851

2.4K

MIC_BIAS_FILT

CRITICAL

1

C6852

2.2UF

20%

6.3V

2

TANT 402

1 2

1/16W 402-1

BI_MIC_HI_F

1

R6852

100K

5% 1/16W MF-LF 402

2

CRITICAL

C6853

0.001UF

50V 402

CERM

10%

BI_MIC_LO_F

HP=80HZ

DRC MIKEY

APN:353S2256

1

HS_MIC_BIAS

2

HS_SW_DET

10

11

MIKEY

C6881

0.01UF

16V

10%

CERM

402

MIKEY

R6884

1 2

MIKEY

1

C6884

0.0082UF

25V

10%

2

X7R 402

CRITICAL

1%

MF

CRITICAL

1

C6854

27PF

5%

2

CERM

HS_RX_BP

1

MIKEY

2

R6881

2.2K

5% 1/16W MF-LF

402

50V 402

1

1K

1% 1/16W MF-LF

402

2

FERR-1000-OHM

MIKEY

1

R6882

2.2K

5% 1/16W MF-LF 402

2

L6850

0402

L6851

0402

MIKEY

1

C6885

27PF

5%

2

CERM

CRITICAL

MIKEY CRITICAL

1

C6882

2.2UF

20%

6.3V

2

TANT 402

GND_AUDIO_CODEC

HS_MIC_P

50V 402

HS_MIC_N

21

BI_MIC_P

21

BI_MIC_N

BI_MIC_SHIELD

53 52 49 48

C

75 52

IN

75 52

IN

B

75 52

7

IN

75 52

7

IN

52

7

IN

A

SYNC_MASTER=AUDIO

PAGE TITLE

AUDIO: JACK TRANSLATORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

68 OF 109

SHEET

53 OF 76

SIZE

A

D

345678

2 1

MagSafe DC Power Jack

CRITICAL

J6900

78048-0573

M-RT-SM

1 2 3 4

D

5

518S0656

ADAPTER_SENSE

7

NO STUFF

1

R6900

100K

1% 1/16W MF-LF 402

2

R6928

0

1 2

5% 1/16W MF-LF

402

PP18V5_DCIN_FUSE

7

MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V

1

C6905

0.01UF

20% 50V

2

CERM 603

1-Wire OverVoltage Protection

ADAPTER_SENSE_R

C

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

R6905

1

PPDCIN_G3H_OR_PBUS

55

1 2

MF-LF

PPDCIN_G3H_OR_PBUS_R

MIN_LINE_WIDTH=0.3 mm

5%

MIN_NECK_WIDTH=0.3 mm

1/8W

VOLTAGE=18.5V

805

BYPASS=U6990.6:5:2 MM

C6990

2.2UF

X5R-CERM

10% 25V

805

3

6

BOOST

VIN

U6990

LT3470A

8

SHDN*

CRITICAL

7

NC

1

2

GND

SW

DFN

BIAS

FB

THRM

PAD

5

9

B

Vout = 1.25V * (1 + Ra / Rb)

CRITICAL

F6905

6AMP-24V

1206-1

1

C6970

1000PF

5% 25V

2

NP0-C0G 402

P3V42G3H_BOOST

DIDT=TRUE

4

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm

2

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE

1

P3V42G3H_FB

21

35

C6994

0.22uF

C6971

1000PF

5% 25V NP0-C0G 402

BI

20%

6.3V X5R 402

DIDT=TRUE

1

2

SYS_ONEWIRE

1

CRITICAL

L6995

2

CDPH4D19FHF-SM

C6995

22pF

5% 50V CERM 402

C6972

1000PF

5% 25V NP0-C0G 402

R6929

33UH

R6995

R6996

2.0K

1/16W MF-LF

348K

1/16W MF-LF

402

200K

1/16W MF-LF

402

5%

402

21

<Ra>

1%

<Rb>

1%

2

1

221

1

2

U6900

MAX9940

SC70-5

=PP3V42_G3H_REG

Vout = 3.425V

250MA MAX OUTPUT

(Switcher limit)

CRITICAL

C6999

22UF

20%

6.3V CERM 805

SMC_BC_ACOK_VCC

1

VCC

54

EXTINT

NC

GND

2

3

NC

8

4

Y

U6901

5

3

TC7SZ08AFEAPE

SOT665

2

A

1

B

=PP18V5_DCIN_CONN

=PP3V42_G3H_ONEWIRE

SMC_BC_ACOK

1

C6908

0.1UF

20%

PLACEMENT_NOTE=PLACE NEAR U6901

10V

2

CERM 402

8

36 35

9

HALL EFFECT ASSEMBLY

Assembly APN: 339S0114

- BOM: 639-0680

- PCBF: 820-2801

- MCO: 056-3515

- Conn APN:518S0788

OMIT

=PP3V42_G3H_HALL

43 36 35

OUT

8

SMC_LID

NOSTUFF

C6955

0.001UF

CERM

10% 50V

402

1

2

R6961

0

5% 1/16W MF-LF

402

12

HALLEFFECT-ASSY-K87

SMC_LID_R

7

PROTO 0: STUFFING K84 CONNECTOR ONTO MODIFIED K84 PADS PROTO 1: STUFFING K87 HALL EFFECT ASSEMBLY ONTO K87 PADS

PART NUMBER

QTY

1

DESCRIPTION

SUB ASSY - HALL EFFECT, K86 K87

REFERENCE DES

J6955

PN: 607-6831 for WCPM. PN: 339S0114 for schematic/board layout

J6955

F-ST-SM

1

339S0114

CRITICAL

CRITICAL607-6831

65 43 2

BOM OPTION

D

C

B

CRITICAL

J6950

BAT-K24

M-RT-TH

1

P1

2

P2

3

P3

4

P4

5

P5

6

P6

7

P7

8

P8

9

P9

SHLD_PIN SHLD_PIN

A

SHLD_PIN SHLD_PIN

10 11 12 13

BATTERY CONNECTOR

SYS_DETECT_L

7

55

PPVBAT_G3H_CONN

7

PLACE_NEAR=J6950.9:1 MM

1

R6950

10K

1/16W MF-LF

5%

402

1

C6950

0.1UF

10% 25V

2

X5R

2

402

PLACE_NEAR=J6950.9:1 MM

1

C6960

1UF

10% 25V

2

X5R 603-1

518-0359

DO NOT SYNC WITH K84. R6900,C6960,SIGNAL NAMES CHANGED. HALL EFFECT CONNECTOR CHANGED.

8 7 5 4 2 1

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

CRITICAL NOSTUFF

D6950

2

1

3

RCLAMP2402B

SC-75

38

SIZE

A

D

SYNC_MASTER=MASTER

PAGE TITLE

DC-In & Battery Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

69 OF 109

SHEET

54 OF 76

36

345678

This node is powered

Reverse-Current Protection

FROM ADAPTER

=PPDCIN_S5_CHGR

8

D

BAT30CWFILM

ACIN pin threshold is 3.2V, +/- 50mV

Divider sets ACIN threshold at 13.55V

Input impedance of ~40K meets sparkitecture requirements

=PP3V42_G3H_CHGR

62

8

1

C

R7010

30.1K

1% 1/16W MF-LF 402

2

R7012

1/16W MF-LF

1

1K

1%

402

2

C7002

37 36 35

1UF

10% 10V X5R 402

IN

1

2

GND_CHGR_AGND

SMC_RESET_L

55

R7000

0

1 2

5% 1/16W MF-LF

402

Float CELL for 1S

NO STUFF

1

R7013

1K

1% 1/16W MF-LF

402

1

R7011

9.31K

1% 1/16W MF-LF 402

2

B

1

R7015

2

56.2K

1% 1/16W MF-LF 402

2

CHGR_VCOMP_R

1

C7015

0.001UF

10% 50V

2

CERM

402

1

R7016

3.01K

1% 1/16W MF-LF

402

CHGR_VNEG_R

1

C7016

470PF

10% 50V

2

CERM 402

2

NO STUFF

38

62

IN BI IN

30mA max load

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm VOLTAGE=5.1V

1

R7002

100K

5% 1/16W MF-LF 402

2

CHGR_RST_L =SMBUS_CHGR_SCL =SMBUS_CHGR_SDA CHGR_VFRQ CHGR_CELL

CHGR_ACIN

CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P

74

CHGR_CSO_N

74

1

C7050

1UF

10% 16V

2

X5R 402

Q7080 Q7085

SO-8

CRITICAL

S

3 21

G

4

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

1

R7081

62K

5% 1/16W MF-LF 402

2

CHGR_DCIN_D_R

12

VHST

13

SMB_RST_N

11

SCL

10

SDA

4

VFRQ

6

CELL

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

R7001

4.7

1 2

5% 1/16W MF-LF

402

19

VDDP

VDD

CRITICAL

U7000

TQFN

ISL6259

20V/V

36V/V

(OD)

(AGND)

THRM_PAD

29

XW7000

1 2

PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm

1

R7080

100K

5% 1/16W MF-LF 402

2

R7005

20

1 2

5% 1/16W MF-LF

402

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

APN 353S2929

20

DCIN

SGATE AGATE

CSIP CSIN

BOOT UGATE PHASE

LGATE

BGATE

AMON

BMON

ACOK

PGND

22

SM

CRITICAL

D7005

SOT-323

1

2

SI7149DP

D

5

3

through body diodes: * DCIN through Q7080. * PBUS through Q7085, Charger TOP FETs and Q7055.

PPDCIN_G3H_OR_PBUS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

1

C7085

0.1UF

10% 25V

2

X5R 402

2

(CHGR_SGATE) (CHGR_AGATE)

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

R7085

470K

1%

1/16W MF-LF

402

54

(CHGR_DCIN)

1

C7020

0.047UF

10% 10V

2

CERM 402

1

C7001

1UF

10% 10V

2

X5R 402

2

CHGR_DCIN

26

CHGR_SGATE

1

CHGR_AGATE

28

CHGR_CSI_P

74

27

CHGR_CSI_N

74

25

CHGR_BOOT

24

CHGR_UGATE

23

CHGR_PHASE

21

CHGR_LGATE

16

CHGR_BGATE

9

CHGR_AMON

15

CHGR_BMON

14

=CHGR_ACOK

GATE_NODE=TRUE

OUT OUT OUT

DIDT=TRUE

40

9

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

Inrush Limiter

SO-8

SI7149DP

S

3 21

G

4

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

1

C7022

0.1UF

10% 25V

2

X5R 402

PLACE_NEAR=U7000.25:2mm

1

C7025

0.22UF

10% 10V

2

CERM 402

4

CRITICAL

D

5

R7021

1 2

1/16W MF-LF

R7022

1 2

1/16W MF-LF

1

C7021

0.1UF

10% 25V

2

X5R 402

5

1 2 3

10

5%

402

10

5%

402

4

CRITICAL

Q7035

RJK0305DPB

R7051 R7052

LFPAK-HF

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

CHGR_CSI_R_P

74

CHGR_CSI_R_N

74

5

D

G

S

321

1 2

2.2

1 2

0

1

R7086

332K

1% 1/16W MF-LF

402

2

CRITICAL

Q7030

RJK0332DPB-01

LFPAK-SM

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE

DIDT=TRUE

CHGR_PHASE_RC

1

2

CHGR_CSO_R_P

74 40

5%

CHGR_CSO_R_N

74 40

5%

1/16W

(PPVBAT_G3H_CHGR_R)

DIDT=TRUE

NO STUFF

C7039

470PF

10% 50V CERM 402

CRITICAL

R7020

0.02

0.5% 1W MF 0612-1

1243

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

Max Current = 8A

f = 400 kHz

NO STUFF

R7039

180

1/10W MF-LF

MF-LF1/16W

402

MF-LF

1

5%

603

2

CRITICAL

1

C7030

22UF

20% 25V

2

POLY-TANT CASE-D2-SM

CRITICAL

L7030

4.7UH-9.5A

IHLP4040DZ-SM

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

R7050

0.01

0612-1

0.5%

21

1W MF

21 43

CRITICAL

1

C7031

22UF

20% 25V

2

POLY-TANT CASE-D2-SM

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

1

C7035

1UF

10% 25V

2

X5R 603-1

CRITICAL

C7040

39UF-0.027OHM

B1A-SM

POLY

1

C7036

1UF

10% 25V

2

X5R 603-1

PLACE_NEAR=L7030.2:2MM

1

C7045

0.001UF

20% 16V

10% 50V

2

X7R 402

2 1

PLACE_NEAR=Q7030.5:1.5MM

1

C7037

0.001UF

10% 50V

2

X7R 402

CRITICAL

F7040

8AMP-24V

21

1206

CRITICAL

Q7055

SI7137DP

SO-8

S

3

21

G

4

D

5

=PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

TO SYSTEM

TO/FROM BATTERY

PPVBAT_G3H_CONN

D

C

8

B

54

7

(CHGR_BGATE)

1

C7042

0.068UF

10% 10V

2

CERM 402

C7011

0.01UF

CERM

1

C7000

1UF

10% 16V

402

10% 10V

2

X5R 402-1

C7005

0.22UF

1

20% 25V

2

X5R 603

55

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

C7026

0.001UF

CERM

1

10% 50V

2

402

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

A

K6 NOTES : L7030 CHANGED BACK TO K24 IND DUE TO LAYOUT K87 NOTES : R7050 APN 107S0075

8 7 5 4 2 1

SIZE

A

D

SYNC_MASTER=(K6_MLB)

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(11/06/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

70 OF 109

SHEET

55 OF 76

36

345678

2 1

5V_S3/3.3V_S5 POWER SUPPLY

D

C

MAX CURRENT = 13.3A PWM FREQ. = 300 KHZ

B

=PP5V_S3_REG

8

PLACE_NEAR=L7260.1:1.5 MM

1

C7293

0.001UF

20% 50V

2

CERM 402

ROUTING NOTE:

Place XW7203 by Pin1 OF L7260.

ROUTING NOTE:

Place XW7202 by C7292.

PLACE_NEAR=Q7260.5:1.5 MM

1

C7282

0.001UF

20% 50V

2

CERM 402

1

C7290

10UF

20%

6.3V

2

X5R 603

1

C7291

220UF

2

20%

6.3V ELEC D1A-SM

CRITICAL

=PPVIN_S3_5VS3

56

8

CRITICAL

1

C7280

39UF-0.027OHM

20% 16V

2

POLY B1A-SM

=PPVIN_S3_5VS3

56

8

CRITICAL

Q7260

SIS424DN

PWRPK-1212-8-SM

L7260

CRITICAL

4.7UH-13A-15MOHM

PCMB104E4R7-SM

SIS426DN

PWRPK-12128

VOUT = (2 * RA / RB) + 2

XW7203

SM

5V_S3_VFB_XW7203

12

XW7202

SM

12

1

C7281

1UF

10% 25V

2

X5R 603-1

CRITICAL

Q7261

5

D

G

S

3 2 1

21

5

D

G

S

13 2

4

C7260

0.1UF

10% 16V X5R 402

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

<RA>

MIN_LINE_WIDTH=0.6 MM

12

MIN_NECK_WIDTH=0.2 MM

<RB>

R7267

15.0K

1% 1/16W MF-LF 402

1 2 1 2

5VS3_3V3S5_VREF

1

C7271

0.22UF

10% 10V

2

CERM 402

5V_S3_VBST

DIDT=TRUE

5V_S3_DRVH

5V_S3_LL

5V_S3_DRVL

5V_S3_VO1

5V_S3_VFB

5V_S3_ENTRIP

R7271

1

86.6K

1%

1/16W MF-LF

402

2

R7268

10K

1% 1/16W MF-LF 402

=P5V3V3_REG_EN

62

1

C7272

1UF

10% 25V

2

X5R 603-1

14

22

21

20

19

24

SKIPSEL

4

TONSEL

VBST1

DRVH1

LL1

DRVL1

VO1

2

VFB1

1

ENTRIP1

<RD>

GND_5V3V3S5_SGND

16

VIN

CRITICAL

U7200

QFN

TPS51125

GND

THRM_PAD

15

5V3V3S5_REG3

3

VREF

ENTRIP2

25

VOUT = (2 * RC / RD) + 2

<RC>

R7269

10K

1% 1/16W MF-LF 402

56

100K

5% 1/16W MF-LF

402

PP5V_S5_LDO

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=5V

3V3S5_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

3V3S5_DRVH

3V3S5_LL

3V3S5DRVL

3V3S5VO2

3V3S5_VFB

3V3S5_ENTRIP

NC

5V3V3_REG_EN

1

2

R7220

402

1 2

1

C7273

10UF

20%

6.3V

2

X5R 603

VREG3

VREG5

VBST2

DRVH2

LL2

DRVL2

VO2

VFB2

VCLK

PGOOD

EN0

R7273

8

17

9

10

11

12

7

5

6

18

23

13

R7270

6.49K

1% 1/16W MF-LF 402

1 21 2

1

C7270

1UF

20% 10V

2

CERM 603

3V3S5_VBST_R

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

C7220

0.1UF

5%

1/16W MF-LF

0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

PLACE_NEAR=U7200.6:1 MM

R7272

1

75K

1% 1/16W MF-LF

402

2

DIDT=TRUE

3V3S5_VFB_R7270

10% 16V X5R 402

12

XW7204

SM

12

XW7205

SM

12

=PPVIN_S5_3V3S5

8

2

D1

G1

1

S1/D2

G2

6

S2

345

ROUTING NOTE:

Place XW7204 by Pin 2 of L7220.

ROUTING NOTE:

Place XW7205 by C7252.

1

C7241

1UF

10% 25V

2

X5R 603-1

Q7220

RJK0384DPA

WPAK

CRITICAL

7

CRITICAL

1

C7240

39UF-0.027OHM

2

CRITICAL

L7220

4.7UH-10A

PCMC063T-SM

PLACE_NEAR=Q7220.2:1.5 MM

20% 16V POLY B1A-SM

21

1

C7242

0.001UF

20% 50V

2

CERM 402

CRITICAL

1

C7251

150UF

20%

6.3V

2

POLY B1A-SM

PWM FREQ. = 375 KHZ MAX CURRENT = 9.1A

=PP3V3_S5_REG

1

C7250

10UF

20%

6.3V

2

X5R 603

PLACE_NEAR=L7220.2:1.5 MM

1

C7253

0.001UF

20% 50V

2

CERM 402

C

B

8

GND_5V3V3S5_SGND

56

VOLTAGE=0V MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

6

D

62

=P5VS3_EN_L

IN

2

SG

1

A

Q7221

SSM6N15FEAPE

SOT563

62

IN

=P3V3S5_EN_L

Q7221

3

D

5

SG

SSM6N15FEAPE

SOT563

4

PLACE_NEAR=U7200.25:1 MM

SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3.

NOTE: DONT SYNC THIS PAGE FROM T27

8 7 5 4 2 1

1 2

XW7201

SM

P5V3V3_PGOOD

ROUTING NOTE:

Place XW7201 between Pin 15 and Pin 25 of U7200.

36

62

SIZE

A

D

SYNC_MASTER=(K6_MLB)

PAGE TITLE

5V/3.3V SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(10/27/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

72 OF 109

SHEET

56 OF 76

1.5V/0.75 DDR3 POWER SUPPLY

345678

2 1

D

=PPVIN_S3_DDRREG

=PPVIN_S0_DDRREG_LDO

8

C7355

10UF

10% 10V X5R 805

R7305

1 2

1

C7305

2

C7350

0.033UF

4.7

5% 1/16W MF-LF

402

10% 16V X5R 402

1

1UF

10% 10V

2

X5R

402-1

NC NC

1

2

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V

PP5V_S3_DDRREG_V5FILT

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=5V

15

V5IN

COMP

10

S3

5

2

7

S5 PGOOD

VTTREF

VTT

VTTSNS

NC0 NC1

VTTGND

VTT Enable VDDQ/VTTREF Enable VDDQ PGOOD

THRM_PAD

1

25

11 13

24

12

PLACE_NEAR=U7300.3:1 mm

14

CRITICAL

U7300

TPS51116

QFN

SYM (2 OF 2)

GND

3

XW7300

SM

1 2

=PP5V_S3_DDRREG

8

C7300

4.7UF

C

=DDRVTT_EN

62

IN

=DDRREG_EN

62

IN

DDRREG_PGOOD

62

OUT

=PPVTT_S3_DDR_BUF

29

8

=PPVTT_S0_DDR_LDO

8

CRITICAL

C7360

22UF

20%

6.3V

X5R-CERM

603

XW7360

1 2

PLACE_NEAR=C7360.1:1 mm

CRITICAL

1

C7361

22UF

20%

6.3V

2

X5R-CERM 603

10mA max load Vout = VDDQSNS/2

Vout = VTTREF

SM

DDRREG_VTTSNS

B

8

1

20%

6.3V 2

X5R 603

23

VLDOINV5FILT

86

VDDQSNS

4

MODE

22

VBST

21

DRVH

20

LL

19

DRVL

16

CS

9

VDDQSET

CS_GND

PGND

17

18

PLACE_NEAR=U7300.25:1 mm

CRITICAL

1

C7330

39UF-0.027OHM

20% 16V

2

POLY B1A-SM

1

R7310

10K

1% 1/16W MF-LF

402

2

DDRREG_VDDQSNS

DDRREG_VBST

MIN_NECK_WIDTH=0.17 mm MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVH

GATE_NODE=TRUE DIDT=TRUE

DDRREG_LL

SWITCH_NODE=TRUE DIDT=TRUE

DDRREG_DRVL

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm DIDT=TRUE

DDRREG_CS

DDRREG_FB

29

DDRREG_CSGND

CRITICAL

1

C7331

39UF-0.027OHM

20% 16V

2

POLY B1A-SM

(DDRREG_DRVH)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

DIDT=TRUE

(DDRREG_LL)

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

(DDRREG_DRVL)

MIN_NECK_WIDTH=0.17 mm

(DDRREG_CSGND)

MIN_LINE_WIDTH=0.1 mm MIN_NECK_WIDTH=0.1 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

(DDRREG_FB)

PLACE_NEAR=Q7330.5:1.5 MM

1

C7332

1UF

10% 25V

2

X5R 603-1

4

C7325

0.1UF

1 2

10% 16V X5R 402

PLACE_NEAR=Q7335.1:1 mm

XW7335

SM

1 2

1

C7333

0.001UF

10% 50V

2

X7R 402

G

4

G

5

CRITICAL

D

Q7330

SIS424DN

PWRPK-1212-8-SM

S

CRITICAL

321

L7330

1.0UH-13A-5.6MOHM

PCMB065T-SM

5

D

Q7335

SIS426DN

PWRPK-12128

S

CRITICAL

1 32

21

CRITICAL

1

C7340

330UF

20%

2.5V

2

TANT CASE-B2-SM

CRITICAL

C7341

330UF

CASE-B2-SM

2.5V TANT

20%

Vout = 0.75V * (1 + Ra / Req) SEL_1V5=0: Req = Rb SEL_1V5=1: Req = Rb || Rc

PLACE_NEAR=L7330.2:1.5 MM

1

C7346

0.001UF

10% 50V

2

X7R 402

1

C7345

2

10UF

6.3V

20% X5R

603

=PPDDR_S3_REG VOUT = 1.501V 19A MAX OUTPUT

f = 400 kHz

PLACE_NEAR=L7330.2:1 MM

1

2

XW7345

SM

2

1

R7320

15.0K

1% 1/16W MF-LF 402

2

<Ra>

OUT

1

C7320

0.001UF

10% 50V

2

X7R 402

<Rb>

63

8

1

R7321

15.0K

1% 1/16W MF-LF 402

2

D

C

B

A

NOTE: DONT SYNC THIS PAGE FROM T27. C7330 AND C7331 IS CHANGED TO OSCON CAPS NOTE: DONT SYNC THIS PAGE FROM K6 REMOVED R7380

8 7 5 4 2 1

36

SYNC_MASTER=(K6_MLB)

PAGE TITLE

SYNC_DATE=(11/06/2009)

1.5V/0.75V DDR3 SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

73 OF 109

SHEET

57 OF 76

SIZE

A

D

C

B

IMVP6:1PHASE BOM

PART NUMBER

A

=PP5V_S0_CPU_IMVP

8

58

=PPVIN_S5_CPU_IMVP

8

58

PM_DPRSLPVR

14 69

IN

=PP3V3_S0_IMVP

8

GND_IMVP6_SGND

58

IMVP6:2PHASE

1

2

114S0307 114S0336 132S0080 114S0236 114S0160 132S4720 114S0410 132S0045 131S1027

8 7 5 4 2 1

1 2

C7405

0.015uF

10% 16V X7R 402

1

R7409

1K

1% 1/16W MF-LF 402

2 1

IMVP6:2PHASE

470PF

10% 50V CERM 402

2

C7414

IMVP6_COMP_RC

IMVP6:2PHASE

1

R7414

97.6K

1% 1/16W MF-LF 402

2

QTY

RES,MTL FILM,1/16W,8.25K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W, 16.9K, 1,0402,SM,LF

1 1

RES,MTL FILM,1/16W,1.58K,1,0402,SMD,LF

1

RES,MTL FILM,1/16W,255 OHM,1,0402,SMD,LF

1 1

RES,MTL FILM,1/16W,97.6K,1,0402,SMD,LF

1 1 1

1 2

R7412

10

5% 1/16W MF-LF 402

1 2

R7421

10

5% 1/16W MF-LF 402

R7408

147K

1% 1/16W MF-LF 402

1 2

IMVP6:2PHASE

C7406

0.001UF

10% 50V CERM 402

1

2

FROM SMC

IMVP6_VDIFF_RC

IMVP6:2PHASE

R7411

255

1% 1/16W MF-LF 402

2

(IMVP6_FB)

IMVP6:2PHASE

C7413

1

220PF

5% 25V CERM

2

402

(IMVP6_COMP)

PWM Freq.

Max Current

Load Line

DESCRIPTION

CAP,CER,.22UF,20,6.3V,X5R,0402

CAP CER 470PF,+/-10%,50V,0402,SMD

CAP,CER,1000PF,50V,10%,X7R,0402,SMD

CAP,CER,100PF,5%,50V,CC0402

C7426

1UF

10%

6.3V CERM 402

1 2

R7420

10

5% 1/16W MF-LF 402

1

R7445

499

1% 1/16W

MF-LF 402

2

R7413

1 2

1K

1% 1/16W MF-LF 402

1

2

C7430

0.1uF

10% 16V X5R 402

CPU_DPRSTP_L

10 14 69

IN

IMVP_DPRSLPVR

69

CPU_PSI_L

10

IN

IMVP6_IMON

40

OUT

IMVP_VR_ON

35

IN

VR_PWRGOOD_DELAY

25

OUT

IMVP6:2PHASE

2PHASE

300 kHz

44 A

-2.107 mV/A

REFERENCE DES

PP5V_S0_IMVP6_VDD

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM

C7496

0.01UF

10% 16V CERM 402

11 69

1

2

MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.6V

VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_IMVP6_3V3

1

2

CPU_VID<6> CPU_VID<5> CPU_VID<4> CPU_VID<3> CPU_VID<2> CPU_VID<1> CPU_VID<0>

IMVP6_VR_TT

9

IMVP6_NTC

9

58

(IMVP6_VW)

C7407

0.001UF

10% 50V CERM 402

1PHASE

300 kHz

17.6 A

-4 mV/A

R7417 R7416 C7428 R7409 R7411 C7406 R7414 C7414 C7413

1

R7447

2.0K

5% 1/16W

MF-LF 402

2

(NC)

IMVP6_SOFT IMVP6_RBIAS

IMVP6_VDIFF

IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW

1

R7410

6.81K

1% 1/16W MF-LF 402

2

CRITICAL

IMVP6 CPU VCORE REGULATOR

=PPVIN_S5_CPU_IMVP

8

58

Q7400

IRF6710

4

3

CRITICAL

D

S

3 4

Q7402

IRF6710

S1

D

G

S

D

S

3 4

IMVP6:1PHASE

S1

D

G

S

71 2 6

CRITICAL

Q7401

IRF6795

DIRECTFET-MX

IMVP6:2PHASE

71 2 6

CRITICAL

Q7403

IRF6795

DIRECTFET-MX

43

VID6

42

VID5

41

VID4

40

VID3

39

VID2

38

VID1

37

VID0

46

DPRSTP*

45

DPRSLPVR

2

PSI*

3

IMON

48

3V3

47

CLK_EN*

44

VR_ON

1

PGOOD

5

VR_TT*

6

NTC

7

SOFT

4

RBIAS

13

VDIFF

12

FB2

11

FB

10

COMP

9

VW

25

NC

C7421

0.22uF

CERM-X5R

BOM OPTION

IMVP6:1PHASE IMVP6:1PHASE IMVP6:1PHASE IMVP6:1PHASE IMVP6:1PHASE IMVP6:1PHASE IMVP6:1PHASE IMVP6:1PHASE IMVP6:1PHASE

20 22 31

VIN VDD

CRITICAL

U7400

QFN

ISL9504BCRZ

GND

2

10%

6.3V 1

402

PVCC

BOOT1 BOOT2

UGATE1

PHASE1

LGATE1

PGND1

ISEN1

UGATE2

PHASE2

LGATE2

PGND2

ISEN2

VSUM

OCSET

VO

DROOP

DFB

VSEN

RTN

TPAD

4921

C7433

0.001UF

1

2

36 26

35

34

32

33

24

27

28

30

29

23

19 8 18 16

17

14 15

CERM

20% 50V

402

C7435

10UF

20%

6.3V X5R 603

58

DPRSLPVR

DIDT=TRUE

IMVP6_BOOT1 IMVP6_BOOT2

DIDT=TRUE

IMVP6_UGATE1 IMVP6_PHASE1 IMVP6_LGATE1

(GND)

IMVP6_ISEN1

IMVP6_UGATE2 IMVP6_PHASE2 IMVP6_LGATE2

(GND)

IMVP6_ISEN2

IMVP6_VSUM IMVP6_OCSET IMVP6_VO IMVP6_DROOP

IMVP6_DFB

C7431

0.001UF

1 2

20% 50V

CERM

402

2

1

IMVP6_VDIFF

58

IMVP6_FB2

58

IMVP6_FB

58

IMVP6_COMP

58

IMVP6_VW

58

IMVP6_VSEN_P

58 69

IMVP6_VSEN_N

58 69

132S0099

0 1 0 1 1

1 2

R7424

0

5% 1/16W MF-LF 402

1 2

R7425

0

5% 1/16W MF-LF 402

1

R7418

1K

1% 1/16W MF-LF 402

2

(IMVP6_VO)

IMVP6:2PHASE

1

C7434

0.047UF

10% 16V

2

X7R 402

IMVP6_VSEN_P

58 69

IMVP6_VSEN_N

58 69

2

C7432

0.001UF

20% 50V

1

CERM 402

GND_IMVP6_SGND

58

VOLTAGE=0V

1

DPRSTP*

1

0

IMVP6_BOOT1_RC

IMVP6_BOOT2_RC

DIDT=TRUE

C7427

1

0.1UF

10% 16V

2

X5R 402

IMVP6:2PHASE

1 2

R7417

5.90K

1% 1/16W MF-LF

402

1

C7428

2

CAP,X5R,0.1UF,10%,16V,0402

PSI*

OPERATION MODE

1 0 10 0

DIDT=TRUE

IMVP6:2PHASE

0.47UF

10%

6.3V CERM-X5R 402

2-PHASE CCM

1-PHASE CCM

1-PHASE DCM

C7415

1

0.1UF

10% 16V

2

X5R 402

C7429

1

180pF

5% 50V

2

CERM 402

1

R7415

10.5K

1% 1/16W MF-LF 402

2

R7422 R7423

XW7400

0.25 MM 0.20 MM

0.25 MM 0.25 MM

1 2

0

1 2

0

OMIT

PLACEMENT_NOTE=PLACE CLOSE TO PIN 21 OF U7400

SM

12

NO STUFF

C7416

0.001UF

CERM

10%

402

50V

IMVP6:2PHASE

1

R7416

13.7K

1% 1/16W MF-LF 402

2

1

R7430

3.92K

1% 1/16W MF-LF 402

2

IMVP6_VO_R

1

CRITICAL

R7431

10KOHM-5%

0603-LF

2

ERT-J1VR103J

MF-LF

5%

402

1/16W

MF-LF

5%

402

1/16W

MIN_NECK_WIDTHMIN_LINE_WIDTH

0.20 MM0.25 MM

DIDT=TRUE

1

2

DIDT=TRUE

G

5

IMVP6:2PHASE

CRITICAL

4

3

DIDT=TRUE

G

5

=PP5V_S0_CPU_IMVP

8

58

R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED

CPU_VCCSENSE_P

CPU_VCCSENSE_N

NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.

C7434

11 69

IMVP6_PHASE1

58

IMVP6_BOOT1

58

IMVP6_UGATE1

58

IMVP6_LGATE1

58

IMVP6_ISEN1

58

IMVP6_PHASE2

58

IMVP6_BOOT2

58

IMVP6_UGATE2

58

IMVP6_LGATE2

58

IMVP6_ISEN2

58

345678

PLACEMENT_NOTE=PLACE C7419 ACROSS PINS 1/2/5/6 OF Q7400 AND PINS 3/4 OF Q7401

CRITICAL

1

C7409

1 2 5 6

2

33UF

20% 16V POLY-TANT CASED2E-SM

CRITICAL

1

C7417

39UF-0.027OHM

20% 16V

2

POLY B1A-SM

(IMVP6_PHASE1)

PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7400

OMIT

XW7401

SM

2

1

IMVP6:2PHASE

IMVP6_PHASE1_XW

(IMVP6_ISEN1)

PLACEMENT_NOTE=PLACE C7422 ACROSS PINS 1/2/5/6 OF Q7402 AND PINS 3/4 OF Q7403

=PPVIN_S5_CPU_IMVP

8

58

IMVP6:2PHASE

CRITICAL

1

C7401

39UF-0.027OHM

2

20% 16V POLY B1A-SM

1 2 5 6

IMVP6:2PHASE

CRITICAL

1

C7408

33UF

20% 16V

2

POLY-TANT CASED2E-SM

IMVP6:2PHASE

1

C7411

1UF

10% 25V

2

X5R 603-1

(IMVP6_PHASE2)

OMIT

XW7403

SM

IMVP6:1PHASE

1

R7426

0

5% 1/16W MF-LF 402

2

(IMVP6_ISEN2)

(IMVP6_VSUM) (IMVP6_VO)

IMVP6_OCSET

58

IMVP6_VSUM

58

GND_IMVP6_SGND

58

IMVP6_VO

58

IMVP6_DROOP

58

IMVP6_DFB

58

IMVP6_SOFT

58

IMVP6_RBIAS

0.25 MM

0.25 MM0.25 MM

0.25 MM

0.25 MM0.25 MM

58

MIN_LINE_WIDTH

1.5 MM

0.25 MM 0.25 MM

1.5 MM

MIN_LINE_WIDTH

1.5 MM

MIN_NECK_WIDTH

36

2 1

C7418

1

1UF

10% 25V X5R

2

603-1

0.36UH-20%-40A-0.00075OHM

PIMA104E-R36MN0R755 DCR=0.75MOHM

PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7400

1 2

R7400

10K

1% 1/16W MF-LF 402

IMVP6:2PHASE

1

C7422

0.001UF

20% 50V

2

CERM 402

IMVP6:2PHASE

0.36UH-20%-40A-0.00075OHM CRITICAL

PIMA104E-R36MN0R755

2

DCR=0.75MOHM

1

IMVP6:2PHASE

1 2

R7405

10K

1% 1/16W MF-LF 402

PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7401

IMVP6:2PHASE

IMVP6_PHASE2_XW

1

R7443

3.65K

1% 1/16W MF-LF 402

2

SYNC_MASTER=(K84_MLB)

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

C7419

1

0.001UF

20% 50V

CERM

2

402

CRITICAL

L7400

PIMA104E-SM

IMVP6:2PHASE

1 2

C7403

0.22uF

10%

6.3V CERM-X5R 402

3.65K

1/16W MF-LF

402

1

1%

2

R7401

L7401

PLACEMENT_NOTE=PLACE C7423 CLOSE TO PIN 2 OF L7401

21

PIMA104E-SM

PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7401

IMVP6:2PHASE

1 2

C7404

0.22uF

10%

6.3V CERM-X5R 402

MIN_LINE_WIDTH

IMVP6 CPU VCore Regulator

Apple Inc.

R

21

=PPVCORE_S0_CPU_REG

OMIT

XW7402

SM

2

1

IMVP6_VO1

1 2

R7404

1

5% 1/16W MF-LF 402

OMIT

XW7404

SM

IMVP6:2PHASE

1 2

R7407

1

5% 1/16W MF-LF 402

0.25 MM 0.20 MM

0.50 MM 0.20 MM

0.25 MM 0.20 MM

2

1

IMVP6_VO2

MIN_NECK_WIDTH

0.20 MM0.25 MM

SYNC_DATE=(11/18/2009)

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

C7420

1

0.001UF

20% 50V

CERM

2

402

C7423

1

0.001UF

20% 50V

CERM

2

402

051-8561

C.0.0

74 OF 109

58 OF 76

D

8

C

B

A

SIZE

D

345678

=PPVIN_S0_MCPCORE

8

=PP5V_S0_MCPREG

D

PP5V_S0_MCPREG_VDD

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

1

R7561

1/16W MF-LF

402

NOSTUFF

20

1% 1/16W MF-LF

402

20

1% 1/16W MF-LF

402

0

1 2

5%

1 2 1 2 1 2 1 2

5%01/16W 5% 402 5%

0 0

1

2

R7563

100

1% 1/16W MF-LF 402

(MCPCORES0_VSEN)

1

C7570

0.001UF

10% 50V

2

X7R 402

(MCPCORES0_RTN)

1

R7571

100

1% 1/16W MF-LF 402

2

1

C7579

0.001UF

10% 50V

2

X7R 402

C7581

100PF

1 2

5%

50V

CERM

402

C7582

4700PF

1 2

10% 100V CERM

402

MF-LF

MF-LF MF-LF MF-LF MF-LF

R7572

402

402 4025%01/16W

147K

1/16W MF-LF

402

1%

1/16W

1/16W 1/16W

(MCPCORES0_VW)

1

R7576

6.98K

1% 1/16W MF-LF 402

2

(MCPCORES0_COMP)

(MCPCORES0_FB)

(MCPCORES0_VDIFF)

1

2

40

OUT

62

OUT

19

IN

19

IN

19

IN

19

IN

62

IN

MCPCORES0_IMON MCPCORES0_PGOOD

MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_VID<3>

=MCPCORES0_EN

=PPMCPCORE_S0_REG

59

8

R7593

R7590 R7591 R7592 R7594

C

R7566

75 22

B

MCPCORES0_VSEN_P

IN

MCPCORES0_VSEN_N

IN

R7577

150K

1 2

1% 1/16W MF-LF

402

R7578

200

1 2

1% 1/16W MF-LF

402

MCPCORES0_COMP_C

MCPCORES0_VDIF_C

1 2

R7568

1 2

C7580

330PF

1 2

5% 50V COG 402

R7579

3.01K

1 2

1% 1/16W MF-LF

402

1

1K

5%

C7550

1UF

10% 16V

2

X5R 402

2

MCPCORES0_RBIAS MCPCORES0_SOFT

MCPCORES0_IMON_R

MCP_VID0_REG MCP_VID1_REG MCP_VID2_REG MCP_VID3_REG

NC

MCPCORES0_FDE

MCPCORES0_VSEN MCPCORES0_RTN

MCPCORES0_VW

MCPCORES0_COMP

MCPCORES0_FB MCPCORES0_VDIFF

1

C7577

1

C7576

0.1UF

10% 16V

2

X7R-CERM 402

GND_MCPCORES0_AGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

0.001UF

10% 50V

2

X7R 402

1

C7578

0.001UF

10% 50V

2

X7R 402

8

R7560

2.2

1 2

5% 1/10W MF-LF

603

16

22

VDD

PVCC

U7500

QFN

ISL9563B

THRM_PAD

15

XW7561

SM

1 2

UGATE

BOOT

LGATE

OCSET

ICOMP

33

VIN

ISP ISN

VO

RBIAS

2

SOFT

28

IMON

31 19

PGOOD PHASE

24

VID0

25

VID1

26

VID2

CRITICAL

27

VID3

23

NC

29

VR_ON

30

AF_EN

32

FDE

8

VSEN

9

RTN

4

VW

5

COMP

6

FB

7

VDIFF

PGND

VSS

20

PLACE_NEAR=U7500.33:1mm

VID<3:0> VOLTAGE 1100 0.9750V

1101 0.9625V 1110 0.9500V 1111 0.9375V 0000 0.9250V 0001 0.9125V 0010 0.9000V

1

C7562

1UF

10% 16V

2

X5R 402

141

18

MCPCORES0_UGATE

17

MCPCORES0_BOOT

DIDT=TRUE

MCPCORES0_PHASE

SWITCH_NODE=TRUE DIDT=TRUE

21

MCPCORES0_LGATE

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE

12

MCPCORES0_VO

40

3

MCPCORES0_OCSET

13

MCPCORES0_ISP

11

MCPCORES0_ISN

10

MCPCORES0_ICOMP

MCPCORES0_BOOT_R

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

2

R7565

0

5% 1/10W MF-LF 603

1

(MCPCORES0_UGATE)

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

(MCPCORES0_PHASE)

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

C7564

0.22UF

CERM-X7R

4

R7569

9.76K

1 2

1% 1/16W MF-LF

402

(MCPCORES0_ISN)

(MCPCORES0_ICOMP)

CRITICAL

C7540

1

5%

10V

2

603

4

5

CRITICAL

D

S

Q7565

RJK0208DPA

WPAK

321

G

POLY-TANT

CASE-D2E-SM

5

CRITICAL

D

G

S

321

CRITICAL

1

68UF

Q7560

RJK0365DPA-02

WPAK

C7541

20% 16V

2

CASE-D2E-SM

CRITICAL

L7560

0.56UH-31A

FDU1040D-SM

POLY-TANT

CRITICAL

1

68UF

C7560

20% 16V

2

POLY-TANT

CASE-D2E-SM

21

PPMCPCORE_S0_R

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V

68UF

1

C7561

1UF

2

10% 25V

2

X5R 603-1

CRITICAL

R7525

0.001

20% 16V

(MCPCORES0_VO)

1

R7573

10K

1% 1/16W MF-LF 402

2

1

R7575

22.1K

1% 1/16W MF-LF 402

2

C7573

47PF

CERM

C7575

5%

50V 402

47PF

50V

CERM

402

1

2

R7500

100

1 2

1/16W MF-LF

1

5%

2

402

40

1%

MCPCORES0_ISP_R

2 1

1

C7563

0.001UF

10% 50V

2

X7R 402

1% 1W MF

0612

21 43

1

C7566

10UF

20% 4V

2

X5R 603

C7567

10UF

20%

4V X5R 603

1

2

CRITICAL

1

C7565

270UF

20% 2V

2

TANT CASE-B4-SM

CRITICAL

C7568

270UF

CASE-B4-SM

TANT

20%

=PPMCPCORE_S0_REG

MAX CURRENT: 30.4A (Q7560 Limit) f = 300 kHz

PLACE_NEAR=L7560.2:1.5MM PLACE_NEAR=R7525.1:1.5MM

1

C7569

0.001UF

10%

2V

50V

2

X7R 402

D

59

8

C

B

0011 0.8875V 0100 0.8750V 0101 0.8625V 0110 0.8500V 0111 0.8375V 1000 0.8250V

A

K6 NOTES : XOR AND INVERTER IS REMOVED, CANNOT SYNC THIS PAGE FROM T27

8 7 5 4 2 1

1001 0.8125V 1010 0.8000V 1011 0.7875V

SIZE

A

D

SYNC_MASTER=(K6_MLB)

PAGE TITLE

MCP VCore Regulator

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(10/27/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

75 OF 109

SHEET

59 OF 76

36

345678

2 1

D

CPUVTT POWER SUPPLY

=PPVIN_S0_CPUVTTS0

8

CRITICAL

39UF-0.027OHM

C7630

POLY

B1A-SM

20% 16V

1

2

C

=PP5V_S0_CPUVTTS0

8

R7601

301

1 2

B

PP5V_S0_CPUVTTS0_V5FILT

MIN_LINE_WIDTH=0.6 mm

1%

MIN_NECK_WIDTH=0.2 mm

1/16W

VOLTAGE=5V

MF-LF

402

62

IN

62

OUT

=CPUVTTS0_EN CPUVTTS0_PGOOD

(=PPCPUVTT_S0_REG)

CPUVTTS0_VFB CPUVTTS0_TRIP

1

R7604

6.04K

1% 1/16W MF-LF 402

2

CPUVTTS0_VOUT

C7601

1UF

402-1

10% 10V X5R

1

2

TPS51117RGY_QFN14

1

EN_PSV

6

PGOOD

3

VOUT

5

VFB

11

TRIP

4

V5FILT

GND

7

V5DRV

CRITICAL

U7600

SYM 2

QFN

THRM_PAD

15

OMIT

XW7600

SM

1 2

PLACE_NEAR=U7600.7:1MM PLACE_NEAR=U7600.15:1MM

10

PGND

VBST

DRVH

DRVL

8

TON

2

14

13

12

LL

9

1

C7604

4.7UF

10%

6.3V

2

X5R-CERM 603

CPUVTTS0_TON CPUVTTS0_VBST CPUVTTS0_DRVH

GATE_NODE=TRUE

CPUVTTS0_LL

SWITCH_NODE=TRUE

CPUVTTS0_DRVL

GATE_NODE=TRUE

(GND)

GND_CPUVTTS0_SGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

(CPUVTTS0_VFB) (=PPCPUVTT_S0_REG)

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

PLACE_NEAR=Q7620.5:1.5 MM PLACE_NEAR=Q7620.2:1 MM

C7695

1UF

10% 25V X5R 603-1

R7603

C7603

0.1UF

603-1

DIDT=TRUE

1

2

10% 50V X7R

C7696

0.001UF

20% 50V

CERM

402

200K

1% 1/16W MF-LF

402

1

2

5

D

CRITICAL

S

D

S

321

Q7620

CSD58858Q3

3.3X3.3-QFN

321

CRITICAL

Q7621

CSD58858Q3

3.3X3.3-QFN

CPUVTTS0_VSNS

1

R7670

8.06K

1% 1/16W MF-LF 402

2

<Ra>

1

R7671

20.0K

1% 1/16W MF-LF 402

2

<Rb>

L7620

2.2UH-8.0A

PCMB065T-SM

PLACE_NEAR=L7620.2:2 MM

XW7665

OMIT

NO STUFF

C7670

100PF

Vout = 0.75V * (1 + Ra / Rb)

50V

CERM

402

5%

CRITICAL

21

2

SM

1

2

1

C7665

10UF

20%

6.3V

2

X5R 603

CRITICAL

C7660

330UF

20%

2.5V TANT

CASE-B2-SM

=PPCPUVTT_S0_REG

PLACE_NEAR=L7620.2:1.5 MM

C7661

1

0.001UF

20% 50V

CERM

2

1

2

SM

402

OMIT

2

XW7601

1

PLACE_NEAR=C7660.1:2 MM

ROUTING NOTE:

Place XW7601 by C7660.

VOUT = 1.052V

7.2A MAX OUTPUT F = 320 KHZ

8

4

G

1

2

5

4

G

C

B

A

8 7 5 4 2 1

36

SYNC_MASTER=(K84_MLB)

PAGE TITLE

CPU VTT(1.05V) SUPPLY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(02/04/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

76 OF 109

SHEET

60 OF 76

SIZE

A

D

345678

2 1

=PP3V3_S0_MCP_PLL_VLDO

1.05V S0 MCP PLL LDO

8

D

=PP1V5_S0_MCP_PLL_VLDO

8

1.05V ENET Switcher

=PP3V3_ENET_FET

63 62

9 8

10uF

1

2

6.3V

EXT1V05

1

C7713

20%

2

X5R 603

0.1uF

CERM

1

20% 10V

2

402

3

VIN

EXT1V05

U7710

NCP1529

UQFN

6

1

EN

FB

CRITICAL

GND

247

THRM

PAD

5

SW

P1V05S0_SW

SWITCH_NODE=TRUE DIDT=TRUE

P1V05S0_FB

EXT1V05

CRITICAL

L7710

2.2UH-3.25A

IHLP1616BZ-SM

C7711

21

EXT1V05

18PF

5%

50V

CERM

402

=PP1V05_S0_REG

EXT1V05

1

R7711

1

100K

1% 1/16W

2

MF-LF 402

2

<Ra>

EXT1V05

1

R7712

133K

1% 1/16W MF-LF 402

2

<Rb>

1

2

VOUT= 1.05V @ 800MA

FREQ = 1.6MHZ

EXT1V05

C7715

10uF

20%

6.3V X5R 603

8

EXT1V05

C7710

=P1V05ENET_EN

62

IN

EXT1V05

C7714

10PF

5%

C

CERM

50V 402

MCPPLL_R:LDO

R7750

MCPPLL_LDO

C7741

1/16W MF-LF

1UF

6.3V CERM

1

0

5%

402

2

1

10%

2

402

MCPPLL_R:LDO

MCPPLL_LDO

C7740

R7743

100

1/16W MF-LF

1UF

10%

6.3V CERM

402

1

5%

402

2

PP3V3_S0_MCP_PLL_LDO_BIAS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP1V5_S0_MCPPLLLDO

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V

MCPPLLLDO_SS

MCPPLL_LDO

1

C7743

0.0022UF

10% 50V

2

CERM 402

CRITICAL

4

MCPPLL_LDO

BIAS

1

IN0

2

IN1

5 8

EN FB

TPS74701

7

SS

GND

U7740

SON

THRML_PAD

6

11

OUT0 OUT1

PG

9 10

3

BOMOPTIONS:

MCPPLL_R:LDO - 1.05V S0 USED FOR MCP PLL LDO POWER. MCPPLL_LDO - STUFFS U7740 AND RELATED CIRCUITRY.

TO USE U7740, MCPPLL_R:LDO AND MCPPLL_LDO MUST BE ACTIVE. TO USE 1.05V S0, MCPPLL_R:REG MUST BE ACTIVE, MCPPLL_LDO CAN BE ACTIVE, MCPPLL_R:LDO MUST BE INACTIVE.

=PP1V05_S0_MCP_PLL_UF_R

8

PP1V05_S0_MCP_PLL_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MCPPLLLDO_FB

MCPPLL_LDO

R7746

MCPPLL_LDO

R7747

Vout = 0.8V * (1 + Ra / Rb)

MCPPLL_LDO

R7748

0

MCPPLLLDO_PGOOD_R

1 2

5% 1/16W MF-LF

402

MCPPLL_R:REG

1

1.37K

1% 1/16W MF-LF

402

221

<Ra>

1

4.42K

1% 1/16W MF-LF

402

2

<Rb>

MCPPLLLDO_PGOOD

R7745

0

1 2

5% 1/16W MF-LF

402

MCPPLL_R:LDO

R7744

0

1 2

5% 1/16W MF-LF

402

MCPPLL_LDO

C7742

4.7UF

20% 4V X5R 402

=PP1V05_S0_MCP_PLL_OR

Vout = 1.05V Max Current = 0.5A

62

OUT

D

8

C

VOUT = 0.6V * (1 + RA / RB)

B

1.8V S0 Switcher

=PP1V8_S0_REG

=PP3V3_S0_P1V8S0

8

=P1V8S0_EN

62

IN

C7760

10uF

6.3V

1

20%

2

X5R 603

CRITICAL

1

VI

U7760

TPS62202

SOT23-5

4

FB

3 5

EN

GND

SW

2

10UH-0.55A-330MOHM

P1V8S0_SW

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

CRITICAL

L7760

PCAA031B-SM

Vout = 1.8V

1

MAX CURRENT = 0.3A F = 1MHZ

1

C7762

10uF

20%

2

6.3V

2

X5R 603

A

K6 NOTES : C7710 AND C7750 HAS BYPASS PROPERTY, SHOULD BE ADDED INCASE THIS PAGE IS SYNC’ED FROM T27

8 7 5 4 2 1

MCP 0.9V S5 (AUXC) Switcher

SIZE

B

A

D

=PP3V3_S5_P0V9S5

8

VIN

U7750

ISL8009B

CRITICAL

62

IN

62

OUT

=P0V9S5_EN P0V9S5_PGOOD

2

EN

3

POR

4

SKIP

GND

7 9

1

2

1

DFN

VFB

RSI

THRM_PAD

BYPASS=U7750.1:9:2 MM

CRITICAL

C7750

22UF

6.3V 20%

CERM

805

P0V9S5_SW

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

8

LX

6

P0V9S5_FB

5

CRITICAL

L7750

2.2UH-3.25A

IHLP1616BZ-SM

C7751

47PF

CERM

21

1

R7751

1

25.5K

1%

5%

50V 402

1/16W

2

MF-LF 402

2

<Ra>

1

R7752

200K

1% 1/16W MF-LF 402

2

<Rb>

=PP0V9_S5_REG

Vout = 0.902V MAX CURRENT = 1.5A f = 1.6MHZ

CRITICAL

1

C7755

22UF

20%

6.3V

2

CERM 805

8

Vout = 0.8V * (1 + Ra / Rb)

SYNC_MASTER=MASTER

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

77 OF 109

SHEET

61 OF 76

36

345678

2 1

S5 Rail Enables & PGOOD

=PP3V42_G3H_PWRCTL

62

8

0.1uF

CERM

1

20% 10V

2

402

C7840

=P5V3V3_REG_EN

56

D

OUT

35

7

IN

75

SMC_PM_G2_EN

MAKE_BASE=TRUE

PP3V3_S5

8 7

Threshold: ??

S5PGOOD_DLY

1

C7841

220PF

5% 25V

2

CERM 402

P0V9S5_PGOOD

61 35

IN

S3 Rail Enables

=PP3V42_G3H_PWRCTL

62

8

2

R7813

68K

SOT563

1/16W MF-LF

402

5% 1/16W MF-LF

402

1

3

D

5

SG

4

1

5%

2

C

Q7891

SSM6N15FEAPE

7

IN

PM_SLP_S4_L

R7810

100K

62 36 35 19

B

S0 Rail Enables

R7859

100

66

7

IN

PM_SLP_S3_L

62 35 19

A

MCP_MEM_VDD_EN

21 19

IN

DO NOT SYNC T27, ENET RAILS CHANGED

MAKE_BASE=TRUE

8 7 5 4 2 1

5% 1/16W MF-LF

402

R7879

100K

1/16W MF-LF

12

2

R7881

33K

5% 1/16W

1

MF-LF 402

1

5%

402

2

1

C7881

0.47UF

10%

6.3V

2

CERM-X5R 402

CRITICAL

1

VDD

U7840

2

IN_A

(IPD)

6

IN_B

2:1

1.3V

7

DLY_1C

R7812

1 2

5% 1/16W MF-LF

402

R7811

5.1K

1 2

5% 1/16W MF-LF

402

SLG4AP012

TDFN

+

-

DLY

GND

5

MAKE_BASE=TRUE

1

2

0

MAKE_BASE=TRUE

1

2

MAKE_BASE=TRUE

1

2

R7880

22K

5% 1/16W MF-LF 402

1

C7880

0.47UF

10%

6.3V

2

CERM-X5R 402

THRM

PAD

P5VS3_EN_L

NO STUFF

C7813

0.068UF

10% 10V CERM 402

P3V3S3_EN

NO STUFF

C7812

0.47UF

10%

6.3V CERM-X5R 402

DDRREG_EN

C7810

0.47UF

10%

6.3V CERM-X5R 402

Internal pull-ups 100K +/- 20%

4

OUT_A*

(OD,IPU)

OUT_A

(OD,IPU)

OUT_B

(OD,IPU)

9

P3V3S5_EN_L

MAKE_BASE=TRUE

3

P0V9S5_EN

MAKE_BASE=TRUE

8

RSMRST_PWRGD

MAKE_BASE=TRUE

=P5VS3_EN_L

=P3V3S3_EN

=DDRREG_EN =USB_PWR_EN

2

R7882

15K

5% 1/16W MF-LF 402

1

C7882

0.47UF

10%

6.3V

2

CERM-X5R 402

2

R7883

10K

5% 1/16W MF-LF 402

1

C7883

0.47UF

10%

6.3V

2

CERM-X5R 402

VTT Rail Enable

=P3V3S5_EN_L =P0V9S5_EN

1

C7801

0.033UF

10% 16V

2

X5R 402

OUT

PM_SLP_S3_R_L

MAKE_BASE=TRUE

2

R7884

5.1K

5% 1/16W MF-LF 402

1

P3V3S0_EN

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

P1V5S0_EN

MAKE_BASE=TRUE

MCPCORES0_EN

MAKE_BASE=TRUE

CPUVTTS0_EN

MAKE_BASE=TRUE

1

C7884

0.47UF

10%

6.3V

2

CERM-X5R 402

Power Control Signals

State Run (S0) Sleep (S3) Soft-Off (S5)

Battery Off (G3Hot)

56

OUT

61

OUT

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

SSM6N15FEAPE

AP_PWR_EN

30 19

IN

SSM6N15FEAPE

56

36 35 19

66 62 35 19

63

SMC_ADAPTER_EN

IN

PM_SLP_S3_L

7

IN

ENET Rail Enables

PM_SLP_RMGT_L

IN

MAKE_BASE=TRUE

57

34

=P5VS0_EN =PBUSVSENS_EN

=P3V3S0_EN =P1V8S0_EN =P1V5S0_EN =MCPCORES0_EN =CPUVTTS0_EN

VTT rail must ramp up in about the same time as MEMVDD rail (Q2300).

=DDRVTT_EN

63 61

9 8

57

OUT

=PP3V3_ENET_FET

OUT

Q7890

SOT563

Q7890

SOT563

63

39

63

61

63

59

60

SMC_PM_G2_ENABLE

D

2

SG

D

5

SG

EXT1V05

R7850

EXT1V05

R7851

1 1 1 0

PM_WLAN_EN_L

Pull-up is with power FET.

6

1

AC_OR_S0_L

3

4

15K

1/16W MF-LF

10K

1/16W MF-LF

5%

402

5%

402

=P3V3ENET_EN =P0V9ENET_EN

1

2

1

2

6

D

S G

1

P1V05ENET_EN

MAKE_BASE=TRUE

=P1V05ENET_EN

30

OUT

Q7891

SSM6N15FEAPE

SOT563

2

OUT OUT

ISL6259 Frequency Select

PM_SLP_S3_LPM_SLP_S4_L 1 1 0 0

1 0 0 0

62 36 35 19

66 62 35 19

PM_SLP_S4_L

7

PM_SLP_S3_L

7

VFRQ:SLPS4&VFRQ:SLPS3&VFRQ:HIGH

VFRQ:SLPS4

R7864

1 2

1/16W MF-LF

VFRQ:SLPS3

R7863

1 2

1/16W MF-LF

VFRQ:SLPS4&VFRQ:SLPS3

0

5%

402

0

5%

402

=PP3V42_G3H_CHGR

55

8

CHGR_VFRQ_GATE

R7861

Q7860

SSM3K15FV

SOD-VESM-HF

1

10K

5% 1/16W MF-LF

402

G S

1

2

CHGR_VFRQ

VFRQ:LOW

3

D

1

R7860

10K

5% 1/16W MF-LF 402

2

55

OUT

D

S0 Rail PGOOD Circuitry

PP5V_S0

8 7

S0PGOOD_ISL

PP3V3_S0

75 62

8 7

PP1V5_S0

75 62

8 7

PP1V05_S0

62

8 7

63 19

63

PP3V3_S0

75 62

8 7

61

OUT

PP1V5_S0

75 62

8 7

PP1V05_S0

62

8 7

1

R7870

10K

1% 1/16W MF-LF

R7871

20.0K

1/16W MF-LF

Worst-Case Thresholds: VDD: 2.9140V V2MON: 3.000V V3MON: 0.610V V4MON: 0.610V

S0 Rail PGOOD (ISL Version)

402

2

PP3V3_S0_VMON

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

1

S0PGOOD_ISL

1%

402

2

C7870

S0 Rail PGOOD (BJT Version)

S0PGOOD_BJT

1

R7821

15.0K

1% 1/16W MF-LF 402

2

VMON_3V3_DIV VMON_Q2_BASE

S0PGOOD_BJT

1

R7822

7.15K

1% 1/16W MF-LF 402

2

1

0.1uF

20% 10V

2

CERM

402

=PP3V3_S5_VMON

8

S0PGOOD_BJT

R7823

1 2

1/16W MF-LF

S0PGOOD_BJT

R7824

1 2

1/16W MF-LF

S0PGOOD_BJT

R7825

1 2

1/16W MF-LF

CRITICAL S0PGOOD_ISL

2

7

VDD

VDDA

U7870

ISL88042IRTJJZ

TDFN

GND

4

150K

1/16W MF-LF

1%

402

(IPU)

MR*

RST*

THRM_PAD

9

353S2718

1

2

S0PGOOD_BJT_L

3

V2MON

5

V3MON

6 8

V4MON

R7826

1K

5%

402

1K

VMON_Q3_BASE

5%

402

1K

VMON_Q4_BASE

5%

402

Worst-Case Thresholds: Q2: 0.XXXV Q3: 0.640V Q4: 0.660V

1

NC

S0PGOOD_RST_L

5

8

NC

7

2

NC

1

6

Q2

Q3

Q4

3

56

59

60

61

4

353S2809

VMON_EMITTER

3.3V w/Divider: 2.345V

SYNC_MASTER=(T27_MLB)

PAGE TITLE

Unused PGOOD signal

DDRREG_PGOOD

57

IN

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

36

=PP3V3_S0_PWRCTL

8

P5V3V3_PGOOD

IN

MCPCORES0_PGOOD

IN

CPUVTTS0_PGOOD

IN

MCPPLLLDO_PGOOD

IN

S0PGOOD_BJT

Q1

CRITICAL S0PGOOD_BJT

Q7820

ASMCC0179

DFN2015H4-8

S0PGOOD_BJT

R7827

1/16W MF-LF

Power Sequencing

NOSTUFF

S0PGOOD_BJT

1

100

5%

402

2

Apple Inc.

R

R7820

R7872

10

1 2

5% 1/16W MF-LF

402

R7828

10

1 2

5% 1/16W MF-LF

402

1

10K

5% 1/16W MF-LF

402

2

ALL_SYS_PWRGD

MAKE_BASE=TRUE

SYNC_DATE=(10/27/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

78 OF 109

SHEET

62 OF 76

C

35 25

OUT

B

A

SIZE

D

345678

2 1

3.3V S3 FET

=PP3V3_S5_P3V3S3FET

8

1

R7912

10K

5% 1/16W MF-LF

D

402

2

P3V3S3_EN_L

Q7903

62

IN

=P3V3S3_EN

SSM3K15FV

SOD-VESM-HF

1

G S

3

D

2

0.033UF

R7910

47K

1 2

1/16W MF-LF

C7911

5%

402

10% 16V X5R 402

1

2

P3V3S3_SS

3.3V S0 FET

=PP3V3_S5_P3V3S0FET

8

1

R7932

100K

5% 1/16W MF-LF

402

1

G S

2

P3V3S0_EN_L

3

D

2

C

Q7905

SSM3K15FV

SOD-VESM-HF

=P3V3S0_EN

62

IN

0.033UF

R7930

47K

1 2

1/16W MF-LF

C7931

10% 16V X5R 402

5%

402

1

2

P3V3S0_SS

CRITICAL

Q7910

FDC638P_G

4

SM

3

C7910

0.01UF

1 2

10% 16V

CERM

402

CRITICAL

Q7930

FDC606P_G

SOT-6

SGD

3

C7930

0.01UF

1 2

10% 16V

CERM

402

6 5 2 1

6521

=PP3V3_S3_FET

=PP3V3_S0_FET

1.5V S0 FET

8

3.3V S3 FET

MOSFET CHANNEL RDS(ON) LOADING

3.3V S0 FET

MOSFET CHANNEL RDS(ON) LOADING

FDC638P P-TYPE 48 mOhm @4.5V

0.811 A (EDP)

FDC606P P-TYPE 26 MOHM @4.5V

1.240 A (EDP)

=PPDDR_S3_REG

57

8

=P1V5S0_EN

62

IN

R7922

10K

5% 1/16W MF-LF

402

Q7923

SSM3K15FV

SOD-VESM-HF

1

G S

=PP3V3_S5_P3V3ENETFET

8

R7962

1/16W MF-LF

Q7961

SSM6N15FEAPE

SOT563

1

2

P1V5S0_EN_L

3

D

2

1

10K

5%

402

2

P3V3ENET_EN_L

3

D

1

C7921

0.033UF

10% 16V

2

X5R 402

R7920

47K

1 2

5% 1/16W MF-LF

402

P1V5S0_SS

3.3V ENET FET

@ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C)

1

5% 1/16W MF-LF

402

2

R7960

100K

1 2

CRITICAL

Q7920

FDC638P_G

4

CRITICAL

Q7960

NTR4101P

SOT-23-HF

C7961

0.033UF

10% 16V X5R 402

P3V3ENET_SS

SM

3

C7920

0.01UF

1 2

CERM

G

1

10% 16V

402

32

DS

C7960

0.01UF

10% 16V

CERM

402

6 5 2 1

12

=PP1V5_S0_FET

=PP3V3_ENET_FET

8

1.5V S0 FET

MOSFET CHANNEL RDS(ON) LOADING

62 61

9 8

FDC638P P-TYPE 48 mOhm @4.5V

0.795 A (EDP)

D

C

5

SG

=P3V3ENET_EN

62

IN

MOBILE:

Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN. Nets separated on ARB for alternate power options.

4

0.9V ENET FET

=PP0V9_ENET_P0V9ENETFET

B

=PP3V3_S5_P0V9ENETFET

8

1

(Used to be 5.0V LT S0 FET)

376S0778

31 2

P5VS0_SS

CRITICAL

Q7948

TPCP8102

23V1K-SM

S

G

4

7 85 6

D

C7943

0.01UF

1 2

10% 16V

CERM

402

=PP5V_S0_FET

5.0V LT S0 FET

8

MOSFET CHANNEL RDS(ON) LOADING

TPCP8102 P-TYPE

13.5 MOHM @4.5V

1.569 A (EDP)

62

IN

SSM6N15FEAPE

=P0V9ENET_EN

5.0V S0 FET

=PP5V_S3_P5VS0FET

8

1

R7943

47K

5% 1/16W MF-LF

402

2

P5VS0_EN_L

A

=P5VS0_EN

62

IN

Q7947

SSM3K15FV

SOD-VESM-HF

1

G S

3

D

2

0.033UF

R7944

1 2

C7942

10% 16V X5R 402

47K

5% 1/16W MF-LF

402

1

2

R7992

Q7991

SOT563

69.8K

1/16W MF-LF

5

402

1%

2

D

SG

DO NOT SYNC FROM K84. ADDED ENET CIRCUITS, REMOVED 1V05 ENET CIRCUIT

8 7 5 4 2 1

8

P0V9ENET_EN_L

3

4

36

R7990

100K

1 2

5% 1/16W MF-LF

402

P0V9ENET_SS

Q7991

SSM6N15FEAPE

R7991

10K

1 2

1% 1/16W MF-LF

402

1

C7990

0.1UF

20% 10V

2

CERM

402

D

SOT563

2

SG

P0V9ENET_EN_L_RC

3

CRITICAL

D

Q7990

10% 16V

CERM

402

S

2

1

2

SI2312BDS

SOT23

=PP0V9_ENET_FET

Q7990

MOSFET Type Rds(on) ID(max) Loading

SI2312BDS N-Channel 37 mOhm @2.5V

3.25 A @85C

0.140 A (EDP)

G

1

6

C7991

1

0.01UF

SYNC_MASTER=MASTER

PAGE TITLE

POWER FETS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=MASTER

051-8561

C.0.0

79 OF 109

63 OF 76

SIZE

B

A

D

345678

2 1

D

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

LVDS_IG_PANEL_PWR

9

1

R9014

1K

5% 1/16W MF-LF 402

2

=PP3V3_S0_LCD_PANEL

8

1

C9009

0.1UF

10% 16V

2

X5R 402

C

B

APN 353S2805

CRITICAL

U9000

FPF1009

MFET-2X2-8IN

1

ON

2

VIN_1

3

VIN_2

GND 6 7

VOUT_1

VOUT_2

THRM

PAD

LCD CONNECTOR

L9004

4

5

1

C9011

0.1UF

10% 16V

2

X5R 402

1

C9012

10UF

20%

6.3V

2

X5R 603

PP3V3_SW_LCD_PANEL

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

FERR-120-OHM-1.5A

CRITICAL

120-OHM-0.3A-EMI

=PP3V3_S0_LCD_DDC

8

1

R9009

100K

5% 1/16W MF-LF 402

2

LVDS_IG_A_CLK_N

71

9

LVDS_IG_A_CLK_P

71

9

LVDS_IG_DDC_CLK

9 7

LVDS_IG_DDC_DATA

9 7

1

R9008

100K

5% 1/16W MF-LF 402

2

0402-LF

L9008

0402-LF

21

7

VOLTAGE=3.3V

(LVDS DDC POWER)

CRITICAL

L9080

90-OHM-200MA

AMC2012-SM

SYM_VER-1

4

3 2

PLACE_NEAR=J9000.32:1MM PLACE_NEAR=L9004.1:1MM

PP3V3_S0_LCD_DDC_F

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

75

1

C9015

0.001UF

10% 50V X7R 402

MIN_NECK_WIDTH=0.20 MM MIN_LINE_WIDTH=0.30 MM

VOLTAGE=3.3V

LVDS_IG_A_CLK_F_N

7

LVDS_IG_A_CLK_F_P

7

PPVOUT_S0_LCDBKLT

67 46

7

1

C9017

1000PF

5% 50V

2

C0G-CERM 603

PLACE_NEAR=J9000.19:1MM

PLACE_NEAR=J9000.32:1MM PLACE_NEAR=L9004.1:1MM

1

C9010

0.001UF

10% 50V

2

X7R 402

L9050

=PP5V_S3_CAMERA

8

2 1

FERR-120-OHM-1.5A

0402-LF

PLACE_NEAR=L9050.2:1MM

C9016

0.1uF

CERM

20% 10V

402

LVDS CONNECTOR:518S0650

ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY

1

2

PP3V3_SW_LCD_PANEL_F

7

LVDS_IG_A_DATA_N<0>

71

9 7

LVDS_IG_A_DATA_P<0>

71

9 7

LVDS_IG_A_DATA_N<1>

71

9 7

LVDS_IG_A_DATA_P<1>

71

9 7

LVDS_IG_A_DATA_N<2>

71

9 7

LVDS_IG_A_DATA_P<2>

71

9 7

LED_RETURN_6

67

7

LED_RETURN_5

67

7

LED_RETURN_4

67

7

LED_RETURN_3

67

7

LED_RETURN_2

67

7

LED_RETURN_1

67

7

PP5V_S3_CAMERA_F

7

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

1

2

FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED

NC

CRITICAL

J9000

20474-030E-11

F-RT-SM 31

32

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

LED BKLT I/F

20 21 22 23 24 25 26 27 28 29 30

CAMERA I/F

33 34

LVDS I/F

C

B

CRITICAL

L9060

90-OHM

DLP0NS

SYM_VER-1

72 18

OUT

USB_CAMERA_P

USB_CAMERA_N

PLACEMENT_NOTE=PLACE CLOSE TO J9000.

43

12

A

8 7 5 4 2 1

CAMERA

USB_CAMERA_CONN_P

75

7

USB_CAMERA_CONN_N

75

7

36

SYNC_MASTER=(K84_MLB)

PAGE TITLE

LVDS CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=(10/19/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

90 OF 109

SHEET

64 OF 76

SIZE

A

D

345678

2 1

D

C9300

DP_IG_AUX_CH_P

71

9

3

SIGNAL_MODEL=DP_AUXCH_FET

D

OMIT

Q9300

SSM6N16FE

SOT563

DP_IG_AUX_CH_N

71

9

3

C

SIGNAL_MODEL=DP_AUXCH_FET

D

OMIT

Q9302

SSM6N16FE

SOT563

4

G S

5

4

G S

5

0.1UF

1 2

10% 16V X5R 402

DP_EXT_DDC_CLK

C9301

0.1UF

1 2

10% 16V X5R 402

DP_EXT_DDC_DATA

1

C9303

0.0033UF

10% 50V

2

CERM 402

1

GS

OMIT

2

Q9300

SSM6N16FE

SOT563

1

GS

OMIT

2

Q9302

SSM6N16FE

SOT563

6

D

SIGNAL_MODEL=DP_AUXCH_FET

376S0857

6

D

SIGNAL_MODEL=DP_AUXCH_FET

376S0857

DP_AUX_CH_C_P

DP_AUX_CH_C_N

9

D

C

DP_CA_DET

B

PART NUMBER

376S0859 CRITICAL2

QTY

DESCRIPTION

XSTR,FT,N-CH,DUAL,SOT-563

REFERENCE DES

Q9300,Q9302

A

8 7 5 4 2 1

9

IN

CRITICAL

BOM OPTION

B

SIZE

A

D

SYNC_MASTER=K6_MLB

PAGE TITLE

DISPLAYPORT SUPPORT

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

93 OF 109

SHEET

65 OF 76

36

345678

2 1

Port Power Switch

D

=PP3V3_S5_DP_PORT_PWR

8

7

IN

PM_SLP_S3_L

C9481

0.1UF

CERM

20% 10V

402

CRITICAL

1

C9480

22UF

6.3V

X5R-CERM-1

2

20%

603

1

2

62 35 19

5 4

CRITICAL

1

C9487

100UF

20%

6.3V

2

POLY-TANT CASE-B2-SM

CRITICAL

U9480

TPS2051B

SOT23

IN

EN

GND

2

OUT

OC*

C9485

0.1UF

CERM

20% 10V

402

L9400

PP3V3_S0_DPILIM

FERR-120-OHM-3A

20%

6.3V X5R 603

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

TP_DPPWR_OC_L

1

C9400

0.01UF

20% 16V

2

CERM 402

1

3

1

C9486

10UF

2

0603

21

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

75

DP_EXT_ML_F_P<0>

75

DP_EXT_ML_F_N<0>

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

FL9400

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

1

75

4

32

75

DP_EXT_ML_C_P<0>

DP_EXT_ML_C_N<0>

C9410

0.1uF

C9411

0.1uF

1 2

DP_EXT_ML_P<0>

16V10% 402X5R

DP_EXT_ML_N<0>

X5R 40210% 16V

9

IN

9

IN

D

75

C

75

9

IN

75

9

IN

75

9

BI

75

9

BI

DP_EXT_ML_P<3>

DP_EXT_ML_N<3>

DP_EXT_AUX_CH_C_P DP_EXT_AUX_CH_C_N

=PP3V3_S0_DPCONN

66

8

=PP5VR3V3_S0_DPCADET

8

DP_EXT_CA_DET

9

OUT

C9414 C9415

1 2

0.1uF

1 2

0.1uF

2N7002DW-X-G

16V10% 402X5R

R9443

100K

1/16W MF-LF

Q9440

SOT-363

402

B

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

=PP3V3_S0_DPCONN

66

8

R9445

10K

1/16W MF-LF

9

OUT

DP_EXT_HPD

2N7002DW-X-G

402

Q9441

SOT-363

A

DO NOT SYNC. K6 PAGE WITH K84 CONNECTOR

8 7 5 4 2 1

DP_EXT_ML_C_P<3>

75

DP_EXT_ML_C_N<3>

75

X5R 40210% 16V

1

5%

2

6

D

G

S

1

2N7002DW-X-G

1

5%

2

6

D

G

S

1

2N7002DW-X-G

R9442

100K

1/16W MF-LF

2

DP_CA_DET_Q_L

Q9440

SOT-363

R9444

10K

1/16W MF-LF

2

DP_HPD_Q_L

Q9441

SOT-363

402

1

5%

2

3

4

1

5%

2

3

4

12-OHM-100MA

D

G

S

D

G

S

FL9403

TCM1210-4SM

SYM_VER-2

4

3 2

5

DP_HPD_Q

5

IO

6

NC NC

1

R9420

100K

5% 1/16W MF-LF

402

2

1

DP_EXT_ML_F_P<3>

75

DP_EXT_ML_F_N<3>

75

CRITICAL

1

R9421

100K

5% 1/16W MF-LF

402

2

PLACE_NEAR=J9400.12:3MM

DP_CA_DET_Q

R9422

1M

5% 1/16W MF-LF

402

R9423

100K

5% 1/16W MF-LF

402

RCLAMP0524P

2 9

DP to DVI/HDMI

1

Cable Adapter (CA) has 100k pull-up to DP_PWR.

2

DP Source must pull

1

down HPD input with greater than or equal to 100K (DPv1.1a).

2

1

2

DP_ESD

D9411

SLP2510P8

IO NC NC

GND

3

HDMI_CEC

R9425

1M

5% 1/16W MF-LF 402

1

IO

10

10 12 14

18 20

CRITICAL

MINIDSPLYPRT-K83-GEN2

2 4 6 8

RCLAMP0504F

J9400

F-RT-THSM

BOT ROW TOP ROW

TH PINS SM PINS

HOT_PLUG_DETECT CONFIG1 CONFIG2 GND ML_LANE3P ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR

DP_ESD

CRITICAL

ML_LANE0P ML_LANE0N

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

SHIELD PINS

22

RETURN

21

514-0706

D9400

SC70-6-1

PLACE_NEAR=J9400.2:3MM

1

2 5

3

6

4

GND

1 3 5 7 9 11 13 1516 17 19

75

DP_EXT_ML_F_P<1>

DP_EXT_ML_F_N<1>

75

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

2

IO

9

NC NC

DP_EXT_ML_F_P<2>

75

DP_EXT_ML_F_N<2>

75

DP_ESD

CRITICAL

D9411

RCLAMP0524P

SLP2510P8

5

IO

6

NC NC

IO

GND

3

IO

GND

3

IO

GND

3

4 7

PLACE_NEAR=J9400.3:3MM

FL9401

12-OHM-100MA

TCM1210-4SM

1

1 10

PLACE_NEAR=J9400.9:3MM

FL9402

12-OHM-100MA

TCM1210-4SM

1

4 7

PLACE_NEAR=J9400.15:3MM

SYM_VER-2

4

75

DP_EXT_ML_C_P<1>

32

75

DP_EXT_ML_C_N<1>

4

75

DP_EXT_ML_C_P<2>

32

75

DP_EXT_ML_C_N<2>

1 2

DP_EXT_ML_P<1>

16V10% 402X5R

DP_EXT_ML_N<1>

X5R 40210% 16V

DP_EXT_ML_P<2>

16V10% 402X5R

DP_EXT_ML_N<2>

16V10% 402X5R

C9412

0.1uF

C9413

0.1uF

C9416

0.1uF

C9417

0.1uF

SYNC_MASTER=MASTER

PAGE TITLE

DisplayPort Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

94 OF 109

SHEET

66 OF 76

C

75

9

IN

75

9

IN

B

75

9

IN

75

9

IN

A

SIZE

D

36

345678

2 1

D

PPBUS_S0_LCDBKLT_PWR

68

ISNS_LCDBKLT_P

75 46

OUT

ISNS_LCDBKLT_N

75 46

OUT

PLACE_NEAR=U9700.1:3MM

C

68

9

IN

B

SENS_R:ENG

CRITICAL

R9700

0.020

1%

0.25W MF-LF

805

1

C9727

1000PF

5%

50V 603

2

C0G-CERM

LVDS_IG_BKL_PWM

1/16W MF-LF

0

5%

402

PLACE_NEAR=L9710:3MM

CRITICAL

D9710

SOD-123 1 2

RB160M-40

1

2

R9715

1/16W MF-LF

<Ra>

R9716

243K

1/16W MF-LF

<Rb>

1

1M

1%

402

2

1

PLACE_NEAR=U9700.25:1MM

1%

XW9700

402

2

PLACE_NEAR=D9710.2:3MM

CRITICAL

1

C9715

4.7UF

20% 50V

2

X7R-CERM 1206

CRITICAL

1

C9716

4.7UF

20% 50V

2

X7R-CERM 1206

PLACE_NEAR=XW9701.1:3MM

1

C9717

1000PF

10% 100V

2

X7R 603

WF: C9711 AND C9717 NOT IN REF SCHEMATIC.

NOSTUFF

1

C9721

100PF

5% 50V

2

CERM 402

NOSTUFF

C9722

100PF

CERM

NOSTUFF

1

C9723

100PF

5% 50V

2

CERM 402

NOSTUFF

1

C9724

100PF

5%

50V

2

402

CERM

5%

50V 402

NOSTUFF

1

C9725

100PF

5% 50V

2

CERM 402

NOSTUFF

1

C9726

100PF

5%

2

CERM

50V 402

OMIT

SM

1 2

PLACEMENT_NOTE=PLACE XW9700 FAR FROM THE NOISY PINS 3 AND 4

OMIT

XW9701

SM

1 2

PLACEMENT_NOTEs: PLACE NEAR U9700

PLACE NEAR U9700

PLACE NEAR U9700 (C9721-C9726)

1

BKLT:PROD

2

R9717

0

1 2

5%

1/16W

MF-LF

402

BKLT:PROD

R9720

1 2

5%01/16W

402

MF-LF

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=50V

BKLT:PROD

R9718

0

1 2

1/16W

5%

MF-LF

402

BKLT:PROD

R9721

0

1 2

1/16W

5%

402

MF-LF

7

BKLT:PROD

R9719

0

1 2

1/16W

5%

402

MF-LF

BKLT:PROD

R9722

1 2

5%

MF-LF

64 46

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm

0

1/16W

402

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

IN

CRITICAL

L9710

21 43

PPVIN_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=9V

PLACEMENT_NOTEs:

PLACE_NEAR=L9710:3MM

C9713

0.1UF

CRITICAL

1

C9710

10UF

10% 25V X5R 402

10% 25V

2

X5R 805

PLACEMENT_NOTE=PLACE CLOSE TO L9710

1

R9730

10

5% 1/16W MF-LF

2

402

1217AS-2SM

(C9710-C9711)

33UH-1.8A-110MOHM

LCDBKLT_VIN

MIN_LINE_WIDTH=0.3 MM

1

C9711

1UF

10% 25V

2

X5R 603-1

1

R9726

10K

1% 1/16W MF-LF 402

2

R9725

200

1% 1/16W MF-LF

402

12

1

2.2UF

20% 10V

2

X5R-CERM

402

LVDS_IG_BKL_PWM_R

1

C9799

47PF

5% 50V

2

CERM 402

C9705

0.033UF

10% 16V X5R 402

MIN_NECK_WIDTH=0.2 MM

PP2V5_S0_LCDBKLT

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=2.5V

PP5V5_S0_LCDBKLT

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

1

C9701C9700

2

1

2

VOLTAGE=5.5V

2.2UF

20% 10V X5R-CERM 402

LCDBKLT_COMP

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM

LCDBKLT_ISET

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM

(SGND)

20

VDC1

23

VDC2

16

PWM

18

WAKE

6

EN

17

COMP

15

ISET

1

VIN

CRITICAL

U9700

MC34845CEP

LLP

LCDBKLT_COMP_RC

1

R9705

3.32K

1% 1/16W MF-LF 402

2

C9706

220PF

CERM

25V 402

R9710

1

7.68K

1%

5%

1/16W MF-LF

2

402

2

<Riset>

GND

211319

PGNDA

5

PGNDB

2

THRM

PAD

ISET = 153mA / <Riset>

21

PPVOUT_S0_LCDBKLT_SW

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=50V SWITCH_NODE=TRUE

DIDT=TRUE

f = 600kHz

GND_LCDBKLT_PGND

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 MM VOLTAGE=0V

4

SWA

3

SWB

24

VOUT

OVP = Vovp * (1 + Ra/Rb) VOVP = 6.9V +/- 0.35V

22

LCDBKLT_OVP

OVP

7

BKL_MC_CH1

CH1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm

8

BKL_MC_CH2

CH2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

9

BKL_MC_CH3

CH3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

10

BKL_MC_CH4

CH4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

11

BKL_MC_CH5

CH5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

12

BKL_MC_CH6

CH6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

14

LCDBKLT_FAIL

FAIL

R9702

NOSTUFF

25

GND_LCDBKLT_SGND

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.24 MM VOLTAGE=0V

D

C

64

7

64

7

64

7

64

7

64

7

64

7

B

A

DO NOT SYNC FROM K84. L9710 CHANGED TO K6/K69

8 7 5 4 2 1

13.3 Inch, K84 Panel (9 LEDs per string)

TARGET: ISET = 20mA, OVP = 35V ACTUAL: ISET = 19.9mA, OVP = 35.2V

PART NUMBER

103S0198 BKLT:ENG3 101S0075

QTY

1

DESCRIPTION

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

RES,MF,0 OHM,5%,1/8W,SMD,LF,0805

REFERENCE DES

R9717,R9718,R9719

R9720,R9721,R9722

R9700

CRITICAL

BOM OPTION

BKLT:ENG103S0198 3

SENS_R:PROD

10.2 ohm resistors for current measurement on LED strings.

36

SYNC_MASTER=MASTER

PAGE TITLE

LCD Backlight Driver (MC34845)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

97 OF 109

SHEET

67 OF 76

SIZE

A

D

345678

CRITICAL

Q9806

FDC638APZ_SBMS001

F9800

=PPBUS_S0_LCDBKLT

8

IN

2AMP-32V

D

Q9807

SSM6N15FEAPE

9

IN

LVDS_IG_BKL_ON

68

SOT563

C

0402-HF

5

21

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PBUS_S0_LCDBKLT_EN_L

3

D

SG

4

BKLT_EN_L

Q9807

SSM6N15FEAPE

SOT563

1

R9808

301K

1% 1/16W MF-LF 402

2

PBUS_S0_LCDBKLT_EN_DIV

1

R9809

147K

1% 1/16W MF-LF 402

2

6

D

C9802

0.1UF

10% 16V X5R 402

1

2

SSOT6-HF

4

1 2 5 6

3

PPBUS_S0_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS S0 LCDBKLT FET

MOSFET

CHANNEL

RDS(ON)

LOADING

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.4 A (EDP)

67

OUT

2 1

D

C

2

SG

1

BKLT_PLT_RST_L

25

IN

B

NOSTUFF NOSTUFF

1

R9840

1K

5% 1/16W MF-LF 402

2

1

R9841

1K

5% 1/16W MF-LF 402

2

LVDS_IG_BKL_ON LVDS_IG_BKL_PWM

68

9

67

9

B

MCP79 HAD INTERNAL 10K PULL-UP FOR THESE SIGNALS MCP89 DRIVES THEM LOW

A

SYNC_MASTER=(K84_MLB)

PAGE TITLE

LCD Backlight Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=(10/19/2009)

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

98 OF 109

SHEET

68 OF 76

SIZE

A

D

345678

2 1

FSB (Front-Side Bus) Constraints

D

FSB_50S

FSB_DSTB_50S

SPACING_RULE_SET

FSB_DATA FSB_DSTB FSB_ADDR

FSB_ADSTB

FSB_1X

LAYER

*

* * * * *

ALLOW ROUTE ON LAYER?

=50_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC =3x_DIELECTRIC

=2x_DIELECTRIC

=STANDARD

MINIMUM LINE WIDTH

WEIGHT

? ? ? ? ?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

FSB_DATA FSB_DSTB FSB_ADDR

FSB_ADSTB

FSB_1X

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE=50_OHM_SE

LAYER

TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR =1:1_DIFFPAIR

LINE-TO-LINE SPACING

WEIGHT

=4x_DIELECTRIC =5x_DIELECTRIC =3x_DIELECTRIC =4x_DIELECTRIC =3x_DIELECTRIC

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD*

TABLE_PHYSICAL_RULE_ITEM

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended. FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe. DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 135 ps. Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 270 ps. Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right. Intel Design Guide recommends FSB signals be routed only on internal layers. NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

CPU Signal Constraints

LAYER

CPU_50S

CPU_27P4S

C

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

SPACING_RULE_SET

LAYER

CPU_AGTL CPU_8MIL CPU_COMP

CPU_GTLREF

CPU_ITP

CPU_VCCSENSE

Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

ALLOW ROUTE ON LAYER?

* =STANDARD =STANDARD

=27P4_OHM_SE*

LINE-TO-LINE SPACING

* * * * *

=2:1_SPACING

*

=STANDARD

8 MIL 25 MIL 25 MIL

25 MIL

MINIMUM LINE WIDTH

=27P4_OHM_SE

WEIGHT

? ? ? ? ? ?

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

=27P4_OHM_SE =27P4_OHM_SE

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

CPU_AGTL

TOP,BOTTOM

SR DG recommends at least 25 mils, >50 mils preferred

LAYER

LINE-TO-LINE SPACING

=2x_DIELECTRIC

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MCP FSB COMP Signal Constraints

LAYER

MCP_50S

SPACING_RULE_SET

MCP_FSB_COMP

B

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.1.4

LAYER

ALLOW ROUTE ON LAYER?

* =STANDARD =STANDARD

LINE-TO-LINE SPACING

*

8 MIL

MINIMUM LINE WIDTH

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

FSB Clock Constraints

CLK_FSB_100D

SPACING_RULE_SET

CLK_FSB

LAYER

*

ALLOW ROUTE ON LAYER?

=100_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

SPACING_RULE_SET

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRICCLK_FSB

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

7 MIL7 MIL

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

A

8 7 5 4 2 1

CPU / FSB Net Properties

ELECTRICAL_CONSTRAINT_SET

FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_DSTB0

FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1

FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2

FSB 4X Signal Groups

FSB 2X

Signals

FSB 1X Signals

FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_DSTB3

FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0

FSB_ADDR_GROUP1 FSB_ADSTB1

FSB_1X FSB_1X FSB_BREQ0_L

FSB_1X FSB_1X FSB_1X FSB_1X

FSB_CPURST_L FSB_1X FSB_1X FSB_1X

CPU_ASYNC CPU_BSEL CPU_FERR_L CPU_ASYNC CPU_INIT_L CPU_ASYNC_R CPU_ASYNC_R CPU_PROCHOT_L CPU_PWRGD CPU_ASYNC CPU_ASYNC PM_THRMTRIP_L FSB_CPUSLP_L CPU_FROM_SB CPU_DPRSTP_L CPU_ASYNC

FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP

CPU_IERR_L

PM_DPRSLPVR

(See above)

MCP_CPU_COMP MCP_FSB_COMP MCP_CPU_COMP MCP_FSB_COMP MCP_CPU_COMP MCP_FSB_COMP MCP_CPU_COMP MCP_FSB_COMP

CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP

XDP_TRST_L XDP_BPM_L XDP_BPM_L5

(FSB_CPURST_L)

CPU_VCCSENSE CPU_VCCSENSE

(CPU_VCCSENSE) (CPU_VCCSENSE)

NET_TYPE

PHYSICAL

FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S

FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_DSTB

FSB_50S FSB_50S FSB_50S

FSB_50S FSB_50S

FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S

CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S

CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D

CPU_50S

CPU_50S CPU_50S

MCP_50S MCP_50S MCP_50S MCP_50S

CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S

CPU_50SXDP_TDI CPU_ITP CPU_50SXDP_TDO CPU_ITP CPU_50SXDP_TMS CPU_ITP CPU_50SXDP_TCK CPU_ITP CPU_50S CPU_50S CPU_50S CPU_50S

CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S

SPACING

FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB

FSB_DATA FSB_DATA FSB_DSTB

FSB_ADDR FSB_ADDR FSB_ADSTB

FSB_ADDR FSB_ADSTB

FSB_1X FSB_1XFSB_1X FSB_1XFSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1XFSB_1X FSB_1XFSB_1X FSB_1X FSB_1X

CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL

CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB

CPU_AGTL CPU_AGTL

CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP

CPU_ITP CPU_ITP CPU_ITP CPU_ITP

CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE

FSB_D_L<15..0> FSB_DINV_L<0> FSB_DSTB_L_P<0> FSB_DSTB_L_N<0>

FSB_D_L<31..16> FSB_DINV_L<1> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1>

FSB_D_L<47..32> FSB_DINV_L<2> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2>

FSB_D_L<63..48> FSB_DINV_L<3> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3>

FSB_A_L<16..3> FSB_REQ_L<4..0> FSB_ADSTB_L<0>

FSB_A_L<35..17> FSB_ADSTB_L<1>

FSB_ADS_L FSB_BREQ0_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<2..0> FSB_TRDY_L

CPU_A20M_L CPU_BSEL<2..0> CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L

FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N

CPU_IERR_L PM_DPRSLPVR

IMVP_DPRSLPVR

MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND

CPU_GTLREF CPU_COMP<3> CPU_COMP<2> CPU_COMP<1> CPU_COMP<0>

XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L<4..0> XDP_BPM_L<5> XDP_CPURST_L

CPU_VID<6..0> IMVP6_VID<6..0> CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N

36

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

7

10 14

10 13 14

10 14

9

10

10 14

10 14 36

10 13 14

10 14

10 14 36

10 14

10 14 58

10 14

13 14

14

10

14 58

58

14

10 29

10

10 13

13

11 58

58

SYNC_MASTER=T27_MLB

PAGE TITLE

CPU/FSB Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

100 OF 109

SHEET

69 OF 76

SIZE

D

C

B

A

D

345678

2 1

Memory Bus Constraints

LAYER

ALLOW ROUTE ON LAYER?

MEM_40S

D

MEM_70D

SPACING_RULE_SET

MEM_CLK2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CMD2CMD MEM_CMD2MEM

MEM_DATA2DATA

MEM_DQS2MEM

MEM_2OTHER

LAYER

* * * * * * * * *

=70_OHM_DIFF

LINE-TO-LINE SPACING

=4:1_SPACING

=2:1_SPACING =2.5:1_SPACING =1.5:1_SPACING

=3:1_SPACING =1.5:1_SPACING

=3:1_SPACINGMEM_DATA2MEM

=3:1_SPACING

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLKMEM_CLK MEM_CLK MEM_CLK MEM_CLK MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CTRL

C

MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS MEM_DQS MEM_DQS MEM_CMD MEM_DQS MEM_DQS MEM_DQS

DDR3:

DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 360 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. CMD/CTRL signals should be matched within 150 ps. All memory signals maximum length is 1.030 ps.

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

B

MCP MEM COMP Signal Constraints

MCP_MEM_COMP

SPACING_RULE_SET

MCP_MEM_COMP

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.2.2

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_DATA

LAYER

ALLOW ROUTE ON LAYER?

* =STANDARD =STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

25 MIL

AREA_TYPE

* * * * *

AREA_TYPE

* * * * *

AREA_TYPE

* * * * *

MINIMUM LINE WIDTH

=70_OHM_DIFF

WEIGHT

? ? ? ? ? ? ? ? ?

SPACING_RULE_SET

MEM_CLK2MEM MEM_CLK2MEM MEM_CLK2MEM MEM_CLK2MEM MEM_CLK2MEM

SPACING_RULE_SET

MEM_CTRL2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM MEM_CTRL2MEM MEM_CTRL2MEM

SPACING_RULE_SET

MEM_DQS2MEM MEM_DQS2MEM MEM_DQS2MEM MEM_DQS2MEM MEM_DQS2MEM

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE

=70_OHM_DIFF=70_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

NV DG says 3x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 2x inner, 4x outer

TABLE_SPACING_RULE_ITEM

NV DG says 4x inner, 5x outer

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMDMEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

Need to support MEM_*-style wildcards!

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MAXIMUM NECK LENGTH

* *

A

8 7 5 4 2 1

DIFFPAIR PRIMARY GAP

AREA_TYPE

* * * * *

AREA_TYPE

* * * *

MEM_DATA2DATA

*

AREA_TYPE

**

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD* =STANDARD

=70_OHM_DIFF=70_OHM_DIFF*

MEM_CMD2MEM MEM_CMD2MEM MEM_CMD2CMD MEM_CMD2MEM MEM_CMD2MEM

MEM_DATA2MEM MEM_DATA2MEM MEM_DATA2MEM

MEM_DATA2MEM

MEM_2OTHER MEM_2OTHER MEM_2OTHER MEM_2OTHER MEM_2OTHER

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK MEM_A_CLK

MEM_A_CKE

MEM_A_CNTL MEM_A_CNTL

MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD

MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_40S MEM_A_DQ_BYTE4 MEM_40S MEM_A_DQ_BYTE5 MEM_40S MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7

MEM_A_DQ_BYTE0 MEM_40S MEM_A_DQ_BYTE1 MEM_40S MEM_A_DQ_BYTE2 MEM_40S MEM_A_DQ_BYTE3 MEM_40S MEM_A_DQ_BYTE4 MEM_40S MEM_A_DQ_BYTE5 MEM_40S MEM_A_DQ_BYTE6 MEM_40S MEM_A_DQ_BYTE7 MEM_40S

MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7

MEM_B_CLK MEM_B_CLK

MEM_B_CKE

MEM_B_CNTL MEM_B_CNTL

MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD

MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3

MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7

MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7

MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7

NET_TYPE

PHYSICAL

MEM_CLKMEM_70D MEM_CLKMEM_70D

MEM_40S

MEM_40S MEM_40S

MEM_40S

MEM_40S MEM_40S

MEM_40S MEM_40S MEM_40S

MEM_40S MEM_40S

MEM_70D

MEM_70D MEM_70D

MEM_70D

MEM_70D MEM_70D

MEM_40S

MEM_40S MEM_40S

MEM_40S MEM_40S MEM_CMD MEM_40S MEM_CMD MEM_40S MEM_CMD MEM_40S MEM_CMD

MEM_40S MEM_40S MEM_40S MEM_40S MEM_40SMEM_B_DQ_BYTE4 MEM_40S MEM_40S MEM_40S

MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S

MEM_70D

MEM_CTRL

MEM_CTRL MEM_CTRL

MEM_CMD MEM_CMDMEM_40S MEM_CMDMEM_40S MEM_CMD MEM_CMD

MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA

MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQS MEM_DQSMEM_70D MEM_DQS

MEM_CLK MEM_CLK

MEM_CTRL

MEM_CTRL MEM_CTRL

MEM_CMD

MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA

MEM_DQSMEM_70D MEM_DQS MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQS MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D MEM_DQSMEM_70D

MCP_MEM_COMPMCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMPMCP_MEM_COMPMCP_MEM_COMP

SPACING

MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0>

MEM_A_CKE<3..0> MEM_A_CS_L<3..0>

MEM_A_ODT<3..0> MEM_A_A<15..0>

MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L

MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56>

MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3> MEM_A_DM<4> MEM_A_DM<5> MEM_A_DM<6> MEM_A_DM<7>

MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7>

MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0>

MEM_B_CKE<3..0> MEM_B_CS_L<3..0>

MEM_B_ODT<3..0> MEM_B_A<15..0>

MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L

MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56>

MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7>

MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>

MCP_MEM_COMP_VDD MCP_MEM_COMP_GND

36

15 26

15 21 26

15 26

15 28

15 27

15 21 27

15 27

15 28

15

SYNC_MASTER=T27_MLB

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

101 OF 109

SHEET

70 OF 76

SIZE

D

C

B

A

D

345678

2 1

PCI-Express

*

* * *

ALLOW ROUTE ON LAYER?

=90_OHM_DIFF

=100_OHM_DIFF

LINE-TO-LINE SPACING

=3X_DIELECTRIC

LAYER

PCIE_90D

CLK_PCIE_100D =100_OHM_DIFF

SPACING_RULE_SET

LAYER

PCIE

CLK_PCIE

MCP_PEX_COMP

D

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.3

20 MIL

8 MIL

MINIMUM LINE WIDTH

=90_OHM_DIFF

=100_OHM_DIFF

WEIGHT

? ? ?

MINIMUM NECK WIDTH

=90_OHM_DIFF =90_OHM_DIFF

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

PCIE

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF =90_OHM_DIFF*

=100_OHM_DIFF =100_OHM_DIFF

LINE-TO-LINE SPACING

=4X_DIELECTRIC

NEED PCIe Gen1/Gen2 notes!

Analog Video Signal Constraints

LAYER

CRT_50S

SPACING_RULE_SET

LAYER

CRT CRT_2CRT CRT_2CLK

CRT_2SWITCHER

CRT_SYNC

MCP_DAC_COMP

C

CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.

- 50-ohm from first to second termination resistor.

- 75-ohm from output of three-pole filter to connector (if possible). R/G/B signals should be matched as close as possible and < 10 inches. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.1.

Digital Video Signal Constraints

LAYER

DP_90D

LVDS_100D

MCP_DV_COMP

SPACING_RULE_SET

LAYER

DISPLAYPORT

LVDS

LVDS intra-pair matching should be 5 mils. Pairs should be matched within 100 mils. NOTE: NV DG recommends 90 ohm differential for LVDS, but cable/display assume 100 ohm. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 100 ps. DisplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max trace length: LVDS 10 inches, DP 8.5 inches. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.4.2

B

SATA Interface Constraints

LAYER

SATA_90D

SPACING_RULE_SET

LAYER

SATA

SATA_TERMP 8 MIL

SATA intra-pair matching should be 1 ps. Max trace length: 12 inches for SATA Gen1/Gen2, TBD for SATA Gen3. SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.6

A

8 7 5 4 2 1

* * * * * *

* *

*

* *

ALLOW ROUTE ON LAYER?

LINE-TO-LINE SPACING

20 MIL 15 MIL 50 MIL

250 MIL =4x_DIELECTRIC =2x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=90_OHM_DIFF*

=100_OHM_DIFF

Y

LINE-TO-LINE SPACING

=3x_DIELECTRIC =3x_DIELECTRIC

ALLOW ROUTE ON LAYER?

=90_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

MINIMUM LINE WIDTH

=50_OHM_SE

MINIMUM LINE WIDTH

WEIGHT

? ? ? ? ? ?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE

CRTCRT

MAXIMUM NECK LENGTH

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

20 MIL 20 MIL

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM LINE WIDTH

=100_OHM_DIFF=100_OHM_DIFF

SPACING_RULE_SET

DISPLAYPORT

LVDS

MINIMUM NECK WIDTH

=100_OHM_DIFF

=STANDARD

LAYER

TOP,BOTTOM TOP,BOTTOM

MAXIMUM NECK LENGTH

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

WEIGHT

? ?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

SATA

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

AREA_TYPE

*

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

=STANDARD =STANDARD

LINE-TO-LINE SPACING

=4x_DIELECTRIC =4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF =90_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

SPACING_RULE_SET

CRT_2CRT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

=90_OHM_DIFF=90_OHM_DIFF

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD* =STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MCP89 Net Properties

ELECTRICAL_CONSTRAINT_SET

PEG_R2D

PEG_D2R

PCIE_AP_R2D

NET_TYPENET_TYPE

PHYSICAL

PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE PCIE_90D PCIE

PCIE_90D PCIE

PCIE_AP_D2R

PCIE_ENET_R2D

PCIE_ENET_D2R

PCIE_FW_R2D

PCIE_FW_D2R

MCP_PE0_REFCLK

MCP_PE1_REFCLK

MCP_PE2_REFCLK

MCP_PE3_REFCLK

MCP_PEX_CLK_COMP

CRT_GREEN CRT_BLUE CRT_SYNC

TMDS_IG_TXC TMDS_IG_TXD TMDS_IG_TXD DISPLAYPORT

DP_EXT_ML DP_EXT_ML DP_EXT_AUX_CH DP_EXT_AUX_CH

MCP_TMDS0_RSET MCP_TMDS0_VPROBE

LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D

CRT_50SCRT_RED CRT_50S CRT_50S CRT_50S CRT_50S

DP_90D DP_90D DP_90D DP_90D

MCP_DV_COMP

LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D

MCP_DV_COMP

SATA_90D

SATA_HDD_D2R SATA_90D

SATA_90D

SATA_90D SATA_90D SATA_90D

SATA_90D SATA_90D

MCP_SATA_TERMP

SPACING

PCIEPCIE_90D PCIEPCIE_90D

PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D

PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D PCIEPCIE_90D

CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE MCP_PEX_COMP

CRT CRT CRT CRT_SYNC CRT_SYNCCRT_SYNC MCP_DAC_COMPMCP_DAC_RSET MCP_DAC_COMPMCP_DAC_VREF

DISPLAYPORTTMDS_IG_TXC DISPLAYPORT DISPLAYPORT

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS

SATASATA_HDD_R2D SATA_90D SATA SATASATA_90D SATA SATA SATA SATA SATA SATASATA_ODD_R2D SATA_90D SATA SATA SATA SATASATA_ODD_D2R SATA_90D SATA SATA SATASATA_90D

SATA_TERMP

PEG_R2D_P<15..0> PEG_R2D_N<15..0> PEG_R2D_C_P<15..0> PEG_R2D_C_N<15..0> PEG_D2R_P<15..0> PEG_D2R_N<15..0> PEG_D2R_C_P<15..0> PEG_D2R_C_N<15..0>

PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N

PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N

PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N

PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_AP_P PCIE_CLK100M_AP_N PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N MCP_PEX0_TERMP

CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC MCP_TV_DAC_RSET MCP_TV_DAC_VREF

TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P<5..0> TMDS_IG_TXD_N<5..0>

DP_IG_ML_P<3..0> DP_IG_ML_N<3..0> DP_IG_AUX_CH_P DP_IG_AUX_CH_N

MCP_TMDS0_RSET MCP_TMDS0_VPROBE

LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_N<2..0> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3>

MCP_IFPAB_RSET MCP_IFPAB_VPROBE

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N

MCP_SATA_TERMP

9

16

9

17 24

9

7 9

17 24

18 33

7

18 33

7

18 33

7

18 33

7

18

D

16

65

64

33

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Constraints 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

102 OF 109

SHEET

71 OF 76

SIZE

C

B

A

D

36

345678

2 1

LPC Bus Constraints

LAYER

LPC_55S

CLK_LPC_55S

SPACING_RULE_SET

LAYER

LPC

CLK_LPC

D

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.7

ALLOW ROUTE ON LAYER?

* =STANDARD *

LINE-TO-LINE SPACING

*

=1.5x_DIELECTRIC

*

=2x_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

? ?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

USB 2.0 Interface Constraints

ALLOW ROUTE ON LAYER?

*

=STANDARD

* =90_OHM_DIFF =90_OHM_DIFF

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

MCP_USB_RBIAS

USB_90D

SPACING_RULE_SET

USB

LAYER

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.8

MINIMUM LINE WIDTH

8 MIL

=90_OHM_DIFF

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SMBus Interface Constraints

*

ALLOW ROUTE ON LAYER?

=55_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

SMB_55S

SPACING_RULE_SET

SMB

LAYER

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.9

HD Audio Interface Constraints

C

LAYER

ALLOW ROUTE ON LAYER?

HDA_55S

* *

LINE-TO-LINE SPACING

=2x_DIELECTRIC

SPACING_RULE_SET

HDA

MCP_HDA_COMP

LAYER

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.10

8 MIL

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM LINE WIDTH

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

WEIGHT

? ?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SIO Signal Constraints

CLK_SLOW_55S

SPACING_RULE_SET

CLK_SLOW

LAYER

*

ALLOW ROUTE ON LAYER?

LINE-TO-LINE SPACING

=1.5x_DIELECTRIC

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.11

MINIMUM LINE WIDTH

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SPI Interface Constraints

ALLOW ROUTE ON LAYER?

* =STANDARD =STANDARD

LINE-TO-LINE SPACING

*

=1.5x_DIELECTRIC

B

SPI_55S

SPACING_RULE_SET

SPI

LAYER

SOURCE: MCP89 Interface DG (DG-04625-001_v0.9), Section 2.12

MINIMUM LINE WIDTH

=55_OHM_SE

WEIGHT

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

MINIMUM NECK WIDTH

8 MIL

=90_OHM_DIFF

SPACING_RULE_SET

USB

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD

=90_OHM_DIFF

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD*

DIFFPAIR PRIMARY GAP

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD=STANDARD

=STANDARD=STANDARD

=90_OHM_DIFF

=STANDARD=STANDARD*

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MCP89 Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD LPC_FRAME_L LPC_RESET_L

MCP_LPC_CLK0

USB_EXTA

USB_MINI

USB_EXTD

USB_CAMERA

USB_BT

USB_TPAD

USB_IR

USB_EXTB

USB_T57

USB_EXTC

USB_SDCARD

USB_WM

PHYSICAL

LPC_55S LPC_55S LPC_55S

CLK_LPC_55S CLK_LPC_55S CLK_LPC_55S

USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D

NET_TYPE

MCP_USB_RBIASMCP_USB_RBIAS

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA (SMBUS_SMC_MGMT_SCL) (SMBUS_SMC_MGMT_SDA)

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

SMB_55S SMB_55S SMB_55S SMB_55S

HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S

MCP_HDA_PULLDN_COMP

MCP_SUS_CLK

SPI_CLK SPI_55S

SPI_MOSI

SPI_MISO

SPI_CS0 SPI_55S

CLK_SLOW_55S CLK_SLOW

SPI_55S SPI_55S SPI_55S SPI_55S

SPI_55S

SPI_55S SPI_55S SPI_55S SPI_55S

SPACING

LPC LPC LPC

CLK_LPC CLK_LPC CLK_LPC

USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB

SMB SMB SMB SMB

HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA

MCP_HDA_COMP

CLK_SLOWCLK_SLOW_55S

SPI SPI SPI SPI SPI SPI SPI

SPI SPI SPI SPI

LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L

LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS

USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_T57_P USB_T57_N USB_EXTC_P USB_EXTC_N USB_SDCARD_P USB_SDCARD_N USB_WM_P USB_WM_N

MCP_USB_RBIAS_GND SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA

HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R

MCP_HDA_PULLDN_COMP PM_CLK32K_SUSCLK_R

PM_CLK32K_SUSCLK SPI_CLK_R

SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L

SPI_MLB_CLK SPI_MLB_MOSI SPI_MLB_MISO SPI_MLB_CS_L

SPI_ALT_CLK SPI_ALT_MOSI SPI_ALT_MISO SPI_ALT_CS_L

19 35 37

19 25

25 35

25 37

18 34

34 75

9

18

9

18

9

18

9

18

18 64

18 30

18 43

9

18

9

18

18 34

9

18

9

18

9

18

9

18

9

18

9

18

9

18

9

18

13 19 38

19 38

19 48

19

19 48

19

19 48

48

19 48

19

19 25

25 35

19 37

7

37

19 37

7

37

7

19 37

7

37

37 47

37

D

C

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

MCP Constraints 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

103 OF 109

SHEET

72 OF 76

SIZE

A

D

345678

2 1

MCP RGMII (Ethernet) Constraints

*

ALLOW ROUTE ON LAYER?

LINE-TO-LINE SPACING

LAYER

MCP_MII_COMP

ENET_MII_55S

SPACING_RULE_SET

MCP_BUF0_CLK

ENET_MII

D

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

LAYER

88E1116R (Ethernet PHY) Constraints

*

ALLOW ROUTE ON LAYER?

LINE-TO-LINE SPACING

LAYER

ENET_MDI_100D

SPACING_RULE_SET

ENET_MDI

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

LAYER

C

=STANDARD

=55_OHM_SE

=100_OHM_DIFF

=3:1_SPACING

12 MIL

25 MIL

MINIMUM LINE WIDTH

7.5 MIL

=55_OHM_SE =55_OHM_SE =55_OHM_SE

MINIMUM LINE WIDTH

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

7.5 MIL

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF =100_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

ELECTRICAL_CONSTRAINT_SET

MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP

MCP_CLK25M_BUF0

ENET_INTR_L ENET_MDIO ENET_MDC ENET_MII_55S ENET_MII ENET_PWRDWN_L

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ENET_RXCLK

ENET_RXD_STRAP ENET_RXD_STRAP ENET_RXD ENET_MIIENET_MII_55S

ENET_TXCLK ENET_TXD0 ENET_TXD ENET_MIIENET_MII_55S ENET_TXD ENET_MIIENET_MII_55S

ENET_MDI ENET_MDI

NET_TYPE

PHYSICAL

ENET_MDI_100D ENET_MDI_100D ENET_MDI_100D ENET_MDI_100D

SPACING

MCP_BUF0_CLKENET_MII_55S MCP_BUF0_CLKENET_MII_55S

ENET_MIIENET_MII_55S ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S ENET_MIIENET_MII_55S ENET_MIIENET_MII_55S ENET_MIIENET_MII_55S ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S ENET_MIIENET_MII_55S ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S

ENET_MDI ENET_MDI ENET_MDI

MCP_MII_COMP_VDD MCP_MII_COMP_GND

MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1

ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L

ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R<3..0> ENET_RXD<0> ENET_RXD<3..1> ENET_RX_CTRL ENET_RXCTL_R

ENET_CLK125M_TXCLK_R ENET_CLK125M_TXCLK ENET_TXD<0> ENET_TXD<3..1> ENET_TX_CTRL

ENET_RESET_L ENET_MDI_P<3..0>

ENET_MDI_N<3..0> ENET_MDI_TRAN_P<3..0> ENET_MDI_TRAN_N<3..0>

18

9

31

18 31

9

31

18 31

31

18 31

31

9

31 32

32

31

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=MASTER

PAGE TITLE

Ethernet Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

104 OF 109

SHEET

73 OF 76

345678

2 1

D

C

1TO1_DIFFPAIR

LAYER

ALLOW ROUTE ON LAYER?

MINIMUM LINE WIDTH

=STANDARD=STANDARD

MINIMUM NECK WIDTH

=STANDARD =STANDARD

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

CHGR_CSI

CHGR_CSO

1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR

PHYSICAL

NET_TYPE

SPACING

SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB

SPACING

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

CHGR_CSI_P CHGR_CSI_N CHGR_CSI_R_P CHGR_CSI_R_N

CHGR_CSO_P CHGR_CSO_N CHGR_CSO_R_P CHGR_CSO_R_N

7

38

7

38

55

40 55

38

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=T27_MLB

PAGE TITLE

SMC Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=02/16/2010

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

106 OF 109

SHEET

74 OF 76

345678

2 1

SENSE_1TO1_55S THERM_1TO1_55S

DIFFPAIR

SPACING_RULE_SET

D

SENSE THERM AUDIO

SPACING_RULE_SET

ENETCONN

SPACING_RULE_SET

GND

MEM_POWER

SPACING_RULE_SET

GND_P2MM PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK MEM_CMD

C

MEM_CTRL GND_P2MM MEM_DATA GND_P2MM

MEM_DQS

NET_SPACING_TYPE1 NET_SPACING_TYPE2

PCIE SATA

USB

SATA

USB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

LVDS

* * *

ALLOW ROUTE ON LAYER?

=1:1_DIFFPAIR

LINE-TO-LINE SPACING

=2:1_SPACING =2:1_SPACING =2:1_SPACING

LINE-TO-LINE SPACING

LAYER

*

LAYER

LINE-TO-LINE SPACING

* *

LAYER

LINE-TO-LINE SPACING

* *

GND GND GND GND GND

GND GND GND GND

SB_POWER PWR_P2MM

GND

25 MILS

=STANDARD =STANDARD

0.20 MM

AREA_TYPE

* * * * *

AREA_TYPE

* * * * * * *

AREA_TYPE

*

MINIMUM LINE WIDTH

=55_OHM_SE =55_OHM_SE

WEIGHT

? ? ?

WEIGHT

?

WEIGHT

? ?

WEIGHT

1000 1000

SPACING_RULE_SET

GND_P2MM GND_P2MM

GND_P2MM

SPACING_RULE_SET

GND_P2MMCLK_PCIE GND_P2MM GND_P2MM GND_P2MM PWR_P2MMSB_POWERCLK_PCIE PWR_P2MMSB_POWER

SPACING_RULE_SET

GND_P2MM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_GTLREF

CPU_VCCSENSE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

B

MCP Fanout Constraint Relaxations

LAYER

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_DV_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MEM_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MII_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_USB_RBIAS

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_DV_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

ALLOW ROUTE ON LAYER?

*

TOP

TOP 0.1 MM

TOP

TOP 0.1 MM

*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.09 MM

0.1 MM

MEM_CLK

MEM_CMD MEM_CTRL MEM_DATA

MEM_DQS

CLK_FSB

ENET_MDI

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE =55_OHM_SE

=1:1_DIFFPAIR

MEM_POWER MEM_POWER MEM_POWER MEM_POWER MEM_POWER

GND GND GND GND

GND

MAXIMUM NECK LENGTH

5.8 MM

500 MIL

250 MIL0.25 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR

PWR_P2MM PWR_P2MM PWR_P2MM PWR_P2MM PWR_P2MM

GND_P2MM GND_P2MMCPU_COMP GND_P2MM GND_P2MM

GND_P2MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

* * * * *

AREA_TYPE

* * * *

AREA_TYPE

*

DIFFPAIR PRIMARY GAP

SPACING_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

Misc Net Properties

ELECTRICAL_CONSTRAINT_SET

(PCIE_AP)

(USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_TPAD) (USB_TPAD) (USB_CAMERA) (USB_CAMERA)

CLK_PCIE_100D CLK_PCIE_100D

USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D

ENET_MDI_100D ENET_MDI_100D

SATA_90D SATA

SATA_90D SATA SATA_90D SATA SATA_90D SATA

SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D SATA SATA_90D

SATA_90D SATA SATA_90D SATA_90D SATA

SATA_90D SATA

PCIE_90D PCIE PCIE_90D PCIE USB_90D USB_90D LVDS_100D LVDS_100D CLK_PCIE_100D CLK_PCIE_100D USB_90D USB_90D USB_90D USB_90D

I296 I297

I299

I298

PCIE_AP_D2R

PCIE_AP_R2D

USB_BT

LVDS_IG_A_CLK

MCP_PE1_REFCLK

USB_EXTA

USB_EXTB

GRAPHICS NET PROPERTIES

ELECTRICAL_CONSTRAINT_SET

(DP_EXT_ML)

(DP_EXT_AUX_CH)

DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D DP_90D

PHYSICAL

NET_TYPE

DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT

SPACING

CLK_PCIE CLK_PCIE

USB USB USB USB USB USB USB USB USB USB

ENETCONN ENETCONN

SATASATA_90D SATASATA_90D SATASATA_90D

SATASATA_90D SATASATA_90D

SATASATA_90D

SATA SATASATA_90D

SATA

SATASATA_90D

PCIEPCIE_90D PCIEPCIE_90D

USB USB LVDS LVDS CLK_PCIE CLK_PCIE USB USB USB USB

SPACING

PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N

USB_EXTA_MUXED_P

USB_EXTA_MUXED_N USB_LT1_P USB_LT1_N USB_TPAD_R_P USB_TPAD_R_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_LT2_P USB_LT2_N

ENETCONN_P<3..0>

ENETCONN_N<3..0> SATA_ODD_R2D_UF_P

SATA_ODD_R2D_UF_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N

SATA_HDD_D2R_FILT_P SATA_HDD_D2R_FILT_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N SATA_HDD_D2R_RDRV_IN_P SATA_HDD_D2R_RDRV_IN_N SATA_HDD_R2D_RDRV_IN_P SATA_HDD_R2D_RDRV_IN_N SATA_HDD_D2R_RDRV_OUT_P SATA_HDD_D2R_RDRV_OUT_N SATA_HDD_R2D_RDRV_OUT_P SATA_HDD_R2D_RDRV_OUT_N SATA_HDD_D2R_NORDRV_P SATA_HDD_D2R_NORDRV_N SATA_HDD_R2D_NORDRV_P SATA_HDD_R2D_NORDRV_N CONN_PCIE_MINI_D2R_P CONN_PCIE_MINI_D2R_N CONN_PCIE_MINI_R2D_P CONN_PCIE_MINI_R2D_N CONN_USB2_BT_P CONN_USB2_BT_N LVDS_IG_A_CLK_F_P LVDS_IG_A_CLK_F_N

PCIE_CLK100M_MINI_CONN_P

PCIE_CLK100M_MINI_CONN_N

CONN_USB_EXTA_P

CONN_USB_EXTA_N

CONN_USB_EXTB_P

CONN_USB_EXTB_N

DP_EXT_ML_P<3..0>

DP_EXT_ML_N<3..0>

DP_EXT_ML_C_P<3..0>

DP_EXT_ML_C_N<3..0>

DP_EXT_ML_F_P<3..0>

DP_EXT_ML_F_N<3..0>

DP_EXT_AUX_CH_C_P

DP_EXT_AUX_CH_C_N DP_EXT_DDC_DATA DP_EXT_DDC_CLK

34 72

43

7

33

7 9

7

34

9

66

9

65

Power Net Properties

ELECTRICAL_CONSTRAINT_SET

CPUTHMSNS_D2

I300

I301

CPU_THERMD

MCPTHMSNS_D2

64

MCP_THMDIODE

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_DIFFPAIR

I277

30

64

30

Audio Net Properties

ELECTRICAL_CONSTRAINT_SET

SPK_OUT

66

THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S THERM_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55SSENSE_DIFFPAIR SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55SSENSE_DIFFPAIR SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S

SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S

DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR

DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR

PHYSICAL

NET_TYPE

AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO

AUDIO AUDIO AUDIO AUDIO

SPACING

THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE MEM_POWER SB_POWER SB_POWER SB_POWER GND

SPACING

CPUTHMSNS_D1_P CPUTHMSNS_D1_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N MCPTHMSNS_D2_P MCPTHMSNS_D2_N MCP_THMDIODE_P

MCP_THMDIODE_N ISNS_1V5_S3_P ISNS_1V5_S3_N ISNS_1V5_S3_R_P ISNS_1V5_S3_R_N ISNS_AIRPORT_P ISNS_AIRPORT_N ISNS_AIRPORT_R_P ISNS_AIRPORT_R_N ISNS_HDD_P ISNS_HDD_N ISNS_HDD_R_P ISNS_HDD_R_N ISNS_LCDBKLT_P ISNS_LCDBKLT_N ISNS_LCDBKLT_R_P ISNS_LCDBKLT_R_N ISNS_ODD_P ISNS_ODD_N ISNS_ODD_R_P ISNS_ODD_R_N ISNS_CPUVTT_P ISNS_CPUVTT_N

MCPCORES0_VSEN_P

MCPCORES0_VSEN_N

PP1V5R1V35_S3

PP3V3_S5

PP3V3_S0

PP1V5_S0

GND

AUD_SPKRAMP_LIN_P

AUD_SPKRAMP_LIN_N

AUD_SPKRAMP_SUBIN_P

AUD_SPKRAMP_SUBIN_N

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

SSM2315L_P

SSM2315L_N

SSM2315S_P

SSM2315S_N

SSM2315R_P

SSM2315R_N

SPKRCONN_L_OUT_P

SPKRCONN_L_OUT_N

SPKRCONN_S_OUT_P

SPKRCONN_S_OUT_N

SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N

BI_MIC_P

BI_MIC_N

HS_MIC_P

HS_MIC_N

41

10 41

19 41

30 46

46

33 46

46

46 67

33 46

46

40

22 59

7 8

7

52 53

D

62

C

B

A

SYNC_MASTER=MASTER

PAGE TITLE

K87 SPECIFIC CONSTRAINTS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

8 7 5 4 2 1

36

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

108 OF 109

SHEET

75 OF 76

SIZE

A

D

345678

2 1

K87 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT 0.100MM

D

55_OHM_SE

LAYER

TOP,BOTTOM

LAYER

50_OHM_SE

TOP,BOTTOM

LAYER

40_OHM_SE

TOP,BOTTOM

LAYER

27P4_OHM_SE

TOP,BOTTOM

LAYER

70_OHM_DIFF

C

70_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

TOP,BOTTOM

LAYER

90_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

TOP,BOTTOM

LAYER

100_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

TOP,BOTTOM

LAYER

1:1_DIFFPAIR

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

ALLOW ROUTE ON LAYER?

*

MINIMUM LINE WIDTH

Y*

Y

MINIMUM LINE WIDTH

Y

MINIMUM LINE WIDTH

Y

MINIMUM LINE WIDTH

Y

MINIMUM LINE WIDTH

Y

Y*

MINIMUM LINE WIDTH

N*

Y

MINIMUM LINE WIDTH

N

Y

MINIMUM LINE WIDTH

N

Y

MINIMUM LINE WIDTH

Y

BOARD AREAS

NO_TYPE,BGA_P1MM

MINIMUM NECK WIDTH

=50_OHM_SE

=DEFAULT

=DEFAULTSTANDARD

MINIMUM NECK WIDTH

0.090 MM

0.076 MM

0.090 MM

0.076 MM

MINIMUM NECK WIDTH

0.115 MM

0.076 MM 0.076 MM

0.115 MM

MINIMUM NECK WIDTH

0.165 MM

0.126 MM

0.100 MM

MINIMUM NECK WIDTH

0.310 MM

0.222 MM0.222 MM

MINIMUM NECK WIDTH

=STANDARD

0.151 MM

0.185 MM

=STANDARD

0.100 MM

MINIMUM NECK WIDTH

=STANDARD =STANDARD

0.112 MM 0.112 MM

=STANDARD

0.095 MM0.095 MM

MINIMUM NECK WIDTH

=STANDARD

0.091 MM

=STANDARD

0.075 MM0.075 MM

0.091 MM

MINIMUM NECK WIDTH

=STANDARD

MAXIMUM NECK LENGTH

30 MM

12.7 MM

MAXIMUM NECK LENGTH

=STANDARD55_OHM_SE

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

DIFFPAIR PRIMARY GAP

0 MM

=DEFAULT

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

0.224 MM

0.200 MM

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

0.244 MM 0.244 MM

0.230 MM

DIFFPAIR PRIMARY GAP

BOARD UNITS (MIL or MM)

MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0 MM

=DEFAULT

=STANDARD=STANDARD

=STANDARD

=STANDARD=STANDARD

=STANDARD

0.224 MM

0.200 MM

=STANDARD

0.234 MM0.234 MM

0.220 MM0.220 MM

=STANDARD

0.230 MM

0.1 MM0.1 MM

ALLEGRO VERSION

15.5.1

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

SPACING_RULE_SET

DEFAULT

BGA_P1MM

BGA_P2MM =DEFAULT

BGA_P3MM

SPACING_RULE_SET

1.5:1_SPACING

2:1_SPACING

2.5:1_SPACING

3:1_SPACING

4:1_SPACING

SPACING_RULE_SET

1.5X_DIELECTRIC

2X_DIELECTRIC

3X_DIELECTRIC

4X_DIELECTRIC

5X_DIELECTRIC

1.5X_DIELECTRIC

2X_DIELECTRIC

3X_DIELECTRIC

4X_DIELECTRIC

5X_DIELECTRIC

LAYER

TOP,BOTTOM

*

LINE-TO-LINE SPACING

0.1 MM

=DEFAULTSTANDARD

=DEFAULT

LINE-TO-LINE SPACING

0.15 MM

0.2 MM

0.25 MM

0.3 MM

0.4 MM

LINE-TO-LINE SPACING

0.105 MM

0.140 MM

0.210 MM

0.280 MM

0.350 MM

0.095 MM

0.126 MM

0.189 MM

0.252 MM

0.315 MM

WEIGHT

?

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

MEM_CLK

CLK_FSB

CLK_LPC

CLK_PCIE

CLK_SLOW BGA_P1MM

BGA_P1MMBGA_P1MM

BGA_P2MMBGA_P1MM

BGA_P2MM

BGA_P3MMFSB_DSTBFSB_DSTB BGA_P1MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

NET_PHYSICAL_TYPE

MEM_40S

AREA_TYPE

PHYSICAL_RULE_SET

AREA_TYPE

**

*

SPACING_RULE_SET

BGA_P1MM BGA_P2MM

BGA_P1MM

BGA_P1MM BGA_P2MM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

STANDARDBGA_P1MM

D

C

SIZE

B

A

D

B

A

8 7 5 4 2 1

36

SYNC_MASTER=MASTER

PAGE TITLE

K87 RULE DEFINITIONS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

SYNC_DATE=MASTER

DRAWING NUMBER

051-8561

REVISION

C.0.0

BRANCH

PAGE

109 OF 109

SHEET

76 OF 76