apple k21_mlb_051-8870_3.13.0 Datasheet

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

87 6 5 4 21

12

APPD

CK

DESCRIPTION OF REVISION

DRAWING

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

04/18/11

PRODUCT SAFETY REQUIREMENTS:

PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE

NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP RATING AND V-O FLAME RATING

PCB,UL RECOGNIZED, MIN. 130-C TEMP RATING AND V-O FLAME RATING PER UL 796 & UL 94

SCHEM,EVT,MLB,K21

Schematic / PCB #’s

1 OF 75

051-8870

3.13.0

1 OF 109

2011-04-18

LAST_MODIFIED=Mon Apr 18 17:52:39 2011

SCHEM,MOCKUP,MLB,K21

High Side Current Sensing

54

K78_MLB

01/16/2011

46

Page

(.csa)

Sync

Date

Contents

PCBF,MLB,K21

CRITICAL

PCB

1

820-3023

SCHEM,MLB,K21

051-8870

SCH

1

CRITICAL

TITLE=MLB

ABBREV=DRAWING

MASTER

1

Table of Contents

1 MASTER

SyncPage

Date

(.csa)

Thermal Sensors

55

01/16/2011

47

Fan

56

K78_MLB

01/10/2011

IPD / KBD Backlight

57

K78_MLB

01/10/2011

SPI ROM

61

K78_MLB

01/10/2011

50

AUDI0: SPEAKER AMP

62

K78_MLB

01/10/2011

51

DC-In & Battery Connectors

69

JACK_K90I

08/20/2010

52

PBus Supply & Battery Charger

70

K78_MLB

12/03/2010

53

System Agent Supply

71

K78_MLB

01/16/2011

54

5V / 3.3V Power Supply

72

K78_MLB

01/16/2011

55

1.5V DDR3 Supply

73

K78_MLB

01/10/2011

56

CPU IMVP7 & AXG VCore Regulator

74

K78_MLB

01/10/2011

57

CPU IMVP7 & AXG VCore Output

75

K78_MLB

12/07/2010

58

CPU VCCIO (1.05V) Power Supply

76

K78_MLB

01/10/2011

59

Misc Power Supplies

77

K78_MLB

01/16/2011

60

Power FETs

78

K78_MLB

01/10/2011

61

Power Control 1/ENABLE

79

K78_MLB

01/10/2011

62

Internal DisplayPort Connector

90

K78_MLB

02/10/2011

63

DisplayPort/T29 A MUXing

93

K21_MLB

12/13/2010

64

DisplayPort/T29 A Connector

94

K78_MLB

12/07/2010

65

LCD Backlight Driver

97

K78_MLB

01/16/2011

66

CPU Constraints

100

K21_CONSTRAINTS

04/06/2011

67

Memory Constraints

101

K21_CONSTRAINTS

04/06/2011

68

PCH Constraints 1

102

K21_CONSTRAINTS

04/06/2011

PCH Constraints 2

103

K21_CONSTRAINTS

04/06/2011

70

Ethernet/FW Constraints

104

K21_CONSTRAINTS

04/06/2011

71

105

K21_CONSTRAINTS

04/06/2011

72

106

K21_CONSTRAINTS

04/06/2011

73

Project Specific Constraints

108

K21_CONSTRAINTS

04/06/2011

74

PCB Rule Definitions

109

K21_CONSTRAINTS

04/06/2011

75

12/11/2009

2

System Block Diagram

2 K6_MLB

19/01/2011

3

Power Block Diagram

3

MASTER

4

Revision History

4 MASTER

05/28/2009

5

BOM Configuration

5

K17_REF

(02/16/2010)

7

Functional Test / No Test

6 (K99_MLB)

05/15/2010

8

Power Aliases

7

K91_MLB

9

Signal Aliases

8

K91_MLB

01/10/2011

10

CPU DMI/PEG/FDI/RSVD

9

K78_MLB

01/10/2011

11

CPU CLOCK/MISC/JTAG

10

K78_MLB

01/10/2011

12

CPU DDR3 INTERFACES

11

K78_MLB

01/10/2011

13

CPU POWER

12

K78_MLB

01/10/2011

14

CPU GROUNDS

13

K78_MLB

02/08/2011

16

CPU DECOUPLING-I

14

K78_MLB

01/10/2011

17

CPU DECOUPLING-II

15

K78_MLB

12/13/2010

18

PCH SATA/PCIE/CLK/LPC/SPI

16

K21_MLB

12/13/2010

19

PCH DMI/FDI/GRAPHICS

17

K21_MLB

12/13/2010

20

PCH PCI/FLASHCACHE/USB

18

K21_MLB

12/13/2010

21

PCH MISC

19

K21_MLB

12/13/2010

22

PCH POWER

20

K21_MLB

01/10/2011

23

PCH GROUNDS

21

K78_MLB

01/10/2011

24

PCH DECOUPLING

22

K78_MLB

12/13/2010

25

CPU & PCH XDP

23

K21_MLB

12/13/2010

26

USB HUBS

24

K21_MLB

11/29/2010

27

Clock (CK505) and Chipset Support

25

K78_MLB

12/13/2010

28

CPU Memory S3 Support

26

K21_MLB

12/07/2010

29

DDR3 DRAM CHANNEL A (0-31)

27

K78_MLB

12/07/2010

30

DDR3 DRAM CHANNEL A (32-63)

28

K78_MLB

12/07/2010

31

DDR3 DRAM CHANNEL B (0-31)

29

K78_MLB

12/07/2010

32

DDR3 DRAM CHANNEL B (32-63)

30

K78_MLB

01/10/2011

33

FSB/DDR3/FRAMEBUF Vref Margining

31

K78_MLB

12/16/2010

34

DDR3 DRAM Channel B (32-63)

32

K78_MLB

(MASTER)

35

SecureDigital Card Reader

33

(MASTER)

01/10/2011

36

T29 Host (1 of 2)

34

K78_MLB

01/10/2011

37

T29 Host (2 of 2)

35

K78_MLB

01/10/2011

38

T29 Power Support

36

K78_MLB

12/13/2010

40

X21 WIRELESS CONNECTOR

37

K21_MLB

01/10/2011

45

SATA CONNECTOR

38

K78_MLB

12/13/2010

46

External USB Connectors

39

K21_MLB

11/09/2010

47

Left I/O (LIO) Connector

40

K21_MLB

01/10/2011

49

SMC41

K78_MLB

01/10/2011

50

SMC Support

42

K78_MLB

01/10/2011

51

LPC+SPI Debug Connector

43

K78_MLB

01/10/2011

52

SMBus Connections

44

K78_MLB

01/10/2011

53

Voltage & Load Side Current Sensing

45

K78_MLB

Contents

05/15/2010

69

SMC Constraints

T29 Constraints

49

48

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

CONN

PG 16

LIO BOARD

AUDIO CODEC

JTAG

SPEAKER

U6210

U6620

PG 10

FAN CONN

PG 29,30

SANDYBRIDGE SFF

DMI

PG 19

LPC

USB

J4700

PG 11

LINE IN

PG 8

FILTER

AMP

FILTER

LINE INSPEAKER

SPEAKER

LEFT

USB

XDP CONN

PCIE

0

DDR3-1066/1333MHZ

CONTROLLER

SD CARD

SERIAL

SMB_BSA SMB_B/0

ADC

FAN0

J5600

PG 52

CONN

IPD FLEX

J5100

INTEL CPU

JTAG

J2500

XDP CONN

RIGHT

64-Bit

PG 16

MISC

CTRL

DP OUT

3

SYSTEM

PG 23

EDP

DMI

PM_SLP S3/S4

PORT

MEMORY

U3100,3230

SPI

PG 9

64-Bit

BOOTROM

PG 50

HDMI OUT

J4600

EXT USB

CONN

PG 39

PG 49

J5700

EXT

USBUSB

CAM

10

PG 24

HUB-2

USB

U2650

51

CONN

SDCARD

J3500

PG 33

U3500

PG 33

U2600

HUB-1

USB

PG 24

PWR

B

A

U1000

PG 9

CONN

DDR3-1066/1333MHZ

MEMORY

LID

PG 51

AMP

J6903

SPEAKER

CONN

PG 52

RIGHT

SMB_A

U4900

MEMORY

U6100

PG 15

GPIO

PG 11

J4610

PCH

PG 23

WIRELESS

X21

J4001

CONN

PG 37

T29

1

U9390

CONN

PG 65

DISPLAY PORT+

PG 64

MUX

J9400

DP

U3600

T29 ROUTER

PCIE

PG 34,35

PG 9

CONN

LVDS OUT

PG 16

I2C

SPK

J6702

PG 9

CONN

PG 10

U6201

J6700

JACK

HEADPHONE/

J6955

HDA

J4702

CAMERA+ALS

CONN

EFFECT

PG 51

HALL

LEFT

J4610

4

SSD

FDI

PG 9

FDI

PG 10

CPU

PG 63

1.6 GHZ

PG 16

PG 17

PG 16

CLOCK

PCI

PG 18PG 16

PG16

PG 17

PG 18

13

EDP OUT

TMDS OUT

RGB OUT

PG 27,38

PG 25

CLOCK

9

HDA

PG 38

6

PG 43

72

CHARGER

PG 52-60

POWER CIRCUITRY

LPC+SPI

TEMP SENSOR

PG 47

PG 41

PG 46

PG 48

U7000

VOLTAGE/CURRENT SENSOR

1G/2GB

SMC

SATA

BUFFER

PG 17

1112

80

DVI OUT

U2700

J4501

PCIE

1G/2GB

U2900,U3030

RTC

DISPLAY

INTERNAL

J9000

EXT USB

CONN

PG 5PG 6

HEADPHONE

PG 40

PG 7

LEFT I/O CONN

SMB

COUGAR POINT

INTEL PCH

U1800

PG 17

SYNC_MASTER=K6_MLB

System Block Diagram

SYNC_DATE=12/11/2009

2 OF 109

3.13.0

051-8870

2 OF 75

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

25

SMC_CPU_VSENSE

CPUVCCIOS0_PGOOD

ISL95870

PP5V_S0_CPUVCCIOS0.

K78/K21 POWER SYSTEM ARCHITECTURE

PPVIN_S5_P5VP3V3

EN2

TPS51980

PP3V3_SUS_FET

PPDCIN_G3H_OR_PBUS

AC

2S3P

(6 TO 8.4V)

PPVBATT_G3H_CONN

14-1

P5VS3_PGOOD

P5V_3V3_SUS_EN

P3V3S3_EN

PG 17

P5VS3_EN

P3V3S3_EN

DDRREG_EN

DELAY

RC

SLP_S4#(H4)

(PAGE 17~21)

P5VS0_EN

P3V3S5_PGOOD

P1V8S0_PGOOD

CPUIMVP_AXG_PGOOD

CPUVCCIOS0_PGOOD

PVCCSA_PGOOD

ALL_SYS_PWRGD

10-3

8

14

P5VS3_PGOOD

PP1V05_S0_LDO.

PP1V5S0_EN

EN

TPS72015

U7780

(PAGE 60)

Q7840

VIN

2

R5400

1.05V

22

25-1

(PAGE 59)

P3V3S5_PGOOD

VIN

PPVCCSA_S0_REG

23

PPVTT_S0_DDR_LDO

VOUT1

27

DDRREG_PGOOD

U7801

16

VOUT

9

14-1

Q9706

13-1

P3V3S5_EN

U7201

(PAGE 55)

PP5V_S3_REG

PP5V_SUS_FET

Q7810

U7740

CPU_VCCSA_VID<1>

23-1

V

U7100

PVCCSA_PGOOD

PP3V3_S5

PP3V3_S5_REG

S3

PP5V_S0_FET

10-4

PP1V05_S0_VMON

A

SMC_BATT_ISENSE

PPVBAT_G3H

15

CPUVCCIOS0_EN

ISL6259HRTZ

T29BST_EN_UVLO

EN/UVLO

DELAY

RC

CPUVCCIOS0_EN

21

P3V3S0_EN

14-1

PPBUS_SW_LCDBKLT_PWR

Q3880

PBUSVSENS_EN

(PAGE 36)

(PAGE 60)

PM_SLP_S3_L

RC

14

14-1

BKLT_PLT_RST_L

7

13

P5VS3_EN

PG62

13-2

LCD_BKLT_EN

P5V_3V3_SUS_EN

PG62

15

VIN

PG 17

VOUT2

P5V_3V3_SUS_EN

Q7820

(PAGE 66)

U9701

F7040

24

DELAY

R7978

SMC_RESET_L

F6905 6A FUSE

22-1

V

U7960

ISL88042IRTEZ

V3MON

V2MON

R7962

VDD

4

6

V4MON

(PAGE 62)

PP1V5_S3RS0_VMON

PP5V_S0_VMON

PPVCORE_S0_CPU_REG

U1800

RESET*

S5_PWRGD

SLP_S5_L(P95)

SMC

25

15

P17(BTN_OUT)

A

26

12

PLT_RERST_L

PM_DSW_PWRGD

CPUIMVP_VR_ON

Q7860

SLP_S3#(F4)

1V05_S0_LDO_EN

P1V8S0_EN

P1V5S0_EN

PVCCSA_EN

U3890

LT3957

T29_A_HV_EN

PP15V_T29_REG

LP8550

VIN

5V

(R/H)

VOUT1

VOUT

SLP_SUS#

(L/H)

29

PM_RSMRST_L

PM_PWRBTN_L

PM_MEM_PWRGD

CPU_PWRGD

30

10

P15

(PAGE 17~21)

RSMRST#

SYS_RERST#

COUGAR-POINT

PWRBTN#

SYSRST(PA2)

PROCPWRGD

RES*

PLTRST#

DRAMPWROK

SM_DRAMPWROK

UNCOREPWRGOOD

4

PP1V05_T29_FET

T29_PWR_EN

SMC POWER

SN0903048

R5330

R5320

ENABLE

PP3V42_G3H_REG

PGOOD

3.425V G3HOT

VOUT

VCC

U7400

U7600

EN

21

D6905

R6920

(PCH)

26-1

RSMRST_IN(P13)

PWRGD(P12)

(PAGE 41)

SLP_S3_L(P93)

SLP_S4_L(P94)

9

PM_SLP_S5_L

PGOOD

VIN

(PAGE 56)

EN

VCC

PVCCSA_EN

Q7830

PGOOD

PPVIN_G3H_P3V42G3H

VOUT

PBUS SUPPLY/

R6905

J6900

EN1

Q7055

7

11

PG 17

PG61

EN

VOUT

VIN

F9700

&&

PG62

13

PG62

PBUSVSENS_EN

PM_SLP_S4_L

SMC

U4900

6

U7940

RC

DELAY

PM_SLP_SUS_L

(PAGE 41)

P60

(PCH)

COUGAR-POINT

U1800

PM_SLP_S3_R_L

P5VS0_EN

22

21

19

17

DELAY

RC

DELAY

RC

DELAY

SMC_RESET_L

PP3V3_S0_VMON

Q5300

PP3V3_S3_FET

18

U7770

TPS720105

EN

ISL8014A

TPS22924

U7720

PP3V3_S0

P1V8_S0_EN

17

U3810

14

P3V3S0_EN

T29_PWR_EN

19

(PAGE 36)

PM_SYSRST_L

PM_DSW_PWRGD

28

CHGR_BGATE

SMC_DCIN_ISENSE

VIN

4

U7000

1

PPVBAT_G3H_CHGR_R

(PAGE 53)

DCIN(14.5V)

ADAPTER

IN

J6950

BATTERY CHARGER

R7020

R7050

1

3

LT3470A

U6990

U5010

(PAGE 42)

CPU

5

IMVP_VR_ON(P16)

RSMRST_OUT(P15)

CPUIMVP_VR_ON

PM_SYSRST_L

4

PM_PWRBTN_L

PWR_BUTTON(P90)

SMC_ONOFF_L

99ms DLY

PM_RSMRST_L

6-1

PM_SLP_S4_L

PM_SLP_S3_L

PM_SLP_S5_L

SMC_PM_G2_EN

P3V3S5_EN

3.3V

PPVOUT_SW_LCDBKLT

SMC_PBUS_VSENSE

EN

TPS720105

(PAGE 60)

PP1V05_SUS_LDO

VOUT

(PAGE 52)

(PAGE 9~15)

VR_ON

10-1

SLP_S5#(E4)

16-1

VOUT2

SMC_RESET_L

22

10-2

16

PP3V3_T29_FET

EN

PP1V5_S0_REG

PP1V5_S3RS0_FET

U2850

U1000

PM_PCH_PWRGD

R7140

P1V5CPU_EN

PGOOD

ISL95870A

(PAGE 54)

PGOOD

VID1

MAX15092GTL

CPU VCORE

VLDOIN

PGOODG

CPUIMVP_AXG_PGOOD

1.5V

0.75V

TPS51916

U7300

CPUIMVP_PGOOD

SMC_GFX_VSENSE

PPVCORE_S0_AXG_REG

26

R7350

A

(PAGE 60)

1V05_S0_LDO_EN

PP1V8_S0_REG

A

(PAGE 57)

S5

PP5V_S0_VCCSA

DPWROK

TPS22924

U3816/U3815

(PAGE 36)

EN

R7640

SMC_CPU_FSB_ISENSE

PPCPUVCCIO_S0_REG

PPDDR_S3_REG

DDRVTT_EN

DDRREG_EN

PPBUS_G3H

A

U4900

P1V8S0_PGOOD

Power Block Diagram

SYNC_DATE=19/01/2011

3 OF 109

3.13.0

051-8870

3 OF 75

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Bar Code Labels / EEEE #’s

BOM Variants

Sub BOM

[EEEE_DP1F]

[EEEE_DP1T]

[EEEE_DP1R]

[EEEE_DP1Q]

EEEE:DP1T

EEEE:DP1R

EEEE:DP1Q

EEEE:DP1P

[EEEE_DP1P]

EEEE:DP1N

[EEEE_DP1N]

EEEE:DP1M

[EEEE_DP1M]

EEEE:DP1L

[EEEE_DP1L]

[EEEE_DP1K]

[EEEE_DP1J]

LABEL,LIO,K99

825-7563

LABEL,LIO,K99

EEEE:DP1K

EEEE:DP1J

EEEE:DP1H

[EEEE_DP1H]

EEEE:DP1G

[EEEE_DP1G]

EEEE:DP1F

LABEL,LIO,K99

CRITICAL

1

825-7563

LABEL,LIO,K99

825-7563

K21_CMNPTS,EEEE:DP1M,CPU:1.7GHZ,DDR3:HYNIX_2GB

K21_COMMON

K21_CMNPTS,EEEE:DP1F,CPU:1.8GHZ,DDR3:HYNIX_2GB

K21_CMNPTS,EEEE:DP1G,CPU:1.7GHZ,DDR3:SAMSUNG_4GB

K21_CMNPTS,EEEE:DP1T,CPU:1.7GHZ,DDR3:MICRON_2GB

PCBA,MLB,1.7GHZ,MI 2GB,K21

639-2559

K21_CMNPTS,EEEE:DP1R,CPU:1.8GHZ,DDR3:SAMSUNG_2GB

PCBA,MLB,1.8GHZ,SA 2GB,K21

639-2556

639-2552

PCBA,MLB,1.7GHZ,SA 2GB,K21

K21_CMNPTS,EEEE:DP1Q,CPU:1.7GHZ,DDR3:SAMSUNG_2GB

PCBA,MLB,1.7GHZ,EL 4GB,K21

PCBA,MLB,1.8GHZ,EL 4GB,K21

PCBA,MLB,1.7GHZ,SA 4GB,K21

K21i MLB DEVELOPMENT BOM

K21_CMNPTS,EEEE:DP1P,CPU:1.7GHZ,DDR3:HYNIX_4GB

PCBA,MLB,1.7GHZ,HY 4GB,K21

639-2551

K21_CMNPTS,EEEE:DP1N,CPU:1.8GHZ,DDR3:MICRON_2GB

PCBA,MLB,1.8GHZ,MI 2GB,K21

639-2550

PCBA,MLB,1.7GHZ,HY 2GB,K21

639-2548

K21_CMNPTS,EEEE:DP1L,CPU:1.8GHZ,DDR3:SAMSUNG_4GB

PCBA,MLB,1.8GHZ,SA 4GB,K21

639-2557

K21_CMNPTS,EEEE:DP1K,CPU:1.8GHZ,DDR3:HYNIX_4GB

PCBA,MLB,1.8GHZ,HY 4GB,K21

639-2555

K21_CMNPTS,EEEE:DP1J,CPU:1.7GHZ,DDR3:ELPIDA_4GB

639-2549

K21_CMNPTS,EEEE:DP1H,CPU:1.8GHZ,DDR3:ELPIDA_4GB

639-2558

639-2554

PCBA,MLB,1.8GHZ,HY 2GB,K21

639-2553

085-2684

K21_DEVEL:ENG

607-8041

CMN PTS,PCBA,MLB,K21

1

DEVEL

CRITICAL085-2684

K21 MLB DEVELOPMENT

DEVEL_BOM

1

CRITICAL607-8041

CMN PTS,PCBA,MLB,K21

CMNPTS

K21_CMNPTS

825-7563

1

CRITICAL

825-7563 CRITICAL

1

LABEL,LIO,K99

825-7563

1

CRITICAL

LABEL,LIO,K99

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

Revision History

825-7563

1

CRITICAL

825-7563 CRITICAL

1

825-7563

1

CRITICAL

1

CRITICAL

825-7563 CRITICAL

1

CRITICAL

825-7563

1

CRITICAL

LABEL,LIO,K99

825-7563

1

CRITICAL

LABEL,LIO,K99

4 OF 109

3.13.0

051-8870

4 OF 75

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DRAM CFG CHART

CFG 3

DIE REV

CFG 0CFG 1

00

CFG 2

1

0

1

0

SAMSUNG

VENDOR

SIZE

HYNIX

ELPIDA

MICRON

1

0

B

A

1

0

4GB

2GB

Programmable Parts

K21 BOM GROUPS

Alternate Parts

Module Parts

PD Module Parts

Murata alt to Taiyo Yuden

138S0648138S0703

ALL

376S0874

FDMC0202S alt to RJK03E0DNS

ALL

Old J9400 alt to New J9400

377S0066

Rohm alt to Toshiba

371S0679 371S0652

138S0691

128S0333

152S1462

104S0035

ALL

Sanyo alt for Sanyo/Frederick

376S0612

Diodes alt to Toshiba

K21_DEVEL:PVT

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT

DEVEL_BOM,SMC_DEBUG_YES,XDP

LPCPLUS,XDP_CONN,XDP_PCH

ALTERNATE,COMMON,K21_MISC,K21_DEBUG:ENG,K21_PROGPARTS,USBHUB_2513B,T29BST:Y,EDP,PCH:B3

DDR3:ELPIDA_4GB

338S0895

1

U4900

CRITICAL

335S0809

1

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix

U6100

BOOTROM_BLANK

CRITICAL

U9330

1

CRITICAL341T0353

341T0352 CRITICAL

U3690

T29ROM:PROG

1

IC,T29-ROM,K21

377S0107

ALL

376S0972

ALL

T29MCU:BLANK

U9330

1

337S3997

U6100

BOOTROM_PROG

CRITICAL

1

341T0349

IC,EFI ROM,K21 K78

ALL

138S0676

1

T29ROM:BLANK

CRITICAL335S0550

U4900

CRITICAL

1

341T0348

SMC_PROG

CRITICAL335S0803

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx

U6100

BOOTROM_BLANK

1

376S0855

ALL

DDR3:MICRON_2GB

K21_MISC

K21_DEVEL:ENG

K21_DEBUG:ENG

K21_DEBUG:PVT

K21_COMMON

BOM Configuration

SYNC_DATE=05/28/2009

SYNC_MASTER=K17_REF

138S0679

ALL

337S4100

337S4101

ALL

Taiyo alt to Murata

K21_PROGPARTS

BOOTROM_PROG,SMC_PROG,T29ROM:PROG,T29MCU:PROG

Murata/Samsung to Taiyo

IC,T29-MCU,K21

IC,EEPROM,SERIAL,SPI,1Kx8,1.8V,MLP8,LF

K21_DEBUG:PROD

DDR3:SAMSUNG_4GB

ALL

DDR3:HYNIX_2GB

337S4093

353S3312

NXP alt to Pericom

ALL

TI alt to Fairchild

376S0790 376S0928

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_2GB

CPUMEM_S0,HUB1_2NONREM,HUB2_2NONREM,T29:YES,SDRVI2C:MCU,SDRV_PD,KB_BL

Murata alt to Samsung

337S4092

353S3055

ALL

152S1295

Toko alt for NEC inductor

152S1307

Toko alt for Cyntec

104S0011

Panasonic alt to Cyntec

ALL

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

376S0977

ALL

Diodes alt to Toshiba

ONsemi alt to Semtech

NXP alt to NXP

138S0678

152S1085

SMC_BLANK

138S0673

ALL

DRAM_CFG0:H,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:ELPIDA_4GB

DRAM_CFG0:H,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:MICRON_2GB

U3690

BKLT:ENG,BMON:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,VREFMRGN,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

BKLT:PROD,BMON:PROD,SMC_DEBUG_YES,XDP,VREFMRGN_NOT,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

U1000

1

CRITICAL

U1000

376S0613

376S0859

138S0671

514-0744 998-3941

376S0895

Murata alt to Taiyo Yuden

138S0660

338S0923

SMSC USX2061 alt to USB2513B

ALL

152S1300

Coilcraft alt to Murata

ALL

152S1493

138S0684

338S0721

ALL

128S0294

CRITICAL

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:HYNIX_4GB

DDR3:HYNIX_4GB

DDR3:SAMSUNG_2GB

EARLY 1.5GHZ CPU SAMPLES

EARLY 1.4GHZ CPU SAMPLES

ALL

CRITICAL

CPU:1.7GHZ

T29MCU:PROG

IC,SMC,K21

IC,SMC,RENESAS,H8S/2117RP,9MM,TLP,HF

SNB,QAYS,QS,J1,1.8,17W,2+2,1.20,4M,BGA

SNB,QAYM,QS,J1,1.7,17W,2+2,1.20,3M,BGA

CPU:1.5GHZ

1

CRITICAL

SNB,QAM1,QS,J1,1.6,17W,2+2,1.1,4M,BGA

U1000

CRITICAL

U1000

1

CRITICAL

SNB,QALV,QS,J1,1.3,17W,2+2,1.05,3M,BGA

CPU:1.3GHZ

CRITICAL

U1000

1

CRITICAL

T29:YES

U3600

1

338S0976

U1800

1

PCH:B3

337S4091

1

U1800

PCH:B2

DRAM_TYPE:HYNIX_2GB

CRITICAL

U2900,U2910,U2920,U2930

333S0585

4

333S0585

CRITICAL

DRAM_TYPE:HYNIX_2GB

U3000,U3010,U3020,U3030

4

CRITICAL

DRAM_TYPE:HYNIX_2GB

333S0585

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,T-DIE,HYNIX

U3100,U3110,U3120,U3130

4

CRITICAL

333S0585

DRAM_TYPE:HYNIX_2GB

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

U3200,U3210,U3220,U3230

4

CRITICAL

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

4

333S0586

DRAM_TYPE:HYNIX_4GB

U3000,U3010,U3020,U3030

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

333S0586

CRITICAL

DRAM_TYPE:HYNIX_4GB

U2900,U2910,U2920,U2930

4

CRITICAL

4

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,B-DIE,HYNIX

333S0586

DRAM_TYPE:HYNIX_4GB

U3100,U3110,U3120,U3130

333S0586

4

CRITICAL

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,B-DIE,HYNIX

DRAM_TYPE:HYNIX_4GB

U3200,U3210,U3220,U3230

4

CRITICAL

U2900,U2910,U2920,U2930

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_2GB

333S0587

U3000,U3010,U3020,U3030

4

333S0587

CRITICAL

DRAM_TYPE:SAMSUNG_2GB

U3100,U3110,U3120,U3130

4

CRITICAL

333S0587

DRAM_TYPE:SAMSUNG_2GB

U2900,U2910,U2920,U2930

4

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

333S0588

CRITICAL

4

CRITICAL

DRAM_TYPE:SAMSUNG_2GB

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

U3200,U3210,U3220,U3230

CRITICAL

4

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

DRAM_TYPE:SAMSUNG_4GB

333S0588

U3000,U3010,U3020,U3030

CRITICAL

4

DRAM_TYPE:SAMSUNG_4GB

333S0588

U3200,U3210,U3220,U3230

4

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,D-DIE,SAMSUNG

333S0588

DRAM_TYPE:SAMSUNG_4GB

CRITICAL

U3100,U3110,U3120,U3130

CRITICAL

4

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

DRAM_TYPE:MICRON_2GB

U2900,U2910,U2920,U2930

333S0590

U3000,U3010,U3020,U3030

CRITICAL

4

DRAM_TYPE:MICRON_2GB

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

CRITICAL

4

DRAM_TYPE:MICRON_2GB

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,V68A-D,MICRON

U3200,U3210,U3220,U3230

U3100,U3110,U3120,U3130

CRITICAL

4

DRAM_TYPE:MICRON_2GB

333S0590

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,V68A-D,MICRON

4

DRAM_TYPE:ELPIDA_4GB

CRITICAL

333S0589

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

U2900,U2910,U2920,U2930

353s2929

U7000

IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28

1

CRITICAL

333S0589

4

IC,SDRAM,2GBIT,DDR3-1333,78P FGBA,C-DIE,ELPIDA

U3100,U3110,U3120,U3130

CRITICAL

DRAM_TYPE:ELPIDA_4GB

333S0589

4

DRAM_TYPE:ELPIDA_4GB

CRITICAL

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

U3000,U3010,U3020,U3030

333S0589

4

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,C-DIE,ELPIDA

U3200,U3210,U3220,U3230

CRITICAL

DRAM_TYPE:ELPIDA_4GB

T29FENCE

K21, T29 Fence

1

CRITICAL

806-2333

MDPSPRING

1

NOSTUFF

K78, mDP Spring

CRITICAL

806-2377

T29CAN

806-2356

NOSTUFF

K21, T29 Can

1

CRITICAL

MDPCAN

K78, mDP Can

1

CRITICAL

806-2376

T29FILTERCAN

K21, T29 Filter Can

1

CRITICAL

806-2347

IC,SDRAM,2GBIT,DDR3-1333,78P FBGA,D-DIE,SAMSUNG

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,G-DIE,SAMSUNG

COUGAR POINT,SLHAG,PRQ,BD82QS67

IC,SDRAM,1GBIT,DDR3-1333,78P FBGA,T-DIE,HYNIX

IC,T29 Eagle Ridge,192 FCBGA,8x9MM

337S4080

337S4098

COUGAR POINT,B3,SLJ4K,PRQ,BD82QS67

337S4099

SNB,QAM3,QS,J1,1.4,17W,2+2,1.05,3M,BGA

337S4100

337S4101

DRAM_CFG0:L,DRAM_CFG1:L,DRAM_CFG2:L,DRAM_CFG3:L,DRAM_TYPE:HYNIX_2GB

DRAM_CFG0:L,DRAM_CFG1:H,DRAM_CFG2:H,DRAM_CFG3:L,DRAM_TYPE:SAMSUNG_4GB

IC,SDRAM,1GBIT,DDR3-1333,78P FGBA,G-DIE,SAMSUNG

333S0587

CRITICAL

CPU:1.4GHZ

CPU:1.8GHZ

CPU:1.6GHZ

U1000

SNB,QAM2,QS,J1,1.5,17W,2+2,1.1,4M,BGA

337S4121

337S4119

1

5 OF 109

3.13.0

051-8870

5 OF 75

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

(Need to add 8 GND TPs)

(Need to add 5 GND TPs)

(Need to add 3 GND TPs)

J6903: Speaker Connector

(Need to add 27 GND TPs)

FUNC_TEST

Misc Voltages & Control Signals

(Need to add 5 GND TPs)

(Need to add 4 GND TPs near J6950 and 1 for shield)

J9000: Internal DP Connector

J6950: Battery Connector

(Need to add 6 GND TPs)

(Need to add 2 GND TP)

J5715: KB BKLT CONNECTOR

FUNC_TEST

J5600: Fan Connector

(Need to add 1 GND TP)

FUNC_TEST

(Need to add 5 GND TPs)

J5700: IPD Flex Connector

J5100: LPC+SPI Connector

(Need to add 2 GND TPs)

J4700: LIO Connector

J6900: DC-In Connector

NO_TEST Nets

(Need 4 TPs)

(Need to add 6 GND TPs)

(Need 2 TPs)

J4800: SD Card Connector

(Need to add 5 GND TPs)

FUNC_TEST

(Need 5 TPs)

J4001: AirPort / BT Connector

FUNC_TEST

(Need 6 TPs)

FUNC_TEST

J4501: SATA SSD Connector

(Need 2 TPs) (Need 2 TPs)

FUNC_TEST

Functional Test Points

NO_TEST

FUNC_TEST

(Need 5 TPs)

I499

I500

I501

I502

I503

I504

I505

I506

I566

I567

I568

I569

I570

I571

I592

I593

I594

I595

I596

I597

I598

I599

I600

I601

I602

I623

I624

I626

I627

I628

I629

I630

I631

I632

I633

I634

I635

I636

I637

I638

I639

I640

I641

I642

I643

I644

I645

I646

I647

I648

I649

I650

I651

I652

I653

I654

I655

I656

I657

Functional Test / No Test

SYNC_MASTER=(K99_MLB)

SYNC_DATE=(02/16/2010)

SPKRAMP_R_N_OUT

TRUE

PP1V5_S3_CPU_VCCDQ

TRUE

PP1V8_S0_CPU_VCCPLL_R

TRUE

PP1V05_S0_CPU_VCCPQE

TRUE

PPVCORE_S0_AXG

TRUE

PPVCORE_S0_CPU

TRUE

PP1V05_S0_PCH_VCCADPLL

TRUE

PP1V05_T29

TRUE

PP15V_T29

TRUE

PP3V3_T29

TRUE

PPVCCSA_S0_CPU

TRUE

PP1V05_SUS

TRUE

PP0V75_S0_DDRVTT

TRUE

PPVTTDDR_S3

TRUE

PP1V05_S0

TRUE

PP1V5_S0

PP1V5_S3RS0

TRUE

PP1V5_S3

TRUE

PP1V8_S0

TRUE

PP3V3_S0

TRUE

PP3V3_SUS

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP5V_SUS

TRUE

PP5V_S5

TRUE

PPVRTC_G3H

TRUE

PP3V42_G3H

TRUE

PPDCIN_G3H

TRUE

PPBUS_S5_HS_COMPUTING_ISNS

TRUE

PPVIN_SW_T29BST

TRUE

PPBUS_G3H

TRUE

SPI_ALT_MOSI

TRUE

DP_INT_HPD_CONN

TRUE

DP_INT_AUX_CH_C_N DP_INT_AUX_CH_C_P

TRUE

=SMBUS_BATT_SCL

TRUE

=SMBUS_BATT_SDA

TRUE

SYS_DETECT_L

PPVBAT_G3H_CONN

TRUE

I2C_TCON_SDA_R

TRUE

PP3V3_SW_LCD

TRUE

SPKRAMP_R_P_OUT

TRUE

=I2C_LIO_SCL

HDA_BIT_CLK

TRUE

USB_CAMERA_P

TRUE

USB_CAMERA_N

TRUE

USB_EXTD_P

TRUE

USB_EXTD_N

TRUE

HDA_RST_L

TRUE

USB_EXTD_OC_L

HDA_SDIN0

TRUE

AUD_I2C_INT_L

TRUE

SMC_HDD_TEMP_CTL_CONN

TRUE

=PP3V3_S0_AUDIO

TRUE

DP_INT_ML_F_P<1> DP_INT_ML_F_N<1>

TRUE

DP_INT_ML_F_N<0>

DP_INT_ML_F_P<0>

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

LED_RETURN_4

TP_PCI_PME_L

TP_PCI_CLK33M_OUT3

TRUE

KBDLED_ANODE

TRUE

KBDLED_FB

FAN_RT_PWM

TRUE

=PP5V_S0_FAN

TRUE

FAN_RT_TACH

PP3V3_TPAD_CONN

TRUE

SMC_PME_S4_WAKE_L

SMC_LID

TRUE

SMC_TPAD_RST_L

TRUE

SMC_ONOFF_L

TRUE

=I2C_TPAD_SCL

TRUE

=I2C_TPAD_SDA

TRUE

USB_TPAD_CONN_N

TRUE

USB_TPAD_CONN_P

TRUE

=PP3V42_G3H_TPAD

TRUE

PP5V_TPAD_FILT

TRUE

PP3V3_SW_SD_PWR

TRUE

SD_CLK

TRUE

SD_CMD

TRUE

SD_D<7..0>

SD_WP

TRUE

SD_CD_L

TRUE

=PP5V_S0_LPCPLUS

TRUE

=PP3V3_S5_LPCPLUS

TRUE

LPC_AD<3..0>

TRUE

HDA_SYNC

NC_PEG_D2RP<15..4>

MAKE_BASE=TRUE

TRUE

SPKRAMP_INR_P

TRUE

=USB_PWR_EN

TRUE

=I2C_LIO_SDA

NC_CPU_RSVD<8..27>

MAKE_BASE=TRUE

TRUE

NC_PEG_R2D_CP<15..4>

MAKE_BASE=TRUE

=PEG_R2D_C_N<15..4>

=PEG_D2R_P<15..4>

NC_PEG_R2D_CN<15..4>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PEG_D2RN<15..4>

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5N

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5P

TRUE

=I2C_MIKEY_SCL

SMC_LID

TRUE

=PP5V_S3_LIO_CONN

TP_CPU_RSVD<8..27>

TRUE

MAKE_BASE=TRUE

NC_CPU_RSVD<30..45>

NC_CPU_THERMDA

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_EDP_AUXP

TRUE

NC_EDP_AUXN

MAKE_BASE=TRUE

TRUE

=PEG_D2R_N<15..4>

NC_PCI_CLK33M_OUT3

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PEBP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PEBN

MAKE_BASE=TRUE

TRUE

NC_CLINK_DATA

TRUE

MAKE_BASE=TRUE

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

NC_CLINK_CLK

TRUE

MAKE_BASE=TRUE

TRUE

NC_CLINK_RESET_L

NC_HDA_SDIN2

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN3

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCH_LVDS_VBG

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_CLK

TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_GREEN

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_BLUE

NC_CRT_IG_RED

MAKE_BASE=TRUE

TRUE

XDP_PCH_USB_HUB_SOFT_RST_L

TRUE

XDP_PCH_AP_PWR_EN

TRUE

XDP_PCH_SDCONN_STATE_RST_L

TRUE

XDP_PCH_ENET_PWR_EN

TRUE

XDP_PCH_SDCONN_DET_L

TRUE

XDP_PCH_S5_PWRGD

TRUE

XDP_PCH_ISOLATE_CPU_MEM_L

TRUE

XDP_PCH_PWRBTN_L

TRUE

XDP_FW_CLKREQ_L

TRUE

XDP_PCH_AUD_IPHS_SWITCH_EN

TRUE

XDP_AP_CLKREQ_L

NC_SDVO_INTN

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINN

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINP

TRUE MAKE_BASE=TRUE

NC_SDVO_INTP

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLP

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_D<0..1>

MAKE_BASE=TRUE

TRUE

NC_TP_XDPPCH_HOOK3

MAKE_BASE=TRUE

TRUE

NC_TP_XDP_PCH_OBSFN_B<0..1>

TRUE MAKE_BASE=TRUE

NC_TP_XDPPCH_HOOK2

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_A<0..1>

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_HOOK4

TRUE MAKE_BASE=TRUE

NC_TP_XDP_PCH_HOOK5

NC_PCH_GPIO64_CLKOUTFLEX0

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE MAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

MAKE_BASE=TRUE

TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

MAKE_BASE=TRUE

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<2>

TRUE

PCH_VSS_NCTF<5>

TRUE

PCH_VSS_NCTF<1>

NC_SMC_BS_ALRT_L

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_BKL_PWM

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKP

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

TRUE

PCH_VSS_NCTF<29>

TRUE

PCH_VSS_NCTF<27>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<17>

TRUE

MAKE_BASE=TRUE

NC_PCH_TP1

NC_PCH_TP2

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_TP3

NC_PCH_TP4

TRUE

MAKE_BASE=TRUE

PCH_VSS_NCTF<15>

TRUE

NC_PCH_TP5

TRUE

MAKE_BASE=TRUE

NC_PCH_TP6

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

MAKE_BASE=TRUE

TRUE

NC_PCH_TP8

MAKE_BASE=TRUE

TRUE

NC_PCH_TP9

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_PCH_TP12

MAKE_BASE=TRUE

TRUE

NC_PCH_TP13

MAKE_BASE=TRUE

NC_PCH_TP14

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP15

MAKE_BASE=TRUE

TRUE

NC_PCH_TP16

MAKE_BASE=TRUE

TRUE

NC_PCH_TP18

MAKE_BASE=TRUE

TRUE

NC_PCH_TP17

MAKE_BASE=TRUE

TRUE

NC_SATA_E_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_R2D_CN

NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RP

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RN

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CN

NC_SATA_D_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_B_D2RP

TRUE MAKE_BASE=TRUE

NC_SATA_B_D2RN

TRUE

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE7P

NC_SATA_B_R2D_CN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N

TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6N

NC_CPU_THERMDC

MAKE_BASE=TRUE

TRUE

NC_EDP_TXN<0..3>

MAKE_BASE=TRUE

TRUE

NC_EDP_TXP<0..3>

MAKE_BASE=TRUE

TRUE

USB_BT_N

TRUE

USB_BT_P

TRUE

PP3V3_WLAN_F

TRUE

WIFI_EVENT_L

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_AP_R2D_P

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_N

TRUE

AP_RESET_CONN_L

TRUE

AP_CLKREQ_Q_L

TRUE

=PP3V3_S3_BT

TRUE

LPC_FRAME_L

TRUE

SPI_ALT_MISO

TRUE

SMC_TMS

TRUE

PM_CLKRUN_L

TRUE

LPCPLUS_RESET_L

TRUE

SMC_TDO

TRUE

SMC_TRST_L

TRUE

SMC_TX_L

TRUE

SMC_MD1

TRUE

LPC_CLK33M_LPCPLUS

TRUE

SPIROM_USE_MLB

TRUE

SPI_ALT_CLK

TRUE

LPC_SERIRQ

TRUE

SPI_ALT_CS_L

TRUE

LPC_PWRDWN_L

TRUE

SMC_TCK

TRUE

SMC_TDI

TRUE

SMC_RESET_L

TRUE

SMC_RX_L

TRUE

SMC_NMI

TRUE

LPCPLUS_GPIO

TRUE

AUD_IP_PERIPHERAL_DET

TRUE

AUD_IPHS_SWITCH_EN

TRUE

SPKRAMP_INR_N

TRUE

AUD_GPIO_3

HDA_SDOUT

TRUE

SMC_BC_ACOK

TRUE

SYS_ONEWIRE

TRUE

=PP3V3R1V5_S0_AUDIO

PP3V3_S0_HDD_R

TRUE

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_R2D_N

TRUE

SMC_HDD_OOB_TEMP_CONN

TP_EDP_TX_P<0..3>

TP_EDP_AUX_P

TP_EDP_TX_N<0..3>

TP_CPU_THERMDA

TP_EDP_AUX_N

TP_CPU_THERMDC

TP_CPU_RSVD<30..45>

=PEG_R2D_C_P<15..4>

TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE7N

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

TP_SATA_B_R2D_CN

TP_PCIE_CLK100M_PE7P

TP_PSOC_P1_3

TP_SATA_B_D2RN

TP_SATA_B_D2RP

TP_SATA_B_R2D_CP

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_D_D2RP

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RP

TP_SATA_E_D2RN

TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

TP_PCH_TP17

TP_PCH_TP18

TP_PCH_TP16

TP_PCH_TP15

TP_PCH_TP14

TP_PCH_TP13

TP_PCH_TP12

TP_PCH_TP10

TP_PCH_TP9

TP_PCH_TP8

TP_PCH_TP7

TP_PCH_TP6

TP_PCH_TP5

TP_PCH_TP4

TP_PCH_TP3

TP_PCH_TP2

TP_PCH_TP1

TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_BKL_PWM

SMC_BS_ALRT_L

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO64_CLKOUTFLEX0

TP_XDP_PCH_HOOK5

TP_XDP_PCH_HOOK4

TP_XDP_PCH_OBSFN_A<0..1>

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_D<0..1>

TP_SDVO_STALLP

TP_SDVO_INTN

TP_SDVO_INTP

TP_SDVO_STALLN

TP_SDVO_TVCLKINN

TP_SDVO_TVCLKINP

TP_CRT_IG_BLUE

TP_CRT_IG_DDC_DATA

TP_LVDS_IG_CTRL_DATA

TP_HDA_SDIN3

TP_CRT_IG_HSYNC

TP_CLINK_CLK

TP_CLINK_DATA

TP_PCIE_CLK100M_PEBN

TP_PCIE_CLK100M_PEBP

TP_CLINK_RESET_L

TP_HDA_SDIN2

TP_HDA_SDIN1

TP_PCH_LVDS_VBG

TP_LVDS_IG_CTRL_CLK

TP_CRT_IG_VSYNC

TP_CRT_IG_DDC_CLK

TP_CRT_IG_RED

TP_CRT_IG_GREEN

=PP18V5_DCIN_CONN

TRUE

=I2C_MIKEY_SDA

TRUE

=PP3V42_G3H_ONEWIRE

SATA_HDD_R2D_P

TRUE

PPVOUT_SW_LCDBKLT

TRUE

I2C_TCON_SCL_R

TRUE

LED_RETURN_5

SATA_HDD_D2R_C_N

TRUE

LED_RETURN_6

TRUE

LED_RETURN_1

PCIE_WAKE_L

TRUE

7 OF 109

3.13.0

051-8870

6 OF 75

70

74 52 51

7

36

7

68

7

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7

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7

74

7

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52

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43

63

70 63

52 44

52

53 52

63

74 52 51

44 40

70 40 16

69 40 18

69 40 24

70 40 16

40 24

70 40 16

40 18

38

40

7

70 63

66 63

66 63 18

18

49

48

7

48

49

49 42 41

49 42 41 40

6

49 42

49 42 41

49 44

74 49

49

7

49

33

43

7

43

7

70 43 41 16

70 40 16

74 51 40

62 40 39

44 40

9

44 40

49 42 41 40

6

52

7

9

23

70

6

70

69 37 24

37

41 37

70 37

70 37 16

37

7

70 43 41 16

43

43 42 41

43 41 17

43 25

43 42 41

43 41

43 42 41 39

43 41

70 43 25

50 43 19

43

43 41 16

43

43 41 17

43 42 41

53 43 42 41

43 42 41 39

43 41

43 19

40 18

40 19

74 51 40

51 40

70 40 16

42 41 40

41 40

40

7

38

69 38

38

9

16

8

16

23

17

16

17

16

17

52

7

44 40

40

7

69 38

66 63

63

66 63

69 38

66 63

37 17

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

1.8V/1.5V/1.2V/1.05V Rails

5V Rails

3.3V Rails

1V05 S0 LDO

Chipset "VCore" Rails

? mA

2A max supply

"G3Hot" (Always-Present) Rails

T29 Rails (off when no cable)

SYNC_DATE=05/15/2010

Power Aliases

SYNC_MASTER=K91_MLB

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

PP1V8_S0

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_S0

MIN_LINE_WIDTH=0.5 MM

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_DP_DDC =PP3V3_S0_FAN

=PP3V3_S0_P3V3T29FET

=PP3V3_S0_PCH

=PP3V3_S0_P1V8S0

=PP3V3_S0_CPU_VCCIO_SEL

=PP3V3_S0_AUDIO

=PP3V3_S0_HS_COMPUTING_ISNS

=PP3V3_S0_PCH_VCC3_3_CLK

=PP3V3_S0_PCH_VCC3_3_HVCMOS =PP3V3_S0_PCH_VCC3_3_PCI =PP3V3_S0_PCH_VCC3_3_SATA =PP3V3_S0_PCH_VCCADAC =PP3V3_S0_PCH_STRAPS =PP3V3_S0_PWRCTL

=PP3V3_S0_FET

=PP3V3_S0_CPUVCCIOISNS

=PP3V3_S3_WLAN

=PP3V3_S3_SMBUS_SMC_MGMT

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP3V3_S3

=PP3V3_S3_BT =PP3V3_S3_CARDREADER =PP3V3_S3_MEMRESET =PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_WLANISNS

=PP3V3_S3_1V5S3ISNS =PP3V3_S3_DBGLEDS

=PP3V42_G3H_TPAD

=PP3V3_S5_LPCPLUS

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PPDCIN_G3H

MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V

MIN_LINE_WIDTH=2 mm

VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S0

MIN_NECK_WIDTH=0.17 mm

=PPVTT_S3_DDR_BUF

=PP3V42_G3H_SMBUS_SMC_BSA

=PP1V5_S3RS0_VMON

=PP3V3R1V5_S0_AUDIO

=PP1V8_S0_REG

=PP1V8_S0_CPU_VCCPLL

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

=PP3V3_S3_PCH_GPIO

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_T29

VOLTAGE=1.05V

=PP1V8_S0_PCH_VCC_DFTERM =PP1V8_S0_P1V05S0LDO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V

PP0V75_S0_DDRVTT

=PP0V75_S0_MEM_VTT_B

=PPVCCSA_S0_CPU

PP1V05_SUS

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_P1V05T29FET

=PPVCCIO_S0_SMC

=PPVCCIO_S0_XDP

=PP1V05_S0_PCH_VCCIO_PLLUSB

=PP1V05_S0_PCH_V_PROC_IO

=PPVCCIO_S0_CPUIMVP

=PP1V05_S0_PCH_VCC_CORE

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_SUS

MIN_LINE_WIDTH=0.50MM

=PP3V42_G3H_SMCUSBMUX

=PP3V3_S4_SMC

=PP3V3_S3_BMON_ISNS

=PP3V3_S3_VREFMRGN

=PP3V3_S5_PCH_VCCDSW =PP3V3_S5_SYSCLK =PP3V3_S5_VMON =PP3V3_S5_PWRCTL =PP3V3_S5_PCH_VCC_SPI =PP3V3_S5_P3V3SUSFET

=PP3V3_SUS_SMC

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_SUS_PCH =PP3V3_SUS_PWRCTL

=PP3V3_S3_FET

=PP3V3_S0_P1V05S0LDO =PP3V3_S0_IMVPISNS =PP3V3_S0_XDP =PP3V3_S0_T29I2C

=PP3V3_S0_SYSCLKGEN

=PP3V3_S0_BKLTISNS

=PP3V42_G3H_CHGR

=PP3V3_S5_SMC

=PP3V42_G3H_PWRCTL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP3V42_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

=PP3V42_G3H_ONEWIRE

=PPVBAT_G3_SYSCLK

=PPVIN_S5_SMCVREF

=PP5V_SUS_PCH

=PP5V_SUS_FET

=PP5V_S5_TPAD

=PP5V_S5_LDO

=PP5V_S5_P5VSUSFET

=PP5V_S5_P1V5DDRFET

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP5V_SUS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP5V_S5

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP5V_S0

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=5V

=PP5V_S0_BKL =PP5V_S0_CPUIMVP =PP5V_S0_CPUVCCIOS0 =PP5V_S0_FAN

=PP5V_S0_VCCSA

=PP5V_S0_LPCPLUS

=PP5V_S0_PCH =PP5V_S0_VMON =PP5V_S0_KBDLED

=PP5V_S3_LIO_CONN

=PP5V_S3_MEMRESET

=PP5V_S3_P5VS0FET

=PP5V_S3_RTUSB

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

=PP5V_S3_AUDIO_AMP

=PP5V_S3_DDRREG

=PP5V_S0_FET

=PP5V_S3_REG

=PP3V3_S5_TPAD =PP3V3_S4_DPAPWRSW

=PP3V3_S5_ROM =PP3V3_S5_USB_RESET

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_PCH

=PP3V3_S5_LCD

=PP3V3_S0_P3V3S0FET

=PP3V3_S5_XDP

=PP3V3_S3_P3V3S3FET =PP3V3_S5_CPU_VCCDDR

=PP1V05_SUS_LDO

VOLTAGE=17.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

PP15V_T29

=PPHV_SW_DPAPWRSW

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLL

=PPVDDIO_T29_CLK

=PPVCORE_S0_CPU_REG

PP1V8_S0_CPU_VCCPLL_R

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0_CPU_VCCPQE

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PPVCORE_S0_AXG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.25V MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_T29

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PPVIN_SW_T29BST

VOLTAGE=12.8V

PPVCCSA_S0_CPU

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=0.9V

PPBUS_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

VOLTAGE=12.8V

=PPDCIN_S5_VSENSE

=PPDCIN_S5_CHGR

=PPVIN_S0_CPUAXG

=PPVIN_S0_VCCSAS0

=PPVIN_S0_CPUVCCIOS0

=PPVIN_S3_DDRREG

=PPVIN_S5_HS_COMPUTING_ISNS

=PP3V42_G3H_REG

=PP3V3_S5_REG

=PPVCCSA_S0_REG

=PPVTT_S0_DDR_LDO

=PPBUS_G3H

=PPCPUVCCIO_S0_REG

=PP1V05_SUS_PCH_JTAG

=PPVTT_S0_VTTCLAMP

=PP0V75_S0_MEM_VTT_A

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PP1V05_S0_PCH_VCCIO_PLLPCIE

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_PCH =PP1V05_S0_PCH_VCCIO =PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_VMON =PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_VCCIO_PLLFDI

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_VCCDMI_FDI

=PP15V_T29_REG

=PP3V3_T29_RTR =PP3V3_T29_PCH_GPIO

=PP3V3_T29_FET

=PP1V05_T29_RTR

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_LDO

=PPCPUVCORE_S0_VSENSE

=PPVCORE_S0_CPU

=PPVCORE_S0_AXG_REG

=PPVCORE_S0_CPU_VCCAXG =PPGFXVCORE_S0_VSENSE

=PP1V5_S3_CPU_VCCDQ

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_PCH_VCCDIFFCLK

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.6 mm

=PPVIN_S5_P5VP3V3

=PP1V05_T29_FET

=PP1V8R1V5_S0_PCH_VCCVRM

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.8 MM MIN_NECK_WIDTH=0.1 MM

PP1V5_S3

MIN_NECK_WIDTH=0.2 MM

PP1V5_S3RS0

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

=PPDDR_S3_REG

=PP1V5_S3_MEMRESET =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B

=PP1V5_S3RS0_FET

=PPVDDIO_S0_SBCLK

=PP18V5_DCIN_CONN

=PPVIN_S0_CPUIMVP

=PP1V5_S3_P1V5S3RS0_FET =PPVIN_S0_DDRREG_LDO

=PP3V3_S3_USB_RESET

PPVRTC_G3H

VOLTAGE=3V

MIN_LINE_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCASW

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.05V MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCIO_SATA

=PPVRTC_G3_PCH

=PPVRTC_G3_OUT

=PP3V3_S3_USB_HUB

=PP1V8_S0_P1V5S0

=PP3V3_SUS_GPIO

=PP3V3_SUS_PCH_VCCSUS_USB =PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_FET

=PPBUS_S0_LCDBKLT =PPBUS_S0_VSENSE =PPVIN_SW_T29BST

=PP1V5_S3_CPU_VCCDDR

=PP1V5_S0_REG

MAKE_BASE=TRUE

PPVTTDDR_S3

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_RSTBUF =PP3V3_S0_SB_PM

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_PCH =PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_HDD

=PP3V3_S0_SMC

=PP3V3_S0_HDDISNS

=PP3V3_S0_P1V5S0

=PP3V3_S0_VMON

=PP3V3_S0_DPSDRVA

=PP3V3_S0_T29PWRCTL

8 OF 109

3.13.0

051-8870

7 OF 75

6

74

6

66

47

8

48

36

22 19 16

60

12

40

6

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22

22 20

22

19 17 16

62

61

45

37

44

6

37

6

33

26

44

46

52

49

6

43

6

56 31

44

62

40

6

60

14

74

6

19 18

36

6

22 20 18

60

22 20 16

6

32

15 12

6

36

41

23

20

22 20

57

22 20

6

39

42

46

31

22 20

25

62

22 20

61

42

60

20

22

62

61

60

45

23

44

25

46

53

42 41

62

6

40

6

25

42

22

61

49

55

61

6

66

57

59

48

6

54

43

6

22

62

49

52

6

26

61

39

51

56

61

55

49

65

50

24

42

25

19 17

63

61

23

61

26

60

6

65

6

25

58

6

36

6

45

53

58

54

59

56

46

52

55

54

56

53

59

23

26

32

46

20

14 12 10

9

22 16

22 20

17

22 20

62

22 20

20

22 20

20

36

8

36 35 34

19 16

36

35

20

60

45

14 12

9

58

15 12

9

45

15 12

14 12

22 20 16

52

6

55

36

20

68

6

68

6

56

26

32 28 27

32 30 29

61

25

52

6

58 57

61

56

24

6

22 20

6

22 20 16

20 17 16

25

24

8

60

19 18 17 16

22 20

61

66

45

36

8

26 15 12 10

60

6

18

22 20

25

44

38

42

46

60

62

64

36

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

SSD Boss

DisplayPort Pogo

(Provides PCB support for small finger above J9400)

T29 JTAG

Unused PGOOD signal

USB/SD Card Pogo

X21 Boss

T29 DP Ports

4x 860-1327

870-1938

Fan Boss

860-1327860-1327

870-1938

806-1176

Digital Ground

Plated Board Slot

T29_A_BIAS caps

Unused USB ports

T29_A_BIAS caps

860-1327

LVDS Aliases

CPU signals

CPU Heat Sink Mounting Bosses

Unused SATA ODD Signals

SATA Aliases

DP_A_BIAS caps

T29 Aliases

T29 Can Slots

EMI I/O Pogo Pins

DisplayPort PCB Stiffener

61

56

34

23 19

19

201

1/20W

MF

5%

0

NO STUFF

5%

NO STUFF

0

MF

1/20W

201

69 16

74 46

STDOFF-4.5OD1.8H-SM

SL-2.3X3.9-2.9X4.5

TH-NSP

STDOFF-4.5OD1.8H-SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

SM

STDOFF-4.5OD1.8H-SM

POGO-2.0OD-3.6H-K86-K87

CRITICAL

SM

STIFFENER-K16-K99

NO STUFF

SM-SP

201

10V

10%

X5R

0.01UF

10%

0.01UF

X5R

10V

201

5%

1/8W

805

MF-LF

0

T29BST:N

201

X5R

10V

10%

0.01UF

201

MF

1/20W

5%

2.2K 2.2K

5%

1/20W

201

MF

1/20W

201

2.2K

5%

MF

5%

201

1/20W

MF

2.2K

201

MF

1/20W

5%

2.2K

201

MF

1/20W

5%

2.2K

1/20W

201

MF

5%

100K

10K

1/20W

5%

MF

201

1/20W

201

MF

5%

10K

X5R

10V

201

0.01UF

10%

SIGNAL_MODEL=EMPTY

MF

1/20W

5%

51

201

SIGNAL_MODEL=EMPTY

SIGNAL_=EMPTY

X5R 201

0.01UF

10% 10V

MF

5%

1/20W

51

SIGNAL_MODEL=EMPTY

201

0.01UF

X5R

10%

201

10V

SIGNAL_MODEL=EMPTYSIGNAL_MODEL=EMPTY

X5R 201

0.01UF

10% 10V

SIGNAL_MODEL=EMPTY

0.01UF

X5R

10% 10V

201

SIGNAL_MODEL=EMPTY

0.01UF

10V

201

10%

X5R

SIGNAL_MODEL=EMPTY

10V

201

10%

X5R

0.01UF

SIGNAL_MODEL=EMPTY

0.01UF

10V

201

10%

X5R

SIGNAL_MODEL=EMPTY

201

MF

1/20W

5%

51

SIGNAL_MODEL=EMPTY

51

5%

1/20W

201

MF

SIGNAL_MODEL=EMPTY

1/20W

5%

51

201

MF

SIGNAL_MODEL=EMPTY

5%

1/20W

MF

51

201

100K

5%

201

MF

1/20W

0612-1

1W MF

0.5%

0.01

CRITICAL

MF

5%

1/20W

201

0

Signal Aliases

SYNC_DATE=05/15/2010

SYNC_MASTER=K91_MLB

GND

JTAG_T29_TCK

JTAG_T29_TCK_R

JTAG_ISP_TCK

MAKE_BASE=TRUE

=PPBUS_SW_BKL

=USB_HUB2_OCS4

MEM_A_CS_L<1>

MEM_A_A<15>

TP_PCH_CLKOUT_DPN

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

P1V5S3RS0_RAMP_DONE

DDRREG_PGOOD

TP_DP_IG_C_HPD

TP_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

DP_T29SNK0_ML_C_N<3..0>

DP_IG_D_HPD

MAKE_BASE=TRUE

TP_DP_IG_C_AUXN

TP_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUE

DP_T29SNK0_ML_C_P<3..0>

TP_DP_IG_D_HPD

DP_T29SNK0_HPD

MAKE_BASE=TRUE

DP_T29SNK0_AUXCH_C_N

MAKE_BASE=TRUE

TP_DP_IG_C_AUXP

MAKE_BASE=TRUE

DP_T29SNK0_AUXCH_C_P

=PEG_R2D_C_N<3..0>

=PP3V3_S0_DP_DDC

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_B_MLP<3..0>

=PEG_D2R_P<3..0>

PEG_R2D_C_N<3..0> PEG_D2R_P<3..0>

DP_IG_B_DDC_DATA

DP_EXTA_DDC_CLK

MAKE_BASE=TRUE

NC_PEG_CLK100MP

T29_A_BIAS_D2RP1

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

PPBUS_SW_BKL

MAKE_BASE=TRUE

DP_EXTA_DDC_DATA

MAKE_BASE=TRUE

=PP3V3_S0_DP_DDC

DP_IG_B_HPD

NC_USB_HUB2_OCS4

MAKE_BASE=TRUE

NC_USB_HUB1_OCS4

MAKE_BASE=TRUE

T29_A_BIAS

=PPVIN_SW_T29BST

TP_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

DP_IG_D_CTRL_CLK

DP_IG_B_DDC_CLK

DP_EXTA_HPD

MAKE_BASE=TRUE

T29_A_BIAS_D2RN1

DP_A_BIAS_P_0DP_A_BIAS_P_2

USB_T29A_N USB_T29A_P

T29_A_RSVD_P

T29_A_RSVD_N

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

JTAG_T29_TDI

JTAG_T29_TDO

T29_A_BIAS_R2DN1

T29_A_BIAS_R

MAKE_BASE=TRUE

DP_IG_C_CTRL_CLK

T29_A_BIAS_R2DN0

T29_A_BIAS_R2DP1

=PP15V_T29_REG

=PP3V3_S3_USB_HUB

JTAG_ISP_TDI

MAKE_BASE=TRUE

JTAG_ISP_TDO

MAKE_BASE=TRUE

T29_A_BIAS_R2DP0

T29_A_BIAS_R

DP_A_BIAS_N_0

LVDS_IG_B_CLK_P

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

LVDS_IG_B_CLK_N

TP_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

LVDS_IG_B_DATA_P<0..3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

LVDS_IG_B_DATA_N<0..3>

NC_LVDS_IG_B_DATAN<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<3>

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_IG_BKL_PWM

LCD_BKLT_PWM

MAKE_BASE=TRUE

LVDS_IG_A_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

LVDS_IG_PANEL_PWR

LCD_IG_PWR_EN

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

LCD_BKLT_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

SATA_ODD_D2R_N

PCIE_T29_R2D_C_P<3..0>

MAKE_BASE=TRUE

PCIE_T29_R2D_C_N<3..0>

MAKE_BASE=TRUE

PEG_R2D_C_P<3..0>

=PEG_R2D_C_P<3..0>

PCIE_T29_D2R_P<3..0>

MAKE_BASE=TRUE

PCIE_T29_D2R_N<3..0>

MAKE_BASE=TRUE

PEG_D2R_N<3..0>

=PEG_D2R_N<3..0>

=DDRVTT_EN

MAKE_BASE=TRUE

MEMVTT_EN

DP_IG_B_AUX_P

DP_IG_B_AUX_N

TP_DP_IG_B_MLN<3..0>

DP_IG_ML_P<3..0>

DP_EXTA_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_IG_ML_N<3..0>

DP_EXTA_ML_C_N<3..0>

MAKE_BASE=TRUE

DP_EXTA_AUXCH_C_P

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2RP

PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

NC_PCIE_EXCARD_D2RN

TRUE

PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

NC_MEM_A_CS_L<1>

MAKE_BASE=TRUE

NC_MEM_A_CKE<1>

MEM_A_CKE<1>

MAKE_BASE=TRUE

TP_MEM_A_CLKP<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

PEG_CLK100M_N

NC_PCIE_CLK100M_EXCARDN

TRUE

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_N

PEG_CLK100M_P

MAKE_BASE=TRUE

TP_MEM_B_A<15>

NC_MEM_B_ODT<1>

MAKE_BASE=TRUE

NC_MEM_B_CKE<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RN

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2DCN

NC_SATA_ODD_R2DCP

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_A_BIAS_N_2

MEM_A_ODT<1>

PCIE_EXCARD_R2D_C_P

DP_EXTA_AUXCH_C_N

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARDP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PEG_CLK100MN

PCIE_EXCARD_R2D_C_N

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

NC_MEM_A_ODT<1>

MAKE_BASE=TRUE

TP_MEM_B_CLKN<1>

NC_MEM_B_CS_L<1>

MAKE_BASE=TRUE

TP_MEM_A_A<15>

DPLL_REF_CLK_P

MAKE_BASE=TRUE

DPLL_REF_CLK_N

MAKE_BASE=TRUE

DPLL_REF_CLKN

DPLL_REF_CLKP

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

=USB_HUB1_OCS4

MAKE_BASE=TRUE

DP_IG_C_CTRL_DATA

DP_IG_D_CTRL_DATA

MAKE_BASE=TRUE

TP_DP_IG_D_CTRL_DATA

TP_DP_IG_C_CTRL_DATA

MAKE_BASE=TRUE

TP_MEM_A_CLKN<1>

MAKE_BASE=TRUE

TP_MEM_B_CLKP<1>

MAKE_BASE=TRUE

PPBUS_SW_LCDBKLT_PWR

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

STDOFF-4.5OD1.9H-SM

MEM_B_CKE<1> MEM_B_CS_L<1> MEM_B_ODT<1>

MEM_B_A<15>

TP_PCH_CLKOUT_DPP

STDOFF-4.5OD1.9H-SM

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.4-1.4X0.7

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V MIN_NECK_WIDTH=0.075MM

SL-1.1X0.45-1.4X0.75 SL-1.1X0.45-1.4X0.75

SL-1.1X0.45-1.4X0.75SL-1.1X0.45-1.4X0.75

TH-NSP

TH-NSP TH-NSP

TH-NSP

R0917

12

R0918

12

Z0910

1

Z0912

1

SL0900

1

Z0913

1

Z0911

1

Z0915

1

ZS0906

1

Z0914

1

Z0905

1

ZS0905

1

MT0900

1

C0964

1

2

C0962

1

2

R0960

12

C0960

1

2

R0920

1

2

R0921

1

2

R0922

1

2

R0923

1

2

R0924

1

2

R0925

1

2

R0908

1

2

R0915

1

2

R0916

1

2

C0906

1

2

R0926

12

C0907

1

2

R0927

12

C0908

1

2

C0905

1

2

C0901

1

2

C0902

1

2

C0903

1

2

C0904

1

2

R0931

12

R0932

12

R0933

12

R0934

12

R0909

1

2

R0910

12 34

R0990

12

SL0901

1

SL0902

1

SL0905

1

SL0906

1

SL0904

1

SL0903

1

9 OF 109

3.13.0

051-8870

8 OF 75

66

24

68 11

17

72 34

17

72 34

17

34

72 34

17 72 34

9

8 7

17

9

67

17

64

65

64

8 7

17

65 64

36

7

17

64

65

64 64

69 24

69 24 69 64

69 64

64

65

8

65

8

65

8

65

8

64

36

7

24

7

64

65

8

65

8

64

69

6

69

6

69

17 66

69

17 63

17 66

70 34

67

9

70 34

67

9

56 26 26

17

69

70 64

69

70 64

16

68 11

70 16

64

68 11

16

70 64

16

69

70 16

68

68 11

16

67 10

68 11

24

17

66

11

IN

OUT

IN

OUT

IN

OUT

IN

NC

EDP_TX_3

EDP_TX_0 EDP_TX_1 EDP_TX_2

EDP_TX_2* EDP_TX_3*

EDP_TX_0* EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2 FDI1_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

VSS_VAL_SENSE

VAXG_VAL_SENSE VSSAXG_VAL_SENSE

VCC_VAL_SENSE

CFG_17

CFG_16

CFG_15

CFG_10 CFG_11 CFG_12 CFG_13 CFG_14

CFG_5 CFG_6 CFG_7 CFG_8 CFG_9

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4

RSVD_28 RSVD_29

RSVD_30

RSVD_32

RSVD_31

RSVD_34

RSVD_33

RSVD_35 RSVD_36 RSVD_37 RSVD_38

RSVD_40

RSVD_39

RSVD_42 RSVD_43

RSVD_41

RSVD_44

RSVD_45

DC_TEST_A4 DC_TEST_C4

DC_TEST_D1

DC_TEST_D3

DC_TEST_A58

DC_TEST_C59

DC_TEST_A59

DC_TEST_C61

DC_TEST_A61

DC_TEST_D61

DC_TEST_BE61

DC_TEST_BD61

DC_TEST_BG61

DC_TEST_BE59

DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4

DC_TEST_BE3

DC_TEST_BG3

DC_TEST_BE1 DC_TEST_BD1

DC_TEST_BG1

VCC_DIE_SENSE

RSVD_7

RSVD_6

RSVD_8 RSVD_9 RSVD_10

RSVD_12

RSVD_11

RSVD_13 RSVD_14 RSVD_15

RSVD_17

RSVD_16

RSVD_18 RSVD_19 RSVD_20 RSVD_21 RSVD_22

RSVD_24

RSVD_23

RSVD_25

RSVD_27

RSVD_26

RESERVED

(5 OF 9)

OUT

NC

IN

D

GS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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SHEET

PAGE TITLE

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A

D

21

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Apple Inc.

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345678

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87 54 21

to SO-DIMM connectors directly. FETs are needed in order to avoid potential leakage while system is in S3 state.

NOTE: Intel is investigating future processor VREF_DQ generation to replace M1 and M2.

even if internal Graphics is disabled since they are shared with other interfaces.

Note. VOLTAGE=0V

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

NOTE: Intel validation sense lines per

Note. VOLTAGE=0V

FOR SANDYBRIDGE PROCESSOR

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

Note. VOLTAGE=1.05V

This would require routing processor signal balls BE7 and BG7 for Sandy Bridge 2-core

Therefore, an inverting level shifter is required on the motherboard

FIXME: Pin should be EDP_HPD*

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

These can be Placed close to J2500 and Only for debug access

Note. VOLTAGE=1.25V

If HPD is disabled while eDP interface is still enabled,

to low voltage signals for the processor

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

Intel Doc 438297 Huron River SFF DG rev1.0 section 2.2.1 recommendation.

NOTE: The EDP_HPD processor input is a low voltage active low signal. to convert the active high signal from Embedded DisplayPort sink device

(refer to latest Processor EDS for DC specifications).

This signal can be left as no-connect if entire eDP interface is disabled.

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

67 17

8

6

8

6

8

6

8

6

8

6

8

6

24.9

201

1%

1/20W

MF

PLACE_NEAR=U1000.G3:12.7MM

67 23

9

67 23

9

67 23

9

67 23

9

67 23

9

67 23

9

67 23

9

67 23

67

23

67 23

23

9

23

67 17

MOBILE-2C-35W

BGA

CRITICAL

OMIT_TABLE

SANDY-BRIDGE

MOBILE-2C-35W

OMIT_TABLE

CRITICAL

BGA

74 47

EDP

1K

5%

MF-LF

1/16W

402

67 23

9

MF

1/20W

1%

49.9

NOSTUFF

PLACE_SIDE=BOTTOM

201

MF

1/20W

1%

49.9

NOSTUFF

49.9

1%

1/20W

MF

201

PLACE_NEAR=U1000.K43:50.8MM

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.K45:50.8MM

PLACE_SIDE=BOTTOM

NOSTUFF

49.9

1% 1/20W MF 201

1/20W

5%

0

MF

201

NOSTUFF

1K

1% 1/20W MF 201

PLACE_NEAR=U1000.AF3:12.7MM

MF

201

1/20W

1%

24.9

1K

5%

MF-LF

1/16W

402

5%

1K

NOSTUFF

MF-LF

1/16W

402

1K

5%

MF-LF

1/16W

402

5%

1K

NOSTUFF

1/16W

MF-LF

402

1K

MF-LF

1/16W

5%

402

NOSTUFF NOSTUFF

MF-LF

1/16W

1K

402

5% 5%

1K

NOSTUFF

MF-LF

1/16W

402

201

1K

MF

1/20W

5%

PLACE_NEAR=U1000.AG11:12.7MM

SOD-VESM-HF

SSM3K15FV

CPU_CFG<0>

CPU_CFG<7>

=PEG_R2D_C_N<6>

=PEG_R2D_C_N<12>

=PEG_R2D_C_N<11>

=PEG_D2R_N<0>

FDI_DATA_N<1>

FDI_DATA_N<0>

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

TP_EDP_TX_P<3>

DP_INT_ML_P<1> TP_EDP_TX_P<2>

TP_EDP_TX_N<2> TP_EDP_TX_N<3>

DP_INT_ML_N<0> DP_INT_ML_N<1>

DP_INT_AUX_CH_P

DP_INT_AUX_CH_N

EDP_COMP

EDP_HPD_L

FDI_LSYNC<1>

DMI_N2S_N<3>

FDI_LSYNC<0>

FDI_DATA_P<3>

FDI_DATA_P<5>

FDI_DATA_P<4>

FDI_DATA_P<6> FDI_DATA_P<7>

FDI_FSYNC<0> FDI_FSYNC<1>

FDI_INT

FDI_DATA_N<7>

FDI_DATA_N<6>

FDI_DATA_P<0>

FDI_DATA_P<2>

FDI_DATA_N<5>

FDI_DATA_N<3>

FDI_DATA_N<4>

FDI_DATA_N<2>

DMI_N2S_N<1> DMI_N2S_N<2>

DMI_N2S_P<0>

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<3>

DMI_S2N_N<2>

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>

DMI_N2S_N<0>

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_N<0>

CPU_PEG_COMP

=PEG_D2R_N<1>

=PEG_D2R_N<7>

=PEG_D2R_N<6>

=PEG_D2R_N<8> =PEG_D2R_N<9> =PEG_D2R_N<10>

=PEG_D2R_N<12>

=PEG_D2R_N<11>

=PEG_D2R_N<14>

=PEG_D2R_N<13>

=PEG_D2R_N<15>

=PEG_D2R_P<3>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

=PEG_D2R_P<6>

=PEG_D2R_P<5>

=PEG_D2R_P<7> =PEG_D2R_P<8>

=PEG_D2R_P<10>

=PEG_D2R_P<9>

=PEG_D2R_P<11> =PEG_D2R_P<12> =PEG_D2R_P<13> =PEG_D2R_P<14> =PEG_D2R_P<15>

=PEG_R2D_C_N<1> =PEG_R2D_C_N<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<7>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<8> =PEG_R2D_C_N<9>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<2> =PEG_R2D_C_P<3> =PEG_R2D_C_P<4>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<5>

=PEG_R2D_C_P<7> =PEG_R2D_C_P<8> =PEG_R2D_C_P<9> =PEG_R2D_C_P<10> =PEG_R2D_C_P<11> =PEG_R2D_C_P<12>

=PEG_R2D_C_P<14>

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<15>

DP_INT_HPD

CPU_CFG<2>

CPU_MEM_VREFDQ_A

TP_CPU_DC_TEST_A4 CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_D1 TP_CPU_DC_TEST_A58 CPU_DC_TEST_C59_A59

CPU_DC_TEST_C61_A61

TP_CPU_DC_TEST_D61

CPU_DC_TEST_BE59_BE61

TP_CPU_DC_TEST_BD61

CPU_DC_TEST_BG59_BG61

TP_CPU_DC_TEST_BG58 TP_CPU_DC_TEST_BG4 CPU_DC_TEST_C4_BE3_BG3

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

TP_CPU_VCC_DIE_SENSE

=PP1V05_S0_CPU_VCCIO

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<15>

CPU_CFG<13> CPU_CFG<14>

CPU_CFG<10> CPU_CFG<11> CPU_CFG<12>

CPU_CFG<8> CPU_CFG<9>

CPU_CFG<0> CPU_CFG<1>

CPU_CFG<3>

CPU_CFG<5> CPU_CFG<6> CPU_CFG<7>

CPU_CFG<4>

=PPVCORE_S0_CPU

CPU_VCC_VALSENSE_P

=PPVCORE_S0_CPU_VCCAXG

CPU_VCC_VALSENSE_N

PP0V75_S3_MEM_VREFDQ_A

CPU_MEM_VREFDQ_A

CPU_CFG<6>

CPU_CFG<1>

=PP1V05_S0_CPU_VCCIO

FDI_DATA_P<1>

=PEG_R2D_C_N<4> =PEG_R2D_C_N<5>

EDP_HPD_L

CPU DMI/PEG/FDI/RSVD

PLACE_NEAR=U1000.H45:50.8MM

201

=PEG_D2R_P<0> =PEG_D2R_P<1>

=PEG_D2R_N<5>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<2>

CPU_AXG_VALSENSE_P CPU_AXG_VALSENSE_N

CPU_THERMD_P CPU_THERMD_N

47 74

=PP1V05_S0_CPU_VCCIO

DP_INT_ML_P<0>

CPU_CFG<16>

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<4>

CPU_CFG<5>

NOSTUFF

1K

5%

1/16W

MF-LF

402

NOSTUFFNOSTUFF

R1010

12

U1000

N3

M2

P7

P6

P3

P1

P11

P10

K3

K1

M7

M8

P4

N4

T3

R2

AF4

AG4

AF3

AG11

AD2

AC1

AC3

AA4

AC4

AE10

AE11

AE6

AE7

AA11

AA10

U6

U7

W10

W11

W3

W1

AA7

AA6

AC12

AG8

W7

W6

T4

V4

AA3

Y2

AC8

AC9

U11

G3 G1 G4

K22

H22

K19

J21

F8

G8

C8

A8

C5

B6

H6

H8

F6

E5

K6

K7

C21

B22

D19

D21

C19

A19

D16

D17

C13

B14

D12

D13

C11

A11

C9

B10

F22

G22

A23

C23

K13

J14

G13

H13

K10

M10

G10

F10

D8

D9

K4

J4

D24

D23

E21

F21

G19

H19

B18

C17

K17

K15

G17

F17

E14

F14

C15

A15

U1000

B50 C51

K49 K53 F53 G53 L51 F51 D52 L53

B54 D53 A51 C53 C55 H49 A55 H51

A4

A58 A59

A61

BD1

BD61

BE1

BE3

BE59

BE61

BG1

BG3

BG4

BG58

BG59

BG61

C4

C59

C61

D1

D3

D61

AG13

AH2

AM14 AM15

AT21

AT49

AU19 AU21

AV19

AY21

AY22

BA19

BA22

BB19

BB21

BD21 BD22 BD25 BD26

BE22

BE24

BE26

BE7

BF23

BG22

BG26

BG7

H48

K24

K48

L42 L45 L47

M13 M14

N42

N50

P13

U14 W14

H45

F48

H43 K43

K45

R1044

1

2

R1064

1

2

R1070

1

2

R1065

1

2

R1071

1

2

R1021

12

R1020

1

2

R1030

12

R1045

1

2

R1046

1

2

R1047

1

2

R1042

1

2

R1040

1

2

R1041

1

2

R1043

1

2

R1049

1

2

R1031

1

2

Q1031

3

1

2

10 OF 109

3.13.0

051-8870

9 OF 75

67 23

9

67 23

9

23

9

67 23

9

67 23

9

6

70 63

6

70 63

67

9

67

63

14

9 7

9

14 12 10

9 7

14 12

7

15 12

7

68 31 30 29 28 27

9

67 23

9

23

9

14 12 10

9 7

67 23

9

23

9

10 12

67

BI

IN

OUT

IN

OUT

BI

NC

OUT

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN

OUT

IN

OUT

IN

OUT

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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87 54 21

(IPU) (IPU)

(IPU) (IPU) (IPU) (IPU) (IPU) (IPU)

(IPU)

67 23

67 26 17

67 23 19

26

67 16

18

67 19

67 57 42

67 41 19

67

OMIT_TABLE

CRITICAL

SANDY-BRIDGE

MOBILE-2C-35W

BGA

62

5% 1/20W MF 201

201

MF

1/20W

5%

51

NOSTUFF

1K

5%

1/20W

MF

201

NOSTUFF NOSTUFF

1K

5% 1/20W MF 201

201

MF

1/20W

5%

56

200

1%

1/20W

MF

201

1%

1/20W

MF

201

130

1%

MF

1/20W

200

201

1% 1/20W

201

MF

25.5140

1% 1/20W MF 201

10K

201

MF

1/20W

5%

75

1%

1/20W

MF

201

43.2

1%

MF

1/20W

201

1/20W MF

4.99K

1%

201

NOSTUFF

67

8

67

8

67 23

67 16

67 17

25 23

67 25 23

67 23

CPU CLOCK/MISC/JTAG

DPLL_REF_CLKN

DPLL_REF_CLKP

XDP_CPU_PRDY_L

XDP_CPU_TMS

XDP_DBRESET_L

XDP_BPM_L<0>

=PP1V05_S0_CPU_VCCIO

PM_SYNC

XDP_CPU_TDO

XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_BPM_L<6> XDP_BPM_L<7>

XDP_CPU_TCK

XDP_CPU_TDI

XDP_CPU_TRST_L

CPU_PROC_SEL_L

PM_THRMTRIP_L

CPU_SM_RCOMP<1>

=PP1V05_S0_CPU_VCCIO

CPU_RESET_L

CPU_PECI

ITPCPU_CLK100M_P ITPCPU_CLK100M_N

XDP_CPU_PREQ_L

CPU_CATERR_L

CPU_PROCHOT_L

CPU_PROCHOT_R_L

=PP1V5_S3_CPU_VCCDDR

PM_MEM_PWRGD

XDP_BPM_L<1>

CPU_SM_RCOMP<2>

CPU_SM_RCOMP<0>

PM_MEM_PWRGD_R

CPU_PWRGD

=MEM_RESET_L

PLT_RESET_LS1V1_L

DMI_CLK100M_CPU_P DMI_CLK100M_CPU_N

U1000

J3 H2

N59 N58

G58 E55 E59 G55 G59 H60 J59 J61

C49

K58

AG3 AG1

A48

C48

N53 N55

C57

F49

C45

D44

BE45

AT30

BF44 BE43 BG43

L56

M60 L59

D45

L55 J58

B46

R1101

1

2

R1104

1

2

R1100

1

2

R1102

1

2

R1103

12

R1120

1

2

R1121

12

R1114

1

2

R1113

1

2

R1112

1

2

R1111

1

2

R1126

1

2

R1125

12

R1115

1

2

11 OF 109

3.13.0

051-8870

10 OF 75

14 12 10

9 7

67

14 12 10

9 7

26 15 12

7

67

BI

OUT

BI

OUT

BI

OUT

BI

OUT

SA_MA_14 SA_MA_15

SA_MA_12 SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5 SA_DQS_6

SA_DQS_3 SA_DQS_4

SA_DQS_2

SA_DQS_0 SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0* SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0 SA_BS_1 SA_BS_2

SA_DQ_62 SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50 SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42 SA_DQ_43

SA_DQ_41

SA_DQ_39 SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34 SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29 SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24 SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19 SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_11 SA_DQ_12

SA_DQ_9 SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12 SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7 SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0 SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34 SB_DQ_35

SB_DQ_33

SB_DQ_31 SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26 SB_DQ_27 SB_DQ_28

SB_DQ_24 SB_DQ_25

SB_DQ_21 SB_DQ_22 SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8 SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4 SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40 SB_DQ_41 SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SIZE

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PAGE TITLE

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A

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C

345678

D

B

87 54 21

68 27

68 28

68 32 28 27

68 29

68 30

68 32 30 29

68 32 28 27

68 27

68 28

68 27

68 28

68 32 28 27

68

8

68 32 30 29

68 29

68 30

68 29

68 30

68 32 30 29

68

8

SANDY-BRIDGE

MOBILE-2C-35W

CRITICAL

BGA

OMIT_TABLE

MOBILE-2C-35W

SANDY-BRIDGE

OMIT_TABLE

CRITICAL

BGA

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

SYNC_DATE=01/10/2011

CPU DDR3 INTERFACES

MEM_B_ODT<1>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>MEM_A_CLK_P<1>

MEM_A_ODT<1>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_CLK_N<1>

MEM_A_CLK_N<0>

MEM_A_DQ<0>

MEM_A_DQ<2> MEM_A_DQ<3>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<1>

MEM_A_DQS_P<3> MEM_A_DQS_P<4>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_CLK_P<0>

MEM_A_DQ<15>

MEM_A_DQS_N<0> MEM_A_DQS_N<1> MEM_A_DQS_N<2> MEM_A_DQS_N<3> MEM_A_DQS_N<4>

MEM_B_CKE<0>

MEM_B_DQ<7> MEM_B_DQ<8>

MEM_A_DQS_N<7>

MEM_B_CLK_P<0>

MEM_B_CS_L<0>

MEM_B_DQS_N<0>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<12> MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<9> MEM_A_A<10>

MEM_A_A<8>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<5> MEM_A_DQS_P<6>

MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<50> MEM_A_DQ<51>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<42> MEM_A_DQ<43>

MEM_A_DQ<41>

MEM_A_DQ<39> MEM_A_DQ<40>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<34> MEM_A_DQ<35>

MEM_A_DQ<31>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<29> MEM_A_DQ<30>

MEM_A_DQ<26>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<24> MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<19> MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<13> MEM_A_DQ<14>

MEM_A_DQ<11> MEM_A_DQ<12>

MEM_A_DQ<9> MEM_A_DQ<10>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<1>

MEM_A_DQS_P<1>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<12> MEM_B_A<13>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_ODT<0>

MEM_B_CLK_N<0>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<34> MEM_B_DQ<35>

MEM_B_DQ<33>

MEM_B_DQ<31> MEM_B_DQ<32>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<26>

MEM_B_DQ<28>

MEM_B_DQ<24> MEM_B_DQ<25>

MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_DQ<6>

MEM_B_DQ<4> MEM_B_DQ<5>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<47>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<57>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<62>

MEM_B_BA<0>

MEM_B_DQ<63>

MEM_B_BA<1> MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_A_DQ<46>

MEM_B_A<7>

MEM_B_DQ<27>

U1000

BD37 BF36 BA28

BE39

AU36 AV36

AT40 AU40

AY26

BB26

BB40 BC41

AG6 AJ6

AU6 AV9 AR6

AP8 AT13 AU13

BC7

BB7 BA13 BB11

AP11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14

AL6

BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48

AJ10

BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56

AJ8

AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53

AL8

AN55 AN52 AG55 AK56

AL7 AR11

AP6

AJ11

AL11

AR10

AR8

AY11

AV11

AU17

AT17

AW45

AV45

AV51

AY51

AT56

AT55

AK54

AK55

BG35 BB34

BE37 BA30 BC30 AW41 AY28 AU26

BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32

AY40 BA41

BD39 AT41

U1000

BG39 BD42 AT22

AV43

BA34 AY34

BA36 BB36

AR22

BF27

BE41 BE47

AL4 AL1

AV4 BA4 AU3 AR3 AY2 BA3 BE9

BD9 BD13 BF12

AN3

BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14

AR4

BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53

AK4

BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58

AK3

AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59

AN4

AM60 AL59 AF61 AH60

AR1

AU4

AT2

AM2

AL3

AV1

AV3

BE11

BG11

BD18

BD17

BE51

BG51

BA61

BA59

AR59

AT60

AK61

AK59

BF32 BE33

BD43 AT28 AV28 BD46 AT26 AU22

BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28

AT43 BG47

BF40 BD45

12 OF 109

3.13.0

051-8870

11 OF 75

OUT

IN

BI

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1 VCCPQE_2

VIDALERT*

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE SVID QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25 VDDQ_26

VCCDQ_1 VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0 VCCSA_VID_1

SM_VREF

VAXG_1 VAXG_2

VAXG_4

VAXG_3

VAXG_5 VAXG_6 VAXG_7 VAXG_8 VAXG_9 VAXG_10 VAXG_11 VAXG_12 VAXG_13 VAXG_14 VAXG_15 VAXG_16 VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25

VAXG_28

VAXG_26 VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31 VAXG_32

VAXG_35

VAXG_34

VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43

VAXG_45

VAXG_44

VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56

VAXG_SENSE VSSAXG_SENSE

VCCPLL_1 VCCPLL_2 VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3 VCCSA_4 VCCSA_5 VCCSA_6 VCCSA_7 VCCSA_8 VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

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SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=1.25V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Fixed at 1.05V

(IPU)

(NOT controlled by VCCIO_SEL)

For Future Compatibility

(IPU)

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

67 57

67 59

54

67 57

54

BGA

CRITICAL

OMIT_TABLE

MOBILE-2C-35W

SANDY-BRIDGE

MOBILE-2C-35W

BGA

CRITICAL

OMIT_TABLE

MF05%

1/20W

201

MF05%

1/20W

201

43

201

1/20W

5% MF

PLACE_NEAR=U1000.C44:2.54mm

201

MF

1/20W

1%

130

10K

1/20W

5%

MF

201

MF

1/20W

1%

75

PLACE_NEAR=R1310.2:2.54mm

PLACE_NEAR=U1000.F45:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

100

1% 1/20W MF 201

PLACE_SIDE=BOTTOM

NOSTUFF

100

1%

1/20W

MF

201

PLACE_NEAR=U1000.G45:50.8mm

PLACE_NEAR=U1000.U10:50.8mm

201

MF

1/20W

1%

100

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.BC43:50.8mm

100

1%

1/20W

MF

201

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.BA43:50.8mm

201

1/20W

1%

100

MF

201

MF

5%

1/20W

10K

201

MF

5% 1/20W

10K

SM_VREF_EXT

5%

201

MF

1/20W

100

PLACE_NEAR=U1000.AY43:2.54mm

SM_VREF_EXT

100

1/20W

MF

201

5%

PLACE_NEAR=U1000.AY43:2.54mm

10% 16V X5R-CERM 0201

0.1UF

SM_VREF_EXT

PLACE_NEAR=U1000.AY43:2.54mm

PLACE_NEAR=U1000.AN16:50.8mm PLACE_SIDE=BOTTOM

201

MF

1/20W

1%

100

NOSTUFF

PLACE_NEAR=U1000.F43:50.8mm

NOSTUFF

100

1%

1/20W

MF

201

PLACE_SIDE=BOTTOM

100

1%

1/20W

MF

201

PLACE_NEAR=U1000.G43:50.8mm

PLACE_SIDE=BOTTOM

NOSTUFF

201

MF

1/20W

1%

100

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AN17:50.8mm

SYNC_DATE=01/10/2011

CPU POWER

SYNC_MASTER=K78_MLB

=PPVCORE_S0_CPU_VCCAXG

=PP1V5_S3_CPU_VCCDDR

=PPVCORE_S0_CPU

=PPVCCSA_S0_CPU

=PP1V5_S3_CPU_VCCDQ

=PP1V05_S0_CPU_VCCPQE

CPU_VIDSCLK_R CPU_VIDSOUT_R

CPU_VCCIO_SEL

CPU_VIDSCLK

CPU_VIDSOUT

CPU_VIDALERT_L_R

CPU_VIDALERT_L

=PP1V05_S0_CPU_VCCIO

=PPVCCSA_S0_CPU

CPU_VCCSASENSE

CPU_VDDQ_SENSE_P

=PP1V5_S3_CPU_VCCDDR

CPU_VDDQ_SENSE_N

CPU_VCCSA_VID<1>

CPU_VCCSA_VID<0>

=PP1V5_S3_CPU_VCCDDR

VOLTAGE=0.75V

CPU_DDR_VREF

=PPVCORE_S0_CPU_VCCAXG

=PP1V05_S0_CPU_VCCIO

CPU_VCCIOSENSE_P

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

CPU_VCCIOSENSE_N

CPU_VCCSENSE_N

=PP1V05_S0_CPU_VCCIO

=PP3V3_S0_CPU_VCCIO_SEL

CPU_AXG_SENSE_P

=PP1V8_S0_CPU_VCCPLL_R

CPU_AXG_SENSE_N

U1000

A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

F43

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20

AF46

AG15 AG16 AG17 AG20 AG21

AG48 AG50 AG51

AJ14 AJ15

AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

BC22

AN16

W16 W17

AM25 AN22

A44 B43 C44

G43

AN17

U1000

AY43

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61

F45

T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61

AM28 AN26

BB3 BC1 BC4

L17 L21 N16 N20 N22 P17 P20 R16 R18 R21

U10

U15 V16 V17 V18 V21

D48 D49

W20

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

BC43 BA43

G45

R1311

12

R1312

12

R1310

12

R1302

1

2

R1320

1

2

R1300

1

2

R1370

1

2

R1371

1

2

R1382

1

2

R1380

1

2

R1381

1

2

R1314

1

2

R1313

1

2

R1330

1

2

R1331

1

2

C1330

1

2

R1362

1

2

R1360

1

2

R1361

1

2

R1363

1

2

13 OF 109

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051-8870

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15 12

9 7

14 12

9 7

15 12

7

15

7

14

7

14 12 10

9 7

15 12

7

26 15 12 10

7

26 15 12 10

7

12

15 12

9 7

14 12 10

9 7

14 12

9 7

7

14

7

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

(9 OF 9)

VSS

(8 OF 9)

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

OMIT_TABLE

CRITICAL

SANDY-BRIDGE

MOBILE-2C-35W

BGA

OMIT_TABLE

CRITICAL

MOBILE-2C-35W

SANDY-BRIDGE

BGA

CPU GROUNDS

U1000

BG13

BG17

BG21

BG24

BG28

BG37

BG41

BG45

BG49

BG53

C29

C35

C40

D10

D14

D18

D22

D26

D29

D35

D4

D40

D43

D46

D50

D54

D58

D6

E25

E29

E3

E35

E40

F13

F15

F19

F29

F35

F40

F55

G48

G51

G6

G61

H10

H14

H17

H21

H4

H53

H58

J1

J49

J55

K11

K21

K51

K8

L16

L20

L22

L26

L30

L34

L38

L43

L48

L61

M11

M15

M4

M58

M6

N1

N17

N21

N25

N28

N33

N36

N40

N43

N47

N48

N51

N52

N56

N61

A5

A57

BC61

BD3

BD59

BE4

BE58

BG5

BG57

C3

C58

D59

E1

E61

P14

P16

P18

P21

P58

P59

P9

R17

R20

R4

R46

T1

T47

T50

T51

T52

T53

T55

T56

U13

U8

V20

V61

W13

W15

W18

W21

W46

W8

Y4

Y47

Y58

Y59

U1000

A13

A17

A21

A25

A28

A33

A37

A40

A45

A49

A53

A9

AA1

AA13

AA50

AA51

AA52

AA53

AA55

AA56

AA8

AB16

AB18

AB21

AB48

AB61

AC10

AC14

AC46

AC6

AD17

AD20

AD4

AD61

AE13

AE8

AF1

AF17

AF21

AF47

AF48

AF50

AF51

AF52

AF53

AF55

AF56

AF58

AF59

AG10

AG14

AG18

AG47

AG52

AG61

AG7

AH4

AH58

AJ13

AJ16

AJ20

AJ22

AJ26

AJ30

AJ34

AJ38

AJ42

AJ45

AJ48

AJ7

AK1

AK52

AL10

AL13

AL17

AL21

AL25

AL28

AL33

AL36

AL40

AL43

AL47

AL61

AM13

AM20

AM22

AM26

AM30

AM34

AM38

AM4

AM42

AM45

AM48

AM58

AN1

AN21

AN25

AN28

AN33

AN36

AN40

AN43

AN47

AN50

AN54

AP10

AP51

AP55

AP7

AR13

AR17

AR21

AR41

AR48

AR61

AR7

AT14

AT19

AT36

AT4

AT45

AT52

AT58

AU1

AU11

AU28

AU32

AU51

AU7

AV17

AV21

AV22

AV34

AV40

AV48

AV55

AW13

AW43

AW61

AW7

AY14

AY19

AY30

AY36

AY4

AY41

AY45

AY49

AY55

AY58

AY9

BA1

BA11

BA17

BA21

BA26

BA32

BA48

BA51

BB53

BC13

BC5

BC57

BD12

BD16

BD19

BD23

BD27

BD32

BD36

BD40

BD44

BD48

BD52

BD56

BD8

BE5

BG9

14 OF 109

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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87 54 21

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide

PLACEMENT_NOTE (C1684-C167F):

PLACEMENT_NOTE (C1672-C1681):

CPU VCCPLL DECOUPLING

Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

PLACEMENT_NOTE (C1646-C1671):

CPU VCORE DECOUPLING

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

PLACEMENT_NOTE (C1667-C1679):

Note:The smallest 10mOhm available in the library are 0805s

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Processor Load Line : -2.9 mOhms

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1655-C1666):

CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

PLACEMENT_NOTE (C1640-C1645):

0.010

MF

0603

1%

1/4W

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

1UF

X5R 402

10% 10V

2.2UF

X5R 402

4V

20%

CRITICAL CRITICAL

2.2UF

X5R 402

4V

20%

CRITICAL

2.2UF

X5R 402

20% 4V

CRITICAL

2.2UF

X5R 402

20% 4V

X5R 402

10% 10V

1UF

CRITICAL

2.2UF

402

20% 4V X5R

CRITICAL

2.2UF

402

20% 4V X5R

CRITICAL

2.2UF

402

20% 4V X5R

CRITICAL

2.2UF

402

20% 4V X5R

CRITICAL

2.2UF

402

20% 4V X5R

1UF

X5R 402

10% 10V

10UF

6.3V

20%

Place near U1000 on bottom side

CERM-X5R 0402-1

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

1UF

X5R 402

10% 10V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R 0402-1

20%

6.3V

20% 2V

CASE-B2-SM

TANT

270UF

2V CASE-B2-SM

TANT

20%

270UF

1UF

X5R 402

10% 10V

X5R 402

4V

20%

22UF

CRITICAL

X5R

4V

20%

402

22UF

CRITICAL CRITICAL

4V

20%

402

X5R

22UF

4V

20%

402

X5R

22UF

CRITICAL

4V

20%

402

X5R

22UF

CRITICAL

20% 4V

402

X5R

22UF

CRITICAL

4V

20%

402

X5R

22UF

CRITICAL

20% 4V

402

X5R

22UF

CRITICAL

4V

20%

402

X5R

22UF

CRITICAL

X5R

4V

20%

402

22UF

CRITICAL

20%

CASE-B2-SM

270UF

2V TANT TANT

20% 2V

CASE-B2-SM

270UF

CASE-B2-SM

2V

20% TANT

270UF

TANT CASE-B2-SM

20% 2V

270UF

TANT CASE-B2-SM

20% 2V

270UF

TANT CASE-B2-SM

20% 2V

2V

20% TANT

PLACE_NEAR=U1000.BC2:5mm

CASE-B2-SM

270UF

CASE-B2-SM

2V

20% TANT

270UF

1UF

X5R 402

10% 10V

X5R

10% 10V

402

1UF

Place on bottom side of U1000Place on bottom side of U100.

1UF

X5R 402

10% 10V

Place on bottom side of U1000

X5R 402

10% 10V

1UF

CRITICAL

4V

20%

402

X5R

22UF

Place close to U1000 on top side.

22UF

4V

20%

402

X5R

CRITICAL

Place on bottom side of U1000

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

2.2UF

X5R

20% 4V

402

CRITICAL

2.2UF

X5R

20% 4V

402

CRITICAL

2.2UF

20% 4V

402

X5R

CRITICAL

402

20% X5R

4V

CRITICAL

2.2UF

X5R

4V

20%

402

2.2UF

CRITICAL

X5R 402

4V

20%

CRITICAL

2.2UF

CRITICAL

2.2UF

402

20% X5R

4V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

1UF

X5R 402

10% 10V

Place near U1000 on bottom side

10UF

CERM-X5R

20%

6.3V 0402-1

0

402

5%

MF-LF

1/16W

PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

1UF

X5R 402

10% 10V

Place near U1000 on top side

CPU DECOUPLING-I

SYNC_MASTER=K78_MLB

SYNC_DATE=02/08/2011

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_CPU_VCCPLL_R

R1601

12

C167F

1

2

C1697

1

2

C161F

1

2

C1698

1

2

C1699

1

2

C169A

1

2

C169B

1

2

C169C

1

2

C1684

1

2

C1685

1

2

C1686

1

2

C1655

1

2

C1656

1

2

C1687

1

2

C1688

1

2

C1689

1

2

C1600

1

2

C1601

1

2

C1602

1

2

C1603

1

2

C1604

1

2

C1605

1

2

C1606

1

2

C169D

1

2

C169E

1

2

C169F

1

2

C161A

1

2

C161B

1

2

C161C

1

2

C161D

1

2

C1690

1

2

C1691

1

2

C1692

1

2

C1693

1

2

C1694

1

2

C1695

1

2

C1696

1

2

R1600

12

C160X

1

2

C160Y

1

2

C1607

1

2

C1608

1

2

C1609

1

2

C1610

1

2

C1611

1

2

C1612

1

2

C1613

1

2

C1614

1

2

C1615

1

2

C161E

1

2

C162A

1

2

C162B

1

2

C162C

1

2

C162D

1

2

C162E

1

2

C167A

1

2

C167B

1

2

C167C

1

2

C167D

1

2

C1680

1

2

C1657

1

2

C1658

1

2

C1659

1

2

C1660

1

2

C1661

1

2

C1662

1

2

C1663

1

2

C1664

1

2

C1665

1

2

C1666

1

2

C1681

1

2

C1682

1

2

C1683

1

2

C167E

1

2

C167G

1

2

C167H

1

2

C160Z

1

2

C1679

1

2

16 OF 109

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051-8870

14 OF 75

12 10

9 7

12

9 7

12

7

12

7

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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87 54 21

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)

VAXG DECOUPLING

PLACEMENT_NOTE (C1700-C1710):

Graphics Load Line : -3.9 mOhms

PLACEMENT_NOTE (C1717-C1722):

PLACEMENT_NOTE (C1711-C1716):

PLACEMENT_NOTE (C1738-C1747):

PLACEMENT_NOTE (C1758-C1762):

CPU VCCSA DECOUPLING

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF

CPU VDDQ/VCCDQ DECOUPLING

PLACEMENT_NOTE (C1723-C1724):

0603

0.010

1%

1/4W

MF

Place on bottom side of U1000

402

X5R

10V

10%

1UF

CASE-B2-SM

270UF

TANT

20% 2V

CASE-B2-SM

20% 2V TANT

270UF

CRITICAL

10UF

0402-1

CERM-X5R

6.3V

20%

CRITICAL

10UF

20%

6.3V

0402-1

CERM-X5R

CRITICAL

6.3V

10UF

20%

0402-1

CERM-X5R

CRITICAL

10UF

CERM-X5R

20%

0402-1

6.3V

CRITICAL

10UF

CERM-X5R

6.3V

20%

0402-1

CRITICAL

0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom side

10UF

20%

CERM-X5R

6.3V

0402-1

6.3V

22UF

20%

CRITICAL

X5R-CERM1 0603

6.3V

Place close to U1000 on bottom side

10UF

CERM-X5R

20%

0402-1 0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1 0402-1

20%

6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

10UF

CERM-X5R

6.3V

20%

0402-1 0402-1

10UF

CERM-X5R

6.3V

20%

10UF

CERM-X5R

6.3V

20%

0402-1

20%

6.3V

22UF

CRITICAL

X5R-CERM1 0603

10UF

CERM-X5R

6.3V

20%

0402-1 0402-1

20%

6.3V

CERM-X5R

10UF

270UF

20% 2V TANT CASE-B2-SM

270UF

20% 2V TANT CASE-B2-SM

270UF

20% 2V TANT CASE-B2-SM

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

6.3V

20%

Place close to U1000 on bottom side

10UF

CERM-X5R

0402-1

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

10V

10%

1UF

402

X5R

Place on bottom side of U1000

1UF

X5R 402

10% 10V 10V

402

1UF

10%

X5R X5R

1UF

10% 10V

402

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

22UF

20%

6.3V

CRITICAL

X5R-CERM1 0603

1UF

402

10V X5R

10% 10%

10V X5R

1UF

402

1UF

10%

X5R 402

10V

Place on bottom side of U1000

402

CRITICAL

10V X5R

10%

1UF 1UF

10%

CRITICAL

402

10V

Place on bottom side of U100.

X5R

CRITICAL

X5R 402

10V

10%

1UF

Place on bottom side of U1000

CRITICAL

1UF

402

10%

X5R

10V

1UF

CRITICAL

10% 10V

402

X5R

CRITICAL

10V

10%

1UF

X5R 402

X5R

10%

10V

402

1UF

402

CRITICAL

1UF

10% 10V X5R

CRITICAL

1UF

402

X5R

10V

10%

CRITICAL

1UF

10% 10V X5R 402

402

10V

10%

1UF

Place on bottom side of U1000

X5R

1UF

Place on bottom side of U100.

10V

402

X5R

10%

Place on bottom side of U1000

402

10V

10%

1UF

X5R

1UF

Place on bottom side of U1000

10V

402

10%

X5R

402

1UF

10%

X5R

10V

CRITICAL

1UF

402

X5R

10% 10V

CRITICAL

10V

10%

402

1UF

X5R

Place on bottom side of U1000

1UF

10V

Place on bottom side of U1000

10%

X5R 402

1UF

402

X5R

Place on bottom side of U100.

10V

10%

SYNC_MASTER=K78_MLB

CPU DECOUPLING-II

SYNC_DATE=01/10/2011

=PPVCORE_S0_CPU_VCCAXG

=PP1V5_S3_CPU_VCCDDR

=PPVCCSA_S0_CPU

=PP1V5_S3_CPU_VCCDQ

R1702

12

C1757

1

2

C1738

1

2

C1739

1

2

C1740

1

2

C1717

1

2

C1718

1

2

C1719

1

2

C1741

1

2

C1742

1

2

C1743

1

2

C1744

1

2

C1720

1

2

C1721

1

2

C1722

1

2

C1745

1

2

C1746

1

2

C1747

1

2

C1700

1

2

C1701

1

2

C1702

1

2

C1704

1

2

C1705

1

2

C1706

1

2

C1707

1

2

C1708

1

2

C1709

1

2

C1758

1

2

C1759

1

2

C1760

1

2

C1761

1

2

C1762

1

2

C1710

1

2

C1703

1

2

C1756

1

2

C1768

1

2

C1711

1

2

C1712

1

2

C1713

1

2

C1714

1

2

C1715

1

2

C1716

1

2

C1748

1

2

C1749

1

2

C1751

1

2

C1752

1

2

C1753

1

2

C1755

1

2

C1763

1

2

C1764

1

2

C1765

1

2

C1766

1

2

C1767

1

2

C1723

1

2

C1724

1

2

C1725

1

2

C1754

1

2

C1750

1

2

17 OF 109

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051-8870

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12

9 7

26 12 10

7

12

7

12

7

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

BI

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

NC

IN

OUT

SRTCRST*

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

RTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0 HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0

RTCX1 RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

SATA1RXP SATA1TXN

SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5TXN SATA5TXP

SATAICOMPO SATAICOMPI

SATALED*

SATA0GP/GPIO21 SATA1GP/GPIO19

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

RTC

IHDA

JTAG

SPI

SATA

LPC

(1 OF 10)

SMBDATA

SML0CLK

SML0ALERT*/GPIO60

SML0DATA

SML1ALERT*/PCHHOT*/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

PETP1

PERP2

PERN2

PERP3 PETN3

PERN4

PETP3

PERP4 PETN4

PERN5

PETP4

PERP5 PETN5 PETP5

PERN6 PERP6

PETP6

PETN6

PERN7 PERP7 PETN7

PERN8

PETP7

PETN8

PERP8

PETP8

SMBALERT*/GPIO11

SMBCLK

PERN1

PETN1

CLKOUT_PCIE0P

CLKOUT_PCIE0N

PERP1

PETN2 PETP2

PERN3

PCIECLKRQ0*/GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1*/GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE3P

CLKOUT_PCIE3N

PCIECLKRQ3*/GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4*/GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ*/GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6*/GPIO45

CLKOUT_PCIE7N CLKOUT_PCIE7P

PCIECLKRQ7*/GPIO46

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CL_DATA1

CL_CLK1

CL_RST1*

PEG_A_CLKRQ*/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_SATA_P

CLKIN_SATA_N

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

CLK

FLEX CLOCK

LINK

CNTRL

SMBUS

PCI-E*

(2 OF 10)

IN

OUT

IN

OUT

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Pullup needed for SPI_DESCRIPTOR_OVERRIDE_L? PD needed for BCM_MEDIA_SENSE?

TIE THEM TOGETHER VERY CLOSE TO PINS. PLACE THE RESISTOR LESS THAN 200MILS FROM THE PINS

(IPU)

PLACE THIS RESISTOR NEAR THE PCH PIN

DOES THIS NEED LENGTH MATCH???

1.5V -> 1.1V

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

10K

MF

201

5%

1/20W

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.H37:1.27mm

PLACE_NEAR=U1800.H35:1.27mm

33

MF

201

5%

1/20W

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.K37:1.27mm

33

MF

201

5%

1/20W

PLACE_NEAR=U1800.F35:1.27mm

1/20W

MF

5%

201

10K

201

5%

1/20W

MF

10K

5%

1/20W

201

MF

NOSTUFF

10K

5%

201

MF

1/20W

MF

201

5%

1/20W

10K

5%

NOSTUFF

1/20W

201

MF

1/20W

5%

10K

201

10K

201

1/20W

5% MF

1/20W

201

MF

10K

5%

NOSTUFF

10K

MF

201

5%

1/20W

330K

5%

201

MF

1/20W

0

MF

201

5%

1/20W

NOSTUFF

PLACE_NEAR=R1813.1:2.54mm

10K

MF 201

5% 1/20W1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

NOSTUFF

0

MF

201

5%

1/20W

0

5%

1/20W

MF

201

NOSTUFF

0

5%

1/20W

MF

201

NOSTUFF

10K

MF

201

5%

1/20W

5%

201

MF

10K

5%

1/20W

MF

201

33

201

MF

1/20W

5%

33

5%

1/20W

MF

201

33

201

MF

1/20W

5%

33

5%

1/20W

MF

201

33

10K

MF 201

5% 1/20W

MF

PLACE_NEAR=U1800.AB10:2.54mm

37.4

201

1%

1/20W

10K

MF

201

5%

1/20W

5%

201

MF

4.7K

5%

1/20W

4.7K

201

MF

PLACE_NEAR=U1800.AF12:2.54mm

49.9

MF

201

1%

1/20W

PLACE_NEAR=U1800.AH4:2.54mm

750

MF

201

1%

1/20W

20K

MF 201

5% 1/20W

MF

5%

1/20W

20K

201

1M

MF 201

5% 1/20W

6.3V

20%

1.0UF

X5R 0201-MUR

6.3V X5R

0201-MUR

20%

1.0UF

201

MF

1/20W

5%

10K

1/20W

MF

201

5%

1/20W

1%201 MF

604

PLACE_NEAR=U1800.W49:5.1mm

PLACE_NEAR=R1885.1:2.54mm

1K

MF 201

1% 1/20W

PLACE_NEAR=U1800.W49:2.54mm

90.9

MF

201

1%

1/20W

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

PCH SATA/PCIE/CLK/LPC/SPI

PCH_INTVRMEN_L

PCH_INTRUDER_L

SPI_MOSI_R

PCH_SPKR

SMC_SCI_L

HDA_SYNC_R

TP_SATA_B_D2RN TP_SATA_B_D2RP

SATA_HDD_D2R_P

LPC_SERIRQ

TP_SATA_B_R2D_CP

PCH_SATA3RBIAS

PCH_SATA3COMP

PCH_SATAICOMP

SPI_MISO

PCIECLKRQ5_L_GPIO44

HDA_SDOUT_R

JTAG_T29_TMS ENET_MEDIA_SENSE

TP_SATA_F_D2RP TP_SATA_F_R2D_CN TP_SATA_F_R2D_CP

PCH_SATALED_L

TP_SATA_E_R2D_CP

TP_SATA_D_R2D_CN

PCH_SRTCRST_L

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

RTC_RESET_L

PCH_INTRUDER_L

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_SYNC_R

HDA_RST_R_L

HDA_SDIN0 TP_HDA_SDIN1 TP_HDA_SDIN2

XDP_PCH_TCK

SPI_CS0_R_L

SPI_CLK_R

SYSCLK_CLK32K_RTC

SATA_HDD_D2R_N

TP_SATA_E_D2RN TP_SATA_E_D2RP TP_SATA_E_R2D_CN

TP_SATA_F_D2RN

DP_AUXCH_ISOL SATARDRVR_EN

HDA_SDOUT_R

HDA_SYNC

HDA_BIT_CLK

HDA_SDOUT

HDA_RST_R_L

HDA_RST_L

ITPCPU_CLK100M_N

ITPXDP_CLK100M_P ITPCPU_CLK100M_P

HDA_SDOUT_R

TP_HDA_SDIN3

XDP_PCH_TMS

XDP_PCH_TDO

TP_SPI_CS1_L

HDA_BIT_CLK_R

TP_SATA_D_R2D_CP

TP_SATA_D_D2RP

=PP3V3_S0_PCH

=PP1V05_S0_PCH_VCCIO_SATA

ENET_MEDIA_SENSE

=PP1V05_S0_PCH

SPI_DESCRIPTOR_OVERRIDE_L

PCH_GPIO11

XDP_PCH_TDI

PCH_SRTCRST_L

=PP1V05_S0_PCH_VCCDIFFCLK

DP_AUXCH_ISOL

SATA_ODD_D2R_P SATA_ODD_R2D_C_N SATA_ODD_R2D_C_P

TP_SATA_D_D2RN

TP_SATA_B_R2D_CN

T29_PWR_EN_PCH

TP_LPC_DREQ0_L

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO66_CLKOUTFLEX2

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO64_CLKOUTFLEX0

PCH_XCLK_RCOMP

PCH_CLK33M_PCIIN

PCH_CLK100M_SATA_N PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N PCH_CLK96M_DOT_P

PCH_CLKIN_GNDP1

PCH_CLKIN_GNDN1

PCIE_CLK100M_PCH_P

PCIE_CLK100M_PCH_N

TP_PCH_CLKOUT_DPP

TP_PCH_CLKOUT_DPN

DMI_CLK100M_CPU_N DMI_CLK100M_CPU_P

PEG_CLK100M_P

PEG_CLK100M_N

PEG_CLKREQ_L

TP_CLINK_RESET_L

TP_CLINK_CLK

TP_CLINK_DATA

ITPXDP_CLK100M_N ITPXDP_CLK100M_P

PCH_GPIO46

TP_PCIE_CLK100M_PE7P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE6N

PEG_B_CLKRQ_L_GPIO56

TP_PCIE_CLK100M_PEBP

TP_PCIE_CLK100M_PEBN

PCIECLKRQ5_L_GPIO44

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE5N

T29_CLKREQ_L

PCIE_CLK100M_T29_P

PCIE_CLK100M_T29_N

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P

PCIECLKRQ2_L_GPIO20

TP_PCIE_CLK100M_PE2P

TP_PCIE_CLK100M_PE2N

AP_CLKREQ_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIECLKRQ0_L_GPIO73

NC_PCIE_3_D2RN

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

NC_PCIE_1_D2RP

TP_PCIE_CLK100M_PE0N TP_PCIE_CLK100M_PE0P

NC_PCIE_1_R2D_CN

NC_PCIE_1_D2RN

SMBUS_PCH_CLK

PCH_GPIO11

NC_PCIE_8_R2D_CP

NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN

NC_PCIE_7_R2D_CP

NC_PCIE_8_D2RN

NC_PCIE_7_R2D_CN

NC_PCIE_7_D2RP

NC_PCIE_7_D2RN

NC_PCIE_6_R2D_CN NC_PCIE_6_R2D_CP

NC_PCIE_6_D2RP

NC_PCIE_6_D2RN

NC_PCIE_5_R2D_CP

NC_PCIE_5_R2D_CN

NC_PCIE_5_D2RP

PCIE_EXCARD_R2D_C_P

NC_PCIE_5_D2RN

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

NC_PCIE_3_R2D_CP

PCIE_EXCARD_D2R_N

NC_PCIE_3_R2D_CN

NC_PCIE_3_D2RP

PCIE_AP_D2R_N PCIE_AP_D2R_P

NC_PCIE_1_R2D_CP

SML_PCH_1_DATA

SML_PCH_1_CLK

SML_PCH_1_ALERT_L

SML_PCH_0_DATA

SML_PCH_0_ALERT_L

SML_PCH_0_CLK

SMBUS_PCH_DATA

PCH_CLK14P3M_REFCLK

SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_SB

SML_PCH_0_ALERT_L

=PP3V3_SUS_GPIO

SML_PCH_1_ALERT_L

=PP3V3_S0_PCH_STRAPS

SATARDRVR_EN

PCIECLKRQ0_L_GPIO73

PEG_B_CLKRQ_L_GPIO56

=PPVRTC_G3_PCH

RTC_RESET_L

LPC_R_AD<0>

LPC_AD<0>

LPC_R_AD<1>

LPC_AD<1>

LPC_R_AD<2>

LPC_AD<2>

LPC_R_AD<3>

LPC_AD<3>

LPC_FRAME_R_L

LPC_FRAME_L

SATA_ODD_D2R_N

JTAG_T29_TMS PCH_SPKR AP_CLKREQ_L PCH_SATALED_L EXCARD_CLKREQ_L

=PP3V3_T29_PCH_GPIO

T29_CLKREQ_L PEG_CLKREQ_L

=PP3V3_S0_PCH_STRAPS

PCIECLKRQ2_L_GPIO20

WOL_EN

TP_PCIE_CLK100M_PE7N

ITPXDP_CLK100M_N

=PP3V3_SUS_GPIO

HDA_SYNC_R

=PP3V3R1V5_S0_PCH_VCCSUSHDA

HDA_SDOUT_R

U1800

A37 A39 C39 C37

K40

H35

K35 M35

F35

D36 B36 C35 A35

K37

H37

K22

C21

M17

U12

M12

M15

H40 F37

F19

A19 C19

M2

AN3 AN1 AU3 AU1

R1

AN6 AN8 AR3 AR1

AD4 AD2 AL3 AL1

AF12

AH4

AF10

AD8 AD6 AG3 AG1

AE3 AE1 AH8 AH6

AC3 AC1 AJ3 AJ1

AB12

AB10

W10

Y4

AD12

AB8

AB6

Y2

W8

N1

A23

U1800

L3

J1

M8

BD17 BF17

M24 K24

BB26 AY26

E51

AK8 AK6

BB24 AY24

AN10 AN12

AR12 AR10

AD48 AD50

AE49 AE51

AD40 AD42

AA49 AA51

Y48 Y50

AB40 AB42

AB44 AB46

W44 W46

AF44 AF46

AF40 AF42

H50

D48

G49

J51

M4

U8

T4

B8

M19

K8

J3

H4

R8

C4

BJ33

BJ35

BH36

BJ37

BJ39

BH40

BJ41

BJ43

BL33

BL35

BK36

BL37

BL39

BK40

BL41

BL43

BB30

BB33

BF33

BD35

AY35

BD37

AY37

AY40

AY30

AY33

BD33

BF35

BB35

BF37

BB37

BB40

J49

H12

F17 F10

H22

K12 A9

C9

D12 C11

AC49

W49 W51

R1876

1

2

R1811

12

R1810

12

R1813

12

R1812

12

R1842

1

2

R1834

1

2

R1844

1

2

R1833

1

2

R1847

1

2

R1849

1

2

R1845

1

2

R1846

1

2

R1848

1

2

R1866

1

2

R1800

1

2

R1880

12

R1853

1

2

R1855

1

2

R1854

1

2

R1888

12

R1841

12

R1840

12

R1850

1

2

R1851

1

2

R1860

12

R1864

12

R1861

12

R1862

12

R1863

12

R1820

1

2

R1830

1

2

R1899

1

2

R1877

1

2

R1878

1

2

R1831

1

2

R1832

1

2

R1803

1

2

R1802

1

2

R1801

1

2

C1803

1

2

C1802

1

2

R1871

1

2

R1870

1

2

R1885

12

R1886

1

2

R1890

1

2

18 OF 109

3.13.0

051-8870

16 OF 75

IN

OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

ACPRESENT/GPIO31

SUSWARN*/SUSPWRDNACK/GPIO30

DPWROK

DMI3RXP

DMI2RXP

DMI1RXP

DMI0RXP

RSMRST*

APWROK

PWRBTN*

SLP_S3*

DMI_IRCOMP

DMI0TXN

DMI2RXN

DRAMPWROK

FDI_RXN6 FDI_RXN7

FDI_RXP0

FDI_RXP3

FDI_RXP1 FDI_RXP2

FDI_RXP5

FDI_RXP4

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_LSYNC0

FDI_FSYNC1

FDI_LSYNC1

WAKE*

CLKRUN*/GPIO32

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S5*/GPIO63

SLP_S4*

SLP_A*

SLP_LAN*/GPIO29

PMSYNCH

DSWVRMEN

SLP_SUS*

SUSACK*

DMI2TXN

DMI1TXN

DMI0TXP

DMI3TXN

DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

SYS_RESET*

SYS_PWROK

PWROK

BATLOW*/GPIO72

RI*

FDI_RXN0 FDI_RXN1

FDI_RXN3

FDI_RXN2

FDI_RXN4 FDI_RXN5

DMI0RXN

DMI3RXN

FDI_RXP6

DMI2RBIAS

DMI1RXN

FDI

DMI

SYSTEM POWER

MANAGEMENT

(3 OF 10)

L_VDD_EN

L_DDC_DATA

L_DDC_CLK

L_CTRL_DATA

L_CTRL_CLK

L_BKLTEN

L_BKLTCTL

LVD_VREFL

LVD_VREFH

LVD_VBG

LVD_IBG

LVDSB_DATA_3*

LVDSB_DATA_2*

LVDSB_DATA_1*

LVDSB_DATA_0*

LVDSB_DATA3

LVDSB_DATA2

LVDSB_DATA1

LVDSB_DATA0

LVDSB_CLK* LVDSB_CLK

LVDSA_DATA_3*

LVDSA_DATA_2*

LVDSA_DATA_1*

LVDSA_DATA_0*

LVDSA_DATA3

LVDSA_DATA2

LVDSA_DATA1

LVDSA_DATA0

LVDSA_CLK* LVDSA_CLK

SDVO_TVCLKINP

SDVO_TVCLKINN

SDVO_STALLP

SDVO_STALLN

SDVO_INTP

SDVO_INTN

SDVO_CTRLDATA

SDVO_CTRLCLK

DDPB_AUXN DDPB_AUXP

DDPB_0N

DDPB_HPD

DDPB_0P DDPB_1N DDPB_1P

DDPB_2P

DDPB_2N

DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_1P

DDPC_0P DDPC_1N

DDPC_2P

DDPC_2N

DDPC_3P

DDPC_3N

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXP

DDPD_AUXN

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N

DDPD_3N

DDPD_2P

DDPD_3P

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC

DAC_IREF

CRT_VSYNC

CRT_IRTN

LVDS

CRT

DIGITAL DISPLAY INTERFACE

(4 OF 10)

NC NC

NC

NC NC NC NC

NC

NC NC

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Set to Vss when Low

DF_TVS:DMI & FDI Term Voltage

.

Set to Vcc when High

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

0

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

NOSTUFF

201

1K

1/20W

1% MF

1K

MF 201

1% 1/20W

10K

MF

201

5%

1/20W

PLACE_NEAR=U1800.BF19:12.7mm

49.9

MF 201

1% 1/20W

750

MF 201

1% 1/20W

PLACE_NEAR=U1800.BK20:2.54mm

100K

MF 201

5% 1/20W

390K

MF

201

5%

1/20W

5%

201

MF

10K

MF

201

1/20W

10K

5%

MF

1/20W

5%

8.2K

201

PLACE_NEAR=U1800.R51:2.54mm

1K

MF 201

5% 1/20W

201

1/20W

100K

5% MF

PCH DMI/FDI/GRAPHICS

TP_DP_IG_D_MLP<1>

FDI_DATA_N<5>

FDI_DATA_N<4>

FDI_DATA_N<3>

PM_CLKRUN_L

PM_PWRBTN_L

PM_SLP_SUS_L

PCH_DSWVRMEN

=PP3V3_S0_PCH_STRAPS

PCH_DMI_COMP

=PP1V05_S0_PCH_VCCIO_PCIE

=T29_WAKE_L

MAKE_BASE=TRUE

PCIE_WAKE_L

PCH_SUSACK_L

FDI_FSYNC<0>

FDI_LSYNC<0> FDI_LSYNC<1>

PM_CLKRUN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_S4_L

PCH_SUSACK_L

FDI_DATA_P<1>

LVDS_IG_BKL_PWM

PM_PCH_SYS_PWROK

FDI_DATA_P<4> FDI_DATA_P<5> FDI_DATA_P<6>

FDI_INT

FDI_DATA_P<2>

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_INTP

TP_SDVO_INTN

DP_IG_B_DDC_DATA

DP_IG_B_DDC_CLK

DP_IG_B_AUX_N DP_IG_B_AUX_P

TP_DP_IG_B_MLN<0>

DP_IG_B_HPD

TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1> TP_DP_IG_B_MLP<1>

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<3> TP_DP_IG_B_MLP<3>

TP_DP_IG_C_CTRL_CLK TP_DP_IG_C_CTRL_DATA

TP_DP_IG_C_AUXN TP_DP_IG_C_AUXP TP_DP_IG_C_HPD

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<0> TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLP<3>

TP_DP_IG_C_MLN<3>

TP_DP_IG_D_CTRL_CLK TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_AUXP

TP_DP_IG_D_AUXN

TP_DP_IG_D_HPD

TP_DP_IG_D_MLN<0> TP_DP_IG_D_MLP<0> TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLP<3>

TP_CRT_IG_BLUE TP_CRT_IG_GREEN TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK TP_CRT_IG_DDC_DATA

TP_CRT_IG_HSYNC

PCH_DAC_IREF

TP_CRT_IG_VSYNC

=PPVRTC_G3_PCH

FDI_FSYNC<1>

LPC_PWRDWN_L

PM_DSW_PWRGD

PM_BATLOW_L

PCH_DMI2RBIAS

PM_SYNC

GPIO29_SLP_LAN_L

FDI_DATA_P<7>

FDI_DATA_P<3>

FDI_DATA_N<2>

FDI_DATA_N<1>

FDI_DATA_N<0>

FDI_DATA_N<7>

FDI_DATA_N<6>

FDI_DATA_P<0>

SMC_ADAPTER_EN

PCH_SUSWARN_L

DMI_N2S_P<2>

DMI_N2S_P<1>

DMI_N2S_P<0>

PM_RSMRST_L

PM_PCH_APWROK

PM_PWRBTN_L

DMI_N2S_N<2>

PM_MEM_PWRGD

DMI_S2N_N<2>

DMI_S2N_P<0>

DMI_S2N_N<3>

PM_SYSRST_L

PM_PCH_PWROK

DMI_N2S_N<0>

DMI_N2S_N<3>

DMI_N2S_N<1>

=PP3V3_S5_PCH

LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR

TP_PM_SLP_A_L

PM_SLP_S3_L

DMI_S2N_P<2>

DMI_S2N_P<1>

PCH_RI_L

DMI_N2S_P<3>

DMI_S2N_N<0> DMI_S2N_N<1>

DMI_S2N_P<3>

=PP3V3_SUS_GPIO

GPIO29_SLP_LAN_L PM_BATLOW_L

=PP3V3_SUS_GPIO

PCH_SUSWARN_L

=PP3V3_SUS_GPIO

PCIE_WAKE_L

PCH_SUSWARN_L

U1800

H19

G3

H10

T2

BL21

BJ21

BD22

BF22

BL23

BJ23

BB22

AY22

BK20

BJ19

BL19

BB19

AY19

BL17

BJ17

BB17

AY17

BD19

BF19

A21

B12

F22

BH12 BK8

BB10

BK12 BH8

BL13 BJ15 BD12 BJ11 AY15 AY12 BJ9 BF10

BJ13 BL15 BF12 BL11 BB15 BB12 BL9 BD10

BB8

K19

M22

F12

B20

C7

A7

D4

K10

F6

A15

G6

F15

D3

C13

M10

L1 D8

U1800

M46

R49 N49

R46

M50

T48

U46

N51

R51

AY48 AY50 AY44 AY46 BB44

BB46

BA49 BA51

AW51 AW49 AY42

BC49 BC51 BD48 BD50 BF46 BF45 BE49 BE51

AU51 AU49

T50 U44

BE46

BG51 BG49 BF42 BD42 BJ47 BL47 BL45 BJ45

AU46 AU44

M48 U42

BK44

L49

M44

R42 M40

L51 K46

M42

AH42 AH40

AG51 AG49

AK46

AK44

AR44 AN51 AN46 AK42

AR46 AN49 AN44 AK40

AH44

AH46

AM48 AL51 AJ49 AH48

AM50 AL49 AJ51 AH50

W42 R44

AT50 AT48

AR51 AR49

AU40 AU42

R1986

12

R1984

1

2

R1925

1

2

R1985

1

2

R1905

1

2

R1900

1

2

R1920

1

2

R1909

1

2

R1915

1

2

R1983

1

2

R1982

1

2

R1991

1

2

R1951

1

2

R1955

1

2

19 OF 109

3.13.0

051-8870

17 OF 75

IN

BI

IN

TP20

TP19

TP18

TP17

TP16

TP15

TP14

TP13

TP12

TP11

TP10

TP9

TP8

TP7

TP6

TP5

TP4

TP3

TP2

TP1

RSVD_BE3 RSVD_BE1 RSVD_AU8 RSVD_BJ7

RSVD_BH3

RSVD_BA3

RSVD_AU6

RSVD_AW1

RSVD_AW3

RSVD_AY6 RSVD_AY2 RSVD_AY4

RSVD_BC1

RSVD_BC3

RSVD_BG1 RSVD_BG3 RSVD_BE6

RSVD_BF7

RSVD_BH4

RSVD_BJ4 RSVD_BJ5 RSVD_BK6

DF_TVS

RSVD_AY8

RSVD_BL5

RSVD_BB6

RSVD_BD2 RSVD_BD4

RSVD_BF6

RSVD_BA1

USBP0N

USBP1N

USBP0P

USBP1P

USBP2N USBP2P

USBP3N USBP3P

USBP4N USBP4P

USBP5N USBP5P

USBP6N USBP6P

USBP7N USBP7P

USBP8N USBP8P

USBP9N USBP9P

USBP10N USBP10P

USBP11P

USBP11N

USBP12N USBP12P

USBP13P

USBP13N

USBRBIAS*

USBRBIAS

TP22

TP21

TP23 TP24 TP41 TP42

TP25 TP26 TP27 TP28 TP29

TP31

TP30

TP32 TP33 TP34 TP35 TP36 TP37 TP38

TP40

TP39

PIRQB*

PIRQA*

PIRQC*

REQ1*/GPIO50

PIRQD*

REQ2*/GPIO52 REQ3*/GPIO54

GNT1*/GPIO51 GNT2*/GPIO53

PIRQE*/GPIO2

GNT3*/GPIO55

PIRQH*/GPIO5

PIRQG*/GPIO4

PIRQF*/GPIO3

PME*

CLKOUT_PCI0

PLTRST*

CLKOUT_PCI2 CLKOUT_PCI3

CLKOUT_PCI1

CLKOUT_PCI4

OC1*/GPIO40

OC0*/GPIO59

OC2*/GPIO41 OC3*/GPIO42 OC4*/GPIO43

OC5*/GPIO9 OC6*/GPIO10 OC7*/GPIO14

TP

RSVD

PCI

USB

(5 OF 10)

NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC NC NC NC

NC

NC NC

NC

NC NC

NC

BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

ON AP_PWR_EN IF ISOLATION RESISTOR R2090 IS UNSTUFFED

NOTE: PULLUP IS REQUIRED

FIXME: NEED INTEL APPROVAL OF NC ON TPS

PUs TO S0 INSTEAD?

USB HUB 1

Unused

USB HUB 2

Unused

Camera

Unused

NOSTUFF

201

10K

1/20W

PCI_INTD_L

PCI_INTC_L

PCI_INTA_L

PCH_PCI_GNT3_L

TP_PCI_CLK33M_OUT3

10K

5% MF

201

PCH PCI/FLASHCACHE/USB

NC_USB_4P

NC_USB_4N

AP_PWR_EN

=PP3V3_SUS_GPIO

=PP3V3_S3_PCH_GPIO

PCH_PCI_GNT3_L

USB_HUB2_UP_N

SDCONN_STATE_RST_L

PCH_CLK33M_PCIOUT

LPC_CLK33M_LPCPLUS_R TP_PCI_CLK33M_OUT2

PLT_RESET_L

LPC_CLK33M_SMC_R

TP_PCI_PME_L

AUD_IP_PERIPHERAL_DET

AUD_I2C_INT_L

PCI_INTE_L

PCH_PCI_GNT2_L

PCH_PCI_GNT1_L

PCI_REQ3_L

T29_A_HV_EN_L

JTAG_GMUX_TMS

PCI_INTB_L

PCH_USB_RBIAS

NC_USB_13N NC_USB_13P

NC_USB_12P

NC_USB_12N

NC_USB_11N NC_USB_11P

NC_USB_10P

NC_USB_10N

USB_CAMERA_P

USB_CAMERA_N

USB_HUB2_UP_P

NC_USB_7P

NC_USB_7N

NC_USB_6P

NC_USB_6N

NC_USB_5P

NC_USB_5N

NC_USB_3P

NC_USB_3N

NC_USB_2P

NC_USB_2N

NC_USB_1P

USB_HUB1_UP_P

NC_USB_1N

USB_HUB1_UP_N

TP_PM_TEST_RST_L

PCH_DF_TVS

CPU_PROC_SEL_L

=PP1V8_S0_PCH_VCC_DFTERM

=PP3V3_S0_PCH_GPIO

T29_MCU_INT_L

PCH_PCI_GNT2_L PCH_PCI_GNT1_L

PCH_GPIO10_OC6_L

SDCONN_STATE_CHANGE

PCH_GPIO43_OC4_L

PCH_GPIO14_OC7_L

ENET_PWR_EN

USB_HUB_SOFT_RESET_L

PCH_GPIO59_OC0_L

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

25

69 25

25

26 25

24 68

1K

1/20W

MF

5%

201

1/20W

MF

5%

0

10K

MF201 5%

1/20W

10K

MF201 5%

1/20W

10K

MF201 5%

1/20W

10K

MF201 5%

1/20W

10K

MF201 5%

1/20W

10K

MF201 5%

1/20W

10K

MF201 5%

1/20W

MF201 5%

201 MF5%

1/20W

MF

10K

5%

1/20W

PLACE_NEAR=U1800.C33:2.54mm

22.6

MF

201

1%

1/20W

2.2K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

10K

MF 201

5% 1/20W

10K

MF

201

5%

1/20W

10K

MF 201

5% 1/20W

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

MF 201

5% 1/20W

10K

NOSTUFF

1/20W

5%

201

MF

10K

NOSTUFF

10K

MF

201

5%

1/20W

NOSTUFF

10K

MF

201

5%

1/20W

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

39

6

63

39

6

U1800

G51 E49 H48 J43 G45

BC7

F42 H42 D44

C17 A17 A13 D16 A11 B16 C23 H15

D49 C48 C47 C45

A47 C41 F45 F40

F7

H2

G46 K44

F46

AU6

AU8

AW1

AW3

AY2 AY4

AY6

AY8

BA1

BA3

BB6

BC1

BC3

BD2 BD4

BE1

BE3

BE6

BF6

BF7

BG1 BG3

BH3

BH4

BJ4 BJ5

BJ7

BK6

BL5

BH24

D20 M30

E3 AM4 AT4 AT2

AD10

B24 D24

AD44

BK24

AD46

BJ48

BL7 W40 K30

BJ25 BJ27 BJ31 BJ29 BL25

BH20

BL27 BL31 BL29 BF26 BB28 BF28 BF30 BD26 AY28 BD28

BK16

BD30

BH49 BB42

BH16 AN42 AN40 AR40 AR42

F24 H24

C31 A31

H33 F33

H30 F30

M33 K33

C25 A25

C27 A27

H28 F28

M26 K26

D28 B28

H26 F26

D32 B32

M28 K28

C29 A29

A33

C33

R2054

1

2

R2053

1

2

R2052

1

2

R2068

1

2

R2069

1

2

R2065

1

2

R2067

1

2

R2064

1

2

R2062

1

2

R2061

1

2

R2060

1

2

R2081

1

2

R2070

1

2

R2015

12

R2031

12

R2030

12

R2018

12

R2017

12

R2016

12

R2013

12

R2012

12

R2011

12

R2010

12

R2090

12

R2080

12

20 OF 109

3.13.0

051-8870

18 OF 75

19 17 16

7

19

7

18

23

6

18

68

7

18

23

OUT

BI

IN

OUT

IN

BI

IN

INIT3_3V*

PROCPWRGD THRMTRIP*

RCIN*

PECI

TACH1/GPIO1 TACH2/GPIO6

BMBUSY*/GPIO0

TACH7/GPIO71

TACH6/GPIO70

GPIO57

TACH4/GPIO68

SDATAOUT1/GPIO48 SATA5GP/GPIO49

SDATAOUT0/GPIO39

SLOAD/GPIO38

SATA2GP/GPIO36

GPIO35

GPIO28

GPIO27

SCLOCK/GPIO22 GPIO24/MEM_LED

TACH0/GPIO17

GPIO8 LAN_PHY_PWR_CTRL/GPIO12

TACH3/GPIO7

A20GATE

SATA4GP/GPIO16

GPIO15

STP_PCI*/GPIO34

TACH5/GPIO69

SATA3GP/GPIO37

VSS_NCTF_A4

VSS_NCTF_A48

VSS_NCTF_A5

VSS_NCTF_A49

VSS_NCTF_BH51

VSS_NCTF_A51 VSS_NCTF_BH1

VSS_NCTF_BJ3

VSS_NCTF_BJ1

VSS_NCTF_BJ49

VSS_NCTF_BL1

VSS_NCTF_BJ51

VSS_NCTF_BL3 VSS_NCTF_BL4

VSS_NCTF_BL48

VSS_NCTF_BL51

VSS_NCTF_BL49

VSS_NCTF_C3 VSS_NCTF_C49 VSS_NCTF_C51

VSS_NCTF_D51

VSS_NCTF_D1

VSS_NCTF_E1

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

NCTF

GPIO

CPU

MISC

(6 OF 10)

Y

A

B

08

Y

A

B

08

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

GPIO[68:71] have 15K-45K internal PUs

ALL RSVD TPs NC-ed per INTEL approval

(IPU)

This has internal pull up and should not pulled low.

(NC-ed per Intel chklist)

(PU necessary?)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(PUs necessary?)

(PU necessary?)

OMIT_TABLE

COUGAR-POINT

MOBILE-SFF

FCBGA

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K10K

MF

201

5%

1/20W

5%

201

MF

10K

DRAM_CFG3:H

MF

1/20W

5%

201

10K

DRAM_CFG2:H

1/20W

5%

201

MF

10K

DRAM_CFG1:H

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

DRAM_CFG0:H

1/20W

5%

201

MF

10K10K

MF

201

5%

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

100K

10K

MF

201

5%

1/20W

201

MF

10K

5%

NOSTUFF

1K

MF

201

5%

1/20W

NOSTUFF

10K

MF

201

5%

1/20W

NOSTUFF

10K

MF

201

5%

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

1/20W

5% MF

20K

201

100K

5%

1/20W

MF

201

10K

MF

201

5%

1/20W

5%

201

MF

10K

201MF1/20W

5%

0

1/20W

5%

201

MF

390

MF

201

5%

1/20W

NOSTUFF

43

1/20W

5%

201

MF

10K

201

1K

MF

1/20W

5%

DRAM_CFG0:L

201

5%

1/20W

MF

1K

DRAM_CFG1:LDRAM_CFG2:L

201

1K

5% 1/20W MF

201

1K

MF

1/20W

5%

DRAM_CFG3:L

74LVC2G08GT

SOT833

74LVC2G08GT

SOT833

0.1UF

10%

0201

X5R-CERM

16V

NOSTUFF

10K

201

MF

5%

1/20W

0

201

5%

MF

1/20W

PCH MISC

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

MLB_RAM_CFG1

T29_PWR_EN

AUD_IPHS_SWITCH_EN_PCH

AUD_IPHS_SWITCH_EN_PCH_R

MLB_RAM_CFG2

MLB_RAM_CFG3

MLB_RAM_CFG1

PCH_GPIO46

WOL_EN

=PP3V3_SUS_GPIO

ENET_LOW_PWR

T29_SW_RESET_L

PCH_INIT3V3_L

MLB_RAM_CFG2

PCH_GPIO12

FW_PWR_EN

MLB_RAM_CFG3

MLB_RAM_CFG0

SMC_IG_THROTTLE_L FW_PME_L

PCH_INIT3V3_L

T29_PWR_EN_PCH

SPIROM_USE_MLB

=PP3V3_S0_PCH

JTAG_ISP_TCK

PCH_GPIO36_SATA2GP

PCH_GPIO35

ENET_LOW_PWR

PM_PCH_PWROK

AUD_IPHS_SWITCH_EN

ISOLATE_CPU_MEM_L

ODD_PWR_EN_L

LPCPLUS_GPIO

AUD_IPHS_SWITCH_EN_PCH

PCH_GPIO15

NC_GPIO8

SMC_RUNTIME_SCI_L

GMUX_INT

PCH_GPIO12

=PP3V3_S5_PCH

=PP3V3_T29_PCH_GPIO

SMC_SCI_L

PCH_GPIO24

SMC_SCI_L

T29_SW_RESET_L

JTAG_ISP_TDO JTAG_ISP_TDI

=PP3V3_SUS_GPIO

ODD_PWR_EN_L

MLB_RAM_CFG3 MLB_RAM_CFG2 MLB_RAM_CFG1

=PP3V3_S0_PCH_STRAPS

MLB_RAM_CFG0

FW_PME_L

=PP3V3_S3_PCH_GPIO

=PP3V3_S0_PCH_STRAPS

SMC_RUNTIME_SCI_L

PM_THRMTRIP_L

CPU_PWRGD

PCH_PROCPWRGD PM_THRMTRIP_L_R

PCH_RCIN_L

PCH_PECI CPU_PECI

=PP3V3_S0_PCH

PCH_A20GATE

JTAG_ISP_TCK

GMUX_INT

SPIROM_USE_MLB

PCH_GPIO24

ISOLATE_CPU_MEM_L

JTAG_ISP_TDO

FW_PWR_EN

=PP3V3_S0_PCH_STRAPS

SMC_IG_THROTTLE_L

MLB_RAM_CFG0

PCH_GPIO36_SATA2GP

=PP3V3_T29_PCH_GPIO

JTAG_ISP_TDI

U1800

U3W1

K6

K15 C15

G1

W12

K17

H17

R6C5

U40

AU12

AU10

U6

W6 M6

AA3

AA1

W3

U10

U1

N3

R3

B44

B40 C43 A45

K42 A43 D40 A41

BC9

AK10 AH12 AK12 AH10

A4 A48 A49 A5 A51 BH1 BH51 BJ1 BJ3 BJ49 BJ51 BL1 BL3 BL4 BL48 BL49 BL51 C3 C49 C51 D1 D51 E1

R2186

1

2

R2185

1

2

R2184

1

2

R2115

1

2

R2114

1

2

R2172

1

2

R2173

1

2

R2174

1

2

R2160

1

2

R2175

1

2

R2113

1

2

R2112

1

2

R2194

1

2

R2193

1

2

R2192

1

2

R2191

1

2

R2130

1

2

R2197

1

2

R2110

1

2

R2196

1

2

R2198

1

2

R2111

1

2

R2190

1

2

R2150

1

2

R2155

1

2

R2140

12

R2156

12

R2170

12

R2199

1

2

R2165

1

2

R2164

1

2

R2163

1

2

R2162

1

2

U2150

5

6

4

8

3

U2150

1

2

4

8

7

C2152

1

2

R2195

1

2

R2152

12

21 OF 109

3.13.0

051-8870

19 OF 75

NC

VCCTX_LVDS_AG37

VSSALVDS_AC33

VCCALVDS_AG33

VCCALVDS_AF33

VSSADAC

VCCADAC

VCCDFTERM_AL13

VCCDFTERM_AK15

VCCSPI

VCCDFTERM_AJ15

VCCDFTERM_AJ13

VCCDMI_AM23

VCCCLKDMI

VCCVRM_AW21

VCCVRM_AU21

VCC3_3_U37

VCC3_3_T39

VCCTX_LVDS_AJ37

VCCTX_LVDS_AG39

VCCDMI_AU15 VCCDMI_AW16

VCCIO_AK21

VCCAFDIPLL_AP13 VCCAFDIPLL_AP15

VCCVRM_AW18

VCCVRM_AU19

VCCIO_AW34

VCC3_3_BK28

VCCIO_AU35

VCCIO_AU29

VCCIO_AU27

VCCIO_AU25

VCCIO_AU23

VCCIO_AR27 VCCIO_AR29

VCCIO_AR25

VCCIO_AR23

VCCIO_AR15 VCCIO_AT13

VCCIO_AM21

VCCAPLLEXP

VCCCORE_AM33 VCCCORE_AM35

VCCCORE_AK33

VCCCORE_AK31

VCCCORE_AK29

VCCCORE_AJ29 VCCCORE_AJ31

VCCCORE_AJ27

VCCCORE_AJ25

VCCCORE_AJ23

VCCCORE_AG27 VCCCORE_AJ21

VCCCORE_AG25

VCCCORE_AG23

VCCCORE_AG21

VCCCORE_AF21 VCCCORE_AF23

VCCCORE_AE23

VCCCORE_AE21

VCCCORE_AB21

VCCTX_LVDS_AF37

VSSALVDS_AE33

VCCCORE_AC23

VCCCORE_AC21

VCCCORE_AB23

(7 OF 10)

VCC CORE

VCCIO

FDI

NAND/SPI

DMI

HVCMOS

LVDS

CRT

NC

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3_V37 VCC3_3_V39

VCCAPLLDMI2

VCCIO_AP27

DCPSUS_V13

DCPSUS_AR33 DCPSUS_AU33

VCCASW_AB27

VCCASW_AB31

VCCASW_AB29

VCCASW_AC27 VCCASW_AC29 VCCASW_AC31 VCCASW_AE27 VCCASW_AE29 VCCASW_AE31

VCCASW_V21

VCCASW_U21

VCCASW_V23 VCCASW_V25 VCCASW_Y21

VCCASW_Y25

VCCASW_Y23

VCCASW_Y27 VCCASW_Y29 VCCASW_Y31

DCPRTC_R15 DCPRTC_U15

VCCVRM_AC39

VCCADPLLA VCCADPLLB

VCCIO_AJ17

VCCDIFFCLKN_AC37 VCCDIFFCLKN_AE37 VCCDIFFCLKN_AE39

VCCSSC DCPSST

V_PROC_IO

VCCRTC

VCCSUSHDA

VCCASW_V19

VCCASW_R19

VCCASW_U19

VCCIO_AC15

VCCIO_AC13

VCCIO_AB15

VCCVRM_AF17

VCCVRM_AE19

VCCAPLLSATA

VCCIO_AF15

VCCIO_AG15

VCCIO_AG13

VCCIO_AA13

VCC3_3_AF6

VCC3_3_R40

VCC3_3_AC19

VCC3_3_AB19

VCCSUS3_3_U35

VCCSUS3_3_U33

VCCSUS3_3_R35

VCCSUS3_3_R33

V5REF

VCCSUS3_3_AM27

DCPSUS_AU31

V5REF_SUS

VCCIO_N18

VCCSUS3_3_N27

VCCSUS3_3_U29

VCCSUS3_3_U27

VCCSUS3_3_R29

VCCSUS3_3_R27

VCCIO_U25

VCCIO_U23

VCCIO_R25

VCCIO_R23

PCI/GPIO/LPC

SATA

CLOCK/MISC

USB

FUSE

HDA

RTC CPU

(8 OF 10)

NC

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

VCCACLK pin left as NC per DG

AL24 left as NC per DG

1.44 A Max, 474mA Idle

55mA Max, 5mA Idle

VCCAPLLDMI2 pin left as NC per DG

(PCH DPLLA PWR)

(PCH DPLLB PWR)

69 mA

VCCAFDIPLL pin left as NC per DG

PCH VCCADPLLA Filter

68 mA

VCCAPLLSATA pin left as NC per DG

NC-ed per DG

PCH VCCADPLLB Filter

PCH output, for decoupling only

10 mA Max, 1mA Idle

0.1UF

16V X5R-CERM 0201

10%

PLACE_NEAR=U1800.N16:2.54mm

CERM

6.3V

10%

402

1UF

PLACE_NEAR=U1800.N16:2.54mm

10%

0201

X5R-CERM

16V

PLACE_NEAR=U1800.U17:2.54mm

0.1UF

10%

0201

X5R-CERM

16V

PLACE_NEAR=U1800.R15:2.54mm

0.1UF

1/16W

5%

402

MF-LF

0

1/16W

5%

402

MF-LF

0

0.1UF

16V X5R-CERM 0201

10%

PLACE_NEAR=U1800.N16:2.54mm

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.BF40:2.54MM

6.3V

10%

402

CERM

1UF

PLACE_NEAR=U1800.BF40:2.54MM

16V X5R-CERM 0201

10%

0.1UF

16V X5R-CERM 0201

10%

0.1UF

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

FCBGA

MOBILE-SFF

COUGAR-POINT

OMIT_TABLE

PCH POWER

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLB

PP1V05_S0_PCH_VCCADPLLA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLA

=PP3V3_S5_PCH_VCCDSW

TP_PPVOUT_PCH_DCPSUSBYP

PP3V3_S0_PCH_VCC3_3_CLK_F

=PP1V05_S0_PCH_VCCIO_CLK

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

=PP1V8R1V5_S0_PCH_VCCVRM

PP1V05_S0_PCH_VCCADPLLB

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V05_S0_PCH_VCCSSC

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

=PP1V05_S0_PCH_V_PROC_IO

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCIO_SATA

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP5V_S0_PCH_V5REF

=PP3V3_SUS_PCH_VCCSUS

=PP5V_SUS_PCH_V5REFSUS

=PP1V05_S0_PCH_VCCIO_PLLUSB

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0_PCH_VCCIO_USB

=PP3V3_S0_PCH_VCC3_3_PCI

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCCDMI_FDI

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO_PLLPCIE

TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S5_PCH_VCC_SPI

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP1V8R1V5_S0_PCH_VCCVRM

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V8_S0_PCH_VCC_DFTERM

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_PLLFDI

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PPVRTC_G3_PCH

=PP1V05_S0_PCH_VCCADPLL

C2232

1

2

C2231

1

2

C2222

1

2

C2210

1

2

R2260

12

R2265

12

C2233

1

2

C2261

1

2

C2266

1

2

C2260

1

2

C2265

1

2

U1800

BK28

T39

U37

U51

AP13 AP15

AF33 AG33

AP19

AP39

AB21 AB23 AC21 AC23 AE21 AE23 AF21 AF23 AG21 AG23 AG25 AG27 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AK29 AK31 AK33 AM33 AM35

AJ13 AJ15 AK15 AL13

AM23

AU15 AW16

AK21

AM21

AR15

AR23 AR25 AR27 AR29

AT13

AU23 AU25 AU27 AU29

AU35 AW34

Y19

AF37 AG37 AG39 AJ37

AU19

AU21

AW18

AW21

V50

AC33 AE33

U1800

R15 U15

U17

AR33

AU31

AU33

V13

R10

N36

M37

AM17

AB19 AC19

AF6

R40

V37 V39

AC51

BF40 BD40

AW31

AM2

AB27 AB29 AB31 AC27 AC29 AC31 AE27 AE29 AE31

R19

U19

U21

V19

V21 V23 V25 Y21 Y23 Y25 Y27 Y29 Y31

AC37 AE37 AE39

R12

AA13

AB15 AC13 AC15

AF15

AG13 AG15

AJ17

AP27

N18

R23 R25 U23 U25

N16

AC35

AM27

N27

R27 R29

R33 R35

U27 U29

U33 U35

V31

AC39

AE19 AF17

22 OF 109

3.13.0

051-8870

20 OF 75

20

7

22

7

20 22

7

20

7

20 22

7

16 22

7

22

7

22

7

20 22

7

16 20 22

7

20

7

16 20 22

7

22

7

22

7

22

7

22

7

22

7

22

7

22

7

20

7

22

7

22

7

22

7

22

7

22

7

20

22

7

18 22

22

7

20 22

7

16 22 17 16

7

VSS_G7

VSS_BA7

VSS_B46

VSS_B42

VSS_B38

VSS_B34

VSS_B30

VSS_B26

VSS_B22

VSS_B18

VSS_B14

VSS_B10

VSS_B6

VSS_AY10

VSS_AW45

VSS_AW43

VSS_AW41

VSS_AW39

VSS_AW36

VSS_AW29

VSS_AW27

VSS_AW25

VSS_AW23

VSS_AW13

VSS_AW11

VSS_AW9

VSS_AW7

VSS_AV50

VSS_AV48

VSS_AV4

VSS_AV2

VSS_AU37

VSS_AU17

VSS_AT45

VSS_AT43

VSS_AT41

VSS_AT39

VSS_AT11

VSS_AT9

VSS_AT7

VSS_AR37

VSS_AR35

VSS_AR31

VSS_AR21

VSS_AR19

VSS_AR17

VSS_AR8

VSS_AR6

VSS_AP50

VSS_AP48

VSS_AP45

VSS_AP43

VSS_AP41

VSS_AP37

VSS_AP35

VSS_AP33

VSS_AP31

VSS_AP29

VSS_AP25

VSS_AP23

VSS_AP21

VSS_AP17

VSS_AP11

VSS_AP9

VSS_AP7

VSS_AP4

VSS_AP2

VSS_AM37

VSS_AM31

VSS_AM29

VSS_AM25

VSS_AM19

VSS_AM15

VSS_AL45

VSS_AL43

VSS_AL41

VSS_AL39

VSS_AL11

VSS_AL9

VSS_AL7

VSS_AK50

VSS_AK48

VSS_AK37

VSS_AK35

VSS_AK27

VSS_AK25

VSS_AK23

VSS_AK19

VSS_AK17

VSS_AK4

VSS_AK2

VSS_AJ45

VSS_AJ43

VSS_AJ41

VSS_AJ39

VSS_AJ35

VSS_AJ33

VSS_AJ19

VSS_AJ11

VSS_AJ9

VSS_AJ7

VSS_AH2

VSS_AG45

VSS_AG43

VSS_AG41

VSS_AG35

VSS_AG31

VSS_AG29

VSS_AG19

VSS_AG17

VSS_AG11

VSS_AG9

VSS_AG7

VSS_AF50

VSS_AF48

VSS_AF35

VSS_AF31

VSS_AF29

VSS_AF27

VSS_AF25

VSS_AF19

VSS_AF8

VSS_AF4

VSS_AF2

VSS_AE45

VSS_AE43

VSS_AE41

VSS_AE35

VSS_AE25

VSS_AE17

VSS_AE15

VSS_AE13

VSS_AE11

VSS_AE9

VSS_AE7

VSS_AC45

VSS_AC43

VSS_AC41

VSS_AC25

VSS_AC17

VSS_AC11

VSS_AC9

VSS_AC7

VSS_AB50

VSS_AB48

VSS_AB37

VSS_AB35

VSS_AB33

VSS_AB25

VSS_AB17

VSS_AB4

VSS_AB2

VSS_AA45

VSS_AA43

VSS_AA39

VSS_AA11

VSS_AA9

VSS_AA7

VSS_BB48 VSS_BA31 VSS_BA34 VSS_BA36 VSS_BA39 VSS_BA41 VSS_BA43 VSS_BA45

VSS_BB4 VSS_BB2

VSS_BA11 VSS_BA13 VSS_BA16 VSS_BA18 VSS_BA21 VSS_BA23 VSS_BA25 VSS_BA27 VSS_BA29 VSS_BA9

VSS_AA41

VSS

(9 OF 10)

VSS_G9

VSS_F50

VSS_F48

VSS_F4

VSS_F2

VSS_D46

VSS_D42

VSS_D38

VSS_D34

VSS_D30

VSS_D26

VSS_D22

VSS_D18

VSS_BK46

VSS_BK42

VSS_BK38

VSS_BK34

VSS_BK32

VSS_BK30

VSS_BK26

VSS_D14

VSS_D10

VSS_D6

VSS_BK22

VSS_BK18

VSS_BK14

VSS_BK10

VSS_BH48

VSS_BH46

VSS_BH44

VSS_BH42

VSS_BH38

VSS_BH34

VSS_BH32

VSS_BH30

VSS_BH28

VSS_BH26

VSS_BH22

VSS_BH18

VSS_BH14

VSS_BH10

VSS_BF50

VSS_BF48

VSS_BH6

VSS_BF24

VSS_BF15

VSS_BE45

VSS_BE43

VSS_BE41

VSS_BE39

VSS_BE36

VSS_BE34

VSS_BF4

VSS_BF2

VSS_BE31

VSS_BE29

VSS_BE27

VSS_BE25

VSS_BE23

VSS_BE21

VSS_BE18

VSS_BE16

VSS_BE13

VSS_BE11

VSS_BE9

VSS_BD24

VSS_BD15

VSS_BC45

VSS_BC43

VSS_BC41

VSS_BC39

VSS_BC36

VSS_BE7

VSS_BC31

VSS_BC29

VSS_BC27

VSS_BC25

VSS_BC23

VSS_BC21

VSS_BC18

VSS_BC16

VSS_BC13

VSS_BC11

VSS_BB50

VSS_Y37

VSS_Y35

VSS_Y33

VSS_V45

VSS_V43

VSS_V41

VSS_V35

VSS_V33

VSS_V29

VSS_V27

VSS_V48 VSS_Y15 VSS_Y17

VSS_V7

VSS_V4

VSS_V2

VSS_U49

VSS_U31

VSS_T45

VSS_V9 VSS_V11 VSS_V15 VSS_V17

VSS_T43

VSS_T11

VSS_T9

VSS_T7

VSS_R37

VSS_R31

VSS_R21

VSS_R17

VSS_T13 VSS_T41

VSS_P50

VSS_N45

VSS_N43

VSS_N41

VSS_N39

VSS_N34

VSS_N31

VSS_N29

VSS_P2

VSS_P4 VSS_P48

VSS_N13

VSS_N11

VSS_N9

VSS_N7

VSS_L45

VSS_L43

VSS_L41

VSS_N21 VSS_N23 VSS_N25

VSS_L29

VSS_L27

VSS_L25

VSS_L23

VSS_L21

VSS_L18

VSS_L31 VSS_L34 VSS_L36 VSS_L39

VSS_L16

VSS_L9

VSS_L7

VSS_K50

VSS_K48

VSS_K4

VSS_K2

VSS_J45

VSS_L11 VSS_L13

VSS_J41

VSS_J29

VSS_J27

VSS_J25

VSS_J23

VSS_J21

VSS_J18

VSS_J34 VSS_J36 VSS_J39

VSS_J9

VSS_J7

VSS_G43

VSS_G41

VSS_G39

VSS_G36

VSS_G34

VSS_J11 VSS_J13 VSS_J16

VSS_G25

VSS_G23

VSS_G21

VSS_G18

VSS_G16

VSS_G13

VSS_G11

VSS_G27 VSS_G29 VSS_G31

VSS_J31

VSS_BC34

VSS

(10 OF 10)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

OMIT_TABLE

MOBILE-SFF

COUGAR-POINT

FCBGA

OMIT_TABLE

MOBILE-SFF

COUGAR-POINT

FCBGA

PCH GROUNDS

SYNC_DATE=01/10/2011

SYNC_MASTER=K78_MLB

U1800

AA11 AA39 AA41 AA43 AA45

AA7 AA9

AB17

AB2

AB25 AB33 AB35 AB37

AB4

AB48 AB50

AC11 AC17 AC25 AC41 AC43 AC45

AC7 AC9

AE11 AE13 AE15 AE17 AE25 AE35 AE41 AE43 AE45

AE7 AE9

AF19

AF2

AF25 AF27 AF29 AF31 AF35

AF4

AF48 AF50

AF8

AG11 AG17 AG19 AG29 AG31 AG35 AG41 AG43 AG45

AG7 AG9

AH2

AJ11 AJ19 AJ33 AJ35 AJ39 AJ41 AJ43 AJ45

AJ7 AJ9

AK17 AK19

AK2

AK23 AK25 AK27 AK35 AK37

AK4

AK48 AK50

AL11 AL39 AL41 AL43 AL45

AL7 AL9

AM15 AM19 AM25 AM29 AM31 AM37

AP11 AP17

AP2

AP21 AP23 AP25 AP29 AP31 AP33 AP35 AP37

AP4

AP41 AP43 AP45 AP48 AP50

AP7 AP9

AR17 AR19 AR21 AR31 AR35 AR37

AR6 AR8

AT11 AT39 AT41 AT43 AT45

AT7 AT9

AU17 AU37 AV2 AV4 AV48 AV50

AW11 AW13 AW23 AW25 AW27 AW29 AW36 AW39 AW41 AW43 AW45

AW7 AW9

AY10

B10 B14 B18 B22 B26 B30 B34 B38 B42 B46

B6

BA11 BA13 BA16 BA18 BA21 BA23 BA25 BA27 BA29

BA31 BA34 BA36 BA39 BA41 BA43 BA45

BA7

BA9 BB2

BB4

BB48

G7

U1800

BB50 BC11 BC13 BC16 BC18 BC21 BC23 BC25 BC27 BC29 BC31 BC34 BC36 BC39 BC41 BC43 BC45 BD15 BD24

BE11 BE13 BE16 BE18 BE21 BE23 BE25 BE27 BE29 BE31 BE34 BE36 BE39 BE41 BE43 BE45

BE7 BE9

BF15

BF2

BF24

BF4

BF48 BF50

BH10 BH14 BH18 BH22 BH26 BH28 BH30 BH32 BH34 BH38 BH42 BH44 BH46 BH48

BH6

BK10 BK14 BK18 BK22 BK26 BK30 BK32 BK34 BK38 BK42 BK46

D10 D14 D18 D22 D26 D30 D34 D38 D42 D46

D6

F2

F4 F48 F50

G11 G13 G16 G18 G21 G23 G25 G27 G29 G31

G34 G36 G39 G41 G43

G9

J11 J13 J16 J18 J21 J23 J25 J27 J29 J31 J34 J36 J39 J41 J45

J7 J9

K2 K4 K48 K50

L11 L13 L16 L18 L21 L23 L25 L27 L29 L31 L34 L36 L39 L41 L43 L45

L7 L9

N11 N13 N21 N23 N25 N29 N31 N34 N39 N41 N43 N45

N7 N9

P2 P4 P48 P50 R17 R21 R31 R37

T11 T13 T41 T43 T45

T7 T9

U31 U49

V11 V15 V17

V2

V27 V29 V33 V35

V4

V41 V43 V45 V48

V7 V9

Y15 Y17 Y33 Y35 Y37

23 OF 109

3.13.0

051-8870

21 OF 75

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

PCH VCCIO BYPASS

NEED PWR CONSTRAINT

PCH VCCSUSHDA BYPASS

PCH V5REF Filter & Follower

(PCH Reference for 5V Tolerance on PCI)

1 mA S0-S5

NEED PWR CONSTRAINT

PCH V5REF_SUS Filter & Follower

<1 MA S0-S5

PCH VCCSUS3_3 BYPASS

1 mA

<1 MA

(PCH 1.05V CORE PWR)

(PCH SUSPEND USB 3.3V PWR)

PCH VCCCORE BYPASS

PCH VCCIO BYPASS

(PCH USB 1.05V PWR)

(PCH HD Audio 3.3V/1.5V PWR)

(PCH Reference for 5V Tolerance on USB)

(PCH PCI 3.3V PWR)

PCH VCC3_3 BYPASS

1UF

10% 10V

402

X5R

PLACE_NEAR=U1800.N36:2.54mm

1/20W

5%

201

MF

100

PLACE_NEAR=U1800.M37:2.54mm

10V

20%

402

CERM

0.1UF

SOT-363

BAT54DW-X-G

201

1/20W

5% MF

10

SOT-363

BAT54DW-X-G

X5R-CERM

PLACE_NEAR=U1800.AF6:2.54mm

16V

10%

0201

0.1UF

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.AJ15:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.V31:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AM23:2.54mm

0.1UF

PLACE_NEAR=U1800.BK28:2.54mm

16V

10%

0201

X5R-CERM

PLACE_NEAR=U1800.U27:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.AM17:2.54mm

6.3V

20%

402

X5R

4.7UF

PLACE_NEAR=U1800.AM17:2.54mm

X5R-CERM

16V

10%

0201

0.1UF

PLACE_NEAR=U1800.R27:2.54mm

PLACE_NEAR=U1800.R40:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AC35:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AE37:2.54mm

PLACE_NEAR=U1800.AJ17:2.54mm

6.3V

20%

0201

X5R

1UF

6.3V

1UF

X5R 0201

20%

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0402

CERM-X5R

10UF

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AC13:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.R12:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.Y19:2.54mm

PLACE_NEAR=U1800.AC19:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AG13:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.U23:2.54mm

PLACE_NEAR=U1800.T39:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

6.3V

20%

0402

CERM-X5R

10UF

PLACE_NEAR=U1800.AK33:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AF23:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AC21:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AJ25:2.54mm

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AU25:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AC27:2.54mm

1UF

6.3V

20%

0201

X5R

PLACE_NEAR=U1800.AC27:2.54mm

1UF

6.3V

20%

0201

X5R

1/20W

5%

201

MF

1

20%

6.3V CERM-X5R 0402-1

10UF

PLACE_NEAR=U1800.AP39:2.54mm

X5R-CERM

16V

10%

0201

0.1UF

PLACE_NEAR=U1800.AM17:2.54mm

1/20W

5%

201

MF

0

16V

10%

0201

X5R-CERM

0.01UF

PLACE_NEAR=U1800.U51:2.54mm

10%

X5R-CERM

16V

0201

0.1UF

PLACE_NEAR=U1800.U51:2.54mm

1

MF-LF

402

5%

1/16W

1UF

X5R 0201

20%

6.3V

PLACE_NEAR=U1800.V37:2.54mm

10UH-0.12A-0.36OHM

0603

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.U33:2.54mm

0603

10UH-0.12A-0.36OHM

6.3V

20%

0402

CERM-X5R

10UF

PLACE_NEAR=U1800.U51:2.54mm

6.3V

20%

0402-1

CERM-X5R

10UF

PLACE_NEAR=U1800.V37:2.54mm

0603

X5R-CERM1

6.3V

20%

22UF

0603

X5R-CERM1

6.3V

20%

22UF

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

PCH DECOUPLING

=PP5V_SUS_PCH_V5REFSUS

=PP3V3_S0_PCH

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

PP5V_S0_PCH_V5REF

MAKE_BASE=TRUE

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_CLK

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_F

PP5V_SUS_PCH_V5REFSUS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM VOLTAGE=5V

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH

=PP1V05_S0_PCH_V_PROC_IO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP3V3_S5_PCH_VCC_SPI

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_S0_PCH_VCC3_3_PCI

=PP5V_S0_PCH

=PP5V_S0_PCH_V5REF

PP1V05_S0_PCH_VCCCLKDMI_F

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

=PP3V3_SUS_PCH =PP5V_SUS_PCH

=PP1V05_S0_PCH_VCCIO_USB

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCC_DMI

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V05_S0_PCH_VCCDIFFCLK

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S0_PCH_VCCADAC

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_R

PP3V3_S0_PCH_VCCA_DAC_F

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCASW

C2439

1

2

R2405

12

C2438

1

2

D2400

1

6

R2404

12

D2400

4

3

C2423

1

2

C2440

1

2

C2441

1

2

C2419

1

2

C2421

1

2

C2413

1

2

C2417

1

2

C2416

1

2

C2484

1

2

C2485

1

2

C2463

1

2

C2475

1

2

C2434

1

2

C2469

1

2

C2414

1

2

C2401

1

2

C2452

1

2

C2499

1

2

C2442

1

2

C2486

1

2

C2444

1

2

C2446

1

2

C2424

1

2

C2460

1

2

C2482

1

2

C2481

1

2

C2483

1

2

C2407

1

2

C2429

1

2

C2496

1

2

C2456

1

2

C2426

1

2

R2415

12

C2411

1

2

C2430

1

2

R2450

12

C2455

1

2

C2451

1

2

R2451

12

C2454

1

2

L2451

12

C2476

1

2

L2406

12

C2450

1

2

C2453

1

2

C2420

1

2

C2428

1

2

24 OF 109

3.13.0

051-8870

22 OF 75

5

2

20

19 16

7

20

7

20

7

20

7

20

7

20

7

16

7

20

7

20 16

7

20

7

20

7

20

7

20

7

20

7

20

7

20 16

7

20

7

20 18

7

20 16

7

20

7

20

7

20

7

20

7

IN

OUT

IN

OUT

NC

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

BI

IN

BI

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

PLACEMENT NOTE:

TMS

OBSDATA_C1

DESIGN NOTE:

TRSTn

TDI

OBSDATA_C3

OBSFN_D0

PLACEMENT NOTE:

PLACE TCK/TDI/TMS/TRST* TERM NEAR CPU

TERM NEAR PCH

TDO

ODT AVAILABLE ON JTAG

HOOK1

OBSFN_B0

OBSFN_D1

OBSDATA_D2

OBSDATA_B0

SCL

OBSDATA_D3

XDP_PRESENT#

HOOK2

SDA

OBSDATA_B1

OBSFN_C0

TCK1

PLACEMENT NOTE:

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_B3

PWRGD/HOOK0

HOOK3

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

OBSFN_B1

SNB XDP CONN

PLACE TDO TERM NEAR

PLACE TCK/TDI/TMS/TRST*

OBSFN_A0

OBSDATA_D1

OBSDATA_D0

DBR#/HOOK7

RESET#/HOOK6

VCC_OBS_CD

OBSDATA_A2

OBSDATA_A3

OBSFN_A1 OBSFN_C1

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

OBSDATA_A0

OBSDATA_A1

TCK0

PCH XDP CONN

PLACE TDO TERM NEAR

PLACEMENT NOTE:

VCC_OBS_AB

OBSDATA_B2

OBSDATA_C0

OBSDATA_C2

Even pins should be facing edge of the board

1K series R on PCH Support P. 28

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_B0

OBSDATA_B1

OBSDATA_B2

OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2

HOOK3

SCL

SDA

TCK1

TCK0

XDP_PRESENT#

TMS

TDI

TRSTn

TDO

DBR#/HOOK7

RESET#/HOOK6

VCC_OBS_CD

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1

OBSDATA_D0

OBSFN_D1

OBSFN_D0

OBSDATA_C3

OBSDATA_C2

OBSDATA_C1

OBSDATA_C0

OBSFN_C1

OBSFN_C0

Use with 920-0782 Adapter Flex to support chipset debug

NOTE: This is not the standard XDP pinout

PCH MICRO2-XDP CONNECTOR

Use with 920-0782 Adapter Flex to support chipset debug

NOTE: This is not the standard XDP pinout

PROCESSOR MICRO2-XDP CONNECTOR

998-2516

201

1/20W

MF

PLACE_NEAR=U1000.B50:2.54MM

XDP

5%

1K

XDP

PLACE_NEAR=U1800.AA3:2.54MM

1/20W

201

MF

0

5%

PLACE_NEAR=U1800.A17:2.54MM

5%

MF

201

XDP

1/20W

0

201

1/20W

MF

51

XDP

5%

PLACE_NEAR=U1800.M17:2.54MM

0.1UF

16V

10%

XDP

X5R

402

10%

0.1UF

16V

X5R

XDP

402

201

XDP

1/20W

MF

0

5%

PLACE_NEAR=U4900.D10:2.54MM

201

1/20W

XDP

MF

0

5%

PLACE_NEAR=U4900.D10:2.54MM

910

XDP

5%

1/16W

MF-LF

402

PLACE_NEAR=J2550.39:2.54MM

1K

XDP

5% MF-LF

1/16W

402

201

1/20W

MF

XDP

0

5%

PLACE_NEAR=U1800.B16:2.54MM

PLACE_NEAR=U1800.H4:2.54MM

201

5%

MF

1/20W

0

XDP

PLACE_NEAR=U1800.G1:2.54MM

5%

0

XDP

MF

1/20W

201

PLACE_NEAR=U1800.A13:2.54MM

XDP

1/20W

201

MF

0

5%

MF

201

1/20W

5%

0

XDP

PLACE_NEAR=U1800.D16:2.54MM

201

1/20W

MF

0

PLACE_NEAR=R1841.1:2.54MM

XDP

5%

201

XDP

1/20W

MF

PLACE_NEAR=R1840.1:2.54MM

5%

0

1/20W

201

MF

XDP

1K

5%

PLACE_NEAR=R1125.1:2.54MM

PLACE_NEAR=J2550.52:2.54MM.

MF-LF

51

1/16W

5%

402

XDP

51

PLACE_NEAR=U1800.U12:2.54MM

201

1/20W

MF

XDP

5%

201

1/20W

MF

PLACE_NEAR=U1800.M15:2.54MM

5%

XDP

51

XDP_CPU:BPM

5%

0

MF-LF

1/16W

402

5%

1/16W

402

XDP_CPU:BPM

MF-LF

0

XDP_CPU:BPM

5%

MF-LF

1/16W

0

402

XDP_CPU:BPM

0

5%

MF-LF

1/16W

402

5%

XDP_CPU:CFG

0

MF-LF

1/16W

402

1/16W

402

5%

0

XDP_CPU:CFG

MF-LF

XDP_CPU:CFG

0

5%

1/16W

402

XDP_CPU:CFG

0

5%

MF-LF

1/16W

402

NOSTUFF

1/16W

MF-LF

1K

5%

16V

10%

X5R

XDP

0.1UF

402

XDP_CONN CRITICAL

DF40RC-60DP-0.4V

M-ST-SM

DF40RC-60DP-0.4V

M-ST-SM

XDP_CONN CRITICAL

10%

XDP

0.1UF

X5R

16V

402

1/20W

PLACE_NEAR=U1000.B46:1MM

XDP

201

MF

1K

5%

PLACE_NEAR=J2500.52:2.54MM

51

5%

XDP

MF-LF

1/16W

402

5%

51

XDP

PLACE_NEAR=U1000.M60

MF-LF

1/16W

402

51

5%

XDP

PLACE_NEAR=U1000.L55:2.54MM

MF-LF

1/16W

402

201

1/20W

MF

51

XDP

5%

PLACE_NEAR=U1000.J58:2.54MM

201

MF

1/20W

5%

PLACE_NEAR=U1000.L56:2.54MM

XDP

51

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

CPU & PCH XDP

PCH_GPIO59_OC0_L

USB_HUB_SOFT_RESET_L

XDP_PCH_ENET_PWR_EN

ALL_SYS_PWRGD

SDCONN_STATE_CHANGE

SDCONN_STATE_RST_L

XDP_PCH_SDCONN_DET_L

XDP_BPM_L<6>

CPU_PWRGD

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

=PPVCCIO_S0_XDP

XDP_BPM_L<4>

PM_PWRBTN_L

=PP1V05_SUS_PCH_JTAG

PM_PCH_SYS_PWROK

XDP_CPU_TRST_L

XDP_CPU_TDO

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_CPU_TMS

XDP_PCH_TDO

CPU_CFG<0>

=PP3V3_S0_XDP

=SMBUS_XDP_SCL

XDP_CPU_PWRBTN_L

XDP_CPU_TDI XDP_CPU_TMS

XDP_BPM_L<0>

CPU_CFG<1>

CPU_CFG<7>

XDP_CPU_TDO XDP_CPU_TRST_L

PCH_GPIO14_OC7_L

PCH_GPIO10_OC6_L

PCH_GPIO43_OC4_L

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_B<1>

TP_XDP_PCH_OBSFN_B<0>

XDP_PCH_TMS

XDP_DBRESET_L

TP_XDP_PCH_TRST_L XDP_PCH_TDI

XDP_PCH_TDO

TP_XDP_PCH_HOOK4

TP_XDP_PCH_OBSFN_D<1>

TP_XDP_PCH_HOOK5

CPU_CFG<5>

XDP_CPU_PWRGD

XDP_OBSDATA_B<2> XDP_OBSDATA_B<3>

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_BPM_L<3>

CPU_CFG<10> CPU_CFG<11>

XDP_BPM_L<2>

XDP_VR_READY

PM_PWRBTN_L

CPU_CFG<14>

XDP_BPM_L<1>

ENET_PWR_EN

XDP_PCH_SDCONN_STATE_RST_L

XDP_PCH_PWRBTN_L

AUD_IPHS_SWITCH_EN_PCH

CPU_CFG<6>

XDP_CPU_TDI

XDP_CPU_TCK

XDP_PCH_TDI XDP_PCH_TMS XDP_PCH_TCK

CPU_CFG<12>

=SMBUS_XDP_SDA

CPU_RESET_L

CPU_CFG<16>

CPU_CFG<0>

XDP_DBRESET_L

XDP_CPURST_L

CPU_CFG<4>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<3>

XDP_CPU_TCK

XDP_OBSDATA_B<0> XDP_OBSDATA_B<1>

XDP_PCH_USB_HUB_SOFT_RST_L

XDP_PCH_GPIO59_OC0_L

XDP_PCH_S5_PWRGD

TP_XDPPCH_HOOK2

XDP_PCH_TCK

XDPPCH_PLTRST_L

XDP_PCH_AUD_IPHS_SWITCH_EN

JTAG_ISP_TCK

PCH_GPIO36_SATA2GP

TP_XDP_PCH_OBSFN_A<0> TP_XDP_PCH_OBSFN_A<1>

=PPVCCIO_S0_XDP

CPU_CFG<17>

CPU_CFG<2>

XDP_CPU_CLK100M_P XDP_CPU_CLK100M_N

ENET_LOW_PWR

TP_XDP_PCH_OBSFN_D<0>

SMC_IG_THROTTLE_L

PCH_GPIO15

=PP3V3_S5_XDP

SATARDRVR_EN

DP_AUXCH_ISOL

PCH_GPIO35

XDP_PCH_ISOLATE_CPU_MEM_L

ISOLATE_CPU_MEM_L

XDP_CPU_CFG<0>

CPU_CFG<15>

CPU_CFG<13>

C2501

1

2

R2500

12

R2510

1

2

R2511

1

2

R2512

1

2

R2513

1

2

R2514

1

2

R2501

12

R2579

12

R2580

12

R2556

1

2

C2580

1

2

C2581

1

2

R2502

12

R2585

12

R2504

12

R2584

12

R2581

12

R2582

12

R2578

12

R2586

12

R2587

12

R2515

12

R2516

12

R2505

12

R2550

1

2

R2551

1

2

R2552

1

2

R2560

12

R2561

12

R2562

12

R2563

12

R2564

12

R2566

12

R2567

12

R2565

12

R2540

1

2

C2500

1

2

J2500

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

61

62

6364

78

9

J2550

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

61

62

6364

78

9

25 OF 109

3.13.0

051-8870

23 OF 75

G

D

S

G

D

S

BI

IN

BI

IN

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1* OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2*

SYM VER 1

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1* OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1* PRTPWR2/BC_EN2*

SYM VER 1

BI

NC NC

NC

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

CRITICAL

BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

.

IPU

1 0 Port 1 and 2 are non removable

BOM TABLE

0 0 All ports are removable

NON_REM1 NON_REM0 DESCRIPTION

0 1 Port 1 is non removable

IPU

1 1 Port 1, 2, and 3 are non removable

T29

Trackpad/Keyboard

Right USB A

IPU

LIO External D

SDCARD(NA to K78)

BlueTooth

201

1/20W MF

10K

5%

SOT-363

2N7002DW-X-G

20K

MF

1/20W

5%

201

2N7002DW-X-G

SOT-363

NOSTUFF

201

25V

100PF

CERM

5%

6.3V

0.47UF

CERM-X5R 402

10%

201

25V

NP0-C0G

5%

CRITICAL

18PF

MF

1/20W

5%

1M

CRITICAL

201

NP0-C0G

25V

5%

18PF

CRITICAL

4.7UF

20%

6.3V

X5R-CERM1

402

BYPASS=U2600.23::5mm

201

1/20W

12K

1%

MF

CRITICAL

69 40 6

69 18

69 40 6

69 33

0201

0.1UF

X5R-CERM

16V

10%

0201

20%

6.3V X5R

1UF

201

1/20W MF

10K

5%

X5R-CERM

0.1UF

10% 16V

0201 0201

20%

6.3V X5R

1UF

0201

BYPASS=U2600.29::2mm

16V

10%

X5R-CERM

0.1UF

BYPASS=U2600.5::5mm

20%

4.7UF

6.3V

402

X5R-CERM1

0.1UF

10%

0201

X5R-CERM

16V

BYPASS=U2600.5::2mm

X5R-CERM

0201

16V

0.1UF

10%

BYPASS=U2600.10::2mm

BYPASS=U2600.34::2mm

0.1UF

16V

10%

0201

X5R-CERM

23 18

201

5%

MF

1/20W

100K

8

40 6

201

1/20W

MF

100

5%

SOD-523

BAT54XV2T1

5% 1/20W MF

10K

201 201

10K

MF

5% 1/20W

10K

HUB1_NONREM0_0

5% 1/20W MF 201

5%

10K

1/20W MF 201

HUB1_NONREM0_1

5%

HUB1_NONREM1_1

10K

1/20W

MF

201

5%

10K

HUB1_NONREM1_0

1/20W

MF

201

0201

X5R

20%

6.3V

1UF

0201

X5R-CERM

0.1UF

10% 16V

0201

6.3V

1UF

X5R

20%

0201

X5R-CERM

10% 16V

0.1UF

10%

X5R-CERM

0201

16V

0.1UF

BYPASS=U2650.5::2mm

201

10K

5% 1/20W MF

201

MF

1/20W

1%

12K

CRITICAL

69 18

0201

16V

X5R-CERM

10%

0.1UF

BYPASS=U2650.34::2mm

BYPASS=U2650.5::5mm

20%

6.3V

4.7UF

402

X5R-CERM1

0201

0.1UF

10% 16V

X5R-CERM

BYPASS=U2650.29::2mm

0.1UF

10%

0201

X5R-CERM

BYPASS=U2650.10::2mm

16V

20%

6.3V

BYPASS=U2650.23::5mm

X5R-CERM1

4.7UF

402

201

MF

5%

100

1/20W

1/20W MF 201

10K

5%

1/20W

201

5%

10K

MF

HUB2_NONREM0_1

10K

5%

MF

1/20W

201

10K

5%

HUB2_NONREM1_1

MF

1/20W

201

5%

10K

HUB2_NONREM0_0

1/20W MF 201

10K

5%

HUB2_NONREM1_0

1/20W

MF

201

49

69 37 6

69 39

8

39

QFN

USB2513B

OMIT_TABLE

USB2513B

QFN

OMIT_TABLE

0201

0.1UF

16V

10%

BYPASS=U2600.23::2mm

X5R-CERM

16V

10%

0.1UF

BYPASS=U2600.15::2mm

0201

X5R-CERM

0201

0.1UF

10% 16V

X5R-CERM

BYPASS=U2650.15::2mm

X5R-CERM

0201

0.1UF

10% 16V

BYPASS=U2650.23::2mm

69 8

24.000M-150PPM-6PF

2X1.6X0.65-SM

CRITICAL

24.000M-150PPM-6PF

2X1.6X0.65-SM

CRITICAL

201

NP0-C0G

25V

5%

18PF

CRITICAL

201

MF

1/20W

5%

1M

CRITICAL

18PF

201

25V

NP0-C0G

5%

CRITICAL

201

5%

1/20W

MF

0

HUB2_NONREM1_1,HUB2_NONREM0_1

HUB2_3NONREM

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB1_ALLREM

HUB1_NONREM1_1,HUB1_NONREM0_0

HUB1_2NONREM

HUB1_NONREM1_1,HUB1_NONREM0_1

HUB1_3NONREM

U2600,U2650

USBHUB_2514

CRITICAL

SMSC USB2514

2

338S0720

HUB1_NONREM1_0,HUB1_NONREM0_1

HUB1_1NONREM

SMSC USX2513B

USBHUB_2513B

338S0923

2

CRITICAL

U2600,U2650

338S0824

2

U2600,U2650

USBHUB_2514B

CRITICAL

SMSC USB2514B

HUB2_2NONREM

HUB2_NONREM1_1,HUB2_NONREM0_0

HUB2_NONREM1_0,HUB2_NONREM0_1

HUB2_1NONREM

HUB2_NONREM1_0,HUB2_NONREM0_0

HUB2_ALLREM

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

USB HUBS

USB_HUB_SOFT_RESET_L_R

PPUSB_HUB2_CRFILT

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM

USB_HUB2_XTAL2

USB_HUB2_XTAL1

USB_TPAD_HUB_P

PPUSB_HUB2_PLLFILT

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM

USB_HUB2_NONREM0

USB_HUB2_NONREM1

USB_HUB2_CFG_SEL0

USB_HUB2_CFG_SEL1

USB_HUB2_TEST

USB_HUB_RESET_L

USB_HUB2_UP_P

NC_USB_HUB2_PRTPWR4

USB_EXTA_OC_L

TP_USB_HUB2_OCS1 NC_USB_HUB2_OCS2

USB_HUB2_UP_N

USB_HUB2_RBIAS

USB_HUB2_VBUS_DET

=USB_HUB2_OCS4

USB_EXTA_P

USB_EXTA_N

USB_TPAD_HUB_N

USB_BT_P

USB_BT_N

NC_USB_HUB2_PRTPWR3

TP_USB_HUB2_PRTPWR1 NC_USB_HUB2_PRTPWR2

P3V3S3_EN_RC

=PP3V3_S3_USB_HUB

USB_HUB_RESET_L

=PP3V3_S5_USB_RESET

USB_HUB_RESET

=PP3V3_S3_USB_RESET

=PP3V3_S3_USB_HUB

NC_USB_HUB1_PRTPWR2

TP_USB_HUB1_PRTPWR1

NC_USB_HUB1_PRTPWR3

USB_T29A_N USB_T29A_P

USB_SDCARD_N USB_SDCARD_P

USB_EXTD_N USB_EXTD_P

=USB_HUB1_OCS4

USB_HUB1_VBUS_DET

USB_HUB1_RBIAS

USB_HUB1_UP_N

NC_USB_HUB1_OCS2

TP_USB_HUB1_OCS1

USB_EXTD_OC_L

NC_USB_HUB1_PRTPWR4

USB_HUB1_UP_P

USB_HUB_RESET_L

USB_HUB1_TEST

USB_HUB1_CFG_SEL1

USB_HUB1_CFG_SEL0

USB_HUB1_NONREM1

USB_HUB1_NONREM0

MIN_LINE_WIDTH=0.4MM

PPUSB_HUB1_CRFILT

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

PPUSB_HUB1_PLLFILT

USB_HUB1_XTAL2

USB_HUB1_XTAL1

=PP3V3_S3_USB_HUB

USB_HUB_SOFT_RESET_L

R2641

1

2

Q2640

3

5

4

R2640

12

Q2640

6

2

1

C2641

1

2

C2640

1

2

C2619

1

2

R2630

12

C2620

1

2

C2607

1

2

R2600

1

2

C2615

1

2

C2616

1

2

R2620

1

2

C2617

1

2

C2618

1

2

C2608

1

2

C2602

1

2

C2609

1

2

C2610

1

2

C2603

1

2

R2642

1

2

R2605

12

D2600

12

R2606

1

2

R2607

1

2

R2604

1

2

R2603

1

2

R2601

1

2

R2602

1

2

C2668

1

2

C2667

1

2

C2666

1

2

C2665

1

2

C2660

1

2

R2670

1

2

R2650

1

2

C2661

1

2

C2652

1

2

C2659

1

2

C2658

1

2

C2657

1

2

R2655

12

R2657

1

2

R2656

1

2

R2653

1

2

R2651

1

2

R2654

1

2

R2652

1

2

U2600

14

25

8 9

20

21

13 17 19

34

12 16 18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

510152329

36

33 32

U2650

14

25

8 9

20

21

13 17 19

34

12 16 18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

510152329

36

33 32

C2611

1

2

C2612

1

2

C2662

1

2

C2653

1

2

Y2600

12

Y2650

12

C2670

1

2

R2680

12

C2669

1

2

R2690

12

26 OF 109

3.13.0

051-8870

24 OF 75

24

24 8 7

7

24 8 7

24

24 8 7

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

NC NC

OUT

IN

NC

OUT

IN

OUT

IN

BIIN

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Powered in S0

SB XTAL Power

T29 XTAL Power

NOTE: 30 PPM crystal required

Buffered

PCH S0 PWRGD

VTT voltage divider on CPU page

System RTC Power Source & 32kHz / 25MHz Clock Generator

GreenClk 25MHz Power

For SB RTC Power

create VDD_RTC_OUT.

available ~3.3V power

Platform Reset Connections

Series R is R3803

VBAT and +V3.3A are

internally ORed to

+V3.3A should be first

to reduce VBAT draw.

outputs for power savings

Unbuffered

No Coin-Cell: 3.3V S5

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Coin-Cell: VBAT (300-ohm & 10uF RC)

Ground VDDIO of unused CLK

UNUSED clock terminations for FCIM MODE

PCH Reset Button

CLOCK (CK505)

No bypass necessary

Coin-Cell & No G3Hot: 3.3V S5

201

MF

1/20W

5%

10K

70 16

70 34

1UF

10%

10V

X5R

402-1

10V

X5R

10%

1UF

SLG3NB148V

CRITICAL

TQFN

CRITICAL

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

5%

12PF

25V

NP0-C0G

201

12PF

5%

25V

NP0-C0G

201

70

43

6

41

33

37

31

23

36

66

23 10

201

5%

33

1/20W

MF

5%

0

1/20W

MF

201

MF

1/20W

33

5%

0

1/20W

MF

201

26 18

5%

1K

XDP

1/20W

MF

201

1/20W

0

5%

MF

201

100K

5% 1/20W

201

MF

SC70

74LVC1G07

0.1UF

16V

X5R-CERM

0201

10%

70 41

70 43

6

69 16

201

MF

1/20W

PLACE_NEAR=U1800.G51:5.1mm

5%

22

201

MF

1/20W

22

5%

PLACE_NEAR=U1800.E49:5.1mm

201

MF

1/20W

5%

22

PLACE_NEAR=U1800.G45:2.54MM:5.1mm

70 18

18

23 17

19 17

17

NO STUFF

5%

201

1/20W

MF

0

PLACE_NEAR=U1800.M10:5.54mm

201

5%

1/20W

MF

0

NO STUFF

201

5%

1/20W

MF

3.0K

201

5%

1/20W

MF

0

0201

16V X5R-CERM

10%

0.1UF

MC74VHC1G08

SC70-HF

0201

0.1UF

10%

X5R-CERM

16V

MC74VHC1G08

SC70-HF

201

MF

1/20W

1K

5%

62 52 41 23

57

41 17 67 23 10

0201

X5R-CERM

0.1UF

10%

16V16V

10%

0.1UF

X5R-CERM

0201

201

0

5%

MF

1/20W

201

1/20W

MF

5%

NO STUFF

1M

0

5%

1/20W

MF 201

10K

5%

1/20W

MF

201

10K

5%

1/20W

MF

201

5%

1/20W

MF

201

10K5%10K

1/20W

MF

201

10K

5%

1/20W

MF

201 201

MF

1/20W

5%

10K

402

0

1/16W

MF-LF

5%

XDP

NO STUFF

0

402

SILK_PART=SYS RESET

5% 1/16W MF-LF

5% 1/16W

402

10K

MF-LF

SYNC_MASTER=K78_MLB

SYNC_DATE=11/29/2010

Clock (CK505) and Chipset Support

=PP3V3_S0_SB_PM

=PP3V3_S5_SYSCLK

=PP3V3_S0_SYSCLKGEN

=PPVBAT_G3_SYSCLK

=PPVDDIO_T29_CLK

=PPVDDIO_S0_SBCLK

SYSCLK_CLK25M_T29

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_X1

SYSCLK_CLK25M_X2_R

=PPVRTC_G3_OUT

SYSCLK_CLK32K_RTC

PCH_CLK14P3M_REFCLK

PCIE_CLK100M_PCH_N

PCH_CLK100M_SATA_N

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

PM_PCH_PWROK

MAKE_BASE=TRUE

SMC_DELAYED_PWRGD

PM_S0_PGOOD

=PP3V3_S5_PCHPWRGD

MAKE_BASE=TRUE

PLT_RST_BUF_L

LPCPLUS_RESET_L

MAKE_BASE=TRUE

SDCARD_PLT_RST_L

AP_RESET_L

PCA9557D_RESET_L

=PP3V3_S0_RSTBUF

PCH_CLK96M_DOT_P

PM_PCH_APWROK

PM_PCH_SYS_PWROK

=PP3V3_S5_PCHPWRGD

SYS_PWROK_R

PCH_CLK33M_PCIOUT

PCH_CLK33M_PCIIN

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

LPC_RESET_L

SMC_LRESET_L

XDPPCH_PLTRST_L

CPUIMVP_PGOOD

ALL_SYS_PWRGD

CPU_RESET_L

=T29_RESET_L

BKLT_PLT_RST_L

PCIE_CLK100M_PCH_P

PLT_RESET_L

MAKE_BASE=TRUE

XDP_DBRESET_L

PM_SYSRST_L

=PP3V3_S0_SB_PM

SYSCLK_CLK25M_X2

R2757

1

2

C2702

1

2

C2710

1

2

U2700

9

8

15

12

71016

13

2

17

5

1

11

6

14

4

3

Y2705

24

13

C2705

12

C2706

12

R2783

12

R2788

12

R2781

12

R2771

12

R2789

12

R2793

12

R2780

1

2

U2780

2

3

5

4

C2780

1

2

R2727

12

R2726

12

R2729

12

R2761

1

2

R2763

12

R2762

12

R2760

12

C2760

1

2

U2760

3

2

1

4

5

C2750

1

2

U2750

3

2

1

4

5

R2750

1

2

C2722

1

2

C2724

1

2

R2705

12

R2706

1

2

R2782

12

R2751

1

2

R2752

1

2

R2753

1

2

R2754

1

2

R2755

1

2

R2756

1

2

R2796

12

R2797

1

2

R2795

1

2

27 OF 109

3.13.0

051-8870

25 OF 75

1

25

7

69 16

41 36

25

7

69 16

25

7

69 16

25

7

IN

D

SG

D

SG

D

SG

D

SG

OUT

D

SG

D

SG

IN

OUT

G

D

S

D

SG

IN

D

SG

IN

D

SG

D

SG

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

MEMVTT Clamp

Ensures CKE signals are held low in S3

60mW max power

75mA max load @ 0.75V

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

1V5 S0 "PGOOD" for CPU

S0

to

S3

to

S0

3 0 0 0 1 X 1 0 0

4 0 0 1 1 X 1 0 1

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

5 0 1 1 1 0 (*) 1 1 1

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

6 0 1 1 1 1 1 1 1

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

2 0 0 1 1 1 1 0 1

1 0 1 1 1 1 1 1 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

0.047UF

402

CPUMEM_S0

SSM6N37FEAPE

MEMRESET_ISOL_LS5V_L

MEM_RESET_L

MAKE_BASE=TRUE

CPU_MEM_RESET_L

PLT_RESET_L

PM_SLP_S4_L

P1V5CPU_EN

PM_SLP_S3_L

MEMVTT_EN_L

=MEM_RESET_L

PM_MEM_PWRGD

=PP3V3_S5_CPU_VCCDDR

=PP1V5_S3_CPU_VCCDDR

VTTCLAMP_L

PM_MEM_PWRGD_L

=PP5V_S3_MEMRESET

VTTCLAMP_EN

=DDRVTT_EN

P1V5_S0_DIV

=PPVTT_S0_VTTCLAMP

=PP3V3_S3_MEMRESET

=PP1V5_S3_MEMRESET

=PP5V_S3_MEMRESET

MEMVTT_EN

P1V5CPU_EN_L

ISOLATE_CPU_MEM_L

ISOLATE_CPU_MEM_L_R

CPU Memory S3 Support

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

8

SOT563

SSM6N37FEAPE

CPUMEM_S0

SOT563

SSM6N37FEAPE

CPUMEM_S0

1/20W

MF

5%

201

0

X7R

10% 16V

X5R-CERM

16V

10%

NOSTUFF

0201

0.1UF

8

56

201

MF

1/20W

1%

33.2K

201

MF

1/20W

1%

27.4K

SOT563

SSM6N37FEAPE

CPUMEM_S0

17 41 62

201

MF

1/20W

5%

100K

CPUMEM_S0

NO STUFF

16V X7R 201

1000PF

10%

SOT563

SSM6N37FEAPE

CPUMEM_S0

NO STUFF

16V X7R 201

1000PF

10%

SOT-563

DMB53D0UV

CRITICAL

201

MF

1/20W

5%

10K

SOT-563

DMB53D0UV

CRITICAL

1/10W

5%

603

MF-LF

10

CPUMEM_S0

201

MF

1/20W

5%

10K

CPUMEM_S0

10 17 67

10

1/20W

CPUMEM_S0

201

MF

5%

100K

19 23

SOT563

SSM6N37FEAPE

CPUMEM_S3

201

1/20W

5% MF

0

CPUMEM_S0

SSM6N37FEAPE

SOT563

27 28 29 30

201

1/20W

5%

20K

CPUMEM_S0

MF

61

SOT563

SSM6N37FEAPE

CPUMEM_S0

201

MF

1/20W

5%

100K

CPUMEM_S0

SOT563

SSM6N37FEAPE

CPUMEM_S0

1/20W

CPUMEM_S0

100K

5% MF

201

CPUMEM_S0

SSM6N37FEAPE

SOT563

CPUMEM_S0

18 25

201

MF

1/20W

5%

10K

CPUMEM_S0

17 41 49 62

R2805

1

2

Q2805

6

2

1

Q2805

3

5

4

R2810

1

2

Q2810

6

2

1

Q2810

3

5

4

R2801

1

2

Q2800

3

5

4

R2802

1

2

Q2800

6

2

1

R2816

1

2

Q2815

3

5

4

R2817

12

Q2815

6

2

1

R2815

1

2

R2850

1

2

Q2820

6

2

1

R2822

1

2

Q2820

5

3

4

C2820

1

2

Q2850

6

2

1

C2851

1

2

R2851

1

2

Q2850

3

5

4

R2820

1

2

R2821

1

2

C2816

1

2

C2817

1

2

R2890

12

28 OF 109

3.13.0

051-8870

26 OF 75

7

10 12 15

7

26

7

26

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

NC NC

NC

NCNC

NC

NC NC NC

NC

NC NC

NC

NC NC NC

NC NC

NC

A14/A15 FOR 2G/4G MONO ONLY

NCNC

NC

CS1 IS FOR 2G DDP RANK CONTROL

MEM_A_DQ<5>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_A<9>

DDR3-1333

MEM_A_A<8>

201

MEM_A_ODT<0>

MEM_A_DQ<8>

201

MEM_A_DQ<14>

MEM_RESET_L

MEM_A_ZQ0

MEM_A_ZQ1

0.47UF

20%

MEM_RESET_L

OMIT_TABLE

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_DQ<7>

MF

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_ZQ2

MEM_A_ODT<0>

201

1/20W

1%

MF

240

MEM_A_ZQ3

MEM_A_ODT<0>

MEM_RESET_L

240

MF

1%

1/20W

201

MEM_A_A<14>MEM_A_A<14>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_BA<2>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_A<5>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_A<14>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

240

201

1/20W

1%

201

1/20W

1%

MF

240

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

MEM_A_CS_L<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_DQ<30>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<29>

MEM_A_DQ<31>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<28>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<5>

DDR3-1333

FBGA

OMIT_TABLEOMIT_TABLE

FBGA

DDR3-1333

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_DQ<20>

MEM_A_DQ<22>

MEM_A_DQ<16>

MEM_A_DQ<18>

MEM_A_DQ<21>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<23>

MEM_A_DQ<17>

MEM_A_DQ<19>

MEM_A_A<0>

MEM_A_A<1>

OMIT_TABLE

FBGA

DDR3-1333

=PP1V5_S3_MEM_A

MEM_A_A<13>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_DQ<12>

MEM_A_DQ<10>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<9>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQ<15>

MEM_A_A<5>

FBGA

MEM_A_A<11>

MEM_A_CAS_L

MEM_A_A<13>

MEM_A_A<10>

MEM_A_A<7>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_DQ<3>

MEM_A_DQ<6>

MEM_A_A<12>

MEM_A_A<6>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<5>

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

DDR3 DRAM CHANNEL A (0-31)

SYNC_DATE=12/07/2010

SYNC_MASTER=K78_MLB

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

20%

0.47UF

4V CERM-X5R-1 201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

20%

0.47UF

20%

CERM-X5R-1

4V

201

4V CERM-X5R-1

0.47UF

4V

CERM-X5R-1

201

20%

CERM-X5R-1

201

0.47UF

20%

4V

4V CERM-X5R-1

0.47UF

20% 0.47UF

4V CERM-X5R-1 201

20%

C2932

1

2

C2931

1

2

C2930

1

2

C2922

1

2

C2921

1

2

C2920

1

2

R2930

12

R2920

12

C2912

1

2

C2911

1

2

C2910

1

2

C2902

1

2

C2901

1

2

C2900

1

2

R2910

12

R2900

12

U2900

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U2910

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U2920

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U2930

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

27 OF 75

051-8870

3.13.0

29 OF 109

32

11

68

11

68

26

11

27

30 29 28

68 32 28

26

11

27

28 27

28 29

32

30

68

68 32

28

11

68 32 28 27

11 68 32 28 27

28 32 68 27 11

11

68 32 27

68 32 28 27

11 27 68 32 28

27 11 68 32 28

27 11 28

11 27 28 68 32

11 68 32 28 27

11 27 28 32 68

11 27 68 32 28

11

27 28 32 68

11 27

11 27 68 32 28

68 32 28

11 68 32 28 27

11 27 68 32 28

11 68 32 28 27

27

26 27 28

28

29 30

32 68

11 27

26 27 30 29 28

68 32 28

11

11 68 32 28 27

68 32 28 27

11 68 32 28 27

11 27 68 32 28

11 68 32 28 27

11 27 28 32 68

11

11 27 28 32 68

11 68

11 27 28 32 68

11 68

11 27 28 32 68

11 68

11 68 11 27 28 32 68

11 27 28 32 68

27 28 32 68

11 68

11 27 28 32 68

11 68

11 27 28 32 68

11 68

11 68 11 27 28 32 68

11 27 28 32 68

7

27 28 32

11 27 28 32 68

27 28 32 68

11 27 28 32 68

11 68

11 27 28 32 68

11 68

11 27 28 68

11 27 28 32 68

11 68

11 68 11 27 28 32 68

11 27 28 32 68

11 27 28 32

11 27 28 32 68

11 68

11 27 28 32 68

11 68

11 27 28 32 68

68

11 68

11 11 27 28 32 68

11 27 28 32 68

7

27 28 32

9

27 28 29 30 31 68

9

27 28 29 30 31 68

7

27 28 32

27 28 29 30 31 68

9

27 28 29

30 31 68

9

27 28 29 30 31 68

7

27 28 32

27 28 29 30 31 68

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

NC

NC NC

NC

NC NC NC

NC

NCNC

NC

NC NC

NC

NC NC

NC

NC NC NC

NC NC

NC

NC NC

NC

CS1 IS FOR 2G DDP RANK CONTROL

A14/A15 FOR 2G/4G MONO ONLY

NC

NC NC

MEM_A_A<5>

MEM_A_DQ<53>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<3>

FBGA

FBGAFBGA

0.47UF

20%

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

201

CERM-X5R-1

4V

0.47UF

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

201

CERM-X5R-1

4V

0.47UF

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

DDR3 DRAM CHANNEL A (32-63)

SYNC_MASTER=K78_MLB

SYNC_DATE=12/07/2010

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

=PP1V5_S3_MEM_A

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQ<39>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_A<6>

MEM_A_A<12>

MEM_A_DQ<32>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<35>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_A<11>

PP0V75_S3_MEM_VREFDQ_A

OMIT_TABLE

DDR3-1333

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQ<46>

MEM_A_DQ<41>

MEM_A_DQ<43>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_A<6>

MEM_A_A<12>

MEM_A_DQ<42>

MEM_A_DQ<47>

MEM_A_DQ<40>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_A<11>

OMIT_TABLE

DDR3-1333

MEM_A_A<5>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<55>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_A<6>

MEM_A_A<12>

MEM_A_DQ<49>

MEM_A_DQ<54>

MEM_A_DQ<52>

MEM_A_DQ<48>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_CAS_L

=PP1V5_S3_MEM_A

MEM_A_A<11>

DDR3-1333

OMIT_TABLE

MEM_A_DQ<59>

MEM_A_DQ<57>

MEM_A_DQ<63>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_A<6>

MEM_A_A<12>

MEM_A_DQ<60>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<58>

MEM_A_DQ<56>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<7>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_A<11>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<14>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_A<14>

201

1/20W

1%

MF

240

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_ZQ8

201

1/20W

1%

MF

240

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_ZQ9

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

DDR3-1333

OMIT_TABLE

MEM_A_CLK_N<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<14>

201

1/20W

1%

MF

240

MEM_RESET_L

MEM_A_ODT<0>

MEM_A_ZQ10

201

1/20W

1%

MF

240

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_ZQ11

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CS_L<0>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<14>

C3032

1

2

C3031

1

2

C3030

1

2

R3030

12

C3022

1

2

C3021

1

2

C3020

1

2

R3020

12

C3012

1

2

C3011

1

2

C3010

1

2

R3010

12

C3002

1

2

C3001

1

2

C3000

1

2

R3000

12

U3000

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3010

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3020

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3030

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

30 OF 109

3.13.0

051-8870

28 OF 75

68

11

28 32 27

7

32 28 27

7

68 31 30 29 28 27

9

68 31 30 29 28 27

9

68 31 30 29 28 27

9

68 31 30 29 28 27

32 28 27

7

9

27 28 29 30

31 68

11 27 28 32 68

27 28 29 30 31 68

11 68

11 27 28 32 68

11 68

11 27 28 32 68

11 68

11 68 11 27 28 32 68

11 27 28 32 68

68 32 28 27 11

68 32 28 27 11 68 11

68 11

68 32 28 27 11

68 11

68 32 28 27 11

68 11

68 32 28 27 11

68 32 28 27 11 68 11

68 11

11

68 32 28 27 11

68 11

68 32 28 27 11

68 11

68 32 28 27 11

32 28 27

7

68 32 28 27 11

32 28 27 11

68 32 28 27 11 68 11

68 11

68 32 28 27 11

68 11

68 32 28 27

68 32 28 27 11

68 11

68 32 28 27 11

27 28 32 68 11

28 32 68 27 11

27 28 32 68 11

11 27 28 32 68

27 28 32 68 11

28 32 68

11 27

27 11

30

68

26 27 28 29

32 28 27 11

30 29 27 28 26

68 32 27 28 11

32 68 11 27 28

28 32 68 11 27

27 28 32 68 11

11 68 32 28 27

27 28 32 68

11

68

30 29 28 27 26

32 28 27 11

30 28 29 27 26

68 11 27 28 32

28 32 68 11 27

28 32 68 27 11

27 28 32 68 11

68

32 28 27 11

32 28

27

11

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

NC

NC NC

NC

NC NC

NC

A14/A15 FOR 2G/4G MONO ONLY CS1 IS FOR 2G DDP RANK CONTROL

NC

NC NC

NC

MEM_B_A<14>

FBGAFBGA

MEM_B_BA<0>

DDR3-1333

OMIT_TABLE

MEM_B_ZQ3

MEM_RESET_L

MEM_B_ODT<0>

201

240

1/20W

1%

MF

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

PP0V75_S3_MEM_VREFDQ_A

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CS_L<0>

PP0V75_S3_MEM_VREFCA_A

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<25>

MEM_B_DQ<31>

MEM_B_DQ<24>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<26>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<5>

MEM_B_ZQ2

MEM_RESET_L

MEM_B_ODT<0>

240

MF

1%

1/20W

201

MEM_B_A<14>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_RAS_L

MEM_B_WE_L

PP0V75_S3_MEM_VREFDQ_A

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<2>

PP0V75_S3_MEM_VREFCA_A

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_DQ<20>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<23>

MEM_B_DQ<17>

MEM_B_DQ<19>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<5>

DDR3-1333

OMIT_TABLE

FBGA

DDR3-1333

MEM_B_ODT<0>

MEM_RESET_L

1%

201

1/20W

240

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CS_L<0>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<8>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<15>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_A<0>

MEM_B_A<1>

OMIT_TABLE

FBGA

DDR3-1333

MEM_B_A<14>

240

MF

1%

1/20W

201

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_BA<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<0>

MEM_B_DQ<7>

MEM_B_DQ<1>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<3>

MEM_B_DQ<5>

MEM_B_DQ<2>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<5>

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_B=PP1V5_S3_MEM_B

SYNC_MASTER=K78_MLB

SYNC_DATE=12/07/2010

DDR3 DRAM CHANNEL B (0-31)

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V CERM-X5R-1 201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

20%

CERM-X5R-1

4V

201

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

20%

4V CERM-X5R-1 201

0.47UF

20%

MEM_B_A<5>

MF

0.47UF

MEM_B_A<3>

0.47UF

MEM_B_ZQ1

MEM_B_ZQ0

MEM_RESET_L

MEM_B_ODT<0>

C3132

1

2

C3131

1

2

C3130

1

2

C3122

1

2

C3121

1

2

C3120

1

2

R3130

12

R3120

12

C3112

1

2

C3111

1

2

C3110

1

2

C3102

1

2

C3101

1

2

C3100

1

2

R3110

12

R3100

12

U3100

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3110

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3120

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3130

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

31 OF 109

3.13.0

051-8870

29 OF 75

11 29

26 27

68 32 30

30 29 28

11

68 32 30 29

11 30 32 68 29

68 32 30 29 11

68 32 30 29 11 68 11

68 11

68 32 30 29 11

68 11

68 32 30 29 11

68 11

68 31 30 29 28 27

29 30 32 68 11

32 68 30 29 11

29 30 32 68 11

68 32 30 29 11

68 31 30 29 28 27

9

11

26

68 32 30 29

30 29 28 27

30 29 11

30 11 29

30 29 11

68 32

29 11 30 32 68

11

68 32 30 29

11 68 32 30 29

30 32 68 29 11

30 29 11 68 32

68 32 30 29 11

68 32 30 29 11 68 11

68 11

68 32 30 29 11

68 11

68 32 30 29 11

68 11

68 31 30 29 28 27

68 32 30 29 11

68 31 30 29 28 27

9

29 11

27 26

32 30

30 29 28

11

11 68 32 30 29

68 32 30 29

29 11 30 32 68

11 29

11 29 68 32 30

68 32 30

11 68 32 30 29

11 29 68 32 30

29 11 68 32 30

11 29 30 32 68

11 68

11 29 30 32 68

11 68

11 29 30 32 68

11 68

11 68 11 29 30 32 68

11 29 30 32 68

11

26 30 29 28 27

68 32 30 29

11

11 68 32 30 29

68 32 30 29

11

11 68 32 30 29

68 32 30 29

11 68 32 30 29

68 32 30 29 11

11 68 32 30 29

11 29 30 32 68

11 68

11 29 30 32 68

11 68

11 29 30 32 68

11 68

11 68 11 29 30 32 68

11 29 30 32 68

7

29 30 32

27 28 29 30 31 68

9

27 28 29 30

31 68

7

29 30 32

27 28 29 30 31 68

9

27 28 29 30 31 68

7

29 30 32

7

29 30 32

68

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

VSS

A5

A1

A0

VSSQ

DQ0 DQ1 DQ2

A9

A8

A14

ZQ

RESET*

ODT

DQS*

DQS

DM/TDQS

A6

A12/BC*

NF/DQ7

NF/DQ6

NF/DQ5

NF/DQ4

DQ3

NF/TDQS*

NC

VREFCA

BA1

CK

CKE

CK*

CS*

WE*

RAS*

A2 A3 A4

A7

A10/AP

A13

BA0

BA2

CAS*

VDD

VDDQ

A11

VREFDQ

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

NC NC

NC

A14/A15 FOR 2G/4G MONO ONLY

NC

NC NC

NC

NC NC

NC

NC NC NC NC NC

NC NC

NC NC NC

NC

NC NC

NC

CS1 IS FOR 2G DDP RANK CONTROL

NC

NC NC

OMIT_TABLE

FBGA

DDR3-1333

0.47UF

=PP1V5_S3_MEM_B

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_DQ<43>

MEM_B_DQ<40>

MEM_B_A<13>

MEM_B_A<12>

FBGA

MEM_B_ZQ8

MEM_B_ODT<0>

MEM_RESET_L

201

1/20W

1%

MF

240

MEM_B_A<14>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_BA<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_A<11>

MEM_B_CAS_L

MEM_B_A<13>

MEM_B_A<10>

MEM_B_A<7>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_DQ<33>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<34>

MEM_B_DQ<32>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_DQ<39>

MEM_B_DQ<36>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<5>

DDR3-1333

OMIT_TABLE

MEM_B_A<5>

MEM_B_ZQ9

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

201

4V CERM-X5R-1

0.47UF

20%

4V CERM-X5R-1 201

0.47UF

20%

4V

CERM-X5R-1

201

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V CERM-X5R-1 201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V

CERM-X5R-1

201

20%

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_A

240

201

1/20W

1%

MF

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQ<63>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<14>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_A<6>

MEM_B_A<12>

MEM_B_DQ<56>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_BA<1>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_CAS_L

=PP1V5_S3_MEM_B

MEM_B_ZQ11

201

4V

20%

0.47UF

CERM-X5R-1

4V

201

CERM-X5R-1

0.47UF

20%

MEM_B_ODT<0>

MEM_RESET_L

0.47UF

PP0V75_S3_MEM_VREFDQ_A

=PP1V5_S3_MEM_B

PP0V75_S3_MEM_VREFCA_A

MEM_B_A<11>

MEM_B_A<5>

SYNC_MASTER=K78_MLB

SYNC_DATE=12/07/2010

DDR3 DRAM CHANNEL B (32-63)

PP0V75_S3_MEM_VREFCA_A

MF

1%

1/20W

201

240

OMIT_TABLE

FBGA

DDR3-1333

MEM_B_A<5>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQ<55>

MEM_B_DQ<53>

MEM_B_DQ<51>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_ZQ10

MEM_RESET_L

MEM_B_ODT<0>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_A<6>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<48>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<11>

OMIT_TABLE

DDR3-1333

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<46>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_A<6>

MEM_B_A<12>

MEM_B_DQ<45>

MEM_B_DQ<47>

MEM_B_DQ<44>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<13>

MEM_B_CAS_L

MEM_B_A<11>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CS_L<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_A<14>

240

201

1/20W

1%

MF

MEM_RESET_L

MEM_B_ODT<0>

MEM_B_DQ<35>

C3232

1

2

C3231

1

2

C3230

1

2

R3230

12

C3222

1

2

C3221

1

2

C3220

1

2

R3220

12

C3212

1

2

C3211

1

2

C3210

1

2

R3210

12

C3202

1

2

C3201

1

2

C3200

1

2

R3200

12

U3230

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3220

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3210

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

U3200

K4 L8

H8 M8 K8 N4 N8

L4 K3 L9 L3 M9 M3 N9 M4

J3 K9 J4

G4

F8 G8

G10

H3

B8

B4 C8 C3 C9

C4

D4

A1 A4 A11 F2 F10 H2 H10 J8 N1 N11

E4 E9 D3 E8

A8

G2

F4

N3

A3

A10D8G9G3K2

K10M2M10

B10C2E3

E10

J9

E2

A2

B2

L10

N10

J2L2N2F3A9D9F9

J10

B3D2B9

C10

D10

H4

H9

32 OF 109

3.13.0

051-8870

30 OF 75

11

68 32

26

29

29 28 27

9

68

32

29

30

32

68

30

11

26

11

30 29 28 27

68 32 30 29

11

68 32 30 29

11 68 32 30 29

68 32 30 29

68 32 30 29 11

11 29 68 32 30

11 68 32 30 29

11 29 30 32 68

11 68

11 29 30 32 68

11 68

11 29 30 32 68

11 68

11 68 11 29 30

11 29 30 32 68

30 11

68

29

32 30 29

7

68 31

30 29 28 27

9

68 31 30 29 28 27

68 31 30

68 31 30 29 28 27

9

32 30 29

7

32 30 29

7

68 31 30 29 28 27

68 32 30 29 11

11 68 32 30 29

68 32 30 29 11

11 29 30 68 32

11 68 32 30 29

68 11

68 32 30 29 11

68 11

68 32 30 29 11

68 11

68 11 68 32 30 29 11

68 32 30 29 11

32 30 29

7

30 31 68

68

30 29

32

29

28 27

30 11

9

27 28

68 31 30 29 27 28 27 28 29 30 31 68

68 32 30 29 11

68 32 30 29 11 68 11

68 11

68 30 29 11

32 30 29 11

30 29 28 27 26

68 32 29 30 11

68 11

68 32 30 29 11

68 32 30 11

68 11

29 32 68

29 68 11

68 32 30 29 11

29 30 32 68 11

30 32 29 11

68 32 30 29 11

68 32 30 11

68 32 30 29 11

29 30 32 68 11

68 32 29 11 30

68 32 30 29 11

32 30 29 11

68 32 30 29 11

68 32 30 29 11 68 11

68 11

68 32 30 29 11

68 11

68 32 30 11

68 32 30 29 11

11

68 11

68 32 30 29 11

32 30 29 11

68 32 30 29 11

30 32 68 29 11

32 68

30 32 68

29

29 11

11 29 68 32 30

29 30 32 68

11

29 30 32 68

27 28 29 30

11

26

68

OUT

V-

V+

V-

V+

V-

V+

V-

V+

IN

NC

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

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PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

NOTE: Margining will be disabled across all

watchdog will disable margining.

RST* on ’platform reset’ so that system

NOTE: MEMVREG and FRAMEBUF share

a DAC output, cannot enable

both at the same time!

buffers at once or VRef source may be overloaded.

NOTE: Must not enable more than two SO-DIMM margining

unused buffer

GPU Frame Buffer (1.8V, 70% VRef)

- =I2C_PCA9557D_SCL

Addr=0x30(WR)/0x31(RD)

10mA max load

1.51mV / step @ output

+6.0mA - -5.0mA (- = sourced)

0.000V - 3.300V (0x00 - 0xFF)

D

1.267V (DAC: 0x8B)

1.056V - 1.442V (+/- 180mV)

8.59mV / step @ output

+33uA - -33uA (- = sourced)

0.000V - 1.501V (0x00 - 0x74)

1.998V - 1.002V (+/- 498mV)

1.5V (DAC: 0x3A)

5

BOM options provided by this page:

Required zero ohm resistors when no VREF margining circuit stuffed

Addr=0x98(WR)/0x99(RD)

MEM B VREF CA

C

0.000V - 1.501V (0x00 - 0x74)

+3.4mA - -3.4mA (- = sourced)

(OD)

Signal aliases required by this page:

VREFMRGN_NOT - Bypasses VREF Margining

VREFMRGN - Stuffs VREF Margining

Power aliases required by this page:

Page Notes

- =PPVTT_S3_DDR_BUF

Circuitry.

- =I2C_PCA9557D_SDA

- =I2C_VREFDACS_SDA

- =I2C_VREFDACS_SCL

- =PP3V3_S3_VREFMRGN

4

MEM A VREF CA

3

C

7.69mV / step @ output

0.300V - 1.200V (+/- 450mV)

MEM B VREF DQ

A

1 2

B

Margined target:

VRef current:

DAC step size:

DAC range:

PCA9557D Pin:

DAC Channel:

D

MEM VREG

0.75V (DAC: 0x3A)

6

soft-resets and sleep/wake cycles.

Nominal value

MEM A VREF DQ

56

VREFMRGN

0.1UF

6.3V X5R 201

10%

33.2K

VREFMRGN

1%

PLACE_NEAR=R7315.2:1mm

1/20W

MF

201

VREFMRGN

100K

5%

1/20W

MF

201

100K

5%

VREFMRGN

1/20W

MF

201

UCSP

VREFMRGN

MAX4253

VREFMRGN

UCSP

MAX4253

UCSP

VREFMRGN

MAX4253

VREFMRGN

UCSP

1%

200

VREFMRGN

1/20W

MF

201

PLACE_NEAR=J2900.126:2.54mm

OMIT

NONE

402

NONE

SHORT

NONE

OMIT

SHORT

NONE

402

NONE

25

VREFMRGN

1%

200

MF

201

PLACE_NEAR=U2900.E1:2.54mm

1/20W

PLACE_NEAR=U2900.J8:1mm

VREFMRGN

1%

133

1/20W

MF

201

MF

1/20W

100K

VREFMRGN

5%

201

5%

VREFMRGN

100K

1/20W

MF

201

133

PLACE_NEAR=R3309.2:1mm

VREFMRGN

1%

1/20W

MF

201

CRITICAL

QFN

PCA9557

VREFMRGN

44

MSOP

DAC5574

CRITICAL

VREFMRGN

44

0201

X5R-CERM

16V

10%

VREFMRGN

0.1UF

VREFMRGN

2.2UF

CERM

402-LF

20%

6.3V

10%

0201

X5R-CERM

16V

0.1UF

VREFMRGN

0201

X5R-CERM

16V

10%

0.1UF

VREFMRGN

2

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

VREFMRGN_NOT

R3309

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_DATE=01/10/2011

SYNC_MASTER=K78_MLB

VREFMRGN_NOT

2

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

R3303

VREFMRGN_SODIMMS_CA

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_MEMVREG_BUF

=PP3V3_S3_VREFMRGN

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_MEMVREG_FBVREF

=PPVTT_S3_DDR_BUF

VREFMRGN_MEMVREG_EN

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_DAC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_CTRL

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

VREFMRGN_FRAMEBUF_EN

VREFMRGN_FRAMEBUF_BUF

=I2C_VREFDACS_SCL

PCA9557D_RESET_L

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

DDRREG_FB

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_SODIMMA_DQ

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

VREFMRGN_CA_SODIMMA_BUF

U3301

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

C3303

1

2

C3302

1

2

R3301

12

R3310

12

U3300

9

10

3

6

7

8

1

2

4

5

C3301

1

2

C3300

1

2

C3305

1

2

R3314

12

R3313

1

2

R3315

1

2

U3302

C3

C2

C1

C4

B1

B4

U3302

A3

A2

A1

A4

B1

B4

U3304

A3

A2

A1

A4

B1

B4

U3304

C3

C2

C1

C4

B1

B4

R3309

12

R3318

12

R3319

12

R3303

12

R3304

12

R3307

1

2

33 OF 109

3.13.0

051-8870

31 OF 75

7

68 30 29 28 27

9

56

7

68 30 29 28 27

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

2 CAPS ALONG PACKAGE EDGE

COLUMN OF THREE CAPS BETWEEN PACKAGES

MEM CLOCK TERMINATION

Place RC end termination after last DRAM Place Source Cterm at neckdown at first DRAM

2 CAPS ALONG PACKAGE EDGE

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

5%361/32W

4X0201

1/32W

5%

4X0201

36

CERM 402-LF

20%

2.2UF

6.3V

36

4X0201

5%

1/32W

36

4X0201

1/32W

5%

4X0201

1/32W

5%

36

4X0201

1/32W

5%

36

4X0201

5%

1/32W

36

68 30 29 11

6.3V

2.2UF

CERM

20%

402-LF

68 30 29 11

20%

CERM-X5R-1

0.47UF

201

4V

20%

0.47UF

201

CERM-X5R-1

4V

0.47UF

4V CERM-X5R-1

20%

201

20%

0.47UF

201

CERM-X5R-1

4V

0.47UF

20%

201

CERM-X5R-1

4V

402-LF

2.2UF

6.3V

20%

CERM

402-LF

2.2UF

6.3V

20%

CERM

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

4V

2.2UF

6.3V

20%

402-LF

CERM

20%

0.47UF

201

CERM-X5R-1

4V

68 28 27 11

20%

2.2UF

402-LF

CERM

6.3V

68 28 27 11

2.2UF

20%

CERM

6.3V

402-LF

2.2UF

20%

402-LF

CERM

6.3V

68 28 27 11

0.1UF

MEM_A_CLK_TERM_R

10% X5R

6.3V

201

0.1UF

201

10% X5R

6.3V

30

5%

1/20W

MF

201

CERM

25V

5%

3.3PF

201

1/20W

5%

30

MF

201

30

201

5%

1/20W

MF

201

CERM

25V

5%

3.3PF

30

201

1/20W

MF

5%

6.3V

2.2UF

20%

402-LF

CERM

6.3V

2.2UF

20%

402-LF

CERM

4X0201

5%

1/32W

36

4X0201

5%

1/32W

36

4X0201

36

5%

1/32W

4X0201

1/32W

5%

36 36

4X0201

1/32W

5%

36

4X0201

1/32W

5%

4X0201

1/32W

5%

36

CERM 402-LF

6.3V

20%

2.2UF

4X0201

36

5%

1/32W

4X0201

36

5%

1/32W

4X0201

36

5%

1/32W

36

4X0201

1/32W

5%

4X0201

5%

1/32W

36

4X0201

1/32W

5%

36

4X0201

5%

1/32W

36

4X0201

5%

1/32W

36

4X0201

1/32W

5%

36

4X0201

1/32W

5%

36

20%

2.2UF

6.3V

402-LF

CERM

4X0201

5%

1/32W

36

5%

1/32W

4X0201

36

4X0201

5%

1/32W

36

4X0201

5%

1/32W

36

4X0201

36

1/32W

5%

4X0201

36

5%

1/32W

4X0201

1/32W365%

4X0201

36

1/32W

5%

1/32W

5%

4X0201

36

4X0201

5%

1/32W

36

CERM 402-LF

20%

2.2UF

6.3V

4X0201

1/32W

5%

36

4X0201

1/32W

5%

36

4X0201

1/32W365%

4X0201

36

5%

1/32W

4X0201

5%

1/32W

36

4X0201

36

5%

1/32W

CERM

6.3V

2.2UF

20%

402-LF

4X0201

36

5%

1/32W

2.2UF

6.3V

402-LF

20%

CERM

6.3V

20%

2.2UF

402-LF

6.3V

20%

2.2UF

402-LF

CERM

6.3V

20%

2.2UF

402-LF

2.2UF

20%

6.3V CERM 402-LF

402-LF

20%

6.3V CERM

2.2UF

6.3V

20%

CERM 402-LF

2.2UF

20%

2.2UF

6.3V

402-LF

CERM

68 30 29 11

1/32W

5%

4X0201

36

68 30 29 11

68 28 27 11

4X0201

5%

1/32W

36

6.3V

2.2UF

20%

402-LF

CERM

6.3V

2.2UF

20%

402-LF

CERM

402-LF

CERM

20%

2.2UF

6.3V

CERM

6.3V

2.2UF

20%

402-LF

2.2UF

20%

6.3V CERM

402-LF

CERM

6.3V

2.2UF

20%

6.3V

2.2UF

20%

402-LF

CERM

20%

6.3V

402-LF

CERM

2.2UF

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

402-LF

6.3V

20%

CERM

2.2UF

20%

6.3V CERM 402-LF

20%

2.2UF

6.3V CERM 402-LF

402-LF

CERM

6.3V

20%

2.2UF

20%

CERM 402-LF

6.3V

2.2UF

6.3V

20%

CERM

2.2UF

402-LF

20%

6.3V CERM 402-LF

2.2UF

CERM 402-LF

20%

6.3V

2.2UF

CERM

20%

2.2UF

6.3V

402-LF

2.2UF

6.3V CERM 402-LF

20%

6.3V

2.2UF

20%

402-LF

CERM

2.2UF

20%

CERM 402-LF

6.3V

CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

2.2UF

6.3V

CERM 402-LF

20%

2.2UF

6.3V

CERM

20%

2.2UF

6.3V

402-LF

6.3V

2.2UF

20%

402-LF

CERM

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

CERM 402-LF

20%

6.3V

2.2UF

6.3V

20%

402-LF

CERM

6.3V

20%

402-LF

2.2UF

6.3V

2.2UF

20%

402-LF

CERM

402-LF

6.3V

20%

CERM

2.2UF

CERM

20%

6.3V

2.2UF

402-LF

6.3V

2.2UF

402-LF

20%

CERM

6.3V

2.2UF

20%

402-LF

CERM

CERM 402-LF

20%

2.2UF

6.3V

2.2UF

CERM 402-LF

20%

6.3V

CERM 402-LF

20%

2.2UF

6.3V

CERM

6.3V

2.2UF

20%

402-LF

2.2UF

402-LF

6.3V

20%

CERM

6.3V

20%

402-LF

CERM

2.2UF

20%

201

4V

0.47UF

CERM-X5R-1

20%

0.47UF

201

CERM-X5R-1

4V

5%

1/32W

4X0201

36

5%

1/32W

4X0201

36

6.3V

2.2UF

402-LF

CERM

20%

4X0201

5%

1/32W

36

4X0201

5%

1/32W

36

4X0201

1/32W

5%

36

20%

0.47UF

201

CERM-X5R-1

4V

20%

0.47UF

201

4V CERM-X5R-1

DDR3 DRAM Channel B (32-63)

SYNC_MASTER=K78_MLB

SYNC_DATE=12/16/2010

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B

=PP0V75_S0_MEM_VTT_B

MEM_B_BA<2>

MEM_B_A<11>

MEM_B_A<2>

MEM_B_A<0> MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<10>

MEM_B_CLK_TERM_R

VOLTAGE=0V

MEM_B_BA<1>

MEM_B_A<12>

MEM_B_A<6>

MEM_B_CS_L<0>

MEM_B_WE_L

MEM_B_A<9>

MEM_B_RAS_L

MEM_B_CKE<0>

MEM_A_BA<1>

MEM_A_A<4>

MEM_B_A<7>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_A<8>

=PP1V5_S3_MEM_B

MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_A<13>

MEM_B_A<1>

MEM_A_A<9>

MEM_A_RAS_L

MEM_A_A<10>

MEM_A_CKE<0>

MEM_A_A<7> MEM_A_BA<0>

MEM_A_A<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_A<3> MEM_A_A<6>

MEM_A_WE_L

MEM_A_A<11>

=PP0V75_S0_MEM_VTT_A

=PP1V5_S3_MEM_A

MEM_B_A<4> MEM_B_ODT<0>

MEM_B_A<14>

MEM_A_A<5>

MEM_A_A<8>

MEM_A_A<2> MEM_A_CAS_L

MEM_A_A<12> MEM_A_A<13> MEM_A_BA<2> MEM_A_A<0> MEM_A_A<14>

C3420

1

2

C3421

1

2

C3410

1

2

C3411

1

2

C3412

1

2

C3400

1

2

C3401

1

2

C3424

1

2

C3425

1

2

C3414

1

2

C3415

1

2

C3416

1

2

C3404

1

2

C3405

1

2

C3450

1

2

C3451

1

2

C3440

1

2

C3441

1

2

C3442

1

2

C3430

1

2

C3431

1

2

C3454

1

2

C3455

1

2

C3444

1

2

C3445

1

2

C3446

1

2

C3434

1

2

C3435

1

2

C3422

1

2

C3423

1

2

C3470

1

2

C3471

1

2

C3472

1

2

C3402

C3403

1

2

C3426

1

2

C3427

1

2

C3474

1

2

C3475

1

2

C3476

1

2

C3406

1

2

C3407

1

2

C3452

1

2

C3453

1

2

C3490

1

2

C3491

1

2

C3492

1

2

C3432

1

2

C3433

1

2

C3456

1

2

C3457

1

2

C3494

1

2

C3495

1

2

C3496

1

2

C3436

1

2

C3437

1

2

C3481

1

2

C3460

1

2

RP3410

36

RP3409

36

RP3411

27

RP3408

45

RP3411

36

C3462

1

2

C3464

1

2

C3467

1

2

C3461

1

2

C3463

1

2

C3465

1

2

C3466

1

2

RP3408

36

RP3410

45

RP3408

18

RP3410

27

RP3414

27

RP3413

27

RP3414

18

C3483

1

2

C3485

1

2

C3480

1

2

C3482

1

2

C3484

1

2

C3487

1

2

C3486

1

2

C3488

1

2

C3489

1

2

C3469

1

2

C3479

1

2

R3468

12

C3468

1

2

R3469

12

R3478

12

C3478

1

2

R3479

12

RP3401

45

RP3402

27

RP3406

27

RP3403

18

RP3402

18

RP3401

27

RP3403

27

RP3407

36

RP3406

18

RP3406

45

RP3402

36

RP3404

36

RP3403

45

RP3404

18

RP3407

27

RP3402

45

RP3403

36

RP3407

18

RP3404

27

RP3404

45

RP3401

36

RP3401

18

RP3406

36

RP3413

18

RP3410

18

RP3409

18

RP3413

36

RP3413

45

RP3409

45

RP3408

27

RP3409

27

RP3414

45

RP3411

18

RP3414

36

C3408

1

2

C3409

1

2

C3418

1

2

C3419

1

2

C3428

1

2

C3429

1

2

C3438

1

2

C3439

1

2

RP3411

45

RP3407

45

34 OF 109

3.13.0

051-8870

32 OF 75

32 28 27

7

32 30 29

7

68 28 27 11

68 30 29 11

32

30 29

7

32 28 27

7

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW CARD_DETECT_GND

DAT6 DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

CLK CMD

DAT0

SHLD_PIN

SHLD_PIN SHLD_PIN

SHLD_PIN

GPIO2

RSTZ*

THRM_PAD

TEST

SD_WP

D7

D6

D5

D0

SD_CLK

D3

D2

GPIO1

DVDD

IOVDD

MS_INS

SD_CDZ

SD_CMD

PLLVDD

AVDD

D4

D1

PMOS

RREF

GPIO0

DP DM

NC

BI

D

SG

D

SG

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Max Current = 800 mA

voltage must be less than 0.5V for at least 1ms per spec.

(IPU)

PDMOD: POWER DOWN MODES

(IPU)

(IPD)

10K HIGH = REMOTE WAKE UP ENABLE

Keep this net short!

516-0237

(IPD)

R3505 is for rail discharge. GL822 may cycle PMOS to recover from card error. Off duration is 100ms and card

10K LOW = POWER SAVING MODE ENABLE

NC = DISABLE (DEFAULT)

10PF

NO STUFF

5%

10PF

NO STUFF

10PF

5%

10PF10PF

CERM

NO STUFF

10PF

402

SD_CLK

0

1/16W

5%

CERM 402

MF-LF

5%

1/16W0402

33 MF

MF-LF

SD_WP

USB_SDCARD_N

USB_SDCARD_P

GL137_GPIO0

GL137_RREF

SD_D_R<1>

SD_D_R<4>

SDCARD_PLLVDD

SD_CMD_R

SD_CD_L

SDCARD_IOVDD

GL137_GPIO1

SD_D_R<2> SD_D_R<3>

SD_CLK_R

SD_D_R<0>

SD_D_R<5> SD_D_R<6> SD_D_R<7>

CRITICAL

GL822

QFN

10PF

CERM

NO STUFF

NPO

5%

NO STUFF

402

MIN_LINE_WIDTH=0.30 MM

SDCARD_PLT_RST

5%

69

5%

SD-CARD-K16

NO STUFF

5%

CERM

402

SD_D<6> SD_D<7>

SD_D<4>

SD_D<3>

SD_D<2>

SD_D<1>

VOLTAGE=3.3V

10PF

NO STUFF

5% 50V CERM

F-RT-TH

CRITICAL

X5R

MF

1/20W

1/16W

0

10PF

CERM 402

5%

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

PP3V3_S3_CARDREADER_AVDD

=PP3V3_S3_CARDREADER

SDCARD_PLT_RST_L

GL137_RESET_L

SDCONN_STATE_RST_RSDCONN_STATE_RST_L

SecureDigital Card Reader

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

25

18 23

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

5%

10K

MF

201

1/20W

NO STUFF

10K

MF

1/20W

201

5%

1%

201

MF

715

1/20W

NO STUFF

201

X5R

10%

0.1UF

6.3V

MF

47K

1/20W

201

5%

24

24 69

10%

201

X5R

6.3V

0.1UF

BYPASS=U3500.3:5:5 mm

0.1UF

10%

X5R

6.3V

BYPASS=U3500.1:16:5 mm

201

X5R

6.3V

5%

0

201

5%

1/16W

0

402

5%

1/16W

1/16W5%402

0

MF-LF

5%

1/16W

402

0

MF-LF

5%

1/16W

402

0

CERM

NO STUFF

50V

5%

402

CERM

NO STUFF

50V

CERM

5%

402

4.7UF

402

X5R-CERM1

6.3V

20%

402

X5R-CERM1

6.3V

4.7UF

20%

201

1/20W

10K

5%

MF

201

5%

10K

1/20W

MF

6.3V

0.1UF

10%

201

X5R

BYPASS=U3500.8:5 mm

201

BYPASS=U3500.8:5 mm

CRITICAL

0805-1

0.22UH

402

0402

50V

5% 50V

25V

5%

50V

NO STUFF

MF-LF

0

PP3V3_SW_SD_PWR

MIN_NECK_WIDTH=0.20 MM

MAKE_BASE=TRUE

0.1UF

6.3V

10%

33NH

201

1/20W

5%

1/16W

402

201

50V

SD_D<5>

402

5%

1/16W

0

10%

0.1UF

MF-LF

SD_CMD SD_D<0>

402

NO STUFF

MF-LF

5%

1/16W

0

50V50V

10PF

SD_CLK_L

0

5%

MF-LF

402

1/16W

SD_CLK_R2SD_CLK_R1

C3505

1

2

C3503

1

2

C3504

1

2

R3505

1

2

C3513

1

2

R3506

1

2

R3507

1

2

R3509

1

2

C3515

1

2

Q3500

3

5

4

Q3500

6

2

1

L3500

2

1

J3500

15

14

1

5

2

7

8

9

10

11

12

13

17

18

19

20

4

3

6

16

U3500

5

13 14 9 10 18 19 20 21

2

3

1716

22

6

17

82528

15

4

26 23

12

11

24

27

29

C3501

1

2

C3502

1

2

R3500

1

2

R3510

1

2

C3514

1

2

C3507

1

2

L3504

12

C3520

1

2

C3521

1

2

C3522

1

2

C3523

1

2

C3524

1

2

C3525

1

2

C3526

1

2

C3527

1

2

R3520

12

R3521

12

R3522

1

2

R3523

12

R3524

12

R3525

12

R3526

1

2

R3527

12

R3528

1

2

R3590

12

R3519

12

C3519

1

2

R3529

12

R3530

1

2

R3531

12

35 OF 109

3.13.0

051-8870

33 OF 75

6

7

6

OUT

BI

IN

D

VCC

THM

VSS

PAD

Q

C

S_L

W_L

HOLD_L

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

PETP_0

PETP_3

PERP_1

PERP_0

DPSRC0_ML_LANE_0N_OUT0_HDMI_TMDS_CLK_N

DPSRC0_ML_LANE_0P_OUT0_HDMI_TMDS_CLK_P

DPSRC0_ML_LANE_3P_OUT0_HDMI_TMDS_2_P DPSRC0_ML_LANE_3N_OUT0_HDMI_TMDS_2_N

DPSNK0_HDMI_IN_HOT_PLUG_DET

DPSNK0_AUX_CHN

DPSNK0_AUX_CHP

DPSNK0_ML_LANE_0N_IN0_HDMI_TMDS_2_N

DPSNK0_ML_LANE_0P_IN0_HDMI_TMDS_2_P

DPSNK0_ML_LANE_1N_IN0_HDMI_TMDS_1_N

DPSNK0_ML_LANE_1P_IN0_HDMI_TMDS_1_P

DPSNK0_ML_LANE_2P_IN0_HDMI_TMDS_O_P DPSNK0_ML_LANE_2N_IN0_HDMI_TMDS_0_N

DPSNK0_ML_LANE_3P_IN0_HDMI_TMDS_CLK_P

TEST_PWR_GOOD

PERP_3

TMU_CLK_IN

TMU_CLK_OUT

XTAL_25_IN

REFCLK_100_IN_N

TDO

TCK

TDI TMS

PCIE_RST_1*

PCIE_RST_0*

THERM_DP

EE_CS*

EE_DO

EE_DI

MONDC1

RBIAS

PETN_0

MONOBSP

PERN_0

PERN_3

MONDC0

MONOBSN

PETP_1 PETN_1

PETN_2

PETP_2

PETN_3

WAKE*

PERST*

CIO_PLUG_EVENT

CIO_1_LSOE

CIO_1_LSEO

PRT1_CIOR_P PRT1_CIOR_N

PRT1_CIOT_P

CIO_0_LSEO CIO_0_LSOE

PRT0_CIOR_P PRT0_CIOR_N

PRT0_CIOT_P PRT0_CIOT_N

HDMI_5V_OUT

HDMI_OUT_HOT_PLUG_DET

HDMI_SDA_IN

HDMI_SCL_IN

DP_RES

DP_ATEST

DPSRC0_HOT_PLUG_DET

TEST_EN

PCIE_CLKREQ_0*

EE_CLK

PERN_2

XTAL_25_OUT

RSENSE

REFCLK_100_IN_P

PCIE_RST_2* PCIE_RST_3*

DPSNK0_ML_LANE_3N_IN0_HDMI_TMDS_CLK_N

PERN_1

PERP_2

CIO_MDIO

CIO_MDC

PRT1_CIOT_N

PORT1 PORT0

PORTS

SINK PORT 0

SOURCE PORT 0

MISC

DISPLAYPORT

HDMI/

HDMI

CLK REQUEST

JTAG

POWER ON RESET

HDMI

TEST PORT

CLOCKS

EEPROM

PCIE GEN2

RECEIVE

TRANSMIT

(1 OF 2)

BI

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

SNK0 AC Coupling

100pF SRF > 40MHz

NOTE: All unused LSOE/EO pairs should be aliased

Not used in host mode.

(T29_SPI_MOSI)

(T29_SPI_CS_L)

(T29_SPI_CLK)

Use B1 GND ball for THERM_DN

DEBUG: For monitoring current/voltage

(T29_SPI_MISO)

together. Other signals okay to float (TP/NC).

DEBUG: For monitoring clock

8

72 44

72

8

72

8

72

8

72

8

72

8

72

8

72

8

72

8

72

8

72

8

2KX8-1.8V

OMIT_TABLE

CRITICAL

MLP

M95160

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70 25

36

8

70 16

8

16

72 64

64

72 64

64

FCBGA

OMIT_TABLE

CRITICAL

EAGLE_RIDGE-192

72 44

X5R10%

6.3V

201

0.1UF

20110%

6.3V

X5R

10% X5R

6.3V

0.1UF

201

20110%

6.3V

X5R

0.1UF

10% 201

0.1UF

X5R

6.3V

0.1UF

10%

6.3V

X5R 201

201

0.1UF

10%

6.3V

X5R

6.3V

0.1UF

10% X5R 201

0

NO STUFF

1/20W

5% MF

201

NO STUFF

201

0

1/20W

5% MF

20110%

6.3V

0.1UF

X5R

0.1UF

X5R

6.3V

10% 201

402

TF

1/16W

0.1%

1.0K

MF

10K

5% 1/20W

201

5%

MF

1/20W

0

5%

201

MF

1/20W

NO STUFF

201

MF

5%

10K

3.3K

201

MF

1/20W

5%

3.3K

201

MF

1/20W

5%

1/20W

201

MF

5%

3.3K

1/20W

201

MF

5%

201

5%

1/20W

MF

100K

MF

5%

201

100K

1/20W

201

MF

1/20W

1K

5%

201

MF

1/20W

1%

806

14K

MF

201

1/20W

1%

100PF

5%

201

CERM

25V

36

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

10%

0201

16V

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

10%

0201

16V

X5R-CERM

10%

0.1UF

X5R-CERM

16V

0201

201

1/20W

MF5%

10K

10% 16V

0201

X5R-CERM

0.1UF

10% 16V

0.1UF

0201

X5R-CERM

10% 16V

0.1UF

0201

X5R-CERM

10% 16V

0.1UF

0201

X5R-CERM

10% 16V

0.1UF

0201

X5R-CERM

10% 16V

0201

X5R-CERM

0.1UF

X5R-CERM

10% 16V

0.1UF

0201

0.1UF

X5R-CERM

10% 16V

0201

0.1UF

10% 16V

0201

X5R-CERM

10% 16V

0.1UF

0201

X5R-CERM

201

5%

10K

MF

1/20W

10K

5%

201

1/20W

MF

10K

5% 1/20W

201

MF

10K

5% 1/20W

201

5%01/20W

MF

201

0

1/20W

MF5%

201

5%01/20W

MF

201

1/20W0MF5%

X5R

10V

10%

0.01UF

201

0201-MUR

X5R

6.3V

20%

1.0UF

70

8

70

8

70

8

70

8

70

8

70

8

70

8

70

8

T29 Host (1 of 2)

SYNC_DATE=01/10/2011

SYNC_MASTER=K78_MLB

DP_T29SRC_ML_CP<3>

DP_T29SRC_ML_CN<0>

T29_TMU_CLK_OUT

DP_T29SRC_ML_CP<0>

DP_T29SRC_ML_CN<3>

T29_SPI_CLK

TP_T29_THERM_DP

T29_TEST_EN

PCIE_CLK100M_T29_P

TP_T29_PCIE_RESET3_L

TP_T29_PCIE_RESET1_L

JTAG_T29_TMS

TP_T29_MONDC1

T29_DP_RES

TP_T29_MONOBSN

TP_T29_HDMI_5V_OUT

DP_T29SNK0_ML_P<0>

T29_LSOE<0>

T29_LSEO<0>

T29_D2R_N<0>

T29_D2R_P<0>

T29_D2R_N<1>

DP_T29SNK0_AUXCH_C_N

T29_HDMI_SCL_IN

T29_HDMI_OUT_HPD

=PP3V3_T29_RTR

T29_CIO_PLUG_EVENT

T29_HDMI_SDA_IN

PCIE_T29_R2D_C_N<2>

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_P<3>

DP_T29SNK0_ML_N<2>

DP_T29SNK0_ML_N<0>

PCIE_T29_R2D_C_N<3>

PCIE_T29_R2D_C_P<2>

PCIE_T29_R2D_C_N<0>

PCIE_T29_R2D_C_P<0>

PCIE_T29_R2D_C_N<1>

PCIE_T29_R2D_C_P<1>

T29ROM_WP_L

SYSCLK_CLK25M_T29

PCIE_T29_R2D_C_P<3>

T29ROM_HOLD_L

TP_T29_MONDC0

TP_T29_MONOBSP

PCIE_T29_D2R_P<0>

PCIE_T29_D2R_N<0>

PCIE_T29_D2R_P<1>

PCIE_T29_D2R_N<1>

PCIE_T29_D2R_P<2>

PCIE_T29_D2R_N<2>

PCIE_T29_D2R_P<3>

PCIE_T29_D2R_N<3>

=PP3V3_T29_RTR

DP_T29SNK0_ML_N<1>

DP_T29SNK0_ML_C_N<1>

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_C_P<1>

DP_T29SNK0_ML_C_N<0>

DP_T29SNK0_ML_C_P<0>

DP_T29SNK0_ML_N<3>

DP_T29SNK0_ML_C_N<3>

DP_T29SNK0_ML_C_P<3>

DP_T29SNK0_ML_C_N<2>

DP_T29SNK0_ML_P<2>

DP_T29SNK0_ML_C_P<2>

DP_T29SNK0_AUXCH_C_P

DP_T29SNK0_AUXCH_N

=PP3V3_T29_RTR

T29_R2D_C_N<1>

I2C_T29_SCL I2C_T29_SDA

PCIE_T29_R2D_P<2>

PCIE_T29_R2D_N<1>

DP_T29SNK0_ML_N<3>

TP_T29_XTAL25OUT

PCIE_T29_R2D_N<2>

=T29_CLKREQ_L

DP_T29SRC_HPD

T29_HDMI_SCL_IN T29_HDMI_SDA_IN

T29_R2D_C_P<0>

T29_R2D_C_P<1>

T29_D2R_P<1>

T29_LSEO<1>

T29_CIO_PLUG_EVENT

T29_PCIE_WAKE_L

PCIE_T29_D2R_C_N<3>

PCIE_T29_D2R_C_P<2> PCIE_T29_D2R_C_N<2>

PCIE_T29_D2R_C_N<1>

PCIE_T29_D2R_C_P<1>

T29_MONOBSN

T29_MONDC0

PCIE_T29_R2D_N<3>

PCIE_T29_R2D_N<0>

T29_MONOBSP

PCIE_T29_D2R_C_N<0>

T29_RBIAS

T29_MONDC1

T29_SPI_MISO

SYSCLK_CLK25M_T29_R

T29_TMU_CLK_IN

PCIE_T29_R2D_P<3>

T29_TEST_POINT_3

DP_T29SNK0_ML_P<3>

DP_T29SNK0_ML_N<2>

DP_T29SNK0_ML_P<2>

DP_T29SNK0_ML_P<1> DP_T29SNK0_ML_N<1>

DP_T29SNK0_ML_P<0> DP_T29SNK0_ML_N<0>

DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N

DP_T29SNK0_HPD

PCIE_T29_R2D_P<0>

PCIE_T29_R2D_P<1>

PCIE_T29_D2R_C_P<3>

PCIE_T29_D2R_C_P<0>

T29_HDMI_OUT_HPD

T29_LSOE<1>

T29_RESET_L

T29_RSENSE

TP_T29_PCIE_RESET0_L

TP_T29_PCIE_RESET2_L

JTAG_T29_TDO

JTAG_T29_TDI

JTAG_T29_TCK

=PP3V3_T29_RTR

T29_R2D_C_N<0>

T29_DP_ATEST

PCIE_CLK100M_T29_N

T29_SPI_MOSI

T29_SPI_CS_L

=PP3V3_T29_RTR

U3690

6

5

7

2

1

9

8

4

3

U3600

H2 K1

J1 K2

C1 F1

H1

U15 U14

U7

T7

T4

U11

T11

U10

T10

U9

T9

U8

T8

T6

R12

N12

U12

T12

N1

U3

U6 P2

U1

F3

B1 A2

A14

A15

B13

A13

P1

R1 L1 L2 G2

P15

K15

F15

B14

P14

K14

F14

B15

C2

T15

M15

H15

D15

T14

M14

H14

D14

B4

A4

B6

A6

B8

A8

A10

B10

C7

B12

A12

C8

R2

T3

U4

E2

D1

B2

T5

M1

U5

M2

D11 C11

C3600

12

C3601

12

C3602

12

C3603

12

C3604

12

C3605

12

C3606

12

C3607

12

R3610

12

R3611

12

C3615

12

C3616

12

R3655

1

2

R3698

1

2

R3625

1

2

R3629

1

2

R3699

1

2

R3690

1

2

R3691

1

2

R3692

1

2

R3693

1

2

R3630

1

2

R3632

1

2

R3696

1

2

R3695

12

R3685

1

2

C3685

1

2

C3640

12

C3641

12

C3642

12

C3643

12

C3644

12

C3645

12

C3646

12

C3647

12

R3651

12

C3620

12

C3621

12

C3622

12

C3623

12

C3624

12

C3625

12

C3626

12

C3627

12

C3628

12

C3629

12

R3670

1

2

R3671

1

2

R3673

1

2

R3674

1

2

R3661

12

R3662

12

R3663

12

R3664

12

C3686

1

2

C3690

1

2

36 OF 109

3.13.0

051-8870

34 OF 75

72

47

72 34

34

36 35 34

7

34

72 34

36 35 34

7

72 34

36 35 34

7

70

72 34

70

34

70

70 70

72

70

72 34

70

34

36 35 34

7

72

36 35 34

7

VSSDP

VSS

VSSPE

VCC1P0_PE

VCC3P3

VCC3P3_CIO

VCC3P3_DP

VDD1P0_DP

VCC1P0

GPIO_0 GPIO_4

GPIO_6

GPIO_5

GPIO_7 GPIO_8

GPIO_9 GPIO_10 GPIO_11

GND

VCC

(2 OF 2)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

2100 mA (Single Port)

EDP: 3000 mA

2100 mA (Single Port) 2250 mA (Dual Port)

EDP: 200 mA

152 mA (Dual-Port)

135 mA (Single-Port)

0-ohms are placeholders for now, replace with proper values after characterization.

EDP: 3000 mA

2250 mA (Dual Port)

5%01/20W MF

201

1/20W05%

MF

CERM-X5R

0402

6.3V

20%

10UF

6.3V

CERM-X5R

20%

10UF

0402

201

10K

5%

1/20W

MF

201

MF

1/20W

5%

10K 10K

5% 1/20W MF 201

MF

1/20W

201

5%

10K

5% 1/20W MF 201201

MF

1/20W

5%

10K10K

5% 1/20W MF 201201

MF

1/20W

5%

10K

MF

201

10K

5%

1/20W

0402

CERM-X5R

6.3V

20%

10UF

0402

CERM-X5R

6.3V

20%

10UF

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R 0201-MUR

1.0UF

20%

6.3V X5R 0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R 0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R 0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R 0201-MUR

1.0UF

20%

6.3V X5R 0201-MUR

1.0UF

20%

6.3V X5R

0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R

0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R

0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R

0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R 0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

1.0UF

20%

6.3V X5R 0201-MUR

X5R

6.3V

20%

1.0UF

0201-MUR

EAGLE_RIDGE-192

OMIT_TABLE

CRITICAL

FCBGA

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

T29 Host (2 of 2)

T29_GPIO<4>

T29_GPIO<6>

T29_GPIO<5>

T29_GPIO<7> T29_GPIO<8> T29_GPIO<9> T29_GPIO<10> T29_GPIO<11>

=PP1V05_T29_RTR

T29_GPIO<0>

=PP1V05_T29_RTR

MIN_LINE_WIDTH=0.4 mm

PP3V3_T29_DP

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

=PP3V3_T29_RTR

PP1V05_T29_VDD_DP

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

U3600

J2

T2 T1

N2 U2 D2

E1 F2 G1

H3 H5

J8

J10

H6 H7 H8

H10

J3 J5 J6 J7

C10 C12

D7

D8 D10 D12 F11 F12 G11 G12

C3 D3

C5 C6 D5 D6

N8 N10 R8 R10

N5 N6 R5 R6

A1

F5

G8 G10

L3

L5

L6

L7

L8 L10

M3

M5

F6

M6

M7

M8 M10 M11 M12

F7

F8 F10

G3

G5

G6

G7

N3

N7 N11

R3

R7 R11 T13 U13

A3 A5

C14 C15 E14 E15 G14 G15 H11 H12 J11 J12

A7

J14 J15 L11 L12 L14 L15 N14 N15 R14 R15

A9 A11 B3 B5 B7 B9 B11

R3750

12

R3720

12

C3701

1

2

C3700

1

2

R3723

1

2

R3722

1

2

R3721

1

2

R3724

1

2

R3734

1

2

R3730

1

2

R3731

1

2

R3732

1

2

R3733

1

2

C3748

1

2

C3749

1

2

C3705

1

2

C3706

1

2

C3707

1

2

C3708

1

2

C3709

1

2

C3714

1

2

C3713

1

2

C3712

1

2

C3711

1

2

C3710

1

2

C3744

1

2

C3743

1

2

C3745

1

2

C3753

1

2

C3752

1

2

C3751

1

2

C3750

1

2

C3746

1

2

C3747

1

2

C3722

1

2

C3721

1

2

C3720

1

2

37 OF 109

3.13.0

051-8870

35 OF 75

35

7

35

7

36 34

7

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

OUT

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

GND

VOUT

ON

VIN

IN

D

GS

D

SG

D

SG

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

- =PP1V05_T29_P1V05T29FET (1.05V FET Input)

Vout = 15.1V

DLY = 60 ms +/- 20%

for 2S.

Max Current = 1.0A

Freq = 300KHz

<Ra>

18 mOhm Typ

<Rb>

U3810 & U3815/U3816

Max Vgs: 10V

50 mOhm Max

TPS22924C

Max Output: 2A per IC

Max Current = 3.4A (85C)

Max Current = 1.7A (85C)

R(on)

Part

Type

Pull-up provided by SB page.

Platform (PCIe) Reset

Open-Drain GPIO

Signal aliases required by this page:

- =T29_RESET_L

- =T29_CLKREQ_L

- =PP3V3_S0_T29PWRCTL

BOM options provided by this page:

U3816.A2:

Load Switch

SI8409DB:

SGND shorted to

- =PP1V05_T29_FET (1.05V FET Output)

1.05V T29 Switch

3.3V T29 Switch

no XW necessary.

GND inside package,

Changes required

8-13V Input

Page Notes

Power aliases required by this page:

- =PP18V_T29_REG (18V Boost Output)

- =PP3V3_T29_P3V3T29FET (3.3V FET Input)

- =PPVIN_SW_T29BST (8-13V Boost Input)

- =PP3V3_T29_FET (3.3V FET Output)

Pull-up provided by SB page.

T29BST:Y - Stuffs 18V boost circuitry.

Vout = 1.6V * (1 + Ra / Rb)

UVLO(rising) = UVLO(falling) + (2uA * R1)

Supervisor & CLKREQ# Isolation

add property on another page.

Voltage not specified here,

Id(max): 3.7A @ 70C

Vgs(th): -1.4V

Vds(max): -30V

<R1>

<R2>

UVLO(falling) = 1.22 * (R1 + R2) / R2

UVLO = 4.55V (falling), 4.95 (rising)

T29 18V Boost Regulator

Rds(on): 46mOhm @ 4.5V Vgs

Vgs(max): +/-12V

201

MF

1%

10K

T29BST_PWREN_L

T29_RESET_L

DIDT=TRUE

PPVIN_SW_T29BST_R

T29_A_HV_EN

T29BST_SHDN_DIV

=PP3V3_S0_T29PWRCTL

=PP1V05_T29_FET

=PP1V05_S0_P1V05T29FET

=T29_CLKREQ_L

=T29_RESET_L

T29BST_SS

SMC_DELAYED_PWRGD

=PP3V3_S0_P3V3T29FET

T29_CLKREQ_L

T29_SW_RESET_L

MAKE_BASE=TRUE

T29_CLKREQ_ISOL_L

PP1V05_T29

=PP3V3_T29_FET

=PPVIN_SW_T29BST

T29BST_VC_RC

T29_PWR_EN

=PP15V_T29_REG

T29BST_VSNS

T29BST_FBX

T29BST_SNS2

GND_T29BST_SGND

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

T29BST_RT

=PP3V3_T29_RTR

T29BST_EN_UVLO

PPVIN_SW_T29BST

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

T29 Power Support

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

T29BST:Y

CRITICAL

PIMB062D-SM

1%

MF

805

T29BST:Y

133K

1% 1/16W MF-LF

402

5%

201

MF

1/20W

150K

T29BST:Y

3300PF

10% 10V X7R 201

T29BST:Y

X7R

0.001UF

10% 50V

402

T29BST:Y

50V

X7R-CERM

10%

1206

4.7UF

DFLS230L

T29BST:Y

CRITICAL

POWERDI-123

201

1/20W

5%

0

MF

T29BST:Y

PLACE_NEAR=C3895.1:2 mm

SM

T29BST:Y

CRITICAL

LT3957

QFN

402

10PF

5% 50V CERM

T29BST:Y

25V

10%

X5R 805

10UF

10%

X5R 805

25V

T29BST:Y

10UF

T29BST:Y

CRITICAL

SI8409DB

BGA

T29BST:Y

10V

10%

805

47PF

5% 25V NP0-C0G 201

T29BST:Y

1206

X7R-CERM

4.7UF

10% 50V

T29BST:Y

X7R-CERM

4.7UF

1206

50V

10%

1206

T29BST:Y

50V

4.7UF

X7R-CERM

10%

1%

T29BST:Y

402

MF-LF

1/16W

15.8K

NO STUFF

100PF

5% 50V CERM 402

25 41

201

330K

5%

T29BST:Y

MF

1/20W

6.3V

0.33UF

CERM-X5R

10%

402

T29BST:Y

41.2K

MF

1/20W

T29BST:Y

201

1%

SSM6N37FEAPE

T29BST:Y

SOT563

T29BST:Y

SSM6N37FEAPE

201

1/20W MF

T29BST:Y

5%

330K

73.2K

T29BST:Y

1%

201

1/20W

SSM3K15FV

SOD-VESM-HF

T29BST:Y

25V

10%

402

X5R

T29BST:Y

0.1UF

201

5%

MF

1/20W

470K

T29BST:Y

64 65

19

PLACE_NEAR=U3815.B2:3 mm

CSP

CRITICAL

TPS22924

19

5%

100K

MF

1/20W

201

CRITICAL

SLG4AP016V

TDFN

402

CERM

6.3V

10%

1UF

402

CERM

1UF

10%

6.3V

34

25

0.1UF

10% 16V

X5R-CERM

0201

16

201

10K

1/20W

MF

5%

34

CRITICAL

CSP

TPS22924

CRITICAL

CSP

TPS22924

1/20W

T29BST_VC

T29BST_INTVCC

1/4W

0.010

VOLTAGE=0V

T29BST:Y

MF

1/20W

1%

200K

T29BST:Y

201

X5R

4.7UF

T29BST_PWREN_DIV_L

MF

MIN_LINE_WIDTH=0.5 mm

T29BST_SNS1

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

T29BST_BOOST

6.8UH-4.0A

U3810

C1

C2

A2

B2

A1

B1

U3815

C1

C2

A2

B2

A1

B1

R3803

12

C3800

1

2

C3810

1

2

C3815

1

2

U3800

6

5

7

3

8

4

2

9

1

R3807

1

2

U3816

C1

C2

A2

B2

A1

B1

R3880

1

2

C3880

1

2

Q3805

3

1

2

R3892

1

2

R3887

1

2

Q3888

3

5

4

Q3888

6

2

1

R3894

1

2

C3894

1

2

R3888

1

2

C3889

1

2

R3896

1

2

C3895

1

2

C3896

1

2

C3897

1

2

C3887

1

2

C3892

1

2

Q3880

23

1

4

C3890

1

2

C3891

1

2

C3888

1

2

U3890

25

31

1213141516

17

28

1

2

10

35

36

33

6

3

42324

37

32

8

9

202138

34

30

27

XW3895

12

R3889

1

2

D3895

1

2

C3898

1

2

C3899

1

2

C3893

1

2

R3881

1

2

R3895

1

2

R3820

12

L3895

12

R3893

1

2

R3891

1

2

38 OF 109

3.13.0

051-8870

36 OF 75

7

7 7

7

6 7

7

7 8

7

34 35

6 7

OUT

IN

BI

OUT

S

G

D

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

DLY = 60 MS +/- 20%

514S0335

CHANNEL

0.750 A (EDP)

P-TYPE

3V S3 WLAN FET

TPCP8102

20-30 MOHM @2.5V

MOSFET

LOADING

RDS(ON)

AIRPORT

BLUETOOTH

17

6

62

0.1UF

X5R20110%

6.3V

PLACEMENT_NOTE=Place close to J4001.

70 16

0.1UF

PLACEMENT_NOTE=Place close to J4001.

6.3V

10% 201X5R

70 16

6

70 16

6

0.1UF

X5R

PLACEMENT_NOTE=Place close to Q4050.

6.3V

10%

201

69 24

6

69 24

6

70 16

6

70 16

6

CRITICAL

0.020

1%

0.25W 805

MF-LF

74 46

CRITICAL

23V1K-SM

TPCP8102

SLG4AP016V

TDFN

CRITICAL

201

6.3V

10% X5R

0.1UF

23 16

25

62 18

5%

201

MF

100K

1/20W

100K

MF

201

1%

1/20W

201

1/20W

1% MF

232K

0.1UF

X5R 201

10%

6.3V

PLACE_NEAR=J4001.18:1.5mm

SSD-K99

CRITICAL

F-RT-SM1

41

6

PLACEMENT_NOTE=Place close to Q4050.

603

10UF

20% 10V X5R

0.1UF

0201

X5R-CERM

16V

10%

5%

0

201

MF

1/20W

16V

10%

402

0.033UF

X5R

1/20W

5%

201

MF

100K

5% 1/20W

201

MF

10K

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

X21 WIRELESS CONNECTOR

=PP3V3_S3_WLAN

WIFI_EVENT_L

PCIE_CLK100M_AP_P

=PP3V3_S3_BT

PCIE_AP_R2D_P

ISNS_AIRPORT_P

PM_WLAN_EN_L

AP_PWR_EN

=PP3V3_S3_WLAN

USB_BT_P

PCIE_AP_R2D_N

PCIE_AP_R2D_C_N

PCIE_WAKE_L

AP_CLKREQ_Q_L

PCIE_CLK100M_AP_N

ISNS_AIRPORT_N

PCIE_AP_D2R_P

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

PP3V3_WLAN_F

P3V3WLAN_SS

PP3V3_WLAN_R

MIN_NECK_WIDTH=0.25 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=1 mm

PCIE_AP_R2D_C_P

PCIE_AP_D2R_N

AP_RESET_CONN_L

USB_BT_N

AP_RESET_L

P3V3WLAN_VMON

AP_CLKREQ_L_R

AP_CLKREQ_L

C4021

1

2

C4051

1

2

R4050

12

R4051

1

2

C4030

12

C4031

12

R4052

12 34

Q4050

5678

4

123

U4002

6

5

7

3

8

4

2

9

1

C4053

1

2

R4053

1

2

R4055

1

2

R4054

1

2

C4032

1

2

J4001

19

20

21

1

10

11

12

13

14

15

16

17

18

2

3

4

5

6

7

8

9

C4020

1

2

C4050

12

R4090

12

40 OF 109

3.13.0

051-8870

37 OF 75

37

7

7 6

70

6

37

7

70

6

OUT

NC NC

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

SATA SSD

CRITICAL

1%

0.003

1W MF

0612

74 46

F-RT-SM1

SSD-K99

CRITICAL

1/20W

0

MF

5%

201

5%

MF

1/20W

0

201

0201

PLACE_NEAR=J4501.1:1.5mm

0.1UF

10% 16V X5R-CERM

69 16

10%

0.01UF

20110V X5R

PLACE_NEAR=J4501.3:1.5MM

PLACE_NEAR=J4501.8:1.5MM

0.01UF

X5R10% 20110V

0.01UF

X5R10% 10V 201

PLACE_NEAR=J4501.7:1.5MM

X5R10% 10V

0.01UF

201

PLACE_NEAR=J4501.4:1.5MM

SYNC_MASTER=K78_MLB

SATA CONNECTOR

SYNC_DATE=01/10/2011

SATA_HDD_D2R_N

ISNS_HDD_N

ISNS_HDD_P

=PP3V3_S0_HDD

TP_SSD_RSRVD

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SMC_HDD_OOB_TEMP

SMC_HDD_TEMP_CTL_CONN

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_N

SMC_HDD_TEMP_CTL

SMC_HDD_OOB_TEMP_CONN

SATA_HDD_R2D_P

SATA_HDD_D2R_P

PP3V3_S0_HDD_R

VOLTAGE=5V

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

GND_VOID=TRUE

C4516

12

C4510

12

C4511

12

C4515

12

R4599

12 34

J4501

19

20

21

1

10

11

12

13

14

15

16

17

18

2

3

4

5

6

7

8

9

R4510

12

R4511

12

C4501

1

2

45 OF 109

3.13.0

051-8870

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

38 OF 75

7

41

6

69

6

69

6

69

6

41

6

69

6

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

NC

BI

SYM_VER-1

IN

OUT

IN

OUT

IOIONC

GND

VBUS

NC

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

VBUS

D-

D+

GND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

SEL=0 Choose SMC

Current limit (R4600): 2.3A max

SEL=1 Choose USB

USB/SMC Debug Mux

Place L4605 at connector pin

Right USB Port A

USB Port Power Switch

We can add protection to 5V if we want, but leaving NC for now

5%

10K

SMC_DEBUG_YES

MF 201

1/20W

0

201

1/20W

MF

5%

SMC_DEBUG_NO

5%

SMC_DEBUG_NO

1/20W

MF

201

0

0201

16V

10%

X5R-CERM

0.01UF

SON

TPS2561DR

CRITICAL

FERR-120-OHM-3A

0603

201

MF

1/20W

0

5%

CRITICAL

220UF-35MOHM

20%

6.3V POLY-TANT CASE-B2-SM1

MF-LF

1/16W

1%

23.2K

402

69 24

CRITICAL

DLP11S

90-OHM-100MA

43 42 41

6

43 42 41

6

41

24

RCLAMP0502N

CRITICAL

SLP1210N6

SMC_DEBUG_YES

CRITICAL

TQFN

PI3USB102ZLE

CRITICAL

F-RT-TH

USB-RIGHT-K99

CERM-X5R

0402

10UF

20%

6.3V CERM-X5R

6.3V

20%

0402

10UF

10%

0201

16V

0.1UF

X5R-CERM

0201

X5R-CERM

16V

10%

0.1UF

SMC_DEBUG_YES

SYNC_DATE=12/13/2010

SYNC_MASTER=K21_MLB

External USB Connectors

USB2_LT1_N

USB2_LT1_P

MIN_NECK_WIDTH=0.375 mm

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

USB_EN2

SMC_RX_L

USB_EXTA_P

SMC_TX_L

=PP3V42_G3H_SMCUSBMUX

USB_DEBUGPRT_EN_L

USB_EXTA_N

=USB_PWR_EN

USB_EXTA_OC_L

USB2_EXTA_MUXED_P

=PP5V_S3_RTUSB

PP5V_S3_RTUSB_A_ILIM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm

USB2_EXTA_MUXED_N

USB_ILIM

L4605

12

L4600

12

34

D4600

1

54

6

U4650

6

7

3

4

5

8

10

9

2

1

J4600

2

3

4

5

6

1

C4690

1

2

C4695

1

2

C4691

1

2

C4650

1

2

R4650

1

2

R4651

12

R4652

12

C4605

1

2

U4600

4 5

10

6

1

7

2 3

9 8

11

R4601

1

2

C4696

1

2

R4600

1

2

46 OF 109

3.13.0

051-8870

39 OF 75

23

74

7

62 40

6

74

7

74

BI

IN

OUT

IN

OUT

BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

(Right Speaker Enable)

516S0862

69 24

6

69 24

6

69 18

6

69 18

6

70 16

6

70 16

6

70 16

6

70 16

6

70 16

6

24

6

62 39

6

44

6

44

6

19

6

42 41

6

18

6

18

6

51

6

74 51

6

74 51

6

44

6

44

6

41

6

49 42 41

6

PLACE_NEAR=J4700.23:1.5mm

0201

X5R-CERM

16V

10%

0.1UF

PLACE_NEAR=J4700.26:1.5mm

X5R-CERM 0201

0.1UF

10% 16V

PLACE_NEAR=J4700.34:1.5mm

X5R-CERM 0201

0.1UF

10% 16V

CRITICAL

AXK736327G

F-ST-SM

Left I/O (LIO) Connector

SYNC_MASTER=K21_MLB

SYNC_DATE=11/09/2010

AUD_GPIO_3

SPKRAMP_INR_P

SPKRAMP_INR_N

AUD_I2C_INT_L

=I2C_MIKEY_SDA

=PP3V42_G3H_ONEWIRE

AUD_IPHS_SWITCH_EN AUD_IP_PERIPHERAL_DET

=I2C_LIO_SCL

=I2C_MIKEY_SCL

SMC_BC_ACOK

SYS_ONEWIRE

=USB_PWR_EN SMC_LID =I2C_LIO_SDA

HDA_SDIN0

=PP3V3R1V5_S0_AUDIO

HDA_SYNC

=PP3V3_S0_AUDIO

USB_EXTD_OC_L HDA_RST_L

USB_CAMERA_N USB_CAMERA_P

HDA_SDOUT HDA_BIT_CLK

USB_EXTD_P

USB_EXTD_N

C4710

1

2

C4700

1

2

C4720

1

2

J4700

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

4

5

6

7

8

9

47 OF 109

3.13.0

051-8870

40 OF 75

7 6

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

IN

P11

P82 P83

P35

P96

P95

P94

P93

P92

P91

P90

P86

P85

P84

P81

P80

P77

P67

P52

P51

P50

P47

P46

P45

P44

P43

P42

P41

P40

P37

P36

P34

P33

P32

P31

P30

P27

P26

P25

P24

P23

P21

P17

P12

P66P16

P15

P14

P13

P22

P20

P63

P61

P60

P65

P64

P62

P70 P71 P72 P73 P74 P75 P76

P97

P10

(1 OF 3)

PEVREF/PH4

PECI/PH3

PH2

PG5

PG4

PG3

PG2

PG1

PG0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PE4

PE3

PE2

PE1

PE0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PA7

PA6

PA3

PA2

PA1

PA0

PA4 PA5

PG6 PG7

PH0 PH1

PEVSTP/PH5

(2 OF 3)

EXTAL

XTAL

RES*

VSS

AVSS

ETRST*

NMI

MD2

MD1

NC

AVCC

VCC

VCL

AVREF

(3 OF 3)

OUT

NC

INBI

OUT

IN

OUT

NC

OUT

IN

NC

BI

IN

OUT

BI

IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

(OC)

(OC) (OC) (OC)

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

(OC)

X5R-CERM

10V

22UF

805

20%

43 17

6

53 43 42

6

49 42

6

0.1UF

CERM

10V

20%

402

PLACE_NEAR=U4900.M12:3mm

0.1UF

CERM

402

20% 10V

10V

20%

402

CERM

0.1UF

SM

PLACE_NEAR=U4900.L3:4mm

23 17

36 25

10V

20%

402

CERM

0.1UF

17

62

62 52 25 23

42

10V

20%

402

CERM

0.1UF

42

42 40

6

43 42 41 39

6

43 42 41 39

6

62

44

43

6

43

6

39

40

6

62 42

42

48

42

48

42

43 42

6

42

43 42

6

43 42

6

43 42

6

49 42 40

6

44

42

43 42 41 39

6

43 42 41 39

6

42

43 16

6

42

25 17

43

6

19 16

43 17

6

42

62 42 17

42

OMIT_TABLE

DF2117RVPLP20HV

TLP-145V

OMIT_TABLE

TLP-145V

DF2117RVPLP20HV

OMIT_TABLE

TLP-145V

DF2117RVPLP20HV

16

42 37

6

201

MF

1/20W

5%

43

201

MF

1/20W

0

5%

201

MF

1/20W

5%

0

10V

CERM

0.1UF

20%

402

62 42

49 42

6

42 19

38

1/20W

10K

5%

MF

201

5% 1/20W MF

10K

201

NO STUFF

0

5%

MF

1/20W

201

10K

5% 1/20W MF 201

5%

10K

1/20W MF 201

20%

0.47UF

CERM-X5R-1

4V

BYPASS=U4900.E1:D2:3 mm

201

4.7

5%

1/20W

MF

PLACE_NEAR=U4900.M12:3mm

201

70 43 16

6

70 43 16

6

70 43 16

6

70 43 16

6

70 43 16

6

25

70 25

49

44

62 26 17

62 49 26 17

62 17

42

44

42

SMC

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

SMC_CASE_OPEN SMC_TCK SMC_TDI

SMC_TX_L SMC_RX_L

SMB_0_S0_DATA

PM_SLP_S5_L SMC_CLK32K

=PP3V3_S5_SMC

SMC_VCL

SMC_MD1

SMC_NMI

SMC_KBC_MDE

SMC_TRST_L

SMC_HDD_OOB_TEMP SMB_MGMT_DATA

SMB_0_S0_CLK

SPI_DESCRIPTOR_OVERRIDE_L

SMC_BATLOW_L

SYS_ONEWIRE

WIFI_EVENT_L

MEM_EVENT_L

SMC_GFX_THROTTLE_L

SMC_HDD_TEMP_CTL

LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L

LPC_SERIRQ

SMC_P43

PM_CLKRUN_L LPC_PWRDWN_L

PM_SLP_S3_L

SMC_PME_S4_WAKE_L

SMC_BC_ACOK

SMC_ONOFF_L

SMB_MGMT_CLK

SMC_RX_L

SMC_TX_L

SMC_BIL_BUTTON_L

SMC_SYS_KBDLED

LPC_CLK33M_SMC

LPC_AD<0>

SMC_P26

SMC_P24

SMC_PROCHOT_3_3_LSMC_DELAYED_PWRGD

SMC_P20

SMC_PM_G2_EN

SMC_ADAPTER_EN

SMC_ADC0 SMC_ADC1 SMC_ADC2 SMC_ADC3 SMC_ADC4 SMC_ADC5

SMC_P10

SMC_S4_WAKESRC_EN

SMC_PB4

SMC_DP_HPD_L

SMC_FAN_0_CTL

PM_SYSRST_L

SMC_GFX_OVERTEMP_L

SMC_FAN_0_TACH

SMC_FAN_3_TACH

=PPVCCIO_S0_SMC

PM_PECI_PWRGD

PVCCIO_S0_SMC_R

SMB_A_S3_CLK

SMC_ADC15

CPU_PECI

SMC_RESET_L

SMC_XTAL SMC_EXTAL

PM_PECI_PWRGD_R

CPU_PECI_R

SMC_THRMTRIP

G3_POWERON_L

SMC_TDO

SMB_B_S0_CLK

SMC_FAN_2_CTL

SMC_TMS

SMC_FAN_1_CTL

SMC_FAN_3_CTL

GND_SMC_AVSS

SMC_ADC14

SMC_ADC13

SMC_ADC12

SMC_ADC11

SMC_ADC10

SMC_ADC9

SMC_ADC8

SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_RUNTIME_SCI_L

USB_DEBUGPRT_EN_L

SMC_PA0_PU

PM_SLP_S4_L

SMC_RSTGATE_L

PP3V3_S5_AVREF_SMC

SMC_ADC6

SMB_A_S3_DATA

SMC_LID

SMB_BSA_CLK

SMB_B_S0_DATA

=SMC_SMS_INT SMB_BSA_DATA

SMC_PF5

MIN_NECK_WIDTH=0.1 MM

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM

SMC_PROCHOT

SMC_SCI_L

SMC_ADC7

PM_PWRBTN_L

PM_DSW_PWRGD

S5_PWRGD

ALL_SYS_PWRGD

C4902

1

2

C4903

1

2

C4904

1

2

C4905

1

2

C4906

1

2

C4920

1

2

XW4900

12

U4900

B12

A13

A12

B13

D11

C13

C12

D10

D13

E11

D12

F11

E13

E12

F13

E10

A9

D9

C8

B7

A8

D8

D7

D6

D4

A5

B4

A1

C2

B2

C1

C3

G2

F3

E4

L13

K12

K11

J12

K13

J10

J11

H12

N10

M11

L10

N11

N12

M13

N13

L12

A7

B6

C7

D5

A6

B5

C6

J4

G3

H2

G1

H4

G4

F4

F1

U4900

N3

N1

M3

M2

N2

L1

K3

L2

B8

C9

B9

A10

C10

B10

C11

A11

G11

G13

F12

H13

G10

G12

H11

J13

M10

N9

K10

L8

M9

N8

K9

L7

K1

J3

K2

J1

K4

A4

B3

C4

K5

N5

M6

L5

M5

N4

L4

M4

M8

N7

K8

K7

K6

N6

M7

L6

E2

F2

J2

U4900

M12

L11

L9

H3

A2

D1

H1

E3

D3

B1M1H10

E1

D2

L3

F10

B11

C5

A3

R4910

12

R4911

12

R4912

12

C4910

1

2

R4909

1

2

R4901

1

2

R4903

1

2

R4998

1

2

R4902

1

2

C4907

1

2

R4999

12

49 OF 109

3.13.0

051-8870

41 OF 75

E5

42

7

42

7

62

67 19 10

42

46 45 42

42

D

SG

IN

OUT

BI

IN

D

SG

G

D

S

OUT

IN

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

OUT

IN

OUT

IN

OUT

D

GS

OUT

D

GS

IN

NC NC

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

SMC Reset "Button", Supervisor & AVREF Supply

NOTE: Internal pull-ups are to VIN, not V+.

Debug Power "Buttons"

Used on mobiles to support SMC reset via keyboard.

BATLOW# Isolation

PROCHOT Level Shifting to 3V3

TO CPU

(IPU)

TO SMC

Mobiles: 3.42V

Desktops: 5V

SMC Crystal Circuit

Internal 20K pull-up on PM_BATLOW_L in PCH.

Check with SMC pullup S0

MR1* and MR2* must both be low to cause manual reset.

Below connections are different from K91

SOT563

SSM6N37FEAPE

5%

10K

1/20W

MF

201

5%

100K

1/20W

MF

201

10K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

5%

10K

1/20W

MF

201

5%

10K

1/20W

MF

201

5%

10K

1/20W

MF

201

10K

5%

1/20W

MF

201

1/20W

10K

5%

201

MF

5%

10K

1/20W

MF

201

MF

10K

1/20W

41

19

SILK_PART=PWR_BTN

PLACE_SIDE=TOP

1/10W MF-LF

0

OMIT

603

5%

3.3K

1/20W

MF

201

67 57 10

41

SSM6N37FEAPE

SOT563

100K

5%

1/20W

MF

201

10K

5%

1/20W

MF

201

0

5%

1/20W

MF

201

25V NPO 201

15PF

5%

470K

1/20W

MF

201

5%

201

MF

1/20W

5%

10K

5%

10K

1/20W

MF

201

DMB53D0UV

SOT-563

5%

100K

1/20W MF 201

DMB53D0UV

SOT-563

10K

5% 1/20W MF 201

41

PLACE_SIDE=BOTTOM

OMIT

MF-LF

603

5%

0

SILK_PART=PWR_BTN

PLACEMENT_NOTE=Place R5001 on BOTTOM side

OMIT

5%

MF-LF

0

603

1/10W

SILK_PART=SMC_RST

49 42 41

6

49

6

201

X5R

10V

10%

0.01UF

0.47UF

6.3V

10%

402

CERM-X5R

DFN

10uF

20%

X5R

6.3V

603 201

X5R

10V

10%

0.01UF

53 43 41

6

17

MF

1/20W

PLACE_NEAR=U1800.N14:5.1mm

5%

22

201

41

10K

5%

1/20W

MF

201

64

41

100K

1/20W MF 201

5%

SSM3K15FV

SOD-VESM-HF

201

MF

1/20W

100K

5%

MF 201

1/20W

49 41

6

5%

NO STUFF

1/20W MF 201

1M

100K

5%

1/20W

MF

201

17

5%

MF

201

1/20W

100K

0

5%

1/20W

MF

201

NOSTUFF

SOD-VESM-HF

CRITICAL

SSM3K15FV

62 41

SM-2.5X2.0MM

20MHZ

CRITICAL

201

15PF

5%

NPO

25V

5%

1/20W

201

MF

49 42 41

6

SYNC_DATE=01/10/2011

SYNC_MASTER=K78_MLB

SMC Support

=PP3V3_S5_SMC

MAKE_BASE=TRUE

TP_SMC_GFX_THROTTLE_L

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=0V

MIN_NECK_WIDTH=0.1 mm

SMC_ONOFF_L

SMC_TPAD_RST_L

SMC_ADC14

SMC_RSTGATE_L

SMC_CLK32K

TP_SMC_ADC13

MAKE_BASE=TRUE

SMC_ADC13

SMC_BC_ACOK

SMC_TMS

SMC_THRMTRIP

MAKE_BASE=TRUE

HISIDE_ISENSE_OC

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

SMC_PA0_PU

SMC_FAN_1_CTL

SMC_PB4

SMC_ADAPTER_EN

SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

TP_SMC_PF5

TP_SMC_P10

MAKE_BASE=TRUE

SMC_P10

SMC_ADC15

SMC_P24

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

SMC_P20

SMC_RUNTIME_SCI_L

SMC_PA0_PU

=PP3V3_S0_SMC

=PP3V3_S4_SMC

=PPVIN_S5_SMCVREF

SMC_ADC3

SMC_GFX_VSENSE

MAKE_BASE=TRUE

SMC_GFX_ISENSE

MAKE_BASE=TRUE

SMC_TCK

SMC_TDI

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMS_INT_L

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL

SMC_EXTAL

PM_CLK32K_SUSCLK_R

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3V

SMC_RESET_L

SMC_ADC5

=SMC_SMS_INT

CPU_PROCHOT_L_R

=PP3V3_S5_SMCBATLOW

PM_BATLOW_L

SMC_GFX_OVERTEMP_L

SMC_ONOFF_L G3_POWERON_L

PM_THRMTRIP_L_R

SMC_PROCHOT

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH

SMC_BC_ACOK

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

SMC_CPU_VSENSE

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

MAKE_BASE=TRUE

SMC_HS_COMPUTING_ISENSE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_1V5S3_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

MAKE_BASE=TRUE

SMC_HDD_ISENSE

SMC_WLAN_ISENSE

MAKE_BASE=TRUE

SMC_ADC4

SMC_ADC1

SMC_FAN_3_CTL

SMC_P26

=CHGR_ACOK

SMC_FAN_3_TACH

SMC_BATLOW_L

SMC_GFX_THROTTLE_L

SMC_FAN_1_TACH

SMC_XTAL

SMC_FAN_2_TACH

CPU_PROCHOT_BUF

SMC_PROCHOT_3_3_L

=PP3V3_S0_SMC

SMC_FAN_2_CTL

SMC_CASE_OPEN

SMC_TDO

SMC_BIL_BUTTON_L

=PP3V3_SUS_SMC

SMC_ONOFF_L

DP_A_EXT_HPD

SMC_XTAL_R

TP_SMC_ADC15

MAKE_BASE=TRUE

SMC_P43

SMC_PF5

SMC_ADC0

SMS_INT_L

MEM_EVENT_L

SMC_DP_HPD_L

=PP3V3_S5_SMC

TP_SMC_P20

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

CPU_PROCHOT_L

SMC_CPUVCCIO_ISENSE

MAKE_BASE=TRUE

SMC_ADC12

SMC_ADC2

SMC_MANUAL_RST_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

TP_SMC_P43

MAKE_BASE=TRUE

SMC_ADC11

SMC_ADC10

SMC_ADC9

SMC_ADC8

SMC_ADC7

SMC_ADC6

1/10W

5%

100K

MF 201

1/20W

VREF-3.3V-VDET-3.0V

=PP3V3_S4_SMC

SMC_PME_S4_WAKE_L

SMC_RX_L

10K

=PP3V3_S5_SMC

SMC_TX_L

SMC_LID

5%

NOSTUFF

Q5059

3

5

4

R5070

12

R5071

12

R5073

12

R5074

12

R5077

12

R5078

12

R5079

12

R5080

12

R5085

12

R5086

12

R5088

12

R5015

1

2

R5062

12

Q5059

6

2

1

R5091

12

R5081

12

R5010

12

C5010

12

R5087

12

R5093

12

R5072

12

Q5060

5

3

4

R5061

1

2

Q5060

6

2

1

R5060

1

2

R5016

1

2

R5001

1

2

C5001

1

2

C5020

1

2

U5010

4

2

6

7

8

5

9

1

3

C5025

1

2

C5026

1

2

R5012

12

R5095

12

R5020

1

2

Q5020

3

1

2

R5090

12

R5076

1

2

R5011

1

2

R5094

12

R5040

1

2

R5041

12

Q5040

3

1

2

Y5010

24

13

C5011

12

R5075

12

R5000

1

2

50 OF 109

3.13.0

051-8870

42 OF 75

42 41

7

46 45 41

41

42 41 40

6

43 41

6

46 42 41

41

62 41 17

62 41

41

46

45

41

41 19

42 41

42

7

42

7

41

45

43 41

6

43 41

6

45

42

41

43 41 39

6

7

41

49 42 41

6

41

49 41 40

6

43 41 39

6

42 41 40

6

45

46

41

53 45

41

42

7

41

42

7

41

43 41

6

41

7

41

42

42 41

7

41

42 41

7

45

46

45

41

OUT

IN

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

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21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

516S0573

LPC+SPI Connector

SPI Bus Series Termination

SPI_ALT_MOSI

SPI_MOSI

SPI_CS0_L

SPI_ALT_MISO

SPI_MISO

SMC_TDI

SPI_MLB_MOSI

=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS

LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>

SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L

SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO

LPC_AD<0> LPC_AD<1>

SPI_ALT_MOSI SPI_ALT_MISO

PM_CLKRUN_L

LPC_FRAME_L

SMC_TMS LPCPLUS_RESET_L

SMC_MD1

SMC_TRST_L

SMC_TX_L

SPIROM_USE_MLB

SPI_ALT_CLK

SMC_TDO

SPI_ALT_CLK SPI_ALT_CS_L

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MOSI_R

SPI_CLK_R

SPI_CLK

SPI_CS0_R_L

SPI_MLB_MISO

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

LPC+SPI Debug Connector

1/20W

PLACE_NEAR=R5126.2:5mm

MF

5%

47

201

PLACE_NEAR=J5100.14:5mm

201

1/20W

LPCPLUS

47

5%

MF

PLACE_NEAR=R5125.2:5mm

MF

47

1/20W

5%

201

16 70

201

1/20W

PLACE_NEAR=U6100.2:5mm

MF

15

5%

50 70

16 70

PLACE_NEAR=U1800.AD12:5mm

5%

1/20W

201

MF

15

50 70

16 70

PLACE_NEAR=U1800.AB8:5mm

201

5%

1/20W

MF

15

50 70

402

LPCPLUS

47

5% 1/16W MF-LF

402

LPCPLUS

0

MF-LF

1/16W

5%

6

25 70

6

16 41 70

6

16 41 70

6

19 50

6

43

6

43

6

16 41

6

17 41

6

41 42

6

16 41 70

6

16 41 70

6

43

6

17 41

6

16 41 70

6

43

6

25

6

41 42

6

41 42

6

41 42 53

6

41

6

39 41 42

6

19

M-ST-SM

LPCPLUS

CRITICAL

55909-0374

6

41 42

6

41

6

41

6

39 41 42

16 70

PLACE_NEAR=U1800.W8:5mm

1/20W

201

5%

MF

15

PLACE_NEAR=R5127.2:5mm

MF

1/20W

5%

47

201

50 70

PLACE_NEAR=J5100.12:5mm

201

5% 1/20W

LPCPLUS

MF

47

R5110

12

R5111

12

R5123

12

R5120

12

R5125

1

2

R5121

12

R5126

1

2

R5122

12

R5112

12

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

R5128

1

2

R5127

1

2

51 OF 109

3.13.0

051-8870

43 OF 75

6

43

70

6

43

6 7

6

43

6

43

70

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

actual CDR(s) in plug.

For Compliance Testing

T29 I2C Connections

SMC "0" SMBus Connections

(* = Multiple options)

(Write: 0x72 Read: 0x73)

Microcontroller abstracts

ISL6258 - U7000

(Write: 0x12 Read: 0x13)

EMC1414-A: U5570

U6800

Mikey

U9701

SMC "B" SMBus Connections

(WRITE: 0x58 READ: 0x59)

LED BACKLIGHT

Left I/O Board

(See Table)

J4700

(MASTER)

(Write: 0x30 Read: 0x31)

SMC "Management" SMBus Connections

PCH "SMLink 0" Connections

CPU Temp

SMC "Battery A" SMBus Connections

PCH "SMLink 1" Connections

U4900

DP Re-driver

(Write: 0x94 Read: 0x95)

U9310

(MASTER)

VRef DACs

SMC

U1800

Battery

J6955

U4900

(MASTER)

Battery

U1800

SMC

(See Table)

(MASTER)

U4900

SMC

(MASTER)

U1800

Cougar-Point

access PCH & CPU via PECI.

U4900

(MASTER)

Margin Control

(Write: 0x98 Read: 0x99)

U3600

T29 IC

T29 Plug uC

SMC

(MASTER)

XDP Connectors

SMLink 1 is slave port to

(Write: 0x88 Read: 0x89)

Cougar-Point

Battery Charger

SMC

PCH SMBus "0" Connections

(MASTER)

Internal DP

J2600 & J2650

U3301

(Write: 0xA0 Read: 0xA1)

U9330

(Write: 0x98 Read: 0x99)

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

U3300

(Write: 0x90 Read: 0x91)

J5700

Trackpad

EMC1704: U5400

(Write: 0x98 Read: 0x99)

T29 & Inlet Temp

Internal DP

(See Table)

J9000

Cougar-Point

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "A" SMBus Connections

ALS - (write: 0x72 Read: 0x73)

Left I/O Board

Finstack Temp - (Write: 0x92 Read: 0x93)

K21 K78

Samsung LGD Samsung LGD AUO

Battery Manager - (Write: 0x16 Read: 0x17)

Battery LED Driver - (Write: 0x36 Read: 0x37)

Battery Temp - (Write: 0x90 Read: 0x91)

201

4.7K

5% 1/20W MFMF

4.7K

201

5%

1/20W

2.0K

1/20W

MF

201

5%

2.0K

MF

5% 1/20W

201

1/20W

1K

201

5%

MF

201

5% 1/20W MF

1K

201

MF

5% 1/20W

4.7K

201

4.7K

MF

1/20W

5%

201

MF

1/20W

5%

8.2K

201

MF

8.2K

1/20W

5%

201

1/20W MF

5%

8.2K

NO STUFF

201

MF

1/20W

5%

8.2K

NO STUFF

201

0

MF

1/20W

5%

201

0

5%

1/20W

MF

201

MF

5%

1K

1/20W1/20W

201

5%

MF

1K

5%

201

1/20W

MF

4.7K 4.7K

5% 1/20W MF 201

201

MF

1/20W

5%

0

SDRVI2C:MCU

MF

201

0

1/20W

5%

SDRVI2C:MCU

201

1/20W

5%

0

SDRVI2C:SB

MF

201

1/20W

0

SDRVI2C:SB

5% MF

402

MF-LF

1/16W

5%

2.0K

402

MF-LF

1/16W

5%

2.0K

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

SMBus Connections

=PP3V3_S3_SMBUS_SMC_MGMT

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

=I2C_T29_INLET_THMSNS_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

MAKE_BASE=TRUE

SMBUS_PCH_CLK

=I2C_BKL_1_SCL

MAKE_BASE=TRUE

SMBUS_PCH_DATA

I2C_DPSDRVA_SDA

MAKE_BASE=TRUE

=I2C_TCON_SCL

=I2C_TCON_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

I2C_DPSDRVA_SCL

I2C_T29_SCL

MAKE_BASE=TRUE

I2C_T29_SDA

MAKE_BASE=TRUE

=PP3V3_S0_T29I2C

=I2C_TPAD_SDA

=I2C_T29_INLET_THMSNS_SDA

=I2C_TPAD_SCL

=I2C_CPUTHMSNS_SCL

=I2C_T29AMCU_SDA

=I2C_T29AMCU_SCL

=I2C_PCA9557D_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK

=SMBUS_XDP_SDA

=I2C_VREFDACS_SDA

=SMBUS_XDP_SCL

SMB_A_S3_CLK

SMB_BSA_DATA

=SMBUS_CHGR_SDA

=I2C_VREFDACS_SCL

=I2C_PCA9557D_SCL

SMB_MGMT_CLK

SMB_0_S0_CLK

SML_PCH_0_CLK

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_PCH

=PP3V42_G3H_SMBUS_SMC_BSA

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMB_BSA_CLK

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SML_PCH_1_DATA

SML_PCH_1_CLK

MAKE_BASE=TRUE

=PP3V3_S0_SMBUS_PCH

SML_PCH_0_DATA

MAKE_BASE=TRUE

=I2C_DPSDRVA_SDA

=I2C_DPSDRVA_SCL

SMB_MGMT_DATA

=I2C_BKL_1_SDA

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_PCH

SMB_0_S0_DATA

=I2C_CPUTHMSNS_SDA

=SMBUS_CHGR_SCL

=I2C_LIO_SCL

=I2C_LIO_SDA

=I2C_MIKEY_SDA

=I2C_MIKEY_SCL

SMB_A_S3_DATA

=PP3V3_S0_SMBUS_SMC_0_S0

R5261

1

2

R5260

1

2

R5280

1

2

R5281

1

2

R5270

1

2

R5271

1

2

R5251

1

2

R5250

1

2

R5210

1

2

R5211

1

2

R5221

1

2

R5220

1

2

R5223

12

R5222

12

R5201

1

2

R5200

1

2

R5230

1

2

R5231

1

2

R5235

1

2

R5234

1

2

R5236

12

R5237

12

R5291

1

2

R5290

1

2

52 OF 109

3.13.0

051-8870

44 OF 75

7

73

46

7

70 16 66

70 16

63

73

72 34

7

49

6

46

49

6

47

64

31

41

23

31

23

41

41 53

31

41

70 16

44

7

52

6

52

6

73

41

73

70 16

44

7

70 16

64

41

66

7

44

7

41

47

53

40

6

40

6

40

6

40

6

41

7

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

V+

REFIN+

IN-

OUT

GND

OUT

IN

V+

V-

THRM

V+

V-

THRM

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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R

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PAGE TITLE

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D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Sense R is R7510

Gain:110.181x

Max VOut: 2.73V at 39.934A

Sense R is R7550

divider when in S0.

Enables PBUS VSense

RTHEVENIN = 4573 Ohms

Max VOut: 3.3V at 19.77V Input

Gain: 200x

(200V/V)

CPU VCore Load Side Current Sense / Filter

Max VOut: 2.18V at 27.2A

EDP: 18A TDP: 15.3A

Sense R is R7640, 2mOhm

EDP: 8.5A TDP :7.225A

Scale: 2.5A / V Max VOut: 3.3V at 8.25A

Enables DC-In VSense divider when AC present.

CPU Vcore Voltage Sense / Filter

GFX/IG Vcore Voltage Sense / Filter

RTHEVENIN = 4573 Ohms

Scale: 8.24A / V

Gain:161.765x

CPU 1.05V VCCIO Current Sense / Filter

Sense R is 0.75mOhm

GFX/IG VCore Load Side Current Sense / Filter

Scale: 12.1A / V

Sense R is 0.75mOhm

EDP: 33A TDP :28.05A

DC-In Voltage Sense Enable & Filter

Max VOut: 3.3V at 19.77V Input

PBUS Voltage Sense Enable & Filter

PLACE_NEAR=U4900.L8:5MM

VCCIOISNS_ENG

NOSTUFF

PLACE_NEAR=U4900.N12:5MM

42

SIGNAL_MODEL=EMPTY

=PBUSVSENS_EN

=PPDCIN_S5_VSENSE

PDCINVSENS_EN_L_DIV

DCINVSENS_EN_L

DCIN_S5_VSENSE

=PPCPUVCORE_S0_VSENSE

CPUVSENSE_IN

=PPGFXVCORE_S0_VSENSE

GFXVSENSE_IN

=CHGR_ACOK

=PP3V3_S0_IMVPISNS

CPUIMVP_ISNS1_P

CPUIMVP_ISUM_R_P

CPUIMVP_ISUM_R_N

=PP3V3_S0_CPUVCCIOISNS

CPUVCCIO_IOUT

PBUSVSENS_EN_L_DIV

CPUIMVP_ISUMG_IOUT

CPUIMVP_ISNS1G_N

CPUVCCIOS0_CS_N

=PPBUS_S0_VSENSE

PBUSVSENS_EN_L

CPUIMVP_ISNS1G_P

CPUVCCIOS0_CS_P

CPUIMVP_ISUMG_R_N

PBUS_S0_VSENSE

SMC_PBUS_VSENSE

GND_SMC_AVSS

SMC_DCIN_VSENSE

GND_SMC_AVSS

SMC_CPU_VSENSE

GND_SMC_AVSS

SMC_GFX_VSENSE

GND_SMC_AVSS

CPUIMVP_ISUM_IOUT

CPUIMVP_ISNS1_N

SMC_CPU_ISENSE

GND_SMC_AVSS

SMC_GFX_ISENSE

GND_SMC_AVSS

SMC_CPUVCCIO_ISENSE

GND_SMC_AVSS

CPUIMVP_ISUMG_R_P

Voltage & Load Side Current Sensing

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

SM

PLACE_NEAR=R7510.2:5 MM

1%

4.53K

1/20W

MF

201

PLACE_NEAR=U4900.N10:5MM

42

SM

PLACE_NEAR=R7550.2:5 MM

0201

PLACE_NEAR=U4900.L12:5MM

VCCIOISNS_ENG

0.22UF

20%

6.3V X5R

0201

0.22UF

20%

6.3V X5R

PLACE_NEAR=U4900.M13:5MM

0201

0.22UF

20%

6.3V X5R

PLACE_NEAR=U4900.M11:5MM

0201

X5R

6.3V

20%

0.22UF

0201

X5R

6.3V

20%

0.22UF

PLACE_NEAR=U4900.N10:5MM

0201

0.22UF

20%

6.3V X5R

PLACE_NEAR=U4900.N9:5MM

0201

X5R

6.3V

20%

0.22UF

PLACE_NEAR=U4900.L8:5MM

42 53

1%

MF

100K

201

1/20W

NTUD3169CZ

SOT-963

100K

1%

MF

1/20W

201

1%

MF

1/20W

5.49K

201

PLACE_NEAR=U4900.N9:5MM

1%

1/20W

MF

201

27.4K

470PF

SIGNAL_MODEL=EMPTY

16V

X5R-X7R

10%

201

NOSTUFF

10%

470PF

X5R-X7R

201

16V

SIGNAL_MODEL=EMPTY

X5R-X7R

16V

470PF

NOSTUFF

10%

201

SIGNAL_MODEL=EMPTY

0.1%

487K

0402

1/16W

MF

470PF

201

NOSTUFF

10% 16V

X5R-X7R

OPA2333

CRITICAL

DFN

CRITICAL

DFN

OPA2333

58 74

57 58 74

1/16W

715K

0.1%

402

MF

0.1%

715K

402

1/16W MF

4.42K

MF

0402

0.1%

1/16W

4.42K

0.1%

0402

MF

PLACE_NEAR=R7510.3:5MM

4.42K

1/16W

MF

0.1%

0402

58 74

0402

1/16W

0.1% MF

487K

PLACE_NEAR=U4900.M13:5MM

4.53K

MF

1/20W

1%

201

PLACE_NEAR=R7510.4:5MM

0402

4.42K

0.1% MF

1/16W

0.1UF

PLACE_NEAR=U5340.8:3MM

201

6.3V X5R

10%

42

201

1/20W

MF

PLACE_NEAR=U4900.M11:5MM

4.53K

1%

VCCIOISNS_ENG

CRITICAL

SC70

INA210

PLACE_NEAR=R7640.4:5MM

59 74

VCCIOISNS_ENG

201

10%

0.1UF

X5R

6.3V

PLACE_NEAR=U4900.L12:5MM

201

MF

1/20W

4.53K

1%

42

NTUD3169CZ

SOT-963

5.49K

1/20W

201

MF

1%

PLACE_NEAR=U4900.L8:5MM

1%

201

1/20W

MF

27.4K

42

201

MF

1/20W

1%

100K

201

MF

1/20W

1%

62

PLACE_NEAR=U4900.N12:5MM

4.53K

MF

1/20W

1%

201

42

R5330

12

XW5330

12

R5320

12

XW5320

12

R5302

1

2

R5301

1

2

R5303

1

2

R5304

1

2

Q5300

6

3

2

5

1

4

R5361

12

C5360

1

2

U5360

2

5

4

6

1

3

R5341

12

C5340

1

2

R5343

12

R5351

12

R5344

1

2

R5342

12

R5352

12

R5353

12

R5354

1

2

R5355

12

U5340

3

2

1

9

4

8

U5340

5

6

7

9

4

8

C5344

1

2

R5345

12

C5345

12

C5354

1

2

C5355

12

R5313

1

2

R5314

1

2

R5312

1

2

Q5310

6

3

2

5

1

4

R5311

1

2

C5304

1

2

C5314

1

2

C5320

1

2

C5330

1

2

C5341

1

2

C5351

1

2

C5361

1

2

53 OF 109

3.13.0

051-8870

45 OF 75

7

74

7

74

41 42 45 46

74

V+

REFIN+

IN-

OUT

GND

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

OUT

IN

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

V+

REFIN+

IN-

OUT

GND

IN

DUR_SEL

DP1

VDD

THERM*

ALERT*

SMDATA

SMCLK

ADDR_SEL

GPIO

THRM_PAD

GND

TH_SEL

SENSE-

SENSE+

DN2/DP3

DP2/DN3

DN1

OUT

IN

BI

OUT

IN

OUT

IN-

IN+ REF

V+

GND

OUT

IN-

IN+ REF

V+

GND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

DDR3 1V5R1V35 Current Sense / Filter

Sense R is R7350, 2mOhm

Sense R is R4052, 20mOhm

Max Vdiff: 15 mV

EDP Current: 2.36A

(For R and C)

MAX VOUT: 3.1V at 16.5A

GAIN: 100X

SCALE: 5A/ V

PLACEMENT_NOTEs:

COMPUTING High Side Current Sense / Filter & T29/Inlet Temp Sensor

Sense R is R5400, 2mOhm

For engineering, stuff BMON_ENG

INA (Engineering) Solution

Max Vdiff: 7.0 mV

LCD Backlight Driver Input Current Sense / Filter

(500V/V)

EDP: 15.5A TDP :13.175A

EDP Current: 15.5 A

Sense R is R5400, 2mOhm

GAIN: 500X

(200V/V)

Max Vdiff: 31 mV

Gain: 50x

Scale: 2A / V

Max VOut: 3.3V at 6.6A

EDP Current: 10A

(100V/V)

EDP Current: 310A

EDP Current: 3.5A

Max VOut: 1.4V at 8.25A

Charger BMON (Production) Solution

Max VOut: 3.3V at 9.167A

Scale: 2.78A / V

ISL6259 Gain: 36x

For production, stuff BMON_PROD

(50V/V)

Sense R is R7050, 10mOhm

battery to PBUS (battery discharge)

across R7050

PLACEMENT_NOTEs:

GAIN: 500X

(For R and C)

(500V/V)

PLACEMENT_NOTEs:

Battery side

Scale: 2.5A / V

Charger/Load side

From charger

PLACEMENT_NOTEs:

(For R and C)

HDD Current Sense / Filter

(For R and C)

COMPUTING High Side Current Sense / Filter

Read Address: 0x99

ISL6259 Gain: 20x

DC-In AMON

Sense R is R7020, 20mOhm

EDP Current: 12 A Max Vdiff: 24 mV

(100V/V)

GAIN: 100X

SCALE: 5A / V

PLACEMENT_NOTEs:

AirPort Current Sense / Filter

DC-IN (AMON) Current Sense Filter

MAX VOUT: 2.4V AT 16.5A

Gain: 200x

Scale: 0.25A / V

EDP Current: 0.750 A

MAX VOUT: 3V AT 0.825A

SCALE: 0.667A / V

Sense R is R4599, 3mOhm

MAX VOUT: 3.3V AT 2.2A

SCALE: 0.2A / V

Sense R is R0910, 10mOhm

EDP Current: 0.67 A Max Vdiff: 6.7 mV

MAX VOUT: 3.3V AT 0.66A

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

NOTE: Monitoring current from

Write Address: 0x98

BMON:ENG

0.1UF

X5R 201

10%

6.3V

PLACE_NEAR=R7050.4:5MM

SC70

INA213

53

PLACE_NEAR=U5421.3:5MM

201

1/20W

MF

0

5%

BMON:PROD

BMON:ENG

0.1UF

6.3V X5R

10%

42

BMON:ENG

SC70

NC7SB3157P6XG

42

74 53

42

MF

1%

PLACE_NEAR=U4900.K10:5MM

201

4.53K

1/20W

53

201

5% 1/20W MF

100K

BMON:ENG

CRITICAL

1%

0.002

0612

MF

1W

0.1UF

0201

10% 16V

X5R-CERM

42

1/20W

Place close to SMC

1%

4.53K

201

MF

0.1UF

201

6.3V X5R

10%

74 56

Place close to SMC

1%

1/20W

MF

201

4.53K

AIRPORTISNS_ENG

201

1/20W

Place close to SMC

1%

4.53K

MF

HDDISNS_ENG

X5R 201

10%

0.1UF

6.3V

AIRPORTISNS_ENG

INA210

SC70

AIRPORTISNS_ENG

X5R

10%

6.3V

201

0.1UF

HDDISNS_ENG

4.53K

1%

1/20W

MF

201

LCDBKLTISNS_ENG

201

6.3V X5R

10%

0.1UF

LCDBKLTISNS_ENG

SC70

INA211

LCDBKLTISNS_ENG

74 37

74 38

74

8

74

8

1/20W

201

1%

300K

MF

PLACE_NEAR=U4900.M9:5MM

201

10V X7R

3300PF

10%

PLACE_NEAR=U4900.M9:5MM

CRITICAL

QFN

7

1/20W

201

5%

MF

10K

NOSTUFF

5% 1/20W

201

MF

44

MF

5%

201

1/20W

82

5%

1/20W

MF

130

1%

1/20W

201

HS_TH_SEL

NOSTUFF

0

5%

201

NOSTUFF

1/20W

MF

0

201

42

201

1/20W

1%

4.53K

MF

6.3V X5R

0.1UF

74

46

74

46

SC70

INA214

0.22UF

20%

6.3V X5R 0201

0.22UF

20%

6.3V X5R 0201

X5R

6.3V

20%

0.22UF

PLACE_NEAR=U4900.K10:5MM

0201

0.22UF

20%

6.3V X5R

AIRPORTISNS_ENG

0201

0.22UF

20%

6.3V X5R

HDDISNS_ENG

0201

0.22UF

20%

6.3V X5R

LCDBKLTISNS_ENG

Place close to SMC

0201

High Side Current Sensing

SYNC_MASTER=K78_MLB

SYNC_DATE=01/16/2011

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

GND_SMC_AVSS

SMC_HDD_ISENSE

GND_SMC_AVSS

SMC_WLAN_ISENSE

GND_SMC_AVSS

SMC_1V5S3_ISENSE

SMC_DCIN_ISENSE

BMON_AMUX_OUT

=PPVIN_S5_HS_COMPUTING_ISNS_R

HISIDE_ISENSE_OC

GND_SMC_AVSS

SMC_HS_COMPUTING_ISENSE

HS_ADDR_SEL

=I2C_T29_INLET_THMSNS_SDA

T29THMSNS_ALERT_L

ISNS_P5VWLAN_IOUT

ISNS_AIRPORT_N

ISNS_1V5_S3_N

ISNS_1V5S3_IOUT

=PP3V3_S3_1V5S3ISNS

=PP3V3_S3_WLANISNS

ISNS_HS_COMPUTING_P

INLET_THMSNS_D1_P

=T29THMSNS_D2_P

=T29THMSNS_D2_N

=PP3V3_S3_BMON_ISNS

CHGR_BMON

CHGR_AMON

=PP3V3_S0_BKLTISNS

ISNS_LCDBKLT_IOUT

HS_DUR_SEL

GND_SMC_AVSS

CHGR_CSO_R_N

SMC_BMON_ISENSE

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

CHGR_CSO_R_P BMON_INA_OUT

SMC_BMON_MUX_SEL

=I2C_T29_INLET_THMSNS_SCL

ISNS_HS_COMPUTING_N

ISNS_AIRPORT_P

ISNS_P5VHDD_IOUT

ISNS_HDD_N

ISNS_HDD_P

=PP3V3_S0_HDDISNS

=PP3V3_S0_HS_COMPUTING_ISNS

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N

INLET_THMSNS_D1_N

=PPVIN_S5_HS_COMPUTING_ISNS

MF

HS_GPIO

201

BMON:ENG

CRITICAL

201

=PP3V3_S0_HS_COMPUTING_ISNS

EMC1704-2

10K

10%

ISNS_HS_COMPUTING_IOUT

INA214

Place close to SMC

0

5%

1/20W

MF

SC70

INA211

GND_SMC_AVSS

SC70

ISNS_1V5_S3_P

C5420

1

2

U5420

2

5

4

6

1

3

R5420

12

C5421

1

2

U5421

43

1

2

6

5

R5431

12

R5423

1

2

R5400

123

4

C5401

1

2

R5465

12

C5460

1

2

R5475

12

R5485

12

C5470

1

2

U5470

2

5

4

6

1

3

C5480

1

2

U5480

2

5

4

6

1

3

R5495

12

C5490

1

2

U5490

2

5

4

6

1

3

R5422

12

C5422

1

2

U5400

6

103

5

2

4

13

8

7

15

16

12

11

14

9

17

1

R5408

1

2

R5409

1

2

R5411

1

2

R5405

1

2

R5406

1

2

R5413

1

2

R5412

1

2

R5455

12

C5450

1

2

U5450

2

5

4

6

1

3

U5460

2

5

4

6

1

3

C5455

1

2

C5465

1

2

C5431

1

2

C5475

1

2

C5485

1

2

C5495

1

2

54 OF 109

3.13.0

051-8870

46 OF 75

46 45 42 41

46

7

42

46 45 42 41

7

74 46

47

74 47

7

46 45 42 41

74 46

7

47

46

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

CPU Proximity Sensor

Place Q5520 close to T29 on TOP side

Place Q5540 on MLB bottom side opposite U5400

Placement note:

Place Q5530 between near rear vent on bottom side

Placement note:

Write Address: 0x98

Place U5510 under CPU

Placement note:

Read Address: 0x99

Place Q5510 next to DDR/5V/3.3V supply on TOP side

Detect CPU Die Temperature

T29 Die

Detect T29 Die Temperature

Use GND pin B1 on U3600 for N leg

Detect DDR/5V/3.3V Proximity Temperature

Placement note:

T29,MLB Bottom & Inlet Proximity Sensors

Replacing caps with 100K PD on ISENSE SMC inputs

10K

MF

1/20W

5%

201

MF

1/20W

5%

10K

201

SOT732-3

BC846BMXXH

PLACE_NEAR=U5510.2:5mm PLACE_NEAR=U5510.3:5mm

SIGNAL_MODEL=EMPTY

10% 10V

X7R-CERM

2200PF

0201

74

9

74

9

DFN

CRITICAL

EMC1413

BC846BMXXH

SOT732-3

34

2200PF

0201

X7R-CERM

10% 10V

SIGNAL_MODEL=EMPTY

SM

PLACE_NEAR=U3600.B1:2mm

PLACE_SIDE=BOTTOM

MF-LF

1/16W

5%

10K

NOSTUFF

402

BC846BMXXH

SOT732-3

10%

X7R-CERM

0201

10V

2200PF

SIGNAL_MODEL=EMPTY

BC846BMXXH

SOT732-3

44

201

6.3V X5R

0.1UF

10%

47

5%

MF

1/20W

201

2200PF

X7R-CERM

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5510.4:5mm PLACE_NEAR=U5510.5:5mm

10% 10V

0201

SYNC_MASTER=K78_MLB

SYNC_DATE=01/16/2011

Thermal Sensors

=MLBBOT_THMSNS_D3_P

=MLBBOT_THMSNS_D3_N

=T29THMSNS_D2_N

=PP3V3_S0_CPUTHMSNS

TP_T29_THERM_DP

T29_THERMD_N

MAKE_BASE=TRUE

T29_THERMD_P

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

MIN_NECK_WIDTH=0.25 mm

INLET_THMSNS_D1_P

INLET_THMSNS_D1_N

=T29THMSNS_D2_N

=MLBBOT_THMSNS_D3_N

MAKE_BASE=TRUE

T29_MLBBOT_THMSNS_P

MAKE_BASE=TRUE

T29_MLBBOT_THMSNS_N

=T29THMSNS_D2_P

=MLBBOT_THMSNS_D3_P

CPU_THERMD_P

CPU_THERMD_N

C5485

HDDISNS_PROD

1

RES,MF,1/20W,100K OHM,5,0201,SMD

117S0008

C5495

LCDBKLTISNS_PROD

117S0008

RES,MF,1/20W,100K OHM,5,0201,SMD

1

AIRPORTISNS_PROD

RES,MF,1/20W,100K OHM,5,0201,SMD

C5475

1

117S0008

C5361

VCCIOISNS_PROD

1

RES,MF,1/20W,100K OHM,5,0201,SMD

C5510

1

2

R5510

12

C5512

1

2

R5512

1

2

R5511

1

2

Q5510

1

3

2

C5511

1

2

U5510

83

5

2

4

6

10

9

7

11

1

Q5520

1

3

2

C5522

1

2

XW5520

12

R5523

1

2

Q5530

1

3

2

C5523

1

2

Q5540

1

3

2

55 OF 109

3.13.0

051-8870

47 OF 75

47

47 74 47 46

7

74

46

74 47 46

47

74 47 46

47

D

GS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

NC

GND

MOTOR CONTROL

TACH

5V DC

NC

FAN CONNECTOR

518S0793

=PP5V_S0_FAN =PP3V3_S0_FAN

SMC_FAN_0_TACH

SMC_FAN_0_CTL

FAN_RT_TACH

FAN_RT_PWM

Fan

SYNC_DATE=01/10/2011

SYNC_MASTER=K78_MLB

CRITICAL

F-RT-SM

FF14A-4C-R11DL-B-3H

SSM3K15FV

SOD-VESM-HF

201

5%

1/20W

MF

100K

MF

5%

1/20W

47K

201

5%

1/20W

MF

201

47K

R5665

12

R5660

1

2

R5661

1

2

Q5660

3

1

2

J5600

5

6

1

2

3

4

56 OF 109

3.13.0

051-8870

48 OF 75

6 7

7

41

6

IN

BI

VIN

SW

OUT

FB

EN

NC

THRM

GND

PAD

NC

BI

OUT

IN

OUT

SYM_VER-1

BI

OUT

BI

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

BI

BIBI

BI

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

518S0793

tristate and read SMC_SYS_KBDLED:

SEL=0 Choose pull up/down

If HIGH, keyboard backlight not present

If LOW, keyboard backlight present

grounded when KB BL flex connected.

IPD Flex Connector

SEL=1 Choose USB

518S0794

R5853 always stuffed, R5854 only

on keyboard backlight flex

J5815 pin 1 is grounded

FIXME: CHECK SEL

Keyboard Backlight Connector

To detect Keyboard backlight, SMC will

Keyboard Backlight Driver & Detection

C5756 SYMBOL NOT READY FOR 0.22UF

0603

0.1uF

402

10V

CERM

20%

PLACE_NEAR=J5700.10:1.5MM

MF

10K

5%

1/20W

201

5%

10K

MF

201

1/20W

62 41 26 17

201

5% MF

0

1/20W

24

CRITICAL

F-RT-SM

FF14A-4C-R11DL-B-3H

NOSTUFF

X5R-CERM

10% 16V

0.1UF

0201

CRITICAL

MLF

KB_BL

0.1UF

PLACE_NEAR=J5700.13:1.5MM

10%

201

X5R

6.3V

49 44

6

CRITICAL

F-RT-SM

FF14A-14C-R11DL-B-3H

0.1UF

PLACE_NEAR=J5700.1:1.5MM

6.3V X5R

10%

201

49 44

6

49 42 41

6

49 42 41 40

6

49 42

6

25V

100PF

201

5%

CERM

PLACE_NEAR=J5700.8:1.5MM

25V

100PF

201

CERM

5%

PLACE_NEAR=J5700.9:1.5mm

100PF

201

PLACE_NEAR=J5700.11:1.5MM

CERM

5%

25V

100PF

25V

201

PLACE_NEAR=J5700.12:1.5MM

5%

CERM

25V

100PF

201

CERM

5%

PLACE_NEAR=J5700.14:1.5MM

DLP0NS

90-OHM

69 49

74 49

6

74 49

6

PLACE_NEAR=J5700.10:1.5MM

FERR-120-OHM-1.5A

0402-LF

0

MF5%

1/20W

201

42 41

6

KB_BL

MF-LF

1/16W

5%

4.7

402

1098AS-SM

KB_BL

CRITICAL

10UH-0.58A-0.35OHM

KB_BL

1UF

X5R

10%

402-1

10V

BYPASS=U5750.1:2:2 MM

41

PI3USB102ZLE

TQFN

CRITICAL

10% 16V

X5R-CERM

0.1UF

0201

74 49

6

74 49

6

69 49

SYNC_MASTER=K78_MLB

IPD / KBD Backlight

SYNC_DATE=01/10/2011

MIN_LINE_WIDTH=0.25 MM

KBDLED_ANODE

KBDLED_FB

=PP3V3_S5_TPAD

MIN_NECK_WIDTH=0.20mm MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

PP5V_TPAD_FILT

=PP5V_S5_TPAD

USB_TPAD_HUB_N

USB_TPAD_MUX_SEL =PP3V42_G3H_TPAD

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM

KBDLED_SW

USB_TPAD_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm

PP3V3_TPAD_CONN

USB_TPAD_N

PM_SLP_S4_L

USB_TPAD_P

=PP3V3_S5_TPAD

USB_TPAD_CONN_P USB_TPAD_CONN_N

=I2C_TPAD_SCL

=I2C_TPAD_SDA

SMC_TPAD_RST_L

SMC_LID

SMC_PME_S4_WAKE_L

USB_TPAD_P

USB_TPAD_CONN_N

USB_TPAD_CONN_P

=I2C_TPAD_SDA

=I2C_TPAD_SCL

SMC_TPAD_RST_L

SMC_ONOFF_L

SMC_LID

SMC_ONOFF_L

USB_TPAD_HUB_P

USB_TPAD_M_P USB_TPAD_M_N

=PP5V_S0_KBDLED

KB_BL

X5R

50V X5R

SMC_SYS_KBDLED

0603

50V

MIN_NECK_WIDTH=0.2 MM

MIC2292

KB_BL

C5755,C5756

10%

0.33UF

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

10%

0.33UF

OMIT_TABLE OMIT_TABLE

138S0704

2

CAP,CER,0.22UF,10%,50V,X5R,0603

C5710

1

2

C5700

1

2

C5720

1

2

J5700

15

16

1

10

11

12

13

14

2

3

4

5

6

7

8

9

C5732

1

2

C5733

1

2

C5734

1

2

C5735

1

2

C5736

1

2

L5710

12

34

L5720

12

R5730

12

R5755

1

2

L5750

12

C5750

1

2

U5700

6

7

3

4

5

8

10

9

2

1

C5701

1

2

R5703

1

2

R5702

1

2

R5704

12

J5715

5

6

1

2

3

4

C5704

1

2

U5750

3

6

4

8

1

7

9

2

C5755

1

2

C5756

1

2

3.13.0

051-8870

57 OF 109

49 OF 75

5

6 6

49

7

6

7

7 6

6

49

7

49 44

6

49 44

6

49 42

6

49 42 41

6

49 42 41 40

6

7

OUT

IN

IN IN

IN

RST*/HOLD*

CE* WP*

SCK

VSS

THRM_PAD

SI/SIO0

SO/SOI1

VDD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

ROM will ignore SPI cycles.

NOTE: If HOLD* is asserted

3.3K

5%

201

1/20W MF

70 43

70 43 70 43

43 19

6

SST25VF064C

OMIT_TABLE

64MBIT

WSON

CRITICAL

X5R

16V

10%

0.1UF

402

SPI ROM

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

SPI_MLB_MOSI

SPIROM_USE_MLB

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MISO

SPI_WP_L

=PP3V3_S5_ROM

R6101

1

2

U6100

1

7

6

5

2

984

3

C6100

1

2

61 OF 109

3.13.0

051-8870

50 OF 75

7

IN

IN-

IN+

OUT+ OUT-

GAINSHDN*

PVDD

NC

PGND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SIZE

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PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

6DBGAIN

APN:353S2888

80 HZ < FC < 132 HZ

SPEAKER AMPLIFIERS

SPEAKER LOWPASS

0.1UF

6.3V

10%

201

X5R

74 40

6

201

6.3V

10%

X5R

0.1UF

6.3V

20%

2012-LLP

POLY-TANT

47UF

5%

0

40

6

74 40

6

WLP

1/20W

5%

201

MF

100K

CRITICAL

X5R 201

10%

6.3V

1/20W

5%

201

MF

100K

MF

100K

5%

NOSTUFF

201

0

5%

MF

201

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

AUDI0: SPEAKER AMP

SPKRAMP_R_P_OUT

MIN_LINE_WIDTH=0.10 mm

MIN_NECK_WIDTH=0.10 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

PP5V_S3_U6210

R_AMP_GAIN

AUD_GPIO_3

SPKRAMP_INR_P

SPKRAMP_R_N_OUT

MIN_LINE_WIDTH=0.10 mm

MIN_NECK_WIDTH=0.10 MM

MAX98300_R_P

SPKRAMP_INR_N

=PP5V_S3_AUDIO_AMP

MAX98300_R_N

1/20W

R_SPKRAMP_SHDN

0.1UF

MAX98300

CRITICAL

1/20W

CRITICAL

1/20W

MF

201

C6210

12

C6207

1

2

C6201

1

2

R6210

12

U6210

C3

B3

A3

C1

B1

A2

A1

C2

R6212

1

2

C6211

12

R6211

1

2

R6213

1

2

R6214

12

62 OF 109

3.13.0

051-8870

51 OF 75

B2

74 52

6

74 52

6

74

7

74

IN

BI

D

GS

IN

NC

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

D

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PAGE TITLE

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A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Vout = 1.25V * (1 + Ra / Rb)

Battery Connector

MLB to LIO Power Cable Connector

K16-Specific

518S0540

518S0508

Debug LEDs

(For development only)

Right Speaker Connector

518S0519

60MA MAX OUTPUT

Vout = 3.425V

(Switcher limit)

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

<Ra>

<Rb>

44

6

44

6

RCLAMP2402B

SC-75

CRITICAL NO STUFF

10K

5%

1/20W

MF

201

0.1UF

402

X5R

25V

10%

402

X5R

16V

10%

1UF

CRITICAL

WTB-PWR-M82

M-RT-SM

603

0.01UF

CERM

50V

20%

M-RT-SM

WTB-PWR-M82

CRITICAL

S3_S0_LED

MF-LF

1/16W

5%

1K

402201

S3_S0_LED

1K

5%

1/20W

MF

GREEN-3.6MCD

2.0X1.25MM-SM

S3_S0_LED

SOD-VESM-HF

SSM3K15FV

2.0X1.25MM-SM

GREEN-3.6MCD

S3_S0_LED

62 41 25 23

CRITICAL

78171-0002

M-RT-SM

74 51

6

74 51

6

33UH-20%-0.39A-0.435OHM

CRITICAL

DP418C-SM

10V

402

CERM

0.22UF

10%10%

25V

X5R-CERM

603

2.2UF

BAT30CWFILM

SOT-323

CRITICAL

MF-LF

5%

1/8W

4.7

805

1/8W

5%

805

MF-LF

10

1%

348K

1/20W

MF

201

MF

201

200K

1%

1/20W

22PF

201

CERM

50V

5%

DFN

LT3470A

CRITICAL

603

CRITICAL

22UF

20%

6.3V X5R-CERM-1

402

0.01UF

10% 16V CERM

SYNC_MASTER=JACK_K90I

SYNC_DATE=08/20/2010

DC-In & Battery Connectors

=PP5V_S3_LIO_CONN

=PP18V5_DCIN_CONN

PPDCIN_G3H_OR_PBUS

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 mm

PPDCIN_G3H_OR_PBUS_R

PPBUS_G3H_R

MIN_LINE_WIDTH=0.4 mm

PPVIN_G3H_P3V42G3H

MIN_NECK_WIDTH=0.2 mm VOLTAGE=18.5V

P3V42G3H_BOOST

DIDT=TRUE

P3V42G3H_SW

MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT

DBGLED_S3

DBGLED_S0_D

DBGLED_S0

=PP3V3_S3_DBGLEDS

PPVBAT_G3H_CONN

SYS_DETECT_L

=SMBUS_BATT_SCL =SMBUS_BATT_SDA

PPBUS_G3H

ALL_SYS_PWRGD

P3V42G3H_FB

=PP3V42_G3H_REG

D6950

3

1

2

R6950

1

2

C6950

1

2

C6951

1

2

J6950

1

2

3

4

5

6

7

8

9

C6905

1

2

J6900

1

2

3

4

5

6

R6941

1

2

R6940

1

2

D6920

A

K

Q6940

3

1

2

D6910

A

K

J6903

3

4

1

2

L6995

12

C6994

1

2

C6990

1

2

D6905

1

2

3

R6920

12

R6905

12

R6995

1

2

R6996

1

2

C6995

1

2

U6990

2

3

1

5

8 4

9

6

C6999

1

2

C6906

1

2

69 OF 109

3.13.0

051-8870

52 OF 75

7

7 6

53

7

53

6

7 6

7

OUT

IN

BI

OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

IN

G

D

S

G

D

S

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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SIZE

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PAGE TITLE

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21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Max Current = 8A

FIXME: C7001 SAME AS C7000?

(PPVBAT_G3H_CHGR_R)

TO SYSTEM

Inrush Limiter

through body diodes:

Reverse-Current Protection

* PBUS through Q7085, Charger TOP FETs and

(CHGR_AGATE)

Q7055.

This node is powered

* DCIN through Q7080.

(AGND)

20V/V

36V/V

(OD)

(CHGR_DCIN)

(CHGR_SGATE)

30mA max load

(GND)

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

(CHGR_BGATE)

ACIN pin threshold is 3.2V, +/- 50mV

Input impedance of ~40K meets sparkitecture requirements

FROM ADAPTER

Float CELL for 1S

DIVIDER SETS ACIN THRESHOLD AT 12.18V

f = 400 kHz

TO/FROM BATTERY

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

2.2

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

=CHGR_ACOK

CHGR_LGATE

CHGR_PHASE

CHGR_VNEG

CHGR_VNEG_R

PPVBAT_G3H_CHGR_R

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

CHGR_VCOMP

CHGR_VCOMP_R

CHGR_CSO_N

CHGR_CSO_P

CHGR_DCIN

CHGR_AGATE

MIN_NECK_WIDTH=0.4 mm

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=18.5V

CHGR_CSI_R_N

CHGR_CSI_R_P

CHGR_CSI_N

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_AGATE_DIV

CHGR_BGATE

PPVBAT_G3H_CONN

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

CHGR_CSO_R_N

GATE_NODE=TRUE

DIDT=TRUE

CHGR_SGATE_DIV

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=5.1V

PP5V1_CHGR_VDDP

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

PPDCIN_G3H_OR_PBUS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=18.5V

DIDT=TRUE

=PPDCIN_S5_CHGR

CHGR_VFRQ

=PP3V42_G3H_CHGR

SMC_RESET_L

CHGR_CSO_R_P

CHGR_RST_L =SMBUS_CHGR_SCL

CHGR_CELL

=SMBUS_CHGR_SDA

CHGR_ICOMP

CHGR_BMON

CHGR_AMON

CHGR_DCIN_D_R

CHGR_SGATE

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

CHGR_ACIN

VOLTAGE=5.1V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.1 mm

PP5V1_CHGR_VDD

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm

CHGR_CSI_P

=PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

SYNC_DATE=12/03/2010

PBus Supply & Battery Charger

SYNC_MASTER=K78_MLB

201

MF

1/20W

1%

220

201

MF

1/20W

1%

255K

0.020

0.5% 1W

MF-LF

0612

CRITICAL

FDA1240F-SM

4.7UH-13.1A

5%

1/20W

MF

201

5%

1/20W

MF

201

10UF

805

X5R

25V

10%

402

X7R

25V

10%

0.01UF

402

X5R

10%10%

1UF

603-1

X5R

25V

20%

62UF

CASE-B2

11V

ELEC

62UF

20%

ELEC

CASE-B2

CRITICAL

11V

CRITICAL

POWERPAK

CRITICAL

SI5419DU

POWERPAK

6

41 42 43

201

5%

MF

1/20W

0

1UF

603-1

X5R

25V

10%

1UF

603-1

X5R

25V

10%

20

1/20W

MF

5%

201

ELEC

11V

20%

62UF

CASE-B2

CRITICAL

470K

1% 1/20W MF 201

100K

5%

1/20W

MF

201

10% 25V X5R 402

0.1UF

CRITICAL

SOT-323

BAT30CWFILM

100

1%

1/20W

MF

201

PWRPK-1212-8

SI7615DN

CRITICAL

62

201

MF

1/20W

5%

100K

NO STUFF

TQFN

ISL6259HRTZ

CRITICAL

16V X7R 201

10%

1000PF

PLACE_NEAR=Q7030.5:1.5mm

0.001UF

402

X7R

50V

10%

0612-3

MF

1W

0.5%

0.01

42 45

1000PF

201

X7R

16V

10%

402

X5R

10V

10%

0.47UF

201

X5R

10V

10%

44

46

603

X5R

25V

20%

62K

5% 1/20W MF 201

332K

1%

1/20W

MF

201

1206

8AMP-24V

CRITICAL

POLY-TANT

33UF-0.06OHM

CRITICAL

CASE-D3L

20% 25V

CRITICAL

CASE-D3L

POLY-TANT

25V

20%

33UF-0.06OHM

1/20W

201

5%

MF

10

201

5%

MF

10

1/20W

CERM

10V

10%

402

0.047UF

X7R

16V

10%

402

X5R

10%

0.1UF

402

X5R

25V

10%

0.1UF

1UF

402

X5R

10V

10%

PLACE_NEAR=U7000.22:1mm

SM

PLACE_NEAR=U7000.29:1mm

30.1K

1%

MF 201

1/20W

5%

1/16W

4.7

1UF

X5R

10V

10%

1UF

402

X5R

10V

10%

201

16V

10%

X5R-X7R

470PF

201

X5R-X7R

16V

10%

0.1UF

201

X5R

6.3V

10%

1% 1/20W MF 201

10.5K

MIN_NECK_WIDTH=0.25 MM

CRITICAL

PPVBAT_G3H_CHGR_REG

GND_CHGR_AGND

0.01UF

402-1

0

CHGR_UGATE

CHGR_BOOT

0.1UF

25V

0.22UF

MIN_NECK_WIDTH=0.2 mm

OMIT_TABLE

402

MF-LF

402

SI5419DU

25V

PLACE_NEAR=L7030.2:1.5mm

FDMS0355S

CRITICAL

POWER56

DIDT=TRUE

GATE_NODE=TRUE

FDMS0349

CRITICAL

POWER56

PLACE_NEAR=U7000.25:2mm

R7011

1

2

C7042

1

2

C7016

1

2

C7015

1

2

C7002

1

2

C7000

1

2

R7001

12

R7010

1

2

XW7000

12

C7001

1

2

C7021

1

2

C7022

1

2

C7020

1

2

C7025

1

2

R7022

12

R7021

12

C7030

1

2

C7031

1

2

F7040

12

R7086

1

2

R7081

1

2

C7005

1

2

C7011

1

2

C7050

1

2

C7026

1

2

R7050

21

43

C7037

1

2

C7045

1

2

U7000

3

14

1

9

16

15

25

6

27

28

17

18

2

5

21

22

23

11

10

26

13

29

24

7

19

20

4

12

8

R7002

1

2

Q7055

5

4

123

R7013

1

2

D7005

1

2

3

C7085

1

2

R7080

1

2

R7085

1

2

C7041

1

2

R7005

12

C7035

1

2

C7036

1

2

R7000

12

Q7080

1

4

5

5A

Q7085

1

4

5

5A

C7043

1

2

C7040

1

2

C7014

1

2

C7013

1

2

C7012

1

2

C7017

1

2

R7051

12

R7052

12

L7030

1

2

3

R7020

123

4

R7015

1

2

R7016

1

2

Q7030

5

4

123

Q7035

5

4

123

70 OF 109

3.13.0

051-8870

53 OF 75

73

74

73

6

52

46 74

52

7

46

73

7

74

OUT

IN

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

6A Max Output

f = 300 kHz

0 0 0.9V

OCP = R7141 x 8.5uA / R7140

OCP = 8.5A

VID1 VID0 Voltage

1 0 0.8V

(VCCSAS0_VO)

(VCCSAS0_OCSET)

62

PLACE_NEAR=U7100.3:1mm

SM

2.2

5%

402

1/16W MF-LF

CRITICAL

603

10V X5R

20%

10UF

MF-LF

5%

1/10W

0

603

10V

402

10%

CERM

0.22UF

25V

5%

402

NP0-C0G

1000PF

201

1K

1%

1/20W

MF

201

1/20W MF

1K

1%

PLACE_NEAR=Q7100.2:1.5mm

1000PF

25V

NP0-C0G

5%

402

CRITICAL

1W

0612

MF-1

1%

0.001

CRITICAL

1.0UH-7.7A

FDV0630H-SM

10% 16V

0805

CRITICAL

10UF

X5R-CERM

X7R-CERM

16V

402

0.1UF

10%

UTQFN

ISL95870AH

CRITICAL

113K

1%

MF

1/20W

201

140K

1%

MF

1/20W

201

MF

1/20W

1%

47.5K

201

12

CRITICAL

10% 16V

X5R-CERM

10UF

0805

0.022UF

402

16V

10%

CERM-X5R

PLACE_NEAR=C1763.2:3mm

SM

POWERPAK-6X3.7

CRITICAL

SIZ710DT

20% 2V TANT CASE-B2-SM

270UF

ELEC

CASE-B2

11V

20%

62UF

CRITICAL

201

47PF

5% 25V NP0-C0G

0

5%

MF

1/20W

201

603

10% 16V

2.2UF

X5R

System Agent Supply

SYNC_MASTER=K78_MLB

SYNC_DATE=01/16/2011

VCCSAS0_SET1

VCCSAS0_VO

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

VCCSAS0_AGND

VCCSAS0_DRVH

MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

VCCSAS0_LL

DIDT=TRUE

VCCSAS0_SREF

CPU_VCCSASENSE

MIN_LINE_WIDTH=0.6 mm

PP5V_S0_VCCSAS0_VCC

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

VCCSAS0_RTN

VCCSAS0_OCSET

VCCSAS0_SET0

CPU_VCCSA_VID<1>

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_DRVL

DIDT=TRUE

VCCSAS0_VBST

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VCCSAS0_BOOT_RC

DIDT=TRUE

PPVCCSA_S0_REG_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_FSEL

PVCCSA_PGOOD

VCCSAS0_CS_N

=PP5V_S0_VCCSA

VCCSAS0_CS_P

=PPVCCSA_S0_REG

=PVCCSA_EN

=PPVIN_S0_VCCSAS0

C7103

1

2

R7103

1

2

C7102

1

2

XW7100

12

R7101

1

2

C7101

1

2

R7130

1

2

C7130

1

2

C7140

12

R7141

1

2

R7142

1

2

C7122

1

2

R7140

12

34

L7100

12

C7120

1

2

C7121

1

2

U7100

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

R7147

1

2

R7148

1

2

R7149

1

2

C7119

1

2

XW7101

1

2

Q7100

1

6

45

237

8

C7141

1

2

C7123

1

2

C7105

1

2

71 OF 109

3.13.0

051-8870

54 OF 75

74

7

74

7

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

152S1424

Vout = 5.0V

7.2A MAX OUTPUT 6.5A MAX OUTPUT

Vout = 3.3V

353S2678

F=400KHZ

1UF

10%

X5R

16V

402

PCMC063T-SM

2.5UH-14A

CRITICAL

1UF

X5R

10% 16V

402

X5R

402

10% 25V

0.1UF

X5R

25V

402

0.1UF

10%

20%

POLY-TANT

150UF

6.3V

CRITICAL

CASE-B2-SM

X5R

10%

1UF

16V

402

CERM

6.3V

10%

402

1UF

0603

10V

20%

10UF

X5R

249K

1/20W

1%

MF

201

62

SM

10V

10%

402

CERM

0.22UF

1%

201

1/20W MF

23.2K

1%

10K

201

1/20W MF

1%

41.2K

MF 201

1/20W

10K

201

MF

1/20W

CRITICAL

ELEC

62UF

11V

CASE-B2

20%

PLACE_NEAR=U7201.28:1mm

SM

4.42K

201

1% 1/20W MF

1/20W

201

1%

1.54K

MF

SM

PLACE_NEAR=L7260.1:3mm

402

16V

0.1UF

10%

X5R

201

1/20W

MF

1.33K

1%

201

4.22K

1/20W

MF

SM SM

201

1%

1/20W

MF

7.5K

201

20K

MF

1%

NO STUFF

1/20W

SM

PLACE_NEAR=L7260.2:3mm

PLACE_NEAR=L7220.1:3mm

SM

150UF-0.018OHM-1.8A

TANT

20%

CRITICAL

6.3V

CASE-B2-SM

NO STUFF

20K

1%

201

MF

1/20W

220PF

201

10%

X7R-CERM

25V

201

1/20W

MF

7.5K

1%

201

4700PF

X7R

10V

10%

62 62

NO STUFF

5%0201MF1/20W

0

201

1/20W

MF

5%

X7R

10% 16V

201

1000PF

PLACE_NEAR=L7260.2:1.5mm

201

1000PF

10%

X7R

PLACE_NEAR=Q7260.2:1.5mm

16V

PLACE_NEAR=Q7220.5.2:1.5mm

201

10%

X7R

16V

1000PF

X7R 201

16V

10%

PLACE_NEAR=L7220.1.2:1.5mm

1000PF

QFN

CRITICAL

TPS51980

ELEC

CRITICAL

CASE-B2

11V

20%

62UF

0

5%

MF-LF

402

1/16W

PLACE_NEAR=U7201.4:2mm

0

5% 1/20W MF 201

PLACE_NEAR=U7201.21:2mm

0

MF

1/20W

5%

201

62

201

X7R

4700PF

10V

10%

0201

270PF

16V

X7R-CERM

10%

X5R 402

16V

0.1UF

0

5%

MF-LF 402

1/16W

HWSON-8

RJK03E0DNS

CRITICAL

RJK03E0DNS

62UF

20%

6.3V

CASE-B2S

ELEC

CRITICAL

CASE-B2-SM

6.3V

20%

POLY-TANT

CRITICAL

150UF

POWERPAK-6X3.7

CRITICAL

62UF

20%

11V

ELEC

CASE-B2

CRITICAL

62UF

11V

ELEC

CASE-B2

20%

10UF

20%

10V X5R 603

10UF

20%

10V X5R 603

5V / 3.3V Power Supply

SYNC_DATE=01/16/2011

SYNC_MASTER=K78_MLB

P3V3S5_COMP2

P5VS3_EN_R

P5VS3_PGOOD

P5VS3_CSP1

=PPVIN_S5_P5VP3V3

=PP5V_S5_LDO

P5VS3_CSP1_R

DIDT=TRUE

SWITCH_NODE=TRUE

P5VS3_LL MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

=PP5V_S3_REG

P5VP3V3_VREF2

DIDT=TRUE

P3V3S5_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

=P3V3S5_EN

=P5VS3_EN

P5VS3_VFB1-R

P5VP3V3_VREG3

P3V3S5_VFB2_R

=PP3V3_S5_REG

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P5VS3_VBST_R

MIN_LINE_WIDTH=0.6 mm

P5VS3_VBST

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

=P5V3V3_REG_EN

MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVL

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVH

GATE_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P5VS3_DRVL

MIN_NECK_WIDTH=0.2 mm

=PP5V_S3_REG

P5VS3_DRVH

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P5VS3_COMP1

P5VP3V3_VREF2

P5VS3_FUNC

P5VP3V3_VREG3

P3V3S5_VBST_R MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

P3V3S5_RF

P3V3S5_PGOOD

P3V3S5_EN_R

P3V3S5_COMP2_R

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

GND_P5VP3V3_SGND

MIN_NECK_WIDTH=0.2 mm

P5VP3V3_VREF2

P3V3S5_LL

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_CSP2

P3V3S5_VFB2

P3V3S5_CSP2_R

P3V3S5_CSN2

P5VS3_COMP1_R

P5VS3_VFB1

P5VS3_CSN1

1%

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

SIZ710DT

PLACE_NEAR=L7260.2:3mm

PLACE_NEAR=L7220.2:3mm

HWSON-8

PLACE_NEAR=L7220.1:3mm

PCMC063T-SM

1.5UH-20%-18A-15MOHM

CRITICAL

C7200

1

2

L7260

12

C7241

1

2

C7264

1

2

C7224

1

2

C7252

1

2

C7281

1

2

C7203

1

2

C7205

1

2

R7206

1

2

XW7261

1

2

C7201

1

2

R7260

1

2

R7261

1

2

R7220

1

2

R7221

1

2

C7240

1

2

XW7200

12

R7216

1

2

R7246

12

XW7260

1

2

C7218

12

R7247

12

R7256

1

2

XW7220

1

2

XW7221

1

2

R7236

1

2

R7237

1

2

XW7262

1

2

XW7222

1

2

C7292

1

2

R7239

1

2

C7239

1

2

R7238

1

2

C7238

1

2

R7248

12

R7249

1

2

C7272

1

2

C7283

1

2

C7270

1

2

C7271

1

2

U7201

10

15

8

17

7

18

1

24

30

27

12

4

21

28

11

14

5

20

3

6

19

32

25

33

2

31

26

9

16

23

13

22

29

C7282

1

2

R7245

1

2

R7251

1

2

R7252

1

2

C7236

1

2

C7237

1

2

C7288

12

R7264

2

1

Q7225

5

4

123

Q7220

5

4

123

C7254

1

2

C7253

1

2

Q7260

1

6

45

237

8

C7242

1

2

C7284

1

2

C7290

1

2

C7250

1

2

L7220

12

051-8870

3.13.0

72 OF 109

55 OF 75

7

55

7

55

7

55

7

55

IN

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

OUT

G

D

S

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

(DDRREG_DRVH)

(DDRREG_VDDQSNS)

10mA max load

(DDRREG_DRVL)

(DDRREG_LL)

VDDQ/VTTREF Enable

VTT Enable

C7360, C7361 close to memory

Vout = 1.5V

f = 400 kHz

14.1A max output

(Q7335 limit)

10UF

X5R

20%

603

10V

PLACE_NEAR=U7300.12:1mm

10%

603-1

X5R

25V

1UF

10%

0.1UF

X5R

25V

402

10% 50V X7R 402

0.001UF

20%

10UF

X5R 603

6.3V

0.001UF

50V

10%

402

X7R

SM

PLACE_NEAR=C7340.1:1mm

62

TPS51916

QFN

CRITICAL

8

SM

PLACE_NEAR=C7361.1:3mm

PLACE_NEAR=U7300.21:1mm

SM

10%

402

0.22UF

CERM

10V

PLACE_NEAR=C3101.1:1mm

603

CRITICAL

6.3V

20%

10UF

X5R

26

8

16V

PLACE_NEAR=U7300.6:1mm

10%

0.1UF

X5R 402

20%

6.3V X5R 603

10UF

CRITICAL

PLACE_NEAR=C3101.1:3mm

200K

1%

1/20W

MF

201

PLACE_NEAR=U7300.19:3mm

201

MF

1/20W

20K

PLACE_NEAR=U7300.8:5mm

1%

201

1/20W

1%

100K

MF

PLACE_NEAR=U7300.8:5mm PLACE_NEAR=U7300.8:1mm

10%

0.01UF

16V CERM 402

X5R

10UF

603

20% 10V

PLACE_NEAR=U7300.2:1mm

1/16W

5%

MF-LF

402

0

CRITICAL

0.88UH-20%-19A-2.3MOHM

MPCG1040LR88-SM

1206

MF-LF

0.002

1/4W

1%

CRITICAL

74 46

74

46

CRITICAL

IRFHM831PBF

PQFN3.3X3.3

IRFHM830DPBF

PQFN3.3X3.3

CRITICAL

62UF

CRITICAL

CASE-B2

ELEC

11V

20%

CRITICAL

CASE-B2

62UF

ELEC

11V

20%

CASE-B2

CRITICAL

62UF

20% 11V ELEC

PLACE_NEAR=U7300.18:3mm

68K

1% 1/20W MF 201

CRITICAL

330UF

20%

2.0V POLY-TANT B2-SM

CRITICAL

330UF

20%

2.0V

POLY-TANT

B2-SM

SYNC_DATE=01/10/2011

SYNC_MASTER=K78_MLB

1.5V DDR3 Supply

DDRREG_VDDQSNS

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm

DDRREG_LL

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

DIDT=TRUE

=PPVTT_S0_DDR_LDO

GND_DDRREG_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVL

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

=PPVIN_S3_DDRREG

ISNS_1V5_S3_P

=PPDDR_S3_REG

DDRREG_TRIP

GATE_NODE=TRUE

DDRREG_DRVH

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

PPDDR_S3_REG_R

=DDRREG_EN

=PPVTT_S3_DDR_BUF

DDRREG_VTTSNS

DDRREG_PGOOD

ISNS_1V5_S3_N

=PPVIN_S0_DDRREG_LDO

=PP5V_S3_DDRREG

=DDRVTT_EN

DDRREG_FB

DDRREG_1V8_VREF

DDRREG_MODE

C7300

1

2

C7332

1

2

C7325

12

C7333

1

2

C7345

1

2

C7346

1

2

XW7301

1

2

U7300

14

11

7

19

10

20

8

17

16

13

21

18

12 15

9

2

6

3

4

5

1

XW7360

12

XW7300

1

2

C7350

1

2

C7360

1

2

C7315

1

2

C7361

1

2

R7317

1

2

R7315

1

2

R7316

1

2

C7316

1

2

C7301

1

2

R7325

12

L7330

12

R7350

12 34

Q7330

5

4

123

Q7335

5

4

123

C7330

1

2

C7331

1

2

C7334

1

2

R7318

1

2

C7340

1

2

C7341

1

2

73 OF 109

3.13.0

051-8870

56 OF 75

7

31

7

31

IN

OUT

IN

OUT

IN

OUT

NC

OUT

NC

IMAXA

SR

IMAXB

ALERT*

THERMA THERMB

VDIO

POKB

CLK

EN

POKA

CSPA3 VRHOT*

DRVPWMA

GNDSB

GNDSA

THRM

CSPB1

DHB LXB

BSTB

DLA2

DLB

CSNB

FBB

LXA1

DHA1

BSTA1

TON

DLA1

CSPA1

CSPAAVE

FBA

CSNA

BSTA2

CSPA2

DHA2 LXA2

VCC

VDDA

VDDB

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

1/16W MF-LF

5%

10

402

X5R-CERM

2.2UF

402

10V

20%

PLACE_NEAR=U7400.24:2mm

402

10V X5R-CERM

20%

2.2UF

67 12

NO STUFF

100PF

CERM 201

25V

5%

MF

5%

201

5%

1

MF

1/20W

201

NO STUFF

0402

X5R-CERM

10% 10V

0.039UF

25

62

67 42 10

58

74 58

SM

PLACE_NEAR=U7400.15:2mm

402

2.2UF

20% 10V X5R-CERM

1%

200K

1/20W

NO STUFF

MF 201

25V

5%

100PF

CERM

NO STUFF

201

1/20W

MF

5%

10

201

10

1/20W

5%

12

67

1000PF

16V

10%

X7R 201

201

16V X7R

10%

201

X7R

10% 16V

1000PF

5%

MF

1/20W

10

201

67 12

201

10%

X7R

16V

5%

10

MF

1/20W

201

74 58 45

201

5%

NO STUFF

25V CERM

100PF

201

5% 25V CERM

NO STUFF

74 58

0.01UF

X5R 201

1%

54.9

201

MF

PLACE_NEAR=U7400.18:2mm

1/20W

PLACE_NEAR=U7400.16:2mm

1/20W

201

MF

1%

130

58

MF

1/20W

201

215K

1%

201

137K

1%

MF

1/20W

402

1/16W

1%

MF-LF

90.9K

5.76K

1% 1/20W MF 201

5.76K

1%

MF

1/20W

201

10%

0.0022UF

CERM

50V

402

10%

2200PF

10V X7R-CERM 0201

CRITICAL

0603

100KOHM-1%-100MW

CRITICAL

0603

470PF

402

50V

NP0-C0G

5%

10V X5R

10%

201

1/20W

201

1%

MF

215K

201

137K

1/20W MF

1/20W

201

10K

1%

MF

1%

1/20W

MF

201

6.34K

47PF

5%

201

NP0-C0G

25V

CRITICAL

QFN

MAX15092GTL

2.2

5%

1/16WMF-LF

402

CPU IMVP7 & AXG VCore Regulator

SYNC_DATE=01/10/2011

CPUIMVP_UGATE1

CPUIMVP_UGATE1_R

CPUIMVP_LGATE1 CPUIMVP_ISUM1_P

CPUIMVP_ISUM_N

CPUIMVP_FBA_R

=PPVIN_S0_CPUIMVP

CPUIMVP_ISUM_R

CPU_AXG_SENSE_P

CPUIMVP_ISNS1_P

CPU_VCCSENSE_P

=PPVCCIO_S0_CPUIMVP

=PP5V_S0_CPUIMVP

CPUIMVP_FBA

CPUIMVP_PHASE1

CPUIMVP_FBB

CPUIMVP_ISUMG_N

CPUIMVP_LGATE1G

CPUIMVP_BOOT1G CPUIMVP_UGATE1G

CPUIMVP_ISUMG_P

VOLTAGE=0V

CPU_VCCSENSE_R

CPU_PROCHOT_L

CPUIMVP_PGOOD

CPUIMVP_VR_ON

CPUIMVP_AXG_PGOOD

CPU_VIDSOUT

CPUIMVP_NTCG

CPUIMVP_SLEW

CPUIMVP_BOOT1

CPUIMVP_TON

CPU_VIDALERT_L

CPUIMVP_ISUM

CPU_AXG_SENSE_R

GND_CPUIMVP_SGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPU_VIDSCLK

CPUIMVP_NTC

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

P5V_S0_CPUIMVP_VDD

1000PF

NO STUFF

VOLTAGE=0V

CPUIMVP_IMAXA CPUIMVP_IMAXB

1%

NO STUFF

100PF

1000PF

CPU_AXG_SENSE_N

NO STUFF

10% 10V

0.01UF

MF

CPU_VCCSENSE_N

VOLTAGE=0V

201

67

12

100KOHM-1%-100MW

CPUIMVP_PHASE1G

1/20W

300

CPUIMVP_FBA

SYNC_MASTER=K78_MLB

MF

1/20W

1%

8.25K

CPUIMVP_FBB

CPUIMVP_FBB_R

201

R7401

12

C7401

1

2

C7402

1

2

C7414

1

2

R7406

12

R7410

12

C7408

12

XW7400

12

C7403

1

2

R7464

1

2

C7415

1

2

R7440

12

R7441

12

C7440

1

2

C7441

1

2

C7412

1

2

R7413

12

C7422

1

2

R7423

12

C7419

1

2

C7418

1

2

C7442

1

2

R7479

1

2

R7480

1

2

R7460

1

2

R7461

1

2

R7402

12

R7468

1

2

R7466

1

2

C7407

1

2

C7404

1

2

R7469

1

2

R7467

1

2

C7409

12

C7443

1

2

R7462

1

2

R7463

1

2

R7465

1

2

R7412

12

C7444

1

2

U7400

17

20

28

11

18

37

9

36

38

39

35

8

22

26

13

23

25

14

31

1

4

6

3

7

29 30

21

27

12

19 10

32

33 34

41

2

402415

16

5

R7403

12

R7422

12

74 OF 109

3.13.0

051-8870

57 OF 75

57

58

7

57

IN

VSW

PGND

TGR

TG

BG

VIN

IN

OUT

S

G

D

G

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

152S1323

AXG PHASE

152S1323

376S0906

THESE TWO CAPS ARE FOR EMC

376S0984

PHASE 1

376S0985

CPU=Sandy Bridge ULV, AXG=GT2

0.36UH-20%-30A-1.2MOHM

PIMB104T-SM

PPVCORE_S0_AXG_R

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5 MM

CRITICAL

0.36UH-20%-30A-1.2MOHM

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.25V

PPVCORE_S0_CPU_PH1

CRITICAL

=PPVCORE_S0_AXG_REG

0.001UF

X5R-CERM

62UF

0.00075

CPUIMVP_ISUMG_N

16V X5R

1UF

402

10%

50V X7R 402

10%

402

0.001UF

50V

10%

X7R

57

0

5%

MF-LF

1/16W

402

10V CERM

0.22UF

402

10%

X7R

50V

402

0.001UF

X7R

50V

10%

402

1UF

X5R

16V

402

10%

NOSTUFF

603

1/10W

2.2

5%

MF-LF

50V CERM

10%

402

NOSTUFF

0.001UF

10% 10V

0.22UF

57

201

1/20W

1%

10

MF

201

1% 1/20W MF

10

SON5X6

57

74 57

74 57 45

4.7

5%

MF-LF

402

1/16W

1%

0612

0.00075

1W

CRITICAL

MF

CRITICAL

0612

MF

1W

1%

201

46.4

1/20W

MF

1%

201

46.4

MF

1%

1/20W

0201

2200PF

X7R-CERM

10V

NO STUFF

10%

NO STUFF

1000PF

201

16V

10%

X7R

CASE-B2

CRITICAL

ELEC

11V

20%

62UF

ELEC CASE-B2

CRITICAL

11V

20%

62UF

20%

CRITICAL

CASE-B2

11V ELEC

62UF 62UF

20% 11V

CASE-B2

ELEC

CRITICAL

ELEC

11V

20%

62UF

CASE-B2

20% 11V ELEC

CRITICAL

CASE-B2

ELEC

11V

20%

CASE-B2

CRITICAL

ELEC

20%

62UF

CASE-B2

CRITICAL

SQ

IRF6811STRPBF

CRITICAL

CASE-B2

62UF

20% 11V ELEC

CASE-B2

62UF

20% 11V ELEC

CRITICAL

DIRECTFET-MX

CRITICAL

0603

X5R-CERM

25V

20%

10UF

CRITICAL

0603

25V

20%

10UF

CRITICAL

0603

X5R-CERM

25V

20%

10UF

CRITICAL

0603

X5R-CERM

25V

20%

10UF

CRITICAL

SYNC_DATE=12/07/2010

SYNC_MASTER=K78_MLB

CPU IMVP7 & AXG VCore Output

=PPVIN_S0_CPUAXG

=PPVIN_S0_CPUIMVP

CPUIMVP_BOOT1

MIN_LINE_WIDTH=0.7 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_ISNS1_N

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS1_P

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.7 MM

DIDT=TRUE

CPUIMVP_PHASE1

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_ISUM1_P

CPUIMVP_ISUM_N

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.7 MM MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1

CPUIMVP_UGATE1

MIN_LINE_WIDTH=0.7 MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_BOOT1_RC

CPUIMVP_ISUMG_P

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

CPUIMVP_LGATE1G

MIN_LINE_WIDTH=0.7 MM

CPUIMVP_ISNS1G_N

MIN_NECK_WIDTH=0.25 MM

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_VSWG

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.7 MM

CPUIMVP_BOOT1G_RC

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

CPUIMVP_AXG_SNUB

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.7 MM

SWITCH_NODE=TRUE

CPUIMVP_UGATE1G

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.7 MM

MIN_NECK_WIDTH=0.2 MM

IRF6894MTRPBF

CRITICAL

62UF

CSD58864Q5D

0.001UF

CPUIMVP_ISNS1G_P

CRITICAL

11V

CPUIMVP_UGATE1G_R

402

CERM

GATE_NODE=TRUE

CPUIMVP_PHASE1G

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1G

402

MF-LF

1/16W

5%

10

C7517

1

2

C7518

1

2

C7519

1

2

R7511

1

2

C7511

1

2

C7559

1

2

C7558

1

2

C7557

1

2

R7552

1

2

C7552

1

2

C7551

1

2

R7514

1

2

R7554

1

2

Q7550

5

9

3

4

1

6

7

8

R7555

12

R7510

12

34

R7550

12

34

R7553

1

2

R7513

1

2

C7571

1

2

C7574

1

2

C7513

1

2

C7514

1

2

C7540

1

2

C7541

1

2

C7561

1

2

C7560

1

2

C7553

1

2

C7554

1

2

Q7510

1

2

5

64

3

C7510

1

2

C7520

1

2

Q7520

1267

5

34

C7515

1

2

C7516

1

2

C7555

1

2

C7556

1

2

R7551

1

2

L7510

12

L7550

12

75 OF 109

3.13.0

051-8870

58 OF 75

7

57

7

74 45

7

74 45 74 45

7

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

VSW

PGND

TGR

TG

BG

VIN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

<Rb>

<Ra>

OCP = 25.6A

(CPUVCCIOS0_VO)

(CPUVCCIOS0_OCSET)

OCP = R7641 x 8.5uA / R7640

Vout = 0.5V * (1 + Ra / Rb)

CPU VCCIO (1.05V S0) Regulator

21A Max Output

Vout = 1.05V

f = 300 kHz

1/20W MF

1%

3.01K

201

62

10%

603

X5R

16V

2.2UF

1/20W MF

5%

0

201

PLACE_NEAR=U7600.1:1mm

SM

CRITICAL

UTQFN

ISL95870

CRITICAL

10UF

603

10V X5R

20%

402

16V

10%

1UF

X5R

3.01K

1% 1/20W MF 201

1%

3.01K

MF

1/20W

201

5%

402

NP0-C0G

25V

1000PF

PLACE_NEAR=L7630.2:1.5mm

1000PF

5%

NP0-C0G

402

25V

1000PF

5%

402

PLACE_NEAR=Q7630.1:1.5mm

NP0-C0G

47PF

5%

25V

NP0-C0G

201

0

5%

MF-LF

603

1/10W

1/16W

MF-LF

402

5%

0

SON5X6

CSD58864Q5D

270UF

20% 2V TANT

CRITICAL

CASE-B2-SM

47PF

5% 25V NP0-C0G 201

CRITICAL

CASE-B2-SM

TANT

2V

20%

270UF

20% 11V

CASE-B2

ELEC

CRITICAL

62UF

11V

20%

62UF

CASE-B2

CRITICAL

ELEC

11V

20%

CASE-B2

ELEC

62UF

CRITICAL

201

2.2

5%

1/20W

MF

0.68UH-22A-2.7MOHM

CRITICAL

PIMB104T-SM

0612

MF

1W

1%

0.001

CRITICAL

402

0.047UF

16V

10%

X7R

2.74K

MF

1/20W

201

1%

201

1/20W

MF

2.74K

1%

201

1/20W

MF

3.01K

1%

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

CPU VCCIO (1.05V) Power Supply

=PP5V_S0_CPUVCCIOS0

CPUVCCIOS0_VO

CPUVCCIOS0_OCSET

CPUVCCIOS0_RTN

CPUVCCIOS0_FB

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

CPUVCCIOS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm

CPUVCCIOS0_SREF

CPUVCCIOS0_AGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_PGOOD

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

CPUVCCIOS0_FSEL

=CPUVCCIOS0_EN

CPUVCCIOS0_R

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_DRVH

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_LL

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

CPUVCCIOS0_VBST

PP5V_S0_CPUVCCIOS0_VCC

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PPCPUVCCIO_S0_REG

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_DRVL

=PPVIN_S0_CPUVCCIOS0

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPCPUVCCIO_S0_REG_R

=PPCPUVCCIO_S0_REG

CPUVCCIOS0_CS_N

CPUVCCIOS0_CS_P

C7604

1

2

C7605

1

2

C7603

1

2

R7645

1

2

R7605

1

2

R7604

1

2

R7644

1

2

C7602

1

2

R7603

1

2

XW7600

12

U7600

12

3

6

5

1

15

7

16

9

10

14

2

4

11

13

8

C7601

1

2

C7630

1

2

R7642

1

2

R7641

1

2

C7640

12

C7623

1

2

C7622

1

2

R7630

1

2

R7631

12

Q7630

5

9

3

4

1

6 7 8

C7648

1

2

C7649

1

2

C7619

1

2

C7621

1

2

C7620

1

2

R7601

1

2

L7630

12

R7640

12 34

76 OF 109

3.13.0

051-8870

59 OF 75

7

67 12

7

74 45

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC NC NC

LX

VDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

IN

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

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SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.

1.05V SUS LDO

Pull-ups (3) must be 51 ohms to support XDP (not required in production). 70mA is required to support pull-ups. Alternative is strong voltage

Max Current = 0.020A

Vout = 1.05V

Freq = 1 MHz

1.5V S0 LDO

Max Current = 0.02A

Max Current = 0.35A

Vout = 1.05V

<Ra>

152S1302

1.8V S0 Regulator

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

1.05V S0 LDO

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.794V

Max Current = 1.8A

Vout = 1.5V

1UF

402

CERM

6.3V

10%

XDP_PCH

SON

CRITICAL

TPS720105

XDP_PCH

X5R 402

2.2UF

6.3V

10%

2.2UF

10%

6.3V

402

X5R

SON

TPS720105

CRITICAL

PLACE_NEAR=U7780.6:1mm

10%

1UF

402

CERM

6.3V

PLACE_NEAR=U7780.4:1mm

10%

6.3V CERM

402

1UF

22UF

CRITICAL

20%

6.3V X5R-CERM-1 603

22UF

6.3V

20%

CRITICAL

X5R-CERM-1

603

5%

47PF

25V NP0-C0G 201

201

1/20W

MF

113K

1%

CRITICAL

1.0UH-20%-4.5A-24MOHM

PIMB042T-SM

22UF

6.3V

CRITICAL

20%

X5R-CERM-1

603

QFN

ISL8014A

CRITICAL

201

10%

1000PF

X7R

16V

62

201

1/20W

MF

90.9K

1%

2.2UF

10%

6.3V X5R 402

SON

TPS72015

CRITICAL

10%

1UF

CERM

6.3V

402

PLACE_NEAR=U7770.6:1mm

10%

6.3V CERM

1UF

402

PLACE_NEAR=U7770.4:1mm

7

62

SYNC_MASTER=K78_MLB

SYNC_DATE=01/16/2011

Misc Power Supplies

=PP3V3_S0_P1V8S0

P1V8S0_PGOOD

=PP3V3_SUS_P1V05SUSLDO

=PP1V8_S0_REG

=P1V8S0_EN

P1V8S0_SW

DIDT=TRUE

SWITCH_NODE=TRUE

=1V05_S0_LDO_EN

=PP3V3_S0_P1V05S0LDO

=PP1V8_S0_P1V05S0LDO

=PP1V05_S0_LDO

=PP3V3_S0_P1V5S0

=PP1V8_S0_P1V5S0

=P1V5S0_EN

=PP1V5_S0_REG

P1V8S0_FB

=PP1V05_SUS_LDO

C7740

1

2

U7740

4

3

5

6

1

7

C7741

1

2

C7781

1

2

U7780

4

3

5

6

1

7

C7780

1

2

C7782

1

2

C7721

1

2

C7722

1

2

C7723

1

2

R7720

1

2

L7720

12

C7720

1

2

U7720

5

14

15

6

16

13

7

11

12

9

10

4

17

3

8

1

2

C7724

1

2

R7721

1

2

C7772

1

2

U7770

4

3

5

6

1

7

C7771

1

2

C7770

1

2

77 OF 109

3.13.0

051-8870

60 OF 75

2

7

62

7

IN

D

SG

D

SG

IN

S

G

D

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

D

SG

D

SG

D

SG

D

S

G

D

S

G

D

S

G

D

S

G

S

D

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

APN 376S0928

3.3V S3 FET

MOSFET

CHANNEL

29 mOhm @4.5V

P-TYPE 12V/8V

100? mA (EDP)

LOADING

26 mOhm @1.8V

SiA427

26 mOhm @1.8V

SiA427

MOSFET CHANNEL

RDS(ON)

LOADING

CHANNEL

RDS(ON)

100? mA (EDP)

P-TYPE 8V/5V

31 mOhm @1.8V

SiA427

SiA427MOSFET

RDS(ON)

1.608 A (EDP)

3.3V S0 FET

RDS(ON)

P-TYPE 8V/5V

MOSFET

CHANNEL

1.678 A (EDP)

RDS(ON)

LOADING

CHANNEL

LOADING

5.0V S0 FET

MOSFET TPCP8102

P-TYPE

18 MOHM @4.5V

3.3V S0 FET

MOSFET

5V SUS FET

3.3V SUS FET

5V_SUS FET

5.0V S0 FET

P-TYPE 8V/5V

3.3V S3 FET

5 A (EDP)

CHANNEL

RDS(ON)

LOADING

1.5V S3/S0 FET

N-TYPE

9.4 mOhm @4.5V

PQFN2X2

3.2 A (EDP)

3.3V_SUS FET

P3V3S0_SS

=PP3V3_SUS_FET

=PP3V3_S5_P3V3SUSFET

P3V3S3_SS

=PP3V3_S3_FET

P1V5S3RS0_RAMP_DONE

P3V3S3_EN_L

P1V5S0FET_GATE

=PP5V_S5_P1V5DDRFET

P1V5CPU_EN

P5V0S0_EN_L

P5VSUS_EN_L

P3V3SUS_EN_L

=PP3V3_S0_P3V3S0FET

=P5V_3V3_SUS_EN

=P3V3S0_EN

=P3V3S3_EN

=P5VS0_EN

=P5V_3V3_SUS_EN

=PP3V3_S0_FET

P5V0S0_SS

P3V3S0_EN_L

=PP5V_S0_FET

P3V3SUS_SS

=PP5V_SUS_FET

=PP5V_S3_P5VS0FET

=PP5V_S5_P5VSUSFET

P5VSUS_SS

=PP3V3_S3_P3V3S3FET

=PP1V5_S3RS0_FET

PP1V5_S3RS0_FET_R

=PP1V5_S3_P1V5S3RS0_FET

P1V5S0FET_GATE_R

SYNC_DATE=01/10/2011

SYNC_MASTER=K78_MLB

Power FETs

CRITICAL

POWER33

FDMC2514SDC

MF-LF

1206

1/4W

5%

0

CRITICAL

SIA413DJ

SC70-6L

100K

5% 1/20W MF 201

220K

MF

1/20W

5%

201

10K

MF

1/20W

5%

201

91K

1/20W

MF

5%

CRITICAL

SIA427DJ

SC70-6L

SIA427DJ

SC70-6L

CRITICAL

SC70-6L

SIA427DJ

CRITICAL

201

1/20W MF

5%

220K

3.3K

MF

1/20W

5%

201

5%

1/20W

MF

12K

201

1/20W MF

5%

100K

SOT563

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

10% 10V X5R

0.01UF

201

0.01UF

10% 16V

CERM

402

10% 16V

402

X5R

0.033UF

402

10% 16V X5R

0.033UF

SOT563

SSM6N37FEAPE

61 62

8

4.7UF

10%

X5R-CERM

6.3V

603

NO STUFF

1/16W

402

0

5%

MF-LF

20%

0.1UF

10V

CERM

402

TDFN

CRITICAL

SLG5AP020

CRITICAL

TPCP8102

23V1K-SM

0.01UF

10%

402

CERM

16V

402

16V

0.033UF

X5R

10%

201

5%

1/20W

MF

10K

62

SOT563

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

62

402

16V

0.033UF

10%

X5R

0.01UF

X5R

10V

10%

201

1/20W

MF

47K

5%

16V X5R

10%

402

0.033UF

10V

0.01UF

10%

X5R 201

26

C7810

12

C7811

1

2

R7810

12

C7830

12

C7831

1

2

Q7812

6

2

1

Q7812

3

5

4

R7860

12

C7861

1

2

C7860

12

Q7860

5678

4

123

U7801

5

7

4

2

8

6

3

9

1

C7801

1

2

R7801

12

C7802

1

2

Q7822

6

2

1

C7841

1

2

C7821

1

2

C7840

12

C7820

12

Q7822

3

5

4

Q7802

3

5

4

R7812

1

2

R7820

12

R7840

12

R7862

1

2

Q7830

1

3

47

Q7820

1

3

47

Q7810

1

3

47

R7830

12

R7832

1

2

R7842

1

2

R7822

1

2

Q7840

1

3

47

R7850

12

Q7801

5

4

123

78 OF 109

3.13.0

051-8870

61 OF 75

7

G

D

S

IN

G

D

S

OUT

IN

OUT

D

GS

IN

OUT

IN

NC

Q3

Q2

Q4

Q1

IN

SENSE

CT

VDD

GND

RESET*

MR*

IN

G

D

S

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

VDD

OUT_A*

OUT_A

THRM

GND

IN_A

DLY_1C

IN_B

OUT_B

DLY

(OD,IPU)

(IPD)

1.3V

PAD

2:1

-

+

OUT

IN

OUT

NC

VCC

A

Y

GND

B

C

IN

OUT

IN

G

D

S

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

S5 Rail Enables & PGOOD

Internal pull-ups 100K +/- 20%

343S0497

CPUVCORE ENABLE

Threshold: ??

SMC-->PM_DSW_PWRGD

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

DLY > 10 ms

Delete R when pull-down added to PCH page

3.3V S4 ENABLE

3.3V/5.0V Sus ENABLE

SMC_BATLOW_L:100K pull up on SMC page

3.3V SUS Detect

Unused fet

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

(PM_SLP_S3_L)

VDD: 2.734V-3.010V

00

VFRQ High: Variable Frequency

353S2310

Deep Sleep (S4)

PP1V5_S3RS0

Battery Off (G3Hot)

State

Run (S0)

Deep Sleep (S5)

0

1

0

11

0

PM_SLP_S3_LPM_SLP_S5_L

SMC_PM_G2_ENABLE

Q3: 0.640V

VFRQ Low: Fix Frequency

1

0

1

Sleep (S3)

1

Thresholds:

V4MON: 0.572V-0.630V

V3MON: 0.572V-0.630V

V2MON: 2.815V-3.099V

3.3V w/Divider: 2.345V

DP S4 Power Enable

U7930 Sense input

No stuff C7931, 12ms

PM_SLP_S4_L

(PM_SLP_S3_R_L)

353S2809

Q4: 0.660V

Q2: 0.XXXV

Worst-Case Thresholds:

S0 Rail PGOOD (BJT Version)

P1V5S0_PGOOD from U7710

(ISL Version in development)

S0 Rail PGOOD Circuitry

(IPU)

PSOC USB Power Enable

Delete R when pull-down added to PCH page

S0 ENABLE

PM_RSMRST_L goes to U1800.C21

(AC_EN_L)

Min delay time

threhold is 3.07V

CHGR VFRQ Generation

(90K IPU)

0

3.3V,5V S3 ENABLE

Delete R when pull-down added to PCH page

2N7002DW-X-G

SOT-363

42 41 17

62 41 26 17

SOT-363

2N7002DW-X-G

37

55

56

61

PLACE_NEAR=Q7812.2:6mm

CERM-X5R

10%

402

0.47UF

6.3V

57

PLACE_NEAR=U7400.1:5mm

201

1/20W

0

MF

5%

61

45

59

60

54

PLACE_NEAR=U7300.16:6mm

201

MF

1/20W

5%

5.1K

PLACE_NEAR=U7300.16:6mm

0.47UF

402

CERM-X5R

6.3V

10%

49 41 26 17

PLACE_NEAR=U7720.5:6mm

0.47UF

10%

CERM-X5R 402

6.3V

PLACE_NEAR=U7720.5:6mm

201

1/20W

MF

5.1K

5%

PLACE_NEAR=U7600.3:6mm

402

CERM-X5R

0.47UF

10%

6.3V

0.47UF

PLACE_NEAR=U7100.15:6mm

CERM-X5R

6.3V

10%

402

PLACE_NEAR=U7100.15:6mm

201

MF

1/20W

5%

33K

201

1/20W

MF

5%

PLACE_NEAR=U1800.D4:5mm

100K

5%

10K

MF

1/20W

201

53

SSM3K15FV

SOD-VESM-HF

62 41 26 17

65

PLACE_NEAR=U7400.1:5mm

0

MF

1/20W

5%

201

41

PLACE_NEAR=U7400.1:5mm

NO STUFF

5% MF

1/20W

0

201

NO STUFF

5%

0

MF

1/20W

201

5%

10K

MF

1/20W

201

62 52 41 25 23

201

5%

100

1/20W

MF

5%

MF

1/20W

100

201

5%

MF

1/20W

100

201

100

MF

1/20W

5%

201

60

55

5%

100

MF

1/20W

201

5%

S0PGOOD_ISL

MF

1/20W

330

201

62 59

54

201

1/20W

MF

1%

150K

201

S0PGOOD_ISL

6.3V X5R

0.1UF

10%

201

1/20W MF

15K

1%

201

7.15K

1/20W MF

1%

ASMCC0179

DFN2015H4-8

CRITICAL

5%

1K

1/20W

MF

201

1/20W

1K

MF

5%

41 17

CRITICAL

SOT23-6

TPS3808G33DBVRG4

NO STUFF

16V X7R

1000PF

10%

201

1/20W

MF

100K

5%

6.3V X5R

0.1UF

10%

PLACE_NEAR=U7930.6:2.3mm

201

5%

MF

1/20W

NO STUFF

100

201

57

SOT-363

2N7002DW-X-G

201

1/20W

MF

100

5%

60

PLACE_NEAR=U7770.3:6mm

0.47UF

6.3V CERM-X5R

10%

402

17

201

MF

1/20W

100K

5%

201

1/20W

MF

5%

100K

ISL88042IRTEZ

S0PGOOD_ISL

CRITICAL

TDFN

15K

201

1/20W

MF

S0PGOOD_ISL

1%

201

MF

1/20W

10K

S0PGOOD_ISL

1%

201

MF

15K

1/20W

S0PGOOD_ISL

1%

S0PGOOD_ISL

1/20W

201

10K

MF

1%

6.04K

1/20W

201

1%

MF

S0PGOOD_ISL

201

S0PGOOD_ISL

1/20W

MF

6.04K

1%

55

X5R 402

NO STUFF

10%

0.033UF

16V

100

MF

5%

1/20W

201

41

0.1UF

201

10% X5R

6.3V

41

SLG4AP012

CRITICAL

TDFN

220PF

X7R-CERM 201

10% 25V

40 39

6

201

5%

1/20W

MF

0

NO STUFF

10V

402

10%

0.068UF

CERM

42 41

60

20K

PLACE_NEAR=U7600.3:6mm

201

1/20W MF

5%

0

5%

NO STUFF

MF

1/20W

201

74AUP1G3208

SOT891

6.3V

0.1UF

201

10%

X5R

PLACE_NEAR=U7940.5:2.3mm

17

42 41

PLACE_NEAR=U1800.A15:5mm

MF

5%

100K

201

1/20W

61

PLACE_NEAR=U7770.3:6mm

201

1/20W MF

39K

5%

PLACE_NEAR=Q7812.2:6mm

201

MF

1/20W

5%

9.1K

5%

100

MF

1/20W

201

55

37 18

SOT-363

2N7002DW-X-G

5%

1K

1/20W

MF

201

SYNC_MASTER=K78_MLB

SYNC_DATE=01/10/2011

Power Control 1/ENABLE

MAKE_BASE=TRUE

PM_SLP_S4_L

P3V3S3_EN

MAKE_BASE=TRUE

P5VS3_EN

MAKE_BASE=TRUE

=P5VS3_EN

PM_SUS_EN

MAKE_BASE=TRUE

PM_SLP_S3_R_L

CPUIMVP_VR_ON

AP_PWR_EN

=P5V_3V3_SUS_EN

P1V5S0_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

PM_RSMRST_L

ALL_SYS_PWRGD

P1V8S0_PGOOD

CPUVCCIOS0_PGOOD

=PP3V3_S0_VMON

P5V_DIV_VMON

P1V5_DIV_VMON

=PP5V_S0_VMON

=PP1V05_S0_VMON

VMON_3V3_DIV VMON_Q2_BASE

=PP3V3_S5_VMON

S0PGD_C

VMON_Q4_BASE

S0PGD_BJT_GND_R

PM_PECI_PWRGD

PM_SLP_SUS_L

S4_PGOOD_CT

=PP3V3_SUS_PWRCTL

=PP3V3_S5_PWRCTL

=DPAPWRSW_EN

=P5V3V3_REG_EN

CPUVCCIOS0_PGOOD

=P3V3S3_EN

=USB_PWR_EN

=DDRREG_EN

=1V05_S0_LDO_EN

=P5VS0_EN

=P3V3S0_EN

=P1V8S0_EN

P1V05_DIV_VMON

CHGR_VFRQ

=PVCCSA_EN

=PP1V5_S3RS0_VMON

ALL_SYS_PWRGD

SMC_ADAPTER_EN

=PBUSVSENS_EN

=CPUVCCIOS0_EN

=P1V5S0_EN

=PP3V42_G3H_PWRCTL

=P3V3S5_EN

=PP3V3_S0_VMON

VMON_Q3_BASE

=PP1V5_S3RS0_VMON

=PP1V05_S0_VMON

ALL_SYS_PWRGD_R

=PP3V3_S0_PWRCTL

P5VS3_PGOOD

P3V3S5_PGOOD

PVCCSA_PGOOD

SMC_BATLOW_L

CPUIMVP_AXG_PGOOD

PM_SLP_S3_L

AC_EN_L

PM_WLAN_EN_L

PVCCSA_EN

MAKE_BASE=TRUE

P1V8S0_EN

CPUVCCIOS0_EN

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

=PP3V3_SUS_PWRCTL

MAKE_BASE=TRUE

S5_PWRGD

S5PGOOD_DLY

P5V3V3_REG_EN

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

PM_SLP_S5_L

PM_SLP_S3_L

ALL_SYS_PWRGD

=PP3V3_S5_PWRCTL

SMC_PM_G2_EN

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

P3V3S5_EN

MAKE_BASE=TRUE

Q7920

6

2

1

Q7925

6

2

1

C7912

1

2

R7974

12

R7911

1

2

C7910

1

2

C7986

1

2

R7986

1

2

C7981

1

2

C7987

1

2

R7987

1

2

R7979

1

2

R7931

12

Q7931

3

1

2

R7975

12

R7976

12

R7929

1

2

R7967

1

2

R7957

1

2

R7966

12

R7964

12

R7901

12

R7963

12

R7962

12

R7956

1

2

C7960

1

2

R7951

1

2

R7952

1

2

Q7950

5

7

1

6

4

8

2

3

R7954

12

R7955

12

U7930

4

2

3

15

6

C7931

1

2

R7933

1

2

C7930

1

2

R7968

12

Q7920

3

5

4

R7978

12

C7988

1

2

R7910

1

2

R7915

1

2

U7960

4

1

8

9

3 5 6

2

7

R7973

1

2

R7971

1

2

R7961

1

2

R7970

1

2

R7972

1

2

R7960

1

2

C7942

1

2

R7941

12

C7940

1

2

U7941

7

5

2

6

3

4

8

9

1

C7941

1

2

R7913

12

C7913

1

2

R7981

1

2

R7917

12

U7940

1

3

6

2

5

4

C7943

1

2

R7918

1

2

R7988

1

2

R7912

1

2

R7965

12

Q7925

3

5

4

R7953

12

79 OF 109

3.13.0

051-8870

62 OF 75

62

7

62

7

62

7

62

7

62 59

62

7

62 52 41 25 23

62

7

62

7

62

7

62

7

62

7

62 52 41 25 23

62

7

62

7

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

OUT

IN

BI

IN

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

(DP_INT_AUX_CH_C_P)

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

DisplayPort I/F

LCD Connector

Internal DP Connector: 518S0787

(DP_INT_AUX_CH_C_N)

LED Backlight I/F

4.7 kOhm to 3.3V

Pull-ups on panel side,

DP_INT_ML_F_N<1>

DP_INT_ML_F_N<0>

PP3V3_SW_LCD

Internal DisplayPort Connector

FERR-120-OHM-1.5A

100K

66

LED_RETURN_1

LED_RETURN_2

DP_INT_HPD_CONN

MIN_LINE_WIDTH=0.30 MM

DP_INT_AUX_CH_C_P

DP_INT_ML_F_P<0>

201201

PLACE_NEAR=J9000.24:1mm

PLACE_NEAR=J9000.25:1mm

PLACE_NEAR=J9000.3:2mm

1M

5% 1/20W MF

1M

5%

1/20W

MF

LED_RETURN_3

100K

5% 1/20W MF 201

0402-LF

5%

DP_INT_ML_F_P<1>

1000PF

X5R-CERM

9

70

MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V

6

DP_INT_AUX_CH_N

LCD_IG_PWR_EN

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

PP3V3_SW_LCD_UF

I2C_TCON_SCL_R

DP_INT_ML_P<0>

LED_RETURN_5

DP_INT_ML_N<0>

DP_INT_ML_P<1>

DP_INT_ML_N<1>

=PP3V3_S5_LCD

LED_RETURN_4

LED_RETURN_6

PPVOUT_SW_LCDBKLT

=I2C_TCON_SDA

=I2C_TCON_SCL

I2C_TCON_SDA_R

DP_INT_AUX_CH_C_N

DP_INT_AUX_CH_P

DP_INT_HPD

SYNC_MASTER=K78_MLB

SYNC_DATE=02/10/2011

1/20W

MF

0

5%

201

MF

1/20W

0

5%

201

44

9

70

9

70

8

9

70

9

70

9

70

6

66

6

66

6

66

6

66

6

66

9

5% 1/20W

201

MF

1/20W

MF

201

0

5%

201

MF

1/20W

CRITICAL

CABLINE-CA

F-RT-SM

0.1UF

0201

X5R-CERM

10% 16V

0.1UF

0201

X5R-CERM

16V

10%

0.1UF

0201

16V

10%

0.1UF

0201

X5R-CERM

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

16V

10%

X7R 201

16V

10%

1000PF

603

50V

5%

FPF1009

CRITICAL

MFET-2X2-8IN

10%

6.3V X5R 201

0.1UF

201

MF

1/20W

5%

1K

0.1UF

201

X5R

6.3V

10% 20%

6.3V X5R 603

10UF

C0G-CERM

100K

L9004

12

C9012

1

2

C9011

1

2

R9014

1

2

C9009

1

2

U9000

617

2

3

4

5

C9017

1

2

C9015

1

2

C9024

12

C9025

12

C9020

12

C9021

12

C9022

12

C9023

12

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

5

6

7

8

9

R9050

1

2

R9060

12

R9080

1

2

R9070

1

2

R9061

12

R9062

12

R9017

1

2

R9018

1

2

90 OF 109

3.13.0

051-8870

63 OF 75

70

6

70

6

70

6

7

6

66

6

70

6

70

6

70

OUT

BI

OUT

IN

OUT

IN

BI

NC

IN

BI

THMPAD

GND

VDD

OUT_D0P OUT_D0N

OUT_D1P

OUT_D2P

OUT_D1N

OUT_D3P

OUT_D2N

OUT_D3N

AC_AUXP AC_AUXN

OUT_HPD

CEXT

IN_D0P IN_D0N

IN_D1N

IN_D2N

IN_D3P

IN_SDA

IN_AUXP IN_AUXN

IN_HPD

I2C_CTL_EN

I2C_ADDR0 I2C_ADDR1

SCL_CTL SDA_CTL

REXT

AUXDDC_OFF

PD

CA_DET

IN_SCL

IN_D3N

IN_D2P

IN_D1P

OUT_AUXN_SDA

OUT_AUXP_SCL

BI

IN

BI

OUT

IN

OUT

VDD

PIO1_8/CT16B1_CAP0

PIO1_7/TXD

XTALIN

PIO1_4/AD5/WAKEUP

PIO1_6/RXD

SWDIO/PIO1_3/AD4

R/PIO1_2/AD3

R/PIO1_1/AD2

R/PIO1_0/AD1

RESET#/PIO0_0 PIO0_1/CLKOUT

SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO0_9/MOSI/CT16B0_MAT1

PIO0_8/MISO/CT16B0_MAT0

PIO0_2/SSEL/CT16B0_CAP0

R/PIO0_11/AD0

PIO0_7/CTS#

PIO0_6/SCK

PIO0_4/SCL PIO0_5/SDA

VSS

THRM

PAD

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

AUX-

AUX+

D1+ D1-

HPD_SEL

GND

THMPAD

SEL

HPD_B

AUX-B

AUX+B

D1-B

D1+B

D0-B

HPD_A

AUX-A

AUX+A

D1-A

D0-

D0+A D0-A

D1+A

HPD

D0+

D0+B

VDD

AUX_SEL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

T29 signals are

(C9383.2)

(C9380/C9381)

(C9383.2)

(C9370/C9371)

to prevent spikes when U9310 AUXDDC_OFF

footprint-compatible parts with

HI=Port B

Note: Other Parade

used by PS8301

(C9372.2)

CBTL04DP081 (353S3151) and

similar pinouts. NXP uses pin 10 for ML and HPD, Pericom uses pin 10 for ML and pin 11 for HPD.

PI3vEDP212 (353S3055) are

(C9373.2)

PS8301 I2C Addresses:

(IPU)

(IPD)

(All 4 D’s)

(D9360/D9361)

(D9361.2)

1 0 0x94/0x95

Must be 3.3V DP A port power

(DP_SDRVA_AUXCH_N)

(DP_SDRVA_AUXCH_P)

T29 A High-Speed Signals

D9364/D9365:

D9372/D9373:

LO=Port A

(D9360.2)

T29: TX_1

T29: TX_0

(D9364.2)

I2C Addr:

SWDIO

SWCLK

detection of DP Source.

P2R = Plug to Receptacle R2P = Receptacle to Plug

0x26/0x27 (Wr/Rd)

(IPU)

(OD)

pull-ups on ML<3>. U9390 AUX defaults to DP mode because 100-ohm pull-downs would defeat DP Sink’s

(IPD)

A1 A0 Addr (W/R)

0 1 0xB6/0xB7

(IPD)

(D9365.2)

(D9372/D9373)

(OD)

(D9382/D9383)

(IPD)

(DP_SDRVA_HPD)

R9330 provides pads for programming/debug of MCU, please make accessible.

=T29_WAKE_L:

Desktops use PCIe WAKE# Mobiles use S4 WAKE#

so only 94/B4 are

devices use 96/B6,

1 1 0xB4/0xB5

transitions from high to low.

during training.

(D9382/D9383)

DP Path Biasing

Display can detect host T29 support using I2C

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29

and DDC, alias nets together at GPU.

(IPD)

(All 4 D’s)

T29 Path Biasing

high while Vcc = 0V.

Port A MCU

IC supports input

If project has space for 10-pin programming header it should be used.

0 0 0x96/0x97

used for this part.

(OD)

If GPU uses common pins for AUX_CH

Must be 3.3V DP A port power

T29: LSX_A_R2P/P2R (P/N)

T29: Unused

T29: RX_1 Bias Sink

(T29_A_LSX_P2R)

AUXCH Snoop Port,

PS8301 has internal

Parade (pin is 5V-tolerant).

~150K pull-down on PD pin. Okay to drive this pin even when VCC=0V per

(T29_A_LSX_R2P)

DP A Super-Driver

R9308/R9309 maintain bias on C9308/C9309

DP/T29 A Low-Speed MUX

caps to improve layout.

P/N-swapped after AC

72 65

201

1/20W MF

1K

5%

4.99K

MF

1/20W

1%

201

8

NO STUFF

1K

5%

MF

1/20W

201

1K

MF

1/20W

201

5%

10%

0201

X5R-CERM

16V

0.1UF

10%

0201

X5R-CERM

16V

0.1UF

402-LF

CERM

20%

2.2UF

PLACE_NEAR=U9310.11:2 mm

70

8

70

8

70

8

70

8

70

8

70

8

0201

0.1UF

16V

X5R-CERM

10%

70

8

70

8

44

70

8

70

8

201

1/20W MF

100K

5%

201

1/20W MF

5%

100K

8

CRITICAL

PS8301TQFN40GTR-A2

QFN

2.2UF

6.3V

402-LF

CERM

20%

72 65

64

72 65

64 42

18

17

34

HVQFN25

LPC1112A

CRITICAL

OMIT_TABLE

44

65 64

8

34

44

34

201

MF

1/20W

1K

5%

201

10K

5% 1/20W MF

10%

0201

X5R-CERM

16V

0.1UF

34

65

10%

0201

X5R-CERM

16V

0.1UF

201

5% 1/20W MF

1K

201

1/20W

MF

1K

5%

1M

MF

1/20W

201

MF

1/20W

5%

10K

201

65

0

OMIT

5%

MF

1/20W

201

5%

51

MF

1/20W

201201

51

5%

MF

1/20W

65 36

MF

1/20W

201

5%

10K

23 16

SDRV_PD

MF

1/20W

5%

0

201

1M

1/20W

MF5%201

5%

1M

MF

1/20W

201

72 65

BAR90-02LRH

TSLP-2-7

GND_VOID=TRUE

CRITICAL

SIGNAL_MODEL=EMPTY

TSLP-2-7

GND_VOID=TRUE

CRITICAL

BAR90-02LRH

SIGNAL_MODEL=T29PIN

BAR90-02LRH

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

TSLP-2-7

CRITICAL

TSLP-2-7

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

CRITICAL

BAR90-02LRH

GND_VOID=TRUE

TSLP-2-7

CRITICAL

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=T29PIN

CRITICAL

TSLP-2-7

BAR90-02LRH

GND_VOID=TRUE

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

TSLP-2-7

CRITICAL

BAR90-02LRH

SIGNAL_MODEL=EMPTY

CRITICAL

TSLP-2-7

GND_VOID=TRUE

201

4V

CERM-X5R-1

20%

0.47UF

GND_VOID=TRUE

1.5K

5%

201

1/20W

MF

SIGNAL_MODEL=EMPTY

1/20W

5%

GND_VOID=TRUE

201

MF

1.5K

MF

1.5K

1/20W

5%

GND_VOID=TRUE

201

5%

1/20W

201

0.47UF

20%

GND_VOID=TRUE

201

CERM-X5R-1

4V

0.47UF

4V

201

CERM-X5R-1

20%

GND_VOID=TRUE

201

4V

GND_VOID=TRUE

CERM-X5R-1

20%

0.47UF

4V

GND_VOID=TRUE

CERM-X5R-1

20%

0.47UF

4V

CERM-X5R-1

201

0201

6.3V

20% X5R

1.5K

201

5%MF1/20W

GND_VOID=TRUE

1.5K

5%

1/20W

201

MF

GND_VOID=TRUE

72 65

1.5K

GND_VOID=TRUE

MF5%201

1/20W

1.5K

GND_VOID=TRUE

MF

5%

1/20W

201

1/20W

201

MF

5%

0201

X5R-CERM

10% 16V

0.1UF

X5R-CERM 0201

16V

10%

0.1UF

201

MF

5%

1/20W

1.5K

5%

1/20W

201

MF

1.5K

5%

201

MF

1/20W

1.5K

MF5%201

1/20W

SC70

201

6.3V X5R

10%

0201

X5R

6.3V

20%

0.22UF

6.3V

X5R

201

4V

20%

0.47UF

CERM-X5R-1

GND_VOID=TRUE

20%

4V

201

0.47UF

CERM-X5R-1

201

5% 1/20W MF

5%

MF

270

1/20W

5% MF

1/20W

201

30

1/20W

201

MF

5% MF

201

8

5%511/20W

201

MF

PLACE_NEAR=C9361.1:2mm

1/20W

201

5%MF

51

PLACE_NEAR=C9361.1:2mm

201

5%

1/20W

MF

51

PLACE_NEAR=C9361.1:2mm

1/20W

201515%MF

0201

X5R-CERM

0.1UF

16V10%

X5R-CERM

0.1UF

16V10%

0201

X5R-CERM

0.1UF

16V10%

X5R-CERM

0.1UF

0201

16V10%

0.1UF

16V10%

0201

X5R-CERM

0201

10% 16V

0.1UF

0201

X5R-CERM

16V10%

0.1UF

0201

16V10%

0.1UF

X5R-CERM

10% 16V

0.1UF

X5R-CERM

0201

0.1UF

16V10%

X5R-CERM

0201

0.1UF

16V10%

X5R-CERM

10%

0.1UF

16V

0.1UF

0201

X5R-CERM

16V10%

0201

0.1UF

16V10%

10% 16V

0.1UF

X5R-CERM

0201

CRITICAL

TQFN

PI3VEDP212

0

5%

MF

SYNC_MASTER=K21_MLB

SYNC_DATE=12/13/2010

DisplayPort/T29 A MUXing

DP_AUXCH_ISOL

DP_AUXCH_ISOL_R

DP_A_PWRDWN

DP_A_PWRDWN_R

DPSDRVA_REXT

DP_SDRVA_AUXCH_N

DP_SDRVA_ML_N<1>

DP_SDRVA_ML_C_N<1>

DP_SDRVA_ML_C_P<1>

DP_SDRVA_ML_C_N<0>

DP_SDRVA_ML_N<3>

T29_A_LSX_P2R

DP_A_EXT_AUXCH_P

T29DPA_ML_P<3>

T29DPA_ML_C_P<2>

T29_R2D_N<0>

T29_D2R_C_N<0>

DP_A_PWRDWN

T29_D2R1_BIASN

T29_D2R1_BIASP

T29_A_RSVD_P

DP_SDRVA_HPD

DP_SDRVA_AUXCH_P

DP_SDRVA_ML_P<1>

PP3V3_SW_DPAPWR

DP_SDRVA_ML_P<3>

DP_A_EXT_HPD

T29_A_BIAS

DP_EXTA_ML_C_N<2>

=T29_WAKE_L

DP_EXTA_AUXCH_C_P

DP_EXTA_AUXCH_C_N

DP_EXTA_ML_N<1>

PP3V3_SW_DPAPWR

DP_EXTA_ML_C_N<0>

T29_A_BIAS_R2DP0

T29_D2R_C_N<1>

T29_R2D_P<0>

DP_EXTA_ML_P<1>

DP_EXTA_ML_N<2>

DP_EXTA_ML_P<0>

DP_A_CA_DET

DPSDRVA_CEXT

DP_SDRVA_ML_C_P<3>

DP_EXTA_AUXCH_P

=PP3V3_S0_DPSDRVA

DP_EXTA_DDC_CLK

DP_SDRVA_ML_R_N<2>

DP_SDRVA_AUXCH_C_P

DP_SDRVA_ML_C_N<3>

DP_EXTA_ML_C_N<3>

DP_EXTA_ML_C_P<3>

DP_EXTA_ML_P<2>

DP_EXTA_AUXCH_N

DP_EXTA_ML_C_P<2>

DP_EXTA_ML_C_N<1>

DP_EXTA_ML_P<3>

DP_EXTA_ML_N<3>

DP_EXTA_ML_C_P<0>

DP_EXTA_ML_N<2>

DP_EXTA_ML_C_P<1>

DP_EXTA_ML_P<1>

DP_EXTA_ML_N<0>

T29_A_HV_EN_R T29_A_UC_ADDR DP_A_EXT_HPD

T29_D2R_C_P<0>

T29DPA_ML_C_N<0>

DP_A_PWRDWN

T29DPA_ML_C_P<0>

DP_EXTA_ML_N<1>

DP_EXTA_ML_N<0>

=I2C_DPSDRVA_SCL

DP_EXTA_AUXCH_N

T29DPA_CONFIG1_RC T29DPA_CONFIG2_RC

T29_LSEO<1>

T29_A_UC_ADDR

DP_EXTA_ML_P<2>

DP_A_CA_DET

T29_A_HV_EN

VOLTAGE=3.3V

DP_A_BIAS_P_2

DP_A_BIAS_N_2

VOLTAGE=3.3V

DP_A_BIAS_P_0

T29DPA_ML_C_N<2>

VOLTAGE=3.3V

DP_A_BIAS_N_0

DP_EXTA_ML_P<0>

DP_SDRVA_AUXCH_C_N

T29_MCU_INT_L

T29_LSOE<1>

T29_LSOE<0>

T29_A_BIAS

T29DPA_HPD

=I2C_T29AMCU_SDA

=I2C_T29AMCU_SCL

T29_LSEO<0>

=PP3V3_S0_DPSDRVA

DP_EXTA_ML_N<3>

DP_SDRVA_ML_C_P<2>

T29DPA_ML_N<3>

DP_A_EXT_AUXCH_N

T29_A_RSVD_N

T29_A_LSX_R2P

T29_D2R_C_P<1>

SIGNAL_MODEL=EMPTY

30

T29DPA_ML_N<1> T29DPA_ML_P<1>

30

GND_VOID=TRUE

72 34

72

34 72

34

34 72

T29_D2R_N<0> T29_D2R_P<0>

T29_D2R_N<1>

72

T29_R2D_C_P<0>

T29_R2D_C_N<0>

GND_VOID=TRUE

T29_R2D_P<1> T29_R2D_N<1>

201

DP_SDRVA_ML_R_P<0>

0.47UF

201

1/20W

=I2C_DPSDRVA_SDA

30

5%

1/20W

270

0.1UF

CRITICAL

DP_SDRVA_ML_C_N<2>

DP_EXTA_DDC_DATA

DP_EXTA_AUXCH_P

DP_EXTA_HPD

DPSDRVA_I2C_CTL_EN

DPSDRVA_I2C_ADDR0 DPSDRVA_I2C_ADDR1

6.3V

1.5K

SIGNAL_MODEL=EMPTY

T29_A_BIAS_R2DP1

T29_A_BIAS_R2DN0

8

DP_SDRVA_ML_N<2>

X5R

GND_VOID=TRUE

0.22UF

DP_A_BIAS

74LVC1G04DBDCK

X5R-CERM

0201

DP_SDRVA_ML_R_P<2>

0201

20%

6.3V 0201

X5R-CERM

=PP3V3_S0_DPSDRVA

0.22UF

20%

GND_VOID=TRUE

T29_A_BIAS_R2DN1

DP_SDRVA_ML_R_N<0>

201

DP_EXTA_ML_P<3>

DP_SDRVA_ML_C_P<0>

T29_D2R_P<1>

MF

SIGNAL_MODEL=EMPTY

DP_SDRVA_ML_P<0> DP_SDRVA_ML_N<0>

DP_SDRVA_ML_P<2>

34 72

72 34

T29_R2D_C_P<1>

T29_R2D_C_N<1>

34

R9312

1

2

R9319

1

2

R9311

1

2

R9310

1

2

C9311

1

2

C9312

1

2

C9319

1

2

C9300

12

R9399

1

2

R9398

1

2

U9310

19

20

39

32

11

6

33

36

35

26

15

16

2

1

5

4

8

7

10

9

3

14

13

17

18

29

30

27

28

24

25

22

23

31

34

12

38

37

41

21

40

C9310

1

2

U9330

2

7

8

9

10

11

12

13

20

23

24

6

15

16

17

18

1

14

19

25

5

22

3

21

4

R9335

1

2

R9336

1

2

C9330

1

2

C9331

1

2

R9397

12

R9396

12

R9339

1

2

R9338

1

2

R9330

1

2

R9393

1

2

R9392

1

2

R9334

12

R9318

12

R9308

12

R9309

12

D9364

12

D9373

12

D9372

12

D9365

12

D9360

12

D9382

12

D9383

12

D9361

12

C9370

12

R9372

12

R9373

12

R9382

12

R9383

12

C9373

12

C9372

12

C9371

12

C9382

12

C9383

12

C9364

12

R9385

12

R9384

12

R9375

12

R9374

12

R9354

12

C9390

1

2

C9391

1

2

R9360

12

R9361

12

R9364

12

R9365

12

U9359

2

3

5

4

C9359

1

2

C9365

12

C9360

12

C9361

12

C9380

12

C9381

12

R9352

1

2

R9353

1

2

R9355

12

R9350

12

R9351

12

R9362

12

R9363

12

R9366

12

R9367

12

C9301

12

C9302

12

C9303

12

C9304

12

C9305

12

C9306

12

C9307

12

C9308

12

C9309

12

C9363

12

C9362

12

C9367

12

C9366

12

C9369

12

C9368

12

U9390

7

6

32

18

19

14

15

2

1

30

31

24

25

5

4

26

27

22

23

21

28

8

17

13

11

10

33

39121620

29

R9390

12

93 OF 109

3.13.0

051-8870

64 OF 75

64

72

64

69

8

72

65 64

72

65 64

8

70 64

65 64

72

70 64

72

70 64

64

7

72

70 64

64

64 42

70 64

64

70 64

64

70 64

8

70 64

72

64

7

70

72

69

8

72

64

7

72

64

72

OUT

IN

BI

IN

OUT

BI

IN

D

SG

D

SG

G

D

S

D

GS

OUT

BI

IN

GND

PGND

OUT

FB

IN

SGD

GND

PGND

OUT

FB

IN

OUT

IN

CT

EN*

RTRY*

VIN

THRM

GND

IFLT

ILIM

FLT*

VOUT

PAD

DP_PWR

AUX_CHP

ML_LANE3P

ML_LANE3N

CONFIG1

AUX_CHN

RETURN

GND

ML_LANE0N

ML_LANE0P

CONFIG2

HOT_PLUG_DETECT

GND

ML_LANE1P ML_LANE1N

ML_LANE2P ML_LANE2N

SHIELD PINS

OC*

OUT IN

EN

GND

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

Circuit threshold range: 3.363-3.439V (3.395V nominal)

High: 2.0 - 5.0V

T29: TX_0

when Source >3.4V

Blocking FET, off

DisplayPort/T29 A Connector

(Both L’s)

T29: Unused

Port A HV Power Switch

HIGH and T29_A_HV_EN

Circuit threshold range: 2.877-2.941V (2.903V nominal)

down HPD input with

ILIM 935mA 925mA 1A (*)

TSD 470ms 235ms 724ms

TFLT 18.3ms 13.4ms 26.7ms

(*) U9410 tolerance unknown

(IPU-Weak!)

Vds(max): -30V

Vgs(th): -1.4V

Id(max): 3.7A @ 70C

P = ~27mW

DP_PWR must be S4/S5 to support

3.3V/HV Power MUX

3.3V Always

or HV_EN high.

Vgs(max): +/-12V

Note: Bleeder active when

wake from T29 devices.

Rds(on): 65mOhm @ 2.5V Vgs

SI8409DB:

to 100K (DPv1.1a).

Sink HPD range:

T29: TX_1

on AC-coupled signals.

Low: 0 - 0.8V

2.5V / 249 ohm = 10mA

470k R’s for ESD protection

is LOW.

DPAPWRSW_HV_DET is

<RFLT>

3.3V/HV MUXed

T29: LSX_R2P/P2R (P/N)

IFLT 885mA 876mA 894mA (*)

Nominal Min Max

20V Max

SN1010017

greater than or equal

DP Source must pull

(Both C’s)

Bleeder Resistor

ZXRE060A REF range: 0.595-0.605V (0.600V nominal)

T29 Dir

(Both C’s)

DP Dir

Port A 3.3V Power Switch

IFLT = 200k / RFLT = 885mA

ILIM = 201k / RLIM = 935mA

TFLT = CCT * 38900

TSD = CCT * 100000

T29 Dir

DP Dir

T29DPA_ML_N<1>

T29DPA_ML_P<1>

T29DPA_ML_N<3>

T29DPA_ML_P<3>

MDP-K21-K78

FERR-120-OHM-3A

SYNC_MASTER=K78_MLB

470K

GND_VOID=TRUE

CERM-X5R-1

MIN_LINE_WIDTH=0.38 MM

MIN_NECK_WIDTH=0.20 MM

10%

0603

DP_A_EXT_AUXCH_N

MF

MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_SW_DPAPWR

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_1

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

650NH-5%-0.430MA-0.052OHM

CRITICAL

0603

GND_VOID=TRUE

402

SIGNAL_MODEL=EMPTY

T29DPA_ML_N<0>

T29DPA_ML_P<0>

10%

MF

DPAPWRSW_HVEN_L_R

GND_DPA7_R

VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

GND_DPACONN_19

VOLTAGE=0V

T29_D2R_C_P<0>

T29DPA_HPD_R

T29_D2R_C_N<0>

T29DPA_ML_C_N<2>

DPAPWRSW_HV_DET_L

DPAPWRSW_ILIM

DPAPWRSW_CT

T29DPA_HPD

DPACONN_20_RC

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

=PPHV_SW_DPAPWRSW

DPAPWRSW_IFLT

TP_DPAPWRSW_FLT_L

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PPHV_SW_DPAPWR

VOLTAGE=15V

T29DPA_CONFIG1_RC

DPAPWR_ON_L_C

DPAPWRSW_VREF

DPAPWRSW_HV_DET_R_L

DPAPWRSW_P3V3_ON_L

DPAPWRSW_P3V3_ON

DPAPWR_FB_DIV

T29_A_HV_EN

T29_A_BIAS

DPAPWRSW_ON_C

T29DPA_ML_C_P<0> T29DPA_ML_C_N<0>

DPAPWRSW_NPN_E

MIN_LINE_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM

DPAPWR_BLDR_E

T29_A_BIAS_R

VOLTAGE=3.3V

T29DPA_ML_C_P<2>

T29_D2R_C_N<1>

T29_A_BIAS_D2RP1

T29_A_BIAS

T29_A_BIAS_D2RN1

T29_A_HV_EN

=PP3V3_S4_DPAPWRSW

VOLTAGE=15V

T29_D2R_C_P<1>

GND_DPA1_R

DPAPWR_BLDR_B

GND_DPACONN_7

DPAPWRSW_HV_DET

T29DPA_CONFIG2_RC

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=3.3V

PP3V3_SW_DPAPWR

DisplayPort/T29 A Connector

SYNC_DATE=12/07/2010

201

5%

12

MF

1/20W

MF

12

5%

201

0.1UF

X5R

6.3V

201

210K

1% 1/20W MF

402

MF-LF

1/16W

5%

0

201

X5R

6.3V

SN1010017

QFN

CRITICAL

402

X5R

10V

10%

1UF

5%

82

MF

1/20W

201

1%

24.9K

MF

1/20W

201

CRITICAL

POWERDI-123

DFLS1100

201

22

5%

1/20W

MF

0.47UF

402

10%

CERM-X5R

6.3V

SM

CRITICAL

STPS2L30AF

8

201

0.1UF

X5R

6.3V

10%

MF

PLACE_NEAR=C9490.1:2mm

5% 1/20W

51

201

5%

12

201

MF

1/20W

0.47UF

201

20%

GND_VOID=TRUE

4V

GND_VOID=TRUE

201

20%

0.47UF

4V

CERM-X5R-1

201

20%

GND_VOID=TRUE

0.47UF

4V

MF

1/20W

201

GND_VOID=TRUE

5%

470K

5%

201

MF

GND_VOID=TRUE

470K

1/20W

5% 1/20W MF 201

4V

20%

GND_VOID=TRUE

CERM-X5R-1

201

64 72

201

1/20W

470K

5%

MF

GND_VOID=TRUE

SIGNAL_MODEL=T29PIN

BAR90-02LRH

GND_VOID=TRUE

CRITICAL

TSLP-2-7

GND_VOID=TRUE

CRITICAL

0.1UF

603-1

X7R

10% 50V

0.1UF

X7R

50V

10%

603-1

MF

1/20W

100K

5%

201

1/20W

220

5%

MF

201

NO STUFF

1/20W

1%

100K

MF

201

0.1UF

16V X5R-CERM 0201

10%

8

64 65

CRITICAL

SOT353

0.1UF

16V

X5R-CERM

0201

10%

NO STUFF

16V

0.1UF

X5R-CERM 0201

10%

SI8409DB

CRITICAL

BGA

CRITICAL

ZXRE060A

SOT353

36 64 65

64 72

64

FERR-120-OHM-3A

249

1%

MF

1/20W

201

SSM3K15FV

SOD-VESM-HF

SOT-563

DMB53D0UV

1K

1/20W

201

DMB53D0UV

SOT-563

470K

5%

1/20W

MF

201

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

5%

MF

1/20W

201

2.2K

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

1/20W

5%

2.2K

MF

201

330PF

201

X7R

16V

10%

201

X7R

16V

330PF

10%

201

1/20W MF

1M

5%

201

1/20W

MF

1M

5%

SOT563

SSM6N37FEAPESSM6N37FEAPE

SOT563

62

201

MF

1/20W

1%

21.5K

201

1/20W

MF

100K

1%

4.7K

MF

1/20W

5%

201

5%

10K

MF

1/20W

201

1K

1/20W MF

5%

201

MF

1/20W

4.7K

5%

SOT363

MMDT3946XG

6.3V

CASE-B2-SM

20%

CRITICAL

POLY-TANT

100UF

6.3V

603

20%

X5R-CERM-1

0.1UF

16V

X5R-CERM

0201

10% 16V X5R-CERM 0201

603

20%

6.3V X5R

10UF

201

MF

1/20W

5%

4.7K

64 72

GND_VOID=TRUE

5% 1/20W

100K

201

30PF

5%

CERM

50V50V

5%

402

CERM

1/20W MF 201

1K

5%

GND_VOID=TRUEGND_VOID=TRUE

1K

5%

1/20W

MF

201

SIGNAL_MODEL=EMPTY

0.01UF

10% 50V

402

X7R

12

5%

201

12

201

5%

1/20W

MF

0603

X7R 402

50V

10%

0.01UF

64 72

10%

X7R

50V

0.01UF

402

30PF

SIGNAL_MODEL=T29PIN

BAR90-02LRH

TSLP-2-7

T29DPA_D2R1_AUXCH_P

SIGNAL_MODEL=EMPTY

0603

5%

VOLTAGE=0V

MIN_LINE_WIDTH=0.38 MM

GND_VOID=TRUE

MIN_NECK_WIDTH=0.20 MM

T29DPA_ML_P<2>

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_SW_DPAPWR_UF

1/20W

MF

0.1UF

0.47UF

T29DPA_ML_N<2>

ZXRE060A

10%

CRITICAL

22UF

T29_A_HV_EN

=DPAPWRSW_EN

TPS2065DBV

0.1UF

CRITICAL

SOT23

DP_A_EXT_AUXCH_P

CRITICAL

F-RT-TH

650NH-5%-0.430MA-0.052OHM

CRITICAL

T29DPA_D2R1_AUXCH_N

L9400

12

C9400

1

2

C9402

1

2

L9408

12

R9402

12

R9401

12

C9401

1

2

R9494

1

2

R9495

1

2

C9498

1

2

C9499

1

2

R9441

1

2

L9498

12

L9499

12

R9425

1

2

C9486

1

2

C9485

1

2

C9481

1

2

C9480

1

2

C9487

1

2

Q9426

2

5

631

4

R9430

1

2

R9426

1

2

R9432

1

2

R9429

1

2

R9427

1

2

R9428

1

2

Q9430

3

5

4

Q9430

6

2

1

R9452

1

2

R9451

1

2

C9494

1

2

C9495

1

2

R9498

1

2

R9499

1

2

R9416

1

2

Q9419

5

3

4

R9418

12

Q9419

6

2

1

Q9415

3

1

2

R9419

12

U9426

4

2

3

5

1

Q9425

23

1

4

C9429

1

2

C9426

1

2

U9435

4

2

3

5

1

C9435

1

2

R9435

1

2

R9433

1

2

R9410

1

2

C9410

1

2

C9411

1

2

D9499

12

D9498

12

R9470

1

2

C9472

12

R9471

1

2

R9472

1

2

R9473

1

2

C9473

12

C9470

12

C9471

12

R9408

12

R9490

1

2

C9490

12

D9410

12

C9424

12

R9424

1

2

D9425

12

R9436

1

2

R9437

1

2

C9436

1

2

U9410

9

16 15

5

13

14

8

76

17

1 2 3 4

10 11 12

C9405

12

R9412

1

2

R9411

1

2

C9406

12

R9405

12

R9406

12

J9400

18

16

4 6

20

1

713

814

2

21222324252627

28

5

3

11

9

17

15

12

10

19

U9480

4

2

5

3

1

94 OF 109

3.13.0

051-8870

65 OF 75

72

7

36 64 65

8

64 65

7

64

72

36 64 65

VDDIO

VIN

VLDO

SW_0 SW_1

FB

OUT3

OUT2

OUT1

OUT4 OUT5 OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

D

SG

D

SG

OUT

IN

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

see spec for others

Fpwm=9.62kHz

PPBUS S0 LCDBkLT FET

Addr: 0x58(Wr)/0x59(Rd)

(EEPROM should set EN_I_RES=1)

I_LED=369/Riset

measurement on LED strings.

10.2 ohm resistors for current

AND PPBUS_SW_BKL

THERE IS A SENSE RESISTOR BETWEEN

LOADING

0.65 A (EDP)

P-TYPE

MOSFET

CHANNEL

FDC638APZ

43 mOhm @4.5V

RDS(ON)

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

I_LED=20.3mA

ON THE SENSOR PAGE

*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

PPBUS_SW_LCDBKLT_PWR

10UF

10%

CRITICAL

X5R

50V

1210-1

PLACE_NEAR=D9701.2:5mm

PLACE_NEAR=D9701.2:3mm

X5R

CRITICAL

50V

10%

10UF

1210-1

PIMB053T-SM

15UH-2.8A

CRITICAL

LP8550

25-BUMP-MICRO

25

8

SSM6N15FEAPE

SOT563

201

1/20W

MF

147K

1%

SSM6N15FEAPE

SOT563

BOTTOM

3AMP-32V-467

603-HF

201

1/20W

MF

301K

1%

X5R

402

0.1UF

16V

10%

SSOT6-HF

FDC638APZ_SBMS001

CRITICAL

PLACE_NEAR=C9797.1:5mm

SM

18.2K

1% 1/20W MF 201

MF

201

1%

1/20W

200K

MF

100K

201

1/20W

1%

1/20W

10K

MF

5%

201

0

MF

1/20W

201

5%

201

5%

1/20W

MF

0

33

201

MF

1/20W

5%

NP0-C0G

25V

5%

201

33PF

1%

MF

201

90.9K

1/20W

10K

5% 1/20W MF 201

0.1UF

6.3V

201

X5R

10%

PLACE_NEAR=U9701.C4:4mm

10% 10V

0.01UF

X5R 201

PLACE_NEAR=U9701.D1:3mm

PLACE_NEAR=L9701.1:3mm

25V

10%

X5R 805

10UF

CRITICAL

X5R

0.1UF

402

10% 25V

PLACE_NEAR=L9701.1:3mm

220PF

X7R-CERM

PLACE_NEAR=U9701.A5:3mm

402

50V

10%

CRITICAL

SOD-123

PLACE_NEAR=L9701.2:3mm

RB160M-60G

BOTTOM

PLACE_NEAR=U9701.E1:10mm

BKLT:PROD

402

5%

MF-LF

1/16W

0

BOTTOM

PLACE_NEAR=U9701.E2:10mm

BKLT:PROD

402

5%

MF-LF

1/16W

0

PLACE_NEAR=U9701.E3:10mm

BOTTOM

0

BKLT:PROD

1/16W MF-LF

5%

402

63

6

63

6

63

6

63

6

63

6

63

6

BOTTOM

PLACE_NEAR=U9701.D5:10mm

BKLT:PROD

1/16W

402

MF-LF

5%

0

BOTTOM

PLACE_NEAR=U9701.C5:10mm

0

5%

402

MF-LF

1/16W

BKLT:PROD

BOTTOM

PLACE_NEAR=U9701.E5:10mm

BKLT:PROD

MF-LF

402

5%

1/16W

0

1UF

PLACE_NEAR=U9701.D1:5mm

X5R

25V

10%

603-1

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

SM

8

44

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

103S0198

R9717,R9718,R9719

3

BKLT:ENG

103S0198

R9720,R9721,R9722

3

RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

BKLT:ENG

LCD Backlight Driver

SYNC_MASTER=K78_MLB

SYNC_DATE=01/16/2011

=PP5V_S0_BKL

=PPBUS_SW_BKL

LCDBKLT_EN_DIV

=PPBUS_S0_LCDBKLT

BKL_PWM

=PP3V3_S0_BKL_VDDIO

BKL_FSET

LCD_BKLT_PWM

=I2C_BKL_1_SDA BKL_SDA

=I2C_BKL_1_SCL

BKL_SCL

BKL_EN

PPBUS_SW_LCDBKLT_PWR

BKL_ISET

LCDBKLT_EN_L

BKLT_PLT_RST_L

LCD_BKLT_EN

LCDBKLT_DISABLE

MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_1

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_3

LED_RETURN_6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

PPBUS_SW_LCDBKLT_PWR

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5 MM

PPVOUT_SW_LCDBKLT

MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V

TP_BKL_FAULT

PLACE_SIDE=BOTTOM

MIN_LINE_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM

VOLTAGE=50V

PPVOUT_SW_LCDBKLT_FB

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

GND_BKL_SGND

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_SW_LCDBKLT_PWR_SW

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=50V SWITCH_NODE=TRUE DIDT=TRUE

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN5

BKL_VSYNC_R

BKL_FLTR

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN4

C9712

1

2

C9713

1

2

C9796

1

2

D9701

12

R9722

12

R9721

12

R9720

12

R9718

12

R9719

12

R9717

12

C9710

1

2

XW9710

12

C9799

1

2

C9797

1

2

L9701

12

U9701

A3

C3

A5

C2

B4

E4B5A1

A2

B3

E5

D5

C5

E3

E2

E1

A4

D3

D4

B1

B2

C4C1D1

D2

Q9707

3

5

4

R9789

1

2

Q9707

6

2

1

F9700

12

R9788

1

2

C9782

1

2

Q9706

1256

3

4

XW9720

12

R9714

1

2

R9731

12

R9715

1

2

R9741

12

R9753

12

R9757

12

R9704

12

C9704

1

2

R9716

1

2

R9755

1

2

C9711

1

2

C9714

1

2

97 OF 109

3.13.0

051-8870

66 OF 75

7

8

7

66

8

66

8

63

6

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

NOTE: CPU_XDP_BPM physical constraint is to prevent routing on outer layers.

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7

Some signals require 27.4-ohm single-ended impedance.

PCI-Express

Most CPU signals with impedance requirements are 50-ohm single-ended.

SOURCE: Huron River SFF DG (DG-438297_v1.0), Section 4.18 and Huron River Platform Power Delivery DG v1.0 Section 2.7

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

CPU Net Properties

(FSB_CPURST_L)

NET_TYPE

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

CPU_VCCSA_VID<0>

CPU Signal Constraints

CPU_VCCSA_VID<1>

SYNC_MASTER=K21_CONSTRAINTS

SYNC_DATE=04/06/2011

CPU Constraints

=2x_DIELECTRIC

CPU_AGTL

TOP,BOTTOM

?

=CPU_50S=CPU_50S=CPU_50S =CPU_50S =CPU_50S=CPU_50S

CPU_XDP_BPM

*

=STANDARD

100 MIL

=STANDARD

100 MIL100 MIL100 MIL

TOP,BOTTOM

CPU_XDP_BPM

=27P4_OHM_SE

CPU_27P4S

*

=27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE

7 MIL 7 MIL

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

CPU_55S

=STANDARD =STANDARD

=50_OHM_SE =50_OHM_SE=50_OHM_SE

CPU_50S

*

=50_OHM_SE

PCIE_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

CLK_PCIE_90D

*

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

CLK_PCIE

*

20 MIL

?

PCIE

*

=3X_DIELECTRIC

?

PCIE

TOP,BOTTOM

=4X_DIELECTRIC

?

*

CPU_ITP

=2:1_SPACING

?

CPU_VCCSENSE

*

25 MIL

?

CPU_COMP

*

20 MIL

?

CPU_AGTL

*

=STANDARD

?

CPU_8MIL

*

8 MIL

?

PEG_R2D_N<15..0>

PCIEPCIE_85D

PEG_R2D_C_P<15..0>

PCIEPCIE_85D

PEG_R2D_C_N<15..0>

PCIEPCIE_85D

CPU_VIDSOUT

CPU_SVIDSOUT CPU_COMP

CPU_50S

CPU_VIDSCLK

CPU_SVIDSCLK CPU_COMP

CPU_50S

CPU_VIDALERT_L

CPU_SVIDALERT_L

CPU_COMP

CPU_50S

CPU_VCCSENSE

CPU_VCC_VALSENSE_N

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VDDQ_SENSE_N

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCAXG_SENSE

CPU_AXG_SENSE_N

CPU_VDDQ_SENSE_P

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCC_VALSENSE_P

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_AXG_VALSENSE_P

CPU_27P4S

CPU_VALSENSE

CPU_VCCSENSE

CPU_27P4S

CPU_VCCAXG_SENSE

CPU_AXG_SENSE_P

CPU_VCCSENSECPU_VCCSENSE

CPU_27P4S

CPU_VCCIOSENSE_N

CPU_VCCAXG_SENSE

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_27P4S

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCAXG_SENSE

PEG_D2R_N<15..0>

PCIEPCIE_85D

PEG_D2R_P<15..0>

PCIEPCIE_85D

PEG_R2D_P<15..0>

PCIEPCIE_85D

PEG_D2R_C_P<15..0>

PCIEPCIE_85D

PEG_D2R_C_N<15..0>

PCIEPCIE_85D

FDI_FSYNC<1..0>

CPU_AGTL

CPU_50S

PM_SYNC

CPU_AGTL

CPU_50SPM_SYNC

PM_MEM_PWRGD

PM_MEM_PWRGD CPU_AGTL

CPU_50S

CPU_VCCSENSE

CPU_AXG_VALSENSE_N

CPU_VALSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCIOSENSE_P

CPU_VCCSENSE

CPU_27P4S

DMI_S2N_N<3:0>

PCIE

DMI_S2N

PCIE_85D

DMI_S2N_P<3:0>

PCIE

DMI_S2N

PCIE_85D

XDP_BPM_L<7..0>

CPU_XDP_BPM

CPU_ITP

XDP_BPM_L

XDP_TDO CPU_ITPCPU_50S

XDP_CPU_TDO

DMI_N2S_P<3:0>

PCIE

DMI_N2S

PCIE_85D

PCIE

DMI_N2S_N<3:0>

DMI_N2S

PCIE_85D

FDI_DATA_P<7:0>

PCIEPCIE_85DFDI_DATA

FDI_DATA_N<7:0>

FDI_DATA PCIEPCIE_85D

CPU_50S

FDI_LSYNC<1..0>

CPU_AGTL

CPU_50S

FDI_INT

CPU_AGTL

CPU_PECI

PCIE

CPU_50S

EDP_COMP

CPU_COMP

CPU_27P4S

ITPXDP_CLK100M_N

CLK_PCIECLK_PCIE_90D

ITPCPU_CLK100M ITPCPU_CLK100M

CLK_PCIE

XDP_CPU_CLK100M_P

CLK_PCIE_90D

ITPXDP_CLK100M_P

CLK_PCIECLK_PCIE_90D

ITPCPU_CLK100M

XDP_CPU_CLK100M_N

CLK_PCIE_90D CLK_PCIE

XDP_CPU_TDI

CPU_ITPCPU_50SXDP_TDI

CPU_ITPCPU_50S

XDP_CPU_PREQ_L

DPLL_REF_CLKP

CLK_PCIECLK_PCIE_90D

DPLL_REF_CLK120M

DPLL_REF_CLKN

CLK_PCIE_90D CLK_PCIE

DPLL_REF_CLK120M

CPU_50S

XDP_DBRESET_L

CPU_ITP

CPU_50S

CPU_VCCIO_SEL

CPU_AGTL

CPU_AGTLCPU_CATERR_L

CPU_CATERR_L

CPU_50S

CPU_ITP

CPU_CFG<11..0>

CPU_50S

CPU_27P4S

CPU_COMP

CPU_SM_RCOMP<2>

CPU_SM_RCOMP

CPU_SM_RCOMP<0>

CPU_COMP

CPU_27P4S

CPU_50S

CPU_AGTL

PM_EXT_TS_L<0>

CPU_PWRGD

CPU_AGTL

CPU_PWRGD

CPU_50S

ITPCPU_CLK100M_P

CLK_PCIE_90D CLK_PCIE

ITPCPU_CLK100M

ITPCPU_CLK100M_N

CLK_PCIE_90D CLK_PCIE

ITPCPU_CLK100M

DMI_CLK100M_CPU_N

DMI_CLK100M

CLK_PCIE_90D CLK_PCIE

CPU_ITP

XDP_CPU_PRDY_L

CPU_50S

CPU_27P4S

CPU_COMP

CPU_PEG_COMP

CPU_50S

CPU_PROCHOT_L

CPU_AGTL

CPU_PROCHOT_L

CPU_AGTL

PM_EXT_TS_L<1>

CPU_50S

XDP_CPURST_L

CPU_50S CPU_ITP

CPU_CFG<15..12>

XDP_BPM_R_L

CPU_ITPCPU_50S

XDP_CPU_TRST_L

CPU_ITPCPU_50S

XDP_TRST_L

XDP_CPU_TCK

XDP_TCK CPU_ITPCPU_50S

XDP_CPU_TMS

CPU_ITPXDP_TMS CPU_50S

DMI_CLK100M_CPU_P

CLK_PCIE

DMI_CLK100M

CLK_PCIE_90D

PM_THRMTRIP_L

CPU_8MIL

CPU_50S

PM_THRMTRIP_L

CPU_SM_RCOMP CPU_COMP

CPU_SM_RCOMP<1>

CPU_27P4S

100 OF 109

3.13.0

051-8870

67 OF 75

8

57 12

9

12

57 12

12

9

57 12

59 12

57 12

8

17

9

17 10

26 17 10

9

59 12

9

17

9

17

23 10

9

17

9

17

9

17

9

17

9

17

9

41 19 10

9

23 16

23

16 23

23

10 23

23 10

16 10

25 23 10

12

10

9

23

10

19 10 23

10 16

10 23

9

42 10 57

23

9

23 10

10 23

10 16

10 19

10

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEMTABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Memory to GND Spacing

Memory Bus Spacing Group Assignments

ELECTRICAL_CONSTRAINT_SET

Need to support MEM_*-style wildcards!

SOURCE: Huron River Platform DG, Rev 1.01 (#436735), Section 2.5

SPACING

Memory Net Properties

PHYSICAL

NET_TYPE

per Huron River SFF DG rev1.0 (#438297).

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

DQ to DQS matching per byte lane should be within 0.127mm.

DQS to clock matching should be within [CLK-63.5mm] and [CLK+38.1mm].

DDR3:

Maximum length of any signal from die pad to SODIMM pad is 119.83mm, from procesor ball to SODIMM pad is 88.9mm.

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs A/BA/CMD signals to each other should match within 5.08mm.

CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0.0mm] of CLK pairs.

Sandybridge SFF 2C when routed on Type-3 (Through hole) should follow rPGA guidelines

Memory Bus Constraints

Memory to Power Spacing

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.0508mm.

Spacing Rule Sets

MEM_2GND

GND

MEM_DQS

*

MEM_CMD2CTRL

MEM_CTRL

MEM_CMD

*

MEM_CMD2CMD

MEM_CMDMEM_CMD

*

MEM_DATAMEM_DATA

*

MEM_DATA2DATA

MEM_MEM2OTHERMEM

MEM_DQS

MEM_DATA

*

MEM_2OTHER

**

MEM_CLK

MEM_2OTHER

**

MEM_CTRL

MEM_2OTHER

**

MEM_CMD

MEM_PWR

MEM_DATA MEM_2PWR

*

* ?

=PWR_P2MM

MEM_2PWR

*

0.6 MM

?

MEM_2OTHER

*

MEM_2GND

?

=GND_P2MM

MEM_CLK2CLK

*

MEM_CLK MEM_CLK

MEM_MEM2OTHERMEM

MEM_DATA

*

MEM_CLK

MEM_CMD2CTRL

*

MEM_CTRL

MEM_CMD

*

MEM_CTRL2CTRL

MEM_CTRL MEM_CTRL

MEM_MEM2OTHERMEM

*

MEM_CTRL

MEM_CLK

MEM_PWR

*

MEM_2PWR

MEM_DQS

MEM_DQS2DQS

MEM_DQSMEM_DQS

* *

MEM_2OTHER

*

MEM_DQS

**

MEM_DATA

MEM_2OTHER

MEM_PWR

MEM_CTRL MEM_2PWR

*

TOP,BOTTOM

Y

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

MEM_85D

=85_OHM_DIFF =85_OHM_DIFF

=STANDARD

=50_OHM_SE

MEM_50S

=STANDARD

ISL3,ISL4,ISL9,ISL10

=50_OHM_SE =50_OHM_SE

Y

TOP,BOTTOM

MEM_50S

Y

=50_OHM_SE

=STANDARD =STANDARD

=50_OHM_SE=50_OHM_SE

=72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF

*

MEM_72D

MEM_40S

*

=40_OHM_SE =40_OHM_SE

=STANDARD =STANDARD

=40_OHM_SE=40_OHM_SE

MEM_37S

=37_OHM_SE =37_OHM_SE=37_OHM_SE

=STANDARD=STANDARD

=37_OHM_SE

*

MEM_MEM2OTHERMEM

MEM_CLK

*

MEM_CMD

MEM_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

=STANDARD =STANDARD

ISL3,ISL4,ISL9,ISL10

MEM_85D

Y

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

MEM_MEM2OTHERMEM

MEM_DQS

MEM_DATA

*

MEM_MEM2OTHERMEM

MEM_DQS MEM_CMD

*

MEM_MEM2OTHERMEM

*

MEM_DQS

MEM_CTRL

MEM_DATA MEM_2GND

GND

*

MEM_CTRL MEM_2GND

GND

*

MEM_PWR

MEM_2PWR

MEM_CLK

*

MEM_MEM2OTHERMEM

*

MEM_DQS MEM_CLK

MEM_MEM2OTHERMEM

*

MEM_CTRL

MEM_DQS

MEM_MEM2OTHERMEM

*

MEM_CTRL MEM_DATA

MEM_MEM2OTHERMEM

MEM_CMD

*

MEM_DATA

MEM_MEM2OTHERMEM

MEM_CTRLMEM_DATA

*

MEM_MEM2OTHERMEM

MEM_DATA

MEM_CLK

*

MEM_MEM2OTHERMEM

MEM_CMD

*

MEM_DATA

MEM_MEM2OTHERMEM

MEM_CMD MEM_DQS

*

MEM_MEM2OTHERMEM

MEM_CLK MEM_DQS

*

MEM_MEM2OTHERMEM

*

MEM_CMDMEM_CLK

MEM_MEM2OTHERMEM

MEM_CTRL

*

MEM_CLK

MEM_CMD

MEM_2GND

GND

*

MEM_CMD MEM_PWR

MEM_2PWR

*

GND

MEM_2GND

MEM_CLK

SYNC_DATE=04/06/2011

SYNC_MASTER=K21_CONSTRAINTS

Memory Constraints

MEM_CLK2CLK

*

0.6 MM

?

*

0.2 MM

MEM_CTRL2CTRL

?

*

0.2 MM

MEM_CMD2CMD

?

MEM_CMD2CTRL

?*

0.2 MM

*

0.14 MM

MEM_DATA2DATA

?

MEM_MEM2OTHERMEM

*

0.4 MM

?

0.4 MM

MEM_DQS2DQS

*

MEM_B_DQ_BYTE4

MEM_DATA

MEM_50S

MEM_B_DQ<39..32>

MEM_B_DQ_BYTE0

MEM_DATA

MEM_B_DQ<7..0>

MEM_50S

MEM_B_RAS_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_BA<2..0>

MEM_B_CMD

MEM_CMDMEM_55S

MEM_CMD

MEM_B_CMD

MEM_55S

MEM_B_CAS_L

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_DATA

MEM_50S

MEM_85D MEM_DQS

MEM_B_DQS_N<0>

MEM_B_DQS0

MEM_DQSMEM_85D

MEM_B_DQS1

MEM_B_DQS_N<1>

MEM_DQSMEM_85D

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_DQS

MEM_B_DQS3

MEM_85D

MEM_B_DQS_N<3>

MEM_B_DQS5

MEM_85D MEM_DQS

MEM_B_DQS_P<5>

MEM_DQS

MEM_B_DQS6

MEM_85D

MEM_B_DQS_P<6>

PP1V5_S3RS0

MEM_PWR MEM_PWR

PP1V5_S3

MEM_CLK

MEM_B_CLK

MEM_B_CLK_N<5..0>

MEM_72D

MEM_A_CMD

MEM_CMD

MEM_A_RAS_L

MEM_55S

MEM_A_CMD

MEM_CMD

MEM_A_BA<2..0>

MEM_55S

MEM_CTRL

MEM_A_ODT<3..0>

MEM_A_CTRL

MEM_55S

MEM_DQS

MEM_B_DQS2

MEM_85D

MEM_B_DQS_N<2>

MEM_DQSMEM_85D

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_B_CMD

MEM_CMD

MEM_B_A<15..0>

MEM_55S

MEM_DQS

MEM_A_DQS6

MEM_A_DQS_N<6>

MEM_85D

MEM_DQS

MEM_A_DQS3

MEM_A_DQS_N<3>

MEM_85D

MEM_DQS

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_85D

MEM_DQS

MEM_A_DQS1

MEM_A_DQS_P<1>

MEM_85D

MEM_DQS

MEM_B_DQS7

MEM_85D

MEM_B_DQS_P<7>

MEM_DQSMEM_85D

MEM_B_DQS6

MEM_B_DQS_N<6>

MEM_B_CTRL

MEM_B_CKE<3..0>

MEM_CTRL

MEM_55S

MEM_B_DQ_BYTE5

MEM_DATA

MEM_50S

MEM_B_DQ<47..40>

MEM_DATA

MEM_50S

MEM_B_DQ<55..48>

MEM_B_DQ_BYTE6

MEM_DATA

MEM_50S

MEM_B_DQ<63..56>

MEM_B_DQ_BYTE7

MEM_85D

MEM_B_DQS_P<0>

MEM_B_DQS0

MEM_DQS

MEM_B_DQS4

MEM_85D MEM_DQS

MEM_B_DQS_P<4>

MEM_B_DQS4

MEM_DQSMEM_85D

MEM_B_DQS_N<4>

MEM_85D MEM_DQS

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_PWR

PP0V75_S3_MEM_VREFDQ_A

MEM_PWR

PP0V75_S3_MEM_VREFCA_A

MEM_85D MEM_DQS

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_DQS

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_85D

MEM_DATA

MEM_A_DQ<31..24>

MEM_A_DQ_BYTE3 MEM_50S

MEM_A_CTRL

MEM_CTRL

MEM_A_CKE<3..0>

MEM_55S

MEM_CTRL

MEM_A_CS_L<3..0>

MEM_A_CTRL

MEM_55S

MEM_A_CLK

MEM_CLKMEM_72D

MEM_A_CLK_P<5..0>

MEM_A_CLK

MEM_CLK

MEM_A_CLK_N<5..0>

MEM_72D

MEM_DATA

MEM_A_DQ<47..40>

MEM_A_DQ_BYTE5 MEM_50S

MEM_DATA

MEM_A_DQ<23..16>

MEM_A_DQ_BYTE2 MEM_50S

MEM_DATA

MEM_A_DQ<15..8>

MEM_A_DQ_BYTE1 MEM_50S

MEM_DATA

MEM_A_DQ<39..32>

MEM_A_DQ_BYTE4 MEM_50S

MEM_DATA

MEM_A_DQ<55..48>

MEM_A_DQ_BYTE6 MEM_50S

MEM_DATA

MEM_A_DQ<63..56>

MEM_A_DQ_BYTE7 MEM_50S

MEM_DQS

MEM_A_DQS0

MEM_A_DQS_P<0>

MEM_85D

MEM_A_DQS0

MEM_A_DQS_N<0>

MEM_DQSMEM_85D

MEM_DQS

MEM_A_DQS1

MEM_A_DQS_N<1>

MEM_85D

MEM_DQS

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_85D

MEM_DQS

MEM_A_DQS2

MEM_A_DQS_N<2>

MEM_85D

MEM_DQS

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_85D

MEM_DQS

MEM_A_DQS4

MEM_A_DQS_N<4>

MEM_85D

MEM_DQS

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_85D

MEM_DQS

MEM_A_DQS5

MEM_A_DQS_N<5>

MEM_85D

MEM_DQS

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_85D

MEM_DQS

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_85D

MEM_B_CLK

MEM_CLK

MEM_B_CLK_P<5..0>

MEM_72D

MEM_CTRL

MEM_B_CTRL

MEM_B_CS_L<3..0>

MEM_55S

MEM_CTRL

MEM_B_CTRL

MEM_B_ODT<3..0>

MEM_55S

MEM_B_CMD

MEM_CMD

MEM_B_WE_L

MEM_55S

MEM_B_DQ_BYTE2

MEM_DATA

MEM_B_DQ<23..16>

MEM_50S

MEM_B_DQ_BYTE3

MEM_DATA

MEM_50S

MEM_B_DQ<31..24>

MEM_A_CMD

MEM_CMD

MEM_A_A<15..0>

MEM_55S

MEM_CMD

MEM_A_CAS_L

MEM_A_CMD

MEM_55S

MEM_CMD

MEM_A_WE_L

MEM_A_CMD

MEM_55S

MEM_DATA

MEM_50S

MEM_A_DQ<7..0>

MEM_A_DQ_BYTE0

MEM_B_DQS5

MEM_DQSMEM_85D

MEM_B_DQS_N<5>

101 OF 109

3.13.0

051-8870

68 OF 75

30 11

29 11

32 30 29 11

29 11

30 11

7

32 30 29 11

8

32 28 27 11

8

29 11

32 30 29 11

8

28 11

27 11

30 11

32 30 29 11

8

30 11

29 11

30 11

31 30 29 28 27

9

31 30 29 28 27

29 11

28 11

27 11

32 28 27 11

8

32 28 27 11

8

32 28 27 11

8

32 28 27 11

8

28 11

27 11

28 11

27 11

28 11

32 30 29 11

8

32 30 29 11

8

32 30 29 11

8

32 30 29 11

29 11

32 28 27 11

8

32 28 27 11

27 11

30 11

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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PHYSICAL

SPACING

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

NET_TYPE

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

USB 2.0 Interface Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

Digital Video Signal Constraints

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

ELECTRICAL_CONSTRAINT_SET

PCH Net Properties

SATA Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

USB

TOP,BOTTOM

=4x_DIELECTRIC

?

*

LVDS

?

=3x_DIELECTRIC

DISPLAYPORT

*

=3x_DIELECTRIC

?

LVDS

TOP,BOTTOM

=4x_DIELECTRIC

?

SATA_ICOMP

*

8 MIL

?

SATA

*

=4x_DIELECTRIC

?

USB

*

=2x_DIELECTRIC

?

*

USB_85D

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

SATA_90D

*

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

DP_85D

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

DISPLAYPORT

TOP,BOTTOM

=4x_DIELECTRIC

?

*

LVDS_90D

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

PCH_USB_RBIAS

*

=STANDARD

8 MIL 8 MIL

=STANDARD =STANDARD =STANDARD

SATA

TOP,BOTTOM

=3x_DIELECTRIC

?

PCH Constraints 1

SYNC_DATE=04/06/2011

SYNC_MASTER=K21_CONSTRAINTS

USB_85D

USB

USB_IR_N

USB_85D

USB

USB_EXTB_N

USB

USB_EXTC

USB_EXTC_P

USB_85D

USB

USB_EXTC_N

USB_85D

USB

USB_EXTA_N

USB_85D

USB_EXTA

USB_85D

USB

USB_EXTA

USB_EXTA_P

USB_EXTD

USB

USB_EXTD_P

USB_85D

USB

T29_A_RSVD_P

USB

USB_85D

T29_A_RSVD_N

USB_85D

USB

USB_CAMERA

USB_CAMERA_P

USB

USB_85D

USB_CAMERA_N

USB_85D

USB

USB_BT

USB_BT_P

USB_TPAD

USB

USB_TPAD_P

USB_85D

LVDS_90D LVDS

LVDS_IG_B_CLK_N

SATA_90D SATA

SATA_HDD_R2D_C_P

SATA_90D SATASATA_ODD_R2D

SATA_ODD_R2D_N

SATA_90D SATASATA_ODD_D2R

SATA_ODD_D2R_N

USB_85D

USB

USB_HUB1_UP

USB_HUB1_UP_P

USB_85D

USB

USB_HUB2_UP_N

USB

USB_EXTB

USB_EXTB_P

USB_85D

USB

USB_EXTD_N

USB_85D

USB

USB_SDCARD_N

USB_85D

USB

USB_BRCRYPT

USB_BRCRYPT_P

USB_85D

USB

USB_BRCRYPT_N

CLK_PCIE

FSB_CLK133M_PCH_P

CLK_PCIE_90D

CLK_PCIE

FSB_CLK133M_PCH_N

CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE

PCH_CLK96M_DOT_P

PCH_DIFFCLK_UNUSED_

USB_85D

USB

USB_HUB1_UP_N

USB

USB_HUB2_UP

USB_HUB2_UP_P

USB_85D

SATA_ICOMP

PCH_SATA_ICOMP

PCH_SATAICOMP

USB_EXTD

USB

USB_85D

USB_T29A_P

USB

USB_85D

USB_T29A_N

USB_85D

USB

USB_CAMERA

USB_CAMERA_CONN_P USB_CAMERA_CONN_N

USB_85D

USB

SATA

SATA_HDD_R2D_C_N

SATA_90D

SATA_90D SATASATA_ODD_R2D

SATA_ODD_R2D_P

SATA_90D SATASATA_ODD_D2R

SATA_ODD_D2R_P

SATA_90D SATA

SATA_HDD_R2D_RC_N

SATA_90D SATA

SATA_ODD_R2D_C_N

SATA_90D SATA

SATA_ODD_R2D_C_P

SATA_90D SATA

SATA_HDD_D2R_C_P

SATA

SATA_HDD_D2R_N

SATA_HDD_D2R SATA_90D

LVDS_90D LVDS

LVDS_IG_B_DATA_N<3..0>

LVDS_90D LVDS

LVDS_IG_B_DATA_P<3..0>

LVDS_90D LVDS

LVDS_IG_A_DATA_N<3>

LVDS_90D LVDS

LVDS_IG_A_DATA

LVDS_IG_A_DATA_N<2..0>

LVDS_90D LVDS

LVDS_IG_A_CLK

LVDS_IG_A_CLK_N

PCH_USB_RBIAS

CLK_PCIE

PCH_DIFFCLK_UNUSED_

PCIE_CLK100M_PCH_P

CLK_PCIE_90D

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH

DP_IG_AUX_CH_P

LVDS_90D LVDS

LVDS_IG_A_DATA

LVDS_IG_A_DATA_P<2..0>

LVDS_90D LVDS

LVDS_IG_A_DATA_P<3>

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH

DP_IG_AUX_CH_N

DP_85D

DISPLAYPORT

DP_ML

DP_IG_ML_N<3..0>

DP_85D

DISPLAYPORT

DP_ML

DP_IG_ML_P<3..0>

LVDS_90D LVDS

LVDS_IG_A_CLK

LVDS_IG_A_CLK_P

CLK_PCIE_90D CLK_PCIE

PCH_CLK96M_DOT_N

PCH_DIFFCLK_UNUSED_

CLK_PCIE_90D CLK_PCIE

GFX_CLK_DPLLSS

GFX_CLK120M_DPLLSS_N

CLK_PCIE_90D CLK_PCIE

GFX_CLK_DPLLSS

GFX_CLK120M_DPLLSS_P

CPU_50S

CLK_PCIE

LPC_CLK33M

PCH_CLK33M_PCIIN

CPU_50S

CLK_PCIE

PCH_CLK14P3M_REFCLK

CLK_PCIE_90D CLK_PCIE

PCH_DIFFCLK_UNUSED_

PCH_CLK100M_SATA_N

CLK_PCIE_90D CLK_PCIE

PCH_DIFFCLK_UNUSED_

PCH_CLK100M_SATA_P

CLK_PCIE

PCH_DIFFCLK_UNUSED_

PCIE_CLK100M_PCH_N

CLK_PCIE_90D

USB_BT

USB_85D

USB

USB_BT_N

SATA_90D

SATA_HDD_D2R_C_N

SATA

SATA_90D SATASATA_HDD_D2R

SATA_HDD_D2R_P

SATA

SATA_HDD_R2D_N

SATA_90DSATA_HDD_R2D

SATA

SATA_HDD_R2D_P

SATA_90DSATA_HDD_R2D

LVDS_90D LVDS

LVDS_IG_B_CLK_P

USB_85D

USB

USB_SDCARD

USB_SDCARD_P

USB_85D

USB

USB_IR

USB_IR_P

USB_TPAD_N

USB_85D

USB

SATA_90D SATA

SATA_HDD_D2R_RC_N

SATA_90D SATA

SATA_HDD_R2D_RC_P

SATASATA_90D

SATA_HDD_D2R_RC_P

102 OF 109

3.13.0

051-8870

69 OF 75

39 24

40 24

6

64

8

64

8

40 18

6

40 18

6

37 24

6

49

8

38 16

16

8

24 18

40 24

6

33 24

8

25 16

24 18

16

24

8

24

8

38 16

16

8

16

8

16

8

38

6

38 16

8

18

25 16

8

25 16

37 24

6

38

6

38 16

38

6

38

6

8

33 24

49

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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87 54 21

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SMBus Interface Constraints

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

Chipset Net Properties

HD Audio Interface Constraints

SPI Interface Constraints

DisplayPort Signal Constraints

PCI-Express Signal Constraints

NET_TYPE

PHYSICAL

PCH Net Properties

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

SIO Signal Constraints

Clock Net Properties

SPACING

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

System Clock Signal Constraints

NOTE: 25MHz system clocks very sensitive to noise.

LPC Bus Constraints

SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

?

=2x_DIELECTRIC

*

SMB

?

8 MIL

SPI

*

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

DP_85D

*

?

=3x_DIELECTRIC

DISPLAYPORT

*

?

=4X_DIELECTRIC

TOP,BOTTOM

PCIE

=STANDARD=STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE

CLK_LPC_50S

=50_OHM_SE

*

8 MIL

?*

CLK_SLOW

?

=5x_DIELECTRIC

*

CLK_25M

?

20 MIL

*

CLK_PCIE

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

*

CLK_PCIE_90D

=STANDARD=STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

*

LPC_50S

?

=4x_DIELECTRIC

TOP,BOTTOM

DISPLAYPORT

=STANDARD=STANDARD

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

*

CLK_25M_55S

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

PCIE_85D

*

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

CLK_SLOW_55S

?

=2x_DIELECTRIC

*

CLK_SLOW

?

=2x_DIELECTRIC

HDA

*

=STANDARD=STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

SMB_50S

*

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

SPI_55S

?

=3X_DIELECTRIC

*

PCIE

=STANDARD=STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SE

*

HDA_50S

=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

CLK_SLOW_55S

=STANDARD

=55_OHM_SE

SYNC_MASTER=K21_CONSTRAINTS

SYNC_DATE=04/06/2011

PCH Constraints 2

?

8 MIL

CLK_LPC

*

?

6 MIL

*

LPC

PCIE_PEG_D2R_LANE0

PCIEPCIE_85D

PCIE_T29_D2R_P<0>

PCIE_PEG_D2R_LANE1

PCIEPCIE_85D

PCIE_T29_D2R_P<1>

PCIE_PEG_D2R_LANE2

PCIE_85D PCIE

PCIE_T29_D2R_P<2>

PCIE_PEG_D2R_LANE3

PCIEPCIE_85D

PCIE_T29_D2R_P<3>

PCIE_85D PCIE

PCIE_AP_R2D

PCIE_AP_R2D_C_P

PCIE_AP_R2D_N

PCIE_85D PCIE

PCIE_AP_D2R_P

PCIE_AP_D2R

PCIE_AP_D2R_N

PCIE_85D PCIE

CONN_PCIE_AP_D2R_N

PCIE_85D PCIE

CONN_PCIE_AP_R2D_P

PCIE_85D PCIE

PCIE_AP_R2D

CONN_PCIE_AP_R2D_N

PCIEPCIE_85D

PCIE_CLK100M_ENET_P

CLK_PCIE_90D

PCIE_CLK100M_ENET

CLK_PCIE

PCIEPCIE_85D

PCIE_PEG_D2R_LANE2

PCIE_T29_D2R_N<2>

PCIEPCIE_85D

PCIE_PEG_D2R_LANE3

PCIE_T29_D2R_N<3>

PCIE_85D PCIE

PCIE_T29_R2D_N<0>

PCIE_PEG_R2D_LANE0

HDA

HDA_BIT_CLK_R

HDA_50S

HDA_SYNC

HDA

HDA_50S

HDA_SYNC

HDA

HDA_50S

HDA_SYNC_R

LPC_AD<3..0>

LPC_AD

LPC

LPC_50S

LPC_RESET_L

LPC

LPC_50S

LPC_RESET_L

SPI_MLB_MISO

SPI

SPI_55S

SPI

SPI_MLB_MOSI

DP_EXTA_AUXCH

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH_C_N

DISPLAYPORT

DP_EXTA_AUXCH_P

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH_N

DP_85D

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_T29

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_T29_R

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_ENET_R

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_ENET

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_SB_R

SYSCLK_CLK32K_RTC

CLK_SLOWCLK_SLOW_55S

SYSCLK_CLK32K_RTC

CLK_25M

CLK_25M_55S

SYSCLK_CLK25M_SB

CLK_PCIE

PCIE_CLK100M_T29

PCIE_CLK100M_T29_N

CLK_PCIE_90D

DP_INT_AUX_CH_C_P

DISPLAYPORT

DP_85D

DP_INT_AUXCH

DP_INT_ML_F_N<3..0>

DISPLAYPORT

DP_85D

DP_INT_ML_F_P<3..0>

DISPLAYPORT

DP_85D

DISPLAYPORT

DP_INT_ML_P<3..0>

DP_85D

DP_INT_ML

DP_85D

DISPLAYPORT

DP_INT_ML_C_N<3..0>

DP_INT_ML

DP_85D

DISPLAYPORT

DP_INT_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_EXTA_AUXCH

DP_EXTA_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_EXTA_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_EXTA_ML_P<3..0>

CPU_27P4S

PCH_VSS_NCTF<9>

CPU_COMP

PCH_VSS_NCTF<9>

CPU_COMP

CPU_27P4S

CPU_COMP

CPU_27P4S

TP_PCH_VSS_NCTF<7>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<5>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<1>

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_EXCARD_N

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<2>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<11> PCH_VSS_NCTF<12>

CPU_27P4S

CPU_COMP

PCH_VSS_NCTF<29>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<27>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<25>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<22>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<21>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<17>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<15>

CPU_COMP

CPU_27P4S

PCH_VSS_NCTF<19>

CPU_COMP

CPU_27P4S

PCIE_CLK100M_EXCARD_P

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_FW_N

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_AP_N

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_FW_P

CLK_PCIECLK_PCIE_90D

MCP_PE2_REFCLK

PCIE_CLK100M_AP_P

CLK_PCIE_90D CLK_PCIE

MCP_PE1_REFCLK

CLK_PCIE_90D

PEG_CLK100M_N

CLK_PCIE

PEG_CLK100M_P

CLK_PCIE_90D CLK_PCIE

CONN_PCIE_AP_D2R_P

PCIEPCIE_85D

PCIE_AP_D2R

PCIE_85D

PCIE_FW_D2R_N

PCIE

PCIE_FW_R2D_C_N

PCIE_85D PCIE

PCIE_FW_R2D_C_P

PCIE_85D PCIE

PCIE_FW_R2D

PCIE_FW_R2D_N

PCIE_85D PCIE

PCIE_FW_R2D_P

PCIE_85D PCIE

PCIE_AP_R2D_C_N

PCIE_ENET_R2D_C_N

PCIE_85D PCIE

PCIE_ENET_D2R_P

PCIEPCIE_85D

PCIE_ENET_D2R

PCIE_ENET_R2D_C_P

PCIE_85D PCIE

PCIE_ENET_R2D

HDA

HDA_50S

HDA_RST_L

HDA_RST_R_L

PM_SUS_CLK

CLK_SLOWCLK_SLOW_55S

PM_CLK32K_SUSCLK

DP_EXTA_ML

DISPLAYPORT

DP_85D

DP_EXTA_ML_C_P<3..0>

SMBUS_PCH_1_CLK

SMB

SMB_50S

SML_PCH_1_CLK

SMB

SMB_50S

SML_PCH_0_CLK

SMBUS_PCH_0_CLK

SMBUS_PCH_DATA

SMB

SMB_50S

LPC_CLK33M

CLK_LPC

LPC_CLK33M_SMC

CLK_LPC_50S

LPC_CLK33M_LPCPLUS

LPC_CLK33M

CLK_LPC

CLK_LPC_50S

SMBUS_PCH_CLK

SMB

SMB_50S

DP_INT_AUX_CH_C_N

DP_85D

DISPLAYPORT

DP_INT_AUXCH

HDA_BIT_CLK

HDA

HDA_BIT_CLK

HDA_50S

SMB

SMB_50S

SML_PCH_1_DATA

SMBUS_PCH_1_DATA

PCIE_CLK100M_ENET_N

CLK_PCIE_90D CLK_PCIE

PCIE_PEG_D2R_LANE1

PCIEPCIE_85D

PCIE_T29_D2R_N<1>

PCIE_T29_R2D_P<1>

PCIE

PCIE_PEG_R2D_LANE1

PCIE_85D

PCIE_85D PCIE

PCIE_T29_D2R_C_P<3..0>

PCIE_FW_D2R_P

PCIE_85D PCIE

PCIE_FW_D2R

PCIE_FW_D2R_C_P

PCIE_85D PCIE

PCIE_FW_D2R_C_N

PCIEPCIE_85D

LPC_CLK33M_SMC_R

LPC_CLK33M

CLK_LPC

CLK_LPC_50S

LPC_FRAME_L

LPC

LPC_50S

LPC_FRAME_L

PCIE_ENET_D2R_N

PCIE_85D PCIE

PCIE_ENET_D2R_C_P

PCIE_85D PCIE

PCIE_ENET_D2R_C_N

PCIE_85D PCIE

PCIE_AP_R2D_P

PCIEPCIE_85D

HDA_SDOUT_R

HDA

HDA_50S

SPI_MLB_CLK

SPI

SPI_55S

SPI_MOSI

SPI

SPI_55S SPI_55S

SPI

SPI_MISO

DP_EXTA_ML

DISPLAYPORT

DP_85D

DP_EXTA_ML_C_N<3..0>

DP_INT_ML_N<3..0>

DISPLAYPORT

DP_85D

HDA

HDA_50S

AUD_SDI_R

HDA_SDIN0

HDA_50S

HDA

HDA_50S

HDA_RST_L

SML_PCH_0_DATA

SMBUS_PCH_0_DATA

SMB_50S

SMB

PCIE

PCIE_T29_R2D_N<3>

PCIE_PEG_R2D_LANE3

PCIE_85D

PCIE_T29_R2D_P<0>

PCIE

PCIE_PEG_R2D_LANE0

PCIE_85D

PCIE_T29_R2D_P<2>

PCIE

PCIE_PEG_R2D_LANE2

PCIE_85D

PCIE

PCIE_T29_R2D_P<3>

PCIE_PEG_R2D_LANE3

PCIE_85D

PCIE

PCIE_PEG_D2R_LANE0

PCIE_T29_D2R_N<0>

PCIE_85D

DP_85D

DP_INT_AUX_CH_P

DISPLAYPORT

DP_85D

DP_INT_AUX_CH_N

DISPLAYPORT

PCIE

PCIE_T29_R2D_C_P<3..0>

PCIE_85D

PCIE

PCIE_T29_R2D_C_N<3..0>

PCIE_85D

SPI_55S

SPI

SPI_CS0

SPI_CS0_R_L

SPI_55S

SPI

SPI_CS0_L

SPI

SPI_55S

SPI_MLB_CS_L

PCIE_ENET_R2D_P

PCIEPCIE_85D

PCIE_ENET_R2D_N

PCIE_85D PCIE

CLK_PCIE

PCIE_CLK100M_T29

PCIE_CLK100M_T29_P

CLK_PCIE_90D

PCIE

PCIE_T29_D2R_C_N<3..0>

PCIE_85D

PCIE

PCIE_T29_R2D_N<1>

PCIE_85D

PCIE_PEG_R2D_LANE1

PCIE

PCIE_T29_R2D_N<2>

PCIE_85D

PCIE_PEG_R2D_LANE2

SPI

SPI_MOSI

SPI_MOSI_R

SPI_55S

SPI

SPI_CLK

SPI_CLK_R

SPI

SPI_CLK

SPI_55S

HDA_SDOUT

HDA_50S

HDA

103 OF 109

3.13.0

051-8870

70 OF 75

8

34

8

34

8

37 16

37

6

37 16

6

37 16

6

34

8

34

8

34

16

40 16

6

16

43 41 16

6

25

50 43

64

8

64

34 25

34

16

25 16

34 16

63

6

63

6

63

6

63

9

63

64

8

64

70

6

70

6

16

8

6

16

8

37 16

6

37 16

6

16

8

16

8

37 16

16

64

8

44 16

41 25

43 25

6

44 16

63

6

40 16

6

44 16

34

8

34

25 18

43 41 16

6

37

6

16

50 43

43

43 16

64

8

63

9

40 16

6

40 16

6

44 16

34

8

63

9

63

9

34

8

34

8

43 16

43

50 43

34 16

34

43 16

43

40 16

6

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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BRANCH

REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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87 54 21

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

SOURCE: Broadcom 5764-DS04-RDS Page 38

FireWire Interface Constraints

CAESAR IV (Ethernet) Constraints

ELECTRICAL_CONSTRAINT_SET

Ethernet Net Properties

SOURCE: Broadcom 5764-DS04-RDS Page 38

CAESAR IV (Ethernet PHY) Constraints

SPACING

PHYSICAL

NET_TYPE

SPACING

NET_TYPE

PHYSICAL

Port 2 Not Used

FireWire Net Properties

I158

I159

I160

I161

I162

I163

I164

I165

I166

I167

I168

I169

I170

I171

=3:1_SPACING

*

FW_TP

?

*

FW_110D

=110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF=110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF

*

ENET_MDI

0.6 MM

?

*

ENET_100D

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

ENET_CR_DATA

*

8MIL

?

*

ENET_3X

=3:1_SPACING

?

*

=50_OHM_SE

ENET_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD=STANDARD

Ethernet/FW Constraints

SYNC_MASTER=K21_CONSTRAINTS

SYNC_DATE=04/06/2011

ENET_50S ENET_CR_DATA

CR_DATA

SDCONN_CMD

ENET_50S ENET_CR_DATA

CR_CLK

SDCONN_CLK

ENET_50S ENET_CR_DATA

CR_CLK

ENET_CR_CLK

ENET_100D

ENET_MDIENET_MDI

ENET_MDI_P<3..0>

ENET_50S

ENET_3X

ENET_RESET_L

ENET_100D

ENET_MDI

ENET_MDI_N<3..0>

FW_110D

FW_TP

FW_P0_TPA

FW_P0_TPA_P

FW_110D

FW_TP

FW_P0_TPA

FW_P0_TPA_N

FW_110D

FW_TP

FW_P0_TPB

FW_P0_TPB_P

FW_110D

FW_TP

FW_P1_TPA

FW_P1_TPA_P

FW_110D

FW_TP

FW_P1_TPA

FW_P1_TPA_N

FW_110D

FW_TP

FW_P1_TPB

FW_P1_TPB_P

FW_110D

FW_TP

FW_P1_TPB

FW_P1_TPB_N

FW_110D

FW_TP

FW_P0_TPB

FW_P0_TPB_N

ENET_50S

ENET_3X

BCM5764_CLK25M_XTALO

ENET_50S

ENET_3X

BCM5764_CLK25M_XTALI

ENET_50S ENET_CR_DATA

CR_DATA

ENET_CR_DATA<7..0>

ENET_50S ENET_CR_DATA

CR_DATA

ENET_CR_CMD

ENET_50S ENET_CR_DATA

CR_DATA

SDCONN_DATA<7..0>

104 OF 109

3.13.0

051-8870

71 OF 75

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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SIZE

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PAGE TITLE

C

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

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A

B

C

345678

D

B

87 54 21

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

T29 IC Net Properties

DisplayPort Signal Constraints

T29 I2C Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SET

T29 Net Properties

DP/T29 Connector Signal Constraints

SPACING

NET_TYPE

PHYSICAL

SOURCE: Bill Cornelius’s T29 Routing Notes

T29 SPI Signal Constraints

T29/DP Net Properties

I262

I263

I264

I265

I266

I267

I268

I269

I270

I271

I272

I273

I274

I275

I276

I277

I282

I283

I284

I285

I286

I287

I288

I289

I290

I291

I292

I293

I294

I295

I296

I297

I298

I299

I300

I301

I302

I303

I304

I305

I306

I307

I308

I309

I310

I311

I312

I313

I314

I315

I316

I317

I318

I319

I320

I321

I322

I323

I324

I325

I326

I327

I328

I329

SYNC_MASTER=K21_CONSTRAINTS

T29 Constraints

SYNC_DATE=04/06/2011

T29DP TOP,BOTTOM

=7x_DIELECTRIC

?*

T29DP

=5x_DIELECTRIC

?

T29DP_80D

*

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

T29DP_100D

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

*

T29_SPI =2x_DIELECTRIC

?

T29_SPI_55S

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

*

T29_I2C =2x_DIELECTRIC

?

*

T29_I2C_55S

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

DP_85D

DISPLAYPORT

DP_T29SNK1_ML_C_N<3..0>

DP_85D

DISPLAYPORT

DP_T29SNK1_ML_C_P<3..0>

T29_R2D0

T29DP_80D

T29DP

T29_R2D_P<0>

T29DP_80D

T29DP

T29_R2D1

T29_R2D_N<1>

T29DP_80D

T29DP

T29_D2R0

T29_D2R_C_P<0>

T29DP_80D

T29DPA_ML_N<3..0>

T29DP

T29DPA_ML_P<3..0>

T29DP_80D

T29DP

T29DPA_ML_ODD

T29DPA_ML_P<3>

T29DP

T29DP_80D

DP_SDRVA_AUXCH_C_N

DP_85D

DISPLAYPORT

DP_T29SNK1_ML

DP_T29SNK1_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_T29SNK1_ML

DP_T29SNK1_ML_N<3..0>

T29DP_80D

T29DP

T29_D2R_P<3..0>

T29DP_80D

T29DP

T29_R2D1

T29_R2D_P<1>

DP_85D

DISPLAYPORT

DP_T29SNK0_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DP_T29SNK0_ML

DP_T29SNK0_ML_P<3..0>

DP_85D

DISPLAYPORT

DP_T29SNK0_AUXCH_C_P

T29DP_80D

T29DP

T29_R2D_C_F_P<1..0>

DP_SDRVA_ML_EVEN

DP_SDRVA_ML_P<0>

T29DP_80D

T29DP

T29DP_80D

T29DP

T29_D2R_N<3..0>

T29_D2R_C_P<1>

T29DP_80D

T29DP

T29_D2R1

T29DP_80D

T29DP

T29_R2D0

T29_R2D_N<0>

T29DP_80D

T29DP

T29_R2D_C_F_N<1..0>

DP_SDRVA_AUXCH

T29DP_80D

T29DP

DP_SDRVA_AUXCH_P

DP_SDRVA_ML_N<0>

DP_SDRVA_ML_EVEN

T29DP_80D

T29DP

DP_SDRVA_ML_P<1>

DP_SDRVA_ML_ODD

T29DP_80D

T29DP

T29DP_80D

T29DP

DP_SDRVA_ML_R_P<3..0>

DP_SDRVA_ML_C_P<3..0>

T29DP_80D

T29DP

DP_85D

DISPLAYPORT

DP_T29SNK1_AUXCH_C_N

DP_85D

DISPLAYPORT

DP_T29SNK1_AUXCH

DP_T29SNK1_AUXCH_P

DP_85D

DISPLAYPORT

DP_T29SNK1_AUXCH

DP_T29SNK1_AUXCH_N

DP_85D

DISPLAYPORT

DP_T29SNK1_AUXCH_C_P

DP_85D

DISPLAYPORT

DP_T29SNK0_AUXCH

DP_T29SNK0_AUXCH_P

DP_85D

DISPLAYPORT

DP_T29SNK0_AUXCH

DP_T29SNK0_AUXCH_N

DP_85D

DISPLAYPORT

DP_T29SNK0_AUXCH_C_N

DP_85D

DISPLAYPORT

DP_T29SNK0_ML

DP_T29SNK0_ML_N<3..0>

DP_85D

DISPLAYPORT

DP_T29SNK0_ML_C_N<3..0>

DP_SDRVA_ML_ODD

DP_SDRVA_ML_N<3>

T29DP_80D

T29DP

DP_SDRVA_ML_EVEN

DP_SDRVA_ML_N<2>

T29DP

T29DP_80D

T29DPA_D2R1_AUXCH_P

T29DP_80D

T29DP

DP_SDRVA_ML_R_N<3..0>

T29DP_80D

T29DP

DP_SDRVA_ML_C_N<3..0>

T29DP_80D

T29DP

T29_D2R_C_N<0>

T29DP_80D

T29DP

T29_D2R0

T29_D2R_C_N<1>

T29DP_80D

T29DP

T29_D2R1

T29DPA_D2R1_AUXCH_N

T29DP

T29DP_80D

DP_SDRVA_AUXCH_C_P

T29DP_80D

T29DP

DP_SDRVA_ML_EVEN

T29DP_80D

T29DP

DP_SDRVA_ML_P<2>

DP_SDRVA_ML_N<1>

DP_SDRVA_ML_ODD

T29DP_80D

T29DP

DP_SDRVA_AUXCH

T29DP_80D

T29DP

DP_SDRVA_AUXCH_N

DP_SDRVA_ML_ODD

T29DP_80D

T29DP

DP_SDRVA_ML_P<3>

T29DPA_ML_ODD

T29DPA_ML_N<3>

T29DPA_ML_ODD

T29DPA_ML_N<1>

T29DPA_ML_ODD

T29DPA_ML_P<1>

DP_A_EXT_AUXCH_N

T29DP_80D

T29DP

DP_A_EXT_AUXCH

T29DPA_ML_C_N<3..0>

T29DP

T29DP_80D

T29DPA_ML_C_P<3..0>

T29DP

T29DP_80D

DP_A_EXT_AUXCH_P

T29DP_80D

T29DP

DP_A_EXT_AUXCH

T29_R2D_C_P<3..0>

T29DP

T29DP_80D

T29_R2D_C_N<3..0>

T29DP

T29DP_80D

T29_SPI_55S

T29_SPI

T29_SPI_CS_L

T29_SPI_55S

T29_SPI

T29_SPI_MISO

T29_SPI_55S

T29_SPI

T29_SPI_MOSI

T29_SPI_55S

T29_SPI

T29_SPI_CLK

T29_I2C_55S

T29_I2C

I2C_T29_SDA

T29_I2C_55S

T29_I2C

I2C_T29_SCL

105 OF 109

3.13.0

051-8870

72 OF 75

64

65 64

64 65

64

64 34

8

64

34

8

34

8

64

64 34

8

65 64

64

34

8

34

8

64

65

64

65 64

65

64

64 65

65 64

8

34 64

8

34 64

34

44 34

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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87 54 21

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

1TO1_DIFFPAIR

*

=STANDARD =STANDARD =STANDARD =STANDARD

0.1 MM 0.1 MM

SMC Constraints

SYNC_MASTER=K21_CONSTRAINTS

SYNC_DATE=04/06/2011

SMB_50S

SMB

SMBUS_SMC_B_S0_SDA

SMB_50S

SMB

SMBUS_SMC_0_S0_SCL

SMB_50S

SMB

SMBUS_SMC_0_S0_SDA

SMB_50S

SMB

SMBUS_SMC_BSA_SCL

SMB_50S

SMB

SMBUS_SMC_MGMT_SCL

SMB_50S

SMB

SMBUS_SMC_MGMT_SDA

SMB_50S

SMB

SMBUS_SMC_BSA_SDA

1TO1_DIFFPAIR

CHGR_CSI_N

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO_N

SMB_50S

SMB

SMBUS_SMC_B_S0_SCL

SMB_50S

SMB

SMBUS_SMC_A_S3_SDA

SMB_50S

SMB

SMBUS_SMC_A_S3_SCL

106 OF 109

3.13.0

051-8870

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TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

DRAWING NUMBER

SIZE

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SHEET

PAGE TITLE

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A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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345678

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87 54 21

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

Audio Net Properties

PHYSICAL

NET_TYPE

SPACING

(USB_TPAD)

K21/K78 Specific Net PropertiesK21/K78 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

(USB_TPAD)

(USB_EXTA)

PHYSICAL

NET_TYPE

SPACING SPACING

NET_TYPE

PHYSICAL

(USB_EXTA)

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

SPACING

NET_TYPE

PHYSICAL

(USB_EXTA)

ELECTRICAL_CONSTRAINT_SET

Memory Constraint Relaxations

Misc Net Properties

I249

I250

I251

I252

I253

I254

I255

I256

I281

I282

I283

I284

I285

I286

I287

I288

I291

I292

I293

I294

I295

I296

I297

I298

I299

I300

I301

I302

I303

I304

I305

I306

I307

I308

I309

I310

I311

I312

I313

I314

I315

I316

I317

I318

I319

I320

I322

I324

I325

I326

I327

I328

I329

I330

I331

I332

I333

I334

I335

I336

CPU_27P4S

0.09 MM

TOP

400 MIL

500 MILUSB_85D

0.1 MM

TOP

10 mm

PCIE_85D 0.076 MM

*

0.09 MM

TOP

CLK_PCIE_90D

400 MIL

Project Specific Constraints

SYNC_DATE=04/06/2011

SYNC_MASTER=K21_CONSTRAINTS

MEM_85D

TOP 0.1 MM

6.35 MM

SATA

SB_POWER

*

PWR_P2MM

CLK_PCIE

GND

*

GND_P2MM

CLK_PCIE SB_POWER

*

PWR_P2MM

USB

SB_POWER

*

PWR_P2MM

*

GND_P2MM

0.20 MM

1000

GND

*

=STANDARD

?

ENET_MDI

*

GND

GND_P2MM

ENETCONN

*

25 MILS

?

CPU_VCCSENSE

*

GND

GND_P2MM

CPU_COMP

*

GND

GND_P2MM

*

AUDIO

=2:1_SPACING

?

=1:1_DIFFPAIR

THERM_1TO1_55S

*

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

DIFFPAIR

*

=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR

USB GND

*

GND_P2MM

THERM

*

=2:1_SPACING

?

SENSE

*

=2:1_SPACING

?

*

SENSE_1TO1_55S

=55_OHM_SE =55_OHM_SE=55_OHM_SE

=1:1_DIFFPAIR=1:1_DIFFPAIR=1:1_DIFFPAIR

LVDS

GND

*

GND_P2MM

PCIE

GND

*

GND_P2MM

SATA

GND

*

GND_P2MM

GND_P2MMMEM_CTRL

GND

*

GND_P2MMMEM_DATA

GND

*

GND_P2MM

MEM_CMD

GND

*

GND_P2MM

MEM_DQS

GND

*

MEM_72D

BOTTOM

6.35 MM

0.127 MM

0.09 MM 400 MIL

*

MEM_40S

MEM_37S 0.09 MM

*

400 MIL

400 MIL0.09 MMMEM_85D

*

0.09 MM 400 MILMEM_72D

*

GND_P2MM

MEM_CLK

GND

*

PWR_P2MM

0.20 MM

1000

GND

PP3V3_S5

SB_POWER

USB_85D

USB

USB_TPAD_R_P

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

SPKRAMP_INSUB_N

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

SPKRAMP_INSUB_P

AUD_DIFF

AUDIO

DIFFPAIR

SPKRAMP_INR_N

SPKRAMP_INR

AUDIO

DIFFPAIR

SPKRAMP_INR_P

SSM2315_SUB_N

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

SSM2315_SUB_P

AUDIO

1TO1_DIFFPAIR

AUD_DIFF

SSM2315_L_N

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

SSM2315_L_P

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

SSM2315_R_P

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

AUD_DIFF

SPKRAMP_INL_P

AUDIO

1TO1_DIFFPAIR

MAX98300_R_N

AUDIO

DIFFPAIR

SPKRAMP_INR_P

SPKRAMP_INR

AUDIO

DIFFPAIR

SPKRAMP_INR_N

AUDIO

DIFFPAIR

I2C_TCON_SCL

SMB

SMB_55S

CPUIMVP_ISNS1G_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS1G_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

CPUIMVP_ISUM_R_P

SENSE

SENSE_1TO1_55S

CPUIMVP_ISNS_N

VCCSAS0_CS_N

SENSE

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

CPUIMVP_ISUMG_P

LVDS_90D LVDS

LVDS_CONN_A_CLK_F_P

ISNS_ODD_R_P

SENSE_1TO1_55S

SENSE

ISNS_ODD_R_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

ISNS_1V5_S3_P

SENSE_1TO1_55S

SENSE

ISNS_P1V8GPU_R_N

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_P1V8GPU_R_P

SENSE

SENSE_1TO1_55S

CPUIMVP_ISUMG_R_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

CPUIMVP_ISUMG_R_P

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

CPUIMVP_ISNS_P

SENSE

SENSE_1TO1_55S

CPUIMVP_ISUMG_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_CPU_N

SENSE

SENSE_1TO1_55S

ISNS_CPU_P

SENSE_DIFFPAIR SENSE_1TO1_55S

VCCSAS0_CS_P

SENSE

SENSE_1TO1_55S

CPUIMVP_ISNS2_N

SENSE

SENSE_1TO1_55S

ISNS_HDD_P

SENSE

ISNS_1V5_S3_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_ODD_P

SENSE

CPUIMVP_ISUM_R_N

SENSE_1TO1_55S

CPUIMVP_ISNS1_N

SENSE

SENSE_1TO1_55S

CPUVCCIOS0_CS_P

SENSE_1TO1_55S

ISNS_HS_COMPUTING_N

SENSE_DIFFPAIR

SENSE

SATA_HDD_R2D_RDRVR_IN_N

SATASATA_90D

SATA_HDD_R2D_RDRVR_IN_P

SATASATA_90D

THERM

THERM_1TO1_55S

CPU_THERMD_N

CPU_THERMD_P

THERM_1TO1_55S

THERM

CPU_THERMD

T29_MLBBOT_THMSNS_P

THERM_1TO1_55S

THERM

SENSE_DIFFPAIR

T29_MLBBOT_THMSNS_N

THERM_1TO1_55S

THERM

SENSE

ISNS_HS_OTHER_N

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISNS2_P

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_HDD_N

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_HDD_R_P

SENSE

SATA_HDD_R2D_RDRVR_OUT_N

SATASATA_90D

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISNS1_P

SENSE

SENSE_1TO1_55S

ISNS_ODD_N

SENSE_DIFFPAIR

SENSE

ISNS_AIRPORT_N

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_AIRPORT_P

SENSE

SENSE_1TO1_55S LVDS_90D LVDS

LVDS_CONN_A_CLK_F_N

ENETCONN_P<3..0>

ENETCONN

ENET_100D

SATA_HDD_D2R_RDRVR_OUT_P

SATASATA_90D

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

CPUVCCIOS0_CS_N

SENSE

ISNS_HS_OTHER_P

SENSE_1TO1_55S

SATA_ODD_D2R_UF_P

SATASATA_90D

ENETCONN_N<3..0>

ENETCONN

ENET_100D

I2C_TCON_SDA_CONN

SMB

SMB_55S

I2C_TCON_SCL_CONN

SMB

SMB_55S

I2C_TCON_SDA

SMB

SMB_55S

I2C_SMC_SMS_SCL_R

SMB

SMB_55S

SMBUS_SMC_MGMT_SCL

I2C_SMC_SMS_SDA_R

SMBUS_SMC_MGMT_SDA

SMB

SMB_55S

USB_TPAD_CONN_N

USB

USB_85D

USB_TPAD_CONN_P

USB

USB_85D

AUD_LO2_P_L

AUDIO

1TO1_DIFFPAIR

AUD_DIFF

USB_LT1_N

USB

USB_85D

ISNS_LCDBKLT_P

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

ISNS_HDD_R_N

SENSE_DIFFPAIR

SENSE

USB_LT1_P

USB

USB_85D

USB_EXTA_MUXED_P

USB

USB_85D

PCIE_CLK100M_AP_CONN_N

CLK_PCIECLK_PCIE_90D

CHGR_CSI_R_N

1TO1_DIFFPAIR

CHGR_CSI_R_P

1TO1_DIFFPAIR

CHGR_CSO_R_P

1TO1_DIFFPAIR

AUD_LO1_N_R

AUDIO

1TO1_DIFFPAIR

AUD_DIFF

AUD_LO2_N_R

AUD_DIFF

AUDIO

1TO1_DIFFPAIR

AUD_LO2_P_R

AUDIO

1TO1_DIFFPAIR

AUD_DIFF

SSM2315_R_N

AUDIO

1TO1_DIFFPAIR

AUD_DIFF

SPKRAMP_R_N_OUT

SPK_OUT

AUDIO

DIFFPAIR

SPKRAMP_R_P_OUT

SPK_OUT

AUDIO

DIFFPAIR

SPKRAMP_SUB_P_OUT

SPK_OUT

AUDIO

DIFFPAIR

SPKRAMP_SUB_N_OUT

SPK_OUT

AUDIO

DIFFPAIR

SPKRAMP_L_N_OUT

SPK_OUT

AUDIO

DIFFPAIR

PCIE_CLK100M_AP_CONN_P

PCIE_CLK100M_AP

CLK_PCIECLK_PCIE_90D

USB2_EXTA_MUXED_N

USB

USB_85D

USB2_LT1_P

USB

USB_85D

USB2_LT1_N

USB

USB_85D

USB_LT2_P

USB

USB_85D

CONN_USB2_BT_N

USB

USB_85D

USB2_EXTA_MUXED_P

USB

USB_85D

CHGR_CSO_R_N

1TO1_DIFFPAIR

CONN_USB2_BT_P

USB

USB_85D

USB_LT2_N

USB

USB_85D

DP_IG_AUX_CH_C_P

DISPLAYPORT

DP_85D

DP_IG_AUX_CH_C_N

DISPLAYPORT

DP_85D

SPKRAMP_L_P_OUT

SPK_OUT

AUDIO

DIFFPAIR

USB_EXTA_MUXED_N

USB

USB_85D

AUD_DIFF

SPKRAMP_INL_N

AUDIO

1TO1_DIFFPAIR

AUD_LO2_N_L

1TO1_DIFFPAIR

AUDIO

AUD_DIFF

USB_TPAD_R_N

USB

USB_85D

SB_POWER

PP3V3_S0

AUD_LO1_P_R

AUDIO

1TO1_DIFFPAIR

AUD_DIFF

AUDIO

MAX98300_R_P

MAX98300_R

DIFFPAIR

SENSE_1TO1_55S

SENSE

ISNS_HS_COMPUTING_P

SATA_ODD_D2R_UF_N

SATASATA_90D

SATA_HDD_D2R_RDRVR_OUT_N

SATASATA_90D

SATA_HDD_D2R_RDRVR_IN_N

SATASATA_90D

SATA_HDD_D2R_RDRVR_IN_P

SATASATA_90D

SATA_HDD_R2D_RDRVR_OUT_P

SATASATA_90D

THERM_1TO1_55S

CPUTHMSNS_D2_P

SENSE_DIFFPAIR

THERM

THERM_1TO1_55S

THERM

CPUTHMSNS_D2_N

THERM_1TO1_55S

T29_THERMD_N

THERM

THERM_1TO1_55S

T29_THERMD_P

SENSE_DIFFPAIR

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47

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

21

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

87 54 21

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

K90i Board-Specific Spacing & Physical Constraints

NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers.

NOTE: These are Intel recommended impedances for PEG, unused on K90i.

NOTE: 85_DIFF_BGA is 85-ohms differential impedance on outer layers and 80-ohms on inner layers.

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

NOTE: 90_DIFF_BGA is 90-ohms differential impedance on outer layers and 85-ohms on inner layers.

2.5:1_SPACING

*

0.25 MM

?

3:1_SPACING

*

0.3 MM

?

4:1_SPACING

*

0.4 MM

?

2:1_SPACING

*

0.2 MM

?

1.5:1_SPACING

*

0.15 MM

?

STANDARD

*

=DEFAULT

?

BGA_P1MM

*

=DEFAULT

?

BGA_P2MM

*

=DEFAULT

?

DEFAULT

*

0.1 MM

?

5X_DIELECTRIC

*

0.350 MM

?

4X_DIELECTRIC

*

0.280 MM

?

7X_DIELECTRIC

*

0.490 MM

?

3X_DIELECTRIC

*

0.210 MM

?

2X_DIELECTRIC

*

0.140 MM

?

MEM_CLK

*

BGA

BGA_P2MM

CLK_PCIE

*

BGA

BGA_P2MM

CLK_SLOW

*

BGA

BGA_P2MM

**

BGA

BGA_P1MM

ISL3,ISL4,ISL9,ISL10

37_OHM_SE

Y

0.160 MM 0.1 MM =STANDARD =STANDARD =STANDARD

*

37_OHM_SE

Y

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

TOP,BOTTOM37_OHM_SE

Y

0.195 MM 0.1 MM

40_OHM_SE

*Y

=STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

ISL3,ISL4,ISL9,ISL10

40_OHM_SE

Y

0.140 MM 0.140 MM =STANDARD =STANDARD =STANDARD

40_OHM_SE TOP,BOTTOM

Y

0.170 MM 0.170 MM

50_OHM_SE

*Y

0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD

50_OHM_SE TOP,BOTTOM

Y

0.110 MM 0.090 MM

STANDARD

*Y

=DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT

DEFAULT

*Y

=50_OHM_SE =50_OHM_SE 10 MM 0 MM 0 MM

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA MM 15.5.1

55_OHM_SE 0.090 MM0.090 MM

Y

TOP,BOTTOM

=STANDARD=STANDARD=STANDARD

0.076 MM0.076 MM

Y*

55_OHM_SE

SYNC_MASTER=K21_CONSTRAINTS

SYNC_DATE=04/06/2011

PCB Rule Definitions

90_OHM_DIFF =STANDARD=STANDARD=STANDARD=STANDARD=STANDARD

Y*

=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD

Y

85_OHM_DIFF

*

0.170 MM0.170 MM0.115 MM0.115 MM

Y

ISL4,ISL985_OHM_DIFF

0.195 MM0.195 MM0.130 MM0.130 MM

Y

TOP,BOTTOM85_OHM_DIFF

0.170 MM0.170 MM0.1 MM0.095 MM

Y

ISL3,ISL1085_OHM_DIFF

90_OHM_DIFF 0.210 MM0.210 MM0.089 MM0.089 MM

Y

ISL3,ISL10

0.210 MM0.210 MM0.105 MM0.105 MM

Y

ISL4,ISL990_OHM_DIFF

0.210 MM0.210 MM0.115 MM0.115 MM

Y

TOP,BOTTOM90_OHM_DIFF

0.250 MM0.250 MM0.074 MM0.074 MM

Y

ISL3,ISL10100_OHM_DIFF

=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD

Y

100_OHM_DIFF

*

0.250 MM0.250 MM0.085 MM0.085 MM

Y

ISL4,ISL9100_OHM_DIFF

0.300 MM0.300 MM0.071 MM0.071 MM

Y

ISL4,ISL9110_OHM_DIFF

0.330 MM0.330 MM0.070 MM0.070 MM

N

ISL3,ISL10110_OHM_DIFF

=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD

Y*

110_OHM_DIFF

0.200 MM0.200 MM0.091 MM0.091 MM

Y

TOP,BOTTOM100_OHM_DIFF

0.280 MM0.280 MM0.077 MM0.077 MM

Y

TOP,BOTTOM110_OHM_DIFF

0.165 MM0.120 MM

Y

TOP,BOTTOM48_OHM_SE

=STANDARD=STANDARD=STANDARD0.090 MM0.097 MM

Y*

48_OHM_SE

=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD

Y

80_OHM_DIFF

*

0.170 MM0.170 MM0.110 MM0.110 MM

Y

ISL3,ISL1080_OHM_DIFF

0.180 MM0.180 MM0.145 MM0.145 MM

Y

TOP,BOTTOM80_OHM_DIFF

0.170 MM0.170 MM0.129 MM0.129 MM

Y

ISL4,ISL980_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF

*

=85_OHM_DIFF85_DIFF_BGA

0.125 MM0.125 MM0.075 MM0.075 MM

Y

ISL3,ISL485_DIFF_BGA

0.125 MM0.125 MM0.075 MM0.075 MM

Y

ISL9,ISL1085_DIFF_BGA

0.125 MM0.125 MM0.075 MM0.075 MM

Y

ISL3,ISL490_DIFF_BGA

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

*

90_DIFF_BGA

0.125 MM0.125 MM0.075 MM0.075 MM

Y

ISL9,ISL1090_DIFF_BGA

0.125 MM0.125 MM0.075 MM0.075 MM

Y

ISL3,ISL4100_DIFF_BGA

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

*

100_DIFF_BGA

0.125 MM0.125 MM0.075 MM0.075 MM

Y

ISL9,ISL10100_DIFF_BGA

0.1 MM 0.1 MM=STANDARD=STANDARD =STANDARD

Y

1:1_DIFFPAIR

*

0.2 MM0.310 MM

Y

TOP,BOTTOM27P4_OHM_SE

=STANDARD=STANDARD=STANDARD0.2 MM0.250 MM

Y*

27P4_OHM_SE

=STANDARD=STANDARD=STANDARD=STANDARD=STANDARD

Y*

72_OHM_DIFF

0.130 MM0.130 MM0.155 MM0.155MM

Y

ISL4,ISL972_OHM_DIFF

0.130 MM0.130 MM0.165 MM0.165 MM

Y

TOP,BOTTOM72_OHM_DIFF

0.130 MM0.130 MM0.135 MM0.135 MM

Y

ISL3,ISL1072_OHM_DIFF

109 OF 109

3.13.0

051-8870

75 OF 75