APLUS ASM8412CA Datasheet

6F-3 NO.7, LANE 75, TA-AN ROAD, SEC.1, TAIPEI, TAIWAN, R.O.C.

http://www.aplusinc.com.tw

台北市大安路一段75巷7號6F-3 TEL:[phone] FAX:[phone]

ASM8412CA

DATA SHEET

ASM8412CA – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

ASM8412CA

1.0 General Description

The ASM8412CA is very low cost voice synthesizer with 4-bit microprocessor. It has various features
including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice
synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function
can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction
pipeline. It allows all instructions to be executed in a single cycle, except for program branches and
data table read instructions (which need two instruction cycles).

1.1 Feature

u Single power supply can operate from 2.4V through 5V
u Internal Program ROM: 4K x 10-bit
u 1 sets of 18-bit DPR can access up to 256K x 10 bits data memory space
u Data Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh
u I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)

u On-chip clock generator: Resistive Clock Drive(RM)
u Timer: 1

• Timer0: a 9-bit auto-reload timer/counter

u Stack: 2-level subroutine nesting
u HALT and Release from HALT function to reduce power consumption
u Watch Dog Timer (WDT)
u Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
u Number of instruction: 22

1

Rev 1.0

FIGURE 1.1 : Block Diagram of ASM8412CA

Instruction

PCH(8)

PCL(4)

Clock Generator

Stack(12)

Data Bus[3:0]

Accumlator(4)

Immediate(4)

PRA0

ASM8412CA

Data Bus[3:0]

(ADDR[17:12])

=000000b

COUT

PCLATCH(8)

DPR3,2,1

DLATCH(10)

ALU(4)

Register(4)

One-Channel

( Voice synthesizer )

COUT

PC[11:0]

ADDR[17:0]

DPR[17:0]

P1,P2,P3,P4

enter test mode

Reset Chip
Reset Chip

(2-Level)

ROM_ADDR[17:0]

ROM_Data[9:0]

SRAM

(96 x 4)

00h-1Fh
40h-7Fh

Test select

Power on Reset

RESET pin

Program

(Data)

ROM

Instruction Bus [9:0]

Instruction Bus [9:0]

Timer0(9)

OSC

VDD/GND

ROM Latch

Latch

Instruction

Decoder

Control Signal

Instruction Bus [9:0]

PRA(4)
PRB(4)
PRC(4)

weak or strong
pull-low for PRA,
PRB, PRC

PRASL(4)

2

Rev 1.0