APLUS ASM34012CB Datasheet

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PLUS MAKE YOUR PRODUCTION A-PLUS

ASM34012C

DATA SHEET

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PLUS INTEGRATED CIRCUITS INC.

Address:

3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,

Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.

TEL: [phone]

FAX: [phone]

WEBSITE : http: //www.aplusinc.com.tw

Sales E-mail: Mr. Jason

[e-mail]

Technology E-mail: Mr. George

[e-mail]

ASM34012CB

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VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

1.0 General Description

The ASM34012CB is very low cost voice synthesizer with 4-bit microprocessor. It has various

features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog

timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS

technology and halt function can minimize power dissipation. Its architecture is similar to RISC,

with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,

except for program branches and data table read instructions (which need two instruction

cycles).

1.1 Feature

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Single power supply can operate from 2.4V through 5.5V

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Internal Program ROM: 4K x 10-bit

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1 sets of 20-bit DPR can access up to 1024K x 10 bits data memory space

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Data Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh

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I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)

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On-chip clock generator: Resistive Clock Drive(RM)

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Timer: 1

• Timer0: a 9-bit auto-reload timer/counter

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Stack: 2-level subroutine nesting

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HALT and Release from HALT function to reduce power consumption

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Watch Dog Timer (WDT)

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Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles

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Number of instruction: 22

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The Voice function can be implemented by microprocessor instruction

• One 8-bit COUT output for ASMxxxxx

FIGURE 1.1 : Block Diagram of ASM34012CB

COUT

OSC

VDD/GND

ROM

PC[11:0]

ROM Latch

Instruction

Latch

Instruction

Decoder

PCH(8) PCL(4)

PCLATCH(8)

DPR3,2,1

Program

DLATCH(10)

Clock Generator

Power on Reset

Tes t s el ect

P1,P2,P3,P4

enter test mode

Timer0(9)

Reset Chip

Stack

(12)

Data Bus[3:0

]

Instruction Bus [9:0]

ROM_ADDR[19:0]

ROM_Data[9:0]

Data Bus[3:0]

Control Signal

ADDR[19:0]

=00000000b

(ADDR[19:12])

PRASL(4)

weak or strong
pull-low for PRA,

(Data)

Instruction Bus [9:0]

Instruction Bus [9:0]

( Voice synthesizer )

One-Channel

SRAM

(96 x 4)

40h-7Fh

(2-Level)

ALU(4)

Register(4)

Accumlator

(4)

Immediate(4

)

DPR[19:0]

RESET pin

Reset Chip

PRA0

00h-1Fh

PRA(4)
PRB(4)
PRC(4)

PRB, PRC

COUT