APLUS ASM0912C Datasheet

6F-3 NO.7, LANE 75, TA-AN ROAD, SEC.1, TAIPEI, TAIWAN, R.O.C.

http://www.aplusinc.com.tw

台北市大安路一段75巷7號6F-3 TEL:[phone] FAX:[phone]

ASM0912C

DATA SHEET

ASM0912C – VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

ASM0912C

1.0 General Description

The ASM0912C is very low cost voice synthesizer with 4-bit microprocessor. It has various

features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog

timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS

technology and halt function can minimize power dissipation. Its architecture is similar to RISC,

with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle,

except for program branches and data table read instructions (which need two instruction

cycles).

1.1 Feature

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Single power supply can operate from 2.4V through 5.5V

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Internal Program ROM: 4K x 10-bit

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1 sets of 16-bit DPR can access up to 32K x 10 bits data memory space

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Data Registers:

• 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh

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I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 4-bit Output Port B (2Dh)

• PRC: 4-bit Input Port C (2Fh)

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On-chip clock generator: Resistive Clock Drive(RM)

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Timer: 1

• Timer0: a 9-bit auto-reload timer/counter

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Stack: 2-level subroutine nesting

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HALT and Release from HALT function to reduce power consumption

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Watch Dog Timer (WDT)

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Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles

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Number of instruction: 22

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The Voice function can be implemented by microprocessor instruction

• One 8-bit COUT output for ASMxxxxx

1

Rev 1.0

FIGURE 1.1 : Block Diagram of ASM0912C

(12)

]

)

)

ASM0912C

(ADDR[14:12])

=0000b

COUT

PCLATCH(8)

PCH(8)

DPR3,2,1

DLATCH(10)

Data Bus[3:0

ALU(4)

Register(4)

One-Channel

( Voice synthesizer )

COUT

PCL(4)

PC[11:0]

ADDR[14:0]

DPR[14:0]

Accumlator(4

enter test mode

Data Bus[3:0]

ROM_Data[9:0]

Immediate(4

P1,P2,P3,P4

Reset Chip

Reset Chip

Stack

(2-Level)

ROM_ADDR[14:0]

Program

(Data)

ROM

SRAM

(96 x 4)

00h-1Fh
40h-7Fh

Clock Generator

Tes t s el ect

Power on Reset

RESET pin

Instruction Bus [9:0]

ROM Latch

Instruction

Instruction Bus [9:0]

Instruction

Decoder

Control Signal

VDD/GND

PRA0

OSC

Timer0(9)

Latch

PRASL(4)

Instruction Bus [9:0]

PRA(4)
PRB(4)
PRC(4)

weak or strong
pull-low for PRA,

PRB, PRC

2

Rev 1.0