APLUS ASM0406CB Datasheet

6F-3 NO.7, LANE 75, TA-AN ROAD, SEC.1, TAIPEI, TAIWAN, R.O.C.

http://www.aplusinc.com.tw

台北市大安路一段75巷7號6F-3 TEL:[phone] FAX:[phone]

ASM0406CB/0906CB

DATA SHEET

ASM0406CB/0906CB

ASM0406CB/0906CB

- VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR

1.0 General Description

The ASM0406CB/0906CB is very low cost voice synthesizer with 4-bit microprocessor. It has

various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator,

watchdog timer ( WDT ), voice synthesizer, etc. It consists of 22 instructions in the device.

With CMOS technology and halt function can minimize power dissipation. Its architecture is similar

to RISC,with two stages of instruction pipeline. It allows all instructions to be executed in a single

cycle, except for program branches and data table read instructions (which need two

instruction cycles).

1.1 Feature

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Single power supply can operate from 2.4V through 5.5V

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Internal Program ROM: 4K x 10-bit

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1 sets of 15-bit DPR can access up to 32K x 10 bits data memory space

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Data Registers:

• 64 x 4-bit data RAM (00-1Fh plus 40h-5Fh)

• Unbanked special function registers (SFR) range: 20h-3Fh

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I/O Ports:

• PRA: 4-bit I/O Port A (2Bh)

• PRB: 2-bit Output Port B (2Dh)

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On-chip clock generator: Resistive Clock Drive(RM)

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Timer: 1

• Timer0: a 9-bit auto-reload timer/counter

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Stack: 2-level subroutine nesting

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HALT and Release from HALT function to reduce power consumption

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Watch Dog Timer (WDT)

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Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles

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Number of instruction: 22

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The Voice function can be implemented by microprocessor instruction

• One 8-bit COUT output for ASM0406CB/0906CB

1

Rev 1.0

FIGURE 1.1 : Block Diagram of ASM0406CB/0906CB

(12)

]

(4)

)

ASM0406CB/0906CB

Data Bus[3:0]

(ADDR[14:12])

=000b

COUT

PCLATCH(8)

PCH(8) PCL(4)

DPR3,2,1

DLATCH(10)

Data Bus[3:0

Accumlator

ALU(4)

Register(4)

One-Channel

( Voice synthesizer )

COUT

PC[11:0]

ADDR[14:0]

DPR[14:0]

P1,P2,P3,P4

enter test mode

Reset Chip

Reset Chip

ROM_Data[9:0]

Immediate(4

Stack

(2-Level)

ROM_ADDR[14:0]

Program

(Data)

ROM

SRAM

(64 x 4)

00h-1Fh
40h-5Fh

Clock Generator

Tes t s el ect

Power on Reset

RESET pin

Instruction Bus [9:0]

Instruction Bus [9:0]

Timer0(9)

OSC

VDD/GND

PRA0

ROM Latch

Instruction

Latch

Instruction

Decoder

Control Signal

Instruction Bus [9:0]

PRA(4)
PRB(2)

weak or strong
pull-low for PRA,

PRB, PRC

PRASL(4)

2

Rev 1.0