APLUS APU429 Datasheet

4-Bit Micro-controller With LCD Driver

Features

y Low power and low voltage operation
y Powerful instruction set (150 instructions)
y Memory capacity

Ϋʳ Instruction ROM capacity 4096 x 16 bits
Ϋʳ Index ROM capacity 256 x 8 bits
Ϋʳ Internal RAM capacity 384 or 256 x 4 bits

y Input/Output ports of up to 20 pins
y 8-level subroutine nesting
y Built-in LCD driver, 8 x 42 = 336 segments
y Built-in EL driver, frequency or melody generator
y Built-in Resistance-to-Frequency Converter
y Built-in 2-channel 6/8-bit PWM output

General Description

The APU429 is an embedded high performance
4-bit micro-computer with an on-chip LCD driver. It
contains all the necessary functions in a single chip:
4-bit parallel processing ALU, ROM, RAM, I/O ports,
timer, clock generator, dual clock, RFC, EL-light,
LCD driver, look-up table, watchdog timer and
keyboard scanning. The instruction set includes not
only 4-bit operation and manipulation instructions
but also various conditional branch instructions and

y Built-in key strobe function

(Shared with segment pin)

y Built-in voltage doubler, halver, tripler

quadrupler charge pump circuit

y Two 6-bit programmable timers with

programmable clock source

y Watchdog timer
y 4 external & 3 internal interrupt resources

Ϋʳ External: INT, RFC, IOA/IOC/S port,

keystrobe

Ϋʳ Internal: TM1, TM2, Predivider

y Dual clock operation
y HALT and STOP function

LCD driver data transfer instructions which are
powerful and easy to use.

The HALT function stops any internal operations
other than the oscillator, divider and LCD driver in
order to minimize the power dissipation.

The STOP function stops all the clocks in the chip.

Block Diagram

S E G 35󲕏38

IO A P o rt

/R F C

Frequency

Generator

CUP 1
CUP 2
CUP 3

Pre-Divider

W atchdog

Tim er

O s c illa t o r

XTIN

XTOUT

CFIN

CFOUT

S E G 31󲕏34

IO B P o rt

/E L , B Z

S E G 39󲕏42

IO C P o rt

/K E Y IN

Table R O M

256 x 8

2x6Bits

PresetTimer

Control

Circ u it

S1󲕏S4

IN T

RESET

SE G 27󲕏30

IO D P o rt

/P W M

4-B itD ata Bus

Index S R AM

256 x 4

COM 1󲕏8 SEG 1󲕏SEG26 VDD1󲕏4

LC D D river

S egm entP LA

ALU

8-Levels S tack

12-B itProgram

Counter

SRAM

128 x 4

In s tru c tio n

Decoder

MaskROM

4096 x 16

Preliminary

1 Ver.0.0

Pad Assignment

APU429

APU429

Chip size : 2620 x 2050 Pm
Pad size : 100 x 100 Pm
Pad window : 90 x 90 Pm
Pad pitch : min. 120 Pm

<

20

10

70

1

60

30

40

50

;

Note: The substrate of die must connect to GND.

Pad Coordinates

Pad No. Pad Name X Y Pad No. Pad Name X Y

1 CFIN 1971.50 2544.50 36 SEG13/KO3 75.25 75.25

2 CFOUT 1785.25 2544.50 37 SEG14/KO4 225.25 75.25

3 XTIN 1665.25 2544.50 38 SEG15/KO5 345.25 75.25

4 XTOUT 1545.25 2544.50 39 SEG16/KO6 465.25 75.25

5 BAK 1425.25 2544.50 40 SEG17/KO7 585.25 75.25

6 TESTA 1305.25 2544.50 41 SEG18/KO8 705.25 75.25

7 RESET 1185.25 2544.50 42 SEG19/KO9 825.25 75.25

8 INT 1065.25 2544.50 43 SEG20/KO10 945.25 75.25

9 S1 945.25 2544.50 44 SEG21/KO11 1065.25 75.25

10 S2 825.25 2544.50 45 SEG22/KO12 1185.25 75.25

11 S3 705.25 2544.50 46 SEG23/KO13 1305.25 75.25

Preliminary

2 Ver.0.0

Pad No. Pad Name X Y Pad No. Pad Name X Y

12 S4 585.25 2544.50 47 SEG24/KO14 1425.25 75.25

13 VDD1 465.25 2544.50 48 SEG25/KO15 1545.25 75.25

14 VDD2 345.25 2544.50 49 SEG26/KO16 1665.25 75.25

15 VDD3 225.25 2544.50 50 SEG27/IOD1 1785.25 75.25

16 VDD4 75.25 2544.50 51 SEG28/IOD2 1971.50 75.25

17 CUP1 75.25 2394.50 52 SEH29/IOD3/PWM1 1971.50 225.25

18 CUP2 75.25 2274.50 53 SEH30/IOD4/PWM2 1971.50 345.25

19 CUP3 75.25 2154.50 54 SEG31/IOB1/ELC 1971.50 465.25

20 COM1 75.25 2034.50 55 SEG32/IOB2/ELP 1971.50 585.25

21 COM2 75.25 1914.50 56 SEG33/IOB3/BZB 1971.50 705.25

22 COM3 75.25 1785.25 57 SEG34/IOB4/BZ 1971.50 825.25

23 COM4 75.25 1665.25 58 SEG35/IOA1/CX 1971.50 945.25

24 SEG1 75.25 1545.25 59 SEG36/IOA2/RR 1971.50 1065.25

25 SEG2 75.25 1425.25 60 SEG37/IOA3/RT 1971.50 1185.25

26 SEG3 75.25 1305.25 61 SEG38/IOA4/RH 1971.50 1305.25

27 SEG4 75.25 1185.25 62 SEG39/IOC1/KI1 1971.50 1425.25

28 SEG5 75.25 1065.25 63 SEG40/IOC2/KI2 1971.50 1545.25

29 SEG6 75.25 945.25 64 SEG41/IOC3/KI3 1971.50 1665.25

30 SEG7 75.25 825.25 65 SEG42/IOC4/KI4 1971.50 1785.25

31 SEG8 75.25 705.25 66 COM5 1971.50 1905.25

32 SEG9 75.25 585.25 67 COM6 1971.50 2034.50

33 SEG10 75.25 465.25 68 COM7 1971.50 2154.50

34 SEG11/KO1 75.25 345.25 69 COM8 1971.50 2274.50

35 SEG12/KO2 75.25 225.25 70 GND 1971.50 2394.50

Chip size : 2620 x 2050 Pm

Pad Descriptions

Pad Name I/O Description

BAK

VDD1
VDD2
VDD3
VDD4

RESET I

INT I

TESTA I Test signal input pin.

CUP1
CUP2
CUP3

Preliminary

Positive back-up voltage.
In Li mode, connects a 0.1P capacitance to GND.

LCD drive voltage and positive supply voltage.
While in Ag mode, connects +1.5V to VDD1.
While in Li/ExtV mode, connects +3.0V to VDD2.

Input pin for LSI reset signal.
With Internal pull-down resistor.

Input pin for external INT request signal.
Falling edge or rising edge triggered by mask option.
Internal pull-down or pull-up resistor or floatting to be selected by mask option.
TESTA I Test signal input pin, internal pull-down resistor.

Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3, 4 pins.
Connects the CUP1, CUP2 and CUP3 pins with a nonpolarized electronic

O

capacitor if 1/2, 1/3 or 1/4 bias mode has been selected. In the STATIC mode,
these pins should be open.

3 Ver.0.0

Pad Name I/O Description

Time based counter frequency (Clock specified. LCD alternating frequency.
Alarm signal frequency.) or system clock oscillation.

XTIN
XTOUT

CFIN
CFOUT

COM1~8 O Output pins for supplying voltage to drive the common pins of the LCD panel.

SEG1~10 O Output pins for LCD panel segment.

SEG11~26/KO1~16 O

SEG27~42 O Output pins for LCD panel segment.

IOA1~4 I/O

IOB1~4

IOC1~4 I/O

IOD1~4 I/O

S1~4 I

KI1~4 I Key scan input, this port shares pins with IOC1~4 and is set by mask option.

CC

RFC RR

RT
RH

EL ELC

ELP

ALM BZB

BZ

PWM1, 2 O 6/8-Bit PWM output; set by mask option.

GND Negative supply voltage.

I

32KHz crystal oscillator.

O

Oscillation stops at the execution of STOP instruction.

System clock oscillation.
Connected with ceramic resonator.

I

Connected with RC oscillation circuit.

O

Oscillation stops at the execution of STOP or SLOW instruction.

Output pins for LCD panel segment.
Key strobe function, share pins as key scan output.

Input/Output port A, can use software to define the internal pull-low resistor
and chattering clock in order to reduce input bounce and generate an
interrupt.

This port shares pins with SEG35~38 and is set by mask option.
This port also shares pins with CC, RR, RT and RH, and is set by mask option.

Input/Output port B.
IOB port shares pins with SEG31~34, and is set by mask option.

I/O

This port also shares pins with ELC, ELP, BZB and BZ, and is set by mask
option.

Input/Output port C, can use software to define internal pull-low/low-level hold
resistor and chattering clock in order to reduce input bounce and generate an
interrupt or keyboard scanning function with ELC, ELP, BZB and BZ, and is
set by mask option.

Input/Output port D.
This port shares pins with SEG27~30 and is set by mask option.
IOD3, 4 shares pins with PWM1, 2 and is set by mask option.

Input ports by mask option to internal pull-low/low-level hold resistor and
chattering clock in order to reduce input bounce and generate an interrupt or
HALT or STOP release.

I

1 input pin and 3 output pins for RFC application.

O

This port shares pins with SEG35~38 and is set by mask option.

O

This port shares pins with IOA1~4 and is set by mask option.

O

OOOutput port for EL-light.

This port shares pins with SEG31, 32 and is set by mask option.
This port shares pins with IOB1, 2 and is set by mask option.

O Output port for alarm, frequency or melody generator.

This port shares pins with IOB3, 4 and is set by mask option.

Preliminary

4 Ver.0.0

Absolute Maximum Rating Ta = 0 to 70к GND=0V

Name Symbol Rating Unit

Maximum Supply Voltage

V

V

V

V

Maximum Input Voltage V

V

V

Maximum Operating Temperature t

Maximum Storage Temperature t

DD1

DD2

DD3

DD4

IN

OUT1

OUT2

OPG

STG

-0.3 ~ +5.5 V

-0.3 ~ +5.5 V

-0.3 ~ +8.5 V

-0.3 ~ +8.5 V

-0.3 to V

-0.3 to V

-0.3 to V

+0.3 V

DD1/2

+0.3 VMaximum Output Voltage

DD1/2

+0.3 V

DD3

0 to +70

-25 to +125

к

к

Allowable operating conditions Ta = 0 to 70к GND=0V

Name Symbol Condition Min. Max. Unit

Supply Voltage

Oscillator Start-up Voltage V

Oscillator Sustain Voltage V

Supply Voltage V

Supply Voltage V

Input sHs Voltage

Input sLs Voltage

Input sHs Voltage

Input sLs Voltage

Input sHs Voltage

Input sLs Voltage

Input sHs Voltage

Input sLs Voltage

Input sHs Voltage

Input sLs Voltage

Input sHs Voltage

Input sLs Voltage

Operating Freq.

V

DD1

V

DD2

V

DD3

V

DD4

DDB

DDB

DD1

DD2

V

V

V

V

V

V

V

V

V

V

V

V

f

OPG1

f

OPG2

f

OPG3

Crystal Mode 1.3 V

Crystal Mode 1.2 V

Ag Mode 1.2 1.65 V

EXT-V, Li Mode 2.4 5.25 V

Ag Battery Mode V

IH1

IL1

Li Battery Mode

IH2

IL2

OSCIN at Ag Battery Mode

IH3

IL3

OSCIN at Li Battery Mode

IH4

IL4

CFIN at Li Battery or EXT-V Mode

IH5

IL5

IH6

RC Mode

IL6

Crystal Mode 32 3580 kHz

External RC Mode 32 1000 kHz

CF Mode 1000 3580 kHz

1.2 5.25 V

2.4 5.25 V

2.4 8.0 V

2.4 8.0 V

DD1-0.7

V

DD1+0.7

-0.7 0.7 V

V

DD2-0.7

V

DD2+0.7

-0.7 0.7 V

0.8V

DD1

00.2V

0.8V

DD2

00.2V

0.8V

DD2

00.2V

0.8V

DDO

00.2V

V

DD1

DD1

V

DD2

DD2

V

DD2

DD2

V

DDO

DDO

V

V

V

V

V

V

V

V

V

V

Preliminary

5 Ver.0.0

Electrical Characteristics

Input resistance

Name Symbol Condition Min. Typ. Max. Unit

sLs-Level Hold tR(IOC)

IOC/IOA Pull-Down t

INT Pull-Up t

R

INT Pull-Down t

RES Pull-Down t

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

IIH1

IIH2

IIH3

MSD1

MSD2

MSD3

INTU1

INTU2

INTU3

INTD1

INTD2

INTD3

RES1

RES2

RES3

VI=0.2V

VI=0.2V

VI=0.2V

VI=V

VI=V

VI=V

VI=V

VI=V

VI=V

, #1 10 40 100

DD1

, #2 10 40 100

DD2

, #3 5 20 50

DD2

, #1 200 500 1000

DD1

, #2 200 500 1000

DD2

, #3 100 250 500

DD3

, #1 200 500 1000

DD1

, #2 200 500 1000

DD2

, #3 100 250 500

DD3

VI=GND, #1 200 500 1000

VI=GND, #2 200 500 1000

VI=GND, #3 100 250 500

VI=GND or V

VI=GND or V

VI=GND or V

, #1 5 20 50

DD1

, #2 5 20 50

DD2

, #3 5 20 50

DD2

k:

k:

k:

k:

k:

k:

k:

k:

k:

k:

k:

k:

k:

k:

k:

Note: #1: V

= 1.2V ( Ag ), #2: V

DD1

DC output characteristics

Name Symbol Condition For Min. Typ. Max. Unit

Output sHs Voltage

Output sLs Voltage

Output sHs Voltage

Output sLs Voltage

Note: #1: V

= 1.2V ( Ag ), #2: V

DD1

V

OH1a

V

OH2 a

V

OH3 a

V

OL1 a

V

OL2 a

V

OL3 a

V

OH1c

V

OH2cIOH

V

OH3cIOH

V

OL1c

V

OL2cIOL

V

OL3CIOL

= 2.4V ( Li ), #3: V

DD2

IOH=-10PA, #1

IOH=-50PA, #2

IOH=-200PA, #3

IOL=20PA, #1

IOL=100PA, #2

IOL=400PA, #3

IOH=-200PA, #1

= 4V (Ext-V).

DD2

SEG1~26

0.8 0.9 1.0 V

1.5 1.8 2.1 V

2.5 3 3.5 V

0.2 0.3 0.4 V

0.3 0.6 0.9 V

0.5 1 1.5 V

0.8 0.9 1.0 V

=-1mA, #2 1.5 1.8 2.1 V

=-3mA, #3 2.5 3 3.5 V

IOL=400PA, #1

SEG27~42

IOA, B, C, D

0.2 0.3 0.4 V

=2mA, #2 0.3 0.6 0.9 V

=6mA, #3

= 2.4V ( Li ), #3: V

DD2

= 4V (Ext-V).

DD2

0.5 1 1.5 V

Preliminary

6 Ver.0.0