Apec AP1280MP Schematic [ru]

Advanced Power

S

N

Electronics Corp.

2A SINK/SOURCE BUS TERMINATION REGULATOR

FEATURE

Ideal for DDR-I, DDR-II and DDR-III VTT Applications
Sink and Source 2A Continuous Current
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL_18,
HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in ESOP-8 (Exposed Pad) Packages

VIN and V
RoHS Compliant and 100% Lead (Pb)-Free

APPLICATIO

Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems

No Power Sequence Issue

CNTL

AP1280MP

DESCRIPTIOON

The AP1280MP is a simple, cost-effective and

high-speed linear regulator designed to generate
termination voltage in double data rate (DDR) memory
system to comply with the JEDEC SSTL_2 and
SSTL_18 or other specific interfaces such as HSTL,
SCSI-2 and SCSI-3 etc. devices requirements. The
regulator is capable of actively sinking or sourcing up to
2A while regulating an output voltage to within 40mV.
The output termination voltage cab be tightly regulated
to track 1/2V

resistors or the desired output voltage can be pro­grammed by externally forcing the REFEN pin voltage.
The AP1280MP also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely low
initial offset voltage, excellent load regulation, current
limiting in bi-directions and on-chip thermal shut-down
protection.
The AP1280MP are available in the ESOP-8
(Exposed Pad) surface mount packages.

by two external voltage divider

DDQ

TYPICAL APPLICATION

VCNTL=3.3V

VIN=2.5V/1.8V/1.5V

R1

2N7002

EN

R1 = R2 = 100KΩ, RTT = 50Ω / 33Ω / 25Ω
C
CSS = 1µF, CIN = 470µF(Low ESR), C

Data and specifications subject to change without notice

= 10uF (Ceramic) + 100uF under the worst case testing condition

OUT,min

R2

REFEN

CSS

VIN VCNTL

AP1280

GND

= 47µF

CNTL

VOUT

CIN

CCNTL

COUT

R

RTT

DUMMY

1

201011058

Advanced Power
Electronics Corp. AP1280MP

ABSOLUTE MAXIMUM RATINGS

Input Voltage (VIN) ------------------------------------------- 6V
CNTL Pin Voltage (V
Power Dissipation (P
Storage Temperature Range (T

) --------------------------------- 6V

CNTL

) ------------------------------------- Internally Limited

D

) ---------------------- -65 to +150°C

ST

Lead Temperature (Soldering, 10sec.) ---------------- 260°C
Thermal Resistance from Junction to Case (R

Note1 : Exceeding the absolute maximum rating may damage the device.

OPERATING RATING

(Note2)

thjc

)

Input Voltage (VIN) ------------------------------------------- 2.5V to 1.5V +3%
CNTL Pin Voltage (V
Junction Temperature Range (T
Ambient Temperature Range (T

Note2 : The device is not guaranteed to function outside its operating conditions.

) --------------------------------- 5.5V or 3.3V +5%

CNTL

) ----------------------- -40 to +125°C

J

) ---------------------- -40 to +85°C

A

ORDERING / PACKAGE INFORMATION

AP1280X-HF

Halogen-Free

MP : ESOP-8

(Note1)

28°C/W

VIN

1

2

3

REFEN

4

VOUT

(

R

= 75oC/W

thja

Top View

GND

ESOP-8

)

8

NC

7

NCGND

6

VCNTL

5

NC

ELECTRICAL SPECIFICATIONS

(VIN=1.8V, V

Parameter SYM TEST CONDITION MIN TYP MAX
Input

VCNTL Operation Current
Standby Current

Output (DDR / DDRII / DDRIII)

Output Offset Voltage
Load Regulation

Protection

Current Limit I
Thermal Shutdown Temperature T
Thermal Shutdown Hysteresis ΔT

REFEN Shutdown

Shutdown Threshold V

Note3. VOS offset is the voltage measurement defined as V
Note4. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation
in the load range from 0A to 2A.

CNTL

=3.3V, V

(Note3)

(Note4)

REFEN

=0.9V, C

=10uF(Ceramic), TA =25oC, unless otherwise specified)

OUT

I

CNTL

I

STBY

V

OS IOUT

ΔV

LIM

SD

V

IH

V

IL

I

= 0A -

OUT

V

< 0.2V (Shutdown), R

REFEN

= 180Ω -

LOAD

= 0A -20 -

I

= 10mA ~ 2A -20 -

Load

OUT

I

= -10mA ~ -2A -20 -

OUT

3.3V < VCNTL < 5V 130 160 -

3.3V < VCNTL < 5V - 30 -

SD

Enable 0.65 - ­Shutdown - - 0.2

subtracted from V

OUT

REFEN

.

1 2.5

50 90

2.2 - -

20
20
20

UNITS

mA

uA

mV

o

A

C

2

Advanced Power

M

Electronics Corp. AP1280MP

PIN DESCRIPTIONS

PIN SYMBOL PIN DESCRIPTION

V

IN

GND
V

OUT

V

CNTL

REFEN

BLOCK DIAGRA

Power Input Voltage.
Ground Pin
Output Voltage
Gate Drive Voltage
Reference Voltage Input and Chip Enable

REFEN

VCNTL

Current Limit

Thermal Protection

+

EA

-

VIN

VOUT

APPLICATION INFORMATION

Input Capacitor and Layout Consideration

Place the input bypass capacitor as close as possible to the AP1280MP. A low ESR
capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to
minimize parasitic resistance and inductance.
Inappropriate layout may result in large parasitic inductance and cause undesired oscillation
between AP1280MP and the preceding powe converter.

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