ANPEC APW7066 Service Manual
APW7066
Dual Synchronous Buck PWM Controll ers and One Linear Controller
Features
• Two Synchronous Buck Converters and
a Linear Regulator
• VIN range up to 12V
• Input Power Supplies Require 12V and 5V or
use 12V to generate a Shunt Regulator 5.8V
• 0.6V Reference for VOUT1 and VOUT3
with 0.8% accurate
• 3.3V Reference for VOUT2 with 0.8% accurate
• Buffered VTT Reference Output
• Three Outputs have Independent Soft-Start
and Enable
• Internal 300kHz Oscillator and Programmable
Frequency range from 70 kHz to 800kHz
• Synchronous Switching Frequency
• DDR mode or Independent Mode Selection
• Phase Shift Selection
• Power Good Function
• Short-Circuit Protection for VOUT1 and VOUT2
• Thermally Enhanced TSSOP-24 and QFN-32
Package
• Lead Free Available (RoHS Compliant)
Applications
• Graphic Cards
• DDR memory Power Supplies
• Low-Voltage Distributed Power Supplies
General Description
The APW7066 has two synchronous buck PWM
controllers and one linear cont roller with high
pre cision internal references voltage to offer accurate
outputs. The PWM controllers are designed to drive
two N-channel MOSFETs in synchronous buck
topology, a nd the linear controller drives an external
N-chan nel MOSFET. The device requires 12V and 5V
power supplies, if the 5V supply is not available,
VCC12 ca n offer an optional shunt regulator 5.8V for
5V supply.
All outputs have independent soft-start and enable
functio ns by SS/EN pins to control. Connect a capacitor
from each SS/EN pin to the ground for setting the
soft-start ti me, and pulling the SS/EN pin below 1V to
disab le regulator. Pull the SS2/EN2 to VCC, enter the
DDR mode, the SS1/EN1 controls both VOUT1 and
VOUT2, and allows VOUT2 to track VOUT1. It also
off ers the phase shift function by REFOUT pin to
sele ct the phase shift between VOUT1 an d VOUT2 in
DDR mode or Independent mode. When all SS/EN
pins exceed 3. 3V and no faults are detected, the
PGOOD pin goes high to indicate the regulators are
ready. If any of t he SS/EN pins goes below 3.2V or
any of the outputs has a fault condition, the PGOOD
pin will be pulled low .
The inte rnal oscillator is nominally 300kHz (keep the
FS/SYN C pin open or short to GND), and it offers the
programmable frequency function from 70kHz t o
800kH z; connecting a resistor from FS/SYNC to VCC
to decrease the frequency, conversely, connect a
resistor fro m FS/SYNC to GND to increase th e frequency.
The IC also provides the synch ronous freque ncy fun ction.
Connect the LGATE signal of another converter to
FS/SYNC pin; forcing the switching frequency to follow
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
www.anpec.com.tw1
APW7066
Genera l Description (Cont.)
th e external clock. The possible synchronous frequency
is from 150kHz to 800kHz. There is no Rds(on)
sensing or under-voltage sensing on APW7066.
Howe ver, it provides a simple short-circuit protection
by monitoring the COMP1 a nd COMP2 for over-voltage.
When any of two pins exce eds their trip point and the
condition persists for 1-2 internal clock cycle (3-6us
at 300kHz), the n it will shut down all regulators.
Pin Description
FB1
COMP1
COMP2
FB2
REFIN
REFOUT
SS1/EN1
SS2/EN2
SS3/EN3
VREF
DRIVE3
FB3
1
2
3
4
5
6
7
8
9
10
11
12
GND
BOTTOM
SIDE
PAD
TSSOP-24
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
VCC
BOOT1
UGATE1
VCC12
LGATE1
LGATE2
PGND
UGATE2
BOOT2
GND
PGOOD
FS/SYNC
REFIN
REFOUT
SS1/EN1
SS2/EN2
SS3/EN3
VREF
DRIVE3
Ord ering and Marking Information
APW7066
Lead Free Code
Handling Code
Temp. Range
Package Code
Package Code
R : TSSOP-P * QA : QFN-32
Operating Ambient Temp. Range
C : 0 to 70 C
Handling Code
TU : Tube TR : Tape & Reel
TY : Tray (for QFN only)
Lead Free Code
L : Lead Free Device Blank : Original Device
NC
32
FB2
COMP2
1
8
9
NC
FB3
32 LD 5x5 QFN32
°
FB1
COMP1
GND
BOTTOM
SIDE PAD
PGOOD
FS/SYNC
Top View
VCC
GND
NC
UGATE2
NC
NC
25
BOOT1
16
BOOT2
24
UGATE1
PGND_1
VCC12_1
LGATE1
LGATE2
VCC12_2
PGND_2
NC
17
APW7066 R :
APW7066 QA :
APW7066
XXXXX
APW7066
XXXXX
XXXXX - Date Code
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termin ation finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
op erations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
fo r MSL classification at lead-free peak reflow temperature.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
www.anpec.com.tw2
APW7066
Block Diag ram
SS1/EN1
SS2/EN2
SS3/EN3
3.3V
30uA
30uA
30uA
VCC VREF VCC12
5.8V
Power On Reset and
Control
Bias
Current
0.6V 3.3V
3.3V
Oscillator
Gate
Control
Logic 1
Gate
Control
Logic 2
BOOT1
UGATE1
LGATE1
BOOT2
UGATE2
LGATE2
PGOOD
Monitor COMP Pins
for Short Protection
COMP1
0.6V
FB1
REFIN
FB2
COMP2
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
3.3V
1-2 Clock
Cycle Filter
If short, Filter shut
down all outputs
GND PGND
FS/SYNC
REFOUT
VCC12
FB3
0.6V
DRIVE3
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APW7066
Ab solute Maximum Ratings
Symbol Parameter Rating Unit
VCC12 VCC12 to GND -0.3 to 15 V
VCC, separate supply VCC, separate supply -0.3 to 5.5 V
VCC, shunt regulator VCC, shunt regulator to GND -0.3 to 6 V
UGATE1, UGATE2,
BOOT1, BOOT2
LGATE1, LGATE2,
DRIVE3
FS/SYNC FS/SYNC to GND -0.3 to 15 V
REFIN, REFOUT,
PGOOD, VREF
FB1, COMP1, FB2,
COMP2, FB3
SS1/EN1, SS2/EN2,
SS3/EN3
PGND PGND to GND -0.3 to +0.3 V
TA Operating Temperature Range 0 to +70
TJ Maximum Junction Temperature +150
T
Storage Temperature Range -65 to +150
STG
TL Lead Temperature (Soldering, 10sec) 260
UGATE1, UGATE2, BOOT1, BOOT2 to GND -0.3 to 30 V
LGATE1, LGATE2, DRIVE3 to GND -0.3 to 15 V
REFIN, REFOUT, PGOOD, VREF to GND -0.3 to VCC V
FB1, COMP1, FB2, COMP2, FB3 to GND -0.3 to VCC V
SS1/EN, SS2/EN2, SS3/EN3 to GND -0.3 to VCC V
Ele ctrical Characteristics
°
C
°C
°C
°C
Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, Unless Otherwise Specified.
Parameter Test Conditions Min. Typ. Max. Units
INPUT SUPPLY POWER
Input Supply Current
(Quiescent)
Input Supply Current (Dynamic)
Shunt Regulator Output Voltage
Shunt Regulator Current
VCC; outputs disabled
VCC12; outputs disabled
VCC12; UGATEs, LGATEs CL = 1nF,
300KHz
VCC; UGATEs, LGATEs CL = 1nF,
300KHz
20mA current; ~Equivalent to 300Ω
resistor VCC to 12V
300Ω resistor VCC to 12V
4 mA
6 mA
50 mA
7 mA
5.6 5.8 6.0 V
20 60 mA
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
www.anpec.com.tw4
APW7066
ND;
DRIVE3 to FB3; compare to internal
Ele ctrical Characteristics (Cont.)
Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, Unless Otherwise Specified.
Parameter Test Conditions Min. Typ. Max. Units
INPUT SUPPLY POWER
VCC Rising 4.15 4.23 4.4 V
Power-On Reset Threshold
SYSTEM ACCURACY
Outputs 1 and 3 Reference
Voltage
Output 2 Reference Voltage 3.3V
Outputs 1 and 2 System Accuracy -0.8 0.8 %
Output 3 System Accuracy -0.8 0.8 %
OSCILLATOR
Accuracy -20 20 %
Frequency FS/SYNC pin open 240 300 360 KHz
Adjustment Range
Sawtooth Amplitude 2.1 V
Duty-Cycle Range 0 85 %
ERROR AMPLIFIER (OUT1 and OUT2)
Open-Loop Gain
Open-Loop Bandwidth
Slew Rate
EA Offset COMP1/2 to FB1/2; compare to
Maximum Output Voltage
Output High Source Current COMP1/2, VCOMP=2V
Output Low Sink Current COMP1/2, VCOMP=2V
PROTECTION AND MONITOR
Under-Voltage Threshold
(COMP1 and COMP2)
UV filter time
PGOOD Low Voltage IPGOOD = 2mA 0.1 0.3 V
LINEAR REGULATOR (OUT3)
VCC Falling 3.9 4.0 4.15
VCC12 Rising 7.55 7.8 8 V
VCC12 Falling 7.1 7.3 7.55
FS/SYNC pin: resistor to G
resistor to VCC12
RL = 10kΩ to ground
CL = 100pF, RL = 10kΩ to ground
CL = 100pF, RL = 10kΩ to ground
internal VREF/REFIN
RL = 10kΩ to ground; (may trip
short-circuit)
Causes PGOOD to go low; if there
for a filter time, implies the COMP
pin(s) is out-of-range, and shuts
down IC
Based on internal oscillator clock
frequency (nominal 300kHz = 3.3µs
clock period)
0.6 V
70 800 KHz
85 dB
15 MHz
4
2
VCC
-50 mA
45 mA
3.3
1 2
V
V
V/µs
mV
V
V
Clock
pulses
EA Offset
DRIVE3 High Output Voltage
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
VREF
2 mV
VCC12
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APW7066
Ele ctrical Characteristics (Cont.)
Operating Conditions: VCC = 5V, VCC12 = 12V, TA = 0 to 70°C, Unless Otherwise Specified.
Parameter Test Conditions Min. Typ. Max. Units
LINEAR REGULATOR (OUT3)
DRIVE3 High Output Source
Current
DRIVE3 Low Output Sink Current
VREF
Output Voltage
Output Accuracy
Source Current
REFOUT (VTTREF)
Output Voltage Determined by REFIN voltage
Offset Voltage
Source Current
Sink Current
Output Capacitance
Output High Voltage Minimum To select 0 degree phase; see Table 1
ENABLE/SOFTSTART (SS/EN 1,2,3)
Enable Threshold
Soft-Start Current
Soft-Start High Voltage End of ramp
Output High Voltage To select DDR mod; see Table 1
FS/SYNC PLL
Frequency range of Lock-in
High Voltage
GATE DRIVERS
Output1 GATE Driver Source UGATE1, LGATE1=3V, BOOT=12V 1.8 A
Output2 GATE Driver Source UGATE2, LGATE2=3V, BOOT=12V 1 A
Output1 GATE Driver Sink UGATE1, LGATE1=3V, BOOT=12V 2.5
Output2 GATE Driver Sink UGATE2, UGATE2=3V, BOOT=12V 4
Output Voltage UGATE1, UGATE2 30 V
Output Voltage LGATE1, LGATE2 12 V
1.1µF max capacitance
EN Rising
EN falling
( from LG pin of another IC, for
example)
1.5 mA
2.5 mA
3.3 V
-0.8 +0.8
2.0 mA
0.6 3.3 V
-10 +10 mV
0.2 20 mA
0.48 mA
0.1 µ
3.8 VCC
1.05
0.95
-30
3.5 V
3.8 VCC
150 800 KHz
12 V
V
µ
%
F
V
A
V
Ω
Ω
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
www.anpec.com.tw6
APW7066
Typical Application Circuit
APW706 6
DDR MODE
VOUT1
VOUT2
VOUT1(DDR)
PHASE
SHIFT 0
VCC12
VCC
VCC
COMP1
FB1
COMP2
FB2
REFIN
Optional for
shunt regulator
APW7066
VCC12
BOOT1
UGATE1
LGATE1
BOOT2
UGATE2
VIN1
VOUT1
VCC12
VIN2=VOUT1(DDR)
VOUT2
PHASE
SHIFT 90
VTTREF
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
REFOUT
VREF
PGOOD
FS/SYNC
SS1/EN1
SS2/EN2
SS3/EN3
GND PGND
LGATE2
DRIVE3
FB3
VIN3
VOUT3
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APW7066
Typ ical Application Circuit (Cont.)
APW706 6
IND EPENDENT MODE
PHASE
SHIFT 180
VTTREF
SYNCHRONOUS
FREQUENCY
VOUT1
VOUT2
VREF
PHASE
SHIFT 0
VCC12
VCC
VCC
COMP1
FB1
COMP2
FB2
REFIN
REFOUT
VREF
PGOOD
FS/SYNC
SS1/EN1
Optional for
shunt regulator
APW7066
VCC12
BOOT1
UGATE1
LGATE1
BOOT2
UGATE2
LGATE2
DRIVE3
VIN1
VOUT1
VCC12
VIN2
VOUT2
VIN3
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
SS2/EN2
SS3/EN3
GND PGND
FB3
VOUT3
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APW7066
Function Pin De scriptions
VCC
Powe r supply input pin. Connect a nominal 5V power
supply to this pin for the control circuit, or connect a
resistor (nominally 300Ω) to VCC12 for a shunt
regulator function (typical 5.8V). It is recommended
that a de coupling capacitor (1 to 10uF) is connected
to the GND for noise decoupling.
GND
This pin is the signal ground pin. The metal thermal
pad und er the package is the IC substrate; connects
the GND pin and metal thermal pad together on the
board, and ties to the good GND p lane for electrical
and thermal con duction.
VC C12
Pow er supply input pin. Connect a no minal 12V power
su pply to this p in for the ga te driver. It is re commended
that a decoupling ca pacitor (1 to 10uF) is connected
to the GND for n oise decoupling.
PGND
This pin is the power grou nd pin for the gate driver a nd
linear driver circuit. It should be tied to the GND.
FB1, FB 2, FB3
These pins are th e inverting inputs of the error amplifiers of their respective regulators. They are used to
set the output voltage and the compensation
components.
SS1/EN1, SS2/EN2, SS3/EN3
These pins provide two functions. Connect a capacitor
to the GND fo r setting the soft-start time. Use an open
drain log ic signal to pull the SS/EN pin low to disable
the respective output, leave open to enable the respe ctive output.
COMP1 , COMP2
These pin s are the outputs of error amplifiers of their
respect ive regulators. They are used to set the
compensa tion components.
UGATE1, UGATE2
These pins provide t he gate driver for the upper
MOSFETs of VOUT1 a nd VOUT2.
LGATE1, LGATE2
These pins provide the gate driver for the lower
MOSFETs of VOUT1 and VOUT2.
BOOT1, BOOT2
These pins provide the bootstrap voltage to the gate
driver for driving the upper MOSFETs. It can be
connected to a power voltage directly, but the difference voltage between the BOOT a nd VIN must be high
enoug h to drive the upper MOSFETs.
REFIN
This pin is th e refere nce input voltag e of error amplifier
of the VOUT2. It also provides the volta ge into a buffe r,
which is ou t on the REFOUT pin.
REFOUT
This pin provides a buffed voltage, which is from REFIN
pin. In Independent mode, it can be used by other
ICs. In DDR mode, it is from th e VOUT1, and can be
use d as the VTT buffer.
This p in also uses to select th e phase shift (see table1 ).
When this pin pulls to VCC, the buffer is disabled and
the REFOUT is not available for use. It is reco mmended
that a 0.1u F capacitor is connected to the ground for
stability.
VR EF
This p in provides a 3.3V refe rence voltage, which can
be used by the REFIN pin or other ICs as a voltage
reference. It is recommended that a 1uF capacitor is
connected to ground for stability.
DRIVE3
This pin drives the gate of an external N-channel
MOSFET for line ar regulator.
PGOOD
This pin is an open drain device; connect a pull up
resistor to the VCC for PGOOD function.
FS/SYN C
This pin is used to adjust the switching frequency.
Con necting a resistor fro m FS/SYNC pin to the ground
increases the switching frequency. Conversely, connecting a resistor from this pin to the VCC12 reduces
the swit ching frequency. In addition, this pin also
provide s synchronous frequency function. An e xternal
clock can be fed into this pin, and force the switching
frequency to follow the external clock.
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
www.anpec.com.tw9
APW7066
Typ ical Characteristics
VOUT1 Po wer Up
VCC12(5V/div)
VCC(2V/div)
VOUT1(1V/div)
SS1(2V/div)
Time(5ms/div)
VOUT2 Po wer Up
VCC12(5V/div)
VCC(2V/div)
VOUT2(2V/div)
SS2(2V/div)
Time(5ms/div)
VOUT3 Po wer Up VREF Power Up
VCC12(5V/div)
VCC(2V/div)
VOUT3(1V/div)
SS3(2V/div)
Time(5ms/div)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
VCC12(5V/div)
VCC(2V/div)
VREF(2V/div)
SS2(2V/div)
Time(5ms/div)
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APW7066
Typ ical Characteristics (Cont.)
VOUT1 Po wer Up
VOUT1(1V/div)
SS1(2V/div)
UGATE1(20V/div)
LGATE1(10V/div)
Time(2ms/div)
VOUT2 Po wer Up
UGATE2(20V/div)
LGATE2(10V/div)
VOUT2(5V/div)
SS2(2V/div)
Time(2ms/div)
DDR Mod e Power Up
VREF(2V/div)
VOUT2(2V/div)
VOUT1(1V/div)
SS1(2V/div)
Time(2ms/div)
Copyright ANPEC Electronics Corp.
Rev. A.4 - Jun., 2005
SS2=VCC
VOUT1= REFIN
Phase Shift 0 degrees
LG1(10V/div)
LG2(10V/div)
Time(1u s/div)
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