ANPEC APU0071-002WE-TY, APU0071-001WE-TY Datasheet

80 Segment / 16 Common Controller

for Dot Matrix LCD

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.

FEATURES DOT MATRIX LCD CONTROL-

LER & DRIVER

APU0071 is a dot matrix LCD driver & controller
LSI that is fabricated by low power CMOS
technology. It is capable of displaying 1-line 16

characters or 2 line 16 characters with 5 × 8 dots
format.

FUNCTIONS

Character type dot matrix LCD driver & controller.

• Easy interface with 4-bit or 8-bit MPU.

• Internal driver : 16 common and 80 segment

signal output.

• Display character pattern : 5 × 7 dots format

(224 kinds)

• Direct programming of the special character

patterns by character Generator RAM.

• Mask open for programming customer charac-

ter patterns

• V arious instructions function.

• Automatic power on reset.

ORDERING INFORMATION

Internal Memory

- Character Generator ROM (CGROM) : 7840bits
(224 characters × 5 × 7dot)

- Character Generator RAM (CGRAM) : 160 bit (4­characters × 5 × 8 dot)

- Display Data RAM (DDRAM) : 256bits (32
characters × 8bits)

• Low power operation

- Power supply voltage range : 2.7 ~ 5.5V (VDD)

- LCD drive voltage range : 3.0 ~ 7.0 (VDD-V5)

• CMOS process

• Duty cycle : 1/16

• Built-in oscillator

• Low power consumption

• Internal divide resistor for LCD driving voltage

• Available for COG

APU0071

ROM Code

Package Type

Handling Code

ROM Code
001 : Standard
002 : Customer

Package Type
W : C O G

Handling Code
TY : Tray

E

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw2

BLOCK DIAGRAM

Oscillator

Power On Reset

(POR)

RESETB

16-bit

shift

register

Common

driver

Input

buffer

Timing generator

EXTCLK

TEST

EXT_INT

C1 ~ C16

Segment

driver

80-bit

latch

circuit

80-bit

shift

register

(Bidir.)

Display

data

RAM

(DDRAM)

32*8 bits

Instruction

Decoder

Address

counter

Instruction

register

(IR)

8

Data

register

(IR)

8

8

DB0

~DB7

RS
RW
E

Character
generator

RAM

(CGRAM)

160 bits

Character
generator

RAM

(CGROM)

7840 bits

Cursor

blink

control

circuit

Parallel to Serial converter

V

DD

V

1

V

2

V

3

V

4

V

5

8

8

V

DD

GND
(V

SS)

S1 ~ S80

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw3

PAD DIAGRAM

APU0071

PAD Diagram

AP

93
94
95
96
97
98
99

89
90
91
92

56

55

54

53

52

51

50

59

58

57

49

47

46

45

44

71

70

69

68

67

66

65

74

73

72

64

63

62

61

60

86

85

84

83

82

81

80

88

87

79

78

77

76

75

111
112
113
114

104
105
106
107
108
109
110

100
101
102
103

115
116
117
118

48

39
40
41
42
43

120

121

122

123

124

125

126

119

31

38373635343332

PAD NO. : 1 ~ 30

PAD PITCH :

≥

120

AL PAD SIZE : 96

×

96

AL PAD WINDOW: 70

×

70

AU PAD SIZE : 84

×

84

UNIT :

µ

m

C8C7C6C5C4C3C2

C1

7
6
5
4

9
8

26

27

28

24

25

29

30

18

19

20

21

17

22

23

11

12

13

10

14

15

16

1

3
2

C16

C15

C14

C13

C12

C11

C10

C9

S22

S21

S30

S29

S28

S27

S26

S25

S24

S23

S40

S39

S38

S37

S36

S35

S34

S33

S32

S31

S50

S49

S48

S47

S46

S45

S44

S43

S42

S41

S60

S59

S58

S57

S56

S55

S54

S53

S52

S51

S20

S19

S18

S17

S16

S15

S14

S13

S12

S11

S10

S9

S8

S7

S6

S75

S74

S73

S72

S71

S70

S69

S68

S67

S66

S65

S64

S63

S62

S61

S80

S79

S78

S77

S76

S5

S4

S3

S2

S1

V

SS

DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
E
R_NW
RS

EXTCLK

EXT_INT

OSC_TS
POR_TS

EXT_RST

M_TS

CLK1_TS

Dummy

Chip size

¡G

6500 x 1140

( 0 , 0 )

V

SS

V

SS

V

5

V

5

V

5

V

3

V

2

V

DD

V

DD

V

DD

PAD NO. : 31 ~ 126

PAD PITCH : 80

AL PAD SIZE : 62

×

102

AL PAD WINDOW: 36

×

76

AU PAD SIZE : 50

×

90

UNIT :

µ

m

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw4

PAD LOCATION

Pad Name X Y Pad Name X Y Pad Name X Y

1 POR_TS -2650.9 -429.84 43 S5 2843.35 404.67 85 S47 -516.65 404.67
2 OSC_TS -2530.9 -429.84 44 S6 2763.35 404.67 86 S48 -596.65 404.67
3 EXTCLK -2410.9 -429.84 45 S7 2683.35 404.67 87 S49 -676.65 404.67
4 EXT_INT -2290.9 -429.84 46 S8 2603.35 404.67 88 S50 -756.65 404.67
5VSS-2158.65 -480.84 47 S9 2523.35 404.67 89 S51 -836.65 404.67
6VSS-2038.65 -480.84 48 S10 2443.35 404.67 90 S52 -916.65 404.67
7VSS-1918.65 -480.84 49 S11 2363.35 404.67 91 S53 -996.65 404.67
8V5-1728.70 -480.84 50 S12 2283.35 404.67 92 S54 -1076.65 404.67
9V5-1608.70 -480.84 51 S13 2203.35 404.67 93 S55 -1156.65 404.67

10 V

5

-1488.70 -480.84 52 S14 2123.35 404.67 94 S56 -1236.65 404.67

11 V

3

-1305.75 -480.84 53 S15 2043.35 404.67 95 S57 -1316.65 404.67
12 DUMMY -1119.15 -480.84 54 S16 1963.35 404.67 96 S58 -1396.65 404.67
13 V

2

-940.20 -480.84 55 S17 1883.35 404.67 97 S59 -1476.65 404.67

14 V

DD

-749.60 -480.84 56 S18 1803.35 404.67 98 S60 -1556.65 404.67

15 V

DD

-629.60 -480.84 57 S19 1723.35 404.67 99 S61 -1636.65 404.67

16 V

DD

-509.60 -480.84 58 S20 1643.35 404.67 100 S62 -1716.65 404.67
17 M_TS -333.50 -480.84 59 S21 1563.35 404.67 101 S63 -1796.65 404.67
18 CLK1_TS -102.10 -480.84 60 S22 1483.35 404.67 102 S64 -1876.65 404.67
19 EXT_RST 131.70 -480.84 61 S23 1403.35 404.67 103 S65 -1956.65 404.67
20 RS 358.80 -480.84 62 S24 1323.35 404.67 104 S66 -2036.65 404.67
21 R_NW 594.20 -480.84 63 S25 1243.35 404.67 105 S67 -2116.65 404.67
22 E 821.30 -480.84 64 S26 1163.35 404.67 106 S68 -2196.65 404.67
23 DB0 1054.80 -480.84 65 S27 1083.35 404.67 107 S69 -2276.65 404.67
24 DB1 1286.80 -480.84 66 S28 1003.35 404.67 108 S70 -2356.65 404.67
25 DB2 1518.40 -480.84 67 S29 923.35 404.67 109 S71 -2436.65 404.67
26 DB3 1750.40 -480.84 68 S30 843.35 404.67 110 S72 -2516.65 404.67
27 DB4 1982.00 -480.84 69 S31 763.35 404.67 111 S73 -2596.65 404.67
28 DB5 2214.00 -480.84 70 S32 683.35 404.67 112 S74 -2676.65 404.67
29 DB6 2445.60 -480.84 71 S33 603.35 404.67 113 S75 -2756.65 404.67
30 DB7 2631.91 -429.84 72 S34 523.35 404.67 114 S76 -2836.65 404.67
31 C1 3149.01 -475.85 73 S35 443.35 404.67 115 S77 -2916.65 404.67
32 C2 3149.01 -395.85 74 S36 363.35 404.67 116 S78 -2996.65 404.67
33 C3 3149.01 -315.85 75 S37 283.35 404.67 117 S79 -3076.65 404.67
34 C4 3149.01 -235.85 76 S38 203.35 404.67 118 S80 -3156.65 404.67
35 C5 3149.01 -155.85 77 S39 123.35 404.67 119 C16 -3137.66 95.82
36 C6 3149.01 -75.85 78 S40 43.35 404.67 120 C15 -3137.66 15.82
37 C7 3149.01 4.15.00 79 S41 -36.65 404.67 121 C14 -3137.66 -64.18
38 C8 3149.01 84.15 80 S42 -116.65 404.67 122 C13 -3137.66 -144.18
39 S1 3163.35 404.67 81 S43 -196.65 404.67 123 C12 -3137.66 -224.18
40 S2 3083.35 404.67 82 S44 -276.65 404.67 124 C11 -3137.66 -304.18
41 S3 3003.35 404.67 83 S45 -356.65 404.67 125 C10 -3137.66 -384.18
42 S4 2923.35 404.67 84 S46 -436.65 404.67 126 C9 -3137.66 -464.18

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw5

PIN DESCRIPTION

PIN

Inp u t /

Output

Name Description Interface

V

DD

For logical circuit (+3v,+5v)

VSS (GND)

0V (GND)

V2,V3,V

5

P

Power supply & LCD
Bias pin

Bias voltage level for LCD driving

Power
Supply

S1 ~ S80 Output Segment output Segment signal output for LCD driving LCD
C1 ~ C16 Output Common output Comm on signal output for LCD driving LCD

EXTCLK Input External clock Input

When using external clock, used as clock input pin.
When using internal oscillator, connect to V

DD

or VSS.

External

clock

EXT_INT Input

Ex ternal / Internal
oscillator clock select

When EX T_INT = “High”, external clock is used.
Wh en “L o w”, ins tru c tio n o sc illa to r is us e d .

MPU

RS Inpu t Re g is ter select

Used as register selection input.
When RS = “High”, data register is selected.
When RS = “Low”, instruction register is selected.

R_NW Input Read / Write

Used as read / write selection input.
When R W = “High”, read operation.
When RW = “Low”, write operation.

E Input Read / Write enable Used as read / write enable signal.
DB0 ~ DB3

When 8-bit bus mode, used as low order bi-directional
data bus.
During 4-bit bus mode open these pins.

DB4 ~ DB7

Inpu t /

Output

Da ta Bus 0 ~ 7

When 8-bit bus mode, used as high order bi-directional
data bus. In case of 4-bit bus mode, used as both high
and low order.
DB7 is used for Busy Flag output during read
instruction operation.

EXT_RST Input Reset

If it is necessary to initialize the system by hardware,
force “Low”, level signal to this terminal about 1.2 ms.

MPU

OSC_TS Output T est Pin Internal oscillator test pin. Open this pin.
POR_TS Output T est Pin Internal test pin. Open this pin.
M_TS Output T est Pin Internal test pin. Open this pin.
CLK1_TS Output T est Pin Internal test pin. Open this pin.

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw6

FUNCTION DESCRIPTION

1. SYSTEM INTERFACE

This chip consists of two kinds of interface type with MPU : 4-bit bus and 8-bit bus.
4-bit bus and 8-bit bus is selected by DL bit of function set in the instruction register.

During read or write operation, two 8-bit registers are used. One is the data register (DR); the other is the
instruction register (IR) .

The data register (DR) is used as a temporary data storage place for being written into or read from
DDRAM / CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,
reading from or writing into RAM, is done automatically.
Thus, after MPU reads DR data, the data in the next DDRAM / CGRAM address is transferred into DR
automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM / CGRAM
automatically.

The Instruction register (IR) is used only to store instruction code transferred from MPU.
MPU cannot read data from instruction register.
Table 1. Various kinds of operation according to RS and R / W bits.

RS R / L Operation

0 0 Instruction Write operation (MPU W rites Instruction into IR)
0 1 Read Bus y flag (DB7) a nd address counter (DB 0 ~ DB6)
1 0 Data Write operation (MPU Writes data into DR)
1 1 Data Read op eration (MP U Writes data into DR)

The register selection depends on RS input pin setting in both 4-bit bus mode.

2. BUSY FLAG (BF)

BF = “High” it indicates that the internal operation is being processed. So during this time the next instruc­tion cannot be accepted. BF can be read, when RS = Low and R / W = High (Read instruction Operation) ,
through DB7 port.
Before exciting the next instruction, be sure that BF is not High.

3. ADDRESS COUNTER (AC)

Address Counter (AC) stores the address of DDRAM / CGRAM that are transferred from IR.
After writing into (reading from) DDRAM / CGRAM data, AC is increased (decreased) by 1 automatically.
When RS = “Low”, and R / W = “High”, AC value can be read through DB0 ~ DB6 ports.

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw7

4. DISPLAY DATA RAM (DDRAM)

DDRAM stores 8bits character code in CGROM / CGRAM and its maximum number is 32 (32 Characters)
. DDRAM address is set by the address counter (AC) as a hexadecimal number.

AC6 AC5 AC4 AC3 AC2 AC1 AC0

MSB LSB

HEX HEX

4-1. DDRAM addressing mode 0 (A = 0) (1 Line)

In this addressing mode, the address range of DDRAM is 00H ~ 0FH.

01 02 03 04 05 06 07 0A 0B 0C 0 D 0E0F

12345678910111213141516

08 0900

01 02 03 04 05 06 07 08 0A 0B 0C 0D 0E 0F

12345678910111213141516

09 00

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

COM1~COM8

COM9~COM16

COM1~COM8

COM9~COM16

COM1~COM8

COM9~COM16

DDRAM Address

Display Position

After shift left

After shift right

4-2. DDRAM addressing mode 1 (A = 1) (2 Line)

In this addressing mode, the address range of DDRAM is 00H ~ 0FH and 40H ~ 4FH.

After shift right

41 42 43 44 45 46 47 48 49 4A 4B 4 C 4D 4E

12345678910111213141516

COM9

COM16

40

00 01 02 03 04 05 06 07 08 09 0A 0 B 0C 0D 0E 0F

12345678910111213141516

COM1
COM8

40 41 42 43 44 45 46 47 48 49 4A 4 B 4C 4D 4E 4F

12345678910111213141516

COM9

COM16

DDRAM Address

Display Position

DDRAM Address

Display Position

After shift left

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0 E 0F

12345678910111213141516

COM1
COM8

40

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

12345678910111213141516

COM9

COM16

00

01 02 03 04 05 06 07 08 09 0A 0B 0 C 0D 0E

12345678910111213141516

COM1
COM8

4F

00

0F

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw8

5. CHARACTER GENERATOR RAM (CGRAM)

CGRAM is used for user defined character pattern. The format of the character pattern is 5 × 7 dots
except for the cursor position and has a maximum of 4 characters. To use the character pattern in
CGRAM write the character code into DDRAM as shown in table 2.
Table 2. Relationship between character Code (DDRAM) and Character Pattern (CGRAM)

Character Code ( DDRAM data )

765432104321043210

CGRAM address CGRAM data

0000

∗∗

000000001110

000011

0 0 01

00010

10001

00011

11111

00100

1 0 0 0 1

00101

10001

00110

10001

00111

00000

Pattern

Number

Pattern 1

cursor position

.................

0000

∗∗

0011

11
11
11
11
11
11
11

000
001
010
011
100
101
110
111

1
1
1
1
1
1
1
0

1
0

1
00

0

1

1

1

1

1

0

1 1

00
0
0
0
0

1

0

0

0

0

0

1
0

0
0
0
0

Pattern 4

Note : The asterisk means "don't care".

.................

.................

.................

.................

cursor position

Copyright  ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002

APU0071

www.anpec.com.tw9

6. CHARACTER GENERATOR ROM (CGROM)

CGROM generates 5 × 5 × 7 character pattern from character generate code in DDRAM. CGROM has 5 ×
7-dot 224-character pattern excluding cursor position. The relationship between character code and
character pattern can be referred to Table 5.

7. TIMING GENERATION CIRCUIT

Timing generation circuit generates clock signals for the internal operations.

8. LCD DRIVER CIRCUIT

LCD driver circuit has 16 common and 80 segment output signals for LCD driving.
Data from CGRAM / CGROM is transferred to 80-bit segment shift register in a serially, which is then it is
stored to 80-bit segment output latch. When each COM is selected by a 16-bit common register, the
segment data also outputs through segment driver from 40-bit segment output latch.

9. CURSOR / BLINK CONTROL CIRCUIT

It controls cursor / blink ON / OFF at the cursor position.

INSTRUCTION DESCRIPTION

1. OUTLINE

To overcome the speed difference between the internal clock of APU0071 and the MPU clock, the
APU0071 per-forms an internal operation by storing control information to IR or DR. The internal operation
is determined according to the signal from MPU, composed of read / write and data bytes.
Instruction can be divided into four types :

1-1. APU0071 function set instructions (set display methods, set data length, etc.)
1-2. Address set instructions to internal RAM
1-3. Data transfer instructions with internal RAM
1-4. Others
The address of internal RAM is automatically increased or increased by 1.

Note : During an internal operation, the Busy Flag (DB7) is High. Busy Flag check must precede the next

instruction.