ANPEC APU0063YE-TY, APU0063QE-TY Datasheet
80 CH Driver for Dot Matrix LCD
Copyright ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
APU0063
www.anpec.com.tw1
PRELIMINARY
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
FEATURES GENERAL DESCRIPTION
The APU0063 is a LCD driver LSI that is fabricated
by low power CMOS technology. Basically this LSI
consists of 40 × 2bit bi-directional shift register, 40
× 2bit data latch and 40 × 2bit driver.
APPLICATIONS
• Dot matrix LCD driver with 80-channel output.
• Input / Output signal
• Output ; 40 × 2 channel waveform for LCD
driving
• Input ; - Serial display data and control pulse
from controller LSI .
ORDERING INFORMATION
Display driving bias ; static-1/5
• Power supply voltage ; +5V ± 10%
+3V ± 10%
• Supply voltage range for display : ≤ 10V
• Negative display voltage :
0 ≥
V
EE
≥
VDD-10V
• CMOS Process
• Interface
APU0063
Package Type
Handling Code
Package Type
Q : QFP
Y : Chip
Handling Code
TY : Tray
E
Driver (cascade connection) Controller
Other APU0065 APU0066
Copyright ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
APU0063
www.anpec.com.tw2
PRELIMINARY
Pre-Stage
Output Voltage
Multiplexor
Part1
End Stage
Output Voltage
Multiplexor
Part1
LATCH part1
SHIFT part 1
SC1~SC40
DL1
DR1
latch clock
register clock
SHL1 CL1
CL2
V
1S
V
2S
End Stage
Output Voltage
Multiplexor
Part2
LATCH part 2
SHIFT part 2
SC41~SC80
DR2
SHL2
DL2
V1V
2
PART 1
PART 2
M
V3V
4
V
1S
V
2S
Figure 1.Block diagram of APU0063
Copyright ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
APU0063
www.anpec.com.tw3
PRELIMINARY
APU0063
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
S30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
M
DR2
DL2
DR1
DL1
CL2
V
DD
NC
NC
SHL2
SHL1
CL1
GND
V
1
V
EE
NC
NC
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
S72
S73
S74
S75
S76
S77
S78
S79
S80
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S71
S41
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
V
2
V
3
V
4
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
Figure 2. QFP100 Top View
Copyright ANPEC Electronics Corp.
Rev. A.07 - FEB., 2002
APU0063
www.anpec.com.tw4
PRELIMINARY
PIN DESCRIPTION-QFP100
NOTE : Input pin can not be floated,or it will cause large leakage current.
PIN(NO.)
V1 ~ V4(32 ~ 35)
INPUT
¡þ
OUTPUT
NAME
Negative Supply
Voltage
Altemated Signal for
LCD Driver Output
DESCRIPTION
The signal enable the latch, it is
negative senstive latched.
Power
INTERFACE
Power SupplyVEE(31)
VDD(42) Power
VSS(36) Power
Operating Voltage
Operating Voltage
Bias VoltageInput
Input
M(48)
For LCD driver circuit
(0 V
EE
VDD-10V)
For logic circuit
(+5V 10% ,+3V
10%)
0V(GND)
Bias Voltage level for LCD drive
This is the signal for LCD twisting
Selection of the shift directon of
Part1 shift register
The signal enable the shift
register, it is negative edge-trigger.
SHL1
V
DD
V
SS
DL1
Output
Input
DR1
Input
Output
CL1(37)
CL2(43)
SHL1(38)
DL1, DR1
(44, 45)
Controller
or
APU0066
SC
1
~ SC
40
Selection of the shift directon of
Part2 shift register
SHL2
V
DD
V
SS
DL2
Output
Input
DR2
Input
Output
SHL2(39)
DL2, DR2
(46, 47)
SC
41
~ SC
80
Power Supply
Power Supply
Power Supply
Controller
Controller
Controller
Controller
LCD
Controller
Controller
or
APU0066
LCD
Input
Input
Input
Input
Output
Output
Input
Input
Output
Output
Data Latch Clock
Data Shift Clock
Shifting Direction
Control Signal of
Part1
Shifting Direction
Control Signal of
Part2
Data Interface
LCD Driver
Data Interface
LCD Driver
Data input / output pf Part1 shift
register
Data input / output pf Part2 shift
register
LCD driver output of Part1
LCD driver output of Part2
≥≥
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