Ultra-Low On-Resistance, 6A Dual Load Switch with Soft Start
Features
•16mΩ(Typical) On-resistance per Channel
•6A Continuous Current
•Soft Start Time Programmable by External
Capacitor
•Wide Input Voltage Range (VIN): 0.8V to 5.5V
•Supply Voltage Range (VBIAS): 3V to 5.5V
•Output Discharge when Switch Disabled
•Reverse Current Blocking when Switch Disabled
•Over-Temperature Protection
•Enable Input
•Lead Free and Green Devices Available (RoHS
Compliant)
Applications
•Notebook
•AIO PC
General Description
The APL3533 is an ultra-low on-resistance, dual powerdistribution switch with external soft start control. It integrates two N-channel MOSFETs that can deliver 6A continuous load current each.
The device integrates over-temperature protection. The
over temperature protection function shuts down the Nchannel MOSFET power switch when the junction temperature rises beyond 160oC and will automatically turns
on the power switch when the temperature drops by 40oC.
The device is available in lead free TDFN2x3-14A
packages.
Simplified Application Circuit
V
Off
On
V
V
BIAS
BIAS
IN1
IN2
VIN1VOUT1
APL3533
VIN2
VOUT2
EN1
EN2
SS1
SS2
GND
www.anpec.com.tw1
V
OUT1
V
OUT2
Pin Configurations
14 VOUT1VIN1 1
VIN1 2
EN1 3
BIAS 4
EN2 5
VIN2 6
VIN2 7
TDFN2x3-14A
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant)and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
(Note 1)
Symbol Parameter Rating Unit
V
BAIS to GND Voltage -0.3 ~ 6 V
BIAS
V
, V
VIN1, VIN2 to GND Voltage -0.3 ~ 6 V
IN1
IN2
V
, V
OUT1
V
, V
EN1
TJ Maximum Junction Temperature -40 ~ 150
T
STG
T
SDR
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
VOUT1, VOUT2 to GND Voltage -0.3 ~ 6 V
OUT2
EN1, EN2 to GND Voltage -0.3 ~ 6 V
EN2
Storage Temperature -65 ~ 150
Maximum Lead Soldering Temperature (10 Seconds) 260
o
C
o
C
o
C
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol Parameter Typical Value
θJA
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Junction-to-Ambient Resistance in Free Air
Copyright ANPEC Electronics Corp.
(Note 2)
80
www.anpec.com.tw2
Rev. A.2 - Mar., 2013
Unit
o
C/W
APL3533
Recommended Operating Conditions
Symbol
V
BIAS Input Voltage 3.0 ~ 5.5 V
BIAS
V
, V
IN1
VIN1, VIN2 Input Voltage 0.8 ~ 5.5 V
IN2
I
VOUT1 or VOUT2 Output Current (single channel) 0 ~ 6 A
OUT
PD Maximum Power Dissipation, TA=50oC
ParameterRangeUnit
(Note4)
0.94 W
(Note 3)
VIH EN1, EN2 Logic High Input Voltage 1.2 ~ 5.5 V
VIL EN1, EN2 Logic Low Input Voltage 0 ~ 0.4 V
TA Ambient Temperature -40 ~ 85
TJ Junction Temperature -40 ~ 125
Note 3 : Refer to the typical application circuit.
Note 4 : Refer to the thermal consideration on page 15.
Electrical Characteristics
Unless otherwise specified, these specifications apply over V
Typical values are at TA=25oC.
Symbol
Parameter Test Conditions
SUPPLY CURRENT
I
BIAS
ISD
BIAS Supply Current (both
channels)
BIAS Supply Current (single
channel)
BIAS Supply Current at
Shutdown
No load, V
No load, V
No load, V
No load, V
VIN Off-State Supply Current
I
OFF
(per channel)
No load, V
No load, V
No load, V
Reverse Leakage Current (per
channel)
V
EN1,2
=0V, V
UNDER-VOLTAGE LOCKOUT (UVLO)
Rising BIAS UVLO Threshold V
BIAS UVLO Hysteresis - 0.1 - V
rising 1.9 2.4 2.9 V
BIAS
POWER SWITCH
= V
IN1
IN2
= 0.8V~5.5V, V
EN1
= V
EN2=VBIAS
=5V and TA= -40~85oC.
APL3533
Min. Typ. Max.
=5V =V
BIAS
=5V, V
BIAS
=5V, V
BIAS
=5V, V
BIAS
=5V, V
BIAS
=5V, V
BIAS
=5V, V
BIAS
=0V - 0.1 16
IN1,2
=5V
EN1,2
EN1
EN1,2
EN1,2
EN1,2
EN1,2
EN1,2
=5V, V
=0V
EN2
=0V - - 2
=0V, V
=0V, V
=0V, V
=0V, V
=5V - 0.1 8
IN1,2
=3.3V - 0.1 3
IN1,2
=1.8V - 0.1 2
IN1,2
=0.8V - 0.1 1
IN1,2
-
-
60 90
50 -
o
C
o
C
Unit
µA
µA
µA
µA
µA
µA
µA
µA
I
=200mA, TJ= 25oC
R
DS(ON)
Power Switch On Resistance
VOUT Discharge Resistance V
OUT
I
=200mA, TJ= -40~125oC
OUT
I
=200mA, TJ= 25oC
OUT
I
=200mA, TJ= -40~125oC
OUT
=0V, VOUT1 or VOUT2 force 1V - 150 180
EN1,2
Channel 1
Channel 2
- 16 18
-
- 24
- 16 18
-
- 24
mΩ
mΩ
mΩ
mΩ
Ω
Copyright ANPEC Electronics Corp.
www.anpec.com.tw3
Rev. A.2 - Mar., 2013
APL3533
, EN2=low, measured at
Electrical Characteristics
Unless otherwise specified, these specifications apply over V
Typical values are at TA=25oC.
1 VIN1
2 VIN1
3 EN1 Enable input of switch 1. Logic high turns on switch 1. The EN1 pin cannot be left floating.
4 BIAS Bias voltage input pin for internal control circuitry.
5 EN2 Enable input of switch 2. Logic high turns on switch 2. The EN2 pin cannot be left floating.
6 VIN2
7 VIN2
8 VOUT2
9 VOUT2
10 SS2
11 GND Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
12 SS1
13 VOUT1
14 VOUT1
Power supply Input of switch 1. Connect this pin to an external DC supply.
Power supply Input of switch 2. Connect this pin to an external DC supply.
Switch 2 output.
Soft start control of switch 2. A capacitor from this pin to ground sets the VOUT2’s rise slew
rate.
Soft start control of switch 1. A capacitor from this pin to ground sets the VOUT1’s rise slew
rate.
Note: The table Contains soft-start time values measured on a typical device. The soft-start times shown are only valid for the powerup sequence where VIN and V
are already in steady state condition, and EN pin is asserted high.
A under-voltage lockout (UVLO) circuit monitors the VBIAS
pins voltage to prevent wrong logic controls. The UVLO
function initiates a soft-start process after the BIAS supply voltages exceed rising UVLO voltage threshold during powering on.
Power Switch
The power switch is an N-channel MOSFET with a ultralow R
MOSFET prevents a reverse current flowing from the VOUT
back to VIN. When IC is in UVLO state, the internal parasitic diodes connected from VOUT to VIN will be forward
biased.
Soft-start
The APL3533 Provides an adjustable soft-start circuitry
to control rise rate of the output voltage and limit the current surge during start-up. The soft-start time is set with a
capacitor from the SS pin to the ground.
. When IC is in shutdown state (V
DS(ON)
EN1,2
=0V), the
Enable Control
The APL3533 has a dedicated enable pin (EN). A logic
low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the
output through initiation of a new soft-start cycle.
Over-Temperature Protection (OTP)
When the junction temperature exceeds 160oC, the internal thermal sense circuit turns off the power FET and
allows the device to cool down. When the device’s junction temperature cools by 40oC, the internal thermal
sense circuit will enable the device, resulting in a pulsed
output during continuous thermal protection. Thermal
protection is designed to protect the IC in the event of
over temperature conditions. For normal operation, the
junction temperature cannot exceed TJ=+125oC.
The APL3533 has a built-in reverse current blocking circuit to prevent a reverse current flowing through the body
diode of power switch from the VOUT back VIN pin when
power switch disabled. The reverse current blocking circuit is not active before V
is ready. When IC is in UVLO
BIAS
state, the internal parasitic diodes of power switch connected from VOUT to VIN will be forward biased.
Otherwise, VOUT should not be higher than VBIAS, and
VBIAS must be higher than the voltage of any other input
pin, the reason is that the internal parasitic diodes connected from VOUT to VBIAS will be forward biased.
Capacitor Selection
The APL3533 requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge
currents, more parasitic inductance needs more input
capacitance.
For normal applications (except OTP or output short circuit has occurred), the recommended input capacitance
of VIN is 1µF and output capacitance of VOUT is 0.1µF at
least. Please place the capacitors near the APL3533 as
close as possible.
A bulk output capacitor, placed close to the load, is recommended to support load transient current.
Soft-Start Capacitor
The soft-start capacitor on SS pin can reduce the inrush
current and overshoot of output voltage. The capacitor is
charge to VSS with a constant current source. This results
in a linear charge of the soft-start capacitor and thus the
output voltage.
Thermal Consideration
The APL3533 maximum power dissipation depends on
the differences of the thermal res istance and temperature between junc tion and ambient air. The power dissipation PD across the device is:
PD = (TJ - TA) / θ
JA
where (TJ-TA) is the temperature difference between the
junction and ambient air. θJA is the thermal resistance
between junction and ambient air. Assuming the TA=25°C
and maximum TJ=160°C (typical thermal limit threshold),
the maximum power dissipation is calc ulated as:
P
=(160-25)/80
D(max)
= 1.68(W)
For normal operation, do not exceed the maximum operating junction temperature of TJ = 125°C. The calc ulated
power dissipation should be less than:
The PCB layout should be carefully performed to maximize thermal dissipation and to minimize voltage drop,
droop and EMI. The following guidelines must be
considered:
1. Please place the input capacitors near the VIN pin as
close as possible.
2. Output decoupling capacitors for load must be placed
near the load as close as possible for decoupling high
frequency ripples.
3. Locate APL3533 and output capacitors near the load to
reduce parasitic resistance and inductance for excellent
load transient performance.
4. The negative pins of the input and output capacitors
and the GND pin must be connected to the ground plane
of the load.
5. Keep VIN and VOUT traces as wide and short as
possible.