ANALOG DEVICES UG-293 Service Manual

Evaluation Board User Guide

One Technology Way • P. O . Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel : [phone] • Fax : [phone] • www.analog.com

UG-293

Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters

FEATURES

Full featured evaluation board for the

AD9643/AD9613/AD6649/AD6643

SPI interface for setup and control
External or AD9523 clocking option
Balun/transformer or amplifier input drive options
LDO regulator power supply
VisualAnalog and SPI controller software interfaces

EQUIPMENT NEEDED

Analog signal source and antialiasing filter
Sample clock source (if not using the on-board oscillator)
2 switching power supplies (6.0 V, 2.5 A), CUI EPS060250UH-

PHP-SZ, provided
PC running Windows® 98 (2nd ed.), Windows 2000,

Windows ME, or Windows XP
USB 2.0 port recommended (USB 1.1 compatible)

AD9643, AD9613, AD6649, or AD6643 evaluation board
HSC-ADC-EVALCZ FPGA-based data capture kit

SOFTWARE NEEDED

VisualAnalog
SPI controller

TYPICAL MEASUREMENT SETUP

DOCUMENTS NEEDED

AD9643, AD9613, AD6649, or AD6643 data sheet
HSC-ADC-EVALCZ data sheet
AN-905 Application Note, VisualAnalog Converter Evaluation

Tool Version 1.0 User Manual

AN-878 Application Note, High Speed ADC SPI Control Software
AN-877 Application Note, Interfacing to High Speed ADCs via SPI
AN-835 Application Note, Understanding ADC Testing and

Evaluation

GENERAL DESCRIPTION

This user guide describes the AD9643, AD9613, AD6649, and

AD6643 evaluation board, which provides all of the support

circuitry required to operate the AD9643, AD9613, AD6649,
and AD6643 in their various modes and configurations. The
application software used to interface with the devices is also
described.

The AD9643, AD9613, AD6649, and AD6643 data sheets
provide additional information and should be consulted when
using the evaluation board. All documents and software tools are
available at http://www.analog.com/fifo. For additional information
or questions, send an email to [e-mail].

Figure 1. AD9643, AD9613, AD6649, or AD6643 Family Evaluation Board and HSC-ADC-EVALCZ Data Capture Board

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.

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UG-293 Evaluation Board User Guide

TABLE OF CONTENTS

Features.............................................................................................. 1

Equipment Needed........................................................................... 1

Software Needed............................................................................... 1

Documents Needed.......................................................................... 1

General Description ......................................................................... 1

Typical Measurement Setup............................................................ 1

Revision History ............................................................................... 2

Evaluation Board Hardware............................................................ 3

Power Supplies ..............................................................................3

Input Signals.................................................................................. 3

REVISION HISTORY

11/11—Revision 0: Initial Version

Output Signals ...............................................................................4

Default Operation and Jumper Selection Settings....................4

Evaluation Board Software Quick Start Procedures.....................6

Configuring the Board .................................................................6

Using the Software for Testing.....................................................6

Evaluation Board Schematics and Artwork................................ 14

Ordering Information.................................................................... 24

Bill of Materials........................................................................... 24

Related Links................................................................................... 27

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Evaluation Board User Guide UG-293

EVALUATION BOARD HARDWARE

The AD9643, AD9613, AD6649, or AD6643 evaluation board
provides all of the support circuitry required to operate these
parts in their various modes and configurations. Figure 2 shows
the typical bench characterization setup used to evaluate the ac
performance of the AD9643, AD9613, AD6649, or AD6643. It is
critical that the signal sources used for the analog input and the
clock have very low phase noise (<1 ps rms jitter) to realize the
optimum performance of the signal chain. Proper filtering of
the analog input signal to remove harmonics and lower the inte­grated or broadband noise at the input is necessary to achieve
the specified noise performance.

See the Evaluation Board Software Quick Start Procedures section
to get started, and see Figure 23 to Figure 34 for the complete
schematics and layout diagrams. These diagrams demonstrate
the routing and grounding techniques that should be applied at
the system level when designing application boards using these
converters.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Connect
the supply to a rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The output from the supply is provided through a

2.1 mm inner diameter jack that connects to the printed circuit
board (PCB) at P201. The 6 V supply is fused and conditioned
on the PCB before connecting to the low dropout linear regulators
(default configuration) that supply the proper bias to each of the
various sections on the board.

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz

SWITCHING
POWER
SUPPLY

The evaluation board can be powered in a nondefault condition
using external bench power supplies. To do this, remove the
jumpers on the P103, P104, P107, P108, and P105 header pins
to disconnect the outputs from the on-board LDOs. This enables
the user to bias each section of the board individually. Use P202
and P203 to connect a different supply for each section. A 1.8 V
supply is needed with a 1 A current capability for DUT_AVDD and
DRVDD; however, it is recommended that separate supplies be
used for both analog and digital domains. An additional supply
is also required to supply 1.8 V for digital support circuitry on
the board, DVDD. This should also have a 1 A current capability
and can be combined with DRVDD with little or no degradation
in performance. To operate the evaluation board using the SPI
and alternate clock options, a separate 3.3 V analog supply is
needed in addition to the other supplies. This 3.3 V supply, or
3P3V_ANALOG, should have a 1 A current capability. This

3.3 V supply is also used to support the optional input path
amplifier (ADL5202) on Channel A and Channel B.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal
generators with low phase noise, such as the Rohde & Schwarz
SMA or HP 8644B signal generators or an equivalent. Use a 1 m
shielded, RG-58, 50 Ω coaxial cable for connecting to the evalua­tion board. Enter the desired frequency and amplitude (see the
Specifications section in the data sheet of the respective part).

SWITCHING
POWER

SIGNAL

SYNTHESIZER

ANALOG INPUT

SIGNAL

SYNTHESIZER

ANALOG INPUT

SUPPLY

6V DC
2A MAX

SIGNAL

SYNTHESIZER

OPTIO NAL CLOCK SOURCE

Figure 2. Evaluation Board Connection

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6V DC
2A MAX

PC

RUNNING ADC

ANALYZER

OR VISUAL ANALO G

USER SOFTW ARE

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UG-293 Evaluation Board User Guide

When connecting the analog input source, use of a multipole,
narrow-band, band-pass filter with 50 Ω terminations is recom­mended. Analog Devices, Inc., uses TTE and K&L Microwave,
Inc., band-pass filters. The filters should be connected directly
to the evaluation board.

If an external clock source is used, it should also be supplied
with a clean signal generator as previously specified. Typically,
most Analog Devices evaluation boards can accept ~2.8 V p-p or
13 dBm sine wave input for the clock.

OUTPUT SIGNALS

The default setup uses the Analog Devices high speed converter
evaluation platform (HSC-ADC-EVALCZ) for data capture. The
output signals from Channel A and Channel B for the AD9643,

AD9613, AD6649, and AD6643 are routed through P601 and

P602, respectively, to the FPGA on the data capture board.

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS

This section explains the default and optional settings or
modes allowed on the AD9643/AD9613/AD6649/AD6643
evaluation board.

Power Circuitry

Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P201.

Analog Input

The A and B channel inputs on the evaluation board are set up for a
double balun-coupled analog input with a 50 Ω impedance. This
input network is optimized to support a wide frequency band. See
the AD9643, AD9613, AD6649, and AD6643 data sheets for addi-
tional information on the recommended networks for different
input frequency ranges. The nominal input drive level is 10 dBm to
achieve 2 V p-p full scale into 50 Ω. At higher input frequencies,
slightly higher input drive levels are required due to losses in the
front-end network.

Optionally, Channel A and Channel B inputs on the board can
be configured to use the ADL5202 digitally controlled, variable
gain wide bandwidth amplifier. The ADL5202 component is
included on the evaluation board at U401. However, the path into

2V p-p

S

SP

A

0.1µF

P

0.1µF

36Ω

36Ω

and out of the ADL5202 can be configured in many different
ways depending on the application; therefore, the parts in the
input and output path are left unpopulated. Users should see
the ADL5202 data sheet for additional information on this part
and for configuring the inputs and outputs. The ADL5202, by
default, is held in power-down mode but can be enabled by
adding 1 kΩ resistors at R427 and R428 to enable Channel A
and Channel B, respectively.

Clock Circuitry

The default clock input circuit that is populated on the AD9643/

AD9613/AD6649/AD6643 evaluation board uses a simple

transformer-coupled circuit with a high bandwidth 1:1
impedance ratio transformer (T503) that adds a very low
amount of jitter to the clock path. The clock input is 50 Ω
terminated and ac-coupled to handle single-ended sine wave
types of inputs. The transformer converts the single-ended
input to a differential signal that is clipped by CR503 before
entering the ADC clock inputs.

The board is set by default to use an external clock generator. An
external clock source capable of driving a 50 Ω terminated input
should be connected to J506.

A differential LVPECL clock driver output can also be used to
clock the ADC input using the AD9523 (U501). To place the

AD9523 into the clock path, populate R541 and R542 with 0 Ω

resistors and remove C532 and C533 to disconnect the default
clock path inputs. In addition, populate R533 and R534 with
0 Ω resistors, remove R522 and R523 to disconnect the default
clock path outputs, and insert AD9523 LVP ECL Output 2. T he

AD9523 must be configured through the SPI controller software to

set up the PLL and other operation modes. Consult the AD9523
data sheet for more information about these and other options.

PDWN

To enable the power-down feature, add a shorting jumper across
P101 at Pin 1 and Pin 2 to connect the PDWN pin to AVDD.

OEB

To disable the digital output pins and place them in a high imped­ance state, add a shorting jumper across P102 at Pin 1 and Pin 2
to connect the OEB pin to AVDD.

8.2pF

49.9Ω

0.1µF

33Ω

8.2pF

33Ω

VIN+x

AD9643/AD9613/

AD6649/AD6643

VIN–x

VCM

49.9Ω

8.2pF

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Figure 3. Default Analog Input Configuration of the AD9643/AD9613/AD6649/AD6643

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Evaluation Board User Guide UG-293

Switching Power Supply

Optionally, the ADC on the board can be configured to use the

ADP2114 dual switching power supply to provide power to the

DRVDD and AVDD rails of the ADC. To configure the board
to operate from the ADP2114, the following changes must be
incorporated (see the Evaluation Board Schematics and Artwork
and the Bill of Materials sections for specific recommendations
for part values):

1. Install R204 and R221 to enable the ADP2114.

2. Install R216 and R218.

3. Install L201 and L202.

4. Remove JP201 and JP203.

5. Remove jumpers from across Pin 1 and Pin 2 on P107 and

P108, respectively.

6. Place jumpers across Pin 1 and Pin 2 of P106 and P109,

respectively.

Making these changes enables the switching converter to power
the ADC. Using the switching converter as the ADC power
source is more efficient than using the default LDOs.

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UG-293 Evaluation Board User Guide

EVALUATION BOARD SOFTWARE QUICK START PROCEDURES

This section provides quick start procedures for using the AD9643/

AD9613/AD6649/AD6643 evaluation board. Both the default

and optional settings are described.

CONFIGURING THE BOARD

Before using the software for testing, configure the evaluation
board as follows:

1. Connect the evaluation board to the data capture board, as

shown in Figure 1 and Figure 2.

2. Connect one 6 V, 2.5 A switching power supply (such as

the CUI, Inc., EPS060250UH-PHP-SZ that is supplied) to
the AD9643/AD9613/AD6649/AD6643 board.

3. Connect another 6 V, 2.5 A switching power supply (such

as the CUI EPS060250UH-PHP-SZ that is supplied) to the

HSC-ADC-EVALCZ board.

4. Connect the HSC-ADC-EVALCZ board (J6) to the PC

with a USB cable.

5. On the ADC evaluation board, confirm that jumpers are

installed on the P105, P108, P104, P107, P110, and P103
headers.

6. Connect a low jitter sample clock to Connector J506.

7. Use a clean signal generator with low phase noise to provide

an input signal to the desired channel(s) at Connector J301
(Channel A) and/or Connector J303 (Channel B). Use a
1 m, shielded, RG-58, 50 Ω coaxial cable to connect the
signal generator. For best results, use a narrow-band band­pass filter with 50 Ω terminations and an appropriate
center frequency. (Analog Devices uses TTE, Allen Avionics,
and K&L band-pass filters.)

USING THE SOFTWARE FOR TESTING

Setting Up the ADC Data Capture

After configuring the board, set up the ADC data capture using
the following steps:

1. Open VisualAnalog® on the connected PC. The appro-

priate part type should be listed in the status bar of the
VisualAnalog – New Canvas window. Select the template
that corresponds to the type of testing to be performed
(see Figure 4 where the AD9643 is shown as an example).
The AD9643 is given as an example in this user guide.
Similar settings are used for the AD9613. For the AD6649
and AD6643, the differences are noted where necessary in
the steps that follow.

2. After the template is selected, a message appears asking if

the default configuration can be used to program the FPGA
(see Figure 5). Click Yes , and the window closes.

3. To change features to settings other than the default settings,

click the Expand Display button, located on the bottom
right corner of the window, to see what is shown in Figure 7.
Detailed instructions for changing the features and capture
settings can be found in the AN-905 Application Note,

VisualAnalog™ Converter Evaluation Tool Version 1.0 User
Manual. After the changes are made to the capture settings,

click the Collapse Display button (see Figure 6).

Figure 4. VisualAnalog, New Canvas Window

Figure 5. VisualAnalog Default Configuration Message

Figure 6. VisualAnalog Window Toolbar, Collapsed Display

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Evaluation Board User Guide UG-293

Figure 7. VisualAnalog, Main Window

Setting Up the SPI Controller Software

After the ADC data capture board setup is complete, set up the
SPI controller software using the following procedure:

1. Open the SPI controller software by going to the Start menu

or by double-clicking the SPIController software desktop
icon. If prompted for a configuration file, select the appropriate
one. If not, check the title bar of the window to determine
which configuration is loaded. If necessary, choose Cfg
Open from the File menu and select the appropriate file
based on your part type. Note that the CHIP ID(1) field
should be filled to indicate whether the correct SPI
controller configuration file is loaded (see Figure 8).

Figure 8. SPI Controller, CHIP ID(1) Section

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UG-293 Evaluation Board User Guide

2. Click the New DUT button in the SPIController window

(see Figure 9).

Figure 9. SPI Controller, New DUT Button

3. In the ADCBase 0 tab of the SPIController window, find the

CLK DIV(B) section (see Figure 11). If using the clock

divider, use the drop-down box to select the correct clock
divide ratio, if necessary. See the appropriate part data sheet;
the AN-878 Application Note, High Speed ADC SPI Control

Software; and the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI, for additional information.

4. In the ADCBase 0 tab of the SPIController window, find the

FLEX OUTPUT DELAY(17) box. Select the DCO Clk Delay
Enable checkbox to enable this feature. In the drop-down box,

select 600 ps additional delay on DCO pin. These settings
align the output timing with the input timing on the
capture FPGA.

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5. Note that other settings can be changed on the ADCBase 0

tab (see Figure 11) and the ADC A and ADC B tabs (see
Figure 10) to set up the part in the desired mode. The
settings on the ADCBase 0 tab affect the entire part,
whereas the settings on the ADC A and ADC pages affect
the selected channel only. See the appropriate part data
sheet; the AN-878 Application Note, Hi

Con

trol Software; and the AN-877 Application Note,

gh Speed ADC SPI

Interfacing to High Speed ADCs via SPI, for additional

information on the available settings.

Figure 10. SPI Controller, Example ADC A Tab

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Figure 11. SPI Controller, CLK DIV(B) Section

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Evaluation Board User Guide UG-293

6. If using the AD6649, the device can be configured into two

different modes. The default mode utilizes a 95 MHz FIR
filter and fixed-frequency NCO. The SPI controller settings
for this mode are shown in Figure 12. Under the MAIN(50)
section, the Fir Low Latency Mode En checkbox must be
selected and the Low Latency NCO (Fs/4 Only) option

must be clicked under the MISC EXTRA(5A) section. The
second mode uses a 100 MHz FIR filter and a tunable­frequency NCO (see Figure 13). In this mode, the High
Latency NCO option under MISC EXTRA(5A) must be
clicked and the Fir Low Latency Mode En checkbox must
be cleared under the MAIN(50) section.

Figure 12. SPI Controller, AD6649 ADC A Tab—95 MHz FIR Filter and Fixed-Frequency NCO Mode

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