ANALOG DEVICES UG-216 Service Manual

Hardware User Guide

UG-216

One Technology Way • P. O . Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel : 781.329.4700 • Fax : 781.461.3113 • www.analog.com

Dual Port Xpressview Advantiv HDMI Receiver Functionality and Features

SCOPE

This user guide provides a detailed description of the Advantiv™ ADV7612 HDMI® functionality and features.

DISCLAIMER

Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FUNCTIONAL BLOCK DIAGRAM

XTALP XTALN

SCL SDA

CEC

RXA_5V RXB_5V

HPA_A/INT2*

HPA_B

DDCA_SDA DDCA_SCL

DDCB_SDA DDCB_SCL

RXA_C± RXB_C±

RXA_0± RXA_1± RXA_2±

RXB_0± RXB_1± RXB_2±

DPLL

CEC

CONTROLLER

5V DETECT

AND HPD

CONTROLLER

EDID

REPEATER

CONTROLLER

PLL

EQUALIZER

CONTROL

INTERFACE

HDCP

EEPROM

HDCP

ENGINE

SAMPLER

P0 TO P11

P12 TO P23

P24 TO P25

CONTROL

AND DATA

HDMI

PROCESSOR

™

XPressView

FAST SWITCHING

DATA

PREPROCESOR

AND COLOR

SPACE

CONVERSION

PACKET

PROCESSOR

COLOR SPACE

CONVERSION

COMPONENT PROCESSOR

A B C

PACKET/

INFOFRAME

MEMORY

BACKEND

INTERRUPT

CONTROLLER

(INT1, INT2)

MUTE

AUDIO

PROCESSOR

OUTPUT FORMATTER

AUDIO OUTPUT FORMATT ER

LLC

HS VS/FIELD/ALSB DE

INT1 INT2*

AP1 AP2 AP3 AP4

AP5 SCLK/INT2*

MCLK/INT2* AP0

ADV7612

*INT2 CAN BE ONLY OUTPUT O N ONE OF THE PI N S : SCLK/INT2, MCLK/INT2, OR HP A _A/INT2.

Figure 1. Functional Block Diagram

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS.

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UG-216 Hardware User Guide

TABLE OF CONTENTS

Scope .................................................................................................. 1

Disclaimer .......................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 5

Using the ADV7612 Hardware User Guide .................................. 6

Number Notations ........................................................................ 6

Acronyms and Abbreviations ..................................................... 6

Field Function Descriptions ........................................................ 8

Example Field Function Description ..................................... 8

References ...................................................................................... 8

Introduction to the ADV7612 ........................................................ 9

HDMI Receiver ............................................................................. 9

Component Processor ................................................................. 9

Main Features of ADV7612 ........................................................ 9

HDMI Receiver ......................................................................... 9

Component Video Processing .............................................. 10

Video Output Formats ........................................................... 10

Additional Features ................................................................ 10

Pin Configuration and Function Descriptions ....................... 11

Global Control Registers ............................................................... 15

ADV7612 Revision Identification ............................................ 15

Power-Down Controls ............................................................... 15

Primary Power-Down Controls ........................................... 15

Secondary Power-Down Controls ....................................... 15

Power-Down Modes .............................................................. 16

Global Pin Control ..................................................................... 17

RESET

Pin ............................................................................... 17

Reset Controls ......................................................................... 17

Tristate Output Drivers ......................................................... 17

Tristate LLC Driver ................................................................ 18

Tristate Synchronization Output Drivers ............................ 18

Tristate Audio Output Drivers.............................................. 18

Drive Strength Selection ........................................................ 19

Output Synchronization Selection ....................................... 20

Output Synchronization Signals Polarity ............................ 20

Digital Synthesizer Controls ................................................. 21

Crystal Frequency Selection ................................................. 21

Primary Mode and Video Standard ............................................. 22

Primary Mode and Video Standard Controls ......................... 22

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V_FREQ .................................................................................. 24

HDMI Decimation Modes ........................................................ 24

Primary Mode and Video Standard Configuration for HDMI

Free Run ....................................................................................... 24

Recommended Settings for HDMI Inputs .............................. 25

Pixel Port Configuration ............................................................... 27

Pixel Port Output Modes ........................................................... 27

Bus Rotation and Reordering Controls ............................... 27

Pixel Data and Synchronization Signals Control ............... 28

LLC Controls............................................................................... 28

DLL on LLC Clock Path ............................................................ 28

Adjusting DLL Phase in All Modes ..................................... 28

DLL Settings for 656, 8-/10-/12-Bit Modes ........................ 29

HDMI Receiver ............................................................................... 30

+5 V Cable Detect ...................................................................... 30

Hot Plug Assert ........................................................................... 31

E-EDID/Repeater Controller .................................................... 33

E-EDID Data Configuration..................................................... 34

Notes ........................................................................................ 34

E-EDID Support for Power-Down Modes ......................... 34

Transitioning of Power Modes ................................................. 35

Structure of Internal E-EDID for Port A ................................ 35

Structure of Internal E-EDID for Port B ................................. 36

TMDS Equalization ................................................................... 38

Port Selection .............................................................................. 38

Fast Switching and Background Port Selection ...................... 39

TMDS Clock Activity Detection .............................................. 40

Important ................................................................................ 41

Clock and Data Termination Control ................................. 41

HDMI/DVI Status Bits .............................................................. 41

Video 3D Detection ................................................................... 41

TMDS Measurement.................................................................. 42

TMDS Measurement After TMDS PLL .............................. 42

Deep Color Mode Support ........................................................ 45

Notes ........................................................................................ 45

Video FIFO .................................................................................. 46

Pixel Repetition .......................................................................... 47

HDCP Support ........................................................................... 49

HDCP Decryption Engine .................................................... 49

Internal HDCP Key OTP ROM ........................................... 50

Hardware User Guide UG-216

HDCP Keys Access Flags ....................................................... 50

HDCP Ri Expired ................................................................... 53

HDMI Synchronization Parameters ......................................... 53

Notes ......................................................................................... 53

Horizontal Filter and Measurements ................................... 53

Primary Port Horizontal Filter Measurements ................... 53

Background Port Horizontal Filter Measurements ............ 55

Horizontal Filter Locking Mechanism ................................. 55

Vertical Filters and Measurements ....................................... 56

Primary Port Vertical Filter Measurements ........................ 56

Background Port Vertical Filter Measurements ................. 58

Vertical Filter Locking Mechanism ...................................... 59

Low Frequency Formats ......................................................... 60

Audio Control and Configuration ............................................ 60

Important ................................................................................. 60

Audio DPLL ............................................................................. 61

Locking Mechanism ............................................................... 61

ACR Parameters Loading Method ....................................... 61

Audio DPLL Coast Feature .................................................... 61

Audio FIFO .................................................................................. 61

Audio Packet Type Flags ............................................................ 63

Notes ......................................................................................... 64

Audio Output Interface .............................................................. 65

I2S/SPDIF Audio Interface and Output Controls ............... 66

Notes ......................................................................................... 67

DSD Audio Interface and Output Controls ........................ 69

HBR Interface and Output Controls .................................... 71

MCLKOUT Setting ..................................................................... 72

Audio Channel Mode ................................................................. 72

Audio Muting .............................................................................. 73

Delay Line Control ................................................................. 73

Audio Mute Configuration .................................................... 74

Internal Mute Status ............................................................... 75

AV Mute Status ........................................................................ 76

Audio Mute Signal .................................................................. 76

Audio Stream with Incorrect Parity Error ........................... 76

Audio Clock Regeneration Parameters .................................... 77

ACR Parameters Readbacks .................................................. 77

Monitoring ACR Parameters ................................................. 77

Channel Status ............................................................................. 78

Validity Status Flag .................................................................. 78

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General Control and Mode Information ............................. 80

Category Code ......................................................................... 80

Source Number and Channel Number ................................ 80

Sampling and Frequency Accuracy ...................................... 81

Word L eng t h ............................................................................ 81

Channel Status Copyright Value Assertion ......................... 82

Monitoring Change of Audio Sampling Frequency ........... 82

Packets and InfoFrames Registers ............................................ 82

InfoFrames Registers .............................................................. 83

InfoFrame Collection Mode .................................................. 83

InfoFrame Checksum Error Flags ........................................ 83

AVI InfoFrame Registers ....................................................... 84

Audio InfoFrame Registers .................................................... 85

SPD InfoFrame Registers ....................................................... 86

MPEG Source InfoFrame Registers ...................................... 87

Vendor Specific InfoFrame Registers ................................... 88

Packet Registers ........................................................................... 89

ACP Packet Registers ............................................................. 89

ISRC Packet Registers............................................................. 90

Gamut Metadata Packets ....................................................... 92

Customizing Packet/InfoFrame Storage Registers ................. 93

Repeater Support ......................................................................... 94

Repeater Routines Performed by the EDID/Repeater

Controller ................................................................................. 94

Repeater Actions Required by External Controller ........... 95

HDCP Registers Available in Repeater Map ....................... 96

Interface to DPP Section .......................................................... 101

Notes ....................................................................................... 102

Pass Through Mode .................................................................. 102

4:2:2 Pass Through ................................................................ 102

4:4:4 Pass Through ................................................................ 102

Color Space Information Sent to the DPP and CP Sections

..................................................................................................... 103

Status Registers .......................................................................... 103

HDMI Section Reset Strategy ................................................. 106

HDMI Packet Detection Flag Reset........................................ 106

Data Preprocessor and Color Space Conversion and Color

Controls .......................................................................................... 107

Color Space Conversion Matrix .............................................. 107

CP CSC Selection .................................................................. 107

Selecting Auto or Manual CP CSC Conversion Mode .... 108

Auto Color Space Conversion Matrix ................................ 108

UG-216 Hardware User Guide

HDMI Automatic CSC Operation ..................................... 110

Manual Color Space Conversion Matrix ........................... 112

CSC in Pass-Through Mode ............................................... 116

Color Controls .......................................................................... 116

Component Processor .................................................................. 118

Introduction to the Component Processor ........................... 118

Clamp Operation ...................................................................... 118

CP Gain Operation................................................................... 120

Features of Manual Gain Control ...................................... 120

Features of Automatic Gain Control ................................. 120

Manual Gain and Automatic Gain Control Selection ..... 120

Manual Gain Control ........................................................... 121

Manual Gain Filter Mode .................................................... 122

Other Gain Controls ............................................................ 123

CP Offset Block......................................................................... 123

Notes ...................................................................................... 124

AV Code Block .......................................................................... 125

CP Data Path for HDMI Modes ............................................. 126

Pregain Block ........................................................................ 127

Sync Processed by CP Section ................................................ 130

Sync Routing from HDMI Section .................................... 130

Standard Detection and Identification .............................. 130

Detailed Mechanism of STDI Block Horizontal/Vertical

Lock Mechanism .................................................................. 132

CP Output Synchronization Signal Positioning ................... 137

CP Synchronization Signals ................................................ 138

HSync Timing Controls ...................................................... 139

VSync Timing Controls ....................................................... 141

DE Timing Controls ............................................................ 142

FIELD Timing Controls ...................................................... 143

HCOUNT Timing Control ................................................. 147

CP HDMI Controls .................................................................. 148

Free Run Mode ......................................................................... 148

Free Run Mode Thresholds ................................................. 148

Free Run Feature in HDMI Mode ...................................... 150

Free Run Default Color Output .......................................... 151

CP Status .................................................................................... 152

CP_REG_FF .......................................................................... 152

CP Core Bypassing ................................................................... 152

Consumer Electronics Control ................................................... 153

Main Controls ........................................................................... 153

CEC Transmit Section ............................................................. 154

CEC Receive Section ................................................................ 156

Logical Address Configuration .......................................... 156

Receive Buffers ..................................................................... 157

CEC Message Reception Overview ................................... 160

Antiglitch Filter Module .......................................................... 161

Typical Operation Flow ........................................................... 162

Initializing CEC Module ..................................................... 162

Using CEC Module as Initiator .......................................... 163

Using CEC Module as Follower ......................................... 164

Low Power CEC Message Monitoring ................................... 165

Interrupts ....................................................................................... 167

Interrupt Architecture Overview ........................................... 167

Interrupt Pins ............................................................................ 170

Notes ...................................................................................... 170

Interrupt Duration ............................................................... 171

Interrupt Drive Level ........................................................... 171

Interrupt Manual Assertion ................................................ 171

Multiple Interrupt Events .................................................... 172

Description of Interrupt Bits .................................................. 173

General Operation ............................................................... 173

HDMI Video Mode .............................................................. 173

CEC ........................................................................................ 173

HDMI Only Mode ............................................................... 173

Additional Explanations .......................................................... 174

STDI_DATA_VALID_RAW ............................................... 174

CP_LOCK, CP_UNLOCK ................................................. 175

HDMI Interrupts Validity Checking Process ................... 175

Storing Masked Interrupts .................................................. 177

Main I2C Port ............................................................................ 189

IO I2C Map Address ............................................................. 189

Addresses of Other Maps .................................................... 190

Protocol for Main I2C Port .................................................. 191

DDC Ports ................................................................................. 191

I2C Protocols for Access to the Internal EDID ................. 192

I2C Protocols for Access to HDCP Registers .................... 192

DDC Port A .......................................................................... 192

DDC Port B ........................................................................... 192

Appendix A ................................................................................... 193

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Hardware User Guide UG-216

PCB Layout Recommendations ............................................. 193

Power Supply Bypassing .......................................................... 193

Example of a Current Loop ................................................ 193

Digital Outputs (Data and Clocks) ........................................ 193

Digital Inputs ............................................................................ 194

XTAL and Load Cap Value Selection .................................... 194

REVISION HISTORY

11/12—Rev. A to Rev. B

Changed Pin 75 from AP1/I2S_TDM to AP1 ................ Unviersal

Changes to Figure 1........................................................................... 1

Deleted TDM from Table 3 .............................................................. 7

Deleted TDM Information from HDMI Reciever Section .......... 9

Changes to Figure 2......................................................................... 11

Changes to Pin 17, Pin 18, Pin 75, Pin 96, and Pin 100 ............. 12

Changes to ADV7612 Revision Identification Section .............. 15

Changes to Table 5 .......................................................................... 16

Changes to Tristate Audio Output Drivers Section .................... 18

Changes to DR_STR Section ......................................................... 19

Changes to INV_F_POL, IO, Address 0x06[3] Section ............. 21

Deleted 0x8D from OP_FORMAT_SEL[7:0] Table ................... 27

Changes to DLL Settings for 656, 8-/10-/12-Bit Modes Section

and Added Table 9 ........................................................................... 29

Changes to E-EDID Data Configuration Section ....................... 34

Changes to Figure 4......................................................................... 35

Added Low Frequency Formats Section and Figure 15 ............. 60

Deleted I2S_TDM_MODE_ENABLE, Addr 68 (HDMI),

Address 0x6D[7] Section ................................................................ 67

Changes to Notes Section ............................................................... 67

Deleted Figure 24 ............................................................................ 69

Deleted Notes Section ..................................................................... 72

Changes to Audio Mute Signal Section ........................................ 76

Changes to XTAL and Load Cap Value Selection Section .......194

Changes to Tab le 7 8 ......................................................................198

Example .................................................................................. 194

Appendix B .................................................................................... 195

Recommended Unused Pin Configurations ......................... 195

Appendix C .................................................................................... 198

Pixel Output Formats ............................................................... 198

2/12—Rev. 0 to Rev. A

Change to Video Output Formats Section ................................... 10

Change to Pin Configuration and Function Descriptions

Section, Table 4, Pin 87 ................................................................... 14

Changes to Table 7 .......................................................................... 25

Added Endnote to OP_FORMAT_SEL[7:0] Table in Pixel

Port Output Modes Section ........................................................... 27

Added LLC_DLL_DOUBLE Section and Table to DLL on

LCC Clock Path Section ................................................................. 28

Added DLL Settings for 656, 8-/10-/12-Bit Modes Section ...... 29

Changes to Audio Mute Signal Section ........................................ 75

Added 1001 to CS_DATA[27:24] Table in Sampling and

Frequency Accuracy Section ......................................................... 80

Changes to Check the Value of Each Coefficient Section ....... 114

Changes to CP_HUE[7:0], Addr 44 (CP) Address 0x3D[7:0]

in Color Controls Section; Changes to CP_HUE[7:0] Table ..... 116

Changes to INT2_POL Table in Interrupt Drive Level Section ... 170

Added Figure 75; Renumbered Sequentially ............................. 191

Added Endnote to Table 76 ......................................................... 197

11/10—Revis

ion 0: Initial Version

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UG-216 Hardware User Guide

R/W

Memory location has read and write access.

HDTV

High definition television.

ISRC

International standard recording code.

USING THE ADV7612 HARDWARE USER GUIDE

NUMBER NOTATIONS

Table 1.

Notation Description

Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0. V[X:Y] Bit field representation covering Bit X to Bit Y of a value or a field (V). 0xNN Hexadecimal (base-16) numbers are preceded by the prefix ‘0x’. 0bNN Binary (base-2) numbers are preceded by the prefix ‘0b’. NN Decimal (base-10) are represented using no additional prefixes or suffixes.

REGISTER ACCESS CONVENTIONS

Table 2.

Mode Description

R Memory location is read access only. A read always returns 0 unless otherwise specified. W Memory location is write access only.

ACRONYMS AND ABBREVIATIONS

Table 3.

Acronym/Abbreviation Description

ACP Audio content protection. AGC Automatic gain control. Ainfo HDCP register. Refer to digital content protection documentation in the References section. AKSV HDCP transmitter key selection vector. Refer to digital content protection documentation in the References

section. An 64-bit pseudo-random value generated by HDCP cipher function of Device A. AP Audio output pin. AVI Auxiliary video information. BCAPS HDCP register. Refer to digital content protection documentation in the References section. BKSV HDCP receiver key selection vector. Refer to digital content protection documentation in the References

section. CP Component processor. CSC Color space converter/conversion. DDR Double data rate. DE Data enable. DLL Delay locked loop. DPP Data preprocessor. DVI Digital visual interface. EAV End of active video. EMC Electromagnetic compatibility. EQ Equalizer. HD High definition. HDCP High bandwidth digital content protection. HDMI High bandwidth multimedia interface.

HPA Hot plug assert. HPD Hot plug detect. HSync Horizontal synchronization. IC Integrated circuit.

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Hardware User Guide UG-216

I2C

Inter integrated circuit.

STDI

Standard detection and identification.

Acronym/Abbreviation Description

I2S Inter IC sound.

KSV Key selection vector. LLC Line locked clock. LSB Least significant bit. L-PCM Linear pulse coded modulated. Mbps Megabit per second. MPEG Moving picture expert group. ms Millisecond. MSB Most significant bit. NC No connect. OTP One-time programmable. Pj’ HDCP enhanced link verification response. Refer to digital content protection documentation in the

References section. Ri’ HDCP link verification response. Refer to digital content protection documentation in the References section. Rx Receiver. SAV Start of active video. SDR Single data rate. SHA-1 Refer to HDCP documentation. SMPTE Society of Motion Picture and Television Engineers. SOG Sync on green. SOY Sync on Y. SPA Source physical address. SPD Source production descriptor.

TMDS Transition minimized differential signaling. Tx Transmitter. VBI Video blanking interval. VSync Vertical synchronization. XTAL Crystal oscillator.

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UG-216 Hardware User Guide

FIELD FUNCTION DESCRIPTIONS

Throughout this user guide, a series of function tables are provided. The function of a field is described in a table preceded by the bit name, a short function description, the I

The detailed description consists of:

• For a readable field, the values the field can take

• For a writable field, the values the field can be set to

Example Field Function Description

This section provides an example of a field function table followed by a description of each part of the table.

PRIM_MODE[3:0], IO Map, Address 0x01[3:0].

A control to select the primary mode of operation of the decoder.

Function PRIM_MODE[3:0] Description

0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 HDMI-Comp 0110 (default) HDMI-GR 0111 to 1111 Reserved

In this example

C map, the register location within the I2C map, and a detailed description of the field.

• The name of the field is PRIM_MODE and it is four bit long.

• Address 0x01 is the I

C location of the field in big endian format (MSB first, LSB last).

• The address is followed by a detailed description of the field.

• The first column of the table lists values the field can take or can be set to. These values are in binary format if not preceded by 0x or

in hexadecimal format if preceded by 0x.

• The second column describes the function of each field for each value the field can take or can be set to. Values are in binary format.

REFERENCES

CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006.

Digital Content Protection (DCP) LLC, High-Bandwidth Digital Content Protection System, Revision 1.4, July 8, 2009.

HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010.

ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998.

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Hardware User Guide UG-216

INTRODUCTION TO THE ADV7612

The ADV7612 is a high quality, 2:1 multiplexed high-definition multimedia interface (HDMI®) receiver.

The ADV7612 incorporates a dual input HDMI receiver that supports all mandatory 3D TV formats defined in the HDMI specification. HDTV formats up to 1080p 36-bit deep color and display resolutions up to UXGA (1600 × 1200 at 60 Hz).

The ADV7612 also integrates a CEC controller that supports the capability discovery and control (CDC) feature.

The ADV7612 incorporates Xpressview™ fast switching on both input HDMI ports. Using Analog Devices’ hardware-based HDCP engine that minimizes software overhead, Xpressview technology allows fast switching between both HDMI input ports in less than 1 second. Each HDMI port has dedicated +5 V detect and hot plug assert pins. The HDMI receiver also includes an integrated programmable equalizer that ensures robust operation of the interface with long cables.

Fabricated in an advanced CMOS process, the ADV7612 is provided in a 14 mm × 14 mm, 100-pin surface-mount LQFP_EP, RoHScompliant package and is specified over −40°C to +85°C temperature range.

HDMI RECEIVER

The HDMI receiver on the ADV7612 incorporates a fast switching feature that allows inactive ports to be HDCP authenticated to provide rapid switching between encrypted HDMI sources. The ADV7612 HDMI receiver incorporates active equalization of the HDMI data signals to compensate for the losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. The equalizer is highly effective and is capable of equalizing for long cables to achieve robust receiver performance.

With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7612 allows a video receiver to authenticate, decrypt encoded data, and renew that authentication during transmission, as specified by the HDCP v1.4 protocol for both active and background HDMI ports.

The ADV7612 offers a flexible audio output port for audio data extraction from the HDMI stream. HDMI audio formats, including super audio CD (SACD) via DSD and HBR are supported by ADV7612. The HDMI receiver has advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output.

COMPONENT PROCESSOR

The component processor (CP) is located behind the HDMI receiver. It processes the video data received from the HDMI receiver. The CP section provides color adjustment features, such as brightness, saturation, and hue. The color space conversion (CSC) matrix allows the color space to be changed as required. The standard detection and identification (STDI) block allows the detection of video timings.

MAIN FEATURES OF ADV7612

HDMI Receiver

• HDMI features supported

• 3D HDMI video format support

• Full colorimetry, including sYCC601, Adobe RGB, Adobe YCC601, and xvYCC extended gamut color

• CEC-compatible

• 3D video support, including frame packing for all 3D formats up to a 225 MHz TMDS clock and/or up a pixel clock of 165 MHz

• Fast switching between HDMI ports

• Supports deep color

• Supports all display resolutions up to UXGA (1600 × 1200 at 60 Hz, 10-bit)

• Supports multichannel audio with sampling frequency up to 192 kHz

• Programmable front-end equalization for long cable lengths

• Audio mute for removing extraneous noise

• Programmable interrupt generator to detect HDMI packets

• Internal EDID support

• Repeater support

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Component Video Processing

• An any-to-any 3 × 3 CSC matrix support YCrCb to RGB and RGB to YCrCb

• Provides color controls, such as saturation, brightness, hue, and contrast

• STDI block that enables format detection

• Free run output mode provides stable timing when no video input is present

Video Output Formats

• Double data rate (DDR) 8-/10-/12-bit 4:2:2 YCrCb

• DDR is supported only up to 50 MHz (an equivalent to ata rate clocked with 100 MHz clock in SDR mode)

• Pseudo DDR (CCIR-656 type stream) 8-/10-/12-bit 4:2:2 YCrCb for 525i, 625i, 525P, and 625P

• SDR 16-/20-/24-bit 4:2:2 YCrCb for all standards

• SDR 24-/30-/36-bit 4:4:4 YCrCb/RGB for all HDMI standards

• DDR 12-/24-/30-/36-bit 4:4:4 RGB

Additional Features

• HS, VS, FIELD, and DE output signals with programmable position, polarity, and width

• Numerous interrupt sources available for the INT1 and INT2 interrupt request output pins, available via one of the selected pins, that

is, SCLK/INT2, MCLK/INT2, or HPA_A/INT2

• Temperature range of −40°C to +85°C

• 14 mm × 14 mm, 100-pin LQFP_EP package

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Hardware User Guide UG-216

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

HPA_A/INT2

RXA_5V

DDCA_SDA

DDCA_SCL

HPA_B

RXB_5V

DDCB_SDA

DDCB_SCL

CEC

DVDD

XTALN

XTALP

100

PVDDCSRESET

898887

INT1

SDA

SCL

DVDD

MCLK/INT2

AP5

SCLK/INT2

AP4

AP3

AP2

787776

CVDD RXA_C– RXA_C+

TVDD

RXA_0– RXA_0+

TVDD

RXA_1– RXA_1+

TVDD

RXA_2– RXA_2+

CVDD RXB_C– RXB_C+

TVDD

RXB_0– RXB_0+

TVDD

RXB_1– RXB_1+

TVDD

RXB_2– RXB_2+

CVDD

1 2 3 4 5 6 7 8

9 10 11

13 14 15 16 17 18 19 20 21 22 23 24 25

PIN 1 INDICATOR

P35

(Not to Scale)

P34

P33

P32

P31

P30

P29

P28

DVDDIO

NOTES

1. NC = NO CONNE . CONNECT EXPOSED PAD (PIN0) TO GROUND (BOTTOM).

T. DO NOT CONNECT TO THI S PIN.

Figure 2. Pin Configuration

ADV7612

TOP VIEW

373839

P27

P26

DVDDIO

AP1

AP0

VS/FIELD/ALSB

DVDDIO

DVDD

P10

P11

P12

P13

DVDDIO

P14

P15

P16

P25

P24

DVDD

P23

P22

P21

LLC

484950

P20

P19

P18

P17

09486-003

Table 4. Pin Function Descriptions

Pin No. Mnemonic Type Description

0 GND Ground Ground. 1 CVDD Power HDMI Analogue Block Supply Voltage (1.8 V). 2 RXA_C− HDMI input Digital Input Clock Complement of Port A in the HDMI Interface. 3 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface. 4 TVDD Power Terminator Supply Voltage (3.3 V). 5 RXA_0− HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface. 6 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface. 7 TVDD Power Terminator Supply Voltage (3.3 V). 8 RXA_1− HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface. 9 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface. 10 TVDD Power Terminator Supply Voltage (3.3 V). 11 RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface. 12 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface. 13 CVDD Power HDMI Analogue Block Supply Voltage (1.8 V). 14 RXB_C− HDMI input Digital Input Clock Complement of Port B in the HDMI Interface. 15 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface. 16 TVDD Power Terminator Supply Voltage (3.3 V).

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RXB_0+

HDMI input

Digital Input Channel 0 True of Port B in the HDMI Interface.

RXB_2+

HDMI input

Digital Input Channel 2 True of Port B in the HDMI Interface.

output

P32

Digital video

Video Pixel Output Port.

P19

Digital video

Video Pixel Output Port.

Pin No. Mnemonic Type Description

17 RXB_0− HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface.

19 TVDD Power Terminator Supply Voltage (3.3 V). 20 RXB_1− HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface. 21 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface. 22 TVDD Power Terminator Supply Voltage (3.3 V). 23 RXB_2− HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface.

25 CVDD Power HDMI Analogue Block Supply Voltage (1.8 V). 26 NC No connect No connect. 27 P35 Digital video

output

28 P34 Digital video

output 29 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 30 P33 Digital video

output 32 P31 Digital video

output 33 P30 Digital video

output 34 P29 Digital video

output 35 P28 Digital video

output 36 P27 Digital video

output 37 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 38 P26 Digital video

output 39 P25 Digital video

output 40 P24 Digital video

output 41 DVDD Power Digital Core Supply Voltage (1.8 V). 42 LLC Digital video

output 43 P23 Digital video

output 44 P22 Digital video

output 45 P21 Digital video

output 46 P20 Digital video

output

Video Pixel Output Port.

Line-Locked Output Clock for the Pixel Data (Range is 13.5 MHz to 170 MHz).

Video Pixel Output Port.

output 48 P18 Digital video

output 49 P17 Digital video

output 50 NC No connect No connect. 51 P16 Digital video

output

Video Pixel Output Port.

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Digital video

Video Pixel Output Port.

Digital video

Video Pixel Output Port.

Digital video

HS is a horizontal synchronization output signal.

AP3

Miscellaneous

Audio Output Pin. Pins AP to AP5 can be configured to output SPDIF Digital Audio Output

Pin No. Mnemonic Type Description

52 P15 Digital video

output

53 P14 Digital video

output 54 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 55 P13 Digital video

output 56 P12 Digital video

output 57 P11 Digital video

output 58 P10 Digital video

output

output 60 P8 Digital video

output 61 P7 Digital video

output 62 DVDD Power Digital Core Supply Voltage (1.8 V ). 63 P6 Digital video

output

Video Pixel Output Port.

output 65 P4 Digital video

Video Pixel Output Port.

output 66 P3 Digital video

Video Pixel Output Port.

output 67 P2 Digital video

Video Pixel Output Port.

output 68 P1 Digital video

Video Pixel Output Port.

output 69 P0 Digital video

Video Pixel Output Port.

output 70 DVDDIO Power Digital I/O Supply Voltage (3.3 V). 71 DE Miscellaneous

DE (data enable) is a signal that indicates active pixel data.

digital

output 73 VS/FIELD/ALSB Digital video

output

74 AP0 Miscellaneous Audio Output Pin. Pins AP0 to AP5 can be configured to output SPDIF Digital Audio Output

75 AP1 Miscellaneous Audio Output Pin. Pins AP0 to AP5 can be configured to output SPDIF Digital Audio Output

76 AP2 Miscellaneous Audio Output Pin. Pins AP to AP5 can be configured to output SPDIF Digital Audio Output

VS is a vertical synchronization output signal. FIELD is a field synchronization output signal in all interlaced video modes. VS or FIELD can be configured for this pin. The ALSB allows selection of the I

(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD), Direct Stream Transfer (DST) or I

C address.

(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD), Direct Stream Transfer (DST) or I2S.

78 AP4 Miscellaneous Audio Output Pin. Pins AP to AP5 can be configured to output SPDIF Digital Audio Output

(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD), Direct Stream Transfer (DST) or I

79 SCLK/INT2 Miscellaneous

digital

A dual function pin that can be configured to output Audio Serial Clock or an Interrupt2 signal.

80 AP5 Miscellaneous Audio Output Pin. Pins AP to AP5 can be configured to output SPDIF Digital Audio Output

(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD), Direct Stream Transfer (DST) or I2S. Additionally, Pin AP5 can be configured to provide LRCLK.

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DVDD

Power

Digital Core Supply Voltage (1.8 V).

Pin No. Mnemonic Type Description

81 MCLK/INT2 Miscellaneous A dual fuction pin that can be configured to output Audio Master Clock or an Interrupt2

signal. 82 DVDD Power Digital Core Supply Voltage (1.8 V). 83 SCL Miscellaneous

digital

84 SDA Miscellaneous

digital

85 INT1 Miscellaneous

digital

88 PVDD Power PLL Supply Voltage (1.8 V) 89 XTAL P Miscellaneous

90 XTAL N Miscellaneous

Miscellaneous

RESET

digital

Miscellaneous

digital

analog

I2C Port Serial Clock Input. SCL is the clock line for the control port.

I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.

Interrupt. This pin can be active low or active high. When status bits change, this pin is

triggered. The events that trigger an interrupt are under user configuration.

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7612 circuitry.

Chip Select. This pin has an internal pull-down. Pulling this line up causes the I2C state

machine to ignore I

Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator

Source to Clock the ADV7612.

Crystal Input. Input pin for 28.63636 MHz crystal.

C transmission.

92 CEC Digital

input/output 93 DDCB_SCL HDMI input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. 94 DDCB_SDA HDMI input HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant. 95 RXB_5V HDMI input 5 V Detect Pin for Port B in the HDMI Interface. 96 HPA_B Miscellaneous

digital 97 DDCA_SCL HDMI input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. 98 DDCA_SDA HDMI input HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant. 99 RXA_5V HDMI input 5 V Detect Pin for Port A in the HDMI Interface. 100 HPA_A/INT2 Miscellaneous

digital

Consumer Electronic Control Channel.

Hot Plug Assert signal output for HDMI port B. This is an open-drain pin.

A dual function open-drain pin that can be configured to output Hot Plug Assert signal (for HDMI Port A) or an Interrupt2 signal.

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Powers down clock to CP core. HDMI block not affected by this bit.

GLOBAL CONTROL REGISTERS

The register control bits described in this section deal with the general control of the chip, and the CP and the HDMI receiver sections of the ADV7612.

ADV7612 REVISION IDENTIFICATION

RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0] (Read Only)

Chip revision code.

Function RD_INFO[15:0] Description

0x2051 ADV7611 Final Silicon 0x2041 ADV7612 Final Silicon

POWER-DOWN CONTROLS

Primary Power-Down Controls

POWER_DOWN is the main power-down control. It is the main control for power-down Mode 0 and Mode 1. See the Power-Down Modes section for more details.

POWER_DOWN, IO, Address 0x0C[5]

A control to enable power-down mode. This is the main I

Function POWER_DOWN Description

0 Chip operational 1 (default) Enables chip power down

Secondary Power-Down Controls

The following controls allow various sections of the ADV7612 to be powered down.

It is possible to stop the clock to the CP to reduce power for a power-sensitive application. The CP_PWRDN bit enables this power-save mode. The HDMI block is not affected by this power-save mode. This allows the use of limited HDMI, STDI monitoring features while reducing the power consumption. For full processing of the HDMI input, the CP core needs to be powered up.

CP_PWRDN, IO, Address 0x0C[2]

A power-down control for the CP core.

Function CP_PWRDN Description

0 (default) Powers up clock to CP core.

C power-down control.

XTAL_PDN

XTAL_PDN allows the user to power down the XTAL clock in the following sections:

• STDI blocks

• Free run synchronization generation block

• I

C sequencer block, which is used for the configuration of the gain, clamp, and offset

• CP and HDMI section

The XTAL clock is also provided to the HDCP engine, EDID, and the repeater controller within the HDMI receiver. The XTAL clock within these sections is not affected by XTAL_PDN.

XTAL_PDN, IO, Address 0x0B[0]

A power-down control for the XTAL in the digital blocks.

Function XTAL_PDN Description

0 (default) Powers up XTAL buffer to digital core 1 Powers down XTAL buffer to digital core

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CORE_PDN

CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections:

• CP block

• Digital section of the HDMI block

CORE_PDN, IO, Address 0x0B[1]

A power-down control for the DPP, CP core, and digital sections of the HDMI core.

Function CORE_PDN Description

0 (default) Powers up CP and digital sections of HDMI block 1 Powers down CP and digital section of HDMI block

Power-Down Modes

The ADV7612 supports the following power-down modes:

• Power-Down Mode 0

• Power-Down Mode 1

Table 5 shows the power-down and normal modes of ADV7612.

Table 5. Power-Down Modes

POWER_DOWN bit CEC_POWER_UP Bit CEC EDID Power-Down Mode

1 0 Disabled Enabled Power-Down Mode 0 1 1 Enabled Enabled Power-Down Mode 1 0 0 Disabled Enabled1 Normal mode 0 1 Enabled Enabled1 Normal mode

Dependent on the values of EDID_X_ENABLE_CPU and EDID_X_ENABLE for the HDMI port (where X is A).

Power-Down Mode 0

In Power-Down Mode 0, selected sections and pads are kept active to provide EDID and +5 V antiglitch filter functionality.

In Power-Down Mode 0, the sections of the ADV7612 are disabled except for the following blocks:

• I

C slave section

• EDID/repeater controller

• EDID ring oscillator

The ring oscillator provides a clock to the EDID/repeater controller (refer to the E-EDID/Repeater Controller section) and the +5 V power supply antiglitch filter. The clock output from the ring oscillator runs at approximately 50 MHz.

The following pads only are enabled in Power-Down Mode 0:

• I

C pads

• SDA

• SCL

• +5 V pads

• RXA_5V

• RXB_5V

• HPA_A

• HPA_B

• DDC pads

• DDCA_SCL

• DDCA_SDA

• DDCB_SCL

• DDCB_SDA

• Reset pad

Power-Down Mode 0 is initiated through a software (I

RESET

C register) configuration.

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PADS_PDN

Description

Entering Power-Down Mode 0 via Software

The ADV7612 can be put into Power-Down Mode 0 by setting POWER_DOWN to 1 (default value) and CEC_POWER_UP to 0. This method allows an external processor to put the system in which the ADV7612 is integrated into standby mode. In this case, the CP and HDMI cores of the ADV7612 are kept powered up from the main power (for example, ac power) and set in or out of power-down Mode 0 through the POWER_DOWN bit.

Power-Down Mode 1

Power-Down Mode 1 is enabled when the following conditions are met:

• POWER_DOWN bit is set to 1

• CEC section is enabled by setting CEC_POWER_UP to 1

Power-Down Mode 1 provides the same functionality as Power-Down Mode 0, with the addition of the following sections:

• XTAL clock

• CEC section

• Interrupt controller section

The following pads are enabled in Power-Down Mode 1:

• Same pads as enabled in Power-Down Mode 0

• CEC pad

• INT1 and INT2 interrupt pads

The internal EDID is also accessible through the DDC bus for Port A and Port B in Power-Down Mode 0 and Power-Down Mode 1.

GLOBAL PIN CONTROL

RESET

The ADV7612 can be reset by a low reset pulse on the reset pin with a minimum width of 5 ms. It is recommended to wait 5 ms after the low pulse before an I

Reset Controls

MAIN_RESET, IO, Address 0xFF[7] (Self-Clearing)

Main reset where I

Function MAIN_RESET Description

0 (default) Normal operation 1 Applies main I2C reset

Tristate Output Drivers

PA DS_PDN , IO, Address 0x0C[0]

A power-down control for pads of the digital output s. When enabled, the pads are tristated and the input path is disabled. This control applies to the DE, HS, VS/FIELD/ALSB, INT1, and LLC pads and to the P0 to P35 pixel pads.

Function

0 (default) Powers up pads of digital output pins 1 Powers down pads of digital output pins

DDC_PWRDN[7:0], Addr 68 (HDMI), Address 0x73[7:0]

A power-down control for DDC pads.

Function DDC_PWRDN[7:0] Description

00000000 (default) Powers up DDC pads

xxxxxxx1 xxxxxx1x

C write is performed to the ADV7612.

C registers are reset to their default values.

Powers down DDC pads on Port A Powers down DDC pads on Port B

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TRI_PIX

This bit allows the user to tristate the output driver of pixel outputs. Upon setting TRI_PIX, the pixel output P[35:0] is tristated.

TRI_PIX, IO, Address 0x15[1]

A control to tristate the pixel data on the pixel pins, P[35:0].

Function TRI_PIX Description

0 Pixel bus active 1 (default) Tristates pixel bus

Tristate LLC Driver

TRI_LLC, IO, Address 0x15[2]

A control to tristate the output pixel clock on the LLC pin.

Function TRI_LLC Description

0 LLC pin active 1 (default) Tristates LLC pin

Tristate Synchronization Output Drivers

The following output synchronization signals are tristated when TRI_SYNCS is set:

• VS/FIELD/ALSB

• HS

• DE

The drive strength controls for these signals are provided via the DR_STR_SYNC bits. The ADV7612 does not support tristating via a dedicated pin.

TRI_SYNCS, IO, Address 0x15[3]

Synchronization output pins tristate control. The synchronization pins under this control are HS, VS/FIELD/ALSB, and DE.

Function TRI_SYNCS Description

0 Sync output pins active 1 (default) Tristates sync output pins

Tristate Audio Output Drivers

TRI_AUDIO, IO Map, Address 0x15, [4]

TRI_AUDIO allows the user to tristate the drivers of the following audio output signals:

• AP0

• AP1

• AP2

• AP3

• AP4

• AP5

• SCLK/INT2

• MCLK/INT2

The drive strength for the output pins can be controlled by the DR_STR[1:0] bits. The ADV7612 does not support tristating via a dedicated pin.

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1 (default)

Tristates audio output pins

High (4×) for LLC greater than 100 MHz

TRI_AUDIO, IO, Address 0x15[4]

A control to tristate the audio output interface pins (AP0, AP1, AP2, … , AP5).

Function TRI_AUDIO Description

0 Audio output pins active

Drive Strength Selection

DR_STR

It may be desirable to strengthen or weaken the drive strength of the output drivers for Electromagnetic Compatibility (EMC) and crosstalk reasons. This section describes the controls to adjust the output drivers used by the CP and HDMI modes.

The drive strenth DR_STR_SYNC[1:0] bits allow the user to select the strength of the following synchronization signals:

• DE

• HS

• VS/FIELD

The DR_STR[1:0] drive strength bits affect output drivers for the following output pins:

• P[35:0]

• AP0-AP5

• SCLK

• SDA

• SCL

The drive strength DR_STR_CLK[1:0] bits affect output driver for LLC line.

DR_STR[1:0], IO, Address 0x14[5:4]

A control to set the drive strength of the data output drivers.

Function DR_STR[1:0] Description

00 Reserved 01 Medium low (2×) 10 (default) Medium high (3×) 11 High (4×)

DR_STR_CLK[1:0], IO, Address 0x14[3:2]

A control to set the drive strength control for the output pixel clock out signal on the LLC pin.

Function DR_STR_CLK[1:0] Description

00 Reserved 01 Medium low (2×) for LLC up to 60 MHz 10 (default) Medium high (3×) for LLC from 44 MHz to 105 MHz

DR_STR_SYNC[1:0], IO, Address 0x14[1:0]

A control to set the drive strength of the synchronization pins, HS, VS/FIELD/ALSB, and DE.

Function DR_STR_SYNC[1:0] Description

00 Reserved 01 Medium low (2×) 10 (default) Medium high (3×) 11 High (4×)

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0 (default)

Selects DE output on DE pin

Positive polarity HS

Output Synchronization Selection

VS_OUT_SEL, IO, Address 0x06[7]

A control to select the VSync or FIELD signal to be output on the VS/FIELD/ALSB pin.

Function VS_OUT_SEL Description

0 Selects FIELD output on VS/FIELD/ALSB pin 1 (default) Selects VSync output on VS/FIELD/ALSB pin

F_OUT_SEL, IO, Address 0x05[4]

A control to select the DE or FIELD signal to be output on the DE pin.

Function F_OUT_SEL Description

1 Selects FIELD output on DE pin

Output Synchronization Signals Polarity

INV_LLC_POL, IO Map, Address 0x06, [0]

The polarity of the pixel clock provided by the ADV7612 via the LLC pin can be inverted using the INV_LLC_POL bit. Note that this inversion affects only the LLC output pin. The other output pins are not affected by INV_LLC_POL.

Changing the polarity of the LLC clock output may be necessary in order to meet the setup and hold time expectations of the downstream devices processing the output data of the ADV7612. It is expected that these parameters must be matched regardless of the type of video data that is transmitted. Therefore, INV_LLC_POL is designed to be mode independent.

INV_LLC_POL, IO, Address 0x06[0]

A control to select the polarity of the LLC.

Function INV_LLC_POL Description

0 (default) Does not invert LLC 1 Inverts LLC

The output synchronization signals HS, VS/FIELD/ALSB, and DE can be inverted using the following control bits:

• INV_HS_POL

• INV_VS_POL

• INV_F_POL

INV_HS_POL, IO, Address 0x06[1]

A control to select the polarity of the HS signal.

Function INV_HS_POL Description

0 (default) Negative polarity HS

INV_VS_POL, IO, Address 0x06[2]

A control to select the polarity of the VS/FIELD/ALSB signal.

Function INV_VS_POL Description

0 (default) Negative polarity VS/FIELD/ALSB 1 Positive polarity VS/FIELD/ALSB

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Inverted FIELD/DE polarity (negative FIELD/DE polarity)

INV_F_POL, IO, Address 0x06[3]

A control to select the polarity of the DE signal.

Function INV_F_POL Description

0 (default) Default FIELD/DE polarity (positive FIELD/DE polarity)

Digital Synthesizer Controls

The ADV7612 features two digital encoder synthesizers that generate the following clocks:

• Video DPLL: this clock synthesizer generates the pixel clock. It undoes the effect of deep color and pixel repetition that are inherent

to HDMI streams. The output of the LLC pin is either this pixel clock or a divided down version, depending on the datapath configuration. It takes less than one video frame for this synthesizer to lock.

• Audio DPLL: this clock synthesizer generates the audio clock. As per HDMI specification, the incomming HDMI clock is divided

down by CTS and then multiplied up by N. This audio clock is used as the main clock in the audio stream section. The output of MCLK represents this clock. It takes less than 5 ms after a valid ACR packet for this synthesizer to lock.

Crystal Frequency Selection

The ADV7612 supports 27.0, 28.63636, 24.576 and 24.0 MHz frequency crystals. Following control allows selecting crystal frequency.

XTAL_FREQ_SEL[1:0], IO, Address 0x04[2:1]

A control to set the XTAL frequency used.

Function XTAL_FREQ_SEL[1:0] Description

00 27 MHz 01 (default) 28.63636 MHz 10 24.576 MHz 11 24.0 MHz

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0011

Reserved

xxxxxx

Reserved

PRIMARY MODE AND VIDEO STANDARD

Setting the primary mode and choosing a video standard are the most fundamental settings when configuring the ADV7612. There are two primary modes for the ADV7612: HDMI-component and HDMI-graphic modes. The appropriate mode should be set with

PRIM_MODE[3:0].

In HDMI modes, the ADV7612 can receive and decode HDMI or DVI data throughout the DVI/HDMI receiver front end. Video data from the HDMI receiver is routed to the CP block while audio data is available on the audio interface. One of these modes is enabled by selecting either the HDMI-component or the HDMI-graphics primary mode.

Note: The HDMI receiver decodes and processes any applied HDMI stream irrespective of the video resolution. However, many primary mode and video standard combinations can be used to define how the decoded video data routed to the DPP and CP blocks is processed. This allows for free run features and data decimation modes that some systems may require.

If free run and decimation are not required, it is recommended to set the following configuration for HDMI mode:

• PRIM_MODE[3:0]: 0x06

• VID_STD[5:0]: 0x02

PRIMARY MODE AND VIDEO STANDARD CONTROLS

PRIM_MODE[3:0], IO, Address 0x01[3:0]

A control to select the primary mode of operation of the decoder. Setting the appropriate HDMI mode is important for free run mode to work properly. This control is used with VID_STD[5:0].

Function PRIM_MODE[3:0] Description

0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 HDMI component 0110 (default) HDMI graphics 0111 to 1111 Reserved

VID_STD[5:0], IO, Address 0x00[5:0]

Sets the input video standard mode. Configuration is dependent on PRIM_MODE[3:0]. Setting the appropriate mode is important for free run mode to work properly.

Function VID_STD[5:0] Description

000010 Default value

PRIM_MODE[3:0] should be used with VID_STD[5:0] to select the required video mode. These controls are set according to Tab le 6.

Table 6. Primary Mode and Video Standard Selection

PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment

0000 Reserved xxxxxx Reserved Reserved 0001 Reserved xxxxxx Reserved Reserved 0010 Reserved xxxxxx Reserved Reserved 0100 Reserved xxxxxx Reserved Reserved

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001011

PR 1×1 625p

720 × 576

001110

XGA

1024 × 768 @ 75

PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment

0101 HDMI-COMP

(Component video)

0110 HDMI-GR

(Graphics)

CP 000000 SD 1×1 525i 720 × 480 HDMI receiver support CP 000001 SD 1×1 625i 720 × 576 CP 000010 SD 2×1 525i 720 × 480 CP 000011 SD 2×1 625i 720 × 576 000100 Reserved Reserved 000101 Reserved Reserved 000110 Reserved Reserved 000111 Reserved Reserved 001000 Reserved Reserved 001001 Reserved Reserved CP 001010 PR 1×1 525p 720 × 480

CP 001100 PR 2×1 525p 720 × 480 CP 001101 PR 2×1 625p 720 × 576 001110 Reserved Reserved 001111 Reserved Reserved 010000 Reserved Reserved 010001 Reserved Reserved 010010 Reserved Reserved CP 010011 HD 1×1 1280 × 720 CP 010100 HD 1×1 1920 × 1080 CP 010101 HD 1×1 1920 × 1035 CP 010110 HD 1×1 1920 × 1080 CP 010111 HD 1×1 1920 × 1152 011000 Reserved Reserved CP 011001 HD 2×1 720p 1280 × 720 CP 011010 HD 2×1 1125 1920 × 1080 CP 011011 HD 2×1 1125 1920 × 1035 CP 011100 HD 2×1 1250 1920 × 1080 CP 011101 HD 2×1 1250 1920 × 1152 CP 011110 HD 1×1 1920 × 1080 CP 011111 HD 1×1 1920 × 1080 CP 000000 SVGA 800 × 600 @ 56 CP 000001 SVGA 800 × 600 @ 60 CP 000010 SVGA 800 × 600 @ 72 CP 000011 SVGA 800 × 600 @ 75 CP 000100 SVGA 800 × 600 @ 85 CP 000101 SXGA 1280 × 1024 @ 60 CP 000110 SXGA 1280 × 1024 @ 75 000111 Reserved Reserved CP 001000 VGA 640 × 480 @ 60 CP 001001 VGA 640 × 480 @ 72 CP 001010 VGA 640 × 480 @ 75 CP 001011 VGA 640 × 480 @ 85 CP 001100 XGA 1024 × 768 @ 60 CP 001101 XGA 1024 × 768 @ 70

HDMI receiver support

0111 Reserved xxxxxx Reserved Reserved 1000 Reserved xxxxxx Reserved Reserved 1001 Reserved xxxxxx Reserved Reserved

CP 001111 XGA 1024 × 768 @ 85 01xxxx Reserved

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PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment

1010 Reserved xxxxxx Reserved Reserved 1011 Reserved xxxxxx Reserved Reserved 1100 Reserved xxxxxx Reserved Reserved 1101 Reserved xxxxxx Reserved Reserved 1110 Reserved xxxxxx Reserved Reserved 1111 Reserved xxxxxx Reserved Reserved

V_FREQ

This control is set to allow free run to work correctly (refer to Tab le 7).

V_FREQ[2:0], IO, Address 0x01[6:4]

A control to set vertical frequency.

Function V_FREQ[2:0] Description

000 (default) 60 Hz 001 50 Hz 010 30 Hz 011 25 Hz 100 24 Hz 101 Reserved 110 Reserved 111 Reserved

HDMI DECIMATION MODES

Some of the modes defined by VID_STD have an inherent 2×1 decimation. For these modes, the main clock generator and the decimation filters in the DPP block are configured automatically. This ensures the correct data rate at the input to the CP block. Refer to the Data Preprocessor and Color Space Conversion and Color Controls section for more information on the automatic configuration of the DPP block.

The ADV7612 correctly decodes and processes any incoming HDMI stream with the required decimation, irrespective of its video resolution:

• In 1×1 mode (that is, without decimation), as long the PRIM_MODE and VID_STD registers are programmed for any HDMI mode

without decimation. For example:

• Set PRIM_MODE to 0x5 and VID_STD to 0x00

• Set PRIM_MODE to 0x5 and VID_STD to 0x13

• Set PRIM_MODE to 0x6 and VID_STD to 0x02

• In 2×1 decimation mode, as long the PRIM_MODE and VID_STD registers are programmed for any HDMI mode with 2×1

decimation. For example:

• Set PRIM_MODE to 0x5 and VID_STD to 0x0C

• Set PRIM_MODE to 0x5 and VID_STD to 0x19

Note: Decimating the video data from an HDMI stream is optional and should be performed only if it is required by the downstream devices connected to the ADV7612.

PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN

If free run is enabled in HDMI mode, PRIM_MODE[3:0] and VID_STD[5:0] specify the input resolution expected by the ADV7612 (for free run Mode 1) and/or the output resolution to which the ADV7612 free runs (for free run Mode 0 and Mode 1). Refer to the Free Run Mode section for additional details on the free run feature for HDMI inputs and to HDMI_FRUN_MODE.

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6, 7

720 (1440) × 480i @ 60 Hz

PRIM_MODE = 0x6

PRIM_MODE = 0x5

1920 × 1080p @ 25 Hz

PRIM_MODE = 0x6

PRIM_MODE = 0x5

RECOMMENDED SETTINGS FOR HDMI INPUTS

This section provides the recommended settings for an HDMI input encapsulating a video resolution corresponding to a selection Video ID Code described in the 861 specification.

Table 7 provides the recommended settings for the following registers:

• PRIM_MODE

• VID_STD

• V_FREQ (V_FREQ should be set to 0x0 if not specified in Tabl e 7.)

• INV_HS_POL = 1 (INV_HS_POL should be set to 1 if not specified in Ta ble 7.)

• INV_VS_POL = 1 (INV_VS_POL should be set to 1 if not specified in Tab le 7.)

Table 7. Recommended Settings for HDMI Inputs

Recommended Settings Video ID Codes (861 Specification) Formats

2, 3 720 × 480p @ 60 Hz 0 PRIM_MODE = 0x6

4 1280 × 720p @ 60 Hz 0 PRIM_MODE = 0x6

5 1920 × 1080i @ 60 Hz 0 PRIM_MODE = 0x6

Pixel Repetition

if Free Run Used and

DIS_AUTOPARAM_BUFFER = 0

VID_STD = 0x2

Recommended Settings if Free Run Not Used or Free Run Used and DIS_AUTO_PARAM_BUFFER = 1

PRIM_MODE = 0x5 VID_STD = 0xA PRIM_MODE = 0x5 VID_STD = 0x13 PRIM_MODE = 0x5 VID_STD = 0x14

VID_STD = 0x2 10, 11 2880 × 480i @ 60 Hz 3 PRIM_MODE = 0x6

VID_STD = 0x2 14, 15 1440 × 480p @ 60 Hz 1 PRIM_MODE = 0x6

VID_STD = 0x2 16 1920 × 1080p @ 60 Hz 0 PRIM_MODE = 0x6

VID_STD = 0x2 17, 18 720 × 576p @ 60 Hz 0 PRIM_MODE = 0x6

VID_STD = 0x2 19 1280 × 720p @ 50 Hz 0 PRIM_MODE = 0x6

VID_STD = 0x2

20 1920 × 1080i @ 50 Hz 0 PRIM_MODE = 0x6

VID_STD = 0x2

21, 22 720 (1440) ×576i @ 60 Hz 1 PRIM_MODE = 0x6

VID_STD = 0x2 25, 26 2880 × 480i @ 60 Hz 3 PRIM_MODE = 0x6

VID_STD = 0x2 29, 30 144 0× 576p @ 60 Hz 1 PRIM_MODE = 0x6

VID_STD = 0x2 31 1920 × 1080p @ 50 Hz 0 PRIM_MODE = 0x6

VID_STD = 0x2

32 1920 × 1080p @ 24 Hz 0 PRIM_MODE = 0x6

VID_STD = 0x2

VID_STD = 0x0 PRIM_MODE = 0x5 VID_STD = 0x0 PRIM_MODE=0x5 VID_STD = 0xA PRIM_MODE = 0x5 VID_STD = 0x1E PRIM_MODE = 0x5 VID_STD = 0xB PRIM_MODE = 0x5 VID_STD = 0xA3 V_FREQ = 0x1 PRIM_MODE = 0x5 VID_STD = 0x14 V_FREQ = 0x1 PRIM_MODE = 0x5 VID_STD = 0x1 PRIM_MODE=0x5 VID_STD = 0x1 PRIM_MODE = 0x5 VID_STD = 0xA PRIM_MODE = 0x5 VID_STD = 0x1E V_FREQ = 0x1 PRIM_MODE = 0x5 VID_STD = 0x1E V_FREQ = 0x4

35, 36 2880 × 480p @ 60 Hz 3 PRIM_MODE = 0x6

37, 38 2880 × 576p @ 60 Hz 3 PRIM_MODE = 0x6

VID_STD = 0x2

Rev. B | Page 25 of 204

VID_STD = 0x1E V_FREQ = 0x3 PRIM_MODE = 0x5 VID_STD = 0xA PRIM_MODE = 0x5 VID_STD = 0xA

UG-216 Hardware User Guide

N/A

VGA 640 × 480p @ 60

PRIM_MODE = 0x6

N/A SVGA 800 × 600p @ 56 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A SVGA 800 × 600p @ 60 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A SVGA 800 × 600p @ 72 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A SVGA 800 × 600p @ 75 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A SVGA 800 × 600p @ 85 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A SXGA 1280 × 1024p @ 60 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A SXGA 1280 × 1024p @ 75 0 PRIM_MODE = 0x6

VID_STD = 0x0

PRIM_MODE = 0x6 VID_STD = 0x0 PRIM_MODE = 0x6 VID_STD = 0x1 PRIM_MODE = 0x6 VID_STD = 0x2 PRIM_MODE = 0x6 VID_STD = 0x3 PRIM_MODE = 0x6 VID_STD = 0x04 PRIM_MODE = 0x6 VID_STD = 0x05 PRIM_MODE = 0x6 VID_STD = 0x06

VID_STD = 0x0

N/A VGA 640 × 480p @ 72 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A VGA 640 × 480p @ 75 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A VGA 640 × 480p @ 85 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A VGA 1024 × 768p @ 60 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A VGA 1024 × 768p @ 70 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A VGA 1024 × 768p @ 75 0 PRIM_MODE = 0x6

VID_STD = 0x0

N/A VGA 1024 × 768p @ 85 0 PRIM_MODE = 0x6

VID_STD = 0x0

VID_STD = 0x08 PRIM_MODE = 0x6 VID_STD = 0x09 PRIM_MODE = 0x6 VID_STD = 0x0A PRIM_MODE = 0x6 VID_STD = 0x0B PRIM_MODE = 0x6 VID_STD = 0x0C PRIM_MODE = 0x6 VID_STD = 0x0D PRIM_MODE = 0x6 VID_STD = 0x0E PRIM_MODE = 0x6 VID_STD = 0x0F

Rev. B | Page 26 of 204

Hardware User Guide UG-216

Function

OP_FORMAT_SEL[7:0]

Description

0x00 (default)1

8-bit SDR ITU-656 mode

0x011

10-bit SDR ITU-656 mode

0x021

12-bit SDR ITU-656 Mode 0

0x061

12-bit SDR ITU-656 Mode 1

0x0A1

12-bit SDR ITU Mode 2

0x20

8-bit 4:2:2 DDR mode

0x21

10-bit 4:2:2 DDR Mode

0x22

12-bit 4:2:2 DDR Mode 0

0x23

12-bit 4:2:2 DDR Mode 1

0x24

12-bit 4:2:2 DDR Mode 2

0x40

24-bit 4:4:4 SDR mode

0x41

30-bit 4:4:4 SDR mode

0x42

36-bit 4:4:4 SDR Mode 0

0x46

36-bit SDR 4:4:4 Mode 1

0x4C

24-bit SDR 4:4:4 Mode 3

0x50

24-bit SDR 4:4:4 Mode 4

0x51

30-bit SDR 4:4:4 Mode 4

0x52

36-bit SDR 4:4:4 Mode 4

0x60

24-bit 4:4:4 DDR mode

0x61

30-bit 4:4:4 DDR mode

0x62

36-bit 4:4:4 DDR mode

0x80

16-bit ITU-656 SDR mode

0x81

20-bit ITU-656 SDR mode

0x82

24-bit ITU-656 SDR Mode 0

0x86

24-bit ITU-656 SDR Mode 1

0x8A

24-bit ITU-656 SDR Mode 2

0x90

16-bit SDR 4:2:2 Mode 4

0x91

20-bit SDR 4:2:2 Mode 4

0x92

24-bit SDR 4:2:2 Mode 4

Function

OP_CH_SEL[2:0]

Description

000

P[35:24] Y/G, P[23:12] U/CrCb/B, P[11:0] V/R

001

P[35:24] Y/G, P[23:12] V/R, P[11:0] U/CrCb/B

010

P[35:24] U/CrCb/B, P[23:12] Y/G, P[11:0] V/R

011 (default)

P[35:24] V/R, P[23:12] Y/G, P[11:0] U/CrCb/B

100

P[35:24] U/CrCb/B, P[23:12] V/R, P[11:0]Y/G

101

P[35:24] V/R, P[23:12] U/CrCb/B, P[11:0] Y/G

110

Reserved

111

Reserved

PIXEL PORT CONFIGURATION

The ADV7612 has a very flexible pixel port, which can be configured in a variety of formats to accommodate downstream ICs. The ADV7612 can provide output modes up to 36 bits.

This section details the controls required to configure the ADV7612 pixel port. Appendix C contains tables describing pixel port configurations.

PIXEL PORT OUTPUT MODES

OP_FORMAT_SEL[7:0], IO, Address 0x03[7:0]

A control to select the data format and pixel bus configuration. for full information on pixel port modes and configuration settings.

Refer to the DLL settings for 656, 8-/10-/12-bit modes in the DLL on LLC Clock Path section.

Bus Rotation and Reordering Controls

Bus reordering controls are available for ADV7612. OP_CH_SEL[2:0] allows the three output buses to be rearranged, thus providing six different output possibilities.

OP_CH_SEL[2:0], IO, Address 0x04[7:5]

A control to select the configuration of the pixel data bus on the pixel pins. Refer to the pixel port configuration for full information on pixel port modes and configuration settings.

Rev. B | Page 27 of 204

UG-216 Hardware User Guide

Pixel Data and Synchronization Signals Control

The polarity of the LLC and synchronization signals can be inverted, and the LLC, the synchronization signals, and the pixel data output can be tristated. Refer to the information on the following controls:

• INV_F_POL

• INV_VS_POL

• INV_HS_POL

• TRI_PIX

• TRI_LLC

• TRI_SYNCS

OP_SWAP_CB_CR, IO, Address 0x05[0]

Controls the swapping of Cr and Cb data on the pixel buses.

Function OP_SWAP_CB_CR Description

0 (default) Outputs Cr and Cb as per OP_FORMAT_SEL 1 Inverts the order of Cb and Cr in the interleaved data stream

OP_SWAP_CB_CR swaps the order in which Cb and Cr are interleaved in the output data stream. It caters for cases in which the data on Channels B and C are swapped. It is effective only if OP_FORMAT_SEL[7:0] is set to a 4:2:2 compatible output mode.

Note: It has no effect for 36-bit SDR modes and DDR modes.

LLC CONTROLS

The ADV7612 has a limited number of adjustment features available for the line locked clock (LLC) output. The polarity of the LLC can be inverted and the LLC of the output driver can be tristated. Controls also exist to skew the LLC versus the output data to achieve suitable setup and hold times for any back end device.

The LLC controls are as follows:

• INV_LLC_POL

• TRI_LLC

• LLC_DLL_EN

• LLC_DLL_MUX

• LLC_DLL_PHASE[4:0]

DLL ON LLC CLOCK PATH

A delay locked loop (DLL) block is implemented on the LLC clock path. This DLL allows the changing of the phase of the output pixel clock on the LLC pin.

LLC_DLL_DOUBLE, IO, Address 0x19[6]

A control to double LLC frequency.

Function LLC_DLL_DOUBLE Description

0 (default) Normal LLC frequency 1 Double LLC frequency

Adjusting DLL Phase in All Modes

LLC_DLL_EN, IO, Address 0x19[7]

A control to enable the DLL for the output pixel clock.

Function LLC_DLL_EN Description

1 Enables LLC DLL 0 (default) Disables LLC DLL

Rev. B | Page 28 of 204

Hardware User Guide UG-216

LLC_DLL_MUX

Description

0 (default)

Bypasses the DLL

Muxes the DLL output on LLC output

LLC_DLL_MUX, IO, Address 0x33[6]

A control to apply the pixel clock DLL to the pixel clock output on the LLC pin.

Function

LLC_DLL_PHASE[4:0], IO, Address 0x19[4:0]

A control to adjust LLC DLL phase in increments of 1/32 of a clock period.

Function LLC_DLL_PHASE[4:0] Description

00000 (default) Default xxxxx Sets one of 32 phases of DLL to vary LLC CLK

DLL Settings for 656, 8-/10-/12-Bit Modes

Table 8 and Table 9 show the settings that must be used to enable 8-/10-/12-bit, 656 output. Note that the 720p 8-/10-/12-bit mode must use OP_FORMAT_SEL = 0x20 or 0x2A (refer to Ta ble 78). Doubling the clock as per Table 8 undoes the DDR mode.

Table 8. DLL Settings for 8-/12-Bit Pixel Bus Output

Address Setting Description

IO Map Address 0x03[7:0] Refer to Table 9 OP_FORMAT_SEL value IO Map Address 0x19[7] 1 Enables LLC DLL IO Map Address 0x33[6] 1 Muxes the DLL output on LLC output IO Map Address 0x19[6] 1 Doubles the clock

Table 9. OP_FORMAT_SEL Settings for 8-/12-Bit Pixel Bus Output (To Be Used With Settings from Table 8)

Input Video OP_FORMAT_SEL Value Output Clock Frequency after Clock Doubling

480i, 576i 8-bit 0x00 27 MHz 480i, 576i 10-/12-bit 0x0A 27 MHz 480p, 576p 8-bit 0x00 54 MHz 480p, 576p 10-/12-bit 0x0A 54 MHz 720p 8-bit 0x20 148.5 MHz 720p 10-/12-bit 0x2A 148.5 MHz

Rev. B | Page 29 of 204

UG-216 Hardware User Guide

HDMI RECEIVER

HPA_A/INT2

HPA_B RXA_5V RXB_5V

CEC

DDCA_SDA/DDCA_SC L DDCA_SDA/DDCB_SC L

RXA_C± RXB_C±

RXA_0± RXA_1± RXA_2±

+5 V CABLE DETECT

The HDMI receiver in the ADV7612 can monitor the level on the +5 V power signal pin of the HDMI port. The results of this detection can be read back from the following I

CABLE_DET_A_RAW, IO, Address 0x6F[0] (Read Only)

Raw status of Port A +5 V cable detection signal.

Function CABLE_DET_A_RAW Description

0 (default) No cable detected on Port A 1 Cable detected on Port A (high level on RXA_5V)

CABLE_DET_B_RAW, IO, Address 0x6A[7] (Read Only)

Raw status of Port B +5 V cable detection signal.

Function CABLE_DET_A_RAW Description

0 (default) No cable detected on Port B 1 Cable detected on Port A (high level on RXB_5V)

The ADV7612 provides a digital glitch filter on the +5 V power signals from the HDMI port. The output of this filter is used to reset the HDMI block (refer to the HDMI Section Reset Strategy section).

The +5 V power signal must be constantly high for the duration of the timer (controlled by FILT_5V_DET_TIMER[6:0]), otherwise the output of the filter is low. The output of the filter returns low as soon as any change in the +5 V power signal is detected.

FILT_5V_DET_DIS, Addr 68 (HDMI), Address 0x56[7]

This control is used to disable the digital glitch filter on the HDMI 5 V detect signals. The filtered signals are used as interrupt flags and used to reset the HDMI section. The filter works from an internal ring oscillator clock and, therefore, is available in power-down mode. The clock frequency of the ring oscillator is 42 MHz ± 10%.

Function FILT_5V_DET_DIS Description

0 (default) Enabled 1 Disabled

Note: If the +5 V pins are not used and are left unconnected, the +5 V detect circuitry must be disconnected from the HDMI reset signal by setting DIS_CABLE_DET_RST to 1. This avoids holding the HDMI section in reset.

5V DETECT

AND HPA

CONTROLLER

EDID/

REPEATER

CONTROLLER

PLL

EQUALIZER

CEC

HDCP

EEPROM

HDCP

BLOCK

SAMPLER

SAMPLEREQUALIZER

DEEP COLOR CONVERSION

DATA

4:2:2 TO 4: 4: 4 CONVERSION

FILTER

PACKET/

INFOFRAME

+ MUX

FAST SWITCHING BLOCK

HDMI DECODE + PORT MEASUR EMENT

MEMORY

PACKET

PROCESSOR

HS VS DE

AUDIO

PROCESSOR

AUDIO OUTPOUT FORMATTER

TO INTERRUPT CONTROLLER

TO DPP TO DPP TO DPP TO DPP

AP0 AP1/I2S_TDM AP2 AP3 AP4 AP5

SCLK/INT2 MCLK/INT2

Figure 3. Functional Block Diagram of HDMI Core

C registers. These readbacks are valid even when the part is not configured for HDMI mode.

09486-004

Rev. B | Page 30 of 204

+ 174 hidden pages

ANALOG DEVICES UG-216 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SCOPE

DISCLAIMER

FUNCTIONAL BLOCK DIAGRAM

REVISION HISTORY

USING THE ADV7612 HARDWARE USER GUIDE

NUMBER NOTATIONS

REGISTER ACCESS CONVENTIONS

ACRONYMS AND ABBREVIATIONS

FIELD FUNCTION DESCRIPTIONS

Example Field Function Description

REFERENCES

INTRODUCTION TO THE ADV7612

HDMI RECEIVER

COMPONENT PROCESSOR

MAIN FEATURES OF ADV7612

HDMI Receiver

Component Video Processing

Video Output Formats

Additional Features

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GLOBAL CONTROL REGISTERS

ADV7612 REVISION IDENTIFICATION

POWER-DOWN CONTROLS

Primary Power-Down Controls

Secondary Power-Down Controls

XTAL_PDN

CORE_PDN

Power-Down Modes

Power-Down Mode 0

Power-Down Mode 1

GLOBAL PIN CONTROL

Reset Controls

Tristate Output Drivers

TRI_PIX

Tristate LLC Driver

Tristate Synchronization Output Drivers

Tristate Audio Output Drivers

Drive Strength Selection

DR_STR

Output Synchronization Selection

Output Synchronization Signals Polarity

Digital Synthesizer Controls

Crystal Frequency Selection

PRIMARY MODE AND VIDEO STANDARD

PRIMARY MODE AND VIDEO STANDARD CONTROLS

V_FREQ

HDMI DECIMATION MODES

PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN

RECOMMENDED SETTINGS FOR HDMI INPUTS

PIXEL PORT CONFIGURATION

PIXEL PORT OUTPUT MODES

Bus Rotation and Reordering Controls

Pixel Data and Synchronization Signals Control

LLC CONTROLS

DLL ON LLC CLOCK PATH

Adjusting DLL Phase in All Modes

DLL Settings for 656, 8-/10-/12-Bit Modes

HDMI RECEIVER

+5 V CABLE DETECT