ANALOG DEVICES UG-074 Service Manual

Evaluation Board User Guide

One Technology Way • P. O . Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel : [phone] • Fax : [phone] • www.analog.com

UG-074

Evaluating the AD9265/AD9255 Analog-to-Digital Converters

FEATURES

Full featured evaluation board for the AD9265/AD9255
SPI interface for setup and control
External, on-board oscillator or AD9517 clocking options
Balun/transformer or amplifier input drive options
LDO regulator or switching power supply options
VisualAnalog® and SPI controller software interfaces

EQUIPMENT NEEDED

Analog signal source and antialiasing filter
Sample clock source (if not using the on-board oscillator)
2 switching power supplies (6.0 V, 2.5 A) provided, CUI, Inc.,

EPS060250UH-PHP-SZ
PC running Windows® XP or Windows Vista
USB 2.0 port recommended (USB 1.1 compatible)
AD9265 or AD9255 evaluation board
HSC-ADC-EVALCZ FPGA-based data capture kit

SOFTWARE NEEDED

VisualAnalog
SPI controller

EVALUATION BOARDS

DOCUMENTS NEEDED

AD9265 or AD9255 data sheet
HSC-ADC-EVALCZ data sheet
AN-905 Application Note, VisualAnalog Converter Evaluation

Tool Version 1.0 User Manual

AN-878 Application Note, High Speed ADC SPI Control Software
AN-877 Application Note, Interfacing to High Speed ADCs via SPI
AN-835 Application Note, Understanding High Speed ADC

Tes ti ng an d Ev al uati on

GENERAL DESCRIPTION

This user guide describes the AD9265 and AD9255 evaluation
board, which provides all of the support circuitry required to
operate the AD9265 or AD9255 in its various modes and
configurations. The application software used to interface with
the devices is also described.

The AD9265 and AD9255 data sheets provide additional
information and should be consulted when using the evaluation
board. All documents and software tools are available at

www.analog.com/fifo. For additional information or questions,

send an email to [e-mail].

Figure 1. AD9265 and AD9255 Evaluation Board and HSC-ADC-EVALCZ Data Capture Board

Please see the last page for an important warning and disclaimers. Rev. 0 | Page 1 of 28

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UG-074 Evaluation Board User Guide

TABLE OF CONTENTS

Features .............................................................................................. 1

Equipment Needed ........................................................................... 1

Software Needed ............................................................................... 1

Documents Needed .......................................................................... 1

General Description ......................................................................... 1

Evaluation Boards ............................................................................. 1

Revision History ............................................................................... 2

Evaluation Board Hardware ............................................................ 3

Power Supplies .............................................................................. 3

REVISION HISTORY

1/11—Revision 0: Initial Version

Input Signals...................................................................................3

Output Signals ...............................................................................3

Default Operation and Jumper Selection Settings ....................5

Evaluation Board Software Quick Start Procedures .....................7

Configuring the Board .................................................................7

Using the Software for Testing .....................................................7

Evaluation Board Schematics and Artwork ................................ 11

Ordering Information .................................................................... 24

Bill of Materials ........................................................................... 24

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Evaluation Board User Guide UG-074

EVALUATION BOARD HARDWARE

The AD9265 and AD9255 evaluation board provides all of the
support circuitry required to operate these parts in their various
modes and configurations. Figure 2 shows the typical bench
characterization setup used to evaluate the ac performance of
the AD9265 or AD9255. It is critical that the signal sources used
for the analog input and clock have very low phase noise (<1 ps
rms jitter) to realize the optimum performance of the signal
chain. Proper filtering of the analog input signal to remove
harmonics and lower the integrated or broadband noise at the
input is necessary to achieve the specified noise performance.

See the Evaluation Board Software Quick Start Procedures section
to get started, and see Figure 15 to Figure 28 for the complete
schematics and layout diagrams. These diagrams demonstrate
the routing and grounding techniques that should be applied at
the system level when designing application boards using these
converters.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Connect
the supply to the rated 100 V ac to the 240 V ac wall outlet at
47 Hz to 63 Hz. The output from the supply is provided through
a 2.1 mm inner diameter jack that connects to the printed circuit
board (PCB) at P26. The 6 V supply is fused and conditioned
on the PCB before connecting to the low dropout linear regulators
(default configuration) that supply the proper bias to each of the
various sections on the board.

The evaluation board can be powered in a nondefault condition
using external bench power supplies. To do this, the P27, P28,
P31, P30, P32, and P29 jumpers can be removed to disconnect
the outputs from the on-board LDOs. This enables the user to
bias each section of the board individually. Use P8 and P9 to
connect a different supply for each section. A 1.8 V supply is
needed with a 1 A current capability for AVDD, SVDD, and
DRVDD; however, it is recommended that separate supplies be
used for both analog and digital domains. An additional supply
is also required to supply 1.8 V for digital support circuitry on
the board, 3V_DIG. This should also have a 1 A current capability
and can be combined with DRVDD with little or no degradation in
performance.

Two additional supplies, 5V_AVDD and 3V_AVDD, are used to
bias the optional input path amplifiers. If used, these supplies
should each have a 1 A current capability. P18 is also necessary if
an amp that requires a negative supply voltage is being used.

A second optional power supply configuration allows the
replacement of the LDOs that supply the AVDD and DRVDD
rails of the ADC with the ADP2108 step-down dc-to-dc converter.
Using this switching controller in place of the LDO regulators
to power the AVDD and DRVDD supplies of the ADC allows
customers to evaluate the performance of the ADC when
powered by a more efficient regulator.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal
generators with low phase noise, such as the Rohde & Schwarz
SMA100A, HP 8644B signal generators, or an equivalent. Use a
1 m shielded, RG-58, 50 Ω coaxial cable for connecting to the
evaluation board. Enter the desired frequency and amplitude (see
the Specifications section in the data sheet of the respective part).
When connecting the analog input source, use of a multipole,
narrow-band, band-pass filter with 50 Ω terminations is
recommended. Analog Devices, Inc., uses TTE and K&L
Microwave, Inc., band-pass filters. The filters should be
connected directly to the evaluation board.

If an external clock source is used, it should also be supplied
with a clean signal generator as previously specified. Typically,
most Analog Devices evaluation boards can accept ~2.8 V p-p or
13 dBm sine wave input for the clock.

OUTPUT SIGNALS

The default setup uses the Analog Devices high speed converter
evaluation platform (HSC-ADC-EVALCZ) for data capture. The
CMOS output signals are buffered through U2 and are routed
through P2 to the FPGA on the data capture board.

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UG-074 Evaluation Board User Guide

WALL OUTLET

100V AC TO 240V AC

47Hz TO 63Hz

SIGNAL

SYNTHESIZER

SWITCHING
POWER
SUPPLY

SWITCHING
POWER
SUPPLY

ANALOG INPUT

6V DC
2A MAX

SIGNAL

SYNTHESIZER

6V DC

2A MAX

PC

RUNNING ADC

ANALYZER

OR VISUAL ANALOG

USER SOFTWARE

OPTIONAL CLOCK SOURCE

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Figure 2. Evaluation Board Connection

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Evaluation Board User Guide UG-074

2

p

DEFAULT OPERATION AND JUMPER SELECTION SETTINGS

This section explains the default and optional settings or modes
allowed on the AD9265/AD9255 Rev. A evaluation board.

Power Circuitry

Connect the switching power supply that is supplied in the
evaluation kit between P26 and a rated 100 V ac to 240 V ac
wall outlet at 47 Hz to 63 Hz.

Analog Input

The inputs on the evaluation board are set up for a double balun­coupled analog input with a 50 Ω impedance. For the AD9265/
AD9255, the default analog input configuration supports analog
input frequencies of up to ~250 MHz (see Figure 3). This input
network is optimized to support a wide frequency band. See the
AD9265 and AD9255 data sheets for additional information on
the recommended networks for different input frequency ranges.

Optionally, the analog input on the board can be configured to
use the ADL5562, which is a 3.3 GHz ultralow distortion RF/IF
differential amplifier. The ADL5562 component is included on
the evaluation board at U1. However, the path into and out of the
ADL5562 can be configured in many different ways depending
on the application; therefore, the parts in the input and output
path are left unpopulated. Users should see the ADL5562 data
sheet for additional information on this part and for configuring
the inputs and outputs. The ADL5562 is normally held in power­down mode and can be enabled by adding a jumper on P19.
The ADL5562 can also be substituted with the ADA4937-1 or
the ADA4938-1 to allow evaluation of these parts with the
ADC.

VREF

VREF is set by default to 1.0 V with SENSE connected to AGND
through a jumper connecting Pin 2 and Pin 3 on Header P5.
This causes the ADC to operate with the internal reference in
the 2.0 V p-p differential full-scale range. The reference voltage
can be changed to 0.5 V for a 1.0 V p-p full-scale range by
moving the SENSE pin jumper connection on P5 from Pin 2
and Pin 3 to Pin 1 and Pin 2 (this connects the SENSE pin to
the VREF pin).

V p-

0.1µF

S

SP

A

0.1µF

P

0.1µF

To use the programmable reference mode, a resistor divider can
be set up by installing R50 and R51. The jumper on P5 should
be removed for this mode of operation. See the data sheet of the
part for additional information on using the programmable
reference mode.

RBIAS

RBIAS has a default setting of 10 kΩ (R68) to ground and is
used to set the ADC core bias current. Note that using a resistor
value other than a 10 kΩ, 1% resistor for RBIAS may degrade
the performance of the device.

Clock Circuitry

The AD9265/AD9255 board is set by default to use an external
clock generator. An external clock source capable of driving a
50 Ω terminated input should be connected to J6. This board is
shipped from Valpey Fisher with a low phase noise oscillator
installed. The oscillator frequency is set to match the rated speed of
the part: 125 MHz, 105 MHz, or 80 MHz for the AD9265/AD9255.
To enable the oscillator, install P6, and to connect it into the
clock path, add a 0 Ω resistor at C70. R25 should also be removed
to remove the 50 Ω termination from the output of the oscillator.

A differential LVPECL clock driver output can also be used to
clock the ADC input using the AD9517-4 (U601). To place the
AD9517-4 into the clock path, populate R28 and R29 with 0 Ω
resistors and remove R30 and R31 to disconnect the default clock
path inputs. In addition, populate R85A and R86A with 0 Ω
resistors and remove R85 and R86 to disconnect the default
clock path outputs and insert the AD9517-4 OUT0 LVPECL. The
AD9517-4 must be configured through the SPI controller software
to set up the PLL and other operation modes. Consult the
AD9517-4 data sheet for more information about these and
other options.

PDWN

To enable the power-down feature, add a shorting jumper across
P7 at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD.

OEB

To disable the outputs using the OEB pin, add a shorting jumper
across P3 at Pin 1 and Pin 2 to connect the OEB pin to DRVDD.

10pF
10Ω

10Ω

33Ω

33Ω

0.1µF

10pF

10Ω 10Ω

VIN+

VIN–

ADC

VCM

10pF

Figure 3. Default Analog Input Configuration of the AD9265/AD9255

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UG-074 Evaluation Board User Guide

Non-SPI Mode

For users who want to operate the device under test (DUT) without
using SPI, remove the shorting jumpers on P4. This disconnects
the CSB, SCLK/DFS, and SDIO/DCS pins from the SPI control
bus and connects CSB to SVDD, allowing the DUT to operate in
non-SPI mode. In this mode, the SCLK/DFS and SDIO/DCS pins
take on their alternate functions to select the data format and
enable/disable the DCS. With the SDIO/DCS jumper removed,
DCS is disabled; to enable DCS, add a shorting jumper on P4
between Pin 2 and Pin 3. With the SCLK/DFS jumper removed,
the data format is set to offset binary. To set the data format to twos
complement, a jumper should be added on P4 between Pin 5
and Pin 6.

Switching Power Supply

Optionally, the ADC on the board can be configured to use the

ADP2108 dual switching power supply to provide power to the

DRVDD and AVDD rails of the ADC. To configure the board
to operate from the ADP2108, the following changes must be
incorporated (see the Evaluation Board Schematics and Artwork
and Bill of Materials sections for specific recommendations for
part values):

1. Install L2 and L3.

2. Install C77, C79, C80, and C81.

3. Install E2, E3, and E11.

4. Remove P31 and E5.

Making these changes enables the switching converter to power
the ADC. Using the switching converter as the ADC power source
is more efficient than using the default LDOs.

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Evaluation Board User Guide UG-074

EVALUATION BOARD SOFTWARE QUICK START PROCEDURES

This section provides quick start procedures for using the AD9265
and AD9255 evaluation board. Both the default and optional
settings are described.

CONFIGURING THE BOARD

Before using the software for testing, configure the evaluation
board as follows:

1. Connect the evaluation board to the data capture board,

as shown in Figure 1 and Figure 2.

2. Connect one 6 V, 2.5 A switching power supply (such as

the CUI, Inc., EPS060250UH-PHP-SZ supplied) to the

AD9265 or AD9255 board.

3. Connect one 6 V, 2.5 A switching power supply (such

as the CUI EPS060250UH-PHP-SZ supplied) to the
HSC-ADC-EVALCZ board.

4. Connect the HSC-ADC-EVALCZ board (at J6) to the PC

with a USB cable.

5. On the ADC evaluation board, confirm that three jumpers

are installed on P4, one between Pin 1 and Pin 2, one between
Pin 4 and Pin 5, and one between Pin 8 and Pin 9, to connect
the SPI bus to the DUT.

6. Make sure a low jitter sample clock is applied at J6.

7. On the ADC evaluation board, use a clean signal generator

with low phase noise to provide an input signal. Use a 1 m,
shielded, RG-58, 50 Ω coaxial cable to connect the signal
generator. For best results, use a narrow-band, band-pass
filter with 50 Ω terminations and an appropriate center
frequency. (Analog Devices uses TTE, Allen Avionics, and
K&L Microwave band-pass filters.)

USING THE SOFTWARE FOR TESTING

Setting Up the ADC Data Capture

After configuring the board, set up the ADC data capture using
the following steps:

1. Open VisualAnalog on the connected PC. The appropriate

part type should be listed in the status bar of the
VisualAnalog – New Canvas window. Select the template
that corresponds to the type of testing to be performed
(see Figure 4 where the AD9265 is shown as an example).

Figure 4. VisualAnalog – New Canvas Window

2. After the template is selected, a message appears asking if

the default configuration can be used to program the FPGA
(see Figure 5). Click Yes and the window closes.

Figure 5. VisualAnalog Default Configuration Message

3. To change features to settings other than the default settings,

click the Expand Display button, located on the bottom
right corner of the window, to see what is shown in Figure 7.
Detailed instructions for changing the features and capture
settings can be found in the AN-905 Application Note,

VisualAnalog Converter Evaluation Tool Version 1.0 User
Manual. After the changes are made to the capture settings,

click Collapse Display (see Figure 7).

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Figure 6. VisualAnalog Window Toolbar, Collapsed Display

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UG-074 Evaluation Board User Guide

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Figure 7. VisualAnalog, Main Window

Setting Up the SPI Controller Software

After the ADC data capture board setup is complete, set up the
SPIController software using the following procedure:

1. Open the SPIController software by going to the Start menu

or by double-clicking the SPIController software desktop
icon. If prompted for a configuration file, select the appropriate
one. If not, check the title bar of the window to determine
which configuration is loaded. If necessary, choose Cfg
Open from the File menu and select the appropriate file
based on your part type. Note that the CHIP ID(1) field
should be filled to indicate whether the correct
SPIController configuration file is loaded (see Figure 8).

Figure 8. SPIController, CHIP ID(1) Box

2. Click the New DUT button in the SPIController window

(see Figure 9).

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Figure 9. SPIController, New DUT Button

3. In the ADCBase 0 tab of the SPIController window, find the

CLOCK DIVIDE(B) box (see Figure 10). If using the clock

divider, use the drop-down box to select the correct clock
divide ratio, if necessary. See the appropriate part data sheet;
the AN-878 Application Note, High Speed ADC SPI Control

Software; and the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI, for additional information.

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Rev. 0 | Page 8 of 28

Figure 10. SPIController, CLOCK DIVIDE(B) Box

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Evaluation Board User Guide UG-074

4. Note that other settings can be changed on the ADCBase 0

tab (see Figure 10). See the appropriate part data sheet; the

AN-878 Application Note, High Speed ADC SPI Control

Software; and the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI, for additional information on the

available settings.

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Figure 11. SPIController, Example ADCBase 0 Page

5. Click the Run button in the VisualAnalog toolbar

(see Figure 12).

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Figure 12. Run Button (Encircled in Red) in VisualAnalog Toolbar, Collapsed

Display

Adjusting the Amplitude of the Input Signal

The next step is to adjust the amplitude of the input signal
as follows:

1. Adjust the amplitude of the input signal so that the

fundamental is at the desired level. (Examine the Fund Power
reading in the left panel of the Graph - AD9265 Average FFT
window, see Figure 13.)

Figure 13. Graph Window of VisualAnalog

2. Click the disk icon within the Graph window to save the

performance plot data as a .csv formatted file. See Figure 14
for an example.

0

125MSPS

70.1MHz @ –1dBFS

–20

SNR = 76.5dB (77.5dBFS)
SFDR = 88.0dBc

–40

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–60

SECOND HARMONIC

–80

AMPLITUDE (dBFS)

–100

–120

–140

0 102030405060

Figure 14. Typical FFT, AD9265/AD9255

THIRD HARMONIC

FREQUENCY (MHz)

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