ANALOG DEVICES UG-070 Service Manual

Evaluation Board User Guide

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UG-070

Setting Up the Evaluation Board for the ADCLK854

PACKAGE LIST

Evaluation board with components installed
Applicable documents (schematic and layout)

GENERAL DESCRIPTION

This user guide describes how to set up and use the evaluation
board for the ADCLK854. The ADCLK854 data sheet contains
full technical details about the specifications and operation of this
device and should be consulted when using the evaluation board.

The ADCLK854 is a high performance clock fanout buffer.
The evaluation board is fabricated using a high quality Rogers®
dielectric material. Transmission line paths are kept as close to
100 Ω differentially as possible.

Figure 1. Evaluation Board

Please see the last page for an important warning and disclaimers. Rev. 0 | Page 1 of 8

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UG-070 Evaluation Board User Guide

TABLE OF CONTENTS

Package List ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Recommended Board Setup ............................................................ 3

REVISION HISTORY

12/09—Revision 0: Initial Version

Clock Outputs ................................................................................4

Evaluation Board Schematic and Artwork .....................................5

ESD Caution...................................................................................8

Rev. 0 | Page 2 of 8

Evaluation Board User Guide UG-070

RECOMMENDED BOARD SETUP

The recommended setup for the ADCLK854 evaluation board
is shown in Figure 2. V

is set to 1.8 V. The IN_SEL jumper

S

provides the desired input configuration. Logic 0 on the IN_SEL
pin selects the CLK0 and
IN_SEL pin selects the CLK1 and

On the evaluation board, the CLK0 and
ac-coupled, differential operation to the . This input

CLK0

inputs, and Logic 1 on the

CLK1

inputs.

CLK0

inputs are set up for

ADCLK854
configuration requires the user to provide the appropriate ac
swing to both inputs. Refer to the data sheet and
the schematic (see ) for the input specifications.

Figure 4

ADCLK854

CLK1 is set up to evaluate with a single-ended source via the balun
on the evaluation board. In addition, series capacitors in the
path provide ac-coupled inputs to the ADCLK854.

POWER SUPPLY

1.8V GND

The range of the peak-to-peak input voltage swing at CLK1 is

0.15 V to 1.8 V. Output jitter performance is degraded by input
slew rate, as shown in the ADCLK854 data sheet.

Table 1. Basic Equipment Required

Quantity Description

1 Single power supply
1 Signal source
1 High bandwidth oscilloscope
1 High bandwidth differential probe
2 Matched high speed cables

BOARD

GND

OUTx
OUTx

PROBE

OSCILLOSCOPE

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CLOCK

SOURCE

V

S

CLK1

CLK1

CLK0

CLK0

Figure 2. Recommended Setup for ADCLK854 Evaluation

ADCLK854

EVALUATION

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UG-070 Evaluation Board User Guide

CLOCK OUTPUTS

The ADCLK854 outputs are pin programmable up to 12
differential LVDS outputs or 24 single-ended 1.8 V CMOS
outputs. Jumpers CTRL_A, CTRL_B, CTRL_C, and SLEEP
are used to configure the outputs. See Tab le 2 and Figure 3
for jumper assignments.

For high precision measurements, it is recommended to evaluate the
nonlaunched outputs on the evaluation board. The nonlaunched
outputs do not go to the SMA connectors. In this case, the
ADCLK854 is physically close to the output load and avoids the
issues of driving a 50 Ω cable. Note that CMOS is not designed
to operate in a 50 Ω environment.

The nonlaunched outputs have a full output swing with 100 Ω
differential trace impedance into a 100 Ω resistor to minimize
reflections. These outputs are set up to evaluate using a high
bandwidth differential probe and oscilloscope. See the
evaluation board schematic in Figure 4 for more details.

ADCLK854

V

REF

CLK0
CLK0

CLK1
CLK1

IN_SEL

CTRL_A

VS/2

LVDS/
CMOS

The outputs that go to the SMA connector may not have a full
output swing, and reflections may be observed.

Table 2. Output Pin Assignment

Jumper
Name Jumper Setting Affected Outputs

CTRL_A Logic 0 = LVDS; Logic 1 = CMOS Output 0 to Output 3
CTRL_B Logic 0 = LVDS; Logic 1 = CMOS Output 4 to Output 7
CTRL_C Logic 0 = LVDS; Logic 1 = CMOS Output 8 to Output 11
SLEEP Logic 1 = sleep Output 0 to Output 11

OUT0 (OUT0A)
OUT0 (OUT0B)

OUT1 (OUT1A)
OUT1 (OUT1B)

OUT2 (OUT2A)
OUT2 (OUT2B)

OUT3 (OUT3A)
OUT3 (OUT3B)

LVDS/

CTRL_B

CTRL_C

SLEEP

CMOS

LVDS/
CMOS

OUT4 (OUT4A)
OUT4 (OUT4B)

OUT5 (OUT5A)
OUT5 (OUT5B)

OUT6 (OUT6A)
OUT6 (OUT6B)

OUT7 (OUT7A)
OUT7 (OUT7B)

OUT8 (OUT8A)
OUT8 (OUT8B)

OUT9 (OUT9A)
OUT9 (OUT9B)

OUT10 (O UT10A)
OUT10 (O UT10B)

OUT11 (O UT11A)
OUT11 (O UT11B)

08669-003

Figure 3. 1:12 Clock/Data Buffer Block Diagram

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Evaluation Board User Guide UG-070

EVALUATION BOARD SCHEMATIC AND ARTWORK

0.1UF

C42

0.1UF

C40

0.1UF

C38

0.1UF

GND

VS

C36

1

OUT2BOUT2OUT1B

1

1

OUT1

1

BYPASS CAPACITORS (DUT)

PWRCONN

1

VS

LABEL "VS (1.8V)"

0.1UF

C33

0.1UF

VREF

C29

25.602.2253.0

2

GND

2345

0.1UF

C18

2345

R18

100

0.1UF

GND GND

C13

0.1UF

C11

R3

100

0.1UF

GNDGND

12

C7

43

235245

C31

10UF

0.1UF

GND

VS

GND

C32

BYPASS CAPACITORS (SUPPLY)

OUT5B

0.1UF

100OHM DIFF MATCH

OUT5

CLK1B

567

100OHM DIFF MATCH

2345

OUT5B

ADCLK854

CLK1

100
R15

DNI

49.9

R9

VREF

49.9

R8

DNI

GND

29

28

VS

OUT6

GND

CP 48-6

VS

OUT11B

OUT11

8

9

100OHM DIFF MATCH

C5

C27

OUT7

27330313233343536

OUT6B

IN_SEL

10

1

26

11

OUT7

CTRL_A

1

OUT6

GND7

1

100OHM DIFF MATCH

25

OUT7B

CTRL_B

12

0.1UF

OUT11B

OUT5

2
345

GND

1

1

C25

C26

0.1UF

100
R24

GND4

1

GND

OUT4BOUT4

11

100
R22

100OHM DIFF MATCH

NC

OUT4

OUT4B

11

OUT3BOUT3OUT0

GNDGND

R19

100

1

11

OUT0B

R16

100

1

GND0 GND3

100OHM DIFF MATCH

100OHM DIFF MATCH

100OHM DIFF MATCH100OHM DIFF MATCH

100OHM DIFF MATCH

NC

VS

37

GND

38

OUT3B

39

OUT3

40

OUT2B

41

OUT2

42

VS

43

GND

44

OUT1B

45

OUT1

46

OUT0B

47

OUT0

48

GND

PAD

VREF

CLK0

GND

CLK0B

1

2

4

100
R14

100OHM DIFF MATCH

0.1UF

GND

GND

2345

100
R25

OUT7B

11

100
R23

100
R12

C6

1

GND11

08669-004

OUT6B

2345

GND

GND

1

C28

0.1UF

OUT9OUT10B

2345

0.1UF

GNDGNDGNDGND

11

100OHM DIFF MATCH

11

GND8

OUT8OUT8B

1

VS

24

GND

23

OUT8

22

OUT8B

21

OUT9

20

OUT9B

19

VS

18

GND

17

OUT10

16

OUT10B

15

SLEEP

14

CTRL_C

13

GND

R21

100

100OHM DIFF MATCH

C20

R20

R17

2345

100

OUT9BOUT10

0.1UF

1

C14

23452345

0.1UF

1

C12

100

0.1UF

C9

R2

R1

1.1K

1.1K

GND

VS

VS

VS

GND

2

123

100OHM DIFF MATCH

CTRL_B

CTRL_A

IN_SEL

0.1UF

1

R13

R10

R11

1.1K

1.1K

1.1K

VS

GNDVSGND

GND

2

123

1231313

MOLEX22-28-4033

SLEEP

CTRL_C

OUT11

C4

C3

0.1UF

0.1UF

T1

34

1

SECPRI

0

R7

5

0

5
4
3
2

CLK1B

DNI

MABA-007159-000000

0

GND

1

GND

CLK1

45

23

GND

R5 R4

DNI

GND

C1

1

CLK0B

C2

0.1UF

GND

3
24512345

CLK0

R6

0

DNI

0.1UF

1

GND

Figure 4. ADCLK854 Evaluation Board Schematic

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UG-070 Evaluation Board User Guide

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Figure 5. Top Trace Layer

Figure 6. Ground Plane Layer

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Evaluation Board User Guide UG-070

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Figure 7. V

Power Plane Layer

S

08669-009

Figure 8. Bottom Trace Layer

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UG-070 Evaluation Board User Guide

NOTES

ESD CAUTION

Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express,
implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under
any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the
right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not
authorized to be used in life support devices or systems.

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
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