ANALOG DEVICES UG-051 Service Manual

Evaluation Board User Guide

BPF

ADL5523 ADL5523

ADL5382

GAIN

CONTROL

BPF

LPF

RF

LO

ADF4360

DA

AD9262

LPF

90°

0°

ADC

ADC

DB

122.88MHz

AD9516-0

DDC

DCO

08471-001

UG-051

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: [phone] • Fax: [phone] • www.analog.com

Evaluating the AD9262, 16-Bit, Dual Continuous Time Sigma Delta ADC and

Demonstrating Direct Conversion

EVALUATION BOARD DESCRIPTION

The AD9262 evaluation board serves two purposes: as an
evaluation platform for the 16-bit dual continuous time sigma
delta ADC and as a direct conversion demonstration platform.
Tabl e 1 lists the product features of all the Analog Devices, Inc.,
components in the demonstrator.

The AD9262 is a dual, 16-bit analog-to-digital converter (ADC)
based on a continuous time sigma-delta (Σ-Δ) architecture that
achieves 86 dB of dynamic range over a 10 MHz real or 20 MHz
complex bandwidth. The integrated features and characteristics
unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
This evaluation board supports the AD9262 family of products,
including the AD9262BCPZ-10, AD9262BCPZ-5, and
AD9262BCPZ.

Direct conversion architectures, as shown in Figure 1, use a
single frequency translation step to convert the RF channel
directly to baseband without any intermediate frequency stages.
The frequency translation in this direct conversion demonstrator
is accomplished by the ADL5382, which is a quadrature demod­ul ator. The ADL5382 covers the frequency range between 700
MHz and 2.7 GHz.

The AD9262 has passive inputs, therefore allowing the ADL5382
to directly drive the ADC. The AD9262 does not require a filter
preceding the converter because the continuous time sigma­delta architecture possesses inherent antialiasing capabilities.

Therefore, minimal or no filtering is required between the
demodulator and the ADC. A prototype area for a fourth order
filter is provided in which additional filtering can be tested.

To achieve optimal performance from the AD9262, a low jitter
differential clock is necessary, and the AD9516 family of parts
offers superior clock performance. The AD9516 and a crystal
oscillator footprint are included on the evaluation board. In
addition to providing a clock option to the ADC, outputs from
the AD9516 can be used to drive other external capture devices.

The ADR130B offers the option of using an external 0.5 V band
gap reference voltage for the AD9262. The ADP3339 provides a
quiet and reliable voltage source to each of the ADI components.

In addition to offering system-level evaluation of the direct
conversion architecture, the evaluation board offers the flexibility
of isolating the AD9262 from the surrounding components,
enabling a detailed evaluation of only the AD9262. The ADC
inputs can be disconnected from the ADL5382 and be driven
with an external source. The analog inputs of the AD9262 can
be driven from either a differential transformer or the ADA4937,
which is a very low noise, high linearity differential amplifier.

Complementing the AD9262 evaluation board are additional
hardware and software to capture and process the digital data
from the output of the ADC. The AD9262 can only be
evaluated using the HSC-ADC-E VA LC Z high speed ADC data
capture card in conjunction with the VisualAnalog
capture and analysis software. The SPIController

TM

data

TM

software is

used to read and write to the AD9262.

See the last page for an important warning and disclaimers. Rev. 0 | Page 1 of 24

Figure 1. Direct Conversion Receiver Block Diagram

UG-051 Evaluation Board User Guide

TABLE OF CONTENTS

Evaluation Board Description ......................................................... 1

Revision History ............................................................................... 2

Product Features ............................................................................... 3

Getting Started .................................................................................. 4

Configuring the Evaluation Board ................................................. 5

Power Supply ................................................................................. 5

Clock .............................................................................................. 5

Receiver Input Configuration ..................................................... 5

ADC Only Input Configuration ................................................. 5

Differential Transformer Path .................................................... 6

ADC Driver Path .......................................................................... 6

Supporting Hardware and Software ............................................... 7

REVISION HISTORY

1/10—Revision 0: Initial Version

Software ..........................................................................................7

Hardware ........................................................................................7

AD9262 SPI Controller ................................................................7

AD9516 SPI Controller ................................................................7

AD9516 Register Settings .............................................................8

VisualAnalog Overview ................................................................9

Schematics ....................................................................................... 10 

Layout ............................................................................................... 15

Ordering Information .................................................................... 19

Bill of Materials ........................................................................... 19

ESD Caution................................................................................ 24

Rev. 0 | Page 2 of 24

Evaluation Board User Guide UG-051

PRODUCT FEATURES

Table 1.

AD9262 ADL5382 AD9516-0
SNR: 82.5 dB (84.5 dBFS) to

10 MHz input
SFDR: 87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 675 mW

1.8 V analog supply operation

1.8 V to 3.3 V output supply
Selectable bandwidth

2.5 MHz/5 MHz/10 MHz real

5 MHz/10 MHz/20 MHz complex
Output data rate: 30 MSPS to

160 MSPS
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier

I/Q demodulator
Operating RF frequency: 700 MHz to

2700 MHz
IIP3 + 30 dBm
IIP2 + 60 dBm
Input P1dB + 13dBm
NF 14 dB @ 900 MHz
Voltage conversion gain: 5 dB
Quadrature demodulation accuracy

Phase accuracy <0.5°

Amplitude balance <0.25 dB
LO input: −10 dBm to +5 dBm
Demodulation bandwidth: ~500 MHz
I/Q drive 2 V

into 200 Ω

PEAK

Programmable power consumption

On-chip voltage reference
Offset binary, gray code, or twos

complement data format

Serial control interface (SPI)

ADR130B ADP3339 ADA4937

Initial accuracy

A grade: ±0.70% (maximum)
B grade: ±0.35% (maximum)

Maximum temperature coefficient

A grade: 50 ppm/°C
B grade: 25 ppm/°C

: 50 nF to 10 μF

C

LOAD

Output current: +4 mA/−2 mA
Low operating current: 80 μA

(typical)

Output noise: 6 μV p-p @ 1.0 V

output
Input range: 2.0 V to 18 V
Temperature range: −40°C to

High accuracy over line and load: ±0.9% @

25°C, ±1.5% over temperature

Ultralow dropout voltage: 230 mV (typical)

@ 1.5 A

Requires only C

= 1.0 μF for stability

O

anyCAP® regulators: stable with any type

of capacitor (including MLCC)
Current and thermal limiting
Low noise

2.8. V to 6 V supply range

−40°C to +85°C ambient temperature

range
SOT-223 package

+125°C

Tiny Pb-free TSOT package

Low phase noise, phase-locked loop

On-chip VCO tunes from 2.55 GHz to 2.95 GHz
External VCO/VCXO to 2.4 GHz (optional)
One differential or two single-ended reference

inputs
Reference monitoring capability
Auto and manual reference switchover/holdover

modes
Autorecover from holdover
Accepts references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable

Three pairs of 1.6 GHz LVPECL outputs

Each pair shares one to 32 dividers with coarse

phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs: <10 ps

Two pairs of 800 MHz LVDS clock outputs

Each pair shares two cascaded one-to-32 dividers

with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (ΔT) on each LVDS output

Eight 250 MHz CMOS outputs (two per LVDS output)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs as needed
Serial control port
64-lead LFCSP

Extremely low harmonic distortion

−112 dBc HD2 @ 10 MHz

−79 dBc HD2 @ 70 MHz

−70 dBc HD2 @ 10 MHz

−102 dBc HD3 @ 10 MHz

−91 dBc HD3 @ 70 MHz

−84 dBc HD3 @ 100 MHz

Low input voltage noise: 2.2 nV/√Hz
High speed

−3 dB bandwidth of 1.0 GHz, G = 1
Slew rate: 6000 V/μs, 25% to 75%
dB gain flatness to 200 MHz
Fast overdrive recovery of 1 ns

1 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended–to-

differential operation

Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
Pb-free, 3 mm × 3 mm 16-lead LFCSP

Rev. 0 | Page 3 of 24

UG-051 Evaluation Board User Guide

08471-002

08471-003

USB

PWR: 6V

PWR: 5V

CLOCK

LO

INPUT

RF

INPUT

08471-004

GETTING STARTED

Figure 2. Evaluation Board Front

Figure 3. Evaluation Board Back

The default configuration of the AD9262 evaluation board allows a quick and easy start to evaluating the direct conversion receiver
subsystem. The default configuration interfaces the ADL5382 directly with the AD9262. Tab l e 2 and Figure 4 show the hardware required
to start the evaluation.

Table 2. Quick Start Hardware Requirements

Name Board Value Reference Designator

Power AD9262EBZ +6 V P2

HSC-ADC-EVALCZ +5 V
Clock AD9262EBZ 640 MHz J3
RF Input AD9262EBZ 700 MHz to 2.7 GHz J2
LO Input AD9262EBZ −10 dBm to +5 dBm J1
USB HSC-ADC-EVALCZ

Figure 4. Quick Start Configuration

Rev. 0 | Page 4 of 24

Evaluation Board User Guide UG-051

0Ω

R13

576Ω

R19

0Ω

R11
280Ω

C107

1000pF

C108
560pF

C31
15,000pF

LF

CP

BYPASS_LDO

08471-005

C48

L3

L7

L11

L15

L4

L8 L12

L16

C50

08471-006

CONFIGURING THE EVALUATION BOARD

POWER SUPPLY

Power is provided to the evaluation board by a single +6.0 V
source applied to P2. The power source is regulated down to the
appropriate levels by the ADP3339 voltage regulators. Tab le 3
shows the necessary voltage levels for each component.

Table 3. Component Power Supplies

Component Power Supply

AD9262 1.8 V
ADL5382 5.0 V
AD9516-0 3.3 V

CLOCK

The AD9262 evaluation board offers many clocking options:
a high frequency external clock can be applied directly to the
ADC; the AD9516-0 LVPECL or CMOS clock can be used; and
a low frequency clock, in conjunction with the integrated PLL
from either the AD9516-0 or AD9262, can provide the necessary
input clock frequency. The default clock option is configured
for an external clock rate of 640 MHz.

The AD9262 evaluation board includes the footprint for a Val p ey
Fisher VFAC3 crystal oscillator. The crystal oscillator can serve
as the reference clock to the AD9516-0, and the chip’s internal
PLL can be used to generate a clock closest to the desired fre­quency for the ADC. For example, a 122.88 MHz reference
produces a VCO frequency of 2.580 GHz. The AD9516-0
possesses an integrated VCO. The VCO frequency is further
divided down by 4 to generate an output clock of 645 MHz,
which serves as the input clock to the ADC. To optimize the
AD9516-0 for this particular frequency, the loop filter must be
configured as shown in Figure 5.

Figure 5. AD9516-0 Loop Filter

If the user chooses an alternative crystal oscillator frequency,
the loop filter components must be configured appropriately.
Some common crystal oscillators and the corresponding loop
filter components are shown in Tab l e 4. Refer to the ADIsimCLK
software for design guidance.

To configure the evaluation board for either the external clock
source or the AD9516-0 requires modifying the JP5 and JP6
solder jumpers. The AD9262 sets the common-mode level of
the input clock to 450 mV; therefore, the clock source should be
ac-coupled to the ADC input clock pins. Use the AD9516-0
software to configure the chip to the appropriate divide ratios.

RECEIVER INPUT CONFIGURATION

The default configuration uses the complex output signals of
the I/Q demodulator as the input signals to the AD9262. In this
configuration, the RF input signal should be applied to J2 and
the LO signal to J1. The RF input range of the ADL5382 is
limited to between 700 MHz and 2.7 GHz. The single-ended
RF and LO signals are converted to differential signals using the
RF transformers, T2 and T1. The resulting output signals of the
demodulator are differential I and Q signals that can be directly
applied to the resistive inputs of the AD9262, and no driver
amplifiers are required.

Between the output of the ADL5382 and the input to the
AD9262 are space holders for a fourth order filter (see Figure 6).
This filter may or may not be necessary depending on the
application.

Figure 6. Fourth Order Filter

ADC ONLY INPUT CONFIGURATION

In addition to using the ADL5382 as an input source to the
ADC, the AD9262 can be driven with an external source through
either the ADA4937 or a differential transformer.

To configure the evaluation board for an external source, follow
the hardware configuration shown in Ta b le 5. The SMA
connectors, labeled J5 and J4, correspond to the input signals to
Channel A and Channel B, respectively, of the AD9262.

Additionally, short TP17, TP23, TP2, and TP24 to the appropriate
pads to route the external signals to the input pins of the AD9262
(see Figure 7). This configuration requires careful attention to
ensure that the output signals of the ADL5382 are disconnected
and only the signals from the transformer or ADA4937 are
routed to the ADC.

Table 4. AD9516-0 CLK Configuration

Crystal
(MHz)

134.4 1000 pF 232 Ω 18,000 pF 486 Ω 680 pF

122.88 1000 pF 280 Ω 15,000 pF 576 Ω 560 pF

39.3216 1500 pF 221 Ω 22,000 pF 453 Ω 680 pF

C107 R11 C31 R13 C108

Loop Filter

AD9262
CLK

MHz

672

MHz

645.12

MHz

648.8

Rev. 0 | Page 5 of 24

UG-051 Evaluation Board User Guide

4 L

L L

L 1

4 6

R37

3

C43

C42

R38 R37

R33

R40

R34

R35

R36

R41

R42

R39

TP24

TP2

TP23

TP17

AD9262

REMOVE R39 T O R42.
SHORT TP 24, TP2,

TP23, AND TP 17 TO
THE CLOSEST PAD.

08471-007

Table 5. External ADC Input Configuration

Connector Setting Notes

J4, J5 J4: Channel B

J5: Channel A

R33 to 42 DNP

Disconnect ADL5382
outputs from the AD9262

TP17

Short to the closest

Connect A+ path

pad on R40

TP23

Short to the closest

Connect A− path

pad on R39

TP2

Short to the closest

Connect B+ path

pad on R42

TP24

Short to the closest

Connect B− path

pad on R41

DIFFERENTIAL TRANSFORMER PATH

To activate the differential transformer path, configure the
jumpers as shown in Tabl e 6.

Table 6. Differential Transformer Configuration

Jumper Setting Notes

JP1, JP2

JP3 to JP6

Short Position 1
and Position2

Short Position 2
and Position 3

Configure SMA connectors for
transformer inputs

Configure differential trans­former outputs to ADC inputs

ADC DRIVER PATH

Set the jumpers as shown in Table 7.

Table 7. ADA4937 Configuration

Jumper Setting Notes

JP1, JP2

JP3 to JP6

Short Position 2
and Position 3

Short Position 1
and Position 2

Configure SMA connectors for
ADA4937 inputs

Configure outputs from the
ADA4937 to ADC inputs

Figure 7. External ADC Jumper Settings

Rev. 0 | Page 6 of 24

Evaluation Board User Guide UG-051

08471-017

08471-018

SUPPORTING HARDWARE AND SOFTWARE

The AD9262 can only be evaluated using the HSC-ADC­EVALCZ high speed ADC data capture card in conjunction
with the VisualAnalog data capture and analysis software.
The SPIController software is used to configure the AD9262
and the AD9516 to the appropriate register settings.

SOFTWARE

Manuals for VisualAnalog, the SPIController software, and
the HSC-ADC-EVALCZ data capture hardware are included
on the CD in the evaluation board package. It is recommended
that the software be installed before connecting the hardware.
VisualAnalog relies on the Microsoft .NET framework version 2,
which is also included on the package CD. The .NET frame­work should be installed before installing VisualAnalog. The
SPIController software should also be installed.

HARDWARE

The AD9262 evaluation board and the HSC-ADC-EVA LC Z
data capture card are powered from a wall-connected switching
power supply. The switching power supplies have different
output voltages. Connect the 6 V power supply to the AD9262
evaluation board and the 5 V power supply to the HSC-ADC­EVALCZ data capture board. With the HSC-ADC-EVA L CZ
data capture board powered on and the VisualAnalog software
installed, connect the USB cable to the PC and follow all the
Found new hardware prompts, using the default driver each time.

AD9516 SPI CONTROLLER

Open another instance of the SPIController for control of the
AD9516. If a box titled Read Test Failure appears, click Ignore
to open the SPIController. This error occurs because the
software has not been configured correctly to read from the
chip. Use the following procedure to appropriately configure the
SPIController to read and write to the AD9516:

1. From the File menu, select CfgOpen; then select

AD9516spiengR03.cfg.

2. When a Calibration File Error! message appears as shown

in Figure 9, click OK.

Figure 8. AD9262 SPIController

AD9262 SPI CONTROLLER

Upon successful software installation and hardware setup, start
the AD9262 SPIController software. By default, the software
recognizes the AD9262 evaluation board and loads the correct
SPIController profile. If it does not, point the software to the
following file: AD9262_16Bit_10MSspiR03.cfg.

The AD9262 SPIController has four tabs. When correctly
configured, a message appears on the CHIP ID subpane
reporting that the AD9262 is interfaced (see Figure 8).

Figure 9.

3. Select Config and then Controller Dialog and make sure

that FIFO Chip Sel is set to 2 and that USB Chan # is set
to the same value as the AD9262 SPIController Cfg dialog
(see Figure 10).

Rev. 0 | Page 7 of 24

UG-051 Evaluation Board User Guide

08471-019

08471-020

2

1

08471-021

3

4

5

6

9

7

8

08471-022

Figure 11. AD9516 Configuration

The AD9516 register settings depend on the particular clock
option chosen. Ta b l e 8 provides a list of register settings for
some common crystal oscillators. The configuration shown in
Figure 12 and Figure 13 is for the 122.88 MHz crystal oscillator.

Figure 12. VCO and Clock Configuration for the 122.88 MHz Crystal Oscillator

Figure 10.

AD9516 REGISTER SETTINGS

Figure 13. PLL Configuration for the 122.88 MHz Crystal Oscillator

The SPIController uses a 4-wire interface; therefore, the
AD9516 must be configured for this interface before any further
writes can take effect. To configure the AD9516, check the SDO
Enable bit, as shown in Figure 11.

Rev. 0 | Page 8 of 24