ANALOG DEVICES SSM3302 Service Manual
Stereo Audio Amplifier
SSM3302
Rev. 0
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Data Sheet
FEATURES
Filterless stereo Class-D amplifier with Σ-Δ modulation
2 × 10 W into 4 Ω load and 2 × 8 W into 8 Ω load at 12 V supply
with <1% total harmonic distortion plus noise (THD + N)
91% efficiency at 12 V, 8 W into 8 Ω speaker
98 dB signal-to-noise ratio (SNR)
Single-supply operation from 7 V to 18 V
Flexible gain adjustment pin from 9 dB to 24 dB
Fixed input impedance of 40 kΩ
Mono output mode pin for 1 × 20 W output power into 2 Ω
10 µA shutdown current
Short-circuit and thermal protection
Available in a 40-lead, 6 mm × 6 mm LFCSP
Pop-and-click suppression
User-selectable ultralow EMI emissions mode
Thermal warning indicator
Power-on reset
APPLICATIONS
Mobile computing
Flat panel televisions
Media docking stations
Portable electronics
Sound bars
GENERAL DESCRIPTION
The SSM3302 is a fully integrated, high efficiency, stereo Class-D
audio amplifier. The application circuit requires minimal external
components and operates from a single 7 V to 18 V supply. The
device is capable of delivering 2 × 10 W of continuous output
power into a 4 Ω load (or 2 × 8 W into 8 Ω) with <1% THD + N
from a 12 V supply. In addition, while mono mode is activated,
the user can drive a load as small as 2 Ω up to 20 W continuous
output power by stacking the stereo output terminals.
The SSM3302 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. This scheme
continues to provide high efficiency even at low output power.
The SSM3302 operates with 90% efficiency at 7 W into an 8 Ω
2 ×10 W Filterless Class-D
load or with 82% efficiency at 10 W into 4 Ω from a 12 V supply,
and it has an SNR of >98 dB.
Spread spectrum pulse density modulation (PDM) is used to
provide lower EMI radiated emissions compared with other
Class-D architectures. The SSM3302 includes an optional
modulation select pin (ultralow EMI emission mode) that
significantly reduces the radiated emissions at the Class-D
outputs, particularly above 100 MHz. The SSM3302 can pass
FCC Class-B emissions testing with an unshielded 20 inch cable
using common-mode choke-based filtering.
The fully differential input of the S
rejection of common-mode noise on the input. The device also
includes a highly flexible gain select pin that only requires one
series resistor to choose a gain between 9 dB and 24 dB, with no
change to the input impedance. The benefit of this is to improve
gain matching between multiple SSM3302 devices within a single
application compared with using external resistors to set gain.
The SSM3302 includes an integrated voltage regulator that
generates a 5 V rail.
The SSM3302 has a micropower shutdown mode with a typical
shutdown current of 10 µA. Shutdown is enabled by applying a
logic low to the
suppression circuitry that minimizes voltage glitches at the output
during turn on and turn off, reducing audible noise during
activation and deactivation.
Other included features to simplify system level integration of
the SSM3302 are input low-pass filtering to suppress out-ofband DAC noise interference to the pulse density modulator,
fixed input impedance to simplify component selection across
multiple platform production builds, and a thermal warning
indicator pin.
The SSM3302 is specified over the commercial temperature
range (−40°C to +85°C). It has built-in thermal shutdown and
output short-circuit protection. It is available in a halide-free,
40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP).
SD
pin. The device also includes pop-and-click
SM3302 provides excellent
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of thi rd parties that may result from its use. Specifications subject to change with out notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
SSM3302 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Typical Application Circuits.......................................................... 14
Applications Information .............................................................. 16
Overview...................................................................................... 16
Analog Supply............................................................................. 16
Gain Selection............................................................................. 16
Amplifier Protection.................................................................. 16
Pop-and-Click Suppression ...................................................... 16
EMI Noise.................................................................................... 16
Mono Mode................................................................................. 16
Output Modulation Description .............................................. 17
Layout .......................................................................................... 17
Input Capacitor Selection.......................................................... 17
Bootstrap Capacitors.................................................................. 17
Power Supply Decoupling......................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
2/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet SSM3302
FUNCTIONAL BLOCK DIAGRAM
SSM3302
INR+
INR–
SDNR
MONO
SDNL
INL+
INL–
40kΩ
40kΩ
40kΩ
40kΩ
GAIN
PVDD
GAIN
CONTROL
GAIN
CONTROL
VREG
(AVDD) REGENAGND
MODULATOR
BIAS
BIAS
MODULATOR
(Σ-∆)
INTERNAL
OSCILLATOR
(Σ-∆)
VREG
FET
DRIVER
CONTROL
FET
DRIVER
EDGE
OUTR+
OUTR–
OUTL+
OUTL–
PGND
THERM
BOOTR+
BOOTR–
EDGE
BOOTL+
BOOTL–
10198-001
Figure 1.
Rev. 0 | Page 3 of 20
SSM3302 Data Sheet
SPECIFICATIONS
PVDD = 12 V, TA = 25oC, RL = 8 Ω + 64 H, EDGE = AGND, gain = 9 dB, VREG = off, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power/Channel P
O
R
R
R
R
R
R
R
R
R
R
R
Efficiency η PO = 7 W, 8 Ω, PVDD = 12 V, EDGE = low (normal operation) 91.5 %
Tot al H armoni c
THD + N P
Distortion + Noise
1.0 AVDD − 1 V
Input Common-Mode
V
CM
Voltage Range
Common-Mode
CMRR
Rejection Ratio
Channel Separation X
Average Switching
TAL K
300 kHz
f
SW
Frequency
Differential Output
V
OOS
Offset Voltage
POWER SUPPLY
Supply Voltage Range PVDD
Power Supply Rejection
PSRR
Ratio
PSRR
Supply Current (Stereo) I
SYPVDD
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 15 V 121 W
= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 8 W
L
= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 2.7 W
L
= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 15 V 151 W
L
= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 10 W
L
= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 3.2 W
L
= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 15 V 201 W
L
= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 131 W
L
= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 4.8 W
L
= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 15 V 241 W
L
= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 161 W
L
= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 5.7 W
L
= 2 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
R
L
29
2
W
(mono mode)
2
= 2 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
R
L
9.4
W
(mono mode)
= 2 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V
R
L
36.6
2
W
(mono mode)
2
= 2 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V
R
L
12.7
W
(mono mode)
= 7 W, 8 Ω, PVDD = 12 V, EDGE = AVDD (ultralow
P
O
82 %
EMI mode)
= 5 W into 8 Ω, f = 1 kHz, PVDD = 12 V 0.01 %
O
VCM = 2.5 V ± 100 mV at 1 kHz, output referred 43 dB
PO = 0.5 W, f = 1 kHz 80 dB
Gain = 9 dB 3.0 mV
Guaranteed from PSRR test 7 18 V
PVDD = 7 V to 15 V, dc input floating 70 dB
DC
V
AC
= 100 mV at 1 kHz, inputs are ac grounded, CIN = 0.1 μF 80 dB
RIPPLE
VIN = 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, V
(internal V
= 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, V
V
IN
(internal V
= 0 V, load = 8 Ω + 68 μH, PVDD = 12 V, V
V
IN
(internal V
= 0 V, load = 8 Ω + 68 μH, PVDD = 7 V, V
V
IN
(internal V
active)
REG
disabled)
REG
disabled)
REG
disabled)
REG
REGEN
REGEN
REGEN
REGEN
= AVDD
= AGND
= AGND
= AGND
12.2 mA
6.2 mA
5 mA
3 mA
Rev. 0 | Page 4 of 20
Data Sheet SSM3302
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
I
Shutdown Current ISD
ANALOG SUPPLY
External Supply Voltage AVDD Permissible range for external AVDD, V
On-Board Regulator V
Regulator Current I
Regulator Power Supply
Rejection
GAIN CONTROL
Closed-Loop Voltage Gain AV See Table 5 for gain options 9 24 dB
Input Impedance Z
SHUTDOWN CONTROL
Input Voltage High V
Input Voltage Low V
Turn-On Time t
Turn-Off Time t
Output Impedance Z
AMPLIFIER PROTECTION
Overcurrent Threshold IOC 6 A
Overtemperature
Warning
Overtemperature
Shutdown
Recovery Temperature T
NOISE PERFORMANCE
Output Voltage Noise en
Signal-to-Noise Ratio SNR PO = 10 W, RL = 8 Ω 98 dB
1
Although the SSM3302 has good audio quality above 2 × 10 W into 4 Ω, continuous output power beyond 2 × 10 W into 4 Ω must be avoided due to device packaging
limitations.
2
Mono mode. Output power beyond 20 W needs special care for thermally considered printed circuit board (PCB) design.
SYAVDD
5 V
VREG
20 mA
VREG
PSRR
VREG
IN
IH
IL
WU
SD
OUT
120 °C
T
WARN
145 °C
T
SD
85 °C
REC
= 0 V, load = 8 Ω + 68 μH, PVDD = 15 V, V
V
IN
(internal V
= 0 V, load = 8 Ω + 68 μH, PVDD = 12 V, V
V
IN
(internal V
= 0 V, load = 8 Ω + 68 μH, PVDD = 7 V, V
V
IN
(internal V
= AGND
SD
disabled)
REG
disabled)
REG
disabled)
REG
REGEN
= AGND
REGEN
= AGND
REGEN
= AGND
REGEN
= AGND 4.5 5.5 V
70 dB
40 kΩ
1.35 V
0.35 V
SD rising edge from AGND to AVDD
SD falling edge from AVDD to AGND
= GND
SD
PVDD = 12 V, f = 20 Hz to 20 kHz, inputs are ac grounded,
5.85 mA
5.8 mA
5.6 mA
10 μA
40 ms
500 μs
56 kΩ
100 μV rms
gain = 9 dB, A-weighted
Rev. 0 | Page 5 of 20
SSM3302 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Power Supply Voltage (PVDD) −0.3 V to +25 V
Analog Supply Voltage (AVDD) −0.3 V to +6 V
Input Voltage −0.3 V to +6 V
ESD Susceptibility 4 kV
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA (junction to air) is specified for the worst-case conditions,
that is, a device soldered in a circuit board for surface-mount
packages. θ
a 4-layer printed circuit board (PCB) with natural convection
cooling.
Table 3. Thermal Resistance
Package Type θJA θJC Unit
40-Lead, 6 mm × 6 mm LFCSP 31 2.5 °C/W
and θJC are determined according to JESD51-9 on
JA
ESD CAUTION
Rev. 0 | Page 6 of 20
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