ANALOG DEVICES SSM2804 Service Manual

Audio Subsystem with Class-D Speaker

FEATURES

3 single-ended stereo audio inputs with optional

differential mode Stereo, 1.4 W, filterless Class-D amplifiers with Σ-Δ modulation Integrated receiver path bypass switch Configurable, high performance capless headphone output

with true ground Class-G technology Optional hardware-based headphone level limiter

2

I

C control interface

Volume control

Flexible input/output mixing

Output mode control

EMI emissions control

Automatic level control (ALC)

Adjustable headphone level limiter Low shutdown current Short-circuit and thermal protection Pop-and-click suppression Available in a 30-ball, 2.5 mm × 3.0 mm WLCSP

APPLICATIONS

Mobile phones Portable multimedia devices

GENERAL DESCRIPTION

The SSM2804 is an audio subsystem designed specifically for mobile phones and portable multimedia devices. This highly flexible subsystem includes three input channels that can be configured as single-ended stereo or monaural differential for multimedia audio sources.

and Capless Headphone Driver

SSM2804

Each set of inputs is independently adjustable with the 2-wire

2

I

C interface and features an adjustable gain over a 30 dB range in steps of 1 dB. Each set of input channels also offers the choice of variable input impedance PGA mode or fixed input impedance boost mode. The input signals are then mixed and routed to the desired set of outputs. This configuration is set using the 2-wire

2

I

C control interface.

The SSM2804 includes three selectable output modes.

The first output mode is a stereo Class-D speaker driver capable of delivering 2 × 1.4 W of continuous power to an 8 Ω bridge-tied load (BTL) with 1% THD + N when using a 5 V supply. This Class-D amplifier incorporates three-level Σ-Δ output modulation designed to increase battery life and improve EMI performance. The Class-D amplifier offers an I with a gain range from +12 dB to −63 dB in 31 steps.

The second output mode is a pair of high performance headphone drivers capable of delivering 20 mW per channel into stereo 32 Ω single-ended loads with 1% THD + N. The stereo headphone drivers use a highly efficient, true ground centered Class-G architecture. The headphone outputs incorporate

2

I

C-adjustable volume control with a gain range from 0 dB to −75 dB in 32 steps.

The third output mode is an integrated receiver path bypass switch for passing voice signals from the audio baseband.

The SSM2804 is specified over the industrial temperature range of −40°C to +85°C. It has built-in thermal shutdown and output short-circuit protection. The SSM2804 is available in a 30-ball,

2.5 mm × 3.0 mm wafer level chip scale package (WLCSP).

2

C-adjustable volume control

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SSM2804

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

SSM2804

A

V

FUNCTIONAL BLOCK DIAGRAM

DD

PVDD

RCV+

RCV–

INA2

INA1

INB2

INB1

INC2

INC1

SD

SSM2804

BOOST = 0dB TO +20dB PGA = –12dB TO +18dB

BIAS

MIX/MUX

+12dB TO –63d B 31 STEPS

0dB TO –75dB 32 STEPS

I2C

CLASS-D

CLASS-G

SUPPLY

EP+

EP–

LSPK+

LSPK–

RSPK+

RSPK–

HPL

HPR

CF1

CF2

CPVDD

BIAS AGND

PGND SCL SDA CPVSS

09960-001

Figure 1.

Rev. 0 | Page 3 of 36

SSM2804

SPECIFICATIONS

TA = 25°C, AVDD = 3.3 V, PVDD = 3.6 V, gain = 0 dB, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Analog Voltage Supply (AVDD) 2.5 3.3 3.6 V Speaker Voltage Supply (PVDD) 2.7 3.6 5.5 V Total Quiescent Current (IDD) 3.5 mA HP mode only

6.0 mA Stereo Class-D mode only

9.8 mA HP and Class-D modes 400 µA Receiver path mode Power-Down Current (ISD) 1 µA

INPUT CHARACTERISTICS

Turn-On Time 10 ms PGA Mode Operation

Input Impedance 38 54 kΩ Minimum gain setting

4.5 6.5 kΩ Maximum gain setting Gain Range −12 +18 dB INAx, INBx, INCx inputs, 31 steps

Boost Mode Operation

Input Impedance 20 kΩ Gain Range 0 20 dB INAx, INBx, INCx inputs, 3 steps

CLASS-D AMPLIFIER

Output Offset Voltage (VOS) 2.3 mV Output muted

12 mV Output unmuted

Output Power (P

) f = 1 kHz, mono operation

OUT

310 mW PVDD = 2.7 V, RL = 8 Ω + 33 µH, THD + N = 1%

700 mW PVDD = 3.6 V, RL = 8 Ω + 33 µH, THD + N = 1%

1.0 W PVDD = 4.2 V, RL = 8 Ω + 33 µH, THD + N = 1%

1.4 W PVDD = 5.0 V, RL = 8 Ω + 33 µH, THD + N = 1%

700 mW PVDD = 2.7 V, RL = 4 Ω + 15 µH, THD + N = 1%

1.5 W PVDD = 3.6 V, RL = 4 Ω + 15 µH, THD + N = 1%

2.0 W PVDD = 4.2 V, RL = 4 Ω + 15 µH, THD + N = 1%

2.9 W PVDD = 5.0 V, RL = 4 Ω + 15 µH, THD + N = 1%

400 mW PVDD = 2.7 V, RL = 8 Ω + 33 µH, THD + N = 10% 860 mW PVDD = 3.6 V, RL = 8 Ω + 33 µH, THD + N = 10%

1.2 W PVDD = 4.2 V, RL = 8 Ω + 33 µH, THD + N = 10%

1.7 W PVDD = 5.0 V, RL = 8 Ω + 33 µH, THD + N = 10%

900 mW PVDD = 2.7 V, RL = 4 Ω + 15 µH, THD + N = 10%

1.8 W PVDD = 3.6 V, RL = 4 Ω + 15 µH, THD + N = 10%

2.5 W PVDD = 4.2 V, RL = 4 Ω + 15 µH, THD + N = 10%

3.6 W PVDD = 5.0 V, RL = 4 Ω + 15 µH, THD + N = 10%

Total Harmonic Distortion Plus Noise

0.01 % R

(THD + N) Output Noise (Vn) 40 µV 20 Hz to 20 kHz, A-weighted Signal-to-Noise Ratio (SNR) 94 dB 2.0 V rms output, A-weighted, PVDD = 5 V Power Supply Rejection Ratio (PSRR) 80 dB 217 Hz, 200 mV p-p ripple 80 dB 1 kHz, 200 mV p-p ripple Common-Mode Rejection Ratio (CMRR) 55 dB Differential input mode, 1 kHz, 10 mV rms Efficiency 89 % P Minimum Load Resistance (R

) 4 Ω

LOAD

Average Switching Frequency (fSW) 400 kHz Volume Control Gain Range −63 +12 dB

pin low

SD

rising edge from AGND to AVDD

SD

= 8 Ω + 33 µH, P

L

= 700 mW

OUT

= 250 mW

OUT

Rev. 0 | Page 4 of 36

SSM2804

Parameter Min Typ Max Unit Test Conditions/Comments

HEADPHONE OUTPUT

Output Offset Voltage (VOS) 2 mV Headphone only

8 mV INAx, INBx, INCx inputs

Output Power (P

40 mW

Total Harmonic Distortion Plus Noise

(THD + N)

0.02 % RL = 16 Ω, P Output Noise (Vn) 16 µV 20 Hz to 20 kHz, A-weighted Signal-to-Noise Ratio (SNR) 96 dB 800 mV rms output, A-weighted Power Supply Rejection Ratio (PSRR) 95 dB 217 Hz, 200 mV p-p ripple

Crosstalk 90 dB 1 kHz, P Minimum Load Resistance (R Maximum Capacitive Load (C Gain Range −75 0 dB ESD Protection ±8 kV

RECEIVER PATH (BYPASS SWITCH)

Path Impedance (RON), Receiver Inputs

to Speaker Outputs

Signal Path THD + N 0.1 %

Output Noise 10 µV 20 Hz to 20 kHz, A-weighted Off Channel Isolation 90 dB 217 Hz, 200 mV p-p ripple Input Common Mode PVDD/2 V

) 20 mW RL = 32 Ω, THD + N = 1%

OUT

= 16 Ω, THD + N = 1%, 1 µF charge pump

R

L

capacitor

0.012 % R

= 32 Ω, P

L

= 15 mW

OUT

= 10 mW

OUT

85 dB 1 kHz, 200 mV p-p ripple

= 12 mW

OUT

) 16 Ω

LOAD

) 500 pF

LOAD

1.5 Ω RCV+ to EP+ and RCV− to EP−

= 70 mW, RL = 32 Ω or P

P

OUT

= 8 Ω

R

L

= 17.5 mW,

OUT

Table 2. Digital Logic Levels (CMOS Levels)

Parameter Min Typ Max Unit

Input Low Level (VIL) 0.35 V Input High Level (VIH) 1.35 V Output Low Level (VOL) 0.1 × AVDD V Output High Level (VOH) 0.9 × AVDD V

Rev. 0 | Page 5 of 36

SSM2804

I2C TIMING CHARACTERISTICS

Table 3.

Limit

Parameter

t

600 ns Start condition setup time

SCS

t

600 ns Start condition hold time

SCH

t

MIN

MAX

tPH 600 ns SCL pulse width high tPL 1.3 s SCL pulse width low f

0 526 kHz SCL frequency

SCL

tDS 100 ns Data setup time tDH 900 ns Data hold time tRT 300 ns SDA and SCL rise time tFT 300 ns SDA and SCL fall time t

600 ns Stop condition setup time

HCS

Timing Diagram

SDA

SCL

Unit Description t

t

SCH

t

DS

t

PL

t

RT

Figure 2. I

t

DH

2

C Timing

PH

t

HCS

t

SCS

FT

09960-002

Rev. 0 | Page 6 of 36

SSM2804

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

Analog Supply Voltage (AVDD) −0.3 V to +3.6 V Speaker Supply Voltage (PVDD) −0.3 V to +3.6 V Input Voltage VDD SD, SCL, SDA, RCV+, RCV− INA1, INA2, INB1, INB2, INC1, INC2 −0.3 V to AVDD + 0.3 V ESD (HBM) on Headphone Output 8 kV Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C Junction Temperature Range −65°C to +165°C Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

−0.3 V to +6.0 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type PCB θJA θJB Unit

30-Ball, 2.5 mm × 3.0 mm WLCSP 1S0P 162 39 °C/W 2S0P 76 21 °C/W

ESD CAUTION

Rev. 0 | Page 7 of 36

SSM2804

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1 CORNER

1

A

LSPK+

B

LSPK– PGND RSPK– EP– RCV– INA2

234

RSPK+ EP+ RCV+ INA1

PVDD

56

C

D

E

CPVSS SCL SDA INB2 INB1

CF2

AGND CPVDD HPR SD INC2 INC1

CF1 AVDD HPL AGND AVDD BIAS

TOP VIEW

(BALL SIDE DO WN)

Not to Scal e

09960-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

A1 LSPK+ Class-D Loudspeaker Output Left + B1 LSPK− Class-D Loudspeaker Output Left − C1 CF2 Charge Pump Flyback Capacitor, Terminal 2 D1 AGND Analog Ground E1 CF1 Charge Pump Flyback Capacitor, Terminal 1 A2 PVDD Speaker Power Supply B2 PGND Speaker Ground C2 CPVSS Charge Pump Negative Supply for Class-G D2 CPVDD Charge Pump Positive Supply for Class-G E2 AVDD Analog Power Supply A3 RSPK+ Class-D Loudspeaker Output Right + B3 RSPK− Class-D Loudspeaker Output Right − C3 SCL 2-Wire I2C Control Interface Clock Input D3 HPR Class-G Headphone Output, Right Channel E3 HPL Class-G Headphone Output, Left Channel A4 EP+ Integrated Switch Output + B4 EP− Integrated Switch Output − C4 SDA 2-Wire I2C Control Interface Data Input/Output D4

SD

Shutdown Control, Active Low (Optional Limiter Threshold Voltage)

E4 AGND Analog Ground A5 RCV+ Baseband Receiver (Voice) Input + B5 RCV− Baseband Receiver (Voice) Input − C5 INB2 Configurable Input B2 (Single-Ended Input B− or Stereo Input B, Left Channel) D5 INC2 Configurable Input C2 (Single-Ended Input C− or Stereo Input C, Left Channel) E5 AVDD Analog Power Supply A6 INA1 Configurable Input A1 (Single-Ended Input A+ or Stereo Input A, Right Channel) B6 INA2 Configurable Input A2 (Single-Ended Input A− or Stereo Input A, Left Channel) C6 INB1 Configurable Input B1 (Single-Ended Input B+ or Stereo Input B, Right Channel) D6 INC1 Configurable Input C1 (Single-Ended Input C+ or Stereo Input C, Right Channel) E6 BIAS Device Bias Pin

Rev. 0 | Page 8 of 36

SSM2804

TYPICAL PERFORMANCE CHARACTERISTICS

100

RL = 8Ω + 33µH

10

PVDD = 3.6V

1

100

10

1

RL = 4Ω + 15µH

PVDD = 3.6V

PVDD = 2.7V

0.1

THD + N (%)

0.01

0.001

0.0001 10

0.001 0.01 0.1 1

PVDD = 2.7V

PVDD = 4.2V

PVDD = 5V

OUTPUT POWER (W)

Figure 4. THD + N vs. Output Power into 8 Ω, Class-D Amplifier,

Mono Operation

100

RL = 8Ω + 33µH

10

PVDD = 3.6V

1

0.1

THD + N (%)

0.01

0.001

0.0001 10

0.001 0.01 0.1 1

PVDD = 2.7V

PVDD = 4.2V

PVDD = 5V

OUTPUT POWER (W)

Figure 5. THD + N vs. Output Power into 8 Ω, Class-D Amplifier,

Stereo Operation

0.1

THD + N (%)

0.01

0.001

0.0001 10

09960-004

0.001 0.01 0.1 1

PVDD = 4.2V

OUTPUT POWER (W)

PVDD = 5V

09960-005

Figure 7. THD + N vs. Output Power into 4 Ω, Class-D Amplifier,

Mono Operation

100

RL = 4Ω + 15µH

10

PVDD = 3.6V

1

0.1

THD + N (%)

0.01

0.001

0.0001 10

09960-006

0.001 0.01 0.1 1

PVDD = 2.7V

OUTPUT POWER (W)

PVDD = 4.2V

PVDD = 5V

09960-007

Figure 8. THD + N vs. Output Power into 4 Ω, Class-D Amplifier,

Stereo Operation

100

PVDD = 2.7V R

= 8Ω + 33µH

L

10

1

0.1

THD + N (%)

0.01

0.001 10 100k

300mW

125mW

62.5mW

100 1k 10k

FREQUENCY (Hz)

Figure 6. THD + N vs. Frequency, Class-D Amplifier, Mono Operation,

= 8 Ω, PVDD = 2.7 V

R

L

09960-008

Rev. 0 | Page 9 of 36

100

PVDD = 2.7V R

= 4Ω + 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001 10 100k

500mW

62.5mW

100 1k 10k

250mW

125mW

FREQUENCY (Hz)

Figure 9. THD + N vs. Frequency, Class-D Amplifier, Mono Operation,

RL = 4 Ω, PVDD = 2.7 V

09960-009

SSM2804

100

10

PVDD = 3.6V R

= 8Ω + 33µH

L

100

10

PVDD = 3.6V R

=4Ω + 15µH

L

1

0.1

THD + N (%)

0.01

0.001 10 100k

600mW

500mW

250mW

100 1k 10k

FREQUENCY (Hz)

125mW

Figure 10. THD + N vs. Frequency, Class-D Amplifier, Mono Operation,

= 8 Ω, PVDD = 3.6 V

R

L

100

PVDD = 4.2V R

=8Ω + 33µH

L

10

1

0.1

THD + N (%)

0.01

900mW

250mW

125mW

1

0.1

THD + N (%)

0.01

0.001 10 100k

09960-010

1.1W

125mW

100 1k 10k

250mW

500mW

FREQUENCY (Hz)

09960-011

Figure 13. THD + N vs. Frequency, Class-D Amplifier, Mono Operation,

= 4 Ω, PVDD = 3.6 V

R

L

100

PVDD = 4.2V R

=4Ω + 15µH

L

10

250mW

1.5W

1W

1

0.1

THD + N (%)

0.01

0.001 10 100k

100 1k 10k

FREQUENCY (Hz)

500mW

Figure 11. THD + N vs. Frequency, Class-D Amplifier, Mono Operation,

= 8 Ω, PVDD = 4.2 V

R

L

100

PVDD = 5V R

= 8Ω + 33µH

L

10

1

0.1

THD + N (%)

0.01

0.001 10 100k

1.2W

250mW

100 1k 10k

FREQUENCY (Hz)

1W

500mW

Figure 12. THD + N vs. Frequency, Class-D Amplifier, Mono Operation,

= 8 Ω, PVDD = 5.0 V

R

L

0.001 10 100k

09960-012

100 1k 10k

FREQUENCY (Hz)

500mW

09960-013

Figure 14. THD + N vs. Frequency, Class-D Amplifier, Mono Operation,

= 4 Ω, PVDD = 4.2 V

R

L

100

PVDD = 5V R

= 4Ω + 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001 10 100k

09960-014

2.2W

250mW

100 1k 10k

FREQUENCY (Hz)

1.5W

500mW

09960-015

Figure 15. THD + N vs. Frequency, Class-D Amplifier, Mono Operation,

= 4 Ω, PVDD = 5.0 V

R

L

Rev. 0 | Page 10 of 36

SSM2804

2.0

f = 1kHz

1.8 R

= 8Ω + 33µH

1.6

1.4

1.2

1.0

0.8

0.6

OUTPUT POWER (W)

0.4

0.2

L

THD + N = 1%

THD + N = 10%

0

2.5 3.0 3.5 4.0 4.5 5.0

SUPPLY VOLTAGE (V)

THD + N = 0.1%

Figure 16. Output Power vs. Supply Voltage, Class-D Amplifier, RL = 8 Ω

09960-016

3.5

f = 1kHz

3.0

R

= 4Ω + 15µH

L

2.5

2.0

1.5

OUTPUT POWER (W)

1.0

0.5

THD + N = 10%

0

2.5 3.0 3.5 4.0 4.5 5.0

THD + N = 1%

THD + N = 0.1%

SUPPLY VOLTAGE (V)

Figure 19. Output Power vs. Supply Voltage, Class-D Amplifier, RL = 4 Ω

09960-017

400

RL = 8Ω + 33µH

350

300

250

200

150

SUPPLY CURRENT (mA)

100

PVDD = 2.7V

50

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

02

PVDD = 3.6V

OUTPUT PO WER (W)

PVDD = 4.2V

PVDD = 5V

.0

09960-018

Figure 17. Supply Current vs. Output Power into 8 Ω, Class-D Amplifier

100

PVDD = 2.7V

90

80

70

60

PVDD = 3.6V

50

40

EFFICIENCY (%)

30

20

10

0

0 0.2 0.4 0. 6 0.8 1.0 1.2 1.4 1.6 1.8

PVDD = 5V

PVDD = 4.2V

OUTPUT PO WER (W)

RL = 8Ω + 33µH

09960-020

Figure 18. Efficiency vs. Output Power into 8 Ω, Class-D Amplifier

800

RL = 4Ω + 15µH

700

600

500

400

300

PVDD = 2.7V

SUPPLY CURRENT (mA)

200

100

0

03

Figure 20. Supply Current vs. Output Power into 4 Ω, Class-D Amplifier

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 0.2 0. 4 0. 6 0.8 1.0 1. 2 1. 4 1.6 1.8 2. 0 2. 2 2.4 2.6 2.8 3.0

Figure 21. Efficiency vs. Output Power into 4 Ω, Class-D Amplifier

PVDD = 4.2V

PVDD = 3.6V

0.5 1.0 1.5 2.0 2.5 3.0

OUTPUT PO WER (W)

PVDD = 2.7V PVDD = 3.6V PVDD = 4.2V PVDD = 5V

OUTPUT PO WER (W)

PVDD = 5V

RL = 4Ω + 15µH

.5

09960-019

09960-021

Rev. 0 | Page 11 of 36

ANALOG DEVICES SSM2804 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

I2C TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS