ANALOG DEVICES SSM2518 Service Manual

Digital Input Stereo, 2 W, Class-D

Data Sheet

FEATURES

Filterless, digital input Class-D amplifier
Serial digital audio interface supports common formats

2

I

S, left justified, right justified, TDM1-16, and PCM

2 channels × 2 W into 4 Ω and 2 channels × 1.4 W into 8 Ω

with 1% THD+N, when using a 5 V supply

2

I

C control interface or standalone operation
91% efficiency at full scale into an 8 Ω load
97 dB signal-to-noise ratio (SNR), A-weighted
80 dB power supply rejection ratio (PSRR) at 217 Hz
Digital volume control: −71.25 dB to +24 dB in 0.375 dB steps
Supports a wide range of sample rates from 8 kHz to 96 kHz
Automatic sample rate detection
Can operate using 64 × f

2.5 V to 5.5 V speaker supply voltage (PVDD)

1.62 V to 3.6 V digital supply voltage (DVDD)
Pop-and-click suppression
Short-circuit and thermal protection with programmable

autorecovery
Smart power-down when no input signal is detected
Power-on reset
Low power modes for performance/power trade-offs
User selectable ultralow EMI emission mode
Programmable dynamic range compression (DRC) with

noise gate, expander, compressor, and limiter
Available in two packages

16-bump, 2.2 mm × 2.2 mm, 0.5 mm pitch WLCSP

20-lead, 4.0 mm × 4.0 mm LFCSP

APPLICATIONS

Mobile phones
Portable media players
Laptop PCs
Wireless speakers
Portable gaming
Small LCD televisions
Navigation systems

BCLK as the MCLK source

S

Audio Power Amplifier

SSM2518

GENERAL DESCRIPTION

The SSM2518 is a digital input, Class-D power amplifier that com­bines a digital-to-analog converter (DAC) and a sigma-delta
(Σ-) Class-D modulator. This unique architecture enables
extremely low real-world power consumption from digital
audio sources with excellent audio performance. The SSM2518
is ideal for power sensitive applications, such as mobile phones
and portable media players, where system noise can corrupt
small analog signals such as those sent to an analog input audio
amplifier.

Using the SSM2518, audio data can be transmitted to the amplifier
over a standard digital audio serial interface, thereby significantly
reducing the effect of noise sources such as GSM interference or
other digital signals on the transmitted audio. The closed-loop
digital input design retains the benefits of an all digital amplifier,
yet enables very good PSRR and audio performance. The three
level, Σ- Class-D modulator is designed to provide the least
amount of EMI interference, the lowest quiescent power dissi­pation, and the highest audio efficiency without sacrificing
audio quality.

Input is provided via a serial audio interface, programmable to
accept all common audio formats including I
of the IC is provided via an I

2

C control interface. The SSM2518
can accept a variety of input MCLK frequencies and can use
BCLK as the clock source in some configurations.

Additional features include a soft digital volume control, de­emphasis, and a programmable digital dynamic range
compressor.

The architecture of the SSM2518 provides a solution that offers
lower power and higher performance than existing DAC plus
Class-D solutions. Its digital interface also offers a better system
solution for other products whose sole audio source is digital,
such as wireless speakers, laptop PCs, portable digital televisions,
and navigation systems.

2

S and TDM. Control

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

SSM2518 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Performance Specifications......................................................... 5

Power Supply Requirements ....................................................... 6

Digital Input/Output.................................................................... 6

Digital Interpolation Filter.......................................................... 6

Digital Timing............................................................................... 7

Absolute Maximum Ratings ....................................................... 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 14

Power Supplies ............................................................................ 14

Power-Down Modes .................................................................. 14

Power-On Reset/Voltage Supervisor........................................ 14

Master and Bit Clock.................................................................. 14

Typical Application Circuit ........................................................... 16

Digital Audio Interface .................................................................. 17

Channel Mapping....................................................................... 17

Sample Rate Detection............................................................... 17

Standalone Mode........................................................................ 17

Low Power Modes ......................................................................17

Dynamic Range Control............................................................ 17

Mute Options.............................................................................. 18

Volume Control .......................................................................... 18

De-emphasis Filter .....................................................................18

Analog Gain ................................................................................18

Fault Detection and Recovery................................................... 19

Digital Audio Formats................................................................... 20

Stereo Mode ................................................................................ 20

TDM, 50% Duty Cycle Mode ................................................... 20

TDM, Pulse Mode...................................................................... 20

PCM, Multichannel Mode ........................................................ 21

PCM Mono Mode ...................................................................... 21

I2C Configuration Interface .......................................................... 22

Overview ..................................................................................... 22

Register Summary (REG_MAP) .................................................. 25

Register (REG_MAP) Details ....................................................... 26

Software Reset and Master Software Power-down Control

Register ........................................................................................ 26

Edge Speed and Clocking Control Register............................ 27

Serial Audio Interface and Sample Rate Control Register.... 28

Serial Audio Interface Control Register.................................. 29

Channel Mapping Control Register......................................... 30

Left Channel Volume Control Register................................... 31

Right Channel Volume Control Register ................................ 32

Volume and Mute Control Register......................................... 33

Fault Control 1 Register............................................................. 34

Power and Fault Control Register............................................ 35

DRC Control 1 Register............................................................. 36

DRC Control 2 Register............................................................. 37

DRC Control 3 Register............................................................. 38

DRC Control 4 Register............................................................. 40

DRC Control 5 Register............................................................. 41

DRC Control 6 Register............................................................. 42

DRC Control 7 Register............................................................. 44

DRC Control 8 Register............................................................. 45

DRC Control 9 Register............................................................. 46

Packaging and Ordering Information ......................................... 47

Outline Dimensions................................................................... 47

Ordering Guide .......................................................................... 48

Rev. A | Page 2 of 48

Data Sheet SSM2518

REVISION HISTORY

12/11—Rev. 0 to Rev. A

Added LFCSP...................................................................... Universal

Changes to Features Section............................................................1

Changes to Table 1, Supply Current Parameter ............................5

Changes to Table 3, Input Voltage Parameter................................6

Changes to Table 7 ............................................................................8

Added Figure 5 and Table 9, Renumbered Sequentially............10

Changes to Power-Down Modes Section.....................................14

Changes to Master and Bit Clock Section....................................14

Changes to Sample Rate Detection Section.................................17

10/11—Revision 0: Initial Version

Rev. A | Page 3 of 48

SSM2518 Data Sheet

FUNCTIONAL BLOCK DIAGRAM

DVDD SA_MOD PVDD GND

POWER-ON

LRCLK

BCLK

SDATA

SD

RESET

VOLUME

2

CONTROL

I

S

CLOCKIN G

POWER

CONTROL

DRC

DAC

2

I

C

-

CLASS-D

MODULATOR

FULL BRIDGE

POWER

STAGE

FULL BRIDGE

POWER

STAGE

OUTL+

OUTL–

OUTR+

OUTR–

MCLK

SDA SCL

ADDR

10242-001

Figure 1.

Rev. A | Page 4 of 48

Data Sheet SSM2518

SPECIFICATIONS

All specifications at PVDD = 5.0 V, DVDD = 1.8 V, fS = 48 kHz, MCLK = 128 × fS, TA = 25°C, RL = 8  + 15 µH, LP_MODE = 0, volume
control = 0 dB, unless otherwise noted.

PERFORMANCE SPECIFICATIONS

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

DEVICE CHARACTERISTICS

P

Output Power
R
R
R
R
R
R
R
R
R
R
R

Efficiency η PO = 1.4 W, 8 Ω, PVDD = 5.0 V, normal operation 91 %
P

Total Harmonic Distortion

Plus Noise

Channel Separation

Average Switching Frequency fSW 280 kHz

Differential Output Offset V

Power Supply Rejection Ratio PSRRDC PVDD = 2.5 V to 5.0 V 70 80 dB

PSRR

PSRR

Supply Current I

PVDD
Dither input, no load, PVDD = 3.6 V 4.4 mA
Dither input, no load, PVDD = 2.5 V 3.8 mA

DVDD I
Dither input, no load, DVDD = 1.8 V 1.5 mA
Dither input, no load, DVDD = 1.8 V, fS = 8 kHz 0.25 mA

Output Noise Voltage en PVDD = 5 V, f = 20 Hz to 20 kHz, dither input, A-weighted 50 μV

PVDD = 3.6 V, f = 20 Hz to 20 kHz, dither input, A-weighted 40 μV
Signal-to-Noise Ratio SNR A-weighted, referred to 0 dBFS, PVDD = 3.6 V 97 dB
Mute Attenuation Soft mute on 100 dB

f = 1 kHz, BW = 20 kHz

O

RL = 4 Ω, THD = 1%, PVDD = 5.0 V 2 W

= 4 Ω, THD = 10%, PVDD = 5.0 V 2.5 W

L

= 8 Ω, THD = 1%, PVDD = 5.0 V 1.42 W

L

= 8 Ω, THD = 10%, PVDD = 5.0 V 1.8 W

L

= 4 Ω, THD = 1%, PVDD = 3.6 V 1.3 W

L

= 4 Ω, THD = 10%, PVDD = 3.6 V 1.7 W

L

= 8 Ω, THD = 1%, PVDD = 3.6 V 0.75 W

L

= 8 Ω, THD = 10%, PVDD = 3.6 V 0.94 W

L

= 4 Ω, THD = 1%, PVDD = 2.5 V 0.4 W

L

= 4 Ω, THD = 10%, PVDD = 2.5 V 0.45 W

L

= 8 Ω, THD = 1%, PVDD = 2.5 V 0.275 W

L

= 8 Ω, THD = 10%, PVDD = 2.5 V 0.35 W

L

= 1.4 W, 8 Ω, PVDD = 5.0 V, ultralow EMI operation 86 %

O

THD + N PO = 0.5 W into 8 Ω each channel, f = 1 kHz, PVDD = 5 V 0.04 %
P
X

TAL K

OOS

GSM VRIPPLE

GSM VRIPPLE

PVDD

DVDD

= 0.25 W into 8 Ω each channel, f = 1 kHz, PVDD = 3.6 V 0.03 %

O

PO = 1 W, f = 1 kHz, PVDD = 5 V 108 dB

2.0 mV

= 100 mV rms at 217 Hz, dither input 80 dB
= 100 mV rms at 217 Hz, no input 100 dB

Dither input, no load, PVDD = 5.0 V 4.7 mA

Software power-down, SD
Hardware power-down, SD

= 1.8 V, SPWDN = 1, PVDD = 3.6 V

= 0 V, PVDD = 3.6 V

4 μA
100 nA

Dither input, no load, DVDD = 3.3 V 3.0 mA

Software power-down, SD
Hardware power-down, SD

= 1.8 V, SPWDN = 1, DVDD = 1.8 V

= 0 V, DVDD = 1.8 V

2.5 μA
100 nA

Rev. A | Page 5 of 48

SSM2518 Data Sheet

POWER SUPPLY REQUIREMENTS

Table 2.

Parameter Min Typ Max Unit

PVDD 2.5 3.6 5.5 V
DVDD 1.62 1.8 3.6 V

DIGITAL INPUT/OUTPUT

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT VOLTAGE

High (VIH) 0.7 × DVDD 3.6 V ADDR, MCLK, BCLK, LRCLK, SDATA, SAMOD

1.35 5.5 V
Low (VIL) −0.3 +0.3 × DVDD V ADDR, MCLK, BCLK, LRCLK, SDATA, SAMOD

−0.3 +0.35 V

INPUT LEAKAGE CURRENT

High (IIH) 1 μA Excluding MCLK
Low (IIL) 1 μA Excluding MCLK and bidirectional pin

MCLK INPUT LEAKAGE CURRENT

High (IIH) 3 μA
Low (IIL) 3 μA

INPUT CAPACITANCE 5 pF

, SDA, SCL

SD

, SDA, SCL

SD

DIGITAL INTERPOLATION FILTER

Table 4.

Parameter Factor Min Typ1 Max Unit

PASS BAND

−3 dB 0.4535 × f

S

Ripple ±0.01 dB

TRANSITION BAND 0.5 × f

S

STOP BAND 0.5465 × fS 26 kHz

Attenuation 70 dB

GROUP DELAY 25/f

1

Typical value given for 48 kHz sample rate.

S

22 kHz

24 kHz

521 μs

Rev. A | Page 6 of 48

Data Sheet SSM2518

SDA

DIGITAL TIMING

All timing specifications are given for the default setting (I2S mode) of the serial input port.

Table 5.

Limit
Parameter Min Max Unit Description

MASTER CLOCK

tMP 74 136 ns MCLK period, 256 × fS mode (MCS = b0010)
tMP 148 271 ns MCLK period, 128 × fS mode (MCS = b0001)

SERIAL PORT

t

40 ns BCLK low pulse width

BIL

t

40 ns BCLK high pulse width

BIH

t

10 ns Setup time from LRCLK or SDATA edge to BCLK rising edge

LIS

t

10 ns Hold time from BCLK rising edge to LRCLK or SDATA edge

LIH

t

10 ns SDATA setup time to BCLK rising

SIS

t

10 ns SDATA hold time from BCLK rising

SIH

I2C PORT

f

SCL

t

0.6 μs SCL high

SCLH

t

1.3 μs SCL low

SCLL

t

0.6 μs Setup time; relevant for repeated start condition

SCS

t

0.6 μs Hold time; after this period, the first clock is generated

SCH

tDS 100 ns Data setup time
t

300 ns SCL rise time

SCR

t

300 ns SCL fall time

SCF

t

300 ns SDA rise time

SDR

t

300 ns SDA fall time

SDF

t

0.6 μs Bus-free time (time between stop and start)

BFT

400 kHz SCL frequency

Digital Timing Diagrams

BCLK

LRCLK

SDATA

LEFT-JUSTIFIED

MODE

SDATA

2

C-JUSTIFIED

I

MODE

RIGHT-JUSTIFIED

SDATA

MODE

SCL

t

BIH

START

CONDITION

t

BP

t

BIL

t

LIS

t

SIS

MSB

t

SIH

MSB – 1

t

SIS

MSB

t

SIH

t

SIS

MSB LSB

t

SIH

t

LIH

t

SIS

t

SIH

10242-002

Figure 2. Serial Input Port Timing

t

SCH

t

SCR

t

SCLL

t

DS

t

SCLH

t

SCF

Figure 3. I

2

C Port Timing

t

SCS

t

SCH

t

BFT

CONDITION

STOP

10242-003

Rev. A | Page 7 of 48

SSM2518 Data Sheet

v

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 6.

Parameter Rating

PVDD Supply Voltage −0.3 V to +6 V
DVDD Supply Voltage −0.3 V to +3.6 V
Input Voltage (ADDR, MCLK, BCLK, LRCLK,

SDATA, SAMOD Pins)

Input Voltage (SD, SDA, and SCL Pins)
ESD Susceptibility 4 kV
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses abovethose listedunderAbsoluteMaximumRatings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute

maximumratingconditionsfor extendedperiodsmayaffect

ice reliability.

de

−0.3 V to +3.6 V

−0.3 V to +6 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA Unit

16-ball, 2 mm × 2 mm WLCSP 56 °C/W
20-lead, 4.0 mm × 4.0 mm LFCSP 54 °C/W

ESD CAUTION

Rev. A | Page 8 of 48

Data Sheet SSM2518

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1
INDICAT OR

234

1

OUTR+

A

OUTR–

B

DVDD

C

SDATA

D

(BALL SIDE DOWN)

Figure 4. WLCSP Pin Configuration

Table 8. Pin Function Descriptions, WLCSP

Pin No. Mnemonic Function1 Description

A1 OUTR+ O Right Channel Output Positive.
B1 OUTR− O Right Channel Output Negative.
A4 OUTL+ O Left Channel Output Positive.
B4 OUTL− O Left Channel Output Negative.
A3 PVDD P 2.5 V to 5.5 V Amplifier Power.
A2 GND P Amplifier Ground.
C1 DVDD P 1.62 V to 3.6 V Digital and Analog Power.
B2

SD

I Power-Down Control, Active Low.
C3 SCL I I2C Clock.
C4 SDA I/O I2C Data.
D4 MCLK I Serial Audio Interface Master Clock.
D2 LRCLK I I2S Word Clock.
D3 BCLK I I2S Bit Clock.
D1 SDATA I I2S Serial Data.
C2 SAMOD I Standalone/I2C Mode Select. High = standalone mode, low = I2C mode.
B3 ADDR I I2C Address Select.

1

I is input, O is output, I/O is input/output, and P is power.

GND

SD

SAMOD

LRCLK

TOP VIEW

Not to Scale

PVDD

ADDR

SCL

BCLK

OUTL+

OUTL–

SDA

MCLK

10242-009

Rev. A | Page 9 of 48

SSM2518 Data Sheet

GND

GND

PVDD
20

1OUTL+
2OUTL–

SSM2518

3ADDR

TOP VIEW

4SDA

(Not to Scale)

5SCL

6

MCLK

NOTES

1. CONNECT THE EXPO S E D PAD TO GND.

Figure 5. LFCSP Pin Configuration

Table 9. Pin Function Descriptions, LFCSP

Pin No. Mnemonic Function1 Description

1 OUTL+ O Left Channel Output Positive.
2 OUTL− O Left Channel Output Negative.
3 ADDR I I2C Address Select.
4 SDA I/O I2C Data.
5 SCL I I2C Clock.
6 MCLK I Serial Audio Interface Master Clock.
7 BCLK I I2S Bit Clock.
8 GND P Amplifier Ground.
9 LRCLK I I2S Word Clock.
10 SDATA I I2S Serial Data.
11 SAMOD I Standalone/I2C Mode Select. High = standalone mode, low = I2C mode.
12 DVDD P 1.62 V to 3.6 V Digital and Analog Power.
13

SD

I Power-Down Control, Active Low.

14 OUTR− O Right Channel Output Negative.
15 OUTR+ O Right Channel Output Positive.
16 PVDD P 2.5 V to 5.5 V Amplifier Power.
17 GND P Amplifier Ground.
18 GND P Amplifier Ground.
19 GND P Amplifier Ground.
20 PVDD P 2.5 V to 5.5 V Amplifier Power.

1

I is input, O is output, I/O is input/output, and P is power.

GND
17

18

19

PIN 1
INDICATOR

9

8

7

GND

BCLK

LRCLK

PVDD
16

10

SDATA

15 OUTR+
14 OUTR–
13 SD
12 DVDD
11 SAMOD

10242-110

Rev. A | Page 10 of 48

Data Sheet SSM2518

TYPICAL PERFORMANCE CHARACTERISTICS

100

GAIN = 5V
MCLK = 256 ×
RL = 8, 33µH

f

S

2.5V

3.6V

5.0V

100

GAIN = 3.6V
MCLK = 256 ×
RL = 8, 33µH

f

S

2.5V

3.6V

5.0V

10

1

THD + N (%)

0.1

0.01

0.001 0.01 0.1 1 10

OUTPUT POWER (W)

Figure 6. THD + N vs. Output Power into 8 Ω, 5.0 V Gain Setting

100

10

THD + N (%)

0.1

GAIN = 5V
MCLK = 256 ×
RL = 4, 15µH

1

f

S

2.5V

3.6V

5.0V

10

1

THD + N (%)

0.1

0.01

0.001 0.01 0.1 1 10

10242-011

OUTPUT POWE R (W)

10242-014

Figure 9. THD + N vs. Output Power into 8 Ω, 3.6 V Gain Setting

100

10

THD + N (%)

0.1

GAIN = 3.6V
MCLK = 256 ×
RL = 4, 15µH

1

f

S

2.5V

3.6V

5.0V

0.01

0.001 0.01 0.1 1 10

OUTPUT POWER (W)

Figure 7. THD + N vs. Output Power into 4 Ω, 5.0 V Gain Setting

100

PVDD = 5V
GAIN = 5V
MCLK = 256 ×
RL = 8, 33µH

10

1

THD + N (%)

0.1

0.01

10 100 1k 10k 100k

f

S

FREQUENCY (Hz)

Figure 8. THD + N vs. Frequency, PVDD = 5 V, R

0.25W

0.5W

1.0W

= 8 Ω

L

0.01

0.001 0. 01 0.1 1 10

10242-012

OUTPUT POWER (W)

10242-015

Figure 10. THD + N vs. Output Power into 4 Ω, 3.6 V Gain Setting

100

PVDD = 5V
GAIN = 5V
MCLK = 256 ×
RL = 4, 15µH

10

1

THD + N (%)

0.1

0.01

10 100 1k 10k 100k

10242-013

f

S

FREQUENCY (Hz)

Figure 11. THD + N vs. Frequency, PVDD = 5 V, R

0.25W

0.5W

1.0W

= 4 Ω

L

10242-016

Rev. A | Page 11 of 48

SSM2518 Data Sheet

100

PVDD = 3.6V
GAIN = 3.6V
MCLK = 256 ×
RL = 8, 33µH

10

0.125W

f

S

0.25W

0.5W

100

PVDD = 3.6V
GAIN = 3.6V
MCLK = 256 ×
RL = 4, 15µH

10

0.125W

f

S

0.25W

0.5W

1

THD + N (%)

0.1

0.01
10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 12. THD + N vs. Frequency, PVDD = 3.6 V, R

100

PVDD = 2.5V
GAIN = 3.6V
MCLK = 256 ×
RL = 8, 33µH

10

1

THD + N (%)

0.1

0.01

10 100 1k 10k 100k

f

S

FREQUENC Y (Hz)

Figure 13. THD + N vs. Frequency, PVDD = 2.5 V, R

9

DAC_LPM = 1
AMP_LPM = 1
DVDD = 1.8V
DITHER INPUT

8

= 8 Ω

L

0.05W

0.10W

0.20W

= 8 Ω

L

1

THD + N (%)

0.1

0.01
10 100 1k 10k 100k

10242-017

Figure 15. THD + N vs. Frequency, PVDD = 3.6 V, R

FREQUENCY (Hz)

= 4 Ω

L

10242-020

100

PVDD = 2.5V
GAIN = 3.6V
MCLK = 256 ×
RL = 4, 15µH

10

1

THD + N (%)

0.1

0.01

10 100 1k 10k 100k

10242-018

f

S

FREQUENC Y (Hz)

Figure 16. THD + N vs. Frequency, PVDD = 2.5 V, R

0.05W

0.10W

0.20W

= 4 Ω

L

10242-021

4.0

MCLK = 256 ×
DAC_LPM = 1, AMP_L PM = 1

3.5

3.0

f

S

7

6

QUIESCENT CURRENT (mA)

5

4

2.5 3.0 3.5 4.0 4.5 5.0 5. 5 6.0

SUPPLY VOLTAGE (V)

NO LOAD
8 + 33µH
4 + 33µH

Figure 14. Quiescent Current (Power Stage) vs. Supply Voltage

10242-019

Rev. A | Page 12 of 48

2.5

2.0

1.5

1.0

QUIESCENT CURRENT (mA)

0.5

0

1.6 2.0 2.4 2.8 3.2 3.6

SUPPLY VOLTAGE (V)

8kHz 256 ×
24kHz 256 ×
48kHz 256 ×

Figure 17. Quiescent Current (Digital Core) vs. Supply Voltage

f

S

f

S

f

S

10242-022

Data Sheet SSM2518

2.5

2.0

1.5

GAIN = 5V

= 4, 15µH

R

L

1kHz

1.4

1.2

1.0

0.8

GAIN = 5V

= 8, 33µH

R

L

1kHz

1.0

OUTPUT POWER (W)

0.5

0

2.5 3. 0 3.5 4.0 4.5 5.0

SUPPLY VOLTAGE (V)

Figure 18. Maximum Output Power vs. Supply Voltage, R

100

5V

3.6V

90

2.5V

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8

COMBINED OUTPUT POW ER, BOTH CHANNELS (W)

RL = 4, 15µ

Figure 19. Efficiency vs. Output Power into 4 Ω

0

PVDD = 5V

= 8, 33H

R

L

P

= 100mW

O

–20

–40

–60

–80

LEFT TO RIGHT

CROSSTALK (dB)

–100

–120

RIGHT TO LEFT

–140

20 200 2k

FREQUENC Y (Hz)

Figure 20. Crosstalk vs. Frequency

1%
5%
10%

= 4 Ω

L

20k

0.6

OUTPUT POWER ( W)

0.4

0.2

0

2.5 3.0 3.5 4.0 4.5 5.0

10242-024

SUPPLY VOLTAGE (V)

1%
5%
10%

10175-026

Figure 21. Maximum Output Power vs. Supply Voltage, RL = 8 Ω

100

5V

3.6V

90

2.5V

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2

10242-028

COMBINED OUTPUT POW ER, BOTH CHANNELS (W)

RL = 8 + 33µ

10175-029

Figure 22. Efficiency vs. Output Power into 8 Ω

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10242-027

PVDD = 2.5V

10 100 1k 10k 100k

PVDD = 5V

FREQUENCY (Hz)

PVDD = 3.6V

10242-030

Figure 23. PSRR vs. Frequency

Rev. A | Page 13 of 48

SSM2518 Data Sheet

THEORY OF OPERATION

The SSM2518 is fully integrated 2-channel digital input, Class-D
output audio amplifier. The SSM2518 receives digital audio input
and produces the PDM differential switching outputs using the
internal power stage. The part has built in protection for over­temperature as well as overcurrent conditions. The SSM2518
also has built in soft turn on and soft turn off for pop-and-click
suppression. The part has programmable register control via the

2

I

C port.

POWER SUPPLIES

The SSM2518 requires two power supplies: PVDD and DVDD.
Descriptions of each of these supplies follow.

PVDD

The PVDD pin supplies power to the full bridge power stage
of a MOSFET and its associated drive, control, and protection
circuitry. PVDD can operate from 2.5 V to 5.5 V and must be
present to obtain audio output. Lowering the supply PVDD
results in lower output power and, correspondingly, lower
power consumption but does not degrade audio performance.

DVDD

The DVDD pin provides power to the digital logic circuitry and
determines the input trip points. DVDD can operate from 1.62 V
to 3.6 V and must be present to obtain audio output. Lowering
the supply voltage of DVDD results in lower power consump­tion but does not affect audio performance.

POWER-DOWN MODES

The SSM2518 offers a hardware shutdown pin, SD, which can

be used to set the IC to its lowest power state, with all blocks
disabled. This hardware shutdown mode is enabled when the

pin is pulled low.

SD

When the hardware shutdown is removed, the IC begins in
software power-down mode, where all blocks except for the

2

I

C interface are disabled. To fully power up the amplifier, clear
S_RST (Bit 7 of Register 0x00). In addition to the software
power-down, the software master mute is enabled at the initial
state of the amplifier; therefore, no audio is output until Bit 0 of
Register 0x07 is cleared.

The left and right channels can be independently shut down
by setting setting L_PWDN and R_PWDN (Bit 1 and Bit 2,
respectively, in Register 0x09). Disabling a channel shuts down
the channel specific digital processing, DAC, Class-D modulator,
and power stage.

The SSM2518 also contains a smart power-down feature, which
is enabled by default. This feature can be disabled by clearing
APWDN_EN (Bit 0 in Register 0x09). When active, this feature

monitors the incoming digital audio signal. If this is zero for
1024 consecutive samples, regardless of sample rate, it puts the
IC in the smart power-down state wherein all blocks, except the

2

I

S and I2C ports, are placed in a low power state. Once a single

nonzero input is received on the I

2

S interface, the SSM2518 leaves

this state and resumes normal operation.

POWER-ON RESET/VOLTAGE SUPERVISOR

The SSM2518 includes an internal power-on reset and voltage
supervisor circuit. This circuit provides an internal reset to all
circuitry whenever PVDD or DVDD is substantially below the
nominal operating threshold. This circuit simplifies supply
sequencing during initial power-on.

The circuit also monitors the power supplies to the SSM2518. If
the supply voltages fall below the nominal operating threshold,
this circuit stops the output and issues a reset. This ensures that
no damage occurs due to low voltage operation and that no pops
can occur under nearly any power removal condition.

MASTER AND BIT CLOCK

The SSM2518 requires an internal master clock to operate. This
clock must run at a frequency between 2.048 MHz and 6.144 MHz,
depending on the input sample rate, and it must be fully synchro­nous with the incoming audio data. This clock signal can be
derived from either the MCLK or BCLK pin, depending on the
configuration used.

If the MCLK pin is used, the internal clock is derived by either
dividing, passing through, or doubling the external clock signal
as required. The clock supplied to the MCLK pin can range from

2.048 MHz to 38.864 MHz. In this case, the external MCLK pin
signal can run at various multiples of the audio sample rate (f
The relationship between the MCLK rate and the audio sample
rate is determined by the master clock select (MCS) register setting,
Bits[4:1] in Register 0x00. Tab le 1 1 provides a summary of the
available options.

In addition, a bit clock must run at the same rate as the incoming
audio data on the SDATA pin. This clock can be supplied to the
BCLK pin, or it can be generated internally by dividing MCLK.
In this case, when BCLK_GEN (Bit 7 of Register 0x03) is set, the
logic level of the BCLK pin is used to select the audio interface
BCLK rate. Tie the BCLK pin to DVDD for 16 clock cycles per
channel; tie it to ground for 32 cycles per channel.

If the system bit clock is in the range of acceptable internal
master clock frequencies (between 2.048 MHz and 6.144 MHz),
then it can serve as both master clock and bit clock. Setting
NO_BCLK (Bit 5 of Register 0x00) routes the signal on the

).

S

Rev. A | Page 14 of 48

Data Sheet SSM2518

MCLK pin to serve as the internal bit clock as well. In this case,
tie the BCLK pin to ground.

Once the SSM2518 has entered its power-down state, it is
possible to gate the clocks to conserve system power. However, a
valid master clock must be present for the audio amplifier to
operate. It is best to use a low jitter clock (less than 1 ns peak­to-peak) to ensure the specified audio performance.

Rev. A | Page 15 of 48