ANALOG DEVICES SSM2317 Service Manual

Filterless High Efficiency

www.BDTIC.com/ADI

FEATURES

Filterless Class-D amplifier with Σ-Δ modulation
Automatic level control (ALC) improves dynamic range and

prevents clipping

3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply

with <10% total harmonic distortion (ALC off)
700 mW into 8 Ω load at 4.2 V supply (ALC 80%)
93% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
>93 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 18 dB or user-adjustable gain setting

APPLICATIONS

Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys

GENERAL DESCRIPTION

The SSM2317 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V

Mono 3 W Class-D Audio Amplifier

SSM2317

supply. It is capable of delivering 3 W of continuous output
power with <1% THD + N driving a 3 Ω load from a 5.0 V supply.

The SSM2317 features a high efficiency, low noise modulation
scheme that does not require any external LC output filters. The
modulation continues to provide high efficiency even at low output
power. It operates with 93% efficiency at 1.4 W into 8 Ω or 85%
efficiency at 3 W into 3 Ω from a 5.0 V supply and has an SNR of
>93 dB. Spread-spectrum pulse density modulation is used to
provide lower EMI radiated emissions compared with other
Class-D architectures.

Automatic level control (ALC) can be activated to suppress
clipping and improve dynamic range. This feature only requires
one external resistor tied to GND via the VTH pin and an
activation voltage on the ALC_EN pin.

The SSM2317 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying
a logic low to the

The device also includes pop-and-click suppression circuitry. This
minimizes voltage glitches at the output during turn-on and turn­off, reducing audible noise on activation and deactivation.

The default gain of the SSM2317 is 18 dB, but users can reduce the
gain by using a pair of external resistors (see the Gain section).

The SSM2317 is specified over the commercial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm
wafer level chip scale package (WLCSP).

SD

pin.

FUNCTIONAL BLOCK DIAGRAM

BIAS

80kΩ

80kΩ

ALC_EN

ALC ENABLE

/2.

DD

ALC

1

AUDIO IN+

AUDIO IN–

SHUTDOWN

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

0.1µF

1

0.1µF

1

INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V

IN+

IN–

SD

10kΩ

10kΩ

VDD

FET

GND

VBATT

2.5V TO 5.5V

OUT+

OUT–

07242-001

10µF

SSM2317

MODULATOR

(Σ-Δ)

INTERNAL

OSCILLAT OR

VTH

R

TH

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

0.1µF

DRIVER

POP-AND-CLICK

SUPPRESSION

SSM2317

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Typical Application Circuits .......................................................... 13

Theory of Operation ...................................................................... 14

Overview ...................................................................................... 14

Gain .............................................................................................. 14

Pop-and-Click Suppression ...................................................... 14

Output Modulation Description .............................................. 14

Layout .......................................................................................... 14

Input Capacitor Selection .......................................................... 15

Proper Power Supply Decoupling ............................................ 15

Automatic Level Control (ALC) ............................................... 15

Operating Modes ........................................................................ 15

Attack Time, Hold Time, and Release Time ........................... 15

Output Threshold ....................................................................... 16

Enable/Disabling ALC ............................................................... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

REVISION HISTORY

6/08—Rev. 0 to Rev. A

Changes to Figure 1 .......................................................................... 1

Changes to Table 2 ............................................................................ 5

Changes to Figure 17 and Figure 18 ............................................... 9

Changes to Figure 39 and Figure 40 ............................................. 13

Changes to Ordering Guide .......................................................... 17

3/08—Revision 0: Initial Version

Rev. A | Page 2 of 20

SSM2317

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SPECIFICATIONS

VDD = 5.0 V, TA = 25°C, RL = 8 Ω + 33 µH, ALC = off, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power PO R

R

R

R

R

R

R

R

R

R

R

R

Efficiency η PO = 1.4 W, 8 Ω, VDD = 5.0 V 93 %

Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.02 %

P

1.0 VDD − 1.0 V

Input Common-Mode Voltage

V

CM

Range
Common-Mode Rejection Ratio CMRR
Average Switching Frequency fSW 280 kHz
Differential Output Offset Voltage V

OOS

POWER SUPPLY

Supply Voltage Range V

DD

Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating 70 85 dB
PSRR

Supply Current (Typically, 170 μA

GSM

I

SY

Increase with ALC On)
V
V
V
V
V
Shutdown Current ISD

GAIN CONTROL

Closed-Loop Gain Gain 18 dB
Differential Input Impedance Z

IN

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Wake-Up Time t
Shutdown Time t

Output Impedance Z

WU

SD

IH

IL

OUT

= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.42 W

L

= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.72 W

L

= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.77 W

L

= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.91 W

L

= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 2.53 W

L

= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.27 W

L

= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.161 W

L

= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.59 W

L

= 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.11

L

= 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.55 W

L

= 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 3.89

L

= 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.94 W

L

= 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.02 %

O

GSM VCM

= 2.5 V ± 100 mV at 217 Hz, output referred 57 dB

1

W

1

W

Gain = 18 dB 2.0 mV

Guaranteed from PSRR test 2.5 5.5 V

V

= 100 mV at 217 Hz, inputs ac grounded,

RIPPLE

= 0.1 μF

C

IN

60 dB

VIN = 0 V, no load, VDD = 5.0 V 3.6 mA

= 0 V, no load, VDD = 3.6 V 3.2 mA

IN

= 0 V, no load, VDD = 2.5 V 2.7 mA

IN

= 0 V, load = 8 Ω + 33 μH, VDD = 5.0 V 3.7 mA

IN

= 0 V, load = 8 Ω + 33 μH, VDD = 3.6 V 3.3 mA

IN

= 0 V, load = 8 Ω + 33 μH, VDD = 2.5 V 2.8 mA

IN

= GND

SD

SD = VDD

= GND

SD

20 nA

10 kΩ
10 kΩ

ISY ≥ 1 mA 1.2 V
ISY ≤ 300 nA 0.5 V
SD rising edge from GND to VDD
SD falling edge from VDD to GND

= GND

SD

28 ms
5 μs
>100 kΩ

Rev. A | Page 3 of 20

SSM2317

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Parameter Symbol Conditions Min Typ Max Unit

NOISE PERFORMANCE

Output Voltage Noise en

Signal-to-Noise Ratio SNR PO = 1.4 W, RL = 8 Ω 93 dB

1

Although the SSM2317 has good audio quality above 3 W, continuous output power beyond 3 W must be avoided due to device packaging limitations.

= 3.6 V, f = 20 Hz to 20 kHz, inputs are ac grounded,

V

DD

gain = 18 dB, A-weighted

72 μV

Rev. A | Page 4 of 20

SSM2317

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ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at TA = 25°C, unless other­wise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Continuous Output Power 3 W
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Susceptibility 4 kV

DD

DD

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type PCB θJA θJB Unit

9-Ball, 1.5 mm × 1.5 mm WLCSP 1S0P 162 39 °C/W
2S0P 76 21 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 5 of 20

SSM2317

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BALL A1
CORNER

A

B

C

SSM2317

TOP VIEW

(BALL SIDE DO WN)

Not to Scale

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1A IN− Inverting Input.
1B IN+ Noninverting Input.
1C GND Ground.
2A
2B ALC_EN Automatic Level Control Enable Input. Active high digital input.
2C VDD Power Supply.
3A VTH Variable Threshold.
3B OUT− Inverting Output.
3C OUT+ Noninverting Output.

SD

Shutdown Input. Active low digital input.

321

07242-002

Rev. A | Page 6 of 20