ANALOG DEVICES SSM2306 Service Manual

2 W, Filterless, Class-D

www.BDTIC.com/ADI

FEATURES

Filterless Class-D amplifier with built-in output stage
2 W into 4 Ω and 1.4 W into 8 Ω at 5.0 V supply
Ultralow idle current with load resistance
>87% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Better than 96 dB SNR (signal-to-noise ratio)
Available in 16-lead, 3 mm × 3 mm LFCSP
Single-supply operation from 2.5 V to 5.0 V
20 nA ultralow shutdown c
Short-circuit and thermal protection
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 18 dB gain and user-adjustable

APPLICATIONS

Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
Notebook computers

GENERAL DESCRIPTION

The SSM2306 is a fully integrated, high efficiency, Class-D stereo
audio amplifier designed to maximize performance for portable
applications. The application circuit requires minimum external
components and operates from a single 2.5 V to 5.0 V supply. It
is capable of delivering 2 W of continuous output power with less
than 10% THD + N driving a 4 Ω load from a 5.0 V supply.

urrent

Stereo Audio Amplifier

SSM2306

The SSM2306 features ultralow idle current, high efficiency, and

w noise modulation scheme. It operates with >87% efficiency

a lo
at 1.4 W into 8 Ω from a 5.0 V supply and has a signal-to-noise
ratio (SNR) that is better than 96 dB. PDM modulation offers lower
EMI radiated emissions compared to other Class-D architectures.

The SSM2306 has a micropower shutdown mode with a typical

utdown current of 20 nA. Shutdown is enabled by applying a

sh
logic low to the

The architecture of the device allows it to achieve a very low level

f pop and click to minimize voltage glitches at the output

o
during turn-on and turn-off, thereby reducing audible noise on
activation and deactivation. The fully differential input of the
SSM2306 provides excellent rejection of common-mode noise
on the input. Input coupling capacitors can be omitted if the dc
input common-mode voltage is approximately V

The SSM2306 also has excellent rejection of power supply noise,

cluding noise caused by GSM transmission bursts and RF

in
rectification.

The SSM2306 has a preset gain of 18 dB that can be reduced by

g external resistors.

usin

The SSM2306 is specified over the commercial temperature range
(−40°C t
short-circuit protection. It is available in a 16-lead, 3 mm × 3 mm
lead frame chip scale package (LFCSP).

SD

pin.

/2.

DD

o +85°C). It has built-in thermal shutdown and output

FUNCTIONAL BLOCK DIAGRAM

1

RIGHT IN+

RIGHT IN–

SHUTDOWN

LEFT IN+

LEFT IN–

GAIN = 344kΩ/(43kΩ + R

1

INPUT CAPS ARE O PTIONAL IF INPUT DC COMMON-MO DE
VOLTAGE IS APPROXIMATELY V

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

22nF

22nF

22nF

22nF

1

1

1

SSM2306

R

EXT

INR+

INR–

R

EXT

SD

R

EXT

INL+

INL–

R

EXT

)

EXT

/2.

DD

344kΩ

43kΩ

43kΩ

344kΩ

344kΩ

43kΩ

43kΩ

344kΩ

10µF

BIAS

Figure 1.

VBATT

0.1µF

MODULATOR

INTERNAL

OSCIL LATO R

MODULATOR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

2.5V TO 5. 0V

VDDVDD

FET

DRIVER

FET

DRIVER

GNDGND

OUTR+

OUTR–

OUTL+

OUTL–

6542-001

SSM2306

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TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Applicat i o n C i rc uits ......................................................... 11

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

4/07—Revision 0: Initial Version

Application Notes........................................................................... 12

Overview ..................................................................................... 12

Gain Selection............................................................................. 12

Pop-and-Click Suppression ...................................................... 12

EMI Noise.................................................................................... 12

Layout .......................................................................................... 13

Input Capacitor Selection.......................................................... 13

Proper Power Supply Decoupling ............................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

SSM2306

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SPECIFICATIONS

VDD = 5.0 V; TA = 25oC; RL = 4 Ω, 8 Ω; gain = 6 dB, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power P

O

R
R
R
R
R
R
R
R
R
R
R

Efficiency η P

P

Total Harmonic Distortion + Noise THD + N PO = 2 W into 4 Ω each channel, f = 1 kHz, VDD = 5.0 V 0.4 %

P

Input Common-Mode Voltage Range V

CM

Common-Mode Rejection Ratio CMRR

Channel Separation X
Average Switching Frequency f
Differential Output Offset Voltage V

TAL K

SW

OOS

POWER SUPPLY

Supply Voltage Range V

DD

Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V 70 85 dB
PSRR

Supply Current I

SY

V
V
Shutdown Current I

SD

GAIN

Closed-Loop Gain A
Differential Input Impedance Z

v

IN

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Turn-On Time t

Turn-Off Time t
Output Impedance O

IH

IL

WU

SD

UT

NOISE PERFORMANCE

Output Voltage Noise e

n

Signal-to-Noise Ratio SNR P

RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.8 W

= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.4 W

L

= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.9 W

L

= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.615 W

L

= 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.35 W

L

= 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.275 W

L

= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 2.4 W

L

= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.53 W

L

= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 1.1 W

L

= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.77 W

L

= 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.45 W

L

= 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.35 W

L

= 2 W, 4 Ω, VDD = 5.0 V 75 %

OUT

= 1.4 W, 8 Ω, VDD = 5.0 V 85 %

OUT

= 1 W into 8 Ω each channel, f = 1 kHz, VDD = 5.0 V 0.02 %

O

1.0 VDD − 1 V
VCM = 2.5 V ± 100 mV at 217 Hz, G = 18 dB, input

GSM

70 dB

referred
PO = 100 mW , f = 1 kHz 78 dB
420 kHz

2.0 mV

Guaranteed from PSRR test 2.5 5.0 V

GSM

V

= 100 mV rms at 217 Hz, inputs ac GND,

RIPPLE

= 0.1 μF, input referred

C

IN

75 dB

VIN = 0 V, no load, VDD = 5.0 V 6.5 mA

= 0 V, no load, VDD = 3.6 V 5.7 mA

IN

= 0 V, no load, VDD = 2.5 V 5.1 mA

IN

SD

= GND

R

= 0 18 dB

EXT

SD

= VDD

20 nA

43 kΩ

ISY ≥ 1 mA 1.2 V
ISY ≤ 300 nA 0.5 V
SD

rising edge from GND to V

SD

falling edge from VDD to GND

SD

= GND

DD

VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are
ac-grounded, A

= 2.0 W, RL = 4 Ω 96 dB

OUT

= 18 dB, RL = 4 Ω, A weighting

V

30 ms
5 μs
>100 kΩ

44 μV

Rev. 0 | Page 3 of 16

SSM2306

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
ESD Susceptibility 4 kV
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

DD

DD

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

16-Lead, 3 mm × 3 mm LFCSP 44 31.5 °C/W

ESD CAUTION

θ

JA

Unit

JC

Rev. 0 | Page 4 of 16

SSM2306

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD

GND

GND

VDD

14

13

15

16

PIN 1
INDICATOR

1OUTL+

2OUTL–

SSM2306

3SD

TOP VIEW

(Not to Scale)

4INL+

5

6

NC

INL–

NC = NO CONNECT

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 OUTL+ Inverting Output for Left Channel.
2 OUTL− Noninverting Output for Left Channel.
3

SD

Shutdown Input. Active low digital input.

4 INL+ Noninverting Input for Left Channel.
5 INL− Inverting Input for Left Channel.
6 NC No Connect.
7 NC No Connect.
8 INR− Inverting Input for Right Channel.
9 INR+ Noninverting Input for Right Channel.
10 NC No Connect.
11 OUTR− Noninverting Output for Right Channel.
12 OUTR+

Inverting Output for Right Channel.
13 GND Ground for Output Amplifiers.
14 VDD Power Supply for Output Amplifiers.
15 VDD Power Supply for Output Amplifiers.
16 GND Ground for Output Amplifiers.

12 OUTR+

11 OU TR–

10 NC

9 INR+

8

7

NC

INR–

06542-002

Rev. 0 | Page 5 of 16