Analog Devices SSM2301CPZ, SSM2301RMZ Schematic [ru]

Filterless High Efficiency

Mono 1.4 W Class-D Audio Amplifier

FEATURES

Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Class-D amplifiers

from Analog Devices, Inc.

1.4 W into 8 Ω at 5.0 V supply with less than 1% THD + N
85% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Greater than 98 dB SNR (signal-to-noise ratio)
Single-supply operation from 2.5 V to 5.0 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 8-lead, 3 mm × 3 mm LFCSP and MSOP packages
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations

APPLICATIONS

Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys

GENERAL DESCRIPTION

The SSM2301 is a fully integrated, high efficiency, Class-D audio
amplifier designed to maximize performance for mobile phone
applications. The application circuit requires a minimum of
external components and operates from a single 2.5 V to 5.0 V
supply. It is capable of delivering 1.4 W of continuous output
power with less than 1% THD + N driving an 8 Ω load from
a 5.0 V supply.

The SSM2301 features a high efficiency, low noise modulation
scheme that does not require external LC output filters. The modu­lation provides high efficiency even at low output power.

SSM2301

The SSM2301 operates with 85% efficiency at 1.4 W into 8 Ω
from a 5.0 V supply and has a signal-to-noise ratio (SNR) that
is greater than 98 dB. Spread-spectrum modulation is used to
provide lower EMI-radiated emissions compared with other
Class-D architectures.

The SSM2301 has a micropower shutdown mode with a maximum
shutdown current of 30 nA. Shutdown is enabled by applying
a logic low to the

The device also includes pop-and-click suppression circuitry.
This minimizes voltage glitches at the output during turn-on
and turn-off, thus reducing audible noise on activation and
deactivation.

The fully differential input of the SSM2301 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately V

The SSM2301 also has excellent rejection of power supply noise,
including noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 63 dB at 217 Hz.

The gain can be set to 6 dB or 12 dB by utilizing the gain control
select pin connected respectively to ground or to VDD. Gain
can also be adjusted externally by inserting a resistor in series
with each input pin.

The SSM2301 is specified over the commercial temperature range
(−40°C to +85°C). It has built-in thermal shutdown and output
short-circuit protection. It is available in both an 8-lead, 3 mm ×
3 mm lead-frame chip scale package (LFCSP) and an 8-lead
MSOP package.

SD

DD

pin.

/2.

FUNCTIONAL BLOCK DIAGRAM

SSM2301

1

0.01µF

AUDIO IN+

AUDIO IN–

SHUTDOWN

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

IN+

IN–

1

0.01µF
GAIN

SD

NOTES

1

INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V

GAIN

CONTROL

DD

10µF

BIAS

/2.

Figure 1.

VBATT

VDD

GND

2.5V TO 5. 0V

FET

DRIVER

POP/CLICK

SUPPRESSION

OUT+

OUT–

06163-001

0.1µF

MODULATOR

OSCILLAT OR

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

SSM2301

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Applicat i o n C i rc uits ......................................................... 10

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

Thermal Resistance ...................................................................... 4

ESD Caution.................................................................................. 4

Pin Configurations and Function Descriptions ........................... 5

Typical Performance Characteristics ............................................. 6

REVISION HISTORY

10/07—Rev. 0 to Rev. A

Added MSOP Package.......................................................Universal

Changes to Features.......................................................................... 1

Changes to General Description .................................................... 1

Changes to Table 1............................................................................ 3

Deleted Evaluation Board Information Section ......................... 14

Updated Outline Dimensions....................................................... 14

Changes to Ordering Guide.......................................................... 14

Applications Information.............................................................. 12

Overview ..................................................................................... 12

Gain Selection............................................................................. 12

Pop-and-Click Suppression ...................................................... 12

Layout .......................................................................................... 12

Input Capacitor Selection.......................................................... 12

Proper Power Supply Decoupling ............................................ 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

1/07—Revision 0: Initial Version

Rev. A | Page 2 of 16

SSM2301

SPECIFICATIONS

VDD = 5.0 V, TA = 25oC, RL = 8 Ω + 33 μH, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DEVICE CHARACTERISTICS

Output Power P

O

VDD = 5.0 V, RL = 8 Ω, THD = 1%
f = 1 kHz, 20 kHz BW

= 5.0 V, RL = 8 Ω, THD = 10%

V

DD

f = 1 kHz, 20 kHz BW

= 3.6 V, RL = 8 Ω, THD = 1%

V

DD

f = 1 kHz, 20 kHz BW

V

= 3.6 V, RL = 8 Ω, THD = 10%

DD

f = 1 kHz, 20 kHz BW

= 2.5 V, RL = 8 Ω, THD = 1%

V

DD

f = 1 kHz, 20 kHz BW

= 2.5 V, RL = 8 Ω, THD = 10%

V

DD

f = 1 kHz, 20 kHz BW

Efficiency η P

= 1.4 W, 8 Ω, VDD = 5.0 V 85 %

OUT

Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V 0.1 %
P
Input Common-Mode Voltage Range V
Common-Mode Rejection Ratio CMRR
Average Switching Frequency f
Differential Output Offset Voltage V

CM

GSMVCM

SW

OOS

= 0.5 W into 8 Ω, f = 1 kHz, VDD = 3.6 V 0.04 %

O

1.0 VDD − 1.0 V
= 2.5 V ± 100 mV at 217 Hz 55 dB

1.8 MHz

G = 6 dB; G = 12 dB 2.0 mV

POWER SUPPLY

Supply Voltage Range V

DD

Guaranteed from PSRR test 2.5 5.0 V
Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, dc input floating/ground 70 85 dB
PSRR

Supply Current I

SY

V
V
Shutdown Current I

SD

V

GSM

= 100 mV at 217 Hz, inputs are ac grounded,

RIPPLE

C

= 0.01 μF, input referred

IN

VIN = 0 V, no load, VDD = 5.0 V 4.2 mA

= 0 V, no load, VDD = 3.6 V 3.5 mA

IN

= 0 V, no load, VDD = 2.5 V 2.9 mA

IN

SD = GND

GAIN CONTROL

Closed-Loop Gain AV0 GAIN pin = 0 V 6 dB
A
Differential Input Impedance Z

1 GAIN pin = V

V

IN

SD = VDD, SD = GND

DD

210 kΩ

SHUTDOWN CONTROL

Input Voltage High V
Input Voltage Low V
Turn-On Time t
Turn-Off Time t

Output Impedance Z

IH

IL

WU

SD

OUT

ISY ≥ 1 mA 1.2 V

ISY ≤ 300 nA 0.5 V

SD rising edge from GND to V

DD

SD falling edge from VDD to GND

SD = GND

NOISE PERFORMANCE

Output Voltage Noise e

n

Signal-to-Noise Ratio SNR P

VDD = 2.5 V to 5.0 V, f = 20 Hz to 20 kHz, inputs are

ac grounded, sine wave, A

= 1.4 W, RL = 8 Ω 98 dB

OUT

= 6 dB, A weighting

V

1.22 W

1.52 W

590 mW

775 mW

275 mW

345 mW

63 dB

20 nA

12 dB
150 kΩ

30 ms
5 μs
>100 kΩ

35 μV

Rev. A | Page 3 of 16

SSM2301

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings apply at 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage 6 V
Input Voltage V
Common-Mode Input Voltage V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C

DD

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

8-lead, 3 mm × 3 mm LFCSP 62 20.8 °C/W
8-lead MSOP 210 45 °C/W

θ

JA

Unit

JC

ESD CAUTION

Rev. A | Page 4 of 16

SSM2301

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

2GAIN

SSM2301

3IN+

(Not to Scale)

4IN–

PIN 1
INDICAT OR

TOP VIEW

8OUT–

7GND

6VDD

5OUT+

06163-002

SD 1

Figure 2. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

SD

Shutdown Input. Active low digital input.

2 GAIN Gain Selection. Digital input.
3 IN+ Noninverting Input.
4 IN− Inverting Input.
5 OUT+ Noninverting Output.
6 VDD Power Supply.
7 GND Ground.
8 OUT− Inverting Output.

SD 1

GAIN

IN+

IN– 4

SSM2301

2

TOP VIEW

3

(Not to Scale)

OUT–8

7

GND

6

VDD

OUT+5

Figure 3. MSOP Pin Configuration

6163-103

Rev. A | Page 5 of 16

SSM2301

TYPICAL PERFORMANCE CHARACTERISTICS

100

THD + N (%)

0.1

RL = 8Ω, 15µH
GAIN = 6dB

10

1

VDD = 2.5V

VDD = 3.6V

VDD = 5V

100

0.1

THD + N (%)

0.01

0.001

VDD = 5.0V
GAIN = 12dB
R

L

10

1

= 8Ω, 15µH

0.5W
1W

0.25W

0.01

0.0001 10

100

10

1

THD + N (%)

0.1

0.01

0.0001 10

100

10

0.001 0.01 0.1 1

OUTPUT POWER (W)

Figure 4. THD + N vs. Output Power into 8 Ω, A

RL = 8Ω, 15µH
GAIN = 12dB

VDD = 2.5V

VDD = 3.6V

0.001 0.01 0.1 1

OUTPUT POWER (W)

Figure 5. THD + N vs. Output Power into 8 Ω, A

VDD = 5.0V
GAIN = 6dB
R

= 8Ω, 15µH

L

= 6 dB

V

VDD = 5V

= 12 dB

V

0.0001
10 100k

06163-004

Figure 7. THD + N vs. Frequency, V

100

VDD = 3.6V
GAIN = 6dB
R

= 8Ω, 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001

0.0001
10 100k

06163-003

Figure 8. THD + N vs. Frequency, V

100

VDD = 3.6V
GAIN = 12dB
R

= 8Ω, 15µH

L

10

100 1k 10k

FREQUENCY (Hz)

= 5.0 V, AV = 12 dB, RL = 8 Ω

DD

0.5W

0.25W

0.125W

100 1k 10k

FREQUENCY (Hz)

= 3.6 V, AV = 6 dB, RL = 8 Ω

DD

06163-008

6163-009

1

0.1

THD + N (%)

0.01

0.001

0.0001
10 100k

0.5W

100 1k 10k

Figure 6. THD + N vs. Frequency, V

1W

0.25W

FREQUENCY (Hz)

= 5.0 V, AV = 6 dB, RL = 8 Ω

DD

06163-007

Rev. A | Page 6 of 16

1

0.1

THD + N (%)

0.01

0.001

0.0001
10 100k

Figure 9. THD + N vs. Frequency, V

0.5W

0.25W

0.125W

100 1k 10k

FREQUENCY (Hz)

= 3.6 V, AV = 12 dB, RL = 8 Ω

DD

6163-010

SSM2301

100

VDD = 2.5V
GAIN = 6dB
R

= 8Ω, 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001

0.0001
10 100k

100 1k 10k

Figure 10. THD + N vs. Frequency, V

100

VDD = 2.5V
GAIN = 12dB
R

= 8Ω, 15µH

L

10

1

0.1

THD + N (%)

0.01

0.001

0.25W

0.125W

0.075W

FREQUENCY (Hz)

DD

0.25W

0.125W

0.075W

= 2.5 V, AV = 6 dB, RL = 8 Ω

12

10

8

6

4

SHUTDOWN CURRENT (µA)

2

0

000.70.60.50.30.1 0.40.2

6163-011

SHUTDOWN VOLTAGE (V)

VDD = 5.0V

V

= 2.5V

DD

VDD = 3.6V

.8

6163-020

Figure 13. Shutdown Current vs. Shutdown Voltage

1.6

f

= 1kHz
GAIN = 6dB
R

= 8Ω

1.4

L

1.2

1.0

0.8

0.6

OUTPUT PO WER (W)

0.4

0.2

10%

1%

0.0001
10 100k

Figure 11. THD + N vs. Frequency, V

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

SUPPLY CURRENT (mA)

1.0

0.5

0

2.5 5.55.04.54.03.53.0

100 1k 10k

FREQUENCY (Hz)

= 2.5 V, AV = 12 dB, RL = 8 Ω

DD

SUPPLY VOLTAGE (V)

Figure 12. Supply Current vs. Supply Voltage, No Load

0

2.5 5.0

6163-012

Figure 14. Maximum Output Power vs. Supply Voltage, A

1.8

1.6

1.4

1.2

1.0

0.8

0.6

OUTPUT PO WER (W)

0.4

0.2

0

2.5 5.0

6163-019

Figure 15. Maximum Output Power vs. Supply Voltage, A

3.0 3.5 4.0 4.5

SUPPLY VOLTAGE (V)

f

= 1kHz
GAIN = 12dB
R

= 8Ω

L

10%

3.0 3.5 4.0 4.5

SUPPLY VOLTAGE (V)

1%

= 6 dB, RL = 8 Ω,

V

= 12 dB, RL = 8 Ω

V

6163-021

6163-022

Rev. A | Page 7 of 16

SSM2301

100

90

= 2.5V

V

DD

80

70

60

50

40

EFFICIE NCY (%)

30

20

10

0

01

0.2 0.4 0.6 0.8 1.21.0

V

= 3.6V

DD

= 5.0V

V

DD

OUTPUT PO WER (W)

RL = 8Ω, 15µH

.4

6163-025

Figure 16. Efficiency vs. Output Power into 8 Ω

400

RL = 8Ω, 15µH

350

300

= 3.6V

V

250

200

= 2.5V

V

DD

150

SUPPLY CURRENT (mA)

100

50

0

0 0.10.20.30.40.50.60.70.80.91.01.11.21.31.41.5

DD

OUTPUT PO WER (W)

= 5.0V

V

DD

Figure 19. Supply Current vs. Output Power into 8 Ω, One Channel

6163-031

0.20
VDD = 3.6V

= 8Ω, 15µH

R

0.18

L

0.16

0.14

0.12

0.10

0.08

0.06

POWER DISSIPATION (W)

0.04

0.02

0

00

Figure 17. Power Dissipation vs. Output Power into 8 Ω at V

0.30
VDD = 5.0V

= 8Ω, 15µH

R

L

0.25

0.20

0.20.1 0.3 0.4 0.5 0. 6 0.7

OUTPUT PO WER (W)

.8

6163-050

= 3.6 V

DD

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

–70

–80

–90

–100

10 100 1k 10k 100k

Figure 20. Power Supply Rejection Ratio vs. Frequency

0

RL = 8Ω, 33µH
GAIN = 6dB

–10

–20

–30

FREQUENCY (Hz)

6163-033

0.15

0.10

POWER DISSIPATION (W)

0.05

0

01

Figure 18. Power Dissipation vs. Output Power into 8 Ω at V

0.30.1 0.5 0.7 0.9 1.1 1.3 1.40.20.40.60.81.01.2

OUTPUT PO WER (W)

.5

6163-051

= 5.0 V

DD

–40

CMRR (dB)

–50

–60

–70

–80

10 100 1k 10k 100k

Figure 21. Common-Mode Rejection Ratio vs. Frequency

Rev. A | Page 8 of 16

FREQUENCY (Hz)

6163-034

SSM2301

7

6

5

4

SD INPUT

3

2

VOLTAGE (V)

1

0

–1

–2

–10 90

–5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85

OUTPUT

TIME (ms)

6163-035

Figure 22. Turn-On Response

7

6

5

SD INPUT

4

3

2

VOLTAGE (V)

1

0

–1

–2

–20 180

0 20 40 60 80 100 120 140 160

OUTPUT

TIME (ms)

Figure 23. Turn-Off Response

6163-036

Rev. A | Page 9 of 16

SSM2301

TYPICAL APPLICATION CIRCUITS

0.1µF

MODULATOR

OSCILLAT OR

VDD

GND

VBATT

2.5V TO 5. 0V

FET

DRIVER

POP/CLICK

SUPPRESSION

OUT+

OUT–

6163-037

AUDIO IN+

AUDIO IN–

V

DD

SHUTDOWN

10µF

SSM2301

1

0.01µF
IN+

IN–

1

0.01µF
GAIN

SD

NOTES

1

INPUT CAPACIT ORS ARE OPT IONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V

GAIN

CONTROL

BIAS

/2.

DD

Figure 24. Differential Input Configuration, Gain = 12 dB

0.1µF

MODULATOR

VDD

VBATT

2.4V TO 5. 0V

FET

DRIVER

OUT+

OUT–

AUDIO IN

0.01µF

0.01µF

SSM2301

IN+

IN–

GAIN

GAIN

CONTROL

10µF

SHUTDOWN

SD

BIAS

OSCILLAT OR

GND

POP/CLICK

SUPPRESSION

06163-038

Figure 25. Single-Ended Input Configuration, Gain = 6 dB

EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)]

SSM2301

1

0.01µF
R

AUDIO IN+

AUDIO IN–

SHUTDOWN

0.01µF

IN+

R

IN–

1

V

DD

GAIN

SD

NOTES

1

INPUT CAPACIT ORS ARE OPT IONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V

GAIN

CONTROL

Figure 26. Differential Input Configuration, User-Adjustable Gain

10µF

BIAS

/2.

DD

0.1µF

MODULATOR

OSCILLAT OR

VDD

GND

VBATT

2.4V TO 5. 0V

FET

DRIVER

POP/CLICK

SUPPRESSION

OUT+

OUT–

06163-039

Rev. A | Page 10 of 16

SSM2301

EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)]

SSM2301

0.01µF
R

AUDIO IN

0.01µF

SHUTDOWN

IN+

R

IN–

V

DD

GAIN

SD

GAIN

CONTROL

10µF

BIAS

0.1µF

MODULATOR

OSCILLAT OR

VDD

GND

VBATT

2.4V TO 5. 0V

FET

DRIVER

POP/CLICK

SUPPRESSION

OUT+

OUT–

06163-040

Figure 27. Single-Ended Input Configuration, User-Adjustable Gain

EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)]

SSM2301

1

0.01µF
R

AUDIO IN+

AUDIO IN–

0.01µF

IN+

R

IN–

1

GAIN

GAIN

CONTROL

10µF

0.1µF

MODULATOR

VDD

VBATT

2.4V TO 5. 0V

FET

DRIVER

OUT+

OUT–

SHUTDOWN

SD

NOTES

1

INPUT CAPACITORS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V

BIAS

/2.

DD

OSCILLAT OR

GND

POP/CLICK

SUPPRESSION

06163-041

Figure 28. Differential Input Configuration, User-Adjustable Gain

EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)]

SSM2301

0.01µF
R

AUDIO IN

0.01µF

SHUTDOWN

IN+

IN–

R

GAIN

SD

GAIN

CONTROL

Figure 29. Single-Ended Input Configuration, User-Adjustable Gain

10µF

BIAS

0.1µF

MODULATOR

OSCILLAT OR

VDD

GND

VBATT

2.4V TO 5. 0V

FET

DRIVER

POP/CLICK

SUPPRESSION

OUT+

OUT–

06163-042

Rev. A | Page 11 of 16

SSM2301

APPLICATIONS INFORMATION

OVERVIEW

The SSM2301 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces external component count,
conserving board space and, thus, reducing system cost. The
SSM2301 does not require an output filter but, instead, relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square-wave output. While most Class-D ampli­fiers use some variation of pulse-width modulation (PWM), the
SSM2301 uses a Σ-Δ modulation to determine the switching
pattern of the output devices. This provides a number of important
benefits. Σ-Δ modulators do not produce a sharp peak with many
harmonics in the AM frequency band, as pulse-width modulators
often do. Σ-Δ modulation reduces the amplitude of spectral
components at high frequencies, thereby reducing EMI emission
that might otherwise be radiated by speakers and long cable traces.
The SSM2301 also offers protection circuitry for output short­circuit and high temperature conditions. When the fault-inducing
condition is removed, the SSM2301 automatically recovers
without the need for a hard reset.

GAIN SELECTION

Pulling the GAIN pin of the SSM2301 high sets the gain of the
speaker amplifier to 12 dB; pulling it low sets the gain of the
speaker amplifier to 6 dB.

It is possible to adjust the SSM2301 gain by using external resistors
at the input. To set a gain lower than 12 dB, see Figure 26 for
differential input configuration and Figure 27 for single-ended
configuration. For external gain configuration from a fixed 12 dB
gain, use the following formula:

External Gain Settings = 20 log[4/(1 + R/150 kΩ)]

To set a gain lower than 6 dB, see Figure 28 for differential input
configuration and Figure 29 for single-ended configuration. For
external gain configuration from a fixed 6 dB gain, use the
following formula:

External Gain Settings = 20 log[2/(1 + R/150 kΩ)]

POP-AND-CLICK SUPPRESSION

Voltage transients at the output of audio amplifiers may occur
when shutdown is activated or deactivated. Voltage transients
as low as 10 mV can be heard as an audio pop in the speaker.
Clicks and pops can also be classified as undesirable audible
transients generated by the amplifier system and, therefore,
as not coming from the system input signal. Such transients may
be generated when the amplifier system changes its operating
mode. For example, the following can be sources of audible
transients: system power-up/power-down, mute/unmute, input
source change, and sample rate change. The SSM2301 has a pop­and-click suppression architecture that reduces these output
transients, resulting in noiseless activation and deactivation.

LAYOUT

As output power continues to increase, care must be taken to
lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Make track widths at least 200 mil for every inch of track length
for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to
further reduce IR drops and inductance.

Poor layout increases voltage drops, consequently affecting
efficiency. Use large traces for the power supply inputs and
amplifier outputs to minimize losses due to parasitic trace
resistance. Proper grounding guidelines help improve audio
performance, minimize crosstalk between channels, and prevent
switching noise from coupling into the audio signal. To maintain
high output swing and high peak output power, PCB traces that
connect the output pins to the load and supply pins should be
as wide as possible to maintain the minimum trace resistances.

It is also recommended that a large-area ground plane be used for
minimum impedances. Good PCB layouts also isolate critical
analog paths from sources of high interference. High frequency
circuits (analog and digital) should be separated from low
frequency circuits. Properly designed multilayer printed circuit
boards can reduce EMI emission and increase immunity to the
RF field by a factor of 10 or more compared with double-sided
boards. A multilayer board allows a complete layer to be used
for the ground plane, whereas the ground plane side of a double­side board is often disrupted with signal crossover. If the system
has separate analog and digital ground and power planes, the
analog ground plane should be underneath the analog power plane,
and, similarly, the digital ground plane should be underneath the
digital power plane. There should be no overlap between analog
and digital ground planes or analog and digital power planes.

INPUT CAPACITOR SELECTION

The SSM2301 does not require input coupling capacitors if the
input signal is biased from 1.0 V to V
are required if the input signal is not biased within this recom­mended input dc common-mode voltage range, if high-pass
filtering is needed (see Figure 24)
source (see Figure 25). If high-pass filtering is needed at the input,
the input capacitor, along with the input resistor of the SSM2301,
forms a high-pass filter whose corner frequency is determined
by the following equation:

= 1/(2π × RIN × CIN)

f

C

The input capacitor can have very important effects on the
circuit performance. Not using input capacitors degrades the
output offset of the amplifier as well as the PSRR performance.

− 1.0 V. Input capacitors

DD

or if using a single-ended

Rev. A | Page 12 of 16

SSM2301

PROPER POWER SUPPLY DECOUPLING

To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. Although the actual switching frequency can
range from 10 kHz to 100 kHz, these spikes can contain frequency
components that extend into the hundreds of megahertz.

The power supply input needs to be decoupled with a good
quality low ESL and low ESR capacitor, usually around 4.7 μF.
This capacitor bypasses low frequency noises to the ground
plane. For high frequency transients noises, use a 0.1 μF
capacitor placed as close as possible to the VDD pin of the
device. Placing the decoupling capacitor as close as possible
to the SSM2301 helps maintain efficient performance.

Rev. A | Page 13 of 16

SSM2301

OUTLINE DIMENSIONS

0.50

0.40

0.30

4

PIN 1
INDICATO

R

1

1.89

1.50

1.74

REF

1.59

PIN 1

INDICATOR

3.00

BSC SQ

TOP

VIEW

2.75

BSC SQ

0.50

BSC

0.60 MAX

8

5

1.60

1.45

1.30

0.90 MAX

0.85 NOM

SEATING

PLANE

12° MAX

0.30

0.23

0.18

0.70 MAX

0.65 TYP

0.05 MAX

0.01 NOM

0.20 REF

Figure 30. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

3 mm × 3 mm Body, Very Thin, Dual Lead

(CP-8-2)

Dimensions shown in millimeters

3.20

3.00

2.80

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

3.20

3.00

2.80

PIN 1

0.95

0.85

0.75

0.15

0.00

COPLANARITY

1

0.65 BSC

0.38

0.22

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 31. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model

SSM2301CPZ-R2

Range

1

−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A1C

Package Description

SSM2301CPZ-REEL1−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A1C
SSM2301CPZ-REEL71−40°C to +85°C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A1C
SSM2301RMZ-R2

1

−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1C
SSM2301RMZ-REEL1−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1C
SSM2301RMZ-REEL71−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A1C
SSM2301-EVALZ

1

Z = RoHS Compliant Part.

1

Evaluation Board with LFCSP Model

Rev. A | Page 14 of 16

Package
Option

Branding

SSM2301

NOTES

Rev. A | Page 15 of 16

SSM2301

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06163-0-10/07(A)

Rev. A | Page 16 of 16