Analog Devices SSM2160 a Datasheet

6-Channel, Serial Input

Master/Balance Volume Controls

SSM2160

FEATURES
Clickless Digitally Controlled Level Adjustment

SSM2160: 6 Channels
7-Bit Master Control Gives 128 Levels of Attenuation
5-Bit Channel Controls Give 32 Levels of Gain
Master/Channel Step Size Set by External Resistors
100 dB Dynamic Range
Automatic Power-On Mute
Excellent Audio Characteristics:

0.01% THD+N

0.001% IMD (SMPTE)

–90 dBu Noise Floor

–80 dB Channel Separation

90 dB SNR
Single-and Dual-Supply Operation

APPLICATIONS
Home Theater Receivers
Surround Sound Decoders
Circle Surround

®

and AC-3® Decoders
DSP Soundfield™ Processors
HDTV and Surround TV Audio Systems
Automotive Surround Sound Systems
Multiple Input Mixer Consoles and Amplifiers

GENERAL DESCRIPTION

The SSM2160 allows digital control of volume of six audio
channels, with a master level control and individual channel
controls. Low distortion VCAs (voltage controlled amplifiers) are
used in the signal path. By using controlled rate-of-change drive
to the VCAs, the “clicking” associated with switched resistive
networks is eliminated in the master control. Each channel is
controlled by a dedicated 5-bit DAC providing 32 levels of gain.
A master 7-bit DAC feeds every control port giving 128 levels of
attenuation. Step sizes are nominally 1 dB and can be changed by
external resistors. Channel balance is maintained over the entire
master control range. Upon power-up, all outputs are automati­cally muted. A 3-wire or 4-wire serial data bus enables interfacing
with most popular microcontrollers. Windows

®

software and an

evaluation board for controlling the SSM2160 are available.

The SSM2160 can be operated from single supplies of +10 V to
+20 V or dual supplies from ±5 V to ±10 V. An on-chip reference
provides the correct analog common voltage for single-supply
applications. The SSM2160 comes in a SOIC package; see the
Ordering Guide for details.

V

REF

CLK

DATA

WRITE

FUNCTIONAL BLOCK DIAGRAM

V+

V–

LD

POWER

SUPPLY AND

REFERENCE

GENERATOR

5-BIT

CHANNEL

DAC

5-BIT

CHANNEL

DAC

5-BIT

CHANNEL

DAC

5-BIT

CHANNEL

DAC

5-BIT

CHANNEL

DAC

5-BIT

CHANNEL

DAC

7-BIT

MASTER

DAC

SHIFT REGISTER

AND
ADDRESS
DECODER

VCA

VCA

VCA

VCA

VCA

VCA

SSM2160

STEP SIZE

ADJUST

CH1 IN

CH1 OUT

CH2 IN

CH2 OUT

CH3 IN

CH3 OUT

CH4 IN

CH4 OUT

CH5 IN

CH5 OUT

CH6 IN

CH6 OUT

CH SET

MSTR SET

MSTR OUT

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

SSM2160–SPECIFICATIONS

(VS = ⴞ6 V, TA = 25ⴗC, AV = 0 dB, f
RL = 10 k⍀, unless otherwise noted.)

AUDIO

= 1 kHz, f

= 250 kHz,

CLOCK

Parameter Symbol Conditions Min Typ Max Unit

AUDIO PERFORMANCE

Noise Floor NFL VIN = GND, BW= 20 kHz, AV = 0 dB
Total Harmonic Distortion + Noise THD+N Second and Third Harmonics Only,

= 0 dBu

V

OUT

2

1

–90 dBu

AV = 0 dB 0.01 0.035 %
Channel Separation Any Channel to Another 80 dB
Dynamic Range NFL to Clip Point 100 dB

ANALOG INPUT

Maximum Level V
Impedance Z

ANALOG OUTPUT

Maximum Level

3

max VS = ±10 V 1.8 V rms

IN

IN

Any Channel 10 kΩ

VS = ±10 V, All Conditions of Master

Attenuation and Channel Gain 1.8 V rms
Impedance Z

OUT

10 Ω

Offset Voltage 20 mV
Minimum Resistive Load R

min 10 kΩ

L

Maximum Capacitive Load CL max 50 pF

MASTER ATTENUATOR ERROR Measured from Best Fit of All Channels

from 0 dB and –127 dB (or Noise Floor)

= 0 dB Channel Gain = 0 dB ±0.5 dB

A

V

= –20 dB Channel Gain = 0 dB ±1.0 dB

A

V

= –40 dB Channel Gain = 0 dB ±2.0 dB

A

V

AV = –60 dB Channel Gain = 0 dB ±2.5 dB

CHANNEL MATCHING ±1.0 dB

CHANNEL GAIN ERROR Master Attenuation = 0 dB

AV = 0 dB ±0.5 dB

= 10 dB ±1.0 dB

A

V

AV = 31 dB ±2.0 dB

MUTE ATTENUATION V

VOLTAGE REFERENCE V

REF

Accuracy Percent of
Output Impedance 5 Ω

= 0 dBu –95 dB

IN

(V +) +(V –)

2

±5%

CONTROL LOGIC

Logic Thresholds

High (1) Re: DGND 2.0 V
Low (0) 0.8 V

Input Current ±1 µA
Clock Frequency 1 1000 kHz
Timing Characteristics See Timing Diagrams

POWER SUPPLIES

Voltage Range

SSM2160 V

S

Single Supply 10 20 V

SSM2160 V+, V– Dual Supply ±5 ±10 V

Supply Current No Load 20 28 mA

NOTES

1

Master = 0 dB; Channel = 0 dB.

2

Input level adjusted accordingly. 0 dBu = 0.775 V rms.

3

For other than ± 10 V supplies, maximum is VS/4.

Specifications subject to change without notice.

REV. A–2–

SSM2160

TIMING CHARACTERISTICS

Timing
Symbol Description Min Typ Max Unit

t

CL

t

CH

t

DS

t

DH

t

CW

t

WC

t

LW

t

WL

t

L

t

W3

NOTES

1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the negative edge.

2. For SPI™ or Microwire™ 3-wire bus operation, tie LD to WRITE and use WRITE pulse to drive both pins. (This generates an automatic internal load signal.)

3. If an idle HI clock is used, tCW and tWL are measured from the final negative transition to the idle state.

4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain/attenuation levels. Refer to the Address/Data Decoding Truth Table.

5. Data must be sent MSB first.

CLK

Input Clock Pulsewidth, Low 200 ns
Input Clock Pulsewidth, High 200 ns
Data Setup Time 50 ns
Data Hold Time 75 ns
Positive CLK Edge to End of Write 100 ns
Write to Clock Setup Time 50 ns
End of Load Pulse to Next Write 50 ns
End of Write to Start of Load 50 ns
Load Pulsewidth 250 ns
Load Pulsewidth (3-Wire Mode) 250 ns

0

1

DATA

WRITE

LD

CLK

DATA

WRITE

LD

1

0

1

0

1

0

1

0

1

0

1

0

1

0

D7 D6 D5 D4 D3 D2 D1 D0

t

CH

t

DS

D7

t

WC

MSB

t

CL

t

DH

t

CW

t

L

t

WL

t

LW

Figure 1. Timing Diagrams

REV. A

–3–

SSM2160

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage

Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

2

(VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V

Single

Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5 V

Operating Temperature Range . . . . . . . . . . . . . . . 0°C to 70°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

Junction Temperature Range . . . . . . . . . . . . . –65°C to +165°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C

ESD Ratings

883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 2.5 kV

PACKAGE THERMAL INFORMATION

Package Type ␪

3

JA

␪

JC

Unit

24-Lead SOIC 71 23 °C/W

NOTES

1

Absolute maximum ratings apply at 25°C, unless otherwise noted.

2

VS is the total supply span from V+ to V–.

3

␪JA is specified for the worst-case conditions for device soldered onto a circuit

board for SOIC packages.

ORDERING GUIDE

PIN CONFIGURATION

24-Lead SOIC

AGND

V

REF

CH1 OUT

CH1 IN

CH3 OUT

CH3 IN

CH5 OUT

CH5 IN

WRITE

LD

V+

10

11

12

V–

1

2

3

4

5

SSM2160

6

TOP VIEW

(Not to Scale)

7

8

9

24

CH SET

23

MSTR OUT

22

MSTR SET

21

CH2 OUT

20

CH2 IN

19

CH4 OUT

18

CH4 IN

17

CH6 OUT

16

CH6 IN

15

DATA

14

CLK

13

DGND

Temperature Package Package

Model Range Description Option

SSM2160S 0°C to 70°C 24-Lead SOIC R-24
SSM2160S-REEL 0°C to 70°C 24-Lead SOIC R-24
EVAL-SSM2160EB Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
SSM2160 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A–4–

SSM2160

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1V+Positive Power Supply. Refer to the Application Information section for details on the power supply.

2 AGND Internal Ground Reference for the Audio Circuitry. When operating the SSM2160 from dual supplies,

AGND should be connected to ground. When operating from a single supply, AGND should be connected
to V

, the internally generated voltage reference. AGND may also be connected to an external

REF

reference. Refer to the Application Information section for more information on the power supply.

3V

REF

4 CH1 OUT Audio Output from Channel 1

5 CH1 IN Audio Input to Channel 1

6 CH3 OUT Audio Output from Channel 3

7 CH3 IN Audio Input to Channel 3

8 CH5 OUT Audio Output from Channel 5

9 CH5 IN Audio Input to Channel 5
10 WRITE A logic low voltage enables the SSM2160 to receive information at the DATA input (Pin 15). A logic

11 LD Loads the Information Retained by WRITE into the SSM2160 at logic low (Figure 1).

12 V– Negative Power Supply. Connect to ground in a single-supply application. Refer to the Application

13 DGND Digital Ground Reference. This pin should always be connected to ground. All digital inputs, including

14 CLK Clock Input. It is positive edge triggered (Figure 1).

15 DATA Channel and master control information flows MSB first into the DATA pin. Refer to the Address/Data

16 CH6 IN Audio Input to Channel 6

17 CH6 OUT Audio Output from Channel 6

18 CH4 IN Audio Input to Channel 4

19 CH4 OUT Audio Output from Channel 4

20 CH2 IN Audio Input to Channel 2

21 CH2 OUT Audio Output from Channel 2

22 MSTR SET Connected to the inverting input of an I-V converting op amp. It is used to generate a master control

23 MSTR OUT Connected to the output of the I-V converting op amp. See MSTR SET description.

24 CH SET The step size of the channel control can be increased by connecting a resistor from CH SET to V+.

V

is the internally generated ground reference for the audio circuitry obtained from a buffered

REF

divider between V+ and V–. In a dual-supply application with the AGND pin connected to ground,

should be left floating. In a single-supply application, V

V

REF

should be connected to AGND. Refer

REF

to the Application Information section for more information on the power supply.

high retains data at their previous settings (Figure 1). Serves as CHIP SELECT.

Information section for details on the power supply.

WRITE, LD, CLK, and DATA are TTL input compatible; drive currents are returned to DGND.

Decoding Truth Table, Figure 7, for information on how to control the VCAs.

voltage from the master control DAC current output. A resistor connected from MSTR OUT to
MSTR SET reduces the step size of the master control. See the Master/Channel Step Sizes section for
more details. A 10 µF capacitor should be connected from MSTR OUT to MSTR SET to eliminate
the zipper noise in the master control.

No connection to CH SET is required if the default value of 1 dB per step is desired. Minimum of 10 Ω
external resistor. See the Master/Channel Step Sizes section for details.

REV. A

–5–