Analog Devices REF191, REF193, REF195, REF196, REF192 Datasheet

Precision Micropower, Low Dropout,

TP
V

S

SLEEP

GND

NC

NC

OUTPUT

TP

1

2

3

4

8

7

6

5

REF19x
SERIES

TOP VIEW

(Not to Scale)

a

FEATURES
Initial Accuracy: ⴞ2 mV max

Temperature Coefficient: 5 ppm/°C max

Low Supply Current: 45 ␮A max
Sleep Mode: 15 ␮A max
Low Dropout Voltage
Load Regulation: 4 ppm/mA
Line Regulation: 4 ppm/V
High Output Current: 30 mA
Short Circuit Protection

APPLICATIONS
Portable Instrumentation
A-to-D and D-to-A Converters
Smart Sensors
Solar Powered Applications
Loop Current Powered Instrumentations

GENERAL DESCRIPTION

REF19x series precision bandgap voltage references use a pat­ented temperature drift curvature correction circuit and laser
trimming of highly stable thin film resistors to achieve a very low
temperature coefficient and a high initial accuracy.

The REF19x series are micropower, Low Dropout Voltage
(LDV) devices providing a stable output voltage from supplies
as low as 100 mV above the output voltage and consuming less

than 45 µA of supply current. In sleep mode, which is enabled

by applying a low TTL or CMOS level to the sleep pin, the
output is turned off and supply current is further reduced to less

than 15 µA.

The REF19x series references are specified over the extended

industrial temperature range (–40°C to +85°C) with typical
performance specifications over –40°C to +125°C for applica-

tions such as automotive.

All electrical grades are available in 8-Lead SOIC; the PDIP and
TSSOP are only available in the lowest electrical grade. Prod­ucts are also available in die form.

Test Pins (TP)

The test pins, Pin 1 and Pin 5, are reserved for in-package
zener-zap. To achieve the highest level of accuracy at the out­put, the zener-zapping technique is used to trim the output
voltage. Since each unit may require a different amount of ad­justment, the resistance value at the test pins will vary widely
from pin-to-pin as well as from part-to-part. The user should
not make any physical nor electrical connections to Pin 1 and
Pin 5.

Voltage References

REF19x Series

PIN CONFIGURATIONS

8-Lead Narrow-Body SO and TSSOP

(S Suffix and RU Suffix)

8-Lead Epoxy DIP (P Suffix)

1

TP
V

SLEEP

GND

NC = NO CONNECT
TP PINS ARE FACTORY TEST POINTS
NO USER CONNECTION

S

REF19x

2

SERIES

TOP VIEW

3

(Not to Scale)

4

Table I

Part Number Nominal Output Voltage (V)

REF191 2.048
REF192 2.50
REF193 3.00
REF194 4.50
REF195 5.00
REF196 3.30
REF198 4.096

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

REF19xGP –40°C to +85°C 8-Lead Plastic DIP

REF19xES
REF19xFS

3

–40°C to +85°C 8-Lead SOIC SO-8

3

–40°C to +85°C 8-Lead SOIC SO-8
REF19xGS –40°C to +85°C 8-Lead SOIC SO-8
REF19xGRU –40°C to +85°C 8-Lead TSSOP RU-8
REF19xGBC +25°C DICE

NOTES

1

N = Plastic DIP, SO = Small Outline, RU = Thin Shrink Small Outline.

2

8-Lead plastic DIP only available in “G” grade.

3

REF193 and REF196 are available in “G” grade only.

8

7

6
5

NC

NC

OUTPUT

TP

2

N-8

1

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

REF19x Series

REF191–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = 3.3 V, TA = +25ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY

“E” Grade V

1

I

O

= 0 mA 2.046 2.048 2.050 V

OUT

“F” Grade 2.043 2.053 V
“G” Grade 2.038 2.058 V

LINE REGULATION

“E” Grade ∆VO/∆V

2

IN

3.0 V ≤ VS ≤ 15 V, I

= 0 mA 2 4 ppm/V

OUT

“F & G” Grades 4 8 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

2

V

LOAD

= 5.0 V, 0 ≤ I

S

≤ 30 mA 4 10 ppm/mA

OUT

“F & G” Grades 6 15 ppm/mA

DROPOUT VOLTAGE V

LONG-TERM STABILITY

3

NOISE VOLTAGE e

NOTES

1

Initial accuracy includes temperature hysteresis effect.

2

Line and load regulation specifications include the effect of self-heating.

3

Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

∆V

S

N

– V

O

O

VS = 3.15 V, I
V

= 3.3 V, I

S

VS = 3.6 V, I

= 2 mA 0.95 V

LOAD

= 10 mA 1.25 V

LOAD

= 30 mA 1.55 V

LOAD

1000 Hours @ +125°C1.2mV

0.1 Hz to 10 Hz 20 µV p-p

(@ V

= 3.3 V, –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

S

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 10 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 5 ppm/°C

OUT

3.0 V ≤ VS ≤ 15 V, I

10 25 ppm/°C

= 0 mA 5 10 ppm/V

OUT

“F & G” Grades 10 20 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 5.0 V, 0 ≤ I

S

≤ 25 mA 5 15 ppm/mA

OUT

“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V

– V

S

O

VS = 3.15 V, I
V

= 3.3 V, I

S

VS = 3.6 V, I

= 2 mA 0.95 V

LOAD

= 10 mA 1.25 V

LOAD

= 25 mA 1.55 V

LOAD

SLEEP PIN

Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I

H

H

L

L

2.4 V

–8 µA

0.8 V

–8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

MAX–TMIN

).

–2–

REV. D

REF191–SPECIFICATIONS

REF19x Series

ELECTRICAL CHARACTERISTICS

(@ V

= 3.3 V, –40ⴗC ≤ TA ≤ +125ⴗC unless otherwise noted)

S

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 ppm/°C

OUT

3.0 V ≤ VS ≤ 15 V, I

10 ppm/°C

= 0 mA 10 ppm/V

OUT

“F & G” Grades 20 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 5.0 V, 0 ≤ I

S

≤ 20 mA 10 ppm/mA

OUT

“F & G” Grades 20 ppm/mA

DROPOUT VOLTAGE V

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

– V

S

MAX–TMIN

O

VS = 3.3 V, I
VS = 3.6 V, I

).

= 10 mA 1.25 V

LOAD

= 20 mA 1.55 V

LOAD

REV. D

–3–

REF19x Series

REF192–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = 3.3 V, TA = +25ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY

“E” Grade V

1

I

O

= 0 mA 2.498 2.500 2.502 V

OUT

“F” Grade 2.495 2.505 V
“G” Grade 2.490 2.510 V

LINE REGULATION

“E” Grade ∆VO/∆V

2

IN

3.0 V ≤ VS ≤ 15 V, I

= 0 mA 2 4 ppm/V

OUT

“F & G” Grades 4 8 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

2

V

LOAD

= 5.0 V, 0 ≤ I

S

≤ 30 mA 4 10 ppm/mA

OUT

“F & G” Grades 6 15 ppm/mA

DROPOUT VOLTAGE V

LONG-TERM STABILITY

3

NOISE VOLTAGE e

NOTES

1

Initial accuracy includes temperature hysteresis effect.

2

Line and load regulation specifications include the effect of self-heating.

3

Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

∆V

S

N

– V

O

O

(@ VS = 3.3 V, T

VS = 3.5 V, I
VS = 3.9 V, I

= 10 mA 1.00 V

LOAD

= 30 mA 1.40 V

LOAD

1000 Hours @ +125°C1.2mV

0.1 Hz to 10 Hz 25 µV p-p

= –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 10 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 5 ppm/°C

OUT

3.0 V ≤ VS ≤ 15 V, I

10 25 ppm/°C

= 0 mA 5 10 ppm/V

OUT

“F & G” Grades 10 20 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 5.0 V, 0 ≤ I

S

≤ 25 mA 5 15 ppm/mA

OUT

“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V

– V

S

O

VS = 3.5 V, I
VS = 4.0 V, I

= 10 mA 1.00 V

LOAD

= 25 mA 1.50 V

LOAD

SLEEP PIN

Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I

H

H

L

L

2.4 V

–8 µA

0.8 V

–8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

MAX–TMIN

).

–4–

REV. D

REF192–SPECIFICATIONS

REF19x Series

ELECTRICAL CHARACTERISTICS

(@ V

= 3.3 V, –40ⴗC ≤ TA ≤ +125ⴗC unless otherwise noted)

S

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 ppm/°C

OUT

3.0 V ≤ VS ≤ 15 V, I

10 ppm/°C

= 0 mA 10 ppm/V

OUT

“F & G” Grades 20 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 5.0 V, 0 ≤ I

S

≤ 20 mA 10 ppm/mA

OUT

“F & G” Grades 20 ppm/mA

DROPOUT VOLTAGE V

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

– V

S

O

MAX–TMIN

VS = 3.5 V, I
VS = 4.0 V, I

).

= 10 mA 1.00 V

LOAD

= 20 mA 1.50 V

LOAD

REF193–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = 3.3 V, TA = +25ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY

“G” Grade V

LINE REGULATION

“G” Grades

LOAD REGULATION

“G” Grade

DROPOUT VOLTAGE V

LONG-TERM STABILITY

NOISE VOLTAGE e

NOTES

1

Initial accuracy includes temperature hysteresis effect.

2

Line and load regulation specifications include the effect of self-heating.

3

Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

1

I

O

2

∆

VO/∆V

IN

2

∆

VO/∆V

LOADVS

– V

S

O

3

∆

V

O

N

= 0 mA 2.990 3.0 3.010 V

OUT

3.3 V, ≤ VS ≤ 15 V, I

= 5.0 V, 0 ≤ I

VS = 3.8 V, I
VS = 4.0 V, I

OUT

= 10 mA 0.80 V

LOAD

= 30 mA 1.00 V

LOAD

= 0 mA 4 8 ppm/V

OUT

≤ 30 mA 6 15 ppm/mA

1000 Hours @ +125°C 1.2 mV

0.1 Hz to 10 Hz 30 µV p-p

REV. D

–5–

REF19x Series

REF193–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = 3.3 V, T

= –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“G” Grade

LINE REGULATION

3

4

“G” Grade ∆VO/∆V

LOAD REGULATION

4

“G” Grade ∆VO/∆V

DROPOUT VOLTAGE V

1, 2

TCV

/°CI

O

IN

LOAD

– V

S

O

= 0 mA 10 25 ppm/°C

OUT

3.3 V ≤ VS ≤ 15 V, I

V

= 5.0 V, 0 ≤ I

S

VS = 3.8 V, I
VS = 4.1 V, I

LOAD

LOAD

= 0 mA 10 20 ppm/V

OUT

≤ 25 mA 10 20 ppm/mA

OUT

= 10 mA 0.80 V
= 30 mA 1.10 V

SLEEP PIN

Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I

H

H

L

L

2.4 V

–8 µA

0.8 V

–8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

MAX–TMIN

).

(@ V

ELECTRICAL CHARACTERISTICS

= 3.3 V, –40ⴗC ≤ TA ≤ +125ⴗC unless otherwise noted)

S

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“G” Grade

LINE REGULATION

3

4

“G” Grade ∆VO/∆V

LOAD REGULATION

4

“G” Grade ∆VO/∆V

DROPOUT VOLTAGE V

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

1, 2

TCV

/°CI

O

IN

LOAD

– V

S

O

MAX–TMIN

= 0 mA 10 ppm/°C

OUT

3.3 V ≤ VS ≤ 15 V, I

V

= 5.0 V, 0 ≤ I

S

VS = 3.8 V, I
VS = 4.1 V, I

).

= 0 mA 20 ppm/V

OUT

≤ 20 mA 10 ppm/mA

OUT

= 10 mA 0.80 V

LOAD

= 20 mA 1.10 V

LOAD

–6–

REV. D

REF194–SPECIFICATIONS

REF19x Series

ELECTRICAL CHARACTERISTICS

(@ VS = 5.0 V, TA = +25ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY

“E” Grade V

1

I

O

= 0 mA 4.498 4.5 4.502 V

OUT

“F” Grade 4.495 4.505 V
“G” Grade 4.490 4.510 V

LINE REGULATION

“E” Grade ∆VO/∆V

2

IN

4.75 V ≤ VS ≤ 15 V, I

= 0 mA 2 4 ppm/V

OUT

“F & G” Grades 4 8 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

2

V

LOAD

= 5.8 V, 0 ≤ I

S

≤ 30 mA 2 4 ppm/mA

OUT

“F & G” Grades 4 8 ppm/mA

DROPOUT VOLTAGE V

LONG-TERM STABILITY

3

NOISE VOLTAGE e

NOTES

1

Initial accuracy includes temperature hysteresis effect.

2

Line and load regulation specifications include the effect of self-heating.

3

Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

∆V

S

N

– V

O

O

VS = 5.00 V, I
VS = 5.8 V, I

= 10 mA 0.50 V

LOAD

= 30 mA 1.30 V

LOAD

1000 Hours @ +125°C2mV

0.1 Hz to 10 Hz 45 µV p-p

(@ VS = 5.0 V, T

= –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 10 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 5 ppm/°C

OUT

4.75 V ≤ VS ≤ 15 V, I

10 25 ppm/°C

= 0 mA 5 10 ppm/V

OUT

“F & G” Grades 10 20 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 5.80 V, 0 ≤ I

S

≤ 25 mA 5 15 ppm/mA

OUT

“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V

S

– V

O

VS = 5.00 V, I
VS = 5.80 V, I

= 10 mA 0.5 V

LOAD

= 25 mA 1.30 V

LOAD

SLEEP PIN

Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I

H

H

L

L

2.4 V

–8 µA

0.8 V

–8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

MAX–TMIN

).

REV. D

–7–

REF19x Series

REF194–SPECIFICATIONS

(@ V

ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

“F & G” Grades 10 ppm/V

LOAD REGULATION

4

“E” Grade ∆VO/∆V

“F & G” Grades 10 ppm/mA

DROPOUT VOLTAGE V

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

1, 2

/°CI

O

– V

S

O

MAX–TMIN

= 5.0 V, –40ⴗC ≤ TA ≤ +125ⴗC unless otherwise noted)

S

= 0 mA 2 ppm/°C

OUT

IN

LOAD

4.75 V ≤ VS ≤ 15 V, I

V

= 5.80 V, 0 ≤ I

S

VS = 5.10 V, I
VS = 5.95 V, I

).

LOAD

LOAD

= 0 mA 5 ppm/V

OUT

≤ 20 mA 5 ppm/mA

OUT

= 10 mA 0.60 V
= 20 mA 1.45 V

10 ppm/°C

–8–

REV. D

REF195–SPECIFICATIONS

REF19x Series

ELECTRICAL CHARACTERISTICS

(@ VS = 5.10 V, TA = +25ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY

“E” Grade V

1

I

O

= 0 mA 4.998 5.0 5.002 V

OUT

“F” Grade 4.995 5.005 V
“G” Grade 4.990 5.010 V

LINE REGULATION

“E” Grade ∆VO/∆V

2

IN

5.10 V ≤ VS ≤ 15 V, I

= 0 mA 2 4 ppm/V

OUT

“F & G” Grades 4 8 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

2

V

LOAD

= 6.30 V, 0 ≤ I

S

≤ 30 mA 2 4 ppm/mA

OUT

“F & G” Grades 4 8 ppm/mA

DROPOUT VOLTAGE V

LONG-TERM STABILITY

3

NOISE VOLTAGE e

NOTES

1

Initial accuracy includes temperature hysteresis effect.

2

Line and load regulation specifications include the effect of self-heating.

3

Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

∆V

S

N

– V

O

O

(@ VS = 5.15 V, T

VS = 5.50 V, I
VS = 6.30 V, I

= 10 mA 0.50 V

LOAD

= 30 mA 1.30 V

LOAD

1000 Hours @ +125°C1.2mV

0.1 Hz to 10 Hz 50 µV p-p

= –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 10 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 5 ppm/°C

OUT

5.15 V ≤ VS ≤ 15 V, I

10 25 ppm/°C

= 0 mA 5 10 ppm/V

OUT

“F & G” Grades 10 20 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 6.30 V, 0 ≤ I

S

≤ 25 mA 5 10 ppm/mA

OUT

“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V

S

– V

O

VS = 5.50 V, I
VS = 6.30 V, I

= 10 mA 0.50 V

LOAD

= 25 mA 1.30 V

LOAD

SLEEP PIN

Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I

H

H

L

L

2.4 V

–8 µA

0.8 V

–8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

MAX–TMIN

).

.

REV. D –9–

REF19x Series

REF195–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ V

= +5.20 V, –40ⴗC ≤ TA ≤ +125ⴗC unless otherwise noted)

S

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 ppm/°C

OUT

5.20 V ≤ VS ≤ 15 V, I

10 ppm/°C

= 0 mA 5 ppm/V

OUT

“F & G” Grades 10 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 6.45 V, 0 ≤ I

S

≤ 20 mA 5 ppm/mA

OUT

“F & G” Grades 10 ppm/mA

DROPOUT VOLTAGE V

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

– V

S

O

MAX–TMIN

VS = 5.60 V, I
VS = 6.45 V, I

).

= 10 mA 0.60 V

LOAD

= 20 mA 1.45 V

LOAD

REF196–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = +3.5 V, TA = +25ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY

“G” Grade V

LINE REGULATION

“G” Grades ∆VO/∆V

LOAD REGULATION

“G” Grade ∆VO/∆V

DROPOUT VOLTAGE V

LONG-TERM STABILITY

NOISE VOLTAGE e

NOTES

1

Initial accuracy includes temperature hysteresis effect.

2

Line and load regulation specifications include the effect of self-heating.

3

Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

1

I

O

2

IN

2

LOAD

– V

S

O

3

∆V

O

N

= 0 mA 3.290 3.3 3.310 V

OUT

3.50 V ≤ VS ≤ 15 V, I

V

= 5.0 V, 0 ≤ I

S

VS = 4.1 V, I
VS = 4.3 V, I

OUT

= 10 mA 0.80 V

LOAD

= 30 mA 1.00 V

LOAD

= 0 mA 4 8 ppm/V

OUT

≤ 30 mA 6 15 ppm/mA

1000 Hours @ +125°C1.2mV

0.1 Hz to 10 Hz 33 µV p-p

–10–

REV. D

REF196–SPECIFICATIONS

REF19x Series

ELECTRICAL CHARACTERISTICS

(@ VS = +3.5 V, T

= –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

A

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“G” Grade

LINE REGULATION

3

4

“G” Grade ∆VO/∆V

LOAD REGULATION

4

“G” Grade ∆VO/∆V

DROPOUT VOLTAGE V

1, 2

TCV

/°CI

O

IN

LOAD

– V

S

O

= 0 mA 10 25 ppm/°C

OUT

3.5 V ≤ VS ≤ 15 V, I

V

= 5.0 V, 0 ≤ I

S

VS = 4.1 V, I
VS = 4.3 V, I

LOAD

LOAD

= 0 mA 10 20 ppm/V

OUT

≤ 25 mA 10 20 ppm/mA

OUT

= 10 mA 0.80 V
= 25 mA 1.00 V

SLEEP PIN

Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I

H

H

L

L

2.4 V

–8 µA

0.8 V

–8 µA

SUPPLY CURRENT No Load 45 µA

Sleep Mode No Load 15 µA

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

MAX–TMIN

).

(@ V

ELECTRICAL CHARACTERISTICS

= +3.50 V, –40ⴗC ≤ TA ≤ +125ⴗC unless otherwise noted)

S

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“G” Grade

LINE REGULATION

3

4

“G” Grade ∆VO/∆V

LOAD REGULATION

4

“G” Grade ∆VO/∆V

DROPOUT VOLTAGE V

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

1, 2

TCV

/°CI

O

IN

LOAD

– V

S

O

MAX–TMIN

= 0 mA 10 ppm/°C

OUT

3.50 V ≤ VS ≤ 15 V, I

V

= 5.0 V, 0 ≤ I

S

VS = 4.1 V, I
VS = 4.4 V, I

).

= 0 mA 20 ppm/V

OUT

≤ 20 mA 20 ppm/mA

OUT

= 10 mA 0.80 V

LOAD

= 20 mA 1.10 V

LOAD

REV. D

–11–

REF19x Series

REF198–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = 5.0 V, TA = +25ⴗC unless otherwise noted)

Parameter Symbol Condition Min Typ Max Units

INITIAL ACCURACY

“E” Grade V

1

I

O

= 0 mA 4.094 4.096 4.098 V

OUT

“F” Grade 4.091 4.101 V
“G” Grade 4.086 4.106 V

LINE REGULATION

“E” Grade ∆VO/∆V

2

IN

4.5 V ≤ VS ≤ 15 V, I

= 0 mA 2 4 ppm/V

OUT

“F & G” Grades 4 8 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

2

V

LOAD

= 5.4 V, 0 ≤ I

S

≤ 30 mA 2 4 ppm/mA

OUT

“F & G” Grades 4 8 ppm/mA

DROPOUT VOLTAGE V

LONG-TERM STABILITY

3

NOISE VOLTAGE e

NOTES

1

Initial accuracy includes temperature hysteresis effect.

2

Line and load regulation specifications include the effect of self-heating.

3

Long-term drift is guaranteed by 1000 hours life test performed on three independent wafer lots at +125 °C, with an LTPD of 1.3.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

∆V

S

N

– V

O

O

VS = 4.6 V, I
VS = 5.4 V, I

= 10 mA 0.50 V

LOAD

= 30 mA 1.30 V

LOAD

1000 Hours @ +125°C1.2mV

0.1 Hz to 10 Hz 40 µV p-p

(@ V

= +5.0 V, –40ⴗC ≤ TA ≤ +85ⴗC unless otherwise noted)

S

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 10 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 5 ppm/°C

OUT

4.5 V ≤ VS ≤ 15 V, I

10 25 ppm/°C

= 0 mA 5 10 ppm/V

OUT

“F & G” Grades 10 20 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 5.4 V, 0 ≤ I

S

≤ 25 mA 5 10 ppm/mA

OUT

“F & G” Grades 10 20 ppm/mA

DROPOUT VOLTAGE V

– V

S

O

VS = 4.6 V, I
VS = 5.4 V, I

= 10 mA 0.50 V

LOAD

= 25 mA 1.30 V

LOAD

SLEEP PIN

Logic High Input Voltage V
Logic High Input Current I
Logic Low Input Voltage V
Logic Low Input Current I

SUPPLY CURRENT No Load 45 µA

.

Sleep Mode No Load 15 µA

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

H

H

L

L

MAX–TMIN

).

2.4 V

–8 µA

0.8 V

–8 µA

–12–

REV. D

REF198–SPECIFICATIONS

REF19x Series

ELECTRICAL CHARACTERISTICS

(@ V

= +5.0 V, –40ⴗC ≤ TA ≤ +125ⴗC unless otherwise noted)

S

Parameter Symbol Condition Min Typ Max Units

TEMPERATURE COEFFICIENT

“E” Grade TCV

“F” Grade 5 ppm/°C

“G” Grade

LINE REGULATION

3

4

“E” Grade ∆VO/∆V

1, 2

/°CI

O

IN

= 0 mA 2 ppm/°C

OUT

4.5 V ≤ VS ≤ 15 V, I

10 ppm/°C

= 0 mA 5 ppm/V

OUT

“F & G” Grades 10 ppm/V

LOAD REGULATION

“E” Grade ∆VO/∆V

4

V

LOAD

= 5.6 V, 0 ≤ I

S

≤ 20 mA 5 ppm/mA

OUT

“F & G” Grades 10 ppm/mA

DROPOUT VOLTAGE V

NOTES

1

For proper operation, a 1 µF capacitor is required between the output pin and the GND pin of the device.

2

TCV

is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ °C.

O

3

Guaranteed by characterization.

4

Line and load regulation specifications include the effect of self-heating.

Specifications subject to change without notice.

TCVO = (V max–V min)/VO (T

S

– V

O

MAX–TMIN

VS = 4.7 V, I
VS = 5.6 V, I

).

= 10 mA 0.60 V

LOAD

= 20 mA 1.50 V

LOAD

REV. D –13–

REF19x Series

WAFER TEST LIMITS

(@ I

= 0 mA, T

LOAD

= +25°C unless otherwise noted)

A

Parameter Symbol Condition Limits Units

INITIAL ACCURACY

REF191 V

O

2.043/2.053 V
REF192 2.495/2.505 V
REF193 2.990/3.010 V
REF194 4.495/4.505 V
REF195 4.995/5.005 V
REF196 3.290/3.310 V
REF198 4.091/4.101 V

LINE REGULATION ∆VO/∆V
LOAD REGULATION ∆VO/∆I

DROPOUT VOLTAGE V

– V+ I

O

LOAD

(VO + 0.5 V) < VIN < 15 V, I

IN

0 mA < I

LOAD

I

LOAD

LOAD

= 10 mA 1.25 V
= 30 mA 1.55 V

= 0 mA 15 ppm/V

OUT

< 30 mA, VIN = (VO + 1.3 V) 15 ppm/mA

SLEEP MODE INPUT

Logic Input High V
Logic Input Low V

SUPPLY CURRENT V

IH

IL

= 15 V No Load 45 µA

IN

2.4 V

0.8 V

Sleep Mode No Load 15 µA

NOTE

For proper operation, a 1 µF capacitor is required between the output pins and the GND pin of the REF19x. Electrical tests and wafer probe to the limits shown. Due

to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications
based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V

Output to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

Output to GND Short-Circuit Duration . . . . . . . . . . Indefinite

1

+ 0.3 V

S

DICE CHARACTERISTICS

OUTPUT

6

OUTPUT

Storage Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

REF19x . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

Package Type ␪

8-Lead Plastic DIP (P) 103 43 °C/W
8-Lead SOIC (S) 158 43 °C/W
8-Lead TSSOP 240 43 °C/W

NOTES

1

Absolute maximum rating applies to both DICE and packaged parts, unless

otherwise noted.

2

θJA is specified for worst case conditions, i.e., θ

P-DIP, and θ

is specified for device soldered in circuit board for SOIC package.

JA

2

JA

␪

JC

Units

2

V+

SLEEP

REF19x Die Size 0.041 × 0.057 Inch, 2,337 Sq. Mils
Substrate Is Connected to V+, Number of Transistors:
Bipolar 25, MOSFET4. Process: CBCMOS1

is specified for device in socket for

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the REF19x features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

6

3

WARNING!

4

GND

ESD SENSITIVE DEVICE

–14–

REV. D

5.004

50

0

20

15

5

–15

10

–20

30

20

25

35

40

45

151050–5–10

TC–V

OUT

– ppm/8C

PERCENTAGE OF PARTS – %

–408C TA +858C

BASED ON 600
UNITS, 4 RUNS

40

0

100

10

5

–25–50

20

15

25

30

35

7550250

TEMPERATURE – 8C

SUPPLY CURRENT – mA

NORMAL MODE

SLEEP MODE

–6

0

100

–3

–1

–25

–2

–50

–5

–4

7550250

TEMPERATURE – 8C

SLEEP PIN CURRENT – mA

V

L

V

H

5.003

5.002

5.001

5.000

4.999

OUTPUT VOLTAGE – Volts

4.998

4.997

3 TYPICAL PARTS

5.15V < V

IN

REF19x Series

< 15V

4.996
–25–50

TEMPERATURE – 8C

100

7550250

Figure 1. REF195 Output Voltage vs. Temperature

32

28

+5.15V V

24

20

16

12

LINE REGULATION – ppm/V

8

4

0

50

Figure 2. REF195 Line Regulation vs. I

20

16

O I

S

OUT

15V

I

LOAD

< 25mA

– mA

+858C

–408C

+258C

25201510

30

LOAD

+858C

Figure 4. TC – V

Distribution

OUT

Figure 5. Quiescent Current vs. Temperature

LOAD REGULATION – ppm/mA

REV. D

12

8

4

0

Figure 3. REF195 Load Regulation vs. V

4

6

VIN – Volts

1412108

+258C

–408C

IN

16

Figure 6. SLEEP Pin Current vs. Temperature

–15–

REF19x Series

VIN = 15V

0

10mA

6

REF19x

2
4

1mF

10

100

0%

90

2V

2V

1mA

LOAD

30mA
LOAD

100ms

VIN = 7.0V

REF19x

2

4

6

1mF

10

100

0%

90

1V

2ms

5V

ON

OFF

V

OUT

IL = 1mA

IL = 10mA

VIN = 15V

REF19x

V

OUT

6

2

4

3

1mF

0

–20

–40

–60

–80

RIPPLE REJECTION – dB

–100

–120

Figure 9b. Load Transient Response Measurement Circuit

10 100 1M100k10k1k

FREQUENCY – Hz

Figure 7a. Ripple Rejection vs. Frequency

10mF

V

= +15V

IN

1kV

REF

10mF

2

REF19x

6

4

1mF

10mF

1kV

Figure 7b. Ripple Rejection vs. Frequency
Measurement Circuit

VIN = 7V

4

3

2

– V

O

I

1
0

10 100 10M1M100k10k1k

2

1mF

REF19x

4

200V

6

1mF

Z

FREQUENCY – Hz

VG = 2V p-p

V

= 4.00V

S

Figure 8. Output Impedance vs. Frequency

Figure 10a. Power ON Response Time

OUTPUT

Figure 10b. Power ON Response Time Measurement
Circuit

Figure 11a. Sleep Response Time

OFF

ON

5V

100

90

10

0%

20mV

Figure 9a. Load Transient Response

100ms

Figure 11b. Sleep Response Time Measurement Circuit

–16–

REV. D

35

0

0.9

15

5

0.1

10

0

30

20

25

0.80.70.60.50.40.30.2

REF195 DROPOUT VOLTAGE – V

LOAD CURRENT – mA

5V

NC
NC

V

IN

SLEEP

1
2
3
4

8
7
6
5

NC

NC

1mF
TANT

OUTPUT

0.1mF10mF

0.1mF

REF19x

100

90

10

0%

200mV 200ms

Figure 12. Line Transient Response

REF19x Series

Figure 13. Dropout Voltage vs. Load Current

APPLICATIONS SECTION
Output Short Circuit Behavior

The REF19x family of devices is totally protected from damage
due to accidental output shorts to GND or to V+. In the event
of an accidental short circuit condition, the reference device will

shutdown and limit its supply current to 100 µA.

Device Power Dissipation Considerations

The REF19x family of references is capable of delivering load
currents to 30 mA with an input voltage that ranges from 3.3 V
to 15 V. When these devices are used in applications with large
input voltages, care should be exercised to avoid exceeding these
devices’ maximum internal power dissipation. Exceeding the
published specifications for maximum power dissipation or
junction temperature could result in premature device failure.
The following formula should be used to calculate a device’s
maximum junction temperature or dissipation:

In this equation, TJ and TA are the junction and ambient tem­peratures, respectively, P

θ

JA

REV. D

+V

V

OUT

SHUTDOWN

GND

Figure 14. Simplified Schematic

TJ–T

P

=

D

is the device power dissipation and

is the device package thermal resistance.

D

A

θ

JA

Output Voltage Bypassing

For stable operation, low dropout voltage regulators and refer­ences, in general, require a bypass capacitor connected from
their V

pins to their GND pins. Although the REF19x

OUT

family of references is capable of stable operation with capacitive

loads exceeding 100 µF, a 1 µF capacitor is sufficient to guaran-
tee rated performance. The addition of a 0.1 µF ceramic ca-

pacitor in parallel with the bypass capacitor will improve load
current transient performance. For best line voltage transient
performance, it is recommended that the voltage inputs of these

devices be bypassed with a 10 µF electrolytic capacitor in paral-
lel with a 0.1 µF ceramic capacitor.

Sleep Mode Operation

All REF19x devices include a sleep capability that is TTL/CMOS
level compatible. Internal to the REF19x at the SLEEP pin, a
pull-up current source to V

is connected. This permits the

IN

SLEEP pin to be driven from an open collector/drain driver.
A logic LOW or a zero volt condition on the SLEEP pin is re­quired to turn the output stage OFF. During sleep, the output
of the references becomes a high impedance state where its
potential would then be determined by external circuitry. If the
sleep feature is not used, it is recommended that the SLEEP pin
be connected to V

(Pin 2).

IN

Basic Voltage Reference Connections

The circuit in Figure 15 illustrates the basic configuration for

the REF19x family of references. Note the 10 µF/0.1 µF bypass
network on the input and the 1 µF/0.1 µF bypass network on the

output. It is recommended that no connections be made to
Pins 1, 5, 7 and 8. If the sleep feature is not required, Pin 3
should be connected to V

.

IN

Figure 15. Basic Voltage Reference Configuration

–17–

REF19x Series

Membrane Switch Controlled Power Supply

With output load currents in the tens of mA, the REF19x family
of references can operate as a low dropout power supply in
hand-held instrument applications. In the circuit shown in
Figure 16, a membrane ON/OFF switch is used to control the
operation of the reference. During an initial power-on condi-

tion, the SLEEP pin is held to GND by the 10 kΩ resistor.

Recall that this condition disables (read: three-state) the
REF19x output. When the membrane ON switch is pressed,
the SLEEP pin is momentarily pulled to V

, enabling the

IN

REF19x output. At this point, current through the 10 kΩ is

reduced and the internal current source connected to the
SLEEP pin takes control. Pin 3 assumes and remains at the
same potential as V

. When the membrane OFF switch is

IN

pressed, the SLEEP pin is momentarily connected to GND,
which once again disables the REF19x output.

NC

8

NC

7

OUTPUT

6
5

NC

1mF
TANT

ON

OFF

V

1kV

5%

1

IN

NC

2
3
4

REF19x

10kV

Figure 16. Membrane Switch Controlled Power Supply

Current-Boosted References with Current Limiting

While the 30 mA rated output current of the REF19x series is
higher than typical of other reference ICs, it can be boosted to
higher levels if desired, with the addition of a simple external
PNP transistor, as shown in Figure 17. Full time current limit­ing is used for protection of the pass transistor against shorts.

+VS = 6 TO 9V

(SEE TEXT)

100mF/25V

V

COMMON

R4
2V

Q2

2N3906

C2

D1

C

1N4148

(SEE TEXT
ON SLEEP)

V

S

U1

REF196

(SEE TABLE)

R1
1kV

R2

1.5kV

1.82kV

Q1

TIP32A

(SEE TEXT)

C3

0.1mF

(TANTALUM)

R3

S

C1

10mF/25V

S

F

REF192
REF193
REF196
REF194
REF195

F

OUTPUT TABLE

V

U1

OUT

2.5

3.0

3.3

4.5

5.0

+V

OUT

3.3V
@ 150mA

R1

V

OUT

COMMON

(V)

In this circuit, the power supply current of reference U1 flowing
through R1–R2 develops a base drive for Q1, whose collector
provides the bulk of the output current. With a typical gain of
100 in Q1 for 100 mA–200 mA loads, U1 is never required to
furnish more than a few mA, so this factor minimizes tempera­ture related drift. Short circuit protection is provided by Q2,
which clamps drive to Q1 at about 300 mA of load current with
values as shown. With this separation of control and power
functions, dc stability is optimum, allowing best advantage use
of premium grade REF19x devices for U1. Of course, load
management should still be exercised. A short, heavy, low DCR
(DC Resistance) conductor should be used from U1–6 to the

sense point “S,” where the collector of Q1 connects to the

V

OUT

load, point “F.”

Because of the current limiting configuration, the dropout volt­age circuit is raised about 1.1 V over that of the REF19x de­vices, due to the V

of Q1 and the drop across current sense

BE

resistor R4. However, overall dropout is typically still low
enough to allow operation of a 5 V to 3.3 V regulator/reference
using the REF196 for U1 as noted, with a V

as low as 4.5 V

S

and a load current of 150 mA.

The requirement for a heat sink on Q1 depends on the maxi­mum input voltage and short circuit current. With V

= 5 V

S

and a 300 mA current limit, the worst case dissipation of Q1 is

1.5 W, less than the TO-220 package 2 W limit. However, if
smaller TO-39 or TO-5 packaged devices such as the 2N4033
are used, the current limit should be reduced to keep maximum
dissipation below the package rating. This is accomplished by
simply raising R 4.

A tantalum output capacitor is used at C1 for its low ESR
(Equivalent Series Resistance), and the higher value is required
for stability. Capacitor C2 provides input bypassing and can be
an ordinary electrolytic.

Shutdown control of the booster stage is shown as an option,
and when used some cautions are in order. Because of the
additional active devices in the V

line to U1, direct drive to

S

Pin 3 does not work as with an unbuffered REF19x device. To
enable shutdown control, the connection to U1-2 is broken at
the “X,” and diode D1 then allows a CMOS control source V

C

to drive U1-3 for ON-OFF operation. Startup from shutdown is
not as clean under heavy load as it is in basic REF19x series and
can require several milliseconds under load. Nevertheless, it is
still effective and can fully control 150 mA loads. When shutdown
control is used, heavy capacitive loads should be minimized.

Figure 17. A Boosted 3.3 V Reference with Current
Limiting

–18–

REV. D

REF19x Series

U2

REF19x

(SEE TABLE)

R1

3.9kV

(SEE TEXT)

C1

0.1mF

+V

S

VS > V

OUT2

+0.15V

V

IN

COMMON

V

OUT

COMMON

OUTPUT TABLE

U1/U2

REF192/REF192
REF192/REF194
REF192/REF195

V

OUT1

(V)

2.5

2.5

2.5

V

OUT2

(V)

5.0

7.0

7.5

+V

OUT2

VO (U2)

C2
1mF

C3

0.1mF
+V

OUT1

VO (U1)

C4
1mF

U1

REF19x

(SEE TABLE)

A Negative Precision Reference without Precision Resistors

In many current-output CMOS DAC applications, where the
output signal voltage must be of the same polarity as the
reference voltage, it is often required to reconfigure a cur­rent-switching DAC into a voltage-switching DAC through the
use of a 1.25 V reference, an op amp and a pair of resistors.
Using a current-switching DAC directly requires an additional
operational amplifier at the output to reinvert the signal. A
negative voltage reference is then desirable from the point that
an additional operational amplifier is not required for either
reinversion (current-switching mode) or amplification (voltage
switching mode) of the DAC output voltage. In general, any
positive voltage reference can be converted into a negative volt­age reference through the use of an operational amplifier and a
pair of matched resistors in an inverting configuration. The
disadvantage to that approach is that the largest single source of
error in the circuit is the relative matching of the resistors used.

The circuit illustrated in Figure 18 avoids the need for tightly
matched resistors with the use of an active integrator circuit. In
this circuit, the output of the voltage reference provides the
input drive for the integrator. The integrator, to maintain cir­cuit equilibrium, adjusts its output to establish the proper rela­tionship between the reference’s V

and GND. Thus, any

OUT

desired negative output voltage can be chosen by simply sub­stituting for the appropriate reference IC. The sleep feature is
maintained in the circuit with the simple addition of a PNP

transistor and a 10 kΩ resistor. One caveat with this approach

should be mentioned: although rail-to-rail output amplifiers
work best in the application, these operational amplifiers require
a finite amount (mV) of headroom when required to provide
any load current. The choice for the circuit’s negative supply
should take this issue into account.

V

IN

10kV

SLEEP

TTL/CMOS

10kV

2N3906

SLEEP

REF19x

GND

V

IN

V

REF

100kV

1kV

1mF

1mF

+5V

A1

–5V

A1 = 1/2 OP295,
1/2 OP291

100V

Figure 18. A Negative Precision Voltage Reference
Uses No Precision Resistors

REV. D

Stacking Reference ICs for Arbitrary Outputs

Some applications may require two reference voltage sources
that are a combined sum of standard outputs. The circuit of
Figure 19 shows how this “stacked output” reference can be
implemented.

Figure 19. Stacking Voltage References with the REF19x

Two reference ICs are used, fed from a common unregulated
input, V

. The outputs of the individual ICs are simply con-

S

nected in series as shown, which provides two output voltages,

and V

V

OUT1

is the sum of this voltage and the terminal voltage of U2.

V

OUT2

OUT2

. V

is the terminal voltage of U1, while

OUT1

U1 and U2 are simply chosen for the two voltages that supply
the required outputs (see table). If, for example, both U1 and
U2 are REF192s, the two outputs are 2.5 V and 5.0 V.

While this concept is simple, some cautions are in order. Since
the lower reference circuit must sink a small bias current from

U2 (50 µA–100 µA), plus the base current from the series PNP

output transistor in U2, either the external load of U1 or R1
must provide a path for this current. If the U1 minimum load is
not well defined, resistor R1 should be used, set to a value that

will conservatively pass 600 µA of current with the applicable

across it. Note that the two U1 and U2 reference circuits

V

OUT1

–V

REF

are locally treated as macrocells, each having its own bypasses at
input and output for best stability. Both U1 and U2 in this
circuit can source dc currents up to their full rating. The mini­mum input voltage, V
puts, V

, plus the dropout voltage of U2.

OUT2

, is determined by the sum of the out-

S

A related variation on stacking two three-terminal references is
shown in Figure 19, where U1, a REF192, is stacked with a
two-terminal reference diode such as the AD589. Like the
three-terminal stacked reference above, this circuit provides two
outputs, V

OUT1

and V

, which are the individual terminal

OUT2

voltages of D1 and U1 respectively. Here this is 1.235 and 2.5,
which provides a V

of 3.735 V. When using two-terminal

OUT2

reference diodes such as D1, the rated minimum and maximum
device currents must be observed and the maximum load cur­rent from V
and V

O(U1)

can be no greater than the current set up by R1

OUT1

. In the case with V

equal to 2.5 V, R1 provides

O(U1)

a 500 µA bias to D1, so the maximum load current available at

is 450 µA or less.

V

OUT1

–19–

REF19x Series

U1

REF19x

(SEE TABLE)

C1

0.1mF

+VS = 6V

V

IN

COMMON

V

OUT

COMMON

+V

OUT

C2
1mF

U2

REF19x

(SEE TABLE)

3412

U3B

74HC04

U3A

74HC04

V

C

OUTPUT TABLE

V

OUT

(V)

5.0

3.3

4.5

5.0

V

C

*

HI
LO

HI
LO

U1/U2
REF195/

REF196
REF194/

REF195

* CMOS LOGIC LEVELS

,

+V

S

VS > V

Figure 20. Stacking Voltage References with the REF19x

A Precision Current Source

Many times, in low power applications, the need arises for a
precision current source that can operate on low supply volt­ages. As shown in Figure 21, any one of the devices in the
REF19x family of references can be configured as a precision
current source. The circuit configuration illustrated is a floating
current source with a grounded load. The reference’s output
voltage is bootstrapped across R
rent into the load. With this configuration, circuit precision is
maintained for load currents in the range from the reference’s

supply current (typically, 30 µA) to approximately 30 mA. The

low dropout voltage of these devices maximizes the current
source’s output voltage compliance without excess headroom.

+0.15V

OUT2

V

COMMON

C1

0.1mF

IN

V

V

REF19x

SLEEP

GND

VIN I

I

• RL (MAX) + VSY (MIN)

OUT

V

OUT

= + ISY (REF19x)

OUT

R

SET

V

OUT

>> I

R

SET

AD589

IN

IN

SY

U1

REF192

D1

V

REF

OUT

I

SY

= 5mA

C2
1mF

C3
1mF

R1

P1

I

OUT

R

L

OUT

10-TURN

VO (U1)

VO (D1)

, which sets the output cur-

SET

1mF

ADJUST

E.G. REF195 : V
I
R1 = 953V
P1 = 100V

R1

4.99kV

(SEE TEXT)

R

SET

= 5V

+V

OUT2

3.735V

+V

OUT1

1.235V

V

OUT

COMMON

Figure 21. A Low Dropout, Precision Current Source

Switched Output 5 V/3.3 V Reference

Applications often require digital control of reference voltages,
selecting between one stable voltage and a second. With the
sleep feature inherent to the REF19x series, switched output
reference configurations are easily implemented with relatively
little additional hardware.

The circuit of Figure 22 illustrates the general technique, which
takes advantage of the output “wire-OR” capability of the
REF19x device family. When OFF, a REF19x device is effec­tively an open circuit at the output node with respect to the
power supply. When ON, a REF19x device can source current

up to its current rating, but sink only a few µA (essentially just

the relatively low current of the internal output scaling divider).
As a result, for two devices wired together at their common
outputs, the output voltage is simply that of the ON device.
The OFF state device will draw a small standby current of

15 µA (max), but otherwise will not interfere with operation of

the ON device, which can operate to its full current rating.
Note that the two devices in the circuit conveniently share
both input and output capacitors, and with CMOS logic
drive, it is power efficient.

Using dissimilar REF19x series devices with this configuration
allows logic selection between the U1/U2 specified terminal
voltages. For example, with U1 (a REF195) and U2 (a REF196),
as noted in the table, changing the CMOS compatible V

logic

C

control voltage from HI to LO selects between a nominal output
of 5.000 V and 3.300 V and vice versa. Other REF19x family
units can also be used for U1/U2, with similar operation in a
logic sense, but with outputs as per the individual paired devices
(see table, again). Of course, the exact output voltage tolerance,
drift and overall quality of the reference voltage will be consis­tent with the grade of individual U1 and U2 devices.

The circuit’s governing equations are:

V

IN

I

OUT

V

OUT

R

SET

= I

=

〉〉I

OUT×RL

V

R

OUT

+I

SET

(REF19x)

SY

(max)+V

(REF19x)

SY

(min, REF19x)

SY

–20–

Figure 22. Switched Output Reference

REV. D

REF19x Series

There is one application caveat that should be understood about
this circuit, which comes about due to the wire-OR nature.
Since U1 and U2 can only source current effectively, negative
going output voltage changes, which require the sinking of cur­rent, will necessarily take longer than positive going changes. In
practice, this means that the circuit is quite fast when undergo­ing a transition from 3.3 to 5 V, but the transition from 5 to

3.3 V will take longer. Exactly how much longer will be a func­tion of the load resistance, R

seen at the output and the

L,

typical 1 µF value of C2. In general, a conservative transition

time here will be on the order of several milliseconds for load

resistances in the range of 100␣ Ω–1 kΩ. Note that for highest

accuracy at the new output voltage, several time constants
should be allowed (>7.6 time constants for <1/2 LSB error @
10 bits, for example).

Kelvin Connections

In many portable instrumentation applications where PC board
cost and area go hand-in-hand, circuit interconnects are very
often of dimensionally minimum width. These narrow lines can
cause large voltage drops if the voltage reference is required to
provide load currents to various functions. In fact, a circuit’s

interconnects can exhibit a typical line resistance of 0.45 mΩ/

square (1 oz. Cu, for example). In those applications where
these devices are configured as low dropout voltage regulators,
these wiring voltage drops can become a large source of error.
To circumvent this problem, force and sense connections can be
made to the reference through the use of an operational ampli­fier, as shown in Figure 23. This method provides a means by
which the effects of wiring resistance voltage drops can be elimi­nated. Load currents flowing through wiring resistance produce
an I-R error (I

LOAD

× R

) at the load. However, the Kelvin

WIRE

connection overcomes the problem by including the wiring

resistance within the forcing loop of the op amp. Since the op
amp senses the load voltage, op amp loop control forces the
output to compensate for the wiring error and to produce the
correct voltage at the load. Depending on the reference device
chosen, operational amplifiers that can be used in this applica­tion are the OP295, the OP291 and the OP183/OP283.

SLEEP

V

IN

V

IN

REF19x

V

OUT

GND

1mF

V

2

A1

3

100kV

A1 = 1/2 OP295

IN

R

LW

R

1

1/2 OP292
1/2 OP283

+V

OUT

SENSE

LW

+V

OUT

FORCE

R

L

Figure 23. A Low Dropout, Kelvin Connected Voltage
Reference

A Fail-Safe 5 V Reference

Some critical applications require a reference voltage to be
maintained constant, even with a loss of primary power. The
low standby power of the REF19x series and the switched out­put capability allow a “fail-safe” reference configuration to be
implemented rather easily. This reference maintains a tight
output voltage tolerance for either a primary power source (ac
line derived) or a standby (battery derived) power source, auto­matically switching between the two as the power conditions
change.

The circuit in Figure 24 illustrates the concept, which borrows
from the switched output idea of Figure 21, again using the
REF19x device family output “wire-OR” capability. In this
case, since a constant 5 V reference voltage is desired for all

+V

BAT

+V

, V

V

BAT

S

COMMON

C2

0.1mF

S

R1

1.1MV

R2
100kV

C4

0.1mF

R3

10MV

3

2

R5
100kV

4

7

6

U3

AD820

R6

100V

R4

900kV

Q1
2N3904

C1

0.1mF

U1

REF195

U2

REF195

+5.000V

C3
1mF

V

OUT

COMMON

Figure 24. A Fail-Safe 5 V Reference

REV. D

–21–

REF19x Series

500V

0.1%

57kV

1%

0.1mF

10kV
1%

0.1mF

1/4

OP492

10mF

1mF

REF195

1/4

OP492

1/4

OP492

1/4

OP492

2.21kV

20kV
1%

10kV

1%

20kV

1%

20kV

1%

0.01mF

10mF

100V

OUTPUT

2N2222

20kV

1%

10kV

1%

conditions, two REF195 devices are used for U1 and U2, with
their ON/OFF switching controlled by the presence or absence

. V

of the primary dc supply source, V

S

backup source that supplies power to the load only when V
fails. For normal (VS present) power conditions, V

is a 6 V battery

BAT

sees only

BAT

S

the 15 µA (max) standby current drain of U1 in its OFF state.

In operation, it is assumed that for all conditions either U1 or
U2 is ON and a 5 V reference output is available. With this
voltage constant, a scaled down version is applied to the com­parator IC U3, providing a fixed 0.5 V input to the (–) input for
all power conditions. The R1–R2
the U3 (+) input proportional to V
U1/U2 dependent upon the absolute level of V

divider provides a signal to

, which switches U3 and

S

. Op amp U3 is

S

configured here as a comparator with hysteresis, which provides
for clean, noise free output switching. This hysteresis is impor­tant to eliminate rapid switching at the threshold due to V

S

ripple. Further, the device chosen is the AD820, a rail-rail
output device, which provides HI and LO output states within a
few mV of V
ible drive for U2 for all V

and ground for accurate thresholds and compat-

S

conditions. R3 provides positive

S

feedback for circuit hysteresis, changing the threshold at the (+)
input as a function of U3’s output.

For V

levels lower than the LOWER threshold, U3’s output is

S

low, thus U2 and Q1 are OFF, while U1 is ON. For V

levels

S

higher than the UPPER threshold, the situation reverses, with
U1 OFF and both U2 and Q1 ON. In the interest of battery
power conservation, all of the comparison switching circuitry is
powered from V

and is so arranged that when VS fails the de-

S

fault output comes from U1.

For the R1–R3

values as shown, the LOWER/UPPER V

S

switching thresholds are approximately 5.5 V and 6 V, respec­tively. These can obviously be changed to suit other V

sup-

S

plies, as can the REF19x devices used for U1 and U2, over a
range of 2.5 V to 5 V of output. U3 can operate down to a V

S

of 3.3 V, which is generally compatible with all family devices.

A Low Power, Strain Gage Circuit

As shown in Figure 25, the REF19x family of references can
be used in conjunction with low supply voltage operational
amplifiers, such as the OP492 and the OP283, in a self-con­tained strain gage circuit. In this circuit, the REF195 was used
as the core of this low power, strain gage circuit. Other refer­ences can be easily accommodated by changing circuit element
values. The references play a dual role as the voltage regulator
to provide the supply voltage requirements of the strain gage
and the operational amplifiers as well as a precision voltage
reference for the current source used to stimulate the bridge. A
distinct feature of the circuit is that it can be remotely controlled
ON or OFF by digital means via the SLEEP pin.

–22–

Figure 25. A Low Power, Strain Gage Circuit

REV. D

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP (P Suffix)

(N-8)

0.430 (10.92)

0.348 (8.84)

8

14

PIN 1

0.100

(2.54)

BSC

5

0.280 (7.11)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

0.070 (1.77)

0.045 (1.15)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

8-Lead Narrow Body SO (S Suffix)

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

REF19x Series

C1951d–2–3/99

0.195 (4.95)

0.115 (2.93)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

SEATING

PLANE

0.177 (4.50)

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

8

5

0.2440 (6.20)

41

0.2284 (5.80)

0.0688 (1.75)

0.0532 (1.35)

0.0500
(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0098 (0.25)

0.0075 (0.19)

8-Lead TSSOP (RU Suffix)

(RU-8)

0.122 (3.10)

0.114 (2.90)

8

5

0.169 (4.30)

1

0.0256 (0.65)
BSC

0.0118 (0.30)

0.0075 (0.19)

4

0.256 (6.50)

0.246 (6.25)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

8°
0°

0.0500 (1.27)

0.0160 (0.41)

0.028 (0.70)

0.020 (0.50)

x 45°

PRINTED IN U.S.A.

REV. D

–23–