5 V Precision Voltage
Reference/Temperature Transducer
FEATURES PIN CONFIGURATIONS
5 V output: ±0.3% max
Temperature voltage output: 1.96 mV/°C
Adjustment range: ±3% min
Excellent temperature stability: 8.5 ppm/°C max
Low noise: 15 µV p-p max
Low supply current: 1.4 mA max
Wide input voltage range: 7 V to 40 V
High load-driving capability: 10 mA
No external components
Short-circuit proof
GENERAL DESCRIPTION
The REF02 precision voltage reference provides a stable 5 V
output that can be adjusted over a ±6% range with minimal
effect on temperature stability. Single-supply operation over an
input voltage range of 7 V to 40 V, low current drain of 1 mA,
and excellent temperature stability are achieved with an
improved band gap design. Low cost, low noise, and low power
make the REF02 an excellent choice whenever a stable voltage
reference is required. Applications include DACs and ADCs,
portable instrumentation, and digital voltmeters. The versatility
of the REF02 is enhanced by its use as a monolithic temperature
transducer. For new designs, refer to the ADR02.
OUTPUT RESISTORS
REF02 OPTION R9 R11 R12
Z PACKAGE AND 18kΩ 2kΩ 6.1kΩ
883C PRODUCT
P, S, J PACKAGES 18kΩ 4.5kΩ 15kΩ
C1
R3
R5
Q1
R1
3
TEMP
R2
*SEE OUTPUT RESISTORS
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
R8
Q8
R6
R4
Q4
Q2
Q5
Q6
Q20
R10
Figure 4. Simplified Schematic
V
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
TEMP
GND
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 2. 8-Lead PDIP (P-Suffix), 8-Lead CERDIP (Z-Suffix),
and 8-Lead SOIC (S-Suffix)
NC
V
IN
NC
TEMP
NC
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 3. REF02RC/883 LCC (RC-Suffix)
R7
Q7
Q9
Q3
R14
Q14
Q10
Q12
Q11
≈
1.23V
Q13
Q21
Q17
R13
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
NC
8
NC
1
2
IN
3
NC TRIM
GROUND
4
(CASE)
NC
7
V
6
OUT
5
Figure 1. TO-99 (J-Suffix)
NC
V
IN
4
5
6
7
8
1
REF02
2
TOP VIEW
3
(Not to Scale)
4
NC
REF02
TOP VIEW
(Not to Scale)
9
NC
GND
Q15
Q18
11NC10
TRIM
19NC20NC1NC2NC3
13NC12
Q16
NC
8
7
NC
V
6
OUT
TRIM
5
18
NC
17
NC
16
NC
15
V
14
NC
OUT
R15
Q19
R12*
R9*
R11*
REF02
00375-F-001
00375-F-002
00375-F-003
INPUT
2
OUTPUT
6
TRIM
5
GROUND
4
00375-F-004
REF02
TABLE OF CONTENTS
Specifications..................................................................................... 3
Electrical Specifications ............................................................... 3
Electrical Specifications ............................................................... 4
Electrical Specifications ............................................................... 5
Electrical Specifications ............................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Typical Performance Characteristics............................................. 8
REVISION HISTORY
2/05—Rev. F to Rev. G
Changes to Specifications................................................................ 3
Change to Outline Dimensions.................................................... 13
7/04—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Simplified Schematic................................................... 1
Changes to Specifications................................................................ 3
Changes to Specifications................................................................ 4
Changes to Specifications................................................................ 5
Changes to Specifications................................................................ 6
Changes to Figure 18...................................................................... 10
Changes to Ordering Guide.......................................................... 15
3/04—Rev. D to Rev. E.
Changes to Features.......................................................................... 1
Changes to Specifications................................................................ 2
Changes to Ordering Guide............................................................ 4
Replaced TPCs 3 and 4 .................................................................... 5
Added Temperature Monitoring section ...................................... 7
Updated Figure 5 ............................................................................. 7
Output Adjustment ........................................................................ 10
Temperature Monitoring........................................................... 10
Reference Stack with Excellent Line Regulation.................... 11
Precision Current Source .......................................................... 11
Supply Bypassing ........................................................................ 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 15
Deleted Table I ...................................................................................7
Updated Figure 6 ..............................................................................7
10/03—Rev. C to Rev. D.
Updated TPCs..................................................................... Universal
Changes to Features .........................................................................1
Changes to Electrical Specifications ..............................................2
Change to Absolute Maximum Ratings .........................................4
Changes to Ordering Guide.............................................................4
Deleted Typical Electrical Characteristics table ........................... 4
Deleted Wafer Test Limits ................................................................4
Deleted Figure 1.................................................................................4
10/02—Rev. B to Rev. C.
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Simplified Schematic....................................................1
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings .......................................5
Changes to Package Type ................................................................5
Changes to Ordering Guide.............................................................5
Updated to Outline Dimensions .................................................. 11
Rev. G | Page 2 of 16
REF02
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
@ VIN = 15 V, TA = 25°C, unless otherwise noted.
Table 1.
REF02A/REF02E REF02/REF02H
Parameter Symbol Conditions
Min Typ Max Min Typ Max
Output Voltage VO IL = 0 mA 4.985 5.000 5.015 4.975 5.000 5.025 V
Output Adjustment Range ∆V
RP = 10 kΩ ±3 ±6 ±3 ±6 %
TRIM
Output Voltage Noise1 en p-p 0.1 Hz to 10 Hz
P, Z, and S Packages 15 15 µV p-p
J Package 20 20 µV p-p
883 Parts 10 15 10 15 µV p-p
Line Regulation
Load Regulation2 I
Turn-On Settling Time1 t
2
V
To ±0.1% of Final Value 5 5 µs
ON
= 8 V to 40 V 0.006 0.010 0.006 0.010 %/V
IN
= 0 mA to 10 mA 0.005 0.010 0.006 0.010 %/mA
L
Quiescent Supply Current ISY No Load 1.0 1.4 1.0 1.4 mA
Load Current IL 10 10 mA
Sink Current3 IS −0.3 –0.5 –0.3 –0.5 mA
Short-Circuit Current ISC VO = 0 30 30 mA
Temperature Voltage Output
Z Package and 883C Product V
P, S, and J Packages V
4
T
T
630 630 mV
550 550 mV
1
Guaranteed by design.
2
Line and load regulation specifications include the effect of self-heating.
3
During sink current test, the device meets the output voltage specified.
4
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
Unit
Rev. G | Page 3 of 16
REF02
ELECTRICAL SPECIFICATIONS
@ V = 15 V, −55°C ≤ T ≤ +125°C for REF02A and REF02, 0°C ≤ T ≤ 70°C for REF02E and REF02H, I
IN A A L
unless otherwise noted.
Table 2.
REF02A/REF02E REF02/REF02H
Parameter Symbol Conditions
Output Voltage Change
with Temperature
Output Voltage Temperature
Coefficient
1, 2
3
Change in VO Temperature Coefficient
∆VOT
TCVO 3 8.5 10 25 ppm/°C
R
0°C ≤ TA ≤ 70°C 0.02 0.06 0.07 0.17 %
−55°C ≤ TA ≤ +125°C 0.06 0.15 0.18 0.45 %
= 10 kΩ 0.7 0.7 ppm/%
P
Min Typ Max Min Typ Max
with Output Adjustment
Line Regulation
= 8 V to 40 V4
V
IN
Load Regulation
= 0 mA to 8 mA4
I
L
Temperature Voltage Output
Temperature Coefficient
5
Z Package and 883C Product
P, S, and J Packages
TCVT
2.10 2.10 mV/°C
1.96 1.96 mV/°C
0°C ≤ TA ≤ 70°C 0.007 0.012 0.007 0.012 %/V
−55°C ≤ TA ≤ +125°C
0°C ≤ TA ≤ 70°C 0.006 0.010 0.007 0.012 %/mA
−55°C ≤ T
≤ +125°C
A
0.009 0.015
0.007 0.012
1
∆VOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed
as a percentage of 5 V.
−
VV
MIN
MAX
=∆
V
OT
2
∆VOT specification applies trimmed to 5000 V or untrimmed.
3
TCVO is defined as ∆VOT divided by the temperature range, i.e.,
TCV
O
4
Line and load regulation specifications include the effect of self-heating.
5
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
V
V
∆
OT
=
C
°
70
1005×
= 0 mA,
Unit
0.009 0.015 %/V
0.009 0.015 %/mA
Rev. G | Page 4 of 16
REF02
ELECTRICAL SPECIFICATIONS
@ VIN = 15 V, TA = 25°C, unless otherwise noted.
Table 3.
REF02C REF02D
Parameter Symbol Conditions
Min Typ Max Min Typ Max
Output Voltage VO IL = 0 mA 4.950 5.000 5.050 4.900 5.000 5.100 V
Output Adjustment Range ∆V
RP = 10 kΩ ±2.7 ±6.0 ±2.0 ±6.0 %
TRIM
Output Voltage Noise1 en p-p 0.1 Hz to 10 Hz
P, Z, and S Packages 15 µV p-p
J Package 20 15 µV p-p
883 Parts 12 18 20 µV p-p
Line Regulation
2
V
= 8 V to 40 V 0.009 0.015 0.010 0.04 %/V
IN
IL = 0 mA to 8 mA 0.006 0.015 %/mA Load Regulation2
I
= 0 mA to 4 mA 0.015 0.04 %/mA
L
Turn-On Settling Time1 t
To ±0.1% of Final Value 5 5 µs
ON
Quiescent Supply Current ISY No Load 1.0 1.6 1.0 2.0 mA
Load Current IL 8 8 mA
Sink Current3 IS −0.3 −0.5 −0.3 −0.5 mA
Short-Circuit Current ISC VO = 0 30 30 mA
Temperature Voltage Output
Z Package and 883C Product V
P, S, and J Packages V
4
T
T
630 630 mV
550 550 mV
1
Guaranteed by design.
2
Line and load regulation specifications include the effect of self-heating.
3
During sink current test the device meets the output voltage specified.
4
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
Unit
Rev. G | Page 5 of 16
REF02
ELECTRICAL SPECIFICATIONS
@ V = 15 V, I
IN L
otherwise noted.
Table 4.
Parameter Symbol Conditions
Output Voltage Change
with Temperature
Output Voltage3
Temperature Coefficient TCVO 20 65 70 250 ppm/°C
Change in VO Temperature
Coefficient with Output Adjustment RP = 10 kΩ 0.7 0.7 ppm/%
Line Regulation4 VIN = 8 V to 40 V 0.011 0.018 0.012 0.05 %/V
Load Regulation4 I
Temperature Voltage Output
Temperature Coefficient5 TCVT
Z Package and 883C Product 2.10 2.10 mV/°C
P, S, and J Packages 1.96 1.96 mV/°C
1
∆VOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed
as a percentage of 5 V:
V
2
∆VOT specification applies trimmed to 5000 V or untrimmed.
3
TCVO is defined as ∆VOT divided by the temperature range, i.e.,
TCV
4
Line and load regulation specifications include the effect of self-heating.
5
Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
= 0 mA, 0°C ≤ T ≤ 70°C for REF02CJ, REF02CZ, REF02DP, and −40°C ≤ T
1, 2
−
VV
MIN
MAX
=∆
OT
=
O
V
V
∆
OT
70
C
°
A A
∆V
OT
1005×
0.14 0.45 0.49 1.7 %
= 0 mA to 5 mA 0.008 0.018 0.016 0.05 %/mA
L
≤ +85°C for REF02CP and REF02CS, unless
REF02C REF02D
Min Typ Max Min Typ Max
Unit
Rev. G | Page 6 of 16
REF02
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Input Voltage 40 V
Output Short-Circuit Duration
to Ground or V
IN
Indefinite
Storage Temperature
J, RC, and Z Packages –65°C to +150°C
P Package –65°C to +125°C
Operating Temperature Range
REF02A, REF02J, REF02RC –55°C to +125°C
REF02CJ, REF02CZ 0°C to 70°C
REF02CP, REF02CS, REF02E, and REF02H –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) 300°C
Absolute maximum ratings apply to both DICE packaged parts,
unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
Table 6. Package Thermal Resistance
Package Type θ
*
JA
θ
JC
Unit
TO-99 (J) 170 24 °C/W
8-Lead CERDIP (Z) 162 26 °C/W
8-Lead PDIP (P) 110 50 °C/W
20-Terminal Ceramic LCC (RC) 120 40 °C/W
8-Lead SOIC (S) 160 44 °C/W
*θJA is specified for worst-case mounting conditions, i.e., θJA is specified for
device in socket for TO, CERDIP, PDIP, and LCC packages; θ
device soldered to printed circuit board for SOIC package.
is specified for
JA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. G | Page 7 of 16
REF02
TYPICAL PERFORMANCE CHARACTERISTICS
10k
VIN = 15V
= 25°C
T
A
20
TA = 25°C
19
1k
100
OUTPUT NOISE (µV p-p)
10
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 5. Output Wideband Noise vs. Bandwidth
(0.1 Hz to Frequency Indicated)
76
66
56
46
36
26
LINE REGULATION (dB)
VIN = 15V
16
= 25°C
T
A
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 6. Line Regulation vs. Frequency
00375-F-005
0.0031
0.0100
0.0310
0.1000
0.3100
1.0000
LINE REGULATION (%/V)
3.1000
00375-F-006
10.0000
18
17
16
MAXIMUM LOAD CURRENT (mA)
15
14
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
Figure 8. Maximum Load Current vs. Input Voltage
1.4
VIN = 15V
1.3
C)
°
1.2
1.1
1.0
0.9
0.8
LOAD REG–T/LOAD REG (25
0.7
0.6
–60 –40 –20 0 20 40 60 80 100 120 140
Figure 9. Normalized Load Regulation (∆I
TEMPERATURE (°C)
= 10 mA) vs. Temperature
L
00375-F-008
00375-F-009
0.016
VIN = 15V
0.014
0.012
0.010
0.008
0.006
0.004
25°C
0.002
PERCENT CHANGE IN OUTPUT VOLTAGGE (%)
0
–10 0 10 20 30 40 50
DEVICE IMMERSED
IN 75°C OIL BATH
TIME (s)
Figure 7. Output Change Due to Thermal Shock
00375-F-007
Rev. G | Page 8 of 16
1.4
1.3
C)
1.2
°
1.1
1.0
0.9
0.8
LINE REG–T/LINE REG (25
0.7
0.6
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
Figure 10. Normalized Line Regulation vs. Temperature
00375-F-010
REF02
0.03
TA = 25°C
30
VIN = 15V
25
0.02
0.01
LINE REGULATION (%/V)
0
5 101520253
INPUT VOLTAGE (V)
Figure 11. Line Regulation vs. Input Voltage
1.3
VIN = 15V
1.2
1.1
1.0
0.9
QUIESCENT CURRENT (mA)
0.8
00375-F-011
0
20
15
10
MAXIMUM LOAD CURRENT (mA)
5
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
00375-F-012
Figure 13. Maximum Load Current vs. Temperature
0.7
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
00375-F-026
Figure 12. Quiescent Current vs. Temperature
Rev. G | Page 9 of 16
REF02
OUTPUT ADJUSTMENT
The REF02 trim terminal can be used to adjust the output
voltage over a 5 V ± 300 mV range. This feature lets the system
designer trim system errors by setting the reference to a voltage
other than 5 V. The output also can be set to exactly 5.000 V or
to 5.12 V for binary applications.
15V
2
V
IN
6
V
O
REF02
4
TRIM
5
3
TEMP
GND
Figure 14. Output Adjustment Circuit
Adjustment of the output does not significantly affect the
temperature performance of the device. The temperature
coefficient change is approximately 0.7 ppm/°C for 100 mV of
output adjustment.
+18V
2
V
IN
REF02
GND
4
–18V
Figure 15. Burn-In Circuit
+15V
2
V
IN
6
V
O
REF02
TRIMTEMP
GND
4
0.1µF
5kΩ
10kΩ
53
Figure 16. ±5 V Reference
10kΩ
00375-F-014
10kΩ
+15V
OP02
–15V
OUTPUT
00375-F-013
+5V
–5V
00375-F-015
VO+
+5V
2
6
+2.5V
R1
5.6kΩ
REF02
V
VO+ =
4
R1
R1 + R2
REF
VO– =
R2
R1 + R2
),
(V
REF
R2
5.6kΩ
)
(V
REF
+V
–2.5V
7
2
–
6
OP02
3
+
4
–9V
O
00375-F-016
Figure 17. ±2.5 V Reference
TEMPERATURE MONITORING
As described previously, the REF02 provides a TEMP output
(Pin 3) that varies linearly with temperature. This output can be
used to monitor the temperature change in the system. The
voltage at V
temperature coefficient is approximately 1.96 mV/°C (see
Figure 18).
850
800
750
700
650
600
550
TEMP PIN OUTPUT (mV)
500
450
400
A voltage change of 39.2 mV at the TEMP pin corresponds to a
20°C change in temperature.
The TEMP function is provided as a convenience rather than a
precise feature. Since the voltage at the TEMP node is acquired
from the band gap core, current pulling from this pin has a
significant effect on V
TEMP output with a suitable low bias current op amp, such as
the AD8601, AD820, or OP1177. Using any of these three op
amps results in less than a 100 µV change in ΔV
19). Without buffering, even tens of microamps drawn from the
TEMP pin can cause V
is approximately 550 mV at 25°C, and the
TEMP
= 9V
V
IN
SAMPLE SIZE = 6
Z PACKAGE AND 833 PRODUCT
∆
V
/∆T = 2.1mV/°C
TEMP
∆
V
/∆T = 1.96mV/°C
TEMP
J, S, AND P PACKAGES
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 18. Voltage at TEMP Pin vs. Temperature
. Care must be taken to buffer the
OUT
(see Figure
OUT
to fall out of specification.
OUT
00375-F-017
Rev. G | Page 10 of 16
REF02
15V
V
IN
V
TEMP
1.9mV/°C
U2
V+
OP1177
V–
REF02
V
IN
TEMP
U1
GND
V
OUT
TRIM
V
O
00375-F-018
Figure 19. Temperature Monitoring
V+ (12V TO 32V)
R7
27kΩ
2
V
IN
V
HEATING
ELEMENT
(SEE NOTE 1)
R5
2.2kΩ
NOTES
1. REF02 SHOULD BE THERMALLY CONNECTED
TO SUBSTANCE BEING HEATED.
2. NUMBERS IN PARENTHESES ARE FOR A
SETPOINT TEMPERATURE OF 60°C.
3. R3 = R1|| R2|| R6
REF02
TEMP
GND
4
O
R1
(9.2kΩ)
6
(1.3kΩ)
3
R6
2
8
+
V+
R3
1.5kΩ
2.7kΩ
CMP02
3
–
R2
R4
7
V–
4
1
Figure 20. Temperature Controller
REFERENCE STACK WITH EXCELLENT LINE REGULATION
Two REF01s and one REF02 can be stacked to yield 5.000 V,
15.000 V, and 25.000 V outputs. An additional advantage is nearperfect line regulation of the 5.0 V and 15.0 V output. A 27 V to
55 V input change produces an output change that is less than
the noise voltage of the devices. A load bypass resistor (R
provides a path for the supply current (I
) of the 15.000 V
SY
regulator.
In general, any number of REF01s and REF02s can be stacked
this way. For example, 10 devices yield 10 outputs in 5 V or 10 V
steps. The line voltage can change from 100 V to 130 V. However, care must be taken to ensure that the total load currents do
not exceed the maximum usable current (typically 21 mA).
)
B
27V TO 55V
2
V
IN
6
V
O
15V
REF02
GND
TRIM
4
5
2
V
6
IN
V
O
10kΩ
10V
REF02
5
2
V
6
IN
V
O
GND
TRIM
4
10kΩ
5V
REF02
R
B
6.8kΩ
00375-F-020
GND
TRIM
4
5
10kΩ
Figure 21. Reference Stack
PRECISION CURRENT SOURCE
A current source with 35 V output compliance and excellent
output impedance can be obtained using this circuit. REF02
00375-F-019
keeps the line voltage and power dissipation constant in the
device; the only important error consideration at room
temperature is the negative supply rejection of the op amp. The
typical 3 µV/V PSRR of the OP02E creates a 20 ppm change
(3 µV/V × 35 V/5 V) in output current over a 25 V range. For
example, a 5 mA current source can be built (R = 1 kΩ) with
350 MΩ output impedance.
+50V
2
V
IN
6
V
O
REF02
2
GND
4
R
C
(TRIM FOR
R
C
CALIBRATION)
RO=
20
2
V
IN
REF02
1
GND
4
35V
–6
×
10
×
5mA
6
V
O
Rev. G | Page 11 of 16
7
2
6
OP02E
3
4
–5V
Figure 22. Precision Current Source
VO= 0V
TO 25V
5V
=
I
O
R
00375-F-021
REF02
±
0.1µF
3
+15V
2
V
IN
REF02
GND
4
3
V
O
15V
2
V
IN
6
V
O
REF02
TEMP
GND
5
TRIM
4
VOLTAGE COMPLIANCE: –25V TO +8V
I
OUT
R
Figure 23. Current Source
I
OUT
VOLTAGE COMPLIANCE: –9V TO +25V
2
V
IN
6
V
O
REF02
TEMP
GND
–15V
4
TRIM
5
R
Figure 24. Current Sink
5kΩ
MSB
B1 B2 B3 B4 B5 B6 B7 B8
5kΩ
6
5
5kΩ
V+
+15V
DAC08
V–
–15V
Figure 25. DAC Reference
10%)
I
OUT
I
OUT
= +
= +
+7.5V (
2
V
IN
6
V
GND
O
R1
20kΩ
R2
4
13.3kΩ
5V
R
+ 1mA
00375-F-022
REF02HJ
1/2 OP04CK
R4
2kΩ
5V
+ 1mA
R
Figure 26. ±3 V Reference
+7.5V
A1
–7.5V
–7.5V
A2
–7.5V (±10%)
(+) = +3V
V
O
1/2 OP04CK
R3
1kΩ
V
(–) = –3V
O
00375-F-025
SUPPLY BYPASSING
00375-F-023
LSB
l
O
l
O
V
C
LC
C
5kΩ
+15V
4
OP02
2
–15V
E
O
00375-F-024
For best results, it is recommended that the power supply pin be
bypassed with a 0.1 µF disc ceramic capacitor.
Rev. G | Page 12 of 16
REF02
OUTLINE DIMENSIONS
0.005 (0.13)
PIN 1
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 27. 8-Lead Ceramic Dual In-Line Package (CERDIP)
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
PIN 1
0.100 (2.54)
0.210
(5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 28. 8-Lead Plastic Dual In-Line Package (PDIP)
0.055 (1.40)
MIN
0.100 (2.54) BSC
0.405 (10.29) MAX
MAX
85
0.310 (7.87)
4
0.070 (1.78)
0.030 (0.76)
0.220 (5.59)
0.060 (1.52)
0.015 (0.38)
0.150 (3.81)
MIN
SEATING
PLANE
1
0.320 (8.13)
0.290 (7.37)
15°
0°
Z-Suffix
(Q-8)
Dimensions shown in inches (millimeters)
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
4
BSC
0.005 (0.13)
MIN
COMPLIANT TO JEDEC STANDARDS MS-001-BA
0.015
(0.38)
MIN
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
GAUGE
PLANE
MAX
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.430 (10.92)
P-Suffix, Narrow Body
(N-8)
Dimensions shown in inches (millimeters)
MAX
0.015 (0.38)
0.008 (0.20)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
REFERENCE PLANE
0.5000 (12.70)
0.1850 (4.70)
0.1650 (4.19)
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
0.0400 (1.02) MAX
0.0400 (1.02)
0.0100 (0.25)
COMPLIANT TO JEDEC STANDARDS MO-002AK
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
MIN
0.2500 (6.35) MIN
0.0500 (1.27) MAX
0.2000
(5.08)
BSC
0.0190 (0.48)
0.0160 (0.41)
0.0210 (0.53)
0.0160 (0.41)
BASE & SEATING PLANE
0.1000
(2.54)
BSC
0.1000 (2.54)
BSC
5
4
3
2
1
0.1600 (4.06)
0.1400 (3.56)
6
7
8
0.0340 (0.86)
0.0280 (0.71)
45° BSC
0.0450 (1.14)
0.0270 (0.69)
Figure 29. 8-Lead Metal Header Package [TO-99]
J-Suffix
(H-08)
Dimensions shown in inches (millimeters)
20
1
VIEW
0.150 (3.81)
BSC
0.200 (5.08)
REF
0.100 (2.54) REF
0.015 (0.38)
MIN
3
4
0.028 (0.71)
0.022 (0.56)
0.050 (1.27)
8
BSC
9
45° TYP
0.075 (1.91)
0.095 (2.41)
0.075 (1.90)
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.055 (1.40)
0.045 (1.14)
REF
19
18
14
13
BOTTOM
0.100 (2.54)
0.064 (1.63)
0.358 (9.09)
0.342 (8.69)
SQ
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.358
(9.09)
MAX
0.088 (2.24)
0.054 (1.37)
SQ
Figure 30. 20-Terminal Ceramic Leadless Chip Carrier (LCC)
RC-Suffix
(E-20A)
Dimensions shown in inches (millimeters)
Rev. G | Page 13 of 16
REF02
4.00 (0.1574)
3.80 (0.1497)
5.00 (0.1968)
4.80 (0.1890)
85
6.20 (0.2440)
5.80 (0.2284)
41
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012AA
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8°
1.27 (0.0500)
0°
0.40 (0.0157)
Figure 31. 8-Lead Standard Small Outline Package (SOIC)
S-Suffix, Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
× 45°
Rev. G | Page 14 of 16
REF02
ORDERING GUIDE
T
= 25°C
Model
∆V
A
OS
Max (mV)
REF02AJ/883C1 ±15 –55°C to +125°C TO-99 J-8
REF02AZ ±15 –55°C to +125°C CERDIP-8 Z-8
REF02AZ/883C1 ±15 –55°C to +125°C CERDIP-8 Z-8
REF02CJ ±50 0°C to 70°C TO-99 J-8
REF02CP ±50 –40°C to +85°C PDIP-8 P-8
REF02CPZ
2
±50 –40°C to +85°C PDIP-8 P-8
REF02CS ±50 –40°C to +85°C SOIC-8 S-8
REF02CS-REEL ±50 –40°C to +85°C SOIC-8 S-8
REF02CS-REEL7 ±50 –40°C to +85°C SOIC-8 S-8
REF02CSZ2 ±50 –40°C to +85°C SOIC-8 S-8
REF02CSZ2-REEL ±50 –40°C to +85°C SOIC-8 S-8
REF02CSZ2-REEL7 ±50 –40°C to +85°C SOIC-8 S-8
REF02CZ2 ±50 0°C to +70°C CERDIP-8 Z-8
REF02DP ±100 0°C to 70°C PDIP-8 P-8
REF02EJ ±15 –40°C to +85°C TO-99 J-8
REF02EZ ±15 –40°C to +85°C CERDIP-8 Z-8
REF02J ±25 –55°C to +125°C TO-99 J-8
REF02HJ ±25 –40°C to +85°C TO-99 J-8
REF02HZ ±25 –40°C to +85°C CERDIP-8 Z-8
REF02HP ±25 –40°C to +85°C PDIP-8 P-8
REF02HPZ2 ±25 –40°C to +85°C PDIP-8 P-8
REF02HS ±25 –40°C to +85°C SOIC-8 S-8
REF02RC/8831 ±25 –55°C to +125°C LCC-20 RC-20
REF02Z ±25 –55°C to +125°C CERDIP-8 Z-8
Operating Temperature
Range (°C
) Package Description Package Option
1
For devices processed in total compliance to MIL-STD-883, add 883 after part number. Consult sales for 883 data sheet.
2
Z = Pb-free part.
Rev. G | Page 15 of 16
REF02
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00375-0-2/05(G)
Rev. G | Page 16 of 16
Loading...