Datasheet OP497FS, OP497CY, OP497AY, OP497GP, OP497FP Datasheet (Analog Devices)

Precision Picoampere Input Current

a

FEATURES
Low Offset Voltage: 50 ␮V max
Low Offset Voltage Drift: 0.5 ␮V/ⴗC max
Very Low Bias Current
25ⴗC: 100 pA max
–55ⴗC to +125ⴗC: 450 pA max
Very High Open-Loop Gain: 2000 V/mV min
Low Supply Current (per Amplifier): 625 ␮A max
Operates from ⴞ2 V to ⴞ20 V Supplies
High Common-Mode Rejection: 120 dB min

APPLICATIONS
Strain Gage and Bridge Amplifiers
High Stability Thermocouple Amplifiers
Instrumentation Amplifiers
Photo-Current Monitors
High Gain Linearity Amplifiers
Long-Term Integrators/Filters
Sample-and-Hold Amplifiers
Peak Detectors
Logarithmic Amplifiers
Battery-Powered Systems

Quad Operational Amplifier

OP497

PIN CONNECTIONS

16-Lead Wide Body SOIC

(S-Suffix)

OUT D

1

OUT A

–IN A

2

+

–

3

+IN A

V+

4

OP497

5

+IN B

–IN B

OUT B

NC

–

+

6

7

8

NC = NO CONNECT

14-Lead Plastic Dip

(P-Suffix)

14-Lead Ceramic Dip

(Y-Suffix)

16

–IN D

15

+

–

+IN D

14

V–

13

+IN C

12

–

+

11

10

9

–IN C

OUT C

NC

GENERAL DESCRIPTION

The OP497 is a quad op amp with precision performance in the
space-saving, industry standard 16-lead SOlC package. Its com­bination of exceptional precision with low power and extremely
low input bias current makes the quad OP497 useful in a wide
variety of applications.

Precision performance of the OP497 includes very low offset,
under 50 µV, and low drift, below 0.5 µV/°C. Open-loop gain
exceeds 2000 V/mV ensuring high linearity in every application.
Errors due to common-mode signals are eliminated by the OP497’s
common-mode rejection of over 120 dB. The OP497’s power
supply rejection of over 120 dB minimizes offset voltage changes
experienced in battery-powered systems. Supply current of the
OP497 is under 625 µA per amplifier, and it can operate with
supply voltages as low as ±2 V.

The OP497 utilizes a superbeta input stage with bias current can­cellation to maintain picoamp bias currents at all temperatures.
This is in contrast to FET input op amps whose bias currents start
in the picoamp range at 25°C, but double for every 10°C rise in
temperature, to reach the nanoamp range above 85°C. Input bias
current of the OP497 is under 100 pA at 25°C and is under 450
pA over the military temperature range.

Combining precision, low power, and low bias current, the
OP497 is ideal for a number of applications, including instru­mentation amplifiers, log amplifiers, photo-diode preamplifiers,
and long-term integrators. For a single device, see the OP97; for a
dual device, see the OP297.

OUT A

1

–IN A

2

+–+

+IN A

V+

+IN B

–IN B

OUT B

1000

100

INPUT CURRENT – PA

10

–75 –50 –25 0 25 50 75 100 125

–

3

4

OP497

5

–

+–+

6

7

TEMPERATURE – C

OUT D

14

–IN D

13

+IN D

12

V–

11

+IN C

10

–IN C

9

OUT C

8

VS = ⴞ15V
V

CM

–I

B

+I

B

I

OS

Input Bias, Offset Current vs. Temperature

= 0V

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

OP497–SPECIFICATIONS

(@ VS = 15 V, TA = 25ⴗC, unless otherwise noted.)

A F C/G

Parameter Symbol Condition Min Typ Max Min Typ Max Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage Vos 20 50 40 75 80 150 µV

–40°C ≤ +85°C 70 150 120 250
–55°C ≤ +125°C 40 100 80 150 140 300

Average Input Offset

Voltage Drift TCV

OS

T

MIN

– T

MAX

0.2 0.5 0.4 1.0 0.6 1.5 µV/°C

Long-Term Input Offset

Voltage Stability 0.1 0.1 0.1 µV/Mo

Input Bias Current I

B

VCM = 0 V 30 100 40 150 60 200 pA
–40° ≤ T
–55° ≤ T

≤ +85°C 60 200 80 300

A

≤ +125°C 80 450 110 600 130 600

A

Average Input Bias

Current Drift TC

IB

Input Offset Current Ios V

–40° ≤ TA ≤ +85°C 0.3 0.3
–55° ≤ T

CM

–40° ≤ T
–55° ≤ T

≤ +125°C 0.5 0.7 0.7 pA/°C

A

= OV 15 100 30 150 50 200 pA

≤ +85°C 50 200 80 300

A

≤ +125°C 35 400 60 600 90 600

A

Average Input Offset

Current Drift T

Input Voltage Range

1

CIOS

IVR + 13 +14 +13 tl4 +13 +14 V

Common-Mode Rejection CMR V

Large Signal Voltage Gain A

VO

T

– T

MIN

MAX

= ±13 V 120 140 114 135 114 135 dB

CM

T

– T

MIN

MAX

VO = ±10 V,
R

= 2 kΩ 2000 6000 1500 4000 1200 4000 V/mV

L

–40° ≤ T
–55° ≤ T

≤ +85°C 800 2000 800 2000

A

≤ +125°C 1200 4000 1000 3000 800 3000

A

0.2 0.3 0.4 pA/°C

+13 +13.5 +13 +13.5 +13 +13.5

114 130 108 120 108 120

Input Resistance

Differential Mode R

IN

30 30 30 MΩ

Input Resistance

Common Mode R

Input Capacitance C

INCM

IN

500 500 500 GΩ
33 3pF

OUTPUT CHARACTERISTICS

Output Voltage Swing V

O

RL = 2 kΩ±13 ±13.7 ±13 ± 13.7 ± 13 ± 13.7 V
R

= 10 kΩ± 13 ±14 ±13 ± 14 ±13 ±14

L

T

– T

MIN

MAX

RL = 10 kΩ±13 ±13.5 ±13 ± 13.5 ± 13 ± 13.5

Short Circuit I

SC

±25 ±25 ±25 mA

POWER SUPPLY

Power Supply PSRR Vs = ±2 V to ± 20 V 120 140 114 135 114 135 dB

Rejection Ratio Vs = ±2.5 V to ±20 V

T

Supply Current I

SY

(per Amplifier) T

Supply Voltage Range V

S

– T

MIN

MAX

No Load 525 625 525 625 525 625 µA

– T

MIN

MAX

Operating Range ±2 ±20 ±2 ±20 ±2 ± 20 V
T

– T

MIN

MAX

114 130 108 120 108 120

580 750 580 750 580 750

±2.5 ± 20 ±2.5 ±20 ±2.5 ± 20

DYNAMIC PERFORMANCE

Slew Rate SR 0.05 0.15 0.05 0.15 0.05 0.15 V/µS
Gain Bandwidth Product GBW 500 500 500 kHz
Channel Separation CS V

= 20 V

O

p-p,

fo = 10 Hz 150 150 150 dB

NOISE PERFORMANCE

Voltage Noise e
Voltage Noise Density e

n p-p

= 10 Hz 17 17 17 nV/√Hz

n

e

= 1 kHz 15 15 15 nV/√Hz

n

0.1 Hz to 10 Hz 0.3 0.3 0.3 µV/p-p

Current Noise Density in = 10 Hz 20 20 20 fA/√Hz

NOTE
1Guaranteed by CMR Test.
Specifications subject to change without notice.

–2–

REV. D

OP497

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V

Input Voltage
Differential Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1

20 V

40 V

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range

Y Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

OP497A, C (Y) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

OP497F, G (Y) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

OP497F, G (P, S) . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature

Y Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C

Package Type ␪

3

JA

␪

JC

Unit

14-Pin Cerdip (Y) 94 10 °C/W
14-Pin Plastic DIP (P) 76 33 °C/W
16-Pin SOIC (S) 92 23 °C/W

NOTES

1

Absolute Maximum Ratings apply to both DICE and packaged parts, unless
otherwise noted.

2

For supply voltages less than ± 20 V, the absolute maximum input voltage is
equal to the supply voltage.

3

HIA is specified for worst-case mounting conditions, i.e., ␪JA is specified for
device in socket for cerdip, P-DIP packages; ␪JA is specified for device soldered
to printed circuit board for SOIC package.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

OP497AY* –55°C to +125°C 14-Lead Cerdip Q-14
OP497CY* –55°C to +125°C 14-Lead Cerdip Q-14
OP497FP –40°C to +85°C 14-Lead Plastic DIP N-14
OP497FS –40°C to +85°C 16-Lead SOIC R-16
OP497GP –40°C to +85°C 14-Lead Plastic DIP N-14
OP497GS –40°C to +85°C 16-Lead SOIC R-16

*Not for new design; obsolete April 2002.

For a military processed devices, please refer to the Standard
Microcircuit Drawing (SMD) available at www.dscc.dla.mil/
programs.milspec./default.asp.

SMD Part Number ADI Part Number

5962–9452101M2A* OP497BRC
5962–9452101MCA OP497BY

*Not for new designs; obsolete April 2002.

DICE CHARACTERISTICS

–

1/4

OP497

+

CHANNEL SEPARATION = 20 log

V

20V p–p @ 10Hz

1

2k⍀

50⍀

V

1

()

V /10000

2

50k⍀

–

1/4

OP497

+

V

2

Channel Separation Test Circuit

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP497 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. D

–3–

OP497

–Typical Performance Characteristics

(25ⴗC, Vs = 15 V, unless otherwise noted.)

50

40

30

20

PERCENTAGE OF UNITS

10

0

–80

–100

–20–40–60

INPUT OFFSET VOLTAGE – ␮V

TA = 25ⴗC

= 15V

V

S

V

CM

0

TPC 1. Typical Distribution of
Input Offset Voltage

50

40

30

20

PERCENTAGE OF UNITS

10

0

0

0.1

TCVOS – ␮V/ⴗC

VS = ⴞ15V
V

TPC 4. Typical Distribution of
TCV

OS

CM

= 0V

= 0V

50

40

30

20

PERCENTAGE OF UNITS

10

100

80604020

0

–80

–100

INPUT BIAS CURRENT – pA

–20–40–60

TA = 25ⴗC

= 15V

V

S

= 0V

V

CM

0

100

80604020

TPC 2. Typical Distribution of
Input Bias Current

1000

VS = ⴞ15V

= 0V

V

CM

100

–I

INPUT CURRENT – pA

10

0.8

0.70.60.50.40.30.2

–75 –50 –25 0 25 50 75 100 125

B

+I

I

OS

TEMPERATURE – ⴗC

B

TPC 5. Input Bias, Offset

Current vs. Temperature

60

TA = 25ⴗC

50

40

30

20

PERCENTAGE OF UNITS

10

0

0

10

INPUT OFFSET CURRENT – pA

V

S

V

CM

TPC 3. Typical Distribution of
Input Offset Current

70

TA = 25 C

= ⴞ15V

V

S

60

50

40

30

20

INPUT BIAS CURRENT – pA

10

0

–10

–15

COMMON-MODE VOLTAGE – Volts

0

–5

TPC 6. Input Bias Current vs.
Common-Mode Voltage

= 15V

= 0V

50403020

105

60

–I

B

+I

B

15

ⴞ3

ⴞ2

ⴞ1

DEVIATION FROM FINAL VALUE – ␮V

0

0

TIME AFTER POWER APPLIED – Minutes

TA = 25ⴗC
V
V

TPC 7. Input Offset Voltage
Warm-Up Drift

= ⴞ15V

S

= 0V

CM

10000

BALANCED OR UNBALANCED

= 15V

V

S

= 0V

V

CM

1000

100

–55 C T 125 C

A

EFFECTIVE OFFSET VOLTAGE – ␮V

10

10

51

432

100

SOURCE RESISTANCE – ⍀

10k

1k

T = +25 C

100k

A

1M

10M

TPC 8. Effective Offset Voltage
vs. Source Resistance

–4–

100

BALANCED OR UNBALANCED

= 15V

V

S

= 0V

V

CM

10

1

EFFECTIVE OFFSET VOLTAGE – ␮V/ ⴗC

0.1
100 1k 10k 100k

SOURCE RESISTANCE – ⍀

TPC 9. Effective TCVOS vs.
Source Resistance

1M 10M

100M

REV. D

OP497

1000

TA = 25ⴗC

= 2V TO 20V

V

S

100

CURRENT NOISE

VOLTAGE NOISE

10

VOLTAGE NOISE DENSITY – nV/ Hz

1

1 10 100

FREQUENCY – Hz

TPC 10. Voltage Noise Density
vs. Frequency

100

80

GAIN

60

PHASE

40

20

0

OPEN-LOOP GAIN – dB

–20

–40

100

1k

FREQUENCY – Hz

TPC 13. Open-Loop Gain,
Phase vs. Frequency

VS = ⴞ15V

= 30pF

C

L

R

= 1M⍀

L

= 25ⴗC

T

A

1M100k10k

1000

10M

90

135

180

225

10

TA = 25ⴗC

= ⴞ2V TO ⴞ20V

V

S

1

10Hz

0.1

CURRENT NOISE DENSITY – fA / Hz

TOTAL NOISE DENSITY – ␮V/ Hz

0.01

2

10

10310410510610

SOURCE RESISTANCE – ⍀

TPC 11. Total Noise Density vs.

1kHz

NOISE VOLTAGE – 100mV/DIV

7

TPC 12. 0.1 Hz to 10 Hz Noise Voltage

5mV

100

90

10

0%

02 4 6810

TIME – Secs

1s

VS = 15V
T

= 25ⴗC

A

Source Resistance

PHASE SHIFT – DEG

10000

1000

OPEN - LOOP GAIN – V/ MV

100

11020

TA = –55ⴗC

TA = +125ⴗC

VS = ⴞ15V

= ⴞ10V

V

O

LOAD RESISTANCE – k⍀

TA = +25C

TPC 14. Open-Loop Gain vs.

RL = 2k⍀

= ⴞ15V

V

S

= ⴞ10V

V

CN

TA= +125ⴗC

TA= +25ⴗC

T

= –55ⴗC

A

DIFFERENTIAL INPUT VOLTAGE – 10␮V/ DIV

OUTPUT VOLTAGE – V

15–10–15 1050–5

TPC 15. Open-Loop Gain Linearity

Load Resistance

COMMON - MODE REJECTION – dB

160

140

120

100

80

60

40

20

0

101

FREQUENCY – Hz

VS = ⴞ15V
T

TPC 16. Common-Mode

Rejection vs. Frequency

REV. D

= 25ⴗC

A

100k10k1k100

1M

POWER SUPPLY REJECTION – dB

160

140

120

100

–PSR

80

60

40

20

0

+PSR

101

FREQUENCY – Hz

VS = ⴞ15V

= 25ⴗC

T

A

TPC 17. Power Supply

Rejection vs. Frequency

–5–

35

30

25

p-p

20

15

10

OUTPUT SWING – V

5

1M

100k10k1k100

0
100

1k

FREQUENCY – Hz

10k

V

= ⴞ15V

S

= 25ⴗC

T

A

A

VCL

1%THD

= 10k⍀

R

L

= +1

100k

TPC 18. Maximum Output
Swing vs. Frequency

OP497

+V

S

–0.5

–1.0

–1.5

1.5

1.0

0.5

(REFERRED TO SUPPLY VOLTAGES)

INPUT COMMON-MODE VOLTAGE – Volts

–V

S

0

ⴞ5
SUPPLY VOLTAGE – V

TA = 25ⴗC

ⴞ15ⴞ10

ⴞ20

TPC 19. Input Common-Mode
Voltage Range vs. Supply Voltage

700

+125 C

600

+25

500

400

300

SUPPLY CURRENT (PER AMPLIFIER) – ␮A

200

C

–55

C

ⴞ5

0

ⴞ10

SUPPLY VOLTAGE – V

NO LOAD

ⴞ15

ⴞ20

TPC 22. Supply Current
(per Amplifier) vs. Supply Voltage

35

VS = ⴞ15V

= 25ⴗC

T

A

30

= +1

A

VCL

1%THD

f

= 1kHz

25

p-p

O

20

15

10

OUTPUT SWING – V

5

0

10

100

LOAD RESISTANCE – ⍀

1k

TPC 20. Maximum Output Swing
vs. Load Resistance

1000

VS = 15V

= 25 C

T

A

100

10

0.1

0.01

0.001

1

10

1

AV = +1

10k1k100

TPC 23. Closed-Loop Output
Impedance vs. Frequency

10k

100k

+V

S

–0.5

–1.0

–1.5

1.5

1.0

OUTPUT VOLTAGE SWING – V

0.5

(REFERRED TO SUPPLY VOLTAGES)

–V

S

0

ⴞ5

ⴞ10

SUPPLY VOLTAGE – V

TA = 25ⴗC

= 10k⍀

R

L

ⴞ15

TPC 21. Output Voltage Swing vs.
Supply Voltage

35

30

25

20

15

VS = ⴞ15V

OUTPUT SHORTED
TO GROUND

SHORT CIRCUIT CURRENT – mA

–15

–20

–25

–30

–35

TA = +125 C

0

1

TIME FROM OUTPUT SHORT – Mins

= –55 C

T

A

TA = +25 C

TA = +125 C

= +25 C

T

A

TA = –55 C

2

3

TPC 24. Short-Circuit Current vs.
Time Temperature

ⴞ20

4

70

VS = ⴞ15V

= 25 C

T

A

60

= +1

A

VCL

= 100mV p–p

V

OUT

50

40

30

OVERSHOOT – %

20

10

0

10

100

LOAD CAPACITANCE – pF

1k

TPC 25. Small-Signal Overshoot
vs. Capacitance Load

10k

–IN

+IN

2.5k⍀

2.5k⍀

TPC 26. Simplified Schematic Showing One Amplifier

V+

V

OUT

V–

–6–

REV. D

APPLICATIONS INFORMATION

1/4

OP497

UNITY GAIN FOLLOWER NONINVERTING AMPLIFIER

INVERTING AMPLIFIER

B

8

A

1

MINI-DIP

BOTTOM VIEW

–

+

–

+

–

+

1/4

OP497

1/4

OP497

Extremely low bias current over the full military temperature range
makes the OP497 attractive for use in sample-and-hold amplifiers,
peak detectors, and log amplifiers that must operate over a wide
temperature range. Balancing input resistances is not necessary
with the OP497. Offset voltage and TCV

are degraded only

OS

minimally by high source resistance, even when unbalanced.

The input pins of the OP497 are protected against large differen­tial voltage by back-to-back diodes and current-limiting resistors.
Common-mode voltages at the inputs are not restricted, and may
vary over the full range of the supply voltages used.

The OP497 requires very little operating headroom about the
supply rails, and is specified for operation with supplies as low
as ±2 V. Typically, the common-mode range extends to within
1 V of either rail. The output typically swings to within 1 V of
the rails when using a 10 kΩ load.

AC PERFORMANCE

The OP497’s ac characteristics are highly stable over its full
operating temperature range. Unity-gain small-signal response is
shown in Figure 1. Extremely tolerant of capacitive loading on
the output, the OP497 displays excellent response even with
1000 pF loads (Figure 2).

100

90

OP497

100

90

10

0%

50

␮

2V

Figure 3. Large-Signal Transient Response (A

GUARDING AND SHIELDING

To maintain the extremely high input impedances of the OP497,
care must be taken in circuit board layout and manufacturing.
Board surfaces must be kept scrupulously clean and free of mois­ture. Conformal coating is recommended to provide a humidity
barrier. Even a clean PC board can have 100 pA of leakage currents
between adjacent traces, so guard rings should be used around
the inputs. Guard traces are operated at a voltage close to that
on the inputs, as shown in Figure 4, so that leakage currents
become minimal. In noninverting applications, the guard ring
should be connected to the common-mode voltage at the invert­ing input. In inverting applications, both inputs remain at ground,
so the guard trace should be grounded. Guard traces should be
on both sides of the circuit board.

s

= 1)

VCL

10

0%

20mV

Figure 1. Small-Signal Transient Response
(C

= 100 pF, A

LOAD

100

90

10

0%

20MV

Figure 2. Small-Signal Transient Response
(C

REV. D

= 1000 pF, A

LOAD

VCL

= 1)

VCL

5

= 1)

5␮s

Figure 4. Guard Ring Layout and Connections

␮

s

–7–

OP497

OPEN-LOOP GAIN LINEARITY

The OP497 has both an extremely high gain of 2000 V/mv mini­mum and constant gain linearity. This enhances the precision of
the OP497 and provides for very high accuracy in high closed-loop
gain applications. Figure 5 illustrates the typical open-loop gain
linearity of the OP 497 over the military temperature range.

RL = 10k⍀

= ⴞ15V

V

S

= 0V

V

CM

DIFFERENTIAL INPUT VOLTAGE – 10µV/ DIV

T

= +125 C

A

= +25C

T

A

= –55 C

T

A

OUTPUT VOLTAGE – Volts

15–10–15 1050–5

Figure 5. Open-Loop Linearity of the OP497

APPLICATIONS

Precision Absolute Value Amplifier

The circuit of Figure 6 is a precision absolute value amplifier
with an input impedance of 30 MΩ. The high gain and low
TCV

of the OP497 ensure accurate operation with microvolt

OS

input signals. In this circuit, the input always appears as a com­mon-mode signal to the op amps. The CMR of the OP497
exceeds 120 dB, yielding an error of less than 2 ppm.

+15V

PRECISION CURRENT PUMP

Maximum output current of the precision current pump shown
in Figure 7 is ±10 mA. Voltage compliance is ±10 V with ±15 V
supplies. Output impedance of the current transmitter exceeds
3 MΩ with linearity better than 16 bits.

R3

2

3

R4

10k⍀

10k⍀

1/4

OP497

7

1

+15V

8

1/4

OP497

–15V

4

R5

10k⍀

I

OUT

ⴞ10mA

5

6

R1

10k⍀

–

R2

V

IN

10k⍀

+

V

V

IN

I

OUT

IN

= = = 10mA/ V

R5

100⍀

Figure 7. Precision Current Pump

PRECISION POSITIVE PEAK DETECTOR

In Figure 8, the CH must be of polystyrene, Teflon*, or polyeth­ylene to minimize dielectric absorption and leakage. The droop
rate is determined by the size of CH and the bias current of the
OP497.

1k⍀

+15V

2

1/4

OP497

1k⍀

V

IN

3

1

RESET

1N4148

C

H

1k⍀

2N930

1k⍀

6

OP497

5

1/4

4

–15V

0.1␮F

8

0.1␮F

7

V

OUT

C2

0.1␮F

C1
30pF

8

2

1/4

–15V

4

C3

0.1␮F

1

OP497

3

V

IN

1k⍀

D1
1N4148

D2

1N4148

R1

R2
2k⍀

6

5

R3

1k⍀

1/4

OP497

0V < V < 10V

Figure 6. Precision Absolute Value Amplifier

*Teflon is a registered trademark of the Dupont Company.

Figure 8. Precision Positive Peak Detector

SIMPLE BRIDGE CONDITIONING AMPLIFIER

7

OUT

Figure 9 shows a simple bridge conditioning amplifier using
the OP497. The transfer function is:

VV

=

OUT REF






RRRR



∆

R

+

F




∆

The REF43 provides an accurate and stable reference voltage
for the bridge. To maintain the highest circuit accuracy, R

F

should be 0.1% or better with a low temperature coefficient.

–8–

REV. D

+5V

1

2

3

6

7

5

C1

100pF

V+

2

3

8

1

4

V–

V

IN

I

IN

C2

100pF

6

5

7

V

OUT

I

O

9

8

10

Q1

Q3

Q2

14

12

Q4

13

–15V

I

REF

MAT-04E

R1

133k⍀

R2

33k⍀

R3

50k⍀

R4
50k⍀

1/4

OP497

1/4

OP497

1

2

3

6

7

5

C1

100pF

V+

2

3

8

1

4

V–

6

5

7

V

OUT

I

O

9

8

10

Q1

Q3

Q2

14

12

Q4

13

–15V

I

REF

MAT-04E

I

IN

V

IN

R1

33k⍀

R2

33k⍀

R5

2k⍀

R3

50k⍀

R4
50k⍀

C2

100pF

1/4

OP497

1/4

OP497

2

REF43

4

V

REF

2.5 V

6

R

R

R + ⌬R

R

+5V

6

8

1/4

OP497

5

7

4

–5V

V

2

3

OUT

R

1/4

OP497

= V

F

1

( )

REF

R + ⌬R

⌬R

V

OUT

R

F

R

Figure 9. A Simple Bridge Conditioning Amplifier Using
the OP497

OP497

NONLINEAR CIRCUITS

Due to its low input bias currents, the OP497 is an ideal log
amplifier in nonlinear circuits such as the square and square
root circuits shown in Figures 10 and 11. Using the squaring
circuit of Figure 10 as an example, the analysis begins by writing a
voltage-loop equation across transistors Q1, Q2, Q3, and Q4.





VIn

T

1






I

IN

+



I



S

1



VIn

T

2




I

IN

I

S



=




2

VInI

T

3



I

O




+



I



S

3



VIn

T

4




I

REF

I

S






4

All the transistors of the MAT04 are precisely matched and at
the same temperature, so the I

2InI InI InI In I I

=+ = ×

IN O REF O REF

and VT terms cancel, giving:

S

()

Exponentiating both sides of thick equation leads to:

2

I

()

I

IN

=

O

I

REF

Op amp A2 forms a current-to-voltage converter which gives
V

= R2 × IO. Substituting (VIN/R1) for IIN and the above

OUT

equation for I

, yields:

O

V

OUT





R2

=





I





REF

2





V

IN





R1





Figure 10. Squaring Amplifier

A similar analysis made for the square-root circuit of Figure 11
leads to its transfer function:

VI

()( )

IN REF

R1

In these circuits, I

VR2

=

OUT

is a function of the negative power sup-

REF

ply. To maintain accuracy, the negative supply should be well
regulated. For applications where very high accuracy is required,
a voltage reference may be used to set I

. An important con-

REF

sideration for the squaring circuit is that a sufficiently large
input voltage can force the output beyond the operating range
of the output op amp. Resistor R4 can be changed to scale I

REF

,
or Rl and R2 can be varied to keep the output voltage within
the usable range.

REV. D

Unadjusted accuracy of the square-root circuit is better than

0.1% over an input voltage range of 100 mV to 10 V. For a
similar input voltage range, the accuracy of the squaring circuit
is better than 0.5%.

–9–

Figure 11. Square-Root Amplifier

OP497

OP497 SPICE MACRO-MODEL

Figure 12 and Table I show the node and net list for a SPICE
macro-model of the OP497. The model is a simplified version of
the actual device and simulates important dc parameters such as

, IOS, IB, AVO, CMR, VO, and ISY. AC parameters such as slew

V

OS

rate, gain and phase response, and CMR change with frequency
are also simulated by the model.

–IN

+IN

2

1

R

IN2

C

IN

R

IN1

15 16

ECM

ⴞ

I

OS

CCM

RCM1

RCM2

8

7

ENZ

R1

D1 D2

R2

– +

E

OS

CNZ

RNZ1

17 18

ⴞ

RNZ2

9

G2

The model uses typical parameters for the OP497. The poles and
zeros in the model were determined from the actual open and
closed-loop gain and phase response of the OP497. In this way,
the model presents an accurate ac representation of the actual
device. The model assumes an ambient temperature of 25°C.

99

ⴞ

V1

R3 R4

C2

56

Q1 Q2

10 11

R6R5

I

1

50

19

R10

C5

G1

98

ⴞ

E

REF

G2

13

D3

12

C3

R7

D4

14

ⴞ

V2

20

C5

R15

98

99

25 26

G4 G5

D8D7

D5

23

24

D6

D10

50

V3

– +

V4

G6

R18

– +

22

G7

R19

L1

V

O

27

R16

I

SY

20

21

R17

D9

Figure 12. OP497 Macro Model

–10–

REV. D

Table I. OP497 SPICE Net-List

OP497

* Node assignments
* noninverting input
* inverting input
* positive supply
* negative supply
* output
*
*SUBCKT OP497 1 2 99 50 27
*
* INPUT STAGE AND POLE AT 6 MHz
*

RIN1 1 7 2500
RIN2 2 8 2500
R1 8 3 6.782E8
R2 7 3 6.782E8
R3 5 99 542.57
R4 6 99 542.57
CIN 7 8 3E-12
C2 5 6 24.445E-12
I1 4 50 0.1E-3
IOS 7 8 15E-12
EOS 9 7 POLY(1) 16 21 40E-6 1
Q15810QX
Q26911QX
R5 10 4 25.374
R6 11 4 25.374
D189DX
D298DX

*

EREF 98 0 21 0 1

*
*GAIN STAGE AND DOMINANT POLE AT 0.11 Hz
*

R7 1 98 2.1703E9
C3 2 98 666.67E-12
G1 98 12 5
V1 99 13 1.275
V2 11 9 1.275
D3 12 13 DX
D4 14 12 DX

*
*COMMON-MODE GAIN NETWORK WITH ZERO AT 50 MHz
*

RCM1 15 16 1E6
CCM 15 16 3.18E-9
RCM2 16 98 1
ECM 15 98 3 21 177.83E-3

* NEGATIVE ZERO AT 1.8 MHz
*

E1 17 98 12 21 1E6
R8 17 18 1E6
C4 17 18 –88.419E-15
R9 18 98 1

*
* POLE AT 6 MHz
*

G2 98 19 18 21 1E-6
R15 20 98 1E6
C8 20 98 26.526E-15

*
* POLE AT 1.8 MHz
*

G6 98 20 19 21 1E-6
R20 20 98 1E6
C10 20 98 88.419E-15

*
* OUTPUT STAGE
*

R16 99 21 160 k
R17 21 50 160 k
ISY 99 50 331E-6
V3 23 22 1.9
D5 20 23 DX
V4 22 24 1.9
D6 24 20 DX
D7 99 25 DX
G4 25 50 20 22 5E-3
D9 50 25 DY
D8 99 26 DX
G5 26 50 22 20 5E-3
D10 50 26 DY
G6 22 99 99 20 5E-3
R18 99 22 200
G7 50 22 20 50 5E-3
R19 22 50 200
L1 22 27 0.1E-6

*
* MODELS USED
*

.MODEL QX NPN (BF = 1.25E6)
.MODEL DX (IS = 1E-15)
.MODEL DZ D(IS = 1E-15 BV = 50)
.ENDS OP497

REV. D

–11–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.005 (0.13)

14

PIN 1

0.060 (1.52)

0.015 (0.38)

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.015 (0.381)
MIN

0.210 (5.33)
MAX

0.160 (4.06)

0.115 (2.92) 0.022 (0.558)

1

0.023 (0.58)

0.014 (0.36)

14

PIN 1

1

0.014 (0.36)

14-Lead Ceramic DIP

(Y-Suffix)

8

7

0.070 (1.78)

0.030 (0.76)

0.098 (2.49)
MAX

0.150
(3.81)

MIN

SEATING PLANE

MIN

0.785 (19.94) MAX

0.100
(2.54)

BSC

14-Lead Epoxy DIP

(P-Suffix)

8

0.280 (7.11)

0.240 (6.10)

7

0.795 (20.19)

0.725 (18.41)

0.130

(3.30)

MIN

0.100

0.070 (1.77)

(2.54)

0.045 (1.15)

BSC

0°–15°

0°–15°

0.310 (7.87)

0.220 (5.59)

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

0.325 (8.25)

0.300 (7.62)

0.015 (0.38)

0.008 (0.20)

16 9

PIN 1

0.0118 (0.30)

0.0040 (0.10)

16-Lead Wide-Body SOIC

(S-Suffix)

0.4133 (10.50)

0.3977 (10.00)

0.2992 (7.60)

0.2914 (7.40)

81

0.050 (1.27)
BSC

0.1043 (2.65)

0.0926 (2.35)

0.0192 (0.49)

0.0138 (0.35)

SEATING
PLANE

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

8ⴗ
0ⴗ

C00309–0–2/02(D)

ⴛ 45ⴗ

0.0500 (1.27)

0.0157 (0.40)

Revision History

Location Page

11/01—Data Sheet changed from REV. C to REV. D.

Edits to PIN CONNECTIONS headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

–12–

PRINTED IN U.S.A.