ANALOG DEVICES OP 275 GPZ Datasheet

Dual Bipolar/JFET, Audio

Operational Amplifier

OP275*

FEATURES
Excellent Sonic Characteristics
Low Noise: 6 nV/÷Hz
Low Distortion: 0.0006%
High Slew Rate: 22 V/␮s
Wide Bandwidth: 9 MHz
Low Supply Current: 5 mA
Low Offset Voltage: 1 mV
Low Offset Current: 2 nA
Unity Gain Stable
SOIC-8 Package

APPLICATIONS
High Performance Audio
Active Filters
Fast Amplifiers
Integrators

GENERAL DESCRIPTION

The OP275 is the first amplifier to feature the Butler Amplifier
front-end. This new front-end design combines both bipolar
and JFET transistors to attain amplifiers with the accuracy and
low noise performance of bipolar transistors, and the speed and
sound quality of JFETs. Total Harmonic Distortion plus Noise
equals that of previous audio amplifiers, but at much lower
supply currents.

A very low l/f corner of below 6 Hz maintains a flat noise density
response. Whether noise is measured at either 30 Hz or 1 kHz,
it is only 6 nV/÷Hz. The JFET portion of the input stage gives
the OP275 its high slew rates to keep distortion low, even when
large output swings are required, and the 22 V/ms slew rate of the
OP275 is the fastest of any standard audio amplifier. Best of all,
this low noise and high speed are accomplished using less than
5 mA of supply current, lower than any standard audio amplifier.

PIN CONNECTIONS

8-Lead Narrow-Body SOIC

(S Suffix)

OUT A

–IN A

+IN A

1

2

OP275

3

4

V–

8

7

6

5

V+

OUT B

–IN B

+IN B

8-Lead Epoxy DIP

(P Suffix)

OP275

1

2

–IN A

3

+IN A

4

V–

8

7

6

5

V+OUT A

OUT B

–IN B

+IN B

Improved dc performance is also provided with bias and offset
currents greatly reduced over purely bipolar designs. Input
offset voltage is guaranteed at 1 mV and is typically less than
200 mV. This allows the OP275 to be used in many dc coupled
or summing applications without the need for special selections
or the added noise of additional offset adjustment circuitry.

The output is capable of driving 600 W loads to 10 V rms while
maintaining low distortion. THD + Noise at 3 V rms is a low

0.0006%.
The OP275 is specified over the extended industrial (–40∞C to

+85∞C) temperature range. OP275s are available in both plastic
DIP and SOIC-8 packages. SOIC-8 packages are available in
2500 piece reels. Many audio amplifiers are not offered in SOIC-8
surface mount packages for a variety of reasons; however, the
OP275 was designed so that it would offer full performance in
surface-mount packaging.

*

Protected by U.S. Patent No. 5,101,126.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

OP275

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = ⴞ15.0 V, TA = 25ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

AUDIO PERFORMANCE

THD + Noise V

Voltage Noise Density e

n

= 3 V rms,

IN

R

= 2 kW, f = 1 kHz 0.006 %

L

f = 30 Hz 7 nV/÷Hz
f = 1 kHz 6 nV/÷Hz

Current Noise Density i

n

f = 1 kHz 1.5 pA/÷Hz

Headroom THD + Noise £ 0.01%,

= 2 kW, VS = ±18 V >12.9 dBu

R

L

INPUT CHARACTERISTICS

Offset Voltage V

Input Bias Current I

Input Offset Current I

Input Voltage Range V

OS

B

OS

CM

Common-Mode Rejection Ratio CMRR V

Large Signal Voltage Gain A

Offset Voltage Drift ⌬V

VO

/⌬T2mV/∞C

OS

–40∞C £ T

£ +85∞C 1.25 mV

A

VCM = 0 V 100 350 nA

= 0 V, –40∞C £ TA £ +85∞C 100 400 nA

V

CM

VCM = 0 V 2 50 nA
V

= 0 V, –40∞C £ TA £ +85∞C2100 nA

CM

–10.5 +10.5 V

= ±10.5 V,

CM

–40∞C £ T

£ +85∞C80106 dB

A

RL = 2 kW 250 V/mV

= 2 kW, –40∞C £ TA £ +85∞C 175 V/mV

R

L

R

= 600 W 200 V/mV

L

1mV

OUTPUT CHARACTERISTICS

Output Voltage Swing V

O

RL = 2 kW –13.5 ±13.9 +13.5 V
R

= 2 kW, –40∞C £ TA £ +85∞C –13 ±13.9 +13 V

L

= 600 W, VS = ±18 V +14, –16 V

R

L

POWER SUPPLY

Power Supply Rejection Ratio PSRR V

Supply Current I

Supply Voltage Range V

SY

S

= ±4.5 V to ±18 V 85 111 dB

S

V

= ±4.5 V to ±18 V,

S

–40∞C £ T

£ +85∞C80 dB

A

VS = ±4.5 V to ±18 V, VO = 0 V,
R

= •, –40∞C £ TA £ +85∞C 45mA

L

= ±22 V, VO = 0 V, RL = •,

V

S

–40∞C £ T

£ +85∞C 5.5 mA

A

±4.5 ±22 V

DYNAMIC PERFORMANCE

Slew Rate SR R
Full-Power Bandwidth BW

P

= 2 kW 15 22 V/ms

L

kHz
Gain Bandwidth Product GBP 9 MHz
Phase Margin Ø

m

Overshoot Factor V

= 100 mV, AV = +1,

IN

62 Degrees

RL = 600 W, CL = 100 pF 10 %

Specifications subject to change without notice.

REV. B–2–

OP275

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V

Input Voltage
Differential Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V

2

. . . . . . . . . . . . . . . . . . . . . . . ± 7.5 V

Output Short-Circuit Duration to GND
Storage Temperature Range

1

3

. . . . . . . . . Indefinite

ORDERING GUIDE

Model Temperature Range Package Option

OP275GP –40∞C to +85∞C 8-Lead Plastic DIP
OP275GS –40∞C to +85∞C 8-Lead SOIC
OP275GSR –40∞C to +85∞C SOIC-8 Reel, 2500 pcs.

P, S Package . . . . . . . . . . . . . . . . . . . . . . . .–65∞C to +150∞C

Operating Temperature Range

OP275G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C

Junction Temperature Range

P, S Package . . . . . . . . . . . . . . . . . . . . . . . .–65∞C to +150∞C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C

Package Type ␪

4

JA

␪

JC

Unit

8-Lead Plastic DIP (P) 103 43 ∞C/W
8-Lead SOIC (S) 158 43 ∞C/W

NOTES

1

Absolute maximum ratings apply to packaged parts, unless otherwise noted.

2

For supply voltages greater than ± 22 V, the absolute maximum input voltage is
equal to the supply voltage.

3

Shorts to either supply may destroy the device. See data sheet for full details.

4

␪JA is specified for the worst-case conditions, i.e., ␪JA is specified for device in

socket for cerdip, P-DIP, and LCC packages; ␪JA is specified for device sol­dered in circuit board for SOIC package.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
OP275 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. B

–3–

OP275–Typical Performance Characteristics

25

TA = 25ⴗC

20

R

= 2k⍀

L

15

10

5

0

–5

–10

–15

OUTPUT VOLTAGE SWING – V

–20

–25

0 ⴞ5 ⴞ25

ⴞ10 ⴞ15 ⴞ20

SUPPLY VOLTAGE – V

+VOM

–VOM

TPC 1. Output Voltage Swing
vs. Supply Voltage

MARKER 15 309.059Hz
MAG (A/H) 60.115dB

60

50

40

30

20

MARKER 15 309.058Hz
PHASE (A/R) 90.606Deg

10

GAIN – dB

0

–10

–20

10k 100k

VS = ⴞ15V

T

= 25ⴗC

A

1M 10M

FREQUENCY – Hz

TPC 4. Open-Loop Gain,
Phase vs. Frequency

135

90

45

0

–45

PHASE – Degrees

–90

1500

VS = ⴞ15V

= ⴞ15V

V

O

1250

1000

750

+GAIN

= 600

⍀

R

L

500

OPEN-LOOP GAIN – V/mV

250

0

–50 –25 100

0255075

TEMPERATURE – ⴗC

–GAIN

= 600

R

L

+GAIN
R

L

–GAIN

= 2k

R

L

⍀

= 2k

⍀

⍀

TPC 2. Open-Loop Gain vs.
Temperature

50

40

A

= +100

VCL

30

20

A

= +10

VCL

10

0

A

= +1

VCL

–10

CLOSED-LOOP GAIN – dB

–20

–30

1k 10k 100M

100k 1M 10M

FREQUENCY – Hz

VS = ⴞ15V

= 25ⴗC

T

A

TPC 5. Closed-Loop Gain vs.
Frequency

40

30

20

10

0

–10

GAIN – dB

–20

–30

–40

10k 100k

FREQUENCY – Hz

VS = ⴞ15V

= 25ⴗC

T

A

1M 10M

TPC 3. Closed-Loop Gain
and Phase, A

60

VS = ⴞ15V

50

= 25ⴗC

T

A

40

⍀

30

20

IMPEDANCE –

10

0
100 1k 10M

= +1

V

A

A

= +10

VCL

A

= +100

VCL

10k 100k 1M

FREQUENCY – Hz

VCL

TPC 6. Closed-Loop Output
Impedance vs. Frequency

= +1

180

135

90

45

0

–45

PHASE – Degrees

–90

–135

–180

120

100

80

60

40

20

COMMON-MODE REJECTION – dB

0

100 1k 10M

10k 100k 1M

FREQUENCY – Hz

VS = ⴞ15V
T

= 25ⴗC

A

TPC 7. Common-Mode
Rejection vs. Frequency

120

100

80

VS = ⴞ15V
T

=

25ⴗC

A

60

40

20

POWER SUPPLY REJECTION – dB

0

10 100 1M

1k 10k 100k

FREQUENCY – Hz

+PSRR

–PSRR

TPC 8. Power Supply Rejection
vs. Frequency

100

80

60

40

20

0

–20

OPEN-LOOP GAIN – dB

–40

–60

GAIN

PHASE

1k 10k 100M

VS = ⴞ15V

= 2k

R

L

TA = 25ⴗC

100k 1M 10M

FREQUENCY – Hz

⍀

Øm= 58

TPC 9. Open-Loop Gain,
Phase vs. Frequency

0

45

90

ⴗ

135

180

225

270

PHASE – Degrees

REV. B–4–

OP275

k

k

11

10

9

8

GAIN BANDWIDTH PRODUCT – MHz

7

–50 –25 100

Ø

m

GBW

0255075

TEMPERATURE – ⴗC

65

60

55

50

40

TPC 10. Gain Bandwidth Product,
Phase Margin vs. Temperature

30

25

20

15

TA = 25ⴗC

= ⴞ15V

V

10

5

MAXIMUM OUTPUT SWING – V

0

S

= +1

A

VCL

= 2k

⍀

R

L

1k 10k 10M

100k 1M

FREQUENCY – Hz

TPC 13. Maximum Output
Swing vs. Frequency

100

90

80

70

60

50

40

OVERSHOOT – %

30

PHASE MARGIN – Degrees

20

10

0

0 100 500

TPC 11. Small-Signal Overshoot
vs. Load Capacitance

5.0

4.5

TA = +85ⴗC

TA = +25ⴗC

4.0

TA = –40ⴗC

3.5

SUPPLY CURRENT – mA

3.0
0 ⴞ5 ⴞ25

TPC 14. Supply Current vs.
Supply Voltage

A

= +1

VCL

NEGATIVE EDGE

A

= +1

VCL

POSITIVE EDGE

VS = ⴞ15V

= 2k⍀

R

L

V

= 100mV p-p

IN

200 300 400

LOAD CAPACITANCE – pF

ⴞ10 ⴞ15

SUPPLY VOLTAGE – V

ⴞ20

16

14

ⱍ–VOMⱍ

12

10

8

6

4

MAXIMUM OUTPUT SWING – V

2

0

100 1k 10

+VOM

T

V

LOAD RESISTANCE – ⍀

= 25ⴗC

A

= ⴞ15V

S

TPC 12. Maximum Output
Voltage vs. Load Resistance

120

110

100

90

80

70

60

50

40

30

ABSOLUTE OUTPUT CURRENT – mA

20

SINK

SOURCE

–50 –25 100

0255075

TEMPERATURE – ⴗC

VS = ⴞ15V

TPC 15. Short Circuit Current
vs. Temperature

300

250

200

150

100

INPUT BIAS CURRENT – nA

50

0

–50 –25 100

TEMPERATURE – ⴗC

VS = ±15V

0255075

TPC 16. Input Bias Current
vs. Temperature

5

Hz

4

3

2

1

CURRENT NOISE DENSITY – pA/

10 100 100

FREQUENCY – Hz

V
T = 25ⴗC

1k

= ⴞ15V

S

A

TPC 17. Current Noise Density
vs. Frequency

500

400

BASED ON 920 OP AMPS

300

UNITS

200

100

0

01 10

23 4 5 67 8 9

VS = ⴞ15V

ⴗ

–40

TCVOS – ␮ V/ⴗC

C to +85ⴗC

TPC 18. TCVOS Distribution

REV. B

–5–

OP275

200

BASED ON 920 OP AMPS

160

120

UNITS

80

40

0

–300–200

–400

–500

INPUT OFFSET VOLTAGE – ␮V

–100

0 100 200

VS = ⴞ15V
T

= 25ⴗC

A

400

300

500

TPC 19. Input Offset (VOS)
Distribution

40

VS = ⴞ15V

35

R

= 2k

⍀

L

30

= 25ⴗC

T

s

A

␮

25

20

15

SLEW RATE – V/

10

5

0

0 1.0

DIFFERENTIAL INPUT VOLTAGE – V

0.80.60.40.2

TPC 22. Slew Rate vs. Differential
Input Voltage

10

8

6

4

2

0

–2

STEP SIZE – V

–4

–6

–8

–10

0 100 900

+0.1%

–0.1%

200 300 400 500 600 700 800

SETTLING TIME – ns

+0.01%

–0.01%

TPC 20. Step Size vs. Settling
Time

50

VS = ⴞ15V

45

= 2k

⍀

R

L

s

40

␮

35

30

SLEW RATE – V/

25

20

–50 –25 100

TEMPERATURE – ⴗC

–SR

+SR

0255075

TPC 23. Slew Rate vs. Temperature

50

TA =

25ⴗC

= ⴞ15V

V

45

40

35

30

SLEW RATE – V/ ␮s

25

20

0 100 500

–SR

+SR

200 300 400

CAPACITIVE LOAD – pF

S

TPC 21. Slew Rate vs. Capacitive
Load

100

90

10

0%

5V

200ns

TPC 24. Negative Slew Rate

= 2 kW , VS = ±15 V, AV = +1

R

L

100

90

10

0%

5V

TPC 25. Positive Slew Rate
R

= 2 kW , VS = ±15 V, AV = +1

L

200ns

100

90

10

0%

50mV

100ns

TPC 26. Small Signal Response

= 2 kW , VS = ±5 V, AV = +1

R

L

CH A: 80.0 ␮V FS 10.0 ␮V/DIV

MKR: 6.23 nV/ Hz

2.5 kHz0 Hz

BW: 15.0 MHzMKR: 1 000 Hz

TPC 27. Voltage Noise Density
vs. Frequency V

= ±15 V

S

REV. B–6–

OP275

k

k

APPLICATIONS
Circuit Protection

OP275 has been designed with inherent short circuit protection
to ground. An internal 30 W resistor, in series with the output,
limits the output current at room temperature to I

– = –90 mA, typically, with ±15 V supplies.

and I

SC

+ = 40 mA

SC

However, shorts to either supply may destroy the device when
excessive voltages or currents are applied. If it is possible for a
user to short an output to a supply, for safe operation, the out­put current of the OP275 should be design-limited to ±30 mA,
as shown in Figure 1.

Total Harmonic Distortion

Total Harmonic Distortion + Noise (THD + N) of the OP275
is well below 0.001% with any load down to 600 W. However,
this is dependent upon the peak output swing. In Figure 2, the
THD + Noise with 3 V rms output is below 0.001%. In Figure 3,
THD + Noise is below 0.001% for the 10 kW and 2 kW loads but
increases to above 0.1% for the 600 W load condition. This is a
result of the output swing capability of the OP275. Notice the
results in Figure 4, showing THD versus V

(V rms). This

IN

figure shows that the THD + Noise remains very low until the
output reaches 9.5 V rms. This performance is similar to com­petitive products.

R

FB

0.010

VS = ⴞ18V

= 600⍀

R

L

0.001

THD + NOISE – %

0.0001

0.5 1 10

OUTPUT SWING – V rms

Figure 4. Headroom, THD + Noise vs. Output
Amplitude (V rms); R

= 600 ⍀ , V

LOAD

= ± 18 V

SUP

The output of the OP275 is designed to maintain low harmonic
distortion while driving 600 W loads. However, driving 600 W
loads with very high output swings results in higher distortion if
clipping occurs. A common example of this is in attempting to
drive 10 V rms into any load with ±15 V supplies. Clipping will
occur and distortion will be very high. To attain low harmonic
distortion with large output swings, supply voltages may be
increased. Figure 5 shows the performance of the OP275 driv­ing 600 W loads with supply voltages varying from ±18 V to ± 20 V.
Notice that with ±18 V supplies the distortion is fairly high,
while with ±20 V supplies it is a very low 0.0007%.

0.0001

FEEDBACK

V

OUT

–

A1

+

R

X

332 ⍀

A1 = 1/2 OP275

Figure 1. Recommended Output Short Circuit Protection

0.010

RL = 600⍀, 2k⍀, 10k
VS = ⴞ15V
V

= 3V rms

IN

= +1

A

V

THD + NOISE – %

0.001

0.0005
20 100 1k 10k 20

FREQUENCY – Hz

Figure 2. THD + Noise vs. Frequency vs. R

1

0.1

0.010

THD + NOISE – %

0.001

0.0001
20 100 1k 10k 20

Figure 3. THD + Noise vs. R

600⍀

2k⍀

10k⍀

FREQUENCY – Hz

LOAD

AV = +1

V

= ⴞ18V

S

= 10V rms

V

IN

80kHz FILTER

; VIN =10 V rms,

⍀

LOAD

0.001

RL = 600

⍀

V

= 10V rms @ 1kHz

0.01

THD – %

0.1

0

ⴞ

17

ⴞ

18

ⴞ

SUPPLY VOLTAGE – V

OUT

ⴞ

19

ⴞ

20

ⴞ

21

22

Figure 5. THD + Noise vs. Supply Voltage

Noise

The voltage noise density of the OP275 is below 7 nV/÷Hz from
30 Hz. This enables low noise designs to have good perfor­mance throughout the full audio range. Figure 6 shows a typical
OP275 with a 1/f corner at 2.24 Hz.

CH A: 80.0␮V FS

0Hz

MKR: 2.24Hz

MKR: 45.6

␮

V/ Hz

10.0␮V/DIV

10Hz

BW: 0.145Hz

REV. B

Figure 6. 1/f Noise Corner, VS = ±15 V, AV = 1000

–7–

OP275

Noise Testing

For audio applications, the noise density is usually the most
important noise parameter. For characterization, the OP275 is
tested using an Audio Precision, System One. The input signal
to the Audio Precision must be amplified enough to measure it
accurately. For the OP275, the noise is gained by approximately
1020 using the circuit shown in Figure 7. Any readings on the
Audio Precision must then be divided by the gain. In imple­menting this test fixture, good supply bypassing is essential.

100

⍀

909

⍀

100

A

OP275

B

909

⍀

⍀

100

OP37

909

⍀

OP37

⍀

4.42k

490

⍀

OUTPUT

⍀

Figure 7. Noise Test Fixture

Input Overcurrent Protection

The maximum input differential voltage that can be applied to
the OP275 is determined by a pair of internal Zener diodes
connected across its inputs. They limit the maximum differential
input voltage to ±7.5 V. This is to prevent emitter-base junction
breakdown from occurring in the input stage of the OP275 when
very large differential voltages are applied. However, to preserve
the OP275’s low input noise voltage, internal resistances in series
with the inputs were not used to limit the current in the clamp
diodes. In small signal applications, this is not an issue; however,
in applications where large differential voltages can be inadvert­ently applied to the device, large transient currents can flow
through these diodes. Although these diodes have been designed
to carry a current of ±5 mA, external resistors as shown in Figure 8
should be used in the event that the OP275’s differential voltage
were to exceed ±7.5 V.

1.4k

⍀

2

–

6

1.4k

⍀

OP275

3

+

Figure 8. Input Overcurrent Protection

Output Voltage Phase Reversal

Since the OP275’s input stage combines bipolar transistors for
low noise and p-channel JFETs for high speed performance, the
output voltage of the OP275 may exhibit phase reversal if either
of its inputs exceeds its negative common-mode input voltage.
This might occur in very severe industrial applications where a
sensor, or system, fault might apply very large voltages on the
inputs of the OP275. Even though the input voltage range of the
OP275 is ±10.5 V, an input voltage of approximately –13.5 V
will cause output voltage phase reversal. In inverting amplifier
configurations, the OP275’s internal 7.5 V input clamping diodes
will prevent phase reversal; however, they will not prevent this

effect from occurring in noninverting applications. For these
applications, the fix is a simple one and is illustrated in Figure 9.
A 3.92 kW resistor in series with the noninverting input of the
OP275 cures the problem.

R

*

FB

–

V

V

IN

*

RFB IS OPTIONAL

R

3.92k

+

S

⍀

R

L

2k

OUT

⍀

Figure 9. Output Voltage Phase Reversal Fix

Overload, or Overdrive, Recovery

Overload, or overdrive, recovery time of an operational amplifier
is the time required for the output voltage to recover to a rated
output voltage from a saturated condition. This recovery time is
important in applications where the amplifier must recover quickly
after a large abnormal transient event. The circuit shown in Fig­ure 10 was used to evaluate the OP275’s overload recovery time.

OUT

OUT

=

The OP275 takes approximately 1.2 ms to recover to V

L

OUT

⍀

= –10 V.

V

+10 V and approximately 1.5 ms to recover to V

R2

⍀

10k

2

–

1

A1

3

+

R

2.43k

V

IN

4V p-p

@100Hz

R1

⍀

1k

R

S

909k

⍀

A1 = 1/2 OP275

Figure 10. Overload Recovery Time Test Circuit

Measuring Settling Time

The design of OP275 combines a high slew rate and a wide
gain-bandwidth product to produce a fast-settling (t

< 1 ms)

S

amplifier for 8- and 12-bit applications. The test circuit designed
to measure the settling time of the OP275 is shown in Figure 11.
This test method has advantages over false-sum node techniques
in that the actual output of the amplifier is measured, instead of
an error voltage at the sum node. Common-mode settling effects
are exercised in this circuit in addition to the slew rate and
bandwidth effects measured by the false-sum-node method. Of
course, a reasonably flat-top pulse is required as the stimulus.

The output waveform of the OP275 under test is clamped by
Schottky diodes and buffered by the JFET source follower. The
signal is amplified by a factor of ten by the OP260 and then
Schottky-clamped at the output to prevent overloading the
oscilloscope’s input amplifier. The OP41 is configured as a fast
integrator, which provides overall dc offset nulling.

High Speed Operation

As with most high speed amplifiers, care should be taken with
supply decoupling, lead dress, and component placement. Rec­ommended circuit configurations for inverting and noninverting
applications are shown in Figures 12 and 13.

REV. B–8–

OP275

16V–20V

–+

0.1␮F

0.1␮F

+

16V–20V

ⴞ5V

+

V+

DUT

–

V–

–

R

1k⍀

1N4148

L

D1 D2

Figure 11. OP275’s Settling Time Test Fixture

+15V

10␮F

2

3

–

1/2

OP275

+

+

8

1

4

0.1␮F

R

2k⍀

V

OUT

L

0.1␮F

V

IN

10␮F
+

–15V

15k⍀

+15V

2N4416

2N2222A

1/2 OP260AJ

+

–

R

F

2k⍀

R

G

222⍀

1k⍀

D3

10k⍀

10k⍀

750⍀

SCHOTTKY DIODES D1–D4 ARE
HEWLETT-PACKARD HP5082-2835
IC1 IS 1/2 OP260AJ
IC2 IS PMI OP41EJ

R

S

C

–

+

S

D4

1␮F

IC2

OUTPUT

(TO SCOPE)

C

FB

R

FB

–

C

IN

+

V

OUT

Figure 14. Compensating the Feedback Pole

–15V

Figure 12. Unity Gain Follower

+15V

␮

F

10
+

V

IN

2.49k

⍀

4.99k

0.1␮F

⍀

2

8

–

1/2

OP275

3

+

4

10

␮

F

0.1

–15V

10pF

⍀

4.99k

1

␮

F
+

V

OUT

2k

⍀

Figure 13. Unity Gain Inverter

In inverting and noninverting applications, the feedback resis­tance forms a pole with the source resistance and capacitance

and CS) and the OP275’s input capacitance (CIN), as shown

(R

S

in Figure 14. With R

and RF in the kilohm range, this pole can

S

create excess phase shift and even oscillation. A small capacitor,

, in parallel and RFB eliminates this problem. By setting R

C

FB

S

(CS + CIN) = RFBCFB, the effect of the feedback pole is com­pletely removed.

REV. B

–9–

Attention to Source Impedances Minimizes Distortion

Since the OP275 is a very low distortion amplifier, careful atten­tion should be given to source impedances seen by both inputs.
As with many FET-type amplifiers, the p-channel JFETs in the
OP275’s input stage exhibit a gate-to-source capacitance that
varies with the applied input voltage. In an inverting configura­tion, the inverting input is held at a virtual ground and, as such,
does not vary with input voltage. Thus, since the gate-to-source
voltage is constant, there is no distortion due to input capaci­tance modulation. In noninverting applications, however, the
gate-to-source voltage is not constant. The resulting capacitance
modulation can cause distortion above 1 kHz if the input
impedance is greater than 2 kW and unbalanced.

Figure 15 shows some guidelines for maximizing the distortion
performance of the OP275 in noninverting applications. The
best way to prevent unwanted distortion is to ensure that the
parallel combination of the feedback and gain setting resistors

and RG) is less than 2 kW. Keeping the values of these resis-

(R

F

tors small has the added benefits of reducing the thermal noise

R

G

R

V

IN

S*

–

+

R

F

OP275

*

RS = RG//RF IF RG//RF > 2k

FOR MINIMUM DISTORTION

V

OUT

⍀

Figure 15. Balanced Input Impedance to Minimize
Distortion in Noninverting Amplifier Circuits

OP275

of the circuit and dc offset errors. If the parallel combination of

and RG is larger than 2 kW, then an additional resistor, RS,

R

F

should be used in series with the noninverting input. The value

is determined by the parallel combination of RF and RG to

of R

S

maintain the low distortion performance of the OP275.

Driving Capacitive Loads

The OP275 was designed to drive both resistive loads to 600 W
and capacitive loads of over 1000 pF and maintain stability.
While there is a degradation in bandwidth when driving capacitive
loads, the designer need not worry about device stability. The
graph in Figure 16 shows the 0 dB bandwidth of the OP275
with capacitive loads from 10 pF to 1000 pF.

10

9

8

7

6

5

4

BANDWIDTH – MHz

3

2

1

0

0 200 400 600 800 1000

Figure 16. Bandwidth vs. C

– pF

C

LOAD

LOAD

High Speed, Low Noise Differential Line Driver

The circuit of Figure 17 is a unique line driver widely used in
industrial applications. With ±18 V supplies, the line driver can
deliver a differential signal of 30 V p-p into a 2.5 kW load. The
high slew rate and wide bandwidth of the OP275 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 10 nV/÷Hz.

R3

2k

⍀

2

–

3

+

R1

⍀

2k

+

3

V

IN

A1 = 1/2 OP275

A2, A3 = 1/2 OP275

R3

GAIN =

SET R2, R4, R5 = R1 AND R6, R7, R8 = R3

1

A1

2

–

R2

2k

R1

R4
2k

R5

⍀

2k

⍀

6

–

5

+

A2

⍀

R6

2k

A3

R9

50

1

R11

⍀

10k

1k

R12
1k

P1

⍀

⍀

R7

⍀

2k

⍀

R10

50

⍀

7

R8

⍀

2k

V

O2

V

O1

– VO1 = V

V

O2

IN

Figure 17. High Speed, Low Noise Differential Line Driver

The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount

importance. Like the transformer based design, either output
can be shorted to ground for unbalanced line driver applica­tions without changing the circuit gain of 1. Other circuit gains
can be set according to the equation in the diagram. This
allows the design to be easily set to noninverting, inverting, or
differential operation.

A 3-Pole, 40 kHz Low-Pass Filter

The closely matched and uniform ac characteristics of the
OP275 make it ideal for use in GIC (Generalized Impedance
Converter) and FDNR (Frequency-Dependent Negative Resistor)
filter applications. The circuit in Figure 18 illustrates a linear­phase, 3-pole, 40 kHz low-pass filter using an OP275 as an
inductance simulator (gyrator). The circuit uses one OP275
(A2 and A3) for the FDNR and one OP275 (A1 and A4) as
an input buffer and bias current source for A3. Amplifier A4
is configured in a gain of 2 to set the pass band magnitude
response to 0 dB. The benefits of this filter topology over classi­cal approaches are that the op amp used in the FDNR is not in
the signal path and that the filter’s performance is relatively
insensitive to component variations. Also, the configuration is
such that large signal levels can be handled without overloading
any of the filter’s internal nodes. As shown in Figure 19, the
OP275’s symmetric slew rate and low distortion produce a
clean, well behaved transient response.

R1

95.3k⍀

2

–

A1

3

V

+

IN

–

1

A2

+

C1

2200pF

1

R2

R6

787⍀

4.12k⍀

C2

2200pF

1.82k⍀

2

2200pF

1.87k⍀

1.82k⍀

C3

3

5

6

R3

R4

R5

+

A3

–

2200pF

7

C4

100k⍀

A1, A4 = 1/2 OP275
A2, A3 = 1/2 OP275

5

+

7

A4

6

1k⍀

–

R8

R9

1k⍀

R7

V

OUT

Figure 18. A 3-Pole, 40 kHz Low-Pass Filter

100

90

V

OUT

10V p-p

10kHz

10

0%

SCALE: VERTICAL–2V/ DIV
HORIZONTAL–10␮s/ DIV

Figure 19. Low-Pass Filter Transient Response

REV. B–10–

OP275

OP275 SPICE Model

*
* Node assignments
* noninverting input
* inverting input
* positive supply
* negative supply
* output
**

.SUBCKT OP275 1 2 99 50 34

*
* INPUT STAGE & POLE AT 100 MHz
*

R3 5 51 2.188
R4 6 51 2.188
CIN 1 2 3.7E-12
CM1 1 98 7.5E-12
CM2 2 98 7.5E-12
C2 5 6 364E-12
I1 97 4 100E-3
IOS 1 2 1E-9
EOS 9 3 POLY(1) 26 28 0.5E-3 1
Q1 5 2 7 QX
Q2 6 9 8 QX
R5 7 4 1.672
R6 8 4 1.672
D1 2 36 DZ
D2 1 36 DZ
EN 3 1 10 0 1
GN1 0 2 13 0 1E-3
GN2 0 1 16 0 1E-3

*

EREF 98 0 28 0 1
EP 97 0 99 0 1
EM 51 0 50 0 1

*
* VOLTAGE NOISE SOURCE
*

DN1 35 10 DEN
DN2 10 11 DEN
VN1 35 0 DC 2
VN2 0 11 DC 2

*
* CURRENT NOISE SOURCE
*

DN3 12 13 DIN
DN4 13 14 DIN
VN3 12 0 DC 2
VN4 0 14 DC 2

*
* CURRENT NOISE SOURCE
*

DN5 15 16 DIN
DN6 16 17 DIN
VN5 15 0 DC 2
VN6 0 17 DC 2

*
* GAIN STAGE & DOMINANT POLE AT 32 Hz
*

R7 18 98 1.09E6
C3 18 98 4.55E-9
G1 98 18 5 6 4.57E-1
V2 97 19 1.35
V3 20 51 1.35
D3 18 19 DX
D4 20 18 DX

*

* POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz
*

R8 21 98 1E-3
R9 21 22 1.25E-3
C4 22 98 47.2E-12
G2 98 21 18 28 1E-3

*
* POLE AT 100 MHz
*

R10 23 98 1
C5 23 98 1.59E-9
G3 98 23 21 28 1

*
* POLE AT 100 MHz
*

R11 24 98 1
C6 24 98 1.59E-9
G4 98 24 23 28 1

*
* COMMON-MODE GAIN NETWORK WITH ZERO AT

1 kHz

*

R12 25 26 1E6
C7 25 26 1.5915E-12
R13 26 98 1
E2 25 98 POLY(2) 1 98 2 98 0 2.50 2.50

*
* POLE AT 100 MHz
*

R14 27 98 1
C8 27 98 1.59E-9
G5 98 27 24 28 1

*
* OUTPUT STAGE
*

R15 28 99 100E3
R16 28 50 100E3
C9 28 50 1E-6
ISY 99 50 1.85E-3
R17 29 99 100
R18 29 50 100
L2 29 34 1E-9
G6 32 50 27 29 10E-3
G7 33 50 29 27 10E-3
G8 29 99 99 27 10E-3
G9 50 29 27 50 10E-3
V4 30 29 1.3
V5 29 31 3.8
F1 29 0 V4 1
F2 0 29 V5 1
D5 27 30 DX
D6 31 27 DX
D7 99 32 DX
D8 99 33 DX
D9 50 32 DY
D10 50 33 DY

*
* MODELS USED
*

.MODEL QX PNP(BF=5E5)
.MODEL DX D(IS=1E-12)
.MODEL DY D(IS=1E-15 BV=50)
.MODEL DZ D(IS=1E-15 BV=7.0)
.MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1)
.MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1)
.ENDS

REV. B

–11–

OP275

OUTLINE DIMENSIONS

8-Lead Standard Small Outline Package [SOIC]

(S suffix)

(R-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

C03364–0–1/03(B)

1.27 (0.0500)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

BSC

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.33 (0.0130)

0.25 (0.0098)

0.19 (0.0075)

0.50 (0.0196)

0.25 (0.0099)

8ⴗ
0ⴗ

1.27 (0.0500)

0.41 (0.0160)

8-Lead Plastic Dual-in-Line Package [PDIP]

(P suffix)

(N-8)

Dimensions shown in inches and (millimeters)

0.375 (9.53)

0.365 (9.27)

0.355 (9.02)

8

1

0.100 (2.54)

0.180

(4.57)

MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095AA

BSC

5

4

0.295 (7.49)

0.285 (7.24)

0.275 (6.98)

0.015
(0.38)
MIN

SEATING
PLANE

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

ⴛ 45ⴗ

Revision History

Location Page

1/03—Data Sheet changed from REV. A to REV. B.

Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

–12–

REV. B

PRINTED IN U.S.A.

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