ANALOG DEVICES OP 200 GPZ Datasheet

Operational Amplifier

OP200

Rev. F Document Feedback

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–IN

A

1

+IN

A

2

NC

3

V–

4

OUT A

16

NC

15

NC

14

V+

13

NC

5

NC

12

+IN B

6

NC

1

1

–IN B

7

OUT B

10

NC

8

NC

9

NC = NO CONNECT

00322-001

OUT A

1

–IN A

2

+IN A

3

V–

4

V+

8

OUT B

7

–IN B

6

+IN B

5

OP200

00322-002

A

B

Data Sheet

FEATURES

Low input offset voltage: 75 µV maximum
Low offset voltage drift, over −55°C < T

0.5 µV/°C maximum
Low supply current (per amplifier): 725 µA maximum
High open-loop gain: 5000 V/mV minimum
Low input bias current: 2 nA maximum
Low noise voltage density: 11 nV/√Hz at 1 kHz
Stable with large capacitive loads: 10 nF typical

< +125°C

A

Dual Low Offset, Low Power

PIN CONNECTIONS

Figure 1. 16-Lead SOIC (S-Suffix)

GENERAL DESCRIPTION

The OP200 is the first monolithic dual operational amplifier
to offer OP77 type precision performance. Available in the
industry standard 8-lead pinout, the OP200 combines precision
performance with the space and cost savings offered by a dual
amplifier.

The OP200 features an extremely low input offset voltage of
less than 75 µV with a drift below 0.5 µV/°C, guaranteed over
the full military temperature range. Open-loop gain of the OP200
exceeds 5,000,000 into a 10 kΩ load; input bias current is under
2 nA; CMRR is over 120 dB; and PSRR is below 1.8 µV/V. On-chip
Zener zap trimming is used to achieve the extremely low input
offset voltage of the OP200 and eliminates the need for offset
pulling.

Figure 2. 8-Lead PDIP (P-Suffix)

8-Lead CERDIP (Z-Suffix)

Power consumption of the OP200 is low, with each amplifier
drawing less than 725 µA of supply current. The total current
drawn by the dual OP200 is less than one-half that of a single

OP07, yet the OP200 offers significant improvements over this

industry-standard op amp. The voltage noise density of the OP200,
11 nV/√Hz at 1 kHz, is half that of most competitive devices.

The OP200 is an ideal choice for applications requiring multiple
precision op amps and where low power consumption is critical.

For a quad precision op amp, see the OP400.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©1978–2015 Analog Devices, Inc. All rights reserved.

OP200* Product Page Quick Links

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Documentation

Application Notes

• AN-649: Using the Analog Devices Active Filter Design
Tool

Data Sheet

• OP200: Dual Low Offset, Low Power Operational
Amplifier Data Sheet

• OP200: Military Data Sheet

Tools and Simulations

• OP200 SPICE Macro-Model

Reference Materials

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Capacitive Loads

Last Content Update: 08/30/2016

Design Resources

• OP200 Material Declaration

• PCN-PDN Information

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OP200 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Pin Connections ............................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 4

Electrical Characteristics ............................................................. 4

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

10/15—Rev. E to Rev. F

Changes to General Description .................................................... 1

Changes to Ordering Guide .......................................................... 16

9/12—Rev. D to Rev. E

Changed Table 2 Conditions from V

Updated Outline Dimensions ....................................................... 15

Changes to Ordering Guide .......................................................... 16

2/09—Rev. C to Rev. D

Change to Large Signal Voltage Gain, Table 2 .............................. 4

Changes to Ordering Guide .......................................................... 16

8/08—Rev. B to Rev. C

Updated Format .................................................................. Universal

Changes to Features Section............................................................ 1

Changes to Table 1 and Table 2 ....................................................... 4

Changes to Table 3 and Table 4 ....................................................... 5

Deleted Table 7; Renumbered Sequentially................................... 5

Changes to Figure 15 ........................................................................ 9

Changes to Figure 21 ...................................................................... 10

Changes to Figure 30 and Figure 31 ............................................. 12

Changes to Programmable High Resolution Window

Comparator Section, Figure 33, and Figure 34 ........................... 13

Changes to Figure 35 ...................................................................... 14

Updated Outline Dimensions ....................................................... 15

Changes to Ordering Guide .......................................................... 16

= 15 V to VS = ±15 V ...... 4

S

Applications Information .............................................................. 12

Dual Low Power Instrumentation Amplifier ......................... 12

Precision Absolute Value Amplifier ......................................... 12

Precision Current Pump ............................................................ 12

Dual 12-Bit Voltage Output DAC ............................................ 13

Dual Precision Voltage Reference ............................................ 13

Programmable High Resolution Window Comparator ........ 14

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 16

2/04—Rev. A to Rev. B.

OP200F Deleted .................................................................. Universal

Changes to Ordering Guide ............................................................. 5

Changes to Figure 4 ........................................................................... 8

Updated Outline Dimension ........................................................ 11

4/02—Rev. 0 to Rev. A.

Edits to Features................................................................................. 1

Edits to General Description ........................................................... 1

Edits to Ordering Information ........................................................ 1

Edits to Pin Connections .................................................................. 1

Edits to Absolute Maximum Ratings .............................................. 2

Edits to Package Type ....................................................................... 2

Rev. F | Page 2 of 16

Data Sheet OP200

00322-003

+IN

VOLTAGE

LIMITING

NETWORK

–IN

BIAS

OUT

V–

V+

Figure 3. Simplified Schematic (One of Two Amplifiers Shown)

Rev. F | Page 3 of 16

OP200 Data Sheet

Input Noise Current Density

in

fO = 10 Hz

0.4

0.4

pA/√Hz

RL = 2 kΩ

2000

3700

1500

3200

M/mV

INPUT CHARACTERISTICS

Large Signal Voltage Gain

AVO

VO = 10 V

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VS = ±15 V, TA = 25°C, unless otherwise noted.

Table 1.

OP200A/OP200E OP200G

Parameter Symbol Conditions

INPUT CHARACTERISTICS

Input Offset Voltage VOS 25 75 80 200 μV
Long-Term Input Voltage Stability 0.1 0.1 μV/mo
Input Offset Current IOS VCM = 0 V 0.05 1.0 0.05 3.5 nA
Input Bias Current IB VCM = 0 V 0.1 2.0 0.1 5.0 nA
Input Noise Voltage en p-p 0.1 Hz to 10 Hz 0.5 0.5 μV p-p
Input Noise Voltage Density1 en fO = 10 Hz 22 36 22 nV/√Hz

fO = 1000 Hz 11 18 11 nV/√Hz

Input Noise Current in p-p 0.1 Hz to 10 Hz 15 15 pA p-p

Input Resistance Differential Mode RIN 10 10 MΩ
Input Resistance Common Mode R
Large Signal Voltage Gain AVO VO = ±10 V

125 125 GΩ

INCM

RL = 10 kΩ 5000 12,000 3000 7000 M/mV

Unit Min Typ Max Min Typ Max

1

Sample tested.

VS = ±15 V, −55°C ≤ TA ≤ +125°C for OP200A, unless otherwise noted.

Table 2.

OP200A

Parameter Symbol Conditions

Input Offset Voltage VOS 45 125 μV
Average Input Offset Voltage Drift TCVOS 0.2 0.5 μV/°C
Input Offset Current IOS VCM = 0 V 0.15 2.5 nA
Input Bias Current IB VCM = 0 V 0.9 5.0 nA

RL = 10 kΩ 3000 9000 V/mV

RL = 2 kΩ 1000 2700 V/mV
Input Voltage Range1 IVR ±12 ±12.5 V
Common-Mode Rejection Ratio CMRR VCM = ±12 V 115 130 dB
Capacitive Load Stability AV = 1 8 nF

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = 3 V to 18 V 0.2 3.2 μV/V
Supply Current Per Amplifier ISY No load 600 775 μA

OUTPUT CHARACTERISTICS

Output Voltage Swing VO RL = 10 kΩ ±12 ±12.4 V

RL = 2 kΩ ±11 ±12 V

1

Guaranteed by CMRR test.

Unit Min Typ Max

Rev. F | Page 4 of 16

Data Sheet OP200

Input Voltage Range1

IVR ±12

±13 ±12

±13 V

Input Offset Current

IOS

VCM = 0 V

0.08

2.5 0.1

6.0

nA

Input Voltage Range1

IVR ±12

±12.5

±12

±12.5

V

OUTPUT CHARACTERISTICS

VS = ±15 V, TA = 25°C, unless otherwise noted.

Table 3.

OP200A/OP200E OP200G

Parameter Symbol Conditions

INPUT CHARACTERISTICS

Common-Mode Rejection Ratio CMRR VCM = ±12 V 120 135 110 130 dB
Channel Separation2 CS VO = 20 V p-p, fO = 10 Hz 123 145 123 145 dB
Input Capacitance CIN 3.2 3.2 pF
Capacitive Load Stability AV = 1, no oscillations 10 10 nF

POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 0.4 1.8 0.6 5.6 μV/V
Supply Current Per Amplifier ISY No load 570 725 570 725 μA

OUTPUT CHARACTERISTICS

Output Voltage Swing VO RL= 10 kΩ ±12 ±12.6 ±12 ±12.6 V
RL = 2 kΩ ±11 ±12.2 ±11 ±12.2 V
DYNAMIC PERFORMANCE

Slew Rate SR 0.1 0.15 0.1 0.15 V/μs

Gain Bandwidth Product GBP AV = 1 500 500 kHz

1

Guaranteed by CMRR test.

2

Guaranteed but not 100% tested.

V

= ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.

S

Unit Min Typ Max Min Typ Max

Table 4.

OP200E OP200G

Parameter Symbol Conditions

INPUT CHARACTERISTICS

Input Offset Voltage VOS 35 100 110 300 μV

Average Input Offset Voltage Drift TCVOS 0.2 0.5 0.6 2.0 μV/°C

Input Bias Current IB VCM = 0 V 0 3 5.0 0.5 10.0 nA

Large-Signal Voltage Gain AVO VO = ±10 V

RL= 10 kΩ 3000 10,000 2000 5000 V/mV

RL = 2 kΩ 1500 3200 1000 2500 V/mV

Common-Mode Rejection Ratio CMRR VCM = ±12 V 115 130 105 130 dB

Capacitive Load Stability AV = 1, no oscillations 10 10 nF
POWER SUPPLY

Power Supply Rejection Ratio PSRR VS = ±3 V to ±18 V 0.15 3.2 0.3 10.0 μV/V

Supply Current Per Amplifier ISY No load 600 775 600 775 μA

Output Voltage Swing VO RL = 10 kΩ ±12 ±12.4 ±12 ±12.4 V

RL = 2 kΩ ±11 ±12 ±11 ±12.2 V

1

Guaranteed by CMRR test.

Unit Min Typ Max Min Typ Max

Rev. F | Page 5 of 16

OP200 Data Sheet

1/2

OP200

50Ω

50Ω

1/2

OP200

CHANNEL SEPARATIO N = 20 log

V

1

V2/1000

V1 20V p-p @ 10Hz

V

2

00322-004

Figure 4. Channel Separation Test Circuit

100Ω 10kΩ

1/2

OP200

1/2

OP200

e

(nV/√Hz) = √2 × e

OUT

(nV/√Hz) × 101

OUT

Figure 5. Noise Test Schematic

e

OUT

TO SPECTRUM
ANALYZER

00322-005

Rev. F | Page 6 of 16

Data Sheet OP200

Operating Temperature Range

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Supply Voltage ±20 V
Differential Input Voltage ±30 V
Input Voltage Supply voltage
Output Short-Circuit Duration Continuous
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Junction Temperature Range (TJ) −65°C to +150°C

THERMAL RESISTANCE

Table 6.

Package Type θ

8-Lead CERDIP (Z Suffix) 148 16 °C/W
8-Lead Plastic DIP (P Suffix) 96 37 °C/W
16-Lead SOIC (S Suffix) 92 27 °C/W

1

θJA is specified for worst-case mounting conditions, that is, θJA is specified for

device in socket for CERDIP and PDIP packages; θ
soldered to printed circuit board for SOIC package.

1

θJC Unit

JA

is specified for device

JA

OP200A −55°C to +125°C

OP200E, OP200G −40°C to +85°C

Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

ESD CAUTION

Rev. F | Page 7 of 16

OP200 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

300

TA = 25°C
V

= ±15V

S

2

1

CHANGE IN OFF SET VOL TAGE (µ V)

INPUT OFF SET CURRENT ( pA)

VS = ±15V

250

200

150

100

50

0

0 1.0 2.0 3.0 4.0 5.0

TIME (Minutes)

Figure 6. Warm-Up Drift

60

VS = ±15V

50

40

30

20

INPUT OFFSET VOLTAGE ( µV)

10

0

–75 –50 –25 0 25 50 75 100 125

TEMPERATURE ( °C)

Figure 7. Input Offset Voltage vs. Temperature

3

VS = ±15V

2

1

0

–1

INPUT BIAS CURRENT (nA)

–2

00322-006

0

–75 –50 –25 0 25 50 75 100 125

TEMPERATURE (° C)

00322-009

Figure 9. Input Offset Current vs. Temperature

1.0

TA = 25°C
V

= ±15V

S

0.8

0.6

0.4

INPUT BIAS CURRENT (nA)

0.2

00322-007

0

–15 –10 –5 .0 0 5.0 10 15

COMON-MODE VOLTAG E (V)

00322-010

Figure 10. Input Bias Current vs. Common-Mode Voltage

140

120

100

80

60

40

COMMON-MO DE REJECTIO N (dB)

20

TA = 25°C

= ±15V

V

S

–3

–75 –50 –25 0 25 50 75 100 125

TEMPERATURE (°C)

Figure 8. Input Bias Current vs. Temperature

00322-008

Rev. F | Page 8 of 16

0

1 10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 11. Common-Mode Rejection vs. Frequency

00322-011

Data Sheet OP200

100

VOLTAGE NOISE DENSITY (nV/√Hz)

TA = 25°C
V

= ±15V

S

1.18
TWO AMPLIFIERS
T

= 25°C

A

1.16

1.14

1.12

1.10

TOTAL S UPPLY CURRENT (mA)

1.08

10

1 10 100 1k

FREQUENCY (Hz)

Figure 12. Voltage Noise Density vs. Frequency

1000

CURRENT NOISE DE NSITY (fA/ √Hz)

100

1 10 100 1k

FREQUENCY (Hz)

Figure 13. Current Noise Density vs. Frequency

TA = 25°C
V

= ±15V

S

00322-012

1.06

±2 ±6 ±10 ±14 ±18

SUPPLY VOLTAGE (V)

00322-015

Figure 15. Total Supply Current vs. Supply Voltage

1.16
TWO AMPLIFIERS
V

= ±15V

S

1.15

1.14

1.13

1.12

TOTAL S UPPLY CURRENT (mA)

00322-013

1.11

–75 –50 –25 0 25 50 75 100 125

TEMPERATURE ( °C)

00322-016

Figure 16. Total Supply Current vs. Temperature

140

120

NEGATIVE SUPPLY

NOISE VOLTAGE (400nV/DIV)

02 4 6810

TIME (SEC)

Figure 14. 0.1 Hz to 10 Hz Noise

00322-014

Rev. F | Page 9 of 16

100

80

60

40

POWER SUPPLY REJECTION (nA)

20

TA = 25°C

0

0.1 1 10 100 1k 10k 100k

POSITIVE SUPPLY

FREQUENCY (Hz)

Figure 17. Power Supply Rejection vs. Frequency

00322-017

OP200 Data Sheet

0.7

0.1

0.2

0.3

0.4

0.5

0.6

–75 –50

00322-018

POWER SUPPLY REJECTION (µV/V)

TEMPERATURE (°C)

–25

0

25 50

75

100

125

6000

0

1000

2000

3000

4000

5000

–75 –50

00322-019

OPEN-LOOP GAIN (V/mV)

TEMPERATURE (°C)

–25 0 25 50 75

100

125

VS = ±15V
R

L

= 2kΩ

140

–20

0

20

60

40

80

100

120

10 100 1k 10k 100k 1M

00322-020

OPEN-LOOP GAIN (dB)

FREQUENCY (Hz )

GAIN

PHASE

T

A

= 25°C

VS = ±15V

PHASE SHIFT (Degrees)

180

135

90

0

140

0

20

60

40

80

100

120

1 10 100 1k 10k 100k 1M

00322-021

CLOSED-LOOP GAIN (dB)

FREQUENCY (Hz )

AV = 1000

A

V

= 100

A

V

= 10

AV = 1

TA = 25°C
V

S

= ±15V

30

0

5

10

15

20

25

10 100 1k 10k 100k

00322-022

OUTPUT SWING (V)

FREQUENCY (Hz )

T

A

= 25°C

V

S

= ±15V

V p-p AT 1%
DISTORTION

1

0.001

0.01

0.1

100 1k 10k

00322-023

TOTAL HARMONIC DISTORTION (%)

FREQUENCY (Hz )

TA = 25°C
VS = ±15V
V

OUT

= 10V p-p

RL = 2kΩ

AV = 1

AV = 10

AV = 100

Figure 18. Power Supply Rejection vs. Temperature

Figure 19. Open-Loop Gain vs. Temperature

Figure 21. Closed-Loop Gain vs. Frequency

Figure 22. Maximum Output Swing vs. Frequency

Figure 20. Open-Loop Gain and Phase Shift vs. Frequency

Figure 23. Total Harmonic Distortion vs. Frequency

Rev. F | Page 10 of 16

Data Sheet OP200

50

0

5

10

15

20

25

30

35

40

45

0 0.5

00322-024

OVERSHOOT (%)

CAPACITIVE LOAD (nF)

1.0 1.5 2.0 2.5 3.0

TA = 25°C
VS = ±15V

FALLING

RISING

29

22

23

24

25

26

27

28

0 1

00322-025

SHORT-CI RCUI T CURRENT (mA)

TIME (Minutes)

2

3 4 5

T

A

= 25°C

V

S

= ±15V

SINKING

SOURCING

150

90

100

110

120

130

140

10 100 1k

10k 100k

00322-026

CHANNEL SEPARATION (dB)

FREQUENCY (Hz )

00322-027

T

A

= 25°C

V

S

= ±15V

AV = +1

100µ

s 5.00V

00322-028

T

A

= 25°C

V

S

= ±15V

A

V

= +1

5µs 20mV

00322-029

T

A

= 25°C
VS = ±15V
AV = +1

5µs 20mV

Figure 24. Overshoot vs. Capacitive Load

Figure 25. Short-Circuit Current vs. Time

Figure 27. Large Signal Transient Response

Figure 28. Small Signal Transient Response

Figure 26. Channel Separation vs. Frequency

Figure 29. Small Signal Transient Response, C

LOAD

= 1 nF

Rev. F | Page 11 of 16

OP200 Data Sheet

Gain

Bandwidth

10

67 kHz

00322-030

20kΩ

1

7

8

4

2

3

6

5

1/2

OP200AZ

1/2

OP200AZ

V

OUT

V

IN

V

OUT

= 5 +

VIN + V

REF

40,000

R

G

–

+

5kΩ

5kΩ

R

G

–15V

+15V

V

REF

20kΩ

00322-031

R3

1kΩ

R2

2kΩ

1/2

OP200AZ

1/2

OP200AZ

V

OUT

0V < V

OUT

< 10V

R1

1kΩ

C1

30pF

D1
1N4148

D1

1N4148

7

1

8

4

6

5

2

3

V

IN

–15V

+15V

C2

0.1pF

C2

0.1pF

00322-032

R5

100Ω

1

2

3

7

8

4

6

5

1/2

OP200EZ

1/2

OP200EZ

I

OUT

V

IN

I

OUT

= = 10mA/V=

V

IN

RS

V

IN

100Ω

–15V

+15V

–

R1

10kΩ

+

R1

10kΩ

R3

10kΩ

R4

1kΩ

APPLICATIONS INFORMATION

The OP200 is inherently stable at all gains and is capable of
driving large capacitive loads without oscillating. Nonetheless,
good supply decoupling is highly recommended. Proper supply
decoupling reduces problems caused by supply line noise and
improves the capacitive load driving capability of the OP200.

DUAL LOW POWER INSTRUMENTATION AMPLIFIER

A dual instrumentation amplifier that consumes less than 33 mW
of power per channel is shown in Figure 30. The linearity of the
instrumentation amplifier exceeds 16 bits in gains of 5 to 200 and is
better than 14 bits in gains from 200 to 1000. CMRR is above
115 dB (gain = 1000). Offset voltage drift is typically 0.2 μV/°C
over the military temperature range, which is comparable to the
best monolithic instrumentation amplifiers. The bandwidth of
the low power instrumentation amplifier is a function of gain
and is shown in Table 7.

Table 7. Gain Bandwidth

PRECISION ABSOLUTE VALUE AMPLIFIER

The circuit in Figure 31 is a precision absolute value amplifier
with an input impedance of 10 MΩ. The high gain and low TCV
of the OP200 ensure accurate operation with microvolt input
signals. In this circuit, the input always appears as a common­mode signal to the op amps. The CMRR of the OP200 exceeds
120 dB, yielding an error of less than 2 ppm.

OS

5 150 kHz

100 7.5 kHz
1000 500 Hz

Figure 30. Dual Low Power Instrumentation Amplifier

The output signal is specified with respect to the reference
input, which is normally connected to analog ground. The
reference input can be used to offset the output from −10 V
to +10 V if required.

Figure 31. Precision Absolute Value Amplifier

PRECISION CURRENT PUMP

The maximum output current of the precision current pump
shown in Figure 32 is ±10 mA. Voltage compliance is ±10 V
with ±15 V supplies. Output impedance of the current transmit­ter exceeds 3 MΩ with linearity better than 16 bits.

Figure 32. Precision Current Pump

Rev. F | Page 12 of 16

Data Sheet OP200

V

V

DUAL 12-BIT VOLTAGE OUTPUT DAC

The dual output DAC shown in Figure 33 is capable of providing
untrimmed 12-bit accurate operation over the entire military
temperature range. Offset voltage, bias current, and gain errors
of the OP200 contribute less than 1/10 of an LSB error at 12 bits
over the military temperature range.

5

21

V

DD

DAC8221

R

DUAL PRECISION VOLTAGE REFERENCE

A dual OP200 and a REF43, a 2.5 V reference, can be used to
build a ±2.5 V precision voltage reference. Maximum output
current from each reference is ±10 mA with load regulation
under 25 μV/mA. Line regulation is better than 15 μV/V and
output voltage drift is under 20 μV/°C. Output voltage noise
from 0.1 Hz to 10 Hz is typically 75 μV p-p. R1 and D1 ensure
correct startup.

FB A

3

8

10V

REFERENCE

VOLTAGE

CONTROL

DAC DATA BUS

PIN 6 (MSB)

DAC

+5

V

IN

REF43

GND

V

REF A

4

TO PIN 17 ( LSB)

V

22

REF B

18

DAC A/DAC B

19

CS

20

WR

R1
22kΩ

2

6

V

OUT

5

TRIM

4

DAC A

1/2

DAC8221

DAC B

1/2

DAC8221

DGND

5

I

OUT A

R

FB B

I

OUT B

AGND

2

23

24

1

Figure 33. Dual 12-Bit Voltage Output DAC

D1

1N914

+5V

8

2

OP200AZ

3

1/2

4

–5V

R3

10kΩ

1

5kΩ

6

OP200AZ

5

R4

R3

10kΩ

1/2

2

3

6

5

OP200AZ

OP200AZ

7

1/2

1/2

+2.5V

1

4

7

OUT A

V–

OUT B

00322-033

–2.5V

0322-034

Figure 34. Dual Precision Voltage Reference

Rev. F | Page 13 of 16

OP200 Data Sheet

V

PROGRAMMABLE HIGH RESOLUTION WINDOW COMPARATOR

The programmable window comparator shown in Figure 35 is
easily capable of 12-bit accuracy over the full military temperature

V

IN

21

V

DD

range. A dual CMOS 12-bit DAC, the DAC8221, is used in the
voltage switching mode to set the upper and lower thresholds
(DAC A and DAC B, respectively).

15

8

10V

REFERENCE

VOLTAGE

CONTRO L

SIGNALS

I

OUT A

2

DAC DATA BUS

PIN 6 (MSB) TO PIN 17 (LSB)

I

24

OUT B

18

DAC

DAC A/DAC B

19

CS

20

WR

DGND

DAC A

1/2

DAC8221

DAC B

1/2

DAC8221

5

AGND

V

4

REF A

V

22

REF B

1

R1

10kΩ

15V–

R2

10kΩ

3

2

4

5

6

1/2

OP200AZ

1/2

OP200AZ

Figure 35. Programmable High Resolution Window Comparator

1

D1
1N4148

R2

10kΩ

D1
1N4148

7

R4
10kΩ

5V

Q1
2N2222

TTL OUT

00322-035

Rev. F | Page 14 of 16

Data Sheet OP200

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

0.310 (7.87)

0.220 (5.59)

0.005 (0.13)
MIN

0.055 (1.40)
MAX

0.100 (2.54) BSC

15°

0°

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

SEATING
PLANE

0.200 (5.08)
MAX

0.405 (10.29) MAX

0.150 (3.81)
MIN

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

1

4

5

8

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES)ARE ROUNDED-O FF INCH EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS M AY BE CONFIG URE D AS WHOLE OR HAL F LEADS.

070606-A

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

SEATING
PLANE

0.015
(0.38)
MIN

0.210 (5.33)
MAX

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

8

1

4

5

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.100 (2.54)
BSC

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

0.060 (1.52)
MAX

0.430 (10.92)
MAX

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)
GAUGE

PLANE

0.005 (0.13)
MIN

OUTLINE DIMENSIONS

Figure 36. 8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)

Z-Suffix

Dimensions shown in inches and (millimeters)

Figure 37. 8-Lead Plastic Dual In-Line Package [PDIP]

(N-8)

P-Suffix

Dimensions shown in inches and (millimeters)

Rev. F | Page 15 of 16

OP200 Data Sheet

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

10.50 (0.4134)

10.10 (0.3976)

0.30 (0.0118)

0.10 (0.0039)

2.65 (0.1043)

2.35 (0.0925)

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

0.75 (0.0295)

0.25 (0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.33 (0.0130)

0.20 (0.0079)

0.51 (0.0201)

0.31 (0.0122)

SEATING
PLANE

8°
0°

16

9

8

1

1.27 (0.0500)
BSC

03-27-2007-B

©1978–2015 Analog Devices, Inc. All rights reserved. Trademarks and

Figure 38. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

S-Suffix

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model1 TA = 25°C VOS Max (µV) Temperature Range Package Description Package Option

OP200AZ 75 −55°C to +125°C 8-Lead CERDIP Z-Suffix (Q-8)
OP200EZ 75 −40°C to +85°C 8-Lead CERDIP Z-Suffix (Q-8)
OP200GPZ 200 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
OP200GSZ 200 −40°C to +85°C 16-Lead SOIC_W S-Suffix (RW-16)
OP200GSZ-REEL 200 −40°C to +85°C 16-Lead SOIC_W S-Suffix (RW-16)

1

The OP200GPZ, OP200GSZ, and OP200GSZ-REEL are RoHS Compliant Parts.

registered trademarks are the property of their respective owners.
D00322-0-10/15(F)

Rev. F | Page 16 of 16